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smsc sch311x datasheet revision 0.4 (06-03-05) datasheet product features sch3112, sch3114, sch3116 lpc io with 8042 kbc, reset generation, hwm and multiple serial ports general features ? 3.3 volt operation (sio block is 5 volt tolerant) ? low pin count bus (lpc) interface ? programmable wake-up event (pme) interface ? pc99, pc2001 compliant ? acpi 2.0 compliant ? serial irq interface compatible with serialized irq support for pci systems ? isa plug-and-play compatible register set ? four address options for power on configuration port ? system management interrupt (smi) ? 40 general purpose i/o pins ? 6 gpio with vid compatible inputs ? support for power button on ps/2 keyboard ? security key register (32 byte) for device authentication watchdog timer resume and main power good generator programmable clock output to 16 hz. 2.88mb super i/o floppy disk controller ? licensed cmos 765b floppy diskcontroller ? supports two floppy drives ? configurable open drain/push-pull ? supports vertical recording format ? 16-byte data fifo ? 100% ibm? compatibility ? detects all overrun and underrun conditions ? sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption ? dma enable logic ? data rate and drive control registers ? 480 address, up to eight irq and four dma options ? support fdd interface on parallel port pins enhanced digital data separator ? 2 mbps, 1 mbps, 500 kbps, 300 kbps, 250 kbp data rates ? programmable precompensation modes keyboard controller ? 8042 software compatible ? 8 bit microcomputer ? 2k bytes of program rom ? 256 bytes of data ram ? four open drain outputs dedicated for keyboard/mouse interface ? asynchronous access to two data registers and one status register ? supports interrupt and polling access ? 8 bit counter timer ? port 92 support ? fast gate a20 and kreset outputs ? phoenix keyboard bios rom multiple serial ports ? sch3112 - 2 full function serial ports ? sch3114 - 4 full function serial ports ? sch3116 - 4 full function and 2 four-pin serial ports ? high speed ns16c550a compatible uarts with ? send/receive 16-byte fifos ? supports 230k, 460k, 921k and 1.5m baud ? programmable baud rate generator ? modem control circuitry ? 480 address and 15 irq options ? support irq sharing among serial ports ? rs485 auto direction control mode infrared port ? multiprotocol infrared interface ? irda 1.0 compliant ? sharp ask ir ? 480 addresses, up to 15 irq multi-mode? parallel port with chiprotect? ? standard mode ibm pc/xt ?, pc/at ? , and ps/2? compatible bi-directional parallel port ? enhanced parallel port (epp) compatible - epp 1.7 and epp 1.9 (ieee 1284 compliant) ? eee 1284 compliant enhanced capabilities port (ecp) ? chiprotect circuitry for protection ? 960 address, up to 15 irq and four dma options hardware monitor ? monitor power supplies (+2.5v, +5v, +12v, vccp (processor voltage), vcc, vbat and vtr. ? remote thermal diode sensing for two external temperature measurements accurate to 1.5 o c ? internal ambient temperature measurement ? limit comparison of all monitored values ? programmable automatic fan control based on temperature ? nhwm_int pin for out-of-limit temperature or voltage indication ? thermtrip signal for over temperature indication ide reset output and 3 pci reset buffers with software control capability (sch3112 and sch3114 only) power button control and ac power failure recovery (sch3112 and sch3114 only) industrial (+85 c to -40 c) temperature range available 128 pin vtqfp package; green, lead-free package also available
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 2 revision 0.4 (06-03-05) datasheet order number(s): sch3112i-ne for 128 pin, vtqfp package (industrial temperature range) sch3114i-ne for 128 pin, vtqfp package (industrial temperature range) sch3116i-ne for 128 pin, vtqfp package (industrial temperature range) SCH3112I-NU for 128 pin, vtqfp package (green, lead-free - industrial temperature range) sch3114i-nu for 128 pin, vtqfp package (green, lead-free - industrial temperature range) sch3116i-nu for 128 pin, vtqfp package (green, lead-free - industrial temperature range) sch3112-ne for 128 pin, vtqfp package (commercial temperature range) sch3114-ne for 128 pin, vtqfp package (commercial temperature range) sch3116-ne for 128 pin, vtqfp package (commercial temperature range) sch3112-nu for 128 pin, vtqfp package (gre en, lead-free - commercial temperature range) sch3114-nu for 128 pin, vtqfp package (gre en, lead-free - commercial temperature range) sch3116-nu for 128 pin, vtqfp package (gre en, lead-free - commercial temperature range) 80 arkay drive hauppauge, ny 11788 (631) 435-6000 fax (631) 273-3123 copyright ? 2005 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc products are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked a nd is believed to be accurate, no responsibility is assumed for inaccuracies. smsc rese rves the right to make changes to specifications and product descriptions at any time without notice. contact your local smsc sales office to ob tain the latest specifications before placing your product order . the provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or oth er intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the terms and conditions of the mos t recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifica tions. anomaly sheets are available upon request. smsc products are not designed , intended, authorized or warranted for use in any life suppor t or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prio r written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copie s of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http://www.smsc.co m. smsc is a registered trademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any course of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, punitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or not smsc has been advised of the possibility of such damages.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 3 revision 0.4 (06-03-05) datasheet 0.1 reference documents 1. intel low pin count specification, revision 1.0 , september 29, 1997 2. pci local bus specification, revision 2.2 , december 18, 1998 3. advanced configuration and power inte rface specification, revision 1.0b , february 2, 1999 4. ieee 1284 extended capa bilities port protocol and isa standard, rev. 1.14, july 14, 1993. 5. hardware description of the 8042, intel 8 bit embedded controller handbook. 6. smsc application note (an 8-8) ?keyboard and mouse wakeup functionality?, dated 03/23/02. 0.2 datasheet revision history table 0.1 sch311x datasheet revision history name revision level and date section/figure/ entry correction r. mahler rev. 0.4 (06-03-05) features removed: ?configurable offset for internal or external temperature channels? r. mahler rev. 0.4 (06-03-05) ordering information added commercial temperature range plus lead-free industrial temperature range chapter 30, package outline new package outline b. filippi rev. 0.4 (06-03-05) section 28.1.1, "super i/o section (pins 3 to 112)" and section 28.1.2, "hardware monitoring block (pins 1 and 2 and pins 113 to 128)" max vcc voltage changed from ?5.5? to ?5.0? table 28.1, "buffer operational ratings" max vcc voltage changed from ?5.5? to ?5.0? maximum currents on vcc and vtr updated m. atchison rev. 0.4 (06-03-05) section 20.4, "resume reset signal generation" changed ?pme_ste1? to ?v trip ? m. atchison rev. 0.4 (06-03-05) section 20.4, "resume reset signal generation" cross-reference modified
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 4 smsc sch311x datasheet s. sipek rev. 0.4 (06-03-05) section 24.2.19, "registers 67-69h: zone low temperature limit" changed reset value from 23h to 80h section 24.2.17, "register 62h, 63h: pwm ramp rate control" bits {7:5] of 62h marked as reserved set to 1 section 24.2.21, "registers 6d-6eh: smsc test registers" register marked as smsc test registers section 24.2.21, "registers 6d-6eh: smsc test registers" registers 1dh, 1eh, and 1fh removed section 2.3, "buffer description" corrected buffer types and pin numbering table 8.4, "baud rates" and figure 8.2, "baud rate selection" updated table and figure to clarify high speed operation increased hwm version number, increased chip version number updated wdt section to correct operation notes table 0.1 sch311x datasheet revision history (continued) name revision level and date section/figure/ entry correction
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 5 revision 0.4 (06-03-05) datasheet table of contents 0.1 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0.2 datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.1 sch311x pinout summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.3 buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 chapter 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 chapter 4 power functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 vcc power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.2 hvtr power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.3 3 volt operation / 5 volt tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4 vtr support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.1 trickle power functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5 vbat support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 32.768 khz trickle clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.7 super i/o functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.8 power management events (pme/sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 chapter 5 sio overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 5.1 super i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.2 host processor interface (lpc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 6 lpc interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1 lpc interface signal definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.1 lpc required signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.1.2 lpc optional signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2 supported lpc cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 device specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.1 sync protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.2 reset policy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 chapter 7 floppy disk controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 fdc internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.1 status register a (sra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1.2 ps/2 model 30 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.1.3 status register encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 7.1.4 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.1.5 data transfer commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 chapter 8 serial port (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.1 infrared interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.1.1 ir transmit pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.2 interrupt sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.3 rs485 auto direction control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.4 reduced pin serial ports (sch3116 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 chapter 9 parallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 6 smsc sch311x datasheet 9.1 ibm xt/at compatible, bi-directional and epp modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.2 extended capabilities pa rallel port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.3 parallel port floppy disk controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.3.1 buffer types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.3.2 fdc/pp control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 chapter 10 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 chapter 11 serial irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 chapter 12 8042 keyboard controller description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.1 keyboard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 12.2 external keyboard and mouse interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.2.1 keyboard/mouse swap bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.3 keyboard power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 12.4 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.5 memory configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.6 register definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 12.7 external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.8 default reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 12.9 keyboard and mouse pme generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 54 chapter 13 general purpose i/o (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.1 gpio pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 13.3 gpio control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4 gpio operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.5 gpio pme and smi functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.6 either edge triggered interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.7 led functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 chapter 14 system management interrupt (smi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 chapter 15 pme support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1 15.1 pme events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 15.2 enabling smi events onto the pme pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.3 pme function pin control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.4 wake on specific key code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 15.5 wake on specific mouse click . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 chapter 16 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 chapter 17 programmable clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 chapter 18 reset generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 18.1 watchdog timer for resets on vcc_por. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 18.2 pwrgd_out timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 18.3 power supply voltage scaling and tolera nces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 chapter 19 buffered pci outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1 buffered pci outputs interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.1 ide reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 19.1.2 npcirstx output logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 7 revision 0.4 (06-03-05) datasheet chapter 20 power control features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 20.1 nio_pme pin use in power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 20.2 front panel reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 20.3 a/c power failure recovery cont rol (sch3112 and sch3114 devices only) . . . . . . . . . . . . . . 190 20.3.1 pb_out# and ps_on# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 20.3.2 power supply timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 20.4 resume reset signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 20.5 keyboard power button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 20.5.1 keyboard data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 20.5.2 system for decoding scan code make bytes received from the keyboa rd . . . . . . . . 195 20.5.3 system for decoding scan code break bytes received from the keyboard . . . . . . . . 196 20.6 wake on specific mouse event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 chapter 21 low battery detection logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 21.1 vbat por . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 21.2 low battery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 21.2.1 under battery power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 21.2.2 under vtr power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 21.2.3 under vcc power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 chapter 22 battery backed security key register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 chapter 23 temperature monitoring and fan control. . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 23.2 hwm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 23.3 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 23.4 resetting the sch311x hardware monito r block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 23.4.1 vtr power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 23.4.2 vcc power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.4.3 soft reset (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.5 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.6 input monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 23.7 monitoring modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 23.7.1 continuous monitoring mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 23.7.2 cycle monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 09 23.8 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 23.8.1 interrupt enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 23.8.2 diode fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 23.9 interrupt si gnal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 23.9.1 interrupt pin (nhwm_int) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 23.9.2 interrupt as a pme event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 23.9.3 interrupt as an sm i event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 23.9.4 interrupt event on serial irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.10 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.11 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.11.1 internal temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.11.2 external temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 23.11.3 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 23.12 thermal zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 23.13 fan control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 23.13.1 limit and configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 23.13.2 device set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 23.13.3 pwm fan speed control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 23.13.4 operation of pwm pin following a power cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 8 smsc sch311x datasheet 23.13.5 active minimum temperature adjustment (amta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 23.14 nthermtrip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 23.14.1 nthermtrip operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 23.14.2 fan speed monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 23.14.3 locked rotor support for tachomet er inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 23.14.4 linking fan tachometers to pwms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 23.15 high frequency pwm options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 23.15.1 pwm frequencies supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 chapter 24 hardware monitoring register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 24.1 undefined registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 24.2 defined registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 24.2.1 register 10h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 24.2.2 registers 20-24h, 99-9ah: voltage reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 24.2.3 registers 25-27h: temperature reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 24.2.4 registers 28-2dh: fan tachometer reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 24.2.5 registers 30-32h: current pwm duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 24.2.6 register 3dh: device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 52 24.2.7 register 3eh: company id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 24.2.8 register 3fh: revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 24.2.9 register 40h: ready/lock/start monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 24.2.10 register 41h: interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 24.2.11 register 42h: interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 24.2.12 registers 44-4dh, 9b-9eh: voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 24.2.13 registers 4e-53h: temperature limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 24.2.14 registers 54-59h: fan tachometer low limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 24.2.15 registers 5c-5eh: pwm configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 24.2.16 registers 5f-61h: zone temperature range, pw m frequency . . . . . . . . . . . . . . . . . . 261 24.2.17 register 62h, 63h: pwm ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 24.2.18 registers 64-66h: minimum pwm duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 24.2.19 registers 67-69h: zone low temperature limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 24.2.20 registers 6a-6ch: absolute temperature limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 24.2.21 registers 6d-6eh: smsc test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 24.2.22 register 70-72h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 24.2.23 register 73-78h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 24.2.24 register 79h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 24.2.25 register 7ch: special function register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 24.2.26 register 7eh: interrupt enable 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 24.2.27 register 7fh: configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 24.2.28 register 80h: interrupt enable 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 24.2.29 register 81h: tach_pwm association register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 24.2.30 register 82h: interrupt enable 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 24.2.31 register 83h: interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 24.2.32 registers 84h-88h: a/d converter lsbs registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 24.2.33 registers registers 89h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.2.34 registers 8ah: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.2.35 registers 8bh: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.2.36 registers 8ch: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.2.37 registers 8dh: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 24.2.38 registers 8eh: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 24.2.39 registers 90h-92h: fantachx option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 24.2.40 registers 94h-96h: pwmx option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 24.2.41 register 97h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 24.2.42 register 98h:smsc test register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 24.2.43 registers 99h-9ah:voltage reading registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 9 revision 0.4 (06-03-05) datasheet 24.2.44 registers 9b-9eh: voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 24.2.45 register a3h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 24.2.46 register a4h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 24.2.47 register a5h: interrupt status register 1 - seconda ry . . . . . . . . . . . . . . . . . . . . . . . . . 277 24.2.48 register a6h: interrupt status register 2 - seconda ry . . . . . . . . . . . . . . . . . . . . . . . . . 278 24.2.49 register a7h: interrupt status register 3 - seconda ry . . . . . . . . . . . . . . . . . . . . . . . . . 278 24.2.50 register abh: tach 1-3 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 24.2.51 register adh: smsc test register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 24.2.52 registers ae-afh, b3h: top temperature limit re gisters . . . . . . . . . . . . . . . . . . . . . . 279 24.2.53 register b4h: min temp adjust temp rd1, rd2 (zones 1& 3) . . . . . . . . . . . . . . . . . . 279 24.2.54 register b5h: min temp adjust temp and dela y amb (zone 2) . . . . . . . . . . . . . . . . . 280 24.2.55 register b6h: min temp adjust delay rd1, rd2 (zone 1 & 3) register . . . . . . . . . . 280 24.2.56 register b7h: min temp adjust enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 24.2.57 register b8h: top temp exceeded status register . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 24.2.58 register bah: smsc reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 24.2.59 register bbh: smsc reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 24.2.60 register 0bdh: smsc reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 24.2.61 register bfh: smsc reserved regi ster. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 24.2.62 register c0h: smsc reserved register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 24.2.63 register c1h: smsc reserved register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 24.2.64 registers c4-c5, c9h: thermtrip temperatur e limit zone registers . . . . . . . . . . . 283 24.2.65 register cah: thermtrip status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 24.2.66 register cbh: thermtrip output enable register . . . . . . . . . . . . . . . . . . . . . . . . . . 284 24.2.67 register ceh: smsc reserved register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 24.2.68 registers d1,d6,dbh: pwm max segment registers . . . . . . . . . . . . . . . . . . . . . . . . . 284 24.2.69 register e0h: enable lsbs for auto fan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 24.2.70 registers e1h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 24.2.71 registers e2h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 24.2.72 registers e3h: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 24.2.73 register e9-eeh: smsc te st registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 24.2.74 register ffh: smsc test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 chapter 25 config registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 25.1 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 25.1.1 global config registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 25.1.2 test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 chapter 26 runtime register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 26.1 runtime register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 26.2 runtime register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 chapter 27 valid power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 chapter 28 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 28.1 maximum guaranteed ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 28.1.1 super i/o section (pins 3 to 112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 28.1.2 hardware monitoring block (pins 1 and 2 and pins 113 to 128) . . . . . . . . . . . . . . . . . . 357 28.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 28.3 capacitance values for pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 chapter 29 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 29.1 power up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 29.2 input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 29.3 lpc interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 29.4 floppy disk controller timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 10 smsc sch311x datasheet 29.5 parallel port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 29.6 ir timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 29.7 serial irq timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 29.8 uart interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 29.9 keyboard/mouse interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 29.10 resume reset signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 29.11 nledx timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 29.12 pwm outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 chapter 30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 appendix a adc voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 appendix b example fan circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 appendix c test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 c.1 xnor-chain test mode overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 c.1.1 board test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 11 revision 0.4 (06-03-05) datasheet list of figures figure 2.1 sch3112 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 2.2 sch3114 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 2.3 sch116 pin diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 2.4 sch3116 summary - 6 ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 3.1 sch311x block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 8.1 serial data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 8.2 baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 8.3 block diagram of the ir components in the sch311 x . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 8.4 half duplex operation with direction control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 figure 8.5 reduce pin serial port control signal selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 12.1 sch311x keyboard and mouse interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 12.2 gpi/o polarity configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 12.3 keyboard latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 12.4 mouse latch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 13.1 gpio function illustration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 figure 15.1 8042 isolation and keyboard and mouse port swap representation . . . . . . . . . . . . . . . . . 175 figure 18.1 reset generation circuit (for illustrative pu rposes only) . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 18.2 pwrgd_out timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 figure 19.1 npcirstx logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 figure 20.1 power control block di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 figure 20.2 nfprst debounce timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 figure 20.3 power supply during normal operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 92 figure 20.4 power supply after power failure (return to off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 figure 20.5 power supply after power failure (return to on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 figure 20.6 sample single-byte make code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 20.7 sample multi-byte make code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 figure 20.8 option 1: kb_pb_sts wake event fixed pulse width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 figure 20.9 option 2: assert kb_pb_ sts wake event until scan code not programmed make code. . . 197 figure 20.10option 3: de-assert kb_pb_sts when scan code equal break code . . . . . . . . . . . . . . 198 figure 21.1 external battery circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 figure 23.1 hwm block embedded in sch311x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 figure 23.2 hwm register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 23.3 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 23.4 automatic fan control flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 figure 23.5 automatic fan control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 figure 23.6 spin up reduction enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 figure 23.7 illustration of pwm ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 figure 23.8 case 1 spinup operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 figure 23.9 case 2 spinup operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 figure 23.10case 3 spinup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 figure 23.11case 4 spinup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 figure 23.12case 5 spinup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 figure 23.13amta illustration, adjusting minimum temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 figure 23.14amta interrupt mappin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 figure 23.15nthermtrip output operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 figure 23.16pwm and tachometer concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 figure 24.1 fan activity above fan temp limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 figure 29.1 power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 figure 29.2 input clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 figure 29.3 pci clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 figure 29.4 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 figure 29.5 output timing measurement cond itions, lpc signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 12 smsc sch311x datasheet figure 29.6 input timing measurement conditions, lpc signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 figure 29.7 i/o write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 figure 29.8 i/o read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 figure 29.9 dma request assertion through ldrq#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 figure 29.10dma write (first byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 figure 29.11dma read (first byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 figure 29.12floppy disk drive timing (at mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 0 figure 29.13epp 1.9 data or addres s write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 figure 29.14epp 1.9 data or addres s read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 figure 29.15epp 1.7 data or addres s write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 figure 29.16epp 1.7 data or addres s read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 figure 29.17parallel port fifo timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 figure 29.18ecp parallel port forward timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 figure 29.19ecp parallel port reverse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 figure 29.20irda receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 figure 29.21irda transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 figure 29.22amplitude shift-keyed ir receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 0 figure 29.23amplitude shift-keyed ir transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1 figure 29.24setup and hold time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 figure 29.25serial port data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 figure 29.26keyboard/mouse receive/send data timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 figure 29.27resume reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 29.28nledx timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 figure 29.29pwmx output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 figure 30.1 128 pin vtqfp package outlin e; 14x14x1.0 body, 2mm footprint . . . . . . . . . . . . . . . . . . 385 figure b.1 fan drive circuitry for lo w frequency option (apply to pwm driving two fans) . . . . . . . 389 figure b.2 fan drive circuitry for low frequency option (apply to pwm driving one fan) . . . . . . . . 390 figure b.3 fan tachometer circuitry (apply to each fan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 figure b.4 remote diode (apply to remote2 li nes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 figure b.5 suggested minimum track width and spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 figure c.1 xnor-chain test structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 13 revision 0.4 (06-03-05) datasheet list of tables table 0.1 sch311x datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2.1 sch3112 summary - 2 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 2.2 sch3114 summary - 4 serial ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2.3 sch311x signal difference summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 table 2.4 sch311x pin core functions description ( note 2.14 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 2.5 sch3112 specific signals ( note 2.15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 2.6 sch3114 specific signals ( note 2.15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 2.7 sch3116 specific signals ( note 2.15 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 2.8 buffer description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5.1 super i/o block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 6.1 supported lpc cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 7.1 status, data and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 7.2 internal 2 drive decode ? normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 7.3 tape select bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 7.4 drive type id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 7.5 precompensation delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 7.6 data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 7.7 drvden mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 7.8 default precompensation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 7.9 fifo service delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 7.10 status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 7.11 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 7.12 status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 7.13 status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 7.14 description of command symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 7.15 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 7.16 sector sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 7.17 effects of mt and n bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 7.18 skip bit vs. read data command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 7.19 skip bit vs. read deleted data command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 table 7.20 result phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 7.21 verify command result phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 7.22 typical values for formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 7.23 interrupt identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 7.24 drive control delays (ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 7.25 effects of wgate and gap bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 8.1 addressing the serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 8.2 interrupt control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 8.3 serial ports mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 8.4 baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 8.5 register reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 8.6 pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 8.7 register summary for an individual uart channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 8.8 sch311x irq sharing summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 12 table 8.9 nrts/ndtr automatic direction control options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 9.1 parallel port connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 9.2 epp pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 9.3 ecp pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 9.4 ecp register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 9.5 mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 9.6 extended control register (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 9.7 extended control register (b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 table 9.8 extended control register (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 14 smsc sch311x datasheet table 9.9 channel/data commands supported in ecp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 9.10 parallel port floppy pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 table 9.11 pp buffer types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 10.1 state of floppy disk drive interface pins in powerdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 12.1 i/o address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 12.2 host interface flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 12.3 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table 12.4 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 13.1 gpio pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 13.2 sch311x general purpose i/o port assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 13.3 gpio configuration option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 table 13.4 gpio read/write behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 15.1 pme interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 15.2 pme events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 18.1 resgen strap option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 18.2 resgen programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 table 18.3 wdt operation following vcc_por or edt2_ctl writ ing . . . . . . . . . . . . . . . . . . . . . . . . 183 table 18.4 pwrgd_out timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 19.1 buffered pci outputs interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 19.2 nide_rstdrv truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 19.3 nide_rstdrv timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 20.1 power control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 20.2 internal pwrok truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 20.3 definition of apf bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 20.4 decoding keyboard scan code for make code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 20.5 decoding keyboard scan code for break code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 table 22.1 security key register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 22.2 description of security key control (skc) register bits[2:1] . . . . . . . . . . . . . . . . . . . . . . . . 204 table 23.1 avg[2:0] bit decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 23.2 adc conversion sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 table 23.3 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 table 23.4 pwm ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 table 23.5 minimum rpm detectable using 3 edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 23.6 minimum rpm detectable using 2 edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 24.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 24.2 voltage vs. register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 table 24.3 temperature vs. register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 24.4 pwm duty vs register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 table 24.5 voltage limits vs. register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 table 24.6 temperature limits vs. register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 24.7 fan zone setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 table 24.8 fan spin-up register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 24.9 pwm frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 24.10register setting vs. temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 63 table 24.11pwm ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 table 24.12pwm duty vs. register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 table 24.13temperature limit vs. register se tting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 table 24.14absolute limit vs. register setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 24.15avg[2:0] bit decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 table 24.16programming options for the pwmx_n[1:0] bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 table 25.1 sysopt strap option configuration address select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 table 25.2 sch311x logical device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 89 table 25.3 configuration register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 table 25.4 chip-level (global) configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 94 table 25.5 test register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 15 revision 0.4 (06-03-05) datasheet table 25.6 logical device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 25.7 base i/o range for logical devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 table 25.8 primary interrupt select register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 table 25.9 dma channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 table 25.10floppy disk controller, logical device 0 [logical device number = 0x00 . . . . . . . . . . . . . 303 table 25.11parallel port, logical device 3 [logical device nu mber = 0x03] . . . . . . . . . . . . . . . . . . . . . 304 table 25.12serial port 1, logical device 4 [logical device number = 0x04 . . . . . . . . . . . . . . . . . . . . . 304 table 25.13serial port 2. logical device 5 [logical device number = 0x05]. . . . . . . . . . . . . . . . . . . . . 305 table 25.14kybd. logical device 7 [logical device number = 0x07]. . . . . . . . . . . . . . . . . . . . . . . . . . 306 table 25.15logical device a [logical device number = 0x0a] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 table 25.16serial port 3, logical device b [logical device number = 0x0b . . . . . . . . . . . . . . . . . . . . . 307 table 25.17serial port 4, logical device c logical device number = 0x0c . . . . . . . . . . . . . . . . . . . . . 308 table 25.18serial port 5, logical device d [logical device number = 0x0d] . . . . . . . . . . . . . . . . . . . . 308 table 25.19serial port 6, logical device e logical device number = 0x0e . . . . . . . . . . . . . . . . . . . . . 309 table 26.1 sch311x runtime register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 26.2 runtime register por summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 table 26.3 detailed runtime register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 table 27.1 valid power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 table 28.1 buffer operational ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 table 28.2 capacitance ta = 25; fc = 1mhz; v cc = 3.3v 10%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 table 29.1 resume reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 table a.1 analog-to-digital voltage conv ersions for hardware monitoring block. . . . . . . . . . . . . . . . . 387 table c.1 toggling inputs in descending order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 table c.2 toggling inputs in ascending order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 16 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 17 revision 0.4 (06-03-05) datasheet chapter 1 general description the sch3112/sch3114/sch3116 product family is a 3.3v (super i/o block is 5v tolerant) pc99/pc2001 compliant super i/o controller with an lpc interface. the s ch3112/sch3114/sch3116 product family also includes hardware monitoring capabilities, enhanced security features, power control logic and motherboard glue logic. the sch3112/sch3114/sch3116 product family 's hardware monitoring capability includes temperature, voltage and fan speed monitoring. it has the ability to alert the system of out-of-limit conditions and automatically control the speeds of multiple fans. there are four analog inputs for monitoring external voltages of +5v, +2.5v, +12v a nd vccp (core processor voltage), as well as internal monitoring of the sio's vcc, vtr, and vbat po wer supplies. the sch3112/sch3114/sch3116 product family includes support for monitoring two exter nal temperatures via thermal diode inputs and an internal sensor for measuring ambient temperature. the nhwm_int pin is implemented to indicate out- of-limit temperature, voltage, and fantach conditions. the hardware monitoring block of the sch3112/sch3114/sch3116 product family is accessible via the lpc bus. the same interrupt event reported on the nhwm_int pin also creates pme wakeup events. a separate thermtrip output is available, which generates a pulse output on a pr ogrammed over temperature condition. this can be used to generate an reset or shutdown indicator to the system. the hardware monitoring capability also has pr ogrammable automatic fa n control. three fan tachometer inputs and three pulse width modulator (pwm) outputs are available. the motherboard glue logic includes various power management and system logic including generation of nrsmrst, a programmable clock output, and rese t generation. the reset generation includes a watchdog timer which can be used to generate a reset pulse. the width of this pulse is selectable via an external strapping option. the sch3112/sch3114/sch3116 product family incor porates complete legacy super i/o functionality including an 8042 based keyboard and mouse controller, an ieee 1284, epp, and ecp compatible parallel port, multiple serial ports, one irda 1.0 infrar ed ports, and a floppy disk controller with smsc's true cmos 765b core and enhanced digital data se parator, the true cmos 765b core provides 100% compatibility with ibm pc/xt and pc /at architectures and is software and register compatible with smsc's proprietary 82077aa core. system related func tionality, which offers flexibility to the system designer, general purpose i/o control fu nctions, and control of two led's. the serial ports are fully functional ns16550 compatible uarts that support data rates up to 1.5 mbps. there are four, 8 pin serial ports and two, 4pin serial ports. the reduced pin serial ports have selectable input and output controls. the serial ports contain programmable direction control, which will automatically drive nrts when the output buffer is loaded, then dr ive nrts when the output buffer is empty. the sch3112/sch3114/sch3116 product family is acpi 1.0/2.0 compatible and therefore supports multiple low power-down modes. it incorporates s ophisticated power control circuitry (pcc), which includes support for keyboard. the sch3112/sch3114/sch3116 produc t family supports the isa plug -and-play standard register set (version 1.0a). the i/o address, dma channel and hardware irq of each logical device in the sch3112/sch3114/sch3116 product family may be r eprogrammed through the internal configuration registers. there are up to 480 (960 - parallel port) i/o address location options, a serialized irq interface, and three dma channels.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 18 smsc sch311x datasheet note 1.1 legacy blocks include floppy disk, parallel port, watc hdog timer and ke yboard controller note 1.2 2 of the 6 serial ports have 4 pin interfaces table 1.1 device specific summary function sch3112 sch3114 sch3116 lpc bus interface yes yes yes legacy functional blocks ( note 1.1 ) yes yes yes floppy on parallel port option yes yes yes reset generator yes yes yes serial ports 246 ( note 1.2 ) programmable clock output yes yes yes ide / pci reset outputs yes yes no power button / ac fail support yes yes no gpios 40 40 40 gpio with vid compatible inputs 666 dedicated gpios 16 0 0 hardware monitor yes yes yes
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 19 revision 0.4 (06-03-05) datasheet chapter 2 pinout figure 2.1 sch3112 pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sch3112 128 pin vtqfp npcirst 3/ gp47 avss vbat gp27 / nio_smi / p17 kdat / gp21 kclk / gp22 mdat / gp32 mclk/ gp33 gp36 /nkbdrst gp37 /a20m vss vtr ninit / ndir nscltin / nstep pd0 / nindex pd1 / ntrk0 pd2 / nwrtprt pd3 / nrdata pd4 / ndskchg pd5 pd6 / nmtr0 pd7 vss slct / nwgate pe / nwdata busy / nmtr1 nack / nds1 nerror / nhdsel nalf / drvden0 nstrobe / nds0 nri1 ndcd1 +12v_in +5v_in gp40 /drvden0 vtr nmtr0 ndskchg nds0 vss ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata clocki lad0 lad1 lad2 lad3 lframe# ldrq# pci_reset# pci_clk ser_irq vss vcc nide_rstdrv/gp44 npcrst1 / gp45 npcirst2 / gp46 +2.5v_in vccp_in remote1+ remote1- remote2+ remote2- hvtr hvss fantach1 fantach2 fantach3 pwm1 pwm2 pwm3 nhwm_int nthermtrip vss vtr nfprst/gp30 pwrgd_ps pwrgd_out gp34 gp62* gp67* gp66* gp65* gp64* vss nrsmrst clki32 gp63* gp31 gp12 gp13 gp60 / nled1 / wdt gp61 / nled2/ clko gp15 vtr gp42 / nio_pme gp16 gp17 / tstout gp14 gp11 gp10 slp_sx# pb_in# ps_on# pb_out# gp57 / ndtr2 gp56/ ncts2 gp55/nrts2/resgen gp54 / ndsr2 gp53 / txd2 (irtx2) gp52 / rxd2 (irrx2) gp51 / ndcd2 vss vtr gp50 / nri2 ndtr1 / sysopt1 ncts1 nrts1 / sysopt0 ndsr1 txd1 /sioxnorout rxd1 hvtr v t r v c c vcc v c c note: sysopt1 pin 68 sysopt0 pin 70 and resgen pin 78 are only sampled during power on configuration vbat hvtr vtr vcc
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 20 smsc sch311x datasheet 2.1 sch311x pinout summary table 2.1 sch3112 summary - 2 serial ports pin # name pin # name pin # name pin # name 1 +12v_in 33 npcirst3 / gp47 65 rxd1 97 gp31 2 +5v_in 34 avss 66 txd1/ sio xnor_out 98 gp63* 3gp40 / drvden0 35 vbat 67 ndsr1 99 clki32 4 vtr 36 gp27/nio_smi/p1 7 68 nrts1/sysopt0 100 nrsmrst 5 nmtr0 37 kdat/gp21 69 ncts1 101 vss 6 ndskchg 38 kclk/gp22 70 ndtr1/sysopt1 102 gp64* 7 nds0 39 mdat/gp32 71 gp50 / nri2 103 gp65* 8 vss 40 mclk/gp33 72 vtr 104 gp66* 9 ndir 41 gp36/nkbdrst 73 vss 105 gp67* 10 nstep 42 gp37/a20m 74 gp51 / ndcd2 106 gp62* 11 nwdata 43 vss 75 gp52 / rxd2(irrx2) 107 gp34 12 nwgate 44 vtr 76 gp53 / txd2(irtx2) 108 pwrgd_out 13 nhdsel 45 ninit / ndir 77 gp54 / ndsr2 109 pwrgd_ps 14 nindex 46 nslctin / nstep 78 gp55 / nrts2 / resgen 110 nfprst / gp30 15 ntrk0 47 pd0 / nindex 79 gp56 / ncts2 111 vtr 16 nwrtprt 48 pd1 / ntrk0 80 gp 57 / ndtr2 112 vss 17 nrdata 49 pd2 / nwrtprt 81 pb_out# 113 nthermtrip 18 clocki 50 pd3 / nrdata 82 ps_on# 114 nhwm_int 19 lad0 51 pd4 / ndskchg 83 pb_in# 115 pwm3 20 lad1 52 pd5 84 slp_sx# 116 pwm2 21 lad2 53 pd6 / nmtr0 85 gp10 117 pwm1 22 lad3 54 pd7 86 gp11 118 fantach3 23 lframe# 55 vss 87 gp14 119 fantach2 24 ldrq# 56 slct / nwgate 88 gp17 120 fantach1 25 pci_reset# 57 pe / nwdata 89 gp16 121 hvss 26 pci_clk 58 busy / nmtr1 90 gp42/nio_pme_ 122 hvtr 27 ser_irq 59 nack / nds1 91 vtr 123 remote2- 28 vss 60 nerror / nhdsel 92 gp15 124 remote2+ 29 vcc 61 nalf / drvden0 93 gp61/nled2/clk o 125 remote1- 30 nide_rstdrv / gp44 62 nstrobe / nds0 94 gp60/nled1/wd t 126 remote1+ 31 npcirst1 / gp45 63 nri1 95 gp13 127 vccp_in 32 npcirst2 / gp46 64 ndcd1 96 gp12 128 +2.5v_in
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 21 revision 0.4 (06-03-05) datasheet figure 2.2 sch3114 pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sch3114 128 pin vtqfp npcirst 3/ gp47 avss vbat gp27 / nio_smi / p17 kdat / gp21 kclk / gp22 mdat / gp32 mclk/ gp33 gp36 /nkbdrst gp37 /a20m vss vtr ninit / ndir nscltin / nstep pd0 / nindex pd1 / ntrk0 pd2 / nwrtprt pd3 / nrdata pd4 / ndskchg pd5 pd6 / nmtr0 pd7 vss slct / nwgate pe / nwdata busy / nmtr1 nack / nds1 nerror / nhdsel nalf / drvden0 nstrobe / nds0 nri1 ndcd1 +12v_in +5v_in gp40 /drvden0 vtr nmtr0 ndskchg nds0 vss ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata clocki lad0 lad1 lad2 lad3 lframe# ldrq# pci_reset# pci_clk ser_irq vss vcc nide_rstdrv/gp44 npcrst1 / gp45 npcirst2 / gp46 +2.5v_in vccp_in remote1+ remote1- remote2+ remote2- hvtr hvss fantach1 fantach2 fantach3 pwm1 pwm2 pwm3 nhwm_int nthermtrip vss vtr nfprst/gp30 pwrgd_ps pwrgd_out gp34 / ndtr4 gp62* / ncts4 gp67* / nrts4 gp66* / ndsr4 gp65* / txd4 gp64* / rxd4 vss nrsmrst clki32 gp63* / ndcd4 gp31 / nri4 gp12 / ndcd3 gp13 / nri3 gp60 / nled1 / wdt gp61 / nled2/ clko gp15 / ndtr3 vtr gp42 / nio_pme gp16 / ncts3 gp17 / nrts3/tstout gp14 / ndsr3 gp11 / txd3 gp10 / rxd3 slp_sx# pb_in# ps_on# pb_out# gp57 / ndtr2 gp56/ ncts2 gp55/nrts2/resgen gp54 / ndsr2 gp53 / txd2 (irtx2) gp52 / rxd2 (irrx2) gp51 / ndcd2 vss vtr gp50 / nri2 ndtr1 / sysopt1 ncts1 nrts1 / sysopt0 ndsr1 txd1 /sioxnorout rxd1 hvtr v t r v c c vcc v c c note: sysopt1 pin 68 sysopt0 pin 70 and resgen pin 78 are only sampled during power on cinfiguration vbat hvtr vtr vcc
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 22 smsc sch311x datasheet table 2.2 sch3114 summary - 4 serial ports pin # name pin # name pin # name pin # name 1 +12v_in 33 npcirst3 / gp47 65 rxd1 97 gp31 / nri4 2 +5v_in 34 avss 66 txd1/ sio xnor_out 98 gp63* / ndcd4 3 gp40/drvden 0 35 vbat 67 ndsr1 99 clki32 4 vtr 36 gp27/nio_smi/p1 7 68 nrts1/sysopt0 100 nrsmrst 5 nmtr0 37 kdat/gp21 69 ncts1 101 vss 6 ndskchg 38 kclk/gp22 70 ndtr1/sysopt1 102 gp64* / rxd4 7 nds0 39 mdat/gp32 71 gp50 / nri2 103 gp65* / txd4 8 vss 40 mclk/gp33 72 vtr 104 gp66* / ndsr4 9 ndir 41 gp36/nkbdrst 73 vss 105 gp67* / nrts4 10 nstep 42 gp37/a20m 74 gp51 / ndcd2 106 gp62* / ncts4 11 nwdata 43 vss 75 gp52 / rxd2(irrx2) 107 gp34 / ndtr4 12 nwgate 44 vtr 76 gp53 / txd2(irtx2) 108 pwrgd_out 13 nhdsel 45 ninit / ndir 77 gp54 / ndsr2 109 pwrgd_ps 14 nindex 46 nslctin / nstep 78 gp55 / nrts2 / resgen 110 nfprst / gp30 15 ntrk0 47 pd0 / nindex 79 gp56 / ncts2 111 vtr 16 nwrtprt 48 pd1 / ntrk0 80 gp 57 / ndtr2 112 vss 17 nrdata 49 pd2 / nwrtprt 81 pb_out# 113 nthermtrip 18 clocki 50 pd3 / nrdata 82 ps_on# 114 nhwm_int 19 lad0 51 pd4 / ndskchg 83 pb_in# 115 pwm3 20 lad1 52 pd5 84 slp_sx# 116 pwm2 21 lad2 53 pd6 / nmtr0 85 gp10/rxd3 117 pwm1 22 lad3 54 pd7 86 gp11 / txd3 118 fantach3 23 lframe# 55 vss 87 gp14 / ndsr3 119 fantach2 24 ldrq# 56 slct / nwgate 88 gp17 / nrts3 120 fantach1 25 pci_reset# 57 pe / nwdata 89 gp16 / ncts3 121 hvss 26 pci_clk 58 busy / nmtr1 90 gp42/nio_pme_ 122 hvtr 27 ser_irq 59 nack / nds1 91 vtr 123 remote2- 28 vss 60 nerror / nhdsel 92 gp15 / ndtr3 124 remote2+ 29 vcc 61 nalf / drvden0 93 gp61/nled2/clk o 125 remote1- 30 nide_rstdrv / gp44 62 nstrobe / nds0 94 gp60/nled1/wd t 126 remote1+ 31 npcirst1 / gp45 63 nri1 95 gp13 / nri3 127 vccp_in 32 npcirst2 / gp46 64 ndcd1 96 gp12 / ndcd3 128 +2.5v_in
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 23 revision 0.4 (06-03-05) datasheet figure 2.3 sch116 pin diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sch3116 preliminary 128 pin vtqfp gp47/nscout6 - npcirst 3/ gp47 avss vbat gp27 / nio_smi / p17 kdat / gp21 kclk / gp22 mdat / gp32 mclk/ gp33 gp36 /nkbdrst gp37 /a20m vss vtr ninit / ndir nscltin / nstep pd0 / nindex pd1 / ntrk0 pd2 / nwrtprt pd3 / nrdata pd4 / ndskchg pd5 pd6 / nmtr0 pd7 vss slct / nwgate pe / nwdata busy / nmtr1 nack / nds1 nerror / nhdsel nalf / drvden0 nstrobe / nds0 nri1 ndcd1 +12v_in +5v_in gp40 /drvden0 vtr nmtr0 ndskchg nds0 vss ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata clocki lad0 lad1 lad2 lad3 lframe# ldrq# pci_reset# pci_clk ser_irq vss vcc gp44 / txd6 e _rstdrv/gp44 gp45 / rxd6 n pcrst1 / gp45 gp46 / nscin6 n pcirst2 / gp46 +2.5v_in vccp_in remote1+ remote1- remote2+ remote2- hvtr hvss fantach1 fantach2 fantach3 pwm1 pwm2 pwm3 nhwm_int nthermtrip vss vtr nfprst/gp30 pwrgd_ps pwrgd_out gp34 / ndtr4 gp62* / ncts4 gp67* / nrts4 / gp66* / ndsr4 gp65* / txd4 gp64* / rxd4 vss nrsmrst clki32 gp63* / ndcd4 gp31 / nri4 gp12 / ndcd3 gp13 / nri3 gp60 / nled1 / wdt gp61 / nled2/ clko gp15 / ndtr3 vtr gp42 / nio_pme gp16 / ncts3 gp17 / nrts3/tstou t gp14 / ndsr3 gp11 / txd3 gp10 / rxd3 slp_sx# / nscin5 pb_in# / nscout5 ps_on# / txd5 pb_out# / rxd5 gp57 / ndtr2 gp56/ ncts2 gp55/nrts2/resge n gp54 / ndsr2 gp53 / txd2 (irtx2) gp52 / rxd2 (irrx2) gp51 / ndcd2 vss vtr gp50 / nri2 ndtr1 / sysopt1 ncts1 nrts1 / sysopt0 ndsr1 txd1 /sioxnorout rxd1 hvtr v t r v c c vcc v c c note: sysopt1 pin 68 sysopt0 pin 70 and resgen pin 78 are only sampled during power on cinfiguration vbat hvtr vtr vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 sch3116 128 pin vtqfp gp47/nscout6 avss vbat gp27 / nio_smi / p17 kdat / gp21 kclk / gp22 mdat / gp32 mclk/ gp33 gp36 /nkbdrst gp37 /a20m vss vtr ninit / ndir nscltin / nstep pd0 / nindex pd1 / ntrk0 pd2 / nwrtprt pd3 / nrdata pd4 / ndskchg pd5 pd6 / nmtr0 pd7 vss slct / nwgate pe / nwdata busy / nmtr1 nack / nds1 nerror / nhdsel nalf / drvden0 nstrobe / nds0 nri1 ndcd1 +12v_in +5v_in gp40 /drvden0 vtr nmtr0 ndskchg nds0 vss ndir nstep nwdata nwgate nhdsel nindex ntrk0 nwrtprt nrdata clocki lad0 lad1 lad2 lad3 lframe# ldrq# pci_reset# pci_clk ser_irq vss vcc gp44 / txd6 gp45 / rxd6 gp46 / nscin6 +2.5v_in vccp_in remote1+ remote1- remote2+ remote2- hvtr hvss fantach1 fantach2 fantach3 pwm1 pwm2 pwm3 nhwm_int nthermtrip vss vtr nfprst/gp30 pwrgd_ps pwrgd_out gp34 / ndtr4 gp62* / ncts4 gp67* / nrts4 gp66* / ndsr4 gp65* / txd4 gp64* / rxd4 vss nrsmrst clki32 gp63* / ndcd4 gp31 / nri4 gp12 / ndcd3 gp13 / nri3 gp60 / nled1 / wdt gp61 / nled2/ clko gp15 / ndtr3 vtr gp42 / nio_pme gp16 / ncts3 gp17 / nrts3/tstout gp14 / ndsr3 gp11 / txd3 gp10 / rxd3 nscin5 nscout5 txd5 rxd5 gp57 / ndtr2 gp56/ ncts2 gp55/nrts2/resgen gp54 / ndsr2 gp53 / txd2 (irtx2) gp52 / rxd2 (irrx2) gp51 / ndcd2 vss vtr gp50 / nri2 ndtr1 / sysopt1 ncts1 nrts1 / sysopt0 ndsr1 txd1 /sioxnorout rxd1 hvtr v t r v c c vcc v c c note: sysopt1 pin 68 sysopt0 pin 70 and resgen pin 78 are only sampled during power on configuration vbat hvtr vtr vcc
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 24 smsc sch311x datasheet figure 2.4 sch3116 summary - 6 ports pin # name pin # name pin # name pin # name 1 +12v_in 33 gp47 / nscout6 65 rxd1 97 gp31 / nri4 2 +5v_in 34 avss 66 txd1/ sio xnor_out 98 gp63* / ndcd4 3 gp40/drvden 0 35 vbat 67 ndsr1 99 clki32 4 vtr 36 gp27/nio_smi/p1 7 68 nrts1/sysopt0 100 nrsmrst 5 nmtr0 37 kdat/gp21 69 ncts1 101 vss 6 ndskchg 38 kclk/gp22 70 ndtr1/sysopt1 102 gp64* / rxd4 7 nds0 39 mdat/gp32 71 gp50 / nri2 103 gp65* / txd4 8 vss 40 mclk/gp33 72 vtr 104 gp66* / ndsr4 9 ndir 41 gp36/nkbdrst 73 vss 105 gp67* / nrts4 10 nstep 42 gp37/a20m 74 gp51 / ndcd2 106 gp62* / ncts4 11 nwdata 43 vss 75 gp52 / rxd2(irrx2) 107 gp34 / ndtr4 12 nwgate 44 vtr 76 gp53 / txd2(irtx2) 108 pwrgd_out 13 nhdsel 45 ninit / ndir 77 gp54 / ndsr2 109 pwrgd_ps 14 nindex 46 nslctin / nstep 78 gp55 / nrts2 / resgen 110 nfprst / gp30 15 ntrk0 47 pd0 / nindex 79 gp56 / ncts2 111 vtr 16 nwrtprt 48 pd1 / ntrk0 80 gp 57 / ndtr2 112 vss 17 nrdata 49 pd2 / nwrtprt 81 rxd5 113 nthermtrip 18 clocki 50 pd3 / nrdata 82 txd5 114 nhwm_int 19 lad0 51 pd4 / ndskchg 83 nscout5 115 pwm3 20 lad1 52 pd5 84 nscin5 116 pwm2 21 lad2 53 pd6 / nmtr0 85 gp10/rxd3 117 pwm1 22 lad3 54 pd7 86 gp11 / txd3 118 fantach3 23 lframe# 55 vss 87 gp14 / ndsr3 119 fantach2 24 ldrq# 56 slct / nwgate 88 gp17 / nrts3 120 fantach1 25 pci_reset# 57 pe / nwdata 89 gp16 / ncts3 121 hvss 26 pci_clk 58 busy / nmtr1 90 gp42/nio_pme_ 122 hvtr 27 ser_irq 59 nack / nds1 91 vtr 123 remote2- 28 vss 60 nerror / nhdsel 92 gp15 / ndtr3 124 remote2+ 29 vcc 61 nalf / drvden0 93 gp61/nled2/clk o 125 remote1- 30 gp44 / txd6 62 nstrobe / nds0 94 gp60/nled1/wd t 126 remote1+ 31 gp45 / rxd6 63 nri1 95 gp13 / nri3 127 vccp_in 32 gp46 / nscin6 64 ndcd1 96 gp12 / ndcd3 128 +2.5v_in
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 25 revision 0.4 (06-03-05) datasheet table 2.3 sch311x signal difference summary pin # sch3112 sch3114 sch3116 30 nide_rstdrv / gp44 nide_rstdrv / gp44 gp44 / txd6 30 nide_rstdrv / gp44 nide_rstdrv / gp44 gp44 / txd6 31 npcirst1 / gp45 npcirst1 / gp45 gp45 / rxd6 32 npcirst2 / gp46 npcirst2 / gp46 gp46 / nscin6 33 npcirst3 / gp47 npcirst3 / gp47 gp47 / nscout6 81 pb_out# pb_out# rxd5 82 ps_on# ps_on# txd5 83 pb_in# pb_in# nscout5 84 slp_sx# slp_sx# nscin5 85 gp10 gp10/rxd3 gp10/rxd3 86 gp11 gp11/txd3 gp11/txd3 87 gp14 gp14/ndsr3 gp14/ndsr3 88 gp17 gp17/nrts3 gp17/nrts3 89 gp16 gp16/ncts3 gp16/ncts3 92 gp15 gp15/ndtr3 gp15/ndtr3 95 gp13 gp13/nri3 gp13/nri3 96 gp12 gp12/ndcd3 gp12/ndcd3 97 gp31 gp31 / nri4 gp31 / nri4 98 gp63* gp63* / ndcd4 gp63* / ndcd4 102 gp64* gp64* / rxd4 gp64* / rxd4 103 gp65* gp65* / txd4 gp65* / txd4 104 gp66* gp66* /ndsr4 gp66* /ndsr4 105 gp67* gp67* / nrts4 gp67* / nrts4 106 gp62* gp62* /ncts4 gp62* /ncts4 107 gp34 gp34 / ndtr4 gp34 / ndtr4
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 26 smsc sch311x datasheet 2.2 pin functions the sch311x family of devices have the same basic pinout for legacy functions, as shown in table 2.4 . the pin descriptions for the sch3112 is shown in ta b l e 2 . 5 . signals specific to the sch3114 are shown in ta b l e 2 . 6 . signals specific to the sch3116 are shown in table 2.7 . table 2.4 sch311x pin core functions description ( note 2.14 ) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 ) power pins (16) 29 2.3 , 2.4 vcc +3.3 volt supply voltage 4,44 ,72, 91, 111 2.3 , 2.4 vtr +3.3 volt standby supply voltage 35 2.8 vbat +3.0 volt battery supply ) 8,28 ,43, 55, 73, 101, 112 vss ground 34 avss analog ground 122 2.3 hvtr analog power. +3.3v vtr pin dedicated to the hardware monitoring block. hvtr is powered by +3.3v standby power vtr. 121 2.3 hvss analog ground. internally connected to all of the hardware monitoring block circuitry. clock pins (2) 99 clki32 32.768khz trickle clock input clki32 no gate is 18 clocki 14.318mhz clock input clocki is lpc interface (9) 22 - 19 lad[3:0] multiplexed command address and data lad[3:0] gate/ hi-z pci_io 23 lframe # frame signal. indicates start of new cycle and termination of broken cycle lframe# gate pci_i 24 ldrq# encoded dma request ldrq# gate/hi-z pci_o 25 pci_res et# pci reset pci_res et# no gate pci_i
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 27 revision 0.4 (06-03-05) datasheet 26 pci_clk pci clock pci_clk gate pci_iclk 27 ser_irq serial irq ser_irq gate / hi-z pci_io fdd interface (13) 3 2.9 gp40/ drvden 0 general purpose i/o /drive density select 0 gp40/ drvden0 gp40 gp40 no gate / hi- z (i/o12/od1 2)/ (o12/od12 ) 5 nmtr0 motor on 0 nmtr0 hi-z (o12/od12 ) 6 ndskch g disk change ndskch g gate is 7 nds0 drive select 0 nds0 hi-z (o12/od12 ) 9 ndir step direction ndir hi-z (o12/od12 ) 10 nstep step pulse nstep hi-z (o12/od12 ) 11 nwdata write disk data nwdata hi-z (o12/od12 ) 12 nwgate write gate nwgate hi-z (o12/od12 ) 13 nhdsel head select nhdsel hi-z (o12/od12 ) 14 nindex index pulse input nindex gate is 15 ntrk0 track 0 ntrk0 gate is 16 nwrtpr t write protected nwrtpr t gate is 17 nrdata read disk data nrdata gate is serial port 1 interface (8) 65 rxd1 receive data 1 rxd1 gate is 66 txd1 /sio xnor_o ut transmit data 1 / xnor-chain test mode output for sio block txd1 /sio xnor_o ut hi-z o12/o12 67 ndsr1 data set ready 1 ndsr1 gate i 68 2.7 nrts1/ sysopt 0 request to send 1/ sysopt (configuration port base address control) nrts1/ sysopt0 gate/ hi-z op14/i table 2.4 sch311x pin core functions description ( note 2.14 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 28 smsc sch311x datasheet 69 ncts1 clear to send 1 ncts1 gate i 70 ndtr1 / sysopt 1 data terminal ready 1 ndtr1 / sysopt1 gate/ hi-z o6 63 2.9 nri1 ring indicator 1 nri1 gate is 64 ndcd1 data carrier detect 1 ndcd1 gate i serial port 2 interface (8) 71 2.9 gp50 / nri2 ring indicator 2 gp50 nri2 no gate/ hi-z i/ iod8 74 2.9 gp51 / ndcd2 data carrier detect 2 gp51 / ndcd2 no gate/ hi-z i 75 2.9 gp52 / rxd2 (irrx2) receive data 2 (irrx2) gp52 / rxd2 (irrx2) no gate/ hi-z is 76 2.11 , 2.9 gp53 / txd2 (irtx2) transmit data 2 (irtx2) gp53 / txd2 (irtx2) no gate/ hi-z o12 77 2.9 gp54 / ndsr2 data set ready 2 gp54 / ndsr2 no gate/ hi-z i 78 2.9 gp55 / nrts2 / resgen request to send 2 / reset generator pulse width strap option gp55 / nrts2 / resgen no gate/ hi-z op14 / i 79 2.9 gp56 / ncts2 clear to send 2 gp56 / ncts2 no gate/ hi-z i 80 2.9 gp57 / ndtr2 data terminal ready 2 gp57 / ndtr2 no gate/ hi-z o6 shared parallel port / fdc intrerface (17) 45 2.12 ninit / ndir initiate output ninit / ndir gate / hi-z (od14/op1 4) 46 2.12 nslctin / nstep printer select input nslctin / nstep gate / hi-z (od14/op1 4) 47 2.12 pd0 / nindex port data 0 pd0 / nindex gate / hi-z iop14 48 2.12 pd1 / ntrk0 port data 1 pd1 / ntrk0 gate / hi-z iop14 49 2.12 pd2 / nwrtpr t port data 2 pd2 / nwrtpr t gate / hi-z iop14 50 2.12 pd3 / nrdata port data 3 pd3 / nrdata gate / hi-z iop14 table 2.4 sch311x pin core functions description ( note 2.14 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 29 revision 0.4 (06-03-05) datasheet 51 2.12 pd4 / ndskch g port data 4 pd4 / ndskch g gate / hi-z iop14 52 2.12 pd5 port data 5 pd5 gate / hi-z iop14 53 2.12 pd6 / nmtr0 port data 6 pd6 / nmtr0 gate / hi-z iop14 54 2.12 pd7 port data 7 pd7 gate / hi-z iop14 56 2.12 slct / nwgate printer selected status slct / nwgate gate / hi-z i 57 2.12 pe / nwdata paper end pe / nwdata gate / hi-z i 58 2.12 busy / nmtr1 busy busy / nmtr1 gate / hi-z i 59 2.12 nack / nds1 acknowledge nack / nds1 gate / hi-z i 60 2.12 nerror / nhdsel error nerror / nhdsel gate / hi-z i 61 2.12 nalf / drvden 0 autofeed output nalf / drvden0 gate / hi-z (od14/op1 4) 62 2.12 nstrob e / nds0 strobe output nstrobe / nds0 gate / hi-z (od14/op1 4) keyboard/mouse interface (6) 37 2.9 kdat/gp 21 keyboard data i/o general purpose i/o kdat/gp 21 no gate / hi-z (i/od16)/ (i/o16/od1 6) 38 2.9 kclk/gp 22 keyboard clock i/o general purpose i/o kclk/gp 22 no gate / hi-z i/od16)/ (i/o16/od1 6) 39 2.9 mdat/gp 32 mouse data i/o /general purpose i/o mdat/gp 32 no gate / hi-z (i/od16) /(i/o16/od1 6) 40 2.9 mclk/gp 33 mouse clock i/o /general purpose i/o mclk/gp 33 no gate / hi-z (i/o16/od1 6) /(i/od16) 41 2.6 gp36/ nkbdrs t general purpose i/o. gpio can be configured as an open-drain output. keyboard reset open- drain output ( note 2.10 ) gp36/ nkbdrst no gate / hi-z (i/o8/od8) /od8 table 2.4 sch311x pin core functions description ( note 2.14 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 30 smsc sch311x datasheet 42 2.6 gp37/ a20m general purpose i/o. gpio can be configured as an open-drain output. gate a20 open-drain output ( note 2.10 ) gp37/ a20m no gate / hi-z (i/o8/od8) /od8 miscellaneous pins (5) 90 gp42/ nio_pme general purpose i/o. power management event output. this active low power management event signal allows this device to request wake-up in either s3 or s5 and below. gp42/ nio_pme no gate (i/o12/od1 2) /(o12/od12 ) 94 2.8 , 2.9 gp60 /nled1 /wdt general purpose i/o /nled1 watchdog timer output gp60 /nled1 /wdt no gate (i/o12/od1 2) /(o12/od12 ) /(o12/od12 ) 110 nfprst / gp30 front panel reset / general purpose io nfprst / gp30 no gate ispu_400 / 109 pwrgd_ ps power good input from power supply pwrgd _ps no gate ispu_400 108 pwrgd_ out power good output ? open drain pwrgd _out no gate od8 100 nrsmrs t resume reset output nrsmrs t no gate od24 93 2.8 , 2.9 gp61 /nled2 / clko general purpose i/o /nled2 / programmable clock output gp61 /nled2 / clko no gate (i/o12/od1 2) /(o12/od12 ) 36 2.9 gp27 /nio_smi /p17 general purpose i/o /system mgt. interrupt /8042 p17 i/o gp27 /nio_smi /p17 gp27 / hi-z (i/o12/od1 2) /(o12/od12 ) /(i/o12/od1 2) hardware monitoring block (23) 114 nhwm_i nt interrupt output for hardware monitor nhwm_i nt od8 2 2.10 +5v_in analog input for +5v hvtr i an 128 2.10 +2.5_in analog input for +2.5v hvtr i an 127 2.10 vccp_in analog input for +vccp (processor voltage: 1.5 v nominal). hvtr i an table 2.4 sch311x pin core functions description ( note 2.14 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 31 revision 0.4 (06-03-05) datasheet 1 2.10 +12v_in analog input for +12v hvtr i an 125 remote 1- this is the negative analog input (current sink) from the remote thermal diode 1. hvtr i and- 126 remote 1+ this is the positive input (current source) from the remote thermal diode 1. hvtr i and+ 123 remote 2- this is the negative analog input (current sink) from the remote thermal diode 2. hvtr i and- 124 remote 2+ this is the positive input (current source) from the remote thermal diode 2. hvtr i and+ 117 pwm1 fan speed control 1 output. pwm1 od8 116 pwm2 fan speed control 2 output pwm2 od8 115 pwm3 fan speed control 3output pwm3 od8 113 ntherm trip thermtrip output ntherm trip od_ph 120 fantac h1 tachometer input 1 for monitoring a fan. fantac h1 i m 119 fantac h2 tachometer input 2 for monitoring a fan. fantac h2 i m 118 fantac h3 tachometer input 4 for monitoring a fan. fantac h3 i m table 2.5 sch3112 specific signals ( note 2.15 ) pin note name description vcc power plane vtr power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 ) reset outputs 33 2.13 npcirst3 / gp47 pci reset output 3 gpio with schmidt trigger input gp47 / npcirst 3 no gate (io8/iod8) 32 2.13 npcirst2 / gp46 pci reset output 2 gpio with schmidt trigger input npcirst 2 no gate (io8/iod8) 31 2.13 npcirst1 / gp45 pci reset output1 gpio with schmidt trigger input gp45 / npcirst 1 no gate (io8/iod8) table 2.4 sch311x pin core functions description ( note 2.14 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 32 smsc sch311x datasheet 30 2.13 nide_rst drv / gp44 ide reset output gpio with schmidt trigger input gp44 / nide_rs tdrv no gate (io8/iod8) glue logic 83 pb_in# / power button in is used to detect a power button event / pb_in# i/ (o8/od8) 84 2.9 slp_sx# sx sleep state input pin. / slp_sx# no gate i/ i 81 pb_out# power button out/ pb_out # no gate (o8/od8) is 82 ps_on# power supply on/ ps_on# no gate od8 / (o12) gpio 95 2.9 gp13 gpio gp13 no gate i/ io8 96 2.9 gp12 gpio gp12 no gate i 85 2.9 gp10 gpio gp10 hi-z is 86 2.11 , 2.9 gp11 gpio gp11 no gate o12 87 2.9 gp14 gpio gp14 no gate i 88 2.9 gp17 // gpio / gp17 op14 / i 89 2.9 gp16 gpio gp16 i 92 2.9 gp15 gpio gp15 o6 97 2.9 gp31 gpio gp31 no gate i 98 2.9 gp63* gpio with i_vid buffer input gp63* no gate i 102 2.9 gp64* gpio with i_vid buffer input gp64* no gate is 103 2.11 , 2.9 gp65* gpio with i_vid buffer input gp65* no gate o12 104 2.9 gp66* gpio with i_vid buffer input gp66* no gate i 105 2.9 gp67* gpio with i_vid buffer input gp67* no gate op14 / i 106 2.9 gp62* gpio with i_vid buffer input gp62* no gate i 107 2.9 gp34 gpio gp34 no gate o6 table 2.5 sch3112 specific signals ( note 2.15 ) (continued) pin note name description vcc power plane vtr power plane vcc=0 opera- tion ( note 2.16 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 33 revision 0.4 (06-03-05) datasheet table 2.6 sch3114 specific signals ( note 2.15 ) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.1 6 ) buffer modes ( note 2.1 ) 33 2.13 npcirst3 / gp47 pci reset output 3 gpio with schmidt trigger input gp47 / npcirst 3 no gate (io8/iod8) 32 2.13 npcirst2 / gp46 pci reset output 2 gpio with schmidt trigger input npcirst 2 no gate (io8/iod8) 31 2.13 npcirst1 / gp45 pci reset output1 gpio with schmidt trigger input gp45 / npcirst 1 no gate (io8/iod8) 30 2.13 nide_rst drv / gp44 ide reset output gpio with schmidt trigger input gp44 / nide_rs tdrv no gate (io8/iod8) glue logic 83 pb_in# / power button in is used to detect a power button event / pb_in# no gate i/ (o8/od8) 84 2.9 slp_sx# sx sleep state input pin. / slp_sx# no gate i/ i 81 pb_out# power bu tton out/ pb_out # no gate (o8/od8) is 82 ps_on# power supply on/ ps_on# no gate od8 / (o12) serial port 3 interface (8) 95 2.9 gp13 / nri3 gpio / ring indicator 3 gp13 / nri3 no gate i/ io8 96 2.9 gp12 / ndcd3 gpio / data carrier detect 3 ndcd3 gp12 no gate i 85 2.9 gp10 / rxd3 gpio / receive data 3 gp10 / rxd3 / hi-z is 86 2.11 , 2.9 gp11 / txd3 gpio / transmit data 3 txd3 gp11 / hi-z o12 87 2.9 gp14 / ndsr3 gpio / data set ready 3 ndsr3 gp14 no gate i 88 2.9 gp17 / nrts3/ gpio / request to send 3 gp17 / nrts3/ / hi-z op14 / i 89 2.9 gp16 / ncts3 gpio / clear to send 3 gp16 / ncts3 / hi-z i 92 2.9 gp15 / ndtr3 gpio / data terminal ready 3 gp15 / ndtr3 / hi-z o6
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 34 smsc sch311x datasheet serial port 4 interface (8) 97 2.9 gp31 / nri4 gpio / ring indicator 4 gp31 / nri4 no gate i 98 2.9 gp63* / ndcd4 gpio with i_vid buffer input / data carrier detect 4 ndcd4 gp63* no gate i 102 2.9 gp64* / rxd4 gpio with i_vid buffer input / receive data 4 rxd4 gp64* no gate is 103 2.11 , 2.9 gp65* / txd4 gpio with i_vid buffer input / transmit data 4 txd4 gp65* / hi-z o12 104 2.9 gp66* / ndsr4 gpio with i_vid buffer input / data set ready 4 ndsr4 gp66* no gate i 105 2.9 gp67* / nrts4 gpio with i_vid buffer input / request to send 4 nrts4 gp67* / hi-z op14 / i 106 2.9 gp62* / ncts4 gpio with i_vid buffer input / clear to send 4 ncts4 gp62* no gate i 107 2.9 gp34 / ndtr4 gpio / data terminal ready 4 ndtr4 gp34 / hi-z o6 table 2.7 sch3116 specific signals ( note 2.15 ) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.1 6 ) buffer modes ( note 2.1 ) serial port 6 i/f 33 2.13 gp47 / nscout6 gpio with schmidt trigger input serial port 6 output control nscout6 gp47 / hi-z (io8/iod8) 32 2.13 gp46 / nscin6 gpio with schmidt trigger input serial port 6 input control gp46 / nscin6 no gate (io8/iod8) 31 2.13 gp45 / rxd6 gpio with schmidt trigger input receive serial port 6 rxd6 gate pg (io8/iod8) 30 2.13 gp44 / txd6 gpio with schmidt trigger input serial port 6 transmit txd6 gp44 no gate/ hi-z (io8/iod8) table 2.6 sch3114 specific signals ( note 2.15 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.1 6 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 35 revision 0.4 (06-03-05) datasheet serial port 5 i/f 83 nscout5 serial port 5 out control nscout5 / hi-z i/ (o8/od8) 84 2.9 nscin5 serial port 5 input control nscin5 no gate i/ i 81 rxd5 receive 5 rxd5 gate (o8/od8) is 82 txd5 serial port 5 transmit txd5 no gate / hi-z od8 / (o12) serial port 3 interface (8) 95 2.9 gp13 / nri3 gpio / ring indicator 3 gp13 / nri3 no gate i/ io8 96 2.9 gp12 / ndcd3 gpio / data carrier detect 3 ndcd3 gp12 no gate i 85 2.9 gp10 / rxd3 gpio / receive data 3 gp10 / rxd3 / hi-z is 86 2.11 , 2.9 gp11 / txd3 gpio / transmit data 3 txd3 gp11 / hi-z o12 87 2.9 gp14 / ndsr3 gpio / data set ready 3 ndsr3 gp14 no gate i 88 2.9 gp17 / nrts3/ gpio / request to send 3 gp17 / nrts3/ / hi-z op14 / i 89 2.9 gp16 / ncts3 gpio / clear to send 3 gp16 / ncts3 / hi-z i 92 2.9 gp15 / ndtr3 gpio / data terminal ready 3 gp15 / ndtr3 / hi-z o6 serial port 4 interface (8) 97 2.9 gp31 / nri4 gpio / ring indicator 4 gp31 / nri4 no gate i 98 2.9 gp63* / ndcd4 gpio with i_vid buffer input / data carrier detect 4 ndcd4 gp63* no gate i 102 2.9 gp64* / rxd4 gpio with i_vid buffer input / receive data 4 rxd4 gp64* no gate is 103 2.11 , 2.9 gp65* / txd4 gpio with i_vid buffer input / transmit data 4 txd4 gp65* / hi-z o12 104 2.9 gp66* / ndsr4 gpio with i_vid buffer input / data set ready 4 ndsr4 gp66* no gate i table 2.7 sch3116 specific signals ( note 2.15 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.1 6 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 36 smsc sch311x datasheet note: the ?n? as the first letter of a signal name or the ?#? as the suffix of a signal name indicates an ?active low? signal. note 2.1 buffer types per function on multiplexed pins are separated by a slash ?/?. buffer types in parenthesis represent multiple buffer types for a single pin function. note 2.2 pins that have input buffers must always be held to either a logical low or a logical high state when powered. bi-directional buses that may be trisected should have either weak external pull-ups or pull-downs to hold the pins in a logic state (i.e., logic states are vcc or ground). note 2.3 vcc and vss pins are for super i/o blocks. hvtr and hvss are dedicated for the hardware monitoring block. note 2.4 vtr can be connected to vcc if no wake-up functionality is required. note 2.5 the over current sense pin requires an exte rnal pull-up (30ua pull-up is suggested). note 2.6 external pull-ups must be placed on the nkbdrst and a20m pins. these pins are gpios that are inputs after an initial power-up (vtr por). if the nkbdrst and a20m functions are to be used, the system must ensure that these pins are high. note 2.7 the nrts1/sysopt0 pin requires an external pull-down resistor to put the base i/o address for configuration at 0x02e. an exte rnal pull-up resistor is required to move the base i/o address for configuration to 0x04e. note 2.8 the led pins are powered by vtr so that the leds can be controlled when the part is under vtr power. note 2.9 this pin is an input into the wake-up logic that is powered by vtr. in the case of a ring indicator for a serial port, or a gpio it will also go to vcc powered logic. this logic must be disabled when vcc=0. note 2.10 this analog input is backdrive protect ed. although hvtr is powered by vtr, it is possible that monitored power supplies may be powered when hvtr is off. note 2.11 the gp53/txd2(irtx) pin defaults to the gpio input function on a vtr por and presents a tristate impedance. when vcc=0 the pin is tristate. if gp53 function is selected and vcc is power is applied, the pin reflects the current state of gp53. the gp53/txd2(irtx) pin is tristate when it is configured for the txd2 (irtx) function under various conditions detailed in section 8.1.1, "ir transmit pin," on page 111 . note 2.12 these pins are multiplexed internally with the fdc i/f. when the fdc on pp mode is selected, the pp port alternate functions are used for the fdc i/f. 105 2.9 gp67* / nrts4 gpio with i_vid buffer input / request to send 4 nrts4 gp67* / hi-z op14 / i 106 2.9 gp62* / ncts4 gpio with i_vid buffer input / clear to send 4 ncts4 gp62* no gate i 107 2.9 gp34 / ndtr4 gpio / data terminal ready 4 ndtr4 gp34 / hi-z o6 table 2.7 sch3116 specific signals ( note 2.15 ) (continued) pin note name description vcc power plane vtr- power plane vcc=0 opera- tion ( note 2.1 6 ) buffer modes ( note 2.1 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 37 revision 0.4 (06-03-05) datasheet note 2.13 the reset glue logic is only available in sch3112, sch3114. the serial port is only available in the sch3116. in all the sch311x family, gp44 -47 have schmidt trigger inputs. note 2.14 the pins listed here are pins used in all of the sch311x devices. note 2.15 the pins listed here represent addition functionality to those pins listed in table 2.5 . note 2.16 all logic is powered by vtr. vcc on pin 29 is used as an indication of the presence of the vcc rail being active. all logic that requires vcc power only, is enabled only when the vcc rail is active. user?s note: open-drain pins should be pulled-up externally to supply shown in the power well column. all other pins are driven under the power well shown. nomenclature: no gate indicates that the pin is not protected, or affected by vcc=0 operation gate indicates that the pin is protected as an input (if required) or set to a hi-z state as an output (if required) in these columns, information is given in order of pin function: e.g. 1st pin function / 2nd pin function 2.3 buffer description table 2.8 lists the buffers that are used in this device. a complete description of these buffers can be found in tbd. table 2.8 buffer description buffer description i input ttl compatible - super i/o block. il input, low leakage current. i m input - hardware monitoring block. i an analog input, hardware monitoring block. i anp back bias protected analog input, hardware monitoring block. i and- remote thermal diode (current sink) negative input i and+ remote thermal diode (current source) positive input is input with schmitt trigger. i_vid input. see dc characteristics section. i m od3 input/output (open drain), 3ma sink. i m o3 input/output, 3ma sink, 3ma source. o6 output, 6ma sink, 3ma source. o8 output, 8ma sink, 4ma source. od8 open drain output, 8ma sink. io8 input/output, 8ma sink, 4ma source. iod8 input/open drain output, 8ma sink, 4ma source.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 38 smsc sch311x datasheet note 2.17 see the ?pci local bus specification,? revision 2.1, section 4.2.2. note 2.18 see the ?pci local bus specification,? revision 2.1, section 4.2.2 and 4.2.3. is/o8 input with schmitt trigger/output, 8ma sink, 4ma source. o12 output, 12ma sink, 6ma source. od12 open drain output, 12ma sink. od4 open drain output, 4ma sink. io12 input/output, 12ma sink, 6ma source. iod12 input/open drain output, 12ma sink, 6ma source. od14 open drain output, 14ma sink. op14 output, 14ma sink, 14ma source. od_ph input/output (open drain), see dc electrical characteristics on page 357 iop14 input/output, 14ma sink, 14ma source. backdrive protected. io16 input/output 16ma sink. iod16 input/output (open drain), 16ma sink. pci_io input/output. these pins must meet the pci 3.3v ac and dc characteristics. pci_o output. these pins must meet the pci 3.3v ac and dc characteristics. pci_i input. these pins must meet the pci 3.3v ac and dc characteristics. pci_iclk clock input. these pins must meet the pci 3.3v ac and dc characteristics and timing. nsw n channel switch (r on ~25 ohms) ispu_400 input with 400mv schmitt trigger and 30ua integrated pull-up. ispu input with schmitt trigger and integrated pull-up. table 2.8 buffer description (continued) buffer description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 39 revision 0.4 (06-03-05) datasheet chapter 3 block diagram figure 3.1 sch311x block diagram leds led2* led1* internal bus (data, address, and control lines) power mgmt clock gen clki32 clocki wdt 32 byte security key register power control and recovery pb_in# ps_on# slp_sx# pb_out# +5vtr_in +12v_in +2.5v_in vccp_in +5v_in hvtr hvss remote1- remote1+ remote2- remote2+ fantach1 fantach2 fantach3 pwm1 pwm2 pwm3 nhwm_int nthermtrip hardware monitor general purpose i/o vcc vtr vbat hwn_int 14.318mhz 96 mhz pci_reset# wdt* ser_irq pciclk lpc bus interface serial irq smsc proprietary 82077 compatible floppydisk controller with digital data separator & write precom- pensation high-speed 16550a uart port 1 & 2 multi-mode parallel port with chiprotect tm / and fdc mux keyboard/mouse 8042 controller pci reset outputs high-speed 16550a uart port 3& 4 high-speed 16550a uart port 5 & 6 txd1, rxd1 ncts1, nrts1 ndsr1, ndtr1 ndcd1, nri1 txd2 (irtx2) rxd2 (irrx2) ncts2, nrts2 ndsr2, ndtr2 ndcd2, nri2 pd[7:0] busy,nscltin sclt, pe nerror, nack nstrobe, ninit, nalf txd3, rxd3 ncts3, nrts3 ndsr3, ndtr3 ndcd3, nri3 txd4, rxd4, ncts4, nrts4 ndsr4, ndtr4 ndcd4, nri4 nide_rstdrv npcirst[1:3] mclk, mdat a20m, nkbdrst, kclk,kdat txd5, rxd5 nscin5 nscout5 txd6, rxd6 nscin6 nscout6 lad[3:0] lframe# ldrq# pci_reset# nio_pme nio_smi nmtr0, ntrk0, nindex nwgate, nhdsel, drvden0*, nwrtprt, ndir, nstep, ndskchg, nds0, nrdata, nwdata gp10-17 gp21,22, gp27, gp30-34, gp36-37, gp40, gp42, gp44-47, gp50-57, gp60-67 sch3116 only sch3114, sch3116 only sch3112, sch3114 only nfprst pwrgd_ps pwrgd_out reset generation watchdog timer n t h r e m t r i p
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 40 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 41 revision 0.4 (06-03-05) datasheet chapter 4 power functionality thesch311x has five power planes: vcc, hvtr, vref, vtr, and vbat. 4.1 vcc power the sch311x is a 3.3 volt part. the vcc supply is 3.3 volts (nominal). vcc is the main power supply for the super i/o block. see section 28.2, "dc electrical characteristics," on page 357 . 4.2 hvtr power the sch311x is family of 3.3 volt devices. the hvtr supply is 3.3 volts (nominal). hvtr is a dedicated power supply for the hardware monitoring block. hvtr is connected to the vtr suspend well. see section 28.2, "dc electrical characteristics," on page 357 . note: the hardware monitoring logic is powered by hvtr, but only operational when vcc is on. the hardware monitoring block is connected to the suspend well to retain the programmed configuration through a sleep cycle. 4.3 3 volt operation / 5 volt tolerance the sch311x is a 3.3-volt part. it is intended sole ly for 3.3v applications. non-lpc bus pins are 5v tolerant; that is, the operating input voltage is 5.5v max, and the i/o buffer output pads are backdrive protected (they do not impose a load on any external vcc powered circuitry). the 5v tolerant pins are applicable to the super i/o block only. the lpc interface pins are 3.3 v only. these signa ls meet pci dc specifications for 3.3v signaling. these pins are: lad[3:0] lframe# ldrq# the input voltage for all other pins is 5.5v max. these pins include all non-lpc bus pins and the following pins in the super i/o block: pci_reset# pci_clk ser_irq nio_pme the hardware monitoring block digital pins are 3.3v only. 4.4 vtr support the sch311x requires a trickle supply (vtr) to provide sleep current for the programmable wake-up events in the pme interface when vcc is removed. the vtr supply is 3.3 volts (nominal). see chapter 28, "operational description," on page 357 . the maximum vtr current that is required depends on the functions that are used in the part. see chapter 28, "operational description," on page 357 . if the sch311x is not intended to provide wake-up capabilities on standby current, vtr can be connected to vcc. vtr powers the ir interface, the pme configuration registers, and the pme interface. the vtr pin generates a vtr power-on-reset signal to initialize these components. if vtr is to be used for programmable wake-up events when vcc is removed, vtr must be at its full
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 42 smsc sch311x datasheet minimum potential at least 10 ms before vcc b egins a power-on cycle. note that under all circumstances, the hardware monitoring hvtr must be driven as the same source as vtr. 4.4.1 trickle power functionality when the sch311x is running under vtr only (vcc removed), pme wakeup events are active and (if enabled) able to assert the nio_pme pin active low. (see pme_sts1.) the following requirements apply to all i/o pins that are specified to be 5 volt tolerant. i/o buffers that are wake-up event compatible are powered by vcc. under vtr power (vcc=0), these pins may only be configured as inputs. these pins have input buffers into the wakeup logic that are powered by vtr. i/o buffers that may be configured as either push-pull or open drain under vtr power (vcc=0), are powered by vtr. this means, at a minimum, th ey will source their specified current from vtr even when vcc is present. the gpios that are used for pme wakeup as in put are gp21-gp22, gp27, gp32, gp33, gp50-gp57, gp60, gp61 (see pme_sts1.)these gpios functi on as follows (with the exception of gp60 and gp61 - see below): buffers are powered by vcc, but in the absence of vcc they are backdrive protected (they do not impose a load on any external vtr powered circuitry). they are wakeup compatible as inputs under vtr power. these pins have input buffers into the wakeup logic that are powered by vtr. all gpios listed above are pme wakeup as a gpio (or alternate function). gp32 and gp33 revert to their non-inverting gpio in put function when vcc is removed from the part. the other gpios function as follows: gp36, gp37 and gp40: buffers are powered by vcc. in the absence of vc c they are backdrive protected. these pins do not have input buffers into the wakeup logic that are powered by vtr, and are not used for wakeup. gp42, gp60 and gp61: buffers powered by vtr. gp42 are the nio_pme pin which is active under vtr. gp60 and gp61 have led as the alternate function and the logic is able to control the pin under vtr. the following list summarizes the blocks, registers and pins that are powered by vtr. pme interface block pme runtime register block (includes all pme, smi, gpio, fan and other miscellaneous registers) digital logic in the hardware monitoring block ?wake on specific key? logic led control logic watchdog timer power recovery logic pins for pme wakeup: gp42/nio_pme (output, buffer powered by vtr) clocki32 (input, buffer powered by vtr) nri1 (input) gp50/nri2 (input) gp52/rxd2(irrx) (input) kdat/gp21 (input) mdat/gp32 (input)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 43 revision 0.4 (06-03-05) datasheet gpios (gp21-gp22, gp27, gp32, gp33, gp50-gp57, gp60, gp61) ? all input-only except gp60, gp61. see below. other pins gp60/led1 (output, buffer powered by vtr) gp61/led2 (output, buffer powered by vtr) nrsmrst pwrgd_ps pb_in# pb_out# ps_on# nfprst slp_sx# pwrgd_out 4.5 vbat support vbat is a battery generated power supply that is needed to support the power recovery logic. the power recovery logic is used to restore power to the syst em in the event of a power failure. power may be returned to the system by a keyboard power button, th e main power button, or by the power recovery logic following an unexpected power failure. the vbat supply is 3.0 volts (nominal). see chapter 28, "operational description," on page 357 . the following runtime registers are powered by vbat: bank 2 of the runtime register block used for the 32kbyte security key register pme_en7 at offset 10h pwr_rec register at offset 49h ps_on register at offset 4ah ps_on previous state register at offset 53h dblclick register at offset 5bh keyboard scan code ? make byte 1 at offset 5fh keyboard scan code ? make byte 2 at offset 60h keyboard scan code ? break byte 1 at offset 61h keyboard scan code ? break byte 2 at offset 62h keyboard scan code ? break byte 3 at offset 63h keyboard pwrbtn/spekey at offset 64h note: all vbat powered pins and registers are powered by vtr when vtr power is on and are battery backed-up when vtr is removed. 4.6 32.768 khz trickle clock input the sch311x utilizes a 32.768 khz trickle input to supply a clock signal for the wdt, led blink, power recovery logic, and wake on specific key function. indication of 32khz clock there is a bit to indicate whether or not the 32khz clock input is connected to the sch311x. this bit is located at bit 0 of the clocki32 register at 0xf0 in logical device a. this register is powered by vtr and reset on a vtr por. bit[0] (clk32_prsn) is defined as follows:
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 44 smsc sch311x datasheet 0=32khz clock is connected to the clki32 pin (default) 1=32khz clock is not connected to the clki32 pin (pin is grounded). bit 0 controls the source of the 32khz (nominal) clock for the led blink logic and the ?wake on specific key? logic. when the external 32khz clock is connected, that will be the source for the fan, led and ?wake on specific key? logic. when the external 32 khz clock is not connected, an internal 32khz clock source will be derived from the 14mhz clock fo r the led and ?wake on specific key? logic. the following functions will not work under vtr power (vcc removed) if the external 32khz clock is not connected. these functions will work under vcc power even if the external 32 khz clock is not connected. wake on specific key led blink power recovery logic wdt front panel reset with input debounce, power supply gate, and cpu powergood signal generation 4.7 super i/o functions the maximum vtr current, i tr , is given with all outputs open (not loaded), and all inputs in a fixed state (i.e., 0v or 3.3v). the total maximum current for the part is the unloaded value plus the maximum current sourced by the pin that is driven by vtr. the super i/o pins that are powered by vtr are as follows: gp42/nio_pme, gp60/led1, gp61/led2, pwrgd_out, and clki32. these pins, if configured as push-pull outputs, will source a minimum of 6ma at 2.4v when driving. the maximum vcc current, i cc , is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0v or 3.3v). the maximum vbat current, i bat , is given with all outputs open (not loaded) and all inputs in a fixed state (i.e., 0v or 3.3v). 4.8 power management events (pme/sci) the sch311x offers support for power management events (pmes), also referred to as system control interrupt (sci) events. the terms pme and sci are used synonymously throughout this document to refer to the indication of an event to the chipset via the assertion of the nio_pme output signal. see the chapter 15, "pme support," on page 171 section.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 45 revision 0.4 (06-03-05) datasheet chapter 5 sio overview the sch311x is a super i/o device with hardwar e monitoring. the super i/o features are implemented as logical devices accessible through the lpc interf ace. the super i/o blocks are powered by vcc, vtr, or vbat. the hardware monitoring block is powered by hvtr and is accessible via the lpc interface. the followi ng chapters define each of the functional blocks implemented in the sch311x, their corresponding registers, and physical characteristics. this chapter offers an intr oduction into the super i/ o functional blocks, regi sters and host interface. details regarding the hardware monitoring block are defined in later chapters. the block diagram in pme_sts1 further details the layout of the device. note that the super i/o registers are implemented as typical plug-and-play components. 5.1 super i/o registers the address map, shown below in ta b l e 5 . 1 shows the addresses of the different blocks of the super i/o immediately after power up. the base addresses of all the super i/o logical blocks, including the configuration register block, can be moved or relocated via the configuration registers. note: some addresses are used to access more than one register. 5.2 host processor interface (lpc) the host processor communicates with the super i/o features in the sch311x through a series of read/write registers via the lpc interface. the port addresses for these registers are shown in table 5.1, "super i/o block addresses" . register access is accompli shed through i/o cycles or dma transfers. all registers are 8 bits wide. table 5.1 super i/o block addresses address block name logical device notes base+(0-5) and +(7) floppy disk 0 na reserved 1 ( note 5.5 ) na reserved 2 ( note 5.5 ) base+(0-3) base+(0-7) base+(0-3), +(400-402) base+(0-7), +(400-402) parallel port spp epp ecp ecp+epp+spp 3 base+(0-7) serial port com 1 4 base+(0-7) serial port com 2 5 na reserved 6 60, 64 kybd 7 na reserved 8,9 base1 + (0-7f) base2 + (0-1f) runtime registers security key registers a( note 5.2 ) base+(0-7) serial port com 3 b ( note 5.3 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 46 smsc sch311x datasheet note 5.1 refer to the configuration register descriptions for setting the base address. note 5.2 logical device a is referred to as the runtime register block at base1 or pme block and may be used interchangeably throughout this document. note 5.3 reserved in sch3112 device note 5.4 reserved in sch3114 device note 5.5 na = not applicable base+(0-7) serial port com 4 c note 5.3 base+(0-7) serial port com 5 d note 5.3 , note 5.4 base+(0-7) serial port com 6 e note 5.3 , note 5.4 na reserved f base + (0-1) configuration ( note 5.1 ) table 5.1 super i/o block addresses (continued) address block name logical device notes
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 47 revision 0.4 (06-03-05) datasheet chapter 6 lpc interface 6.1 lpc interface signal definition the signals implemented for the lpc bus interface are described in the tables below. lpc bus signals use pci 33mhz electrical signal characteristics. 6.1.1 lpc required signals 6.1.2 lpc optional signals 6.2 supported lpc cycles ta b l e 6 . 1 summarizes the cycle types are supported by the sch311x. all other cycle types are ignored. signal name type description lad[3:0] i/o lpc address/data bus. multiplexed command, address and data bus. lframe# input frame signal. indicates start of new cycle and termination of broken cycle pci_reset# input pci reset. used as lpc interface re set. same functionality as rst_drv but active low 3.3v. pci_clk input pci clock. signal name type description comment ldrq# output encoded dma/bus master request for the lpc interface. implemented ser_irq i/o serial irq. implemented clkrun# od clock run not implemented nio_pme od same as the pme# or power mgt event signal. allows the sch311x to request wakeup in s3 and below. implemented lpcpd# i power down - indicates that the device should prepare for lpc i/f shutdown not implemented lsmi# od only need for smi# generation on i/o instruction for retry. not implemented table 6.1 supported lpc cycles cycle type transfer size comment i/o write 1 byte supported i/o read 1 byte supported memory write 1 byte not supported memory read 1 byte not supported
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 48 smsc sch311x datasheet 6.3 device specific information the lpc interface conforms to the ?low pin count (lpc) interface specification? . the following section will review any implementation specific information for this device. 6.3.1 sync protocol the sync pattern is used to add wait states. for read cycles , the sch311x immediately drives the sync pattern upon recognizing the cycle. the host immediately drives the sync pattern for write cycles. if the sch311x needs to assert wait states, it does so by driving 0101 or 0110 on lad[3:0] until it is ready, at which point it will drive 0000 or 1001. the sch311x will choose to assert 0101 or 0110, but not switch between the two patterns. the data (or wait state sync) will immediately follow the 0000 or 1001 value. the sync value of 0101 is intended to be used for normal wait states, wherein the cycle will complete within a few clocks. the sch311x uses a sync of 0101 for all wait states in a dma transfer. the sync value of 0110 is intended to be used where the number of wait states is large. this is provided for epp cycles, where the number of wait states could be quite large (>1 microsecond). however, the sch311x uses a sync of 0110 for all wait states in an i/o transfer. the sync value is driven within 3 clocks. dma write 1 byte supported dma write 2 byte supported dma write 4 byte not supported dma read 1 byte supported dma read 2 byte supported dma read 4 byte not supported bus master memory write 1 byte not supported bus master memory write 2 byte not supported bus master memory write 4 byte not supported bus master memory read 1 byte not supported bus master memory read 2 byte not supported bus master memory read 4 byte not supported bus master i/o write 1 byte not supported bus master i/o write 2 byte not supported bus master i/o write 4 byte not supported bus master i/o read 1 byte not supported bus master i/o read 2 byte not supported bus master i/o read 4 byte not supported table 6.1 supported lpc cycles (continued) cycle type transfer size comment
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 49 revision 0.4 (06-03-05) datasheet 6.3.2 reset policy the following rules govern the reset policy: when pci_reset# goes inactive (high), the pc i clock is assumed to have been running for 100usec prior to the removal of the reset signal, so that everything is stable. this is the same reset active time after clock is stable that is used for the pci bus. when pci_reset# goes active (low): 1. the host drives the lframe# signal high, trista tes the lad[3:0] signals, and ignores the ldrq# signal. 2. the sch311x ignores lframe#, tristates the lad[ 3:0] pins and drives the ldrq# signal inactive (high).
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 50 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 51 revision 0.4 (06-03-05) datasheet chapter 7 floppy disk controller the floppy disk controller (fdc) provides the interface between a host microprocessor and the floppy disk drives. the fdc integrates the functions of the formatter/controller, digital data separator, write precompensation and data rate selection logic for an ibm xt/at compatible fdc. the true cmos 765b core guarantees 100% ibm pc xt/at compatibility in addition to providing data overflow and underflow protection. sch311x suppor ts a single floppy disk drive. the fdc is compatible to the 82077aa using smsc?s proprietary floppy disk controller core. 7.1 fdc internal registers the floppy disk controller contains eight internal registers which facilitate the interfacing between the host microprocessor and the disk drive. table 7.1 shows the addresses required to access these registers. registers other than the ones shown are not supported. the rest of the description assumes that the primary addresses have been selected. (shown with base addresses of 3f0 and 370) 7.1.1 status register a (sra) address 3f0 read only this register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in ps/2 and model 30 modes. the sra can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 ? d7 are held in a high impedance state for a read of address 3f0. ps/2 mode table 7.1 status, data and control registers primary address secondary address r/w register 3f0 3f1 3f2 3f3 3f4 3f4 3f5 3f6 3f7 3f7 370 371 372 373 374 374 375 376 377 377 r r r/w r/w r w r/w r w status register a (sra) status register b (srb) digital output register (dor) tape drive register (tdr) main status register (msr) data rate select register (dsr) data (fifo) reserved digital input register (dir) configuration control register (ccr) 7 6543210 int pending ndrv2 step ntrk0 hdsel nindx nwp dir reset cond. 0 1 0 n/a 0 n/a n/a 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 52 smsc sch311x datasheet bit 0 direction active high status indicating the direction of head movement. a logic ?1? indicates inward direction; a logic ?0? indicates outward direction. bit 1 nwrite protect active low status of the write protect disk interface input. a logic ?0? indicates that the disk is write protected. bit 2 nindex active low status of the index disk interface input. bit 3 head select active high status of the hdsel disk interface input. a logic ?1? selects side 1 and a logic ?0? selects side 0. bit 4 ntrack 0 active low status of the trk0 disk interface input. bit 5 step active high status of the step output disk interface output pin. bit 6 ndrv2 this function is not supported. this bit is always read as ?1?. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt output. 7.1.2 ps/2 model 30 mode bit 0 direction active low status indicating the direction of head movement. a logic ?0? indicates inward direction; a logic ?1? indicates outward direction. bit 1 write protect active high status of the write protect disk interface input. a logic ?1? indicates that the disk is write protected. bit 2 index active high status of the index disk interface input. bit 3 head select active low status of the hdsel disk interface input. a logic ?0? selects side 1 and a logic ?1? selects side 0. 7 6543 210 int pending drq step f/f trk0 nhdsel indx wp ndir reset cond. 0 0 0 n/a 1 n/a n/a 1
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 53 revision 0.4 (06-03-05) datasheet bit 4 track 0 active high status of the trk0 disk interface input. bit 5 step active high status of the latched step disk interface output pin. this bit is latched with the step output going active, and is cleared with a read from the dir register, or with a hardware or software reset. bit 6 dma request active high status of the dma request pending. bit 7 interrupt pending active high bit indicating the state of the floppy disk interrupt. status register b (srb) address 3f1 read only this register is read-only and monitors the state of several disk interface pins in ps/2 and model 30 modes. the srb can be accessed at any time when in ps/2 mode. in the pc/at mode the data bus pins d0 ? d7 are held in a high impedance state for a read of address 3f1. ps/2 mode bit 0 motor enable 0 active high status of the mtr0 disk interface output pin. this bit is low after a hardware reset and unaffected by a software reset. bit 1 reserved reserved will return a zero (0) when read. this bit is low after a hardware reset and unaffected by a software reset. bit 2 write gate active high status of the wgate disk interface output. bit 3 read data toggle every inactive edge of the rdata input causes this bit to change state. bit 4 write data toggle every inactive edge of the wdata input causes this bit to change state. bit 5 drive select 0 reflects the status of the drive select 0 bit of th e dor (address 3f2 bit 0). this bit is cleared after a hardware reset and it is unaffected by a software reset. 7 6 54321 0 reserved reserved drive sel0 wdata toggle rdata toggle wgate reserved mot en0 reset cond. 1 1 00000 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 54 smsc sch311x datasheet bit 6 reserved always read as a logic ?1?. bit 7 reserved always read as a logic ?1?. ps/2 model 30 mode bit 0 ndrive select 2 the ds2 disk interface is not supported. bit 1 ndrive select 3 the ds3 disk interface is not supported. bit 2 write gate active high status of the latched wgate output signal. this bit is latched by the active going edge of wgate and is cleared by the read of the dir register. bit 3 read data active high status of the latched rdata output signal. this bit is latched by the inactive going edge of rdata and is cleared by the read of the dir register. bit 4 write data active high status of the latched wdata output signal. this bit is latched by the inactive going edge of wdata and is cleared by the read of the dir register. this bit is not gated with wgate. bit 5 ndrive select 0 active low status of the ds0 disk interface output. bit 6 ndrive select 1 the ds 1 disk interface is not supported. bit 7 ndrv2 active low status of the drv2 disk interface input. note: this function is not supported. digital output register (dor) address 3f2 read/write the dor controls the drive select and motor enables of the disk interface outputs. it also contains the enable for the dma logic and a software reset bit. the contents of the dor are unaffected by a software reset. the dor can be written to at any time. 76543210 ndrv2 nds1 nds0 wdata f/f rdata f/f wgate f/f nds3 nds2 reset cond. n/a1 100011
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 55 revision 0.4 (06-03-05) datasheet bit 0 and 1 drive select these two bits are binary encoded for the drive sele cts, thereby allowing only one drive to be selected at one time. for proper device operation, they must be programmed to 0b00. bit 2 nreset a logic ?0? written to this bit resets the floppy disk controller. this reset will remain active until a logic ?1? is written to this bit. this software reset d oes not affect the dsr and ccr registers, nor does it affect the other bits of the dor register. the mi nimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. bit 3 dmaen pc/at and model 30 mode: writing this bit to logic ?1? will enable the dma and interrupt functions. this bit being a logic ?0? will disable the dma and interrupt functions. this bit is a logic ?0? after a reset and in these modes. ps/2 mode: in this mode the dma and interrupt functions are always enabled. during a reset, this bit will be cleared to a logic ?0?. bit 4 motor enable 0 this bit controls the mtr0 disk interface output. a logic ?1? in this bit will cause the output pin to go active. bit 5 motor enable 1 the mtr1 disk interface output is not support in the lpc$&m262. for proper device operation this bit must be programmed with a zero (0). 76543210 mot en3 mot en2 mot en1 mot en0 dmaen nreset drive sel1 drive sel0 reset cond. 00000000 drive dor value 01ch table 7.2 internal 2 drive decode ? normal digital output register drive select outputs (active low) motor on outputs (active low) bit 4bit1bit 0 nds0 nmtr0 100 0 nbit 4 x10 1 nbit 4 xx1 1 nbit 4
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 56 smsc sch311x datasheet bit 6 motor enable 2 the mtr2 disk interface output is not supported in the sch311x. bit 7 motor enable 3 the mtr3 disk interface output is not supported in the sch311x. tape drive register (tdr) address 3f3 read/write the tape drive register (tdr) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during init ialization. any future references to that drive automatically invokes tape support. the tdr tape select bits tdr.[1:0] determine the tape drive number. ta b l e 7 . 3 illustrates the tape select bit encoding. note that drive 0 is the boot device and cannot be assigned tape support. the remaining tape drive register bits tdr.[7:2] are tristated when read. the tdr is unaffected by a software reset. application note: note that in this device since only drive 0 is supported, the tape sel0/1 bits must be set to 0b00 for proper operation. normal floppy mode normal mode.register 3f3 contains only bits 0 and 1. when this register is read, bits 2 ? 7 are ?0? note only drive 0 is supported. enhanced floppy mode 2 (os2) register 3f3 for enhanced floppy mode 2 operation. note only drive 0 is supported table 7.3 tape select bits tape sel1 (tdr.1) tape sel0 (tdr.0) drive selected 0 0 1 1 0 1 0 1 none 1 (not supported) 2 (not supported) 3 (not supported) db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3000000tape sel1tape sel0 db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 reserved reserved drive type id floppy boot drive tape sel1 tape sel0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 57 revision 0.4 (06-03-05) datasheet note: l0-crf2-bx = logical device 0, configuration register f2, bit x. data rate select register (dsr) address 3f4 write only this register is write only. it is used to program the data rate, am ount of write precompensation, power down status, and software reset. the data rate is programmed using the configuration control register (ccr) not the dsr, for pc/at and ps/2 model 30. this register is write only. it is used to program the data rate, am ount of write precompensation, power down status, and software reset. the data rate is programmed using the configuration control register (ccr) not the dsr, for pc/at and ps/2 model 30. other applications can set the data rate in the dsr. the data rate of the floppy controller is the most recent write of either the dsr or ccr. the dsr is unaffected by a software reset. a hardware reset will set the dsr to 02h, which corresponds to the default precompensation setting and 250 kbps. bit 0 and 1 data rate select these bits control the data rate of the floppy controller. see ta b l e 7 . 6 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 through 4 precompensation select these three bits select the value of write precompensation that will be applied to the wdata output signal. ta b l e 7 . 5 shows the precompensation values for the combination of these bits settings. track 0 is the default starting track number to start pr ecompensation. this starting track number can be changed by the configure command. table 7.4 drive type id digital output register register 3f3 ? drive type id bit 1 bit 0 bit 5 bit 4 0 0 l0-crf2 ? b1 l0-crf2 ? b0 0 1 l0-crf2 ? b3 l0-crf2 ? b2 1 0 l0-crf2 ? b5 l0-crf2 ? b4 1 1 l0-crf2 ? b7 l0-crf2 ? b6 76543210 s/w reset power down 0pre- comp2 pre- comp1 pre- comp0 drate sel1 drate sel0 reset cond. 00000010
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 58 smsc sch311x datasheet bit 5 undefined should be written as a logic ?0?. bit 6 low power a logic ?1? written to this bit will put the floppy controller into manual low power mode. the floppy controller clock and data separator circuits will be turned off. the controller will come out of manual low power mode after a software reset or access to the data register or main status register. bit 7 software reset this active high bit has the same function as the dor reset (dor bit 2) except that this bit is self clearing. note: the dsr is shadowed in the floppy data rate select shadow register, located at the offset 0x1f in the runtime register blo ck separator circuits will be turn ed off. the controller will come out of manual low power. table 7.5 precompensation delays precomp 432 precompensation delay (nsec) <2mbps 2mbps 111 001 010 011 100 101 110 000 0.00 41.67 83.34 125.00 166.67 208.33 250.00 default 0 20.8 41.7 62.5 83.3 104.2 125 default default: see table 7.8 on page 59 . table 7.6 data rates drive rate data rate data rate densel drate(1) drt1 drt0 sel1 sel0 mfm fm 10 0 0 1 1 1meg --- 1 1 1 0 0 0 0 500 250 1 0 0 0 0 0 1 300 150 0 0 1 0 0 1 0 250 125 0 1 0 0 1 1 1 1meg --- 1 1 1 0 1 0 0 500 250 1 0 0 0 1 0 1 500 250 0 0 1 0 1 1 0 250 125 0 1 0 1 0 1 1 1meg --- 1 1 1 1 0 0 0 500 250 1 0 0 1 0 0 1 2meg --- 0 0 1
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 59 revision 0.4 (06-03-05) datasheet drive rate table (recommended) 00 = 360k, 1.2m, 720k, 1.44m and 2.88m vertical format 01 = 3-mode drive 10 = 2 meg tape note: the drate and densel values are mapped onto the drvden pins. main status register address 3f4 read only the main status register is a read-only register and indicates the status of the disk controller. the main status register can be read at any time. the msr indicates when the disk controller is ready to receive data via the data register. it should be read before each byte transferring to or from the data register except in dma mode. no delay is required when reading the msr after a data transfer. bit 0 drv0 busy this bit is set to 1 when a drive is in the seek portion of a command, including implied and overlapped seeks and re calibrates. 1 0 1 0 250 125 0 1 0 table 7.7 drvden mapping dt1 dt0 drvden1 (1) drvden0 (1) drive type 0 0 drate0 densel 4/2/1 mb 3.5? 2/1 mb 5.25? fdds 2/1.6/1 mb 3.5? (3-mode) 1 0 drate0 drate1 0 1 drate0 ndensel ps/2 1 1 drate1 drate0 table 7.8 default precompensation delays data rate precompensation delays 2 mbps 1 mbps 500 kbps 300 kbps 250 kbps 20.8 ns 41.67 ns 125 ns 125 ns 125 ns 76543210 rqm dio non dma cmd busy reserved reserved reserved drv0 busy table 7.6 data rates (continued) drive rate data rate data rate densel drate(1)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 60 smsc sch311x datasheet bit 1 reserved reserved - read returns 0 bit 4 command busy this bit is set to a 1 when a command is in progres s. this bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. if there is no result phase (seek, re calibrate commands), this bit is returned to a 0 after the last command byte. bit 5 non-dma reserved, read ?0?. this part does not support non-dma mode. bit 6 dio indicates the direction of a data transfer once a rqm is set. a 1 indicates a read and a 0 indicates a write is required. bit 7 rqm indicates that the host can transfer data if set to a 1. no access is permitted if set to a 0. data register (fifo) address 3f5 read/write all command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the data register. data transfers are governed by the rqm and dio bits in the main status register. the data register defaults to fifo disabled mode after any form of reset. this maintains pc/at hardware compatibility. the default values can be changed through the configure command (enable full fifo operation wi th threshold control) . the advantage of the fifo is that it allows the system a larger dma latency without causing a disk error. ta b l e 7 . 9 gives several examples of the delays with a fifo. the data is based upon the following formula: delay = fifo threshold # x data rate x 8 - 1.5 s at the start of a command, the fifo action is always disabled and command parameters must be sent based upon the rqm and dio bit settings. as the command execution phase is entered, the fifo is cleared of any data to ensure that invalid data is not transferred. an overrun or underrun will termin ate the current command and the transfer of data. disk writes will complete the current sector by generating a 00 pattern and valid crc. reads require the host to remove the remaining data so that the result phase may be entered.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 61 revision 0.4 (06-03-05) datasheet digital input register (dir) address 3f7 read only this register is read-only in all modes. pc-at mode bit 0 ? 6 undefined the data bus outputs d0 ? 6 are read as ?0?. bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see the runtime register at offset 0x1e). ps/2 mode table 7.9 fifo service delay fifo threshold examples maximum delay to servicing at 2 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 4 s - 1.5 s = 2.5 s 2 x 4 s - 1.5 s = 6.5 s 8 x 4 s - 1.5 s = 30.5 s 15 x 4 s - 1.5 s = 58.5 s fifo threshold examples maximum delay to servicing at 1 mbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 8 s - 1.5 s = 6.5 s 2 x 8 s - 1.5 s = 14.5 s 8 x 8 s - 1.5 s = 62.5 s 15 x 8 s - 1.5 s = 118.5 s fifo threshold examples maximum delay to servicing at 500 kbps data rate 1 byte 2 bytes 8 bytes 15 bytes 1 x 16 s - 1.5 s = 14.5 s 2 x 16 s - 1.5 s = 30.5 s 8 x 16 s - 1.5 s = 126.5 s 15 x 16 s - 1.5 s = 238.5 s 76543210 dsk chg 0000000 reset cond. n/a n/a n/a n/a n/a n/a n/a n/a 76543210 dsk chg 1111drate sel1 drate sel0 nhigh dens reset cond. n/a n/a n/a n/a n/a n/a n/a 1
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 62 smsc sch311x datasheet bit 0 nhigh dens this bit is low whenever the 500 kbps or 1 mbps data rates are selected, and high when 250 kbps and 300 kbps are selected. bits 1 ? 2 data rate select these bits control the data rate of the floppy controller. see table 7.6 on page 58 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bits 3 ? 6 undefined always read as a logic ?1? bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see runtime register at offset 0x1e). model 30 mode bits 0 ? 1 data rate select these bits control the data rate of the floppy controller. see ta b l e 7 . 6 for the settings corresponding to the individual data rates. the data rate select bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. bit 2 noprec this bit reflects the value of noprec bit set in the ccr register. bit 3 dmaen this bit reflects the value of dmaen bit set in the dor register bit 3. bits 4 ? 6 undefined always read as a logic ?0? bit 7 dskchg this bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value programmed in the force disk change register (see runtime register at offset 0x1e). 76543210 dsk chg 0 0 0 dmaen noprec drate sel1 drate sel0 reset cond. n/a0000010
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 63 revision 0.4 (06-03-05) datasheet 7.1.2.1 configuration c ontrol register (ccr) address 3f7 write only pc/at and ps/2 modes bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy controller. see table 7.6 on page 58 for the appropriate values. bit 2 ? 7 reserved should be set to a logical ?0? ps/2 model 30 mode bit 0 and 1 data rate select 0 and 1 these bits determine the data rate of the floppy controller. see table 7.6 on page 58 for the appropriate values. bit 2 no precompensation this bit can be set by software, but it has no functionality. it can be read by bit 2 of the dsr when in model 30 register mode. unaffected by software reset. bit 3 ? 7 reserved should be set to a logical ?0? table 7.7 on page 59 shows the state of the densel pin. the densel pin is set high after a hardware reset and is unaffected by the dor and the dsr resets. 7.1.3 status register encoding during the result phase of certain commands, the data register contains data bytes that give the status of the command just executed. 76543210 000000drate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0 76543210 00000noprecdrate sel1 drate sel0 reset cond. n/a n/a n/a n/a n/a n/a 1 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 64 smsc sch311x datasheet table 7.10 status register 0 bit no. symbol name description 7,6 ic interrupt code 00 - normal termination of command. the specified command was properly executed and completed without error. 01 - abnormal termination of command. command execution was started, but was not successfully completed. 10 - invalid command. the requested command could not be executed. 11 - abnormal termination caused by polling. 5 se seek end the fdc completed a seek, relative seek or recalibrate command (used during a sense interrupt command). 4 ec equipment check the trk0 pin failed to become a "1" after: 1. 80 step pulses in the recalibrate command. 2. the relative seek command caused the fdc to step outward beyond track 0. 3 unused. this bit is always "0". 2 h head address the current head address. 1,0 ds1,0 drive select the current selected drive. table 7.11 status register 1 bit no. symbol name description 7 en end of cylinder the fdc tried to access a sector beyond the final sector of the track (255d). will be set if tc is not issued after read or write data command. 6 unused. this bit is always "0". 5 de data error the fdc detected a crc error in either the id field or the data field of a sector. 4 or overrun/ underrun becomes set if the fdc does not receive cpu or dma service within the required time interval, resulting in data overrun or underrun. 3 unused. this bit is always "0". 2 nd no data any one of the following: 1. read data, read deleted data command - the fdc did not find the specified sector. 2. read id command - the fdc cannot read the id field without an error. 3. read a track command - the fdc cannot find the proper sector sequence. 1 nw not writable wp pin became a "1" while the fdc is executing a write data, write deleted data, or format a track command.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 65 revision 0.4 (06-03-05) datasheet 0 ma missing address mark any one of the following: 1. the fdc did not detect an id address mark at the specified track after encountering the index pulse from the nindex pin twice. 2. the fdc cannot detect a data address mark or a deleted data address mark on the specified track. table 7.12 status register 2 bit no. symbol name description 7 unused. this bit is always "0". 6 cm control mark any one of the following: read data command - the fdc encountered a deleted data address mark. read deleted data command - the fdc encountered a data address mark. 5 dd data error in data field the fdc detected a crc error in the data field. 4wcwrong cylinder the track address from the sector id field is different from the track address maintained inside the fdc. 3 unused. this bit is always "0". 2 unused. this bit is always "0". 1 bc bad cylinder the track address from the sector id field is different from the track address maintained inside the fdc and is equal to ff hex, which indicates a bad track with a hard error according to the ibm soft-sectored format. 0 md missing data address mark the fdc cannot detect a data address mark or a deleted data address mark. table 7.13 status register 3 bit no. symbol name description 7 unused. this bit is always "0". 6wpwrite protected indicates the status of the wrtprt pin. 5 unused. this bit is always "1". 4 t0 track 0 indicates the status of the trk0 pin. 3 unused. this bit is always "1". 2 hd head address indicates the status of the hdsel pin. 1,0 ds1,0 drive select indicates the status of the ds1, ds0 pins. table 7.11 status register 1 (continued) bit no. symbol name description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 66 smsc sch311x datasheet reset there are three sources of system reset on the fdc: the pci_reset# pi n, a reset generated via a bit in the dor, and a reset generated via a bit in the dsr. at power on, a power on reset initializes the fdc. all resets take the fdc out of the power down state. all operations are terminated upon a pci_reset#, and the fdc enters an idle state. a reset while a disk write is in progress will corrupt the data and crc. on exiting the reset state, various internal regi sters are cleared, including the configure command information, and the fdc waits for a new command. drive polling will start unless disabled by a new configure command. pci_reset# pin (hardware reset) the pci_reset# pin is a global reset and clears all registers except those programmed by the specify command. the dor reset bit is enabled and must be cleared by the host to exit the reset state. dor reset vs. dsr reset (software reset) these two resets are functionally the same. both will reset the fdc core, which affects drive status information and the fifo circuits. the dsr reset clears itself automatica lly while the dor reset requires the host to manually clear it. dor rese t has precedence over the dsr reset. the dor reset is set automatically upon a pin reset. the user must manually clear this reset bit in the dor to exit the reset state. modes of operation the fdc has three modes of operation, pc/at mode, ps/2 mode and model 30 mode. these are determined by the state of the interface mode bits in ld0-crf0[3,2]. pc/at mode the pc/at register set is enabled, the dma enable bit of the dor becomes valid (controls the interrupt and dma functions), and densel is an active high signal. ps/2 mode this mode supports the ps/2 models 50/60/80 configuration and register set. the dma bit of the dor becomes a ?don?t care?. the dma and interrupt functions are always enabled, and densel is active low. model 30 mode this mode supports ps/2 model 30 configuration and register set. the dma enable bit of the dor becomes valid (controls the interrupt and dma functions), and densel is active low. dma transfers dma transfers are enabled with the specify command and are initiated by the fdc by activating a dma request cycle. dma read, write and verify cycl es are supported. the fdc supports two dma transfer modes: single transfer and burst transfer. burst mode is enabled via logical device 0- crf0-bit[1] (ld0-crf0[1]). controller phases for simplicity, command handling in the fdc can be divided into three phases: command, execution, and result. each phase is described in the following sections. command phase after a reset, the fdc enters the command phase and is ready to accept a command from the host. for each of the commands, a defined set of command code bytes and parameter bytes has to be written to the fdc before the command phase is complete. (please refer to table 7.14 on page 68 for the command set descriptions). these bytes of data must be transferred in the order prescribed.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 67 revision 0.4 (06-03-05) datasheet before writing to the fdc, the host must examine the rqm and dio bits of the main status register. rqm and dio must be equal to ?1? and ?0? respectively before command bytes may be written. rqm is set false by the fdc after each write cycle until the received byte is processed. the fdc asserts rqm again to request each parameter byte of the command unless an illegal command condition is detected. after the last parameter byte is received, rqm remains ?0? and the fdc automatically enters the next phase as defined by the command definition. the fifo is disabled during the command phase to provide for the proper handling of the ?invalid command? condition. execution phase all data transfers to or from the fdc occur duri ng the execution phase, which can proceed in dma mode as indicated in the specify command. after a reset, the fifo is disabled. each data byte is transferred by a read/write or dma cycle depending on the dma mode. the configure command can enable the fifo and set the fifo threshold value. the following paragraphs detail the operation of the fifo automatic direction control. in these descriptions, is defined as the number of bytes available to the fdc when service is requested from the host and ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host reads (writes) from (to) the fifo until empty (full), then the transfer request goes inactive. the host must be very responsive to the service request. this is the desired case for use with a ?fast? system. a high value of threshold (i.e. 12) is used with a ?sluggish? system by affo rding a long latency period after a service request, but results in more frequent service requests. non-dma mode ? transfers from the fifo to the host this part does not support non-dma mode. non-dma mode ? transfers from the host to the fifo this part does not support non-dma mode. dma mode ? transfers from the fifo to the host the fdc generates a dma request cycle when the fifo contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in t he fifo. the dma controller must respond to the request by reading data from the fifo. the fdc will deactivate the dma request when the fifo becomes empty by generating the proper sync for the data transfer. dma mode ? transfers from the host to the fifo the fdc generates a dma request cycle when enter ing the execution phase of the data transfer commands. the dma controller must respond by placing data in the fifo. the dma request remains active until the fifo becomes full. the dma r equest cycle is reasserted when the fifo has bytes remaining in th e fifo. the fdc will terminate th e dma cycle after a tc, indicating that no more data is required. data transfer termination the fdc supports terminal count explicitly th rough the tc pin and implicitly through the underrun/overrun and end-of-track (eot) functions. for full sector transfers, the eot parameter can define the last sector to be transferred in a single or multi-sector transfer. if the last sector to be transferred is a partial sector, the host can stop transferring the data in mid- sector, and the fdc will continue to complete the sector as if a tc cycle was received. the only difference between these implicit functions and tc cycle is that they return ?abnormal termination? result status. such status indications can be ignored if they were expected.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 68 smsc sch311x datasheet note that when the host is sending data to the fi fo of the fdc, the internal sector count will be complete when the fdc reads the last byte from its side of the fifo. there may be a delay in the removal of the transfer request signal of up to the time taken for the fdc to read the last 16 bytes from the fifo. the host must tolerate this delay. result phase the generation of the interrupt determines the beginning of the result phase. for each of the commands, a defined set of result bytes has to be read from the fdc before the result phase is complete. these bytes of data must be read out for another command to start. rqm and dio must both equal ?1? before the result bytes may be read. after all the result bytes have been read, the rqm and dio bits switch to ?1? and ?0? respectively, and the cb bit is cleared, indicating that the fdc is ready to accept the next command. command set/descriptions commands can be written whenever the fdc is in the command phase. each command has a unique set of needed parameters and status results. the fdc checks to see that the first byte is a valid command and, if valid, proceeds with the command. if it is invalid, an interrupt is issued. the user sends a sense interrupt status command which returns an invalid command error. refer to table 7.14 for explanations of the various symbols used. ta b l e 7 . 1 5 lists the required parameters and the results associated with each command that the fdc is capable of performing. table 7.14 description of command symbols symbol name description c cylinder address the currently selected address; 0 to 255. d data pattern the pattern to be written in each sector data field during formatting. d0, d1 drive select 0-1 designates which drives ar e perpendicular drives on the perpendicular mode command. a ?1? indicates a perpendicular drive. dir direction control if this bit is 0, then the head will step out from the spindle during a relative seek. if set to a 1, the head will step in toward the spindle. ds0, ds1 disk drive select 00 drive 0 selected 01 not allowed 1x not allowed dtl special sector size by setting n to zero (00), dtl may be used to control the number of bytes transferred in disk read/write commands. the sector size (n = 0) is set to 128. if the actual sector (on the diskette) is larger than dtl, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. the crc check code is calculated with the actual sector. when n is not zero, dtl has no meaning and should be set to ff hex. ec enable count when this bit is ?1? the ?dtl? parameter of the verify command becomes sc (number of sectors per track). efifo enable fifo this active low bit when a 0, enables the fifo. a ?1? disables the fifo (default). eis enable implied seek when set, a seek operation will be performed before executing any read or write command that requires the c parameter in the command phase. a ?0? disables the implied seek. eot end of track the final sector number of the current track. gap alters gap 2 length when using perpendicular mode. gpl gap length the gap 3 size. (gap 3 is the space between sectors excluding the vco synchronization field).
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 69 revision 0.4 (06-03-05) datasheet h/hds head address selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector id field. hlt head load time the time interval that fdc waits after loading the head and before initializing a read or write operation. refer to the specify command for actual delays. hut head unload time the time interval from the end of the execution phase (of a read or write command) until the head is unloaded. refer to the specify command for actual delays. lock lock defines whether efifo, fifothr, and pretrk parameters of the configure command can be reset to their default values by a ?software reset?. (a reset caused by writing to t he appropriate bits of either the dsr or dor) mfm mfm/fm mode selector a one selects the double density (mfm) mode. a zero selects single density (fm) mode. mt multi-track selector when set, this flag selects the multi-track operating mode. in this mode, the fdc treats a complete cylinder under head 0 and 1 as a single track. the fdc operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. with this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the fdc finishes operating on the last sector under head 0. nsector size code this specifies the number of bytes in a sector. if this parameter is "00", then the sector size is 128 bytes. the number of bytes transferred is determined by the dtl parameter. otherwise the sector size is (2 raised to the "n'th" power) times 128. all values up to "07" hex are allowable. "07"h would equal a sector size of 16k. it is the user's responsibility to not select combinations that are not possible with the drive. n sector size 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes ? ? 07 16k bytes ncn new cylinder number the desired cylinder number. nd non-dma mode flag write ?0?. this part does not support non-dma mode. ow overwrite the bits d0-d3 of the perpendicular mode command can only be modified if ow is set to 1. ow id defined in the lock command. pcn present cylinder number the current position of the head at the completion of sense interrupt status command. poll polling disable when set, the internal polling routine is disabled. when clear, polling is enabled. pretrk precompensatio n start track number programmable from track 00 to ffh. r sector address the sector number to be read or written. in multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. rcn relative cylinder number relative cylinder offset from present cy linder as used by the relative seek command. sc number of sectors per track the number of sectors per track to be initialized by the format command. the number of sectors per track to be verified during a verify command when ec is set. table 7.14 description of command symbols (continued) symbol name description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 70 smsc sch311x datasheet sk skip flag when set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of read data. if read deleted is executed, only sectors with a deleted address mark will be accessed. when set to ?0?, the sector is read or written the same as the read and write commands. srt step rate interval the time interval between step pulses issued by the fdc. programmable from 0.5 to 8 milliseconds in increments of 0.5 ms at the 1 mbit data rate. refer to the specify command for actual delays. st0 st1 st2 st3 status 0 status 1 status 2 status 3 registers within the fdc which store status information after a command has been executed. this status information is available to the host during the result phase after command execution. wgate write gate alters timing of we to allow for pre-erase loads in perpendicular drives. table 7.14 description of command symbols (continued) symbol name description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 71 revision 0.4 (06-03-05) datasheet 7.1.4 instruction set table 7.15 instruction set read data phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w mt mfm sk 0 0 1 1 0 command codes w 0 0 0 0 0 hds ds 1 ds 0 w c sector id information prior to command execution. wh wr wn weot wgpl wdtl execution data transfer between the fdd and system. result r st0 status information after command execution. rst1 rst2 r c sector id information after command execution. rh rr rn
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 72 smsc sch311x datasheet read deleted data phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w mt mfm sk 0 1 1 0 0 command codes w 0 0 0 00hdsds1ds0 w c sector id information prior to command execution. wh wr wn weot wgpl wdtl execution data transfer between the fdd and system. result r st0 status information after command execution. rst1 rst2 r c sector id information after command execution. rh rr rn
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 73 revision 0.4 (06-03-05) datasheet write data phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w mt mfm 0 0 0 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. wh wr wn weot wgpl wdtl execution data transfer between the fdd and system. result r st0 status information after command execution. rst1 rst2 r c sector id information after command execution. rh rr rn
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 74 smsc sch311x datasheet write deleted data phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w mt mfm 0 0 1 0 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. wh wr wn weot wgpl wdtl execution data transfer between the fdd and system. result r st0 status information after command execution. rst1 rst2 r c sector id information after command execution. rh rr rn
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 75 revision 0.4 (06-03-05) datasheet read a track phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w 0 mfm 0 0 0 0 1 0 command codes w 0 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. wh wr wn weot wgpl wdtl execution data transfer between the fdd and system. fdc reads all of cylinders? contents from index hole to eot. result r st0 status information after command execution. rst1 rst2 r c sector id information after command execution. rh rr rn
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 76 smsc sch311x datasheet read a track phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w mt mfm sk 1 0 1 1 0 command codes w ec 0 0 0 0 hds ds1 ds0 w c sector id information prior to command execution. wh wr wn weot wgpl wdtl/sc execution no data transfer takes place. result r st0 status information after command execution. rst1 rst2 r c sector id information after command execution. rh rr rn version phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 commandw 00 0100 0 0 comm and code result r 10 0100 0 0 e nhanced controller
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 77 revision 0.4 (06-03-05) datasheet format a track phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w 0 mfm 0 0 1 1 0 1 command codes w 0 0 0 0 0 hds ds1 ds0 w n bytes/sector w sc sectors/cylinder wgplgap 3 w d filler byte execution for each sector repeat: w c input sector parameters wh wr wn fdc formats an entire cylinder result r st0 status information after command execution rst1 rst2 r undefined r undefined r undefined r undefined recalibrate phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 commandw 0000011 1 command codes w 000000ds1ds0 execution head retracted to track 0 interrupt.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 78 smsc sch311x datasheet sense interrupt status phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 commandw 00001000command codes result r st0 status information at the end of each seek operation. rpcn specify phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 commandw 00000011 command codes wsrt hut whltnd sense drive status data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks commandw 000001 0 0 command codes w 00000hdsds1ds0 result r st3 status information about fdd seek phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w 0 0 0 0 1 1 1 1 command codes w 00000hdsds1ds0 w ncn execution head positioned over proper cylinder on diskette.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 79 revision 0.4 (06-03-05) datasheet configure phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w 0 0 0 1 0 0 1 1 configure information w000 0 0000 w 0 eis efifo poll fifothr execution w pretrk relative seek phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w 1 dir 0 0 1 1 1 1 w 0 0 0 0 0 hds ds1 ds0 w rcn dumpreg phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0 command w 0 0 0 0 1 1 1 0 *note: registers placed in fifo execution result r pcn-drive 0 r pcn-drive 1 r pcn-drive 2 r pcn-drive 3 rsrt hut rhltnd rsc/eot r lock 0 d3 d2 d1 d0 gap wgate r 0 eis efifo poll fifothr
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 80 smsc sch311x datasheet rpretrk read id data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 mfm 0 0 1 0 1 0 commands w 0 0 0 0 0 hds ds1 ds0 execution the first correct id information on the cylinder is stored in data register result r st0 status information after command execution. disk status after the command has completed. rst1 rst2 rc rh rr rn perpendicular mode data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w 0 001001 0 comm and codes ow 0 d3d2d1d0gap wgate dumpreg phase r/w data bus remarks d7 d6 d5 d4 d3 d2 d1 d0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 81 revision 0.4 (06-03-05) datasheet sc is returned if the last command that was issued was the format command. eot is returned if the last command was a read or write. note: these bits are used internally only. they are no t reflected in the drive select pins. it is the user?s responsibility to maintain correspondence between these bits and the drive select pins (dor). 7.1.5 data transfer commands all of the read data, write data and verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. an implied seek will be executed if the feature was enabled by the configure command. this seek is completely transparent to the user. the drive busy bit for the drive will go active in the main status register during the seek portion of the command. if the seek portion fails, it is reflected in the results status normally returned for a read/write data command. status register 0 (st0) would contain the error code and c would contain the cylinder on which the seek failed. read data a set of nine (9) bytes is required to place the fdc in the read data mode. after the read data command has been issued, the fdc loads the head (if it is in the unloaded state), waits the specified head settling time (defined in the specify command), and begins reading id address marks and id fields. when the sector address read off the diskette matches with the sector address specified in the command, the fdc reads the sector?s data field and transfers the data to the fifo. after completion of the read operation from the current sector, the sector address is incremented by one and the data from the next logical sector is read and output via the fifo. this continuous read function is called ?multi-sector read operation?. upon receipt of the tc cycle, or an implied tc (fifo overrun/underrun), the fdc stops sending data but will continue to read data from the current sector, check the crc bytes, and at the end of the sector, terminate the read data command. n determines the number of bytes per sector (see ta b l e 7 . 1 6 ). if n is set to zero, the sector size is set to 128. the dtl value determines the number of bytes to be transferred. if dtl is less than 128, the fdc transfers the specified number of bytes to the host. for reads, it continues to read the entire invalid codes data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w invalid codes invalid command codes (noop ? fdc goes into standby state) result r st0 st0 = 80h lock data bus phase r/w d7 d6 d5 d4 d3 d2 d1 d0 remarks command w lock 0 0 1 0 1 0 0 command codes result r 0 00 lock 0000
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 82 smsc sch311x datasheet 128-byte sector and checks for crc e rrors. for writes, it completes the 128-byte sector by filling in zeros. if n is not set to 00 hex, dtl should be set to ff hex and has no impact on the number of bytes transferred. the amount of data which can be handled with a single command to the fdc depends upon mt (multi- track) and n (number of bytes/sector). the multi-track function (mt) allows the fdc to r ead data from both sides of the diskette. for a particular cylinder, data will be transferred starting at sector 1, side 0 and completing the last sector of the same track at side 1. if the host terminates a read or write operation in the fdc, the id information in the result phase is dependent upon the state of the mt bit and eot byte. refer to ta b l e 7 . 1 7 . at the completion of the read data command, the head is not unloaded until after the head unload time interval (specified in the specify command) has elapsed. if the host issues another command before the head unloads, then the head settling time may be saved between subsequent reads. if the fdc detects a pulse on the nindex pin twice without finding the specified sector (meaning that the diskette?s index hole passes through index detect logic in the drive twice), the fdc sets the ic code in status register 0 to ?01? indicating abnormal termination, sets the nd bit in status register 1 to ?1? indicating a sector not found, and terminates the read data command. after reading the id and data fields in each sector, the fdc checks the crc bytes. if a crc error occurs in the id or data field, the fdc sets the ic code in status register 0 to ?01? indicating abnormal termination, sets the de bit flag in status register 1 to ?1?, sets the dd bit in status register 2 to ?1? if crc is incorrect in the id field, and terminates the read data command. table 7.18 describes the effect of the sk bit on the read data command execution and results. except where noted in table 7.18 , the c or r value of the sector address is automatically incremented (see table 7.20 on page 84 ). table 7.16 sector sizes n sector size 00 01 02 03 .. 07 128 bytes 256 bytes 512 bytes 1024 bytes ? 16 kbytes table 7.17 effects of mt and n bits mt n maximum transfer capacity final sector read from disk 0 1 0 1 0 1 1 1 2 2 3 3 256 x 26 = 6,656 256 x 52 = 13,312 512 x 15 = 7,680 512 x 30 = 15,360 1024 x 8 = 8,192 1024 x 16 = 16,384 26 at side 0 or 1 26 at side 1 15 at side 0 or 1 15 at side 1 8 at side 0 or 1 16 at side 1
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 83 revision 0.4 (06-03-05) datasheet read deleted data this command is the same as the read data command, only it operates on sectors that contain a deleted data address mark at the beginning of a data field. table 7.19 describes the effect of the sk bit on the read deleted data command execution and results. except where noted in ta b l e 7 . 1 9 , the c or r value of the sector address is automatically incremented (see table 7.20 ). read a track this command is similar to the read data command except that the entire data field is read continuously from each of the sectors of a trac k. immediately after encountering a pulse on the nindex pin, the fdc starts to read all data fields on the track as continuous blocks of data without regard to logical sector numbers. if the fdc finds an error in the id or data crc check bytes, it continues to read data from the track and sets the appropriate error bits at the end of the command. the fdc compares the id information read from each sector with the specified value in the command and sets the nd flag of status register 1 to a ?1? if there no comparison. multi-track or skip operations are not allowed with this command. the mt and sk bits (bits d7 and d5 of the first command byte respectively) should always be set to ?0?. this command terminates when the eot specified number of sectors has not been read. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the nindex pin, then it sets the ic code in status regi ster 0 to ?01? (abnormal termination), sets the ma bit in status register 1 to ?1?, and terminates the command. table 7.18 skip bit vs. read data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes yes no no yes no yes normal termination. address not incremented. next sector not searched for. normal termination. normal termination. sector not read (?skipped?). table 7.19 skip bit vs. read deleted data command sk bit value data address mark type encountered results sector read? cm bit of st2 set? description of results 0 0 1 1 normal data deleted data normal data deleted data yes yes no yes yes no yes no address not incremented. next sector not searched for. normal termination. normal termination. sector not read (?skipped?). normal termination.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 84 smsc sch311x datasheet nc: no change, the same value as the one at the beginning of command execution. lsb: least significant bit, the lsb of h is complemented. write data after the write data command has been issued, the fdc loads the head (if it is in the unloaded state), waits the specified head load time if unloaded (defined in the specify command), and begins reading id fields. when the sector address read from the di skette matches the sector address specified in the command, the fdc reads the data from the host via the fifo and writes it to the sector?s data field. after writing data into the current sector, the fdc computes the crc value and writes it into the crc field at the end of the sector transfer. the sector number stored in ?r? is incremented by one, and the fdc continues writing to the next data field. the fdc continues this ?multi-sector write operation?. upon receipt of a terminal count signal or if a fifo over/under run occurs while a data field is being written, then the remainder of the data field is filled with zeros. the fdc reads the id field of each sector and checks the crc bytes. if it detects a crc error in one of the id fields, it sets the ic code in status register 0 to ?01? (abnormal termination), sets the de bit of status register 1 to ?1?, and terminates the write data command. the write data command operates in much the same manner as the read data command. the following items are the same. please refer to the read data command for details: transfer capacity en (end of cylinder) bit nd (no data) bit head load, unload time interval id information when the host terminates the command definition of dtl when n = 0 and when n does not = 0 write deleted data this command is almost the same as the write data command except that a deleted data address mark is written at the beginning of the data field instead of the normal data address mark. this command is typically used to mark a bad sector containing an error on the floppy disk. table 7.20 result phase mt head final sector transferred to id information at result phase host c h r n 0 0 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 nc 01 nc 1 0 less than eot nc nc r + 1 nc equal to eot nc lsb 01 nc 1 less than eot nc nc r + 1 nc equal to eot c + 1 lsb 01 nc
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 85 revision 0.4 (06-03-05) datasheet verify the verify command is used to verify the data stored on a disk. this command acts exactly like a read data command except that no data is transferred to the host. data is read from the disk and crc is computed and checked against the previously-stored value. because data is not transferred to the host, the tc cycle cannot be used to terminate this command. by setting the ec bit to ?1 ?, an implicit tc will be issued to the fdc. this implic it tc will occur when the sc value has decremented to 0 (an sc value of 0 will verify 256 sectors). this command can also be terminated by setting the ec bit to ?0? and the eot value equal to the final sector to be checked. if ec is set to ?0?, dtl/sc should be programmed to 0ffh. refer to table 7.20 on page 84 and table 7.21 on page 85 for information concerning the values of mt and ec versus sc and eot value. definitions: # sectors per side = number of formatted sectors per each side of the disk. # sectors remaining = number of formatted sectors left which can be read, including side 1 of the disk if mt is set to ?1?. note: if mt is set to ?1? and the sc value is greater than the number of remaining formatted sectors on side 0, verifying will co ntinue on side 1 of the disk. format a track the format command allows an entire track to be formatted. after a pulse from the nindex pin is detected, the fdc starts writing data on the disk including gaps, address marks, id fields, and data fields per the ibm system 34 or 3740 format (mfm or fm respectively). the particular values that will be written to the gap and data field are controlled by the values programmed into n, sc, gpl, and d which are specified by the host durin g the command phase. the data field of the sector is filled with the data byte specified by d. the id field for each sector is supplied by the host; that is, four data bytes per sector are needed by the fdc for c, h, r, and n (cylinder, head, sector number and sector size respectively). table 7.21 verify command result phase mt ec sc/eot value termination result 00sc = dtl eot <= # sectors per side success termination result phase valid 00sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 0 1 sc <= # sectors remaining and eot <= # sectors per side successful termination result phase valid 0 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid 10sc = dtl eot <= # sectors per side successful termination result phase valid 10sc = dtl eot > # sectors per side unsuccessful termination result phase invalid 1 1 sc <= # sectors remaining and eot <= # sectors per side successful termination result phase valid 1 1 sc > # sectors remaining or eot > # sectors per side unsuccessful termination result phase invalid
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 86 smsc sch311x datasheet after formatting each sector, the host must send new values for c, h, r and n to the fdc for the next sector on the track. the r value (sector number) is the only value that must be changed by the host after each sector is formatted. this allows the disk to be formatted with nonsequential sector addresses (interleaving). this incrementing and formatting continues for the whole track until the fdc encounters a pulse on the nindex pin again and it terminates the command. table 7.22 on page 87 contains typical values for gap fields which are dependent upon the size of the sector and the number of sectors on each track. actual values can vary due to drive electronics. format fields system 34 (double density) format gap 4a 80x 4e syn c 12x 00 iam ga p1 50x 4e syn c 12x 00 ida m c y l h d s e c n o c r c ga p2 22x 4e syn c 12x 00 dat a am da ta c r c ga p3 gap 4b 3 x c 2 f c 3 x a 1 f e 3 x a 1 f b f 8 system 3740 (single density) format gap 4a 40x ff syn c 6x 00 iam ga p1 26x ff syn c 6x 00 ida m c y l h d s e c n o c r c ga p2 11x ff syn c 6x 00 dat a am da ta c r c ga p3 gap 4b fc fe fb or f8 perpendicular format gap 4a 80x 4e syn c 12x 00 iam ga p1 50x 4e syn c 12x 00 ida m c y l h d s e c n o c r c ga p2 41x 4e syn c 12x 00 dat a am da ta c r c ga p3 gap 4b 3 x c 2 f c 3 x a 1 f e 3 x a 1 f b f 8
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 87 revision 0.4 (06-03-05) datasheet control commands control commands differ from the other commands in that no data transfer takes place. three commands generate an interrupt when complete: read id, re calibrate, and seek. the other control commands do not generate an interrupt. read id the read id command is used to find the present position of the recording heads. the fdc stores the values from the first id field it is able to read into its registers. if the fdc does not find an id address mark on the diskette after the second occurrence of a pulse on the nindex pin, it then sets the ic code in status register 0 to ?01? (abnormal termination), sets the ma bit in status register 1 to ?1?, and terminates the command. the following commands will generate an interrupt upon completion. they do not return any result bytes. it is highly recommended that control commands be followed by the sense interrupt status command. otherwise, valuable interrupt status information will be lost. recalibrate this command causes the read/write head within the fdc to retract to the track 0 position. the fdc clears the contents of the pcn counter and checks the status of the ntrk0 pin from the fdd. as long as the ntrk0 pin is low, the dir pin remains 0 and step pulses are issued. when the ntrk0 pin goes high, the se bit in status register 0 is set to ?1? and the command is terminated. if the ntrk0 pin is still low after 79 step pulses have been issued, the fdc sets the se and the ec bits of status register 0 to ?1? and te rminates the command. disks capable of handling more than 80 tracks per side may require more than one recalibrate command to return the head back to physical track 0. table 7.22 typical values for formatting format sector size n sc gpl1 gpl2 5.25? drives fm 128 128 512 1024 2048 4096 ... 00 00 02 03 04 05 ... 12 10 08 04 02 01 07 10 18 46 c8 c8 09 19 30 87 ff ff mfm 256 256 512* 1024 2048 4096 ... 01 01 02 03 04 05 ... 12 10 09 04 02 01 0a 20 2a 80 c8 c8 0c 32 50 f0 ff ff 3.5? drives fm 128 256 512 0 1 2 0f 09 05 07 0f 1b 1b 2a 3a 3.5? drives mfm 256 512** 1024 1 2 3 0f 09 05 0e 1b 35 36 54 74 gpl1 = suggested gpl values in read and write commands to avoid splice point between data field and id field of contiguous sections. gpl2 = suggested gpl value in format a track command. *pc/at values (typical) **ps/2 values (typical). applies with 1.0 mb and 2.0 mb drives. note: all values except sector size are in hex.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 88 smsc sch311x datasheet the recalibrate command does not have a result phase. the sense interrupt status command must be issued after the recalibrate command to effectively terminate it and to provide verification of the head position (pcn). during the command phase of the recalibrate operation, the fdc is in the busy state, but during the execution phase it is in a no n-busy state. at this time, another recalibrate command may be issued, and in this manner parallel recalibrate operations may be done on up to four drives at once. upon power up, the software must issue a recalibrate command to properly initialize all drives and the controller. seek the read/write head within the drive is moved from track to track under the control of the seek command. the fdc compares the pcn, which is the current head position, with the ncn and performs the following operation if there is a difference: pcn < ncn:direction signal to drive set to ?1? (step in) and issues step pulses. pcn > ncn:direction signal to drive set to ?0? (step out) and issues step pulses. the rate at which step pulses are issued is controlled by srt (stepping rate time) in the specify command. after each step pulse is issued, ncn is compared against pcn, and when ncn = pcn the se bit in status register 0 is set to ?1? and the command is terminated. during the command phase of the seek or recalibrate operation, the fdc is in the busy state, but during the execution phase it is in the non-busy state. at this time, another seek or recalibrate command may be issued, and in this manner, parallel seek operations may be done on up to four drives at once. note that if implied seek is not enabled, the read and write commands should be preceded by: 1. seek command - step to the proper track 2. sense interrupt status command - terminate the seek command 3. read id - verify head is on proper track 4. issue read/write command. the seek command does not have a result phase. therefore, it is highly recommended that the sense interrupt status command is issued after the seek command to terminate it and to provide verification of the head position (pcn). the h bit (head address) in st0 will always return to a ?0?. when exiting powerdown mode, the fdc clears the pcn value an d the status information to zero. prior to issuing the powerdown command, it is highly recommended that the user service all pending interrupts through the sense interrupt status command. sense interrupt status an interrupt signal is generated by the fdc for one of the following reasons: 1. upon entering the result phase of: a. read data command b. read a track command c. read id command d. read deleted data command e. write data command f. format a track command g. write deleted data command h. verify command 2. end of seek, relative seek, or recalibrate command the sense interrupt status command resets the interrupt signal and, via the ic code and se bit of status register 0, identifies the cause of the interrupt.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 89 revision 0.4 (06-03-05) datasheet the seek, relative seek, and recalibrate commands have no result phase. the sense interrupt status command must be issued immediately after these commands to terminate them and to provide verification of the head position (pcn). the h (head address) bit in st0 will always return a ?0?. if a sense interrupt status is not issued, the drive w ill continue to be busy and may affect the operation of the next command. sense drive status sense drive status obtains drive status information. it has not execution phase and goes directly to the result phase from the command phase. status re gister 3 contains the drive status information. specify the specify command sets the initial values for each of the three internal times. the hut (head unload time) defines the time from the end of the execution phase of one of the read/write commands to the head unload state. the srt (step rate time) defines the time interval between adjacent step pulses. note that the spacing between the first and second step pulses may be shorter than the remaining step pulses. the hlt (head load time) defines the time between when the head load signal goes high and the read/write operation star ts. the values change with the data rate speed selection and are documented in table 7.24 . the values are the same for mfm and fm. dma operation is selected by the nd bit. when nd is ?0?, the dma mode is selected. this part does not support non-dma mode. in dma mode, data tr ansfers are signaled by the dma request cycles. configure the configure command is issued to select the spec ial features of the fdc. a configure command need not be issued if the default values of the fd c meet the system requirements. table 7.23 interrupt identification se ic interrupt due to 0 1 1 11 00 01 polling normal termination of seek or recalibrate command abnormal termination of seek or recalibrate command
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 90 smsc sch311x datasheet configure default values: eis - no implied seeks efifo - fifo disabled poll - polling enabled fifothr - fifo threshold set to 1 byte pretrk - pre-compensation set to track 0 eis - enable implied seek. when set to "1", the fdc will perform a seek operation before executing a read or write command. defaults to no implied seek. efifo - a "1" disables the fifo (default). this m eans data transfers are asked for on a byte-by-byte basis. defaults to "1", fifo disabled. the threshold defaults to "1". poll - disable polling of the drives. defaults to "0", polling enabled. when enabled, a single interrupt is generated after a reset. no polling is performed while the drive head is loaded and the head unload delay has not expired. fifothr - the fifo threshold in the execution phase of read or write commands. this is programmable from 1 to 16 bytes. defaults to one byte. a "00" selects one byte; "0f" selects 16 bytes. pretrk - pre-compensation start track number. programmable from track 0 to 255. defaults to track 0. a "00" selects tra ck 0; "ff" selects track 255. version the version command checks to see if the controller is an enhanced type or the older type (765a). a value of 90 h is returned as the result byte. relative seek the command is coded the same as for seek, except for the msb of the first byte and the dir bit. table 7.24 drive control delays (ms) hut srt 2m 1m 500k 300k 250k 2m 1m 500k 300k 250k 0 1 . e f 64 4 .. 56 60 128 8 .. 112 120 256 16 .. 224 240 426 26.7 .. 373 400 512 32 .. 448 480 4 3.75 .. 0.5 0.25 8 7.5 .. 1 0.5 16 15 .. 2 1 26.7 25 .. 3.33 1.67 32 30 .. 4 2 hlt 2m 1m 500k 300k 250k 00 01 02 .. 7f 7f 64 0.5 1 .. 63 63.5 128 1 2 .. 126 127 256 2 4 .. 252 254 426 3.3 6.7 .. 420 423 512 4 8 . 504 508
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 91 revision 0.4 (06-03-05) datasheet dir head step direction control rcn relative cylinder number that determines how many tracks to st ep the head in or out from the current track number. the relative seek command differs from the seek command in that it steps the head the absolute number of tracks specified in the command inst ead of making a comparison against an internal register. the seek command is good for drives that support a maximum of 256 tracks. relative seeks cannot be overlapped with other relative seeks. only one relative seek can be active at a time. relative seeks may be overlapped with seeks and recalibrates. bit 4 of status register 0 (ec) will be set if relative seek attempts to step outward beyond track 0. as an example, assume that a floppy drive has 300 usable tracks. the host needs to read track 300 and the head is on any track (0-255). if a seek command is issued, the head will stop at track 255. if a relative seek command is issued, the fdc will move the head the specified number of tracks, regardless of the inte rnal cylinder position register (but will increment th e register). if the head was on track 40 (d), the maximum track that the fdc could position the head on using relative seek will be 295 (d), the initial track + 255 (d). the maximum count that the head can be moved with a single relative seek command is 255 (d). the internal register, pcn, will overflow as the cylinder number crosses track 255 and will contain 39 (d). the resulting pcn value is thus (rcn + pcn) mod 256. functionally, the fdc starts counting from 0 again as the track number goes above 255 (d). it is the user?s responsibility to compensate fdc functions (precompensation track number) when accessing tr acks greater than 255. the fdc does not keep track that it is working in an ?e xtended track area? (greater than 255). any command issued will use the current pcn value except for th e recalibrate command, which only looks for the track0 signal. recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a maximum of 80 step pulses. the user simply needs to issue a second recalibrate command. the seek command and implied seeks will function correctly within the 44 (d) track (299-255) area of the ?extended track area?. it is the user?s responsi bility not to issue a new track position that will exceed the maximum track that is present in the extended area. to return to the standard floppy range (0-255) of tracks, a relative seek should be issued to cross the track 255 boundary. a relative seek can be used instead of the normal seek, but the host is required to calculate the difference between the current head location and the new (target) head location. this may require the host to issue a read id command to ensure that the head is physically on the track that software assumes it to be. different fdc commands will return different cylinder results which may be difficult to keep track of with software without the read id command. perpendicular mode the perpendicular mode command should be issued prior to executing read/write/format commands that access a disk drive with perpendicular recording capability. with this command, the length of the gap2 field and vco enable timing can be altered to accommodate the unique requirements of these drives. table 7.25 on page 93 describes the effects of the wgate and gap bits for the perpendicular mode command. upon a reset, the fdc will default to the conventional mode (wgate = 0, gap = 0). selection of the 500 kbps and 1 mbps perpendicular modes is independent of the actual data rate selected in the data rate select register. the user must ensure that these two data rates remain consistent. the gap2 and vco timing requirements for perpendicula r recording type drives are dictated by the design of the read/write head. in the design of this head, a pre-erase head precedes the normal read/write head by a distance of 200 micrometers. this works out to about 38 bytes at a 1 mbps dir action 0 1 step head out step head in
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 92 smsc sch311x datasheet recording density. whenever the write head is ena bled by the write gate signal, the pre-erase head is also activated at the same time. thus, when the write head is initially turned on, flux transitions recorded on the media for the first 38 bytes will not be preconditioned with the pre-erase head since it has not yet been activated. to accommodate this head activation and deactivation time, the gap2 field is expanded to a length of 41 bytes. the form at fields table illustrates the change in the gap2 field size for the perpendicular format. on the read back by the fdc, the controller must begin synchronization at the beginning of the sync field. for the conventional mode, the internal pll vco is enabled (vcoen) approximately 24 bytes from the start of the gap2 field. but, when the controller operates in the 1 mbps perpendicular mode (wgate = 1, gap = 1), vcoen goes active after 43 bytes to accommodate the increased gap2 field size. for both cases, and approximate two-byte cushion is maintained from the beginning of the sync field for the purposes of avoiding write splices in the presence of motor speed variation. for the write data case, the fdc activates write gate at the beginning of the sync field under the conventional mode. the controller then writes a new sync field, data address mark, data field, and crc. with the pre-erase head of the perpendicular dr ive, the write head must be activated in the gap2 field to insure a proper write of the new sync field. for the 1 mbps perpendicular mode (wgate = 1, gap = 1), 38 bytes will be written in the gap2 space. since the bit density is proportional to the data rate, 19 bytes will be written in the gap2 field for the 500 kbps perpendicular mode (wgate = 1, gap =0). it should be noted that none of the alterations in gap2 size, vco timing, or write gate timing affect normal program flow. the information provided here is just for background purposes and is not needed for normal operation. once the perpendicular mode command is invoked, fdc software behavior from the user standpoint is unchanged. the perpendicular mode command is enhanced to allo w specific drives to be designated perpendicular recording drives. this enhancement allows data transfers between conventional and perpendicular drives without having to issue perpendicular mode commands between the accesses of the different drive types, nor having to change write pre-compensation values. when both gap and wgate bits of the perpendicular mode command are both programmed to ?0? (conventional mode), then d0, d1, d2, d3, and d4 can be programmed independently to ?1? for that drive to be set automatically to per pendicular mode. in this mode the following set of conditions also apply: the gap2 written to a perpendicular drive during a write operation will depend upon the programmed data rate. the write pre-compensation given to a perpendicular mode drive will be 0ns. for d0-d3 programmed to ?0? for conventional mode drives any data written will be at the currently programmed write pre-compensation. note: bits d0-d3 can only be overwritten when ow is programmed as a ?1?.if either gap or wgate is a ?1? then d0-d3 are ignored. software and hardware resets have the following effect on the perpendicular mode command: 1. ?software? resets (via the dor or dsr registers) will only clear gap and wgate bits to ?0?. d0- d3 are unaffected and retain their previous value. 2. ?hardware? resets will clear all bits (gap, wgate and d0-d3) to ?0?, i.e all conventional mode.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 93 revision 0.4 (06-03-05) datasheet lock in order to protect systems with lo ng dma latencies against older applic ation software that can disable the fifo the lock command has been added. this command should only be used by the fdc routines, and application software should refrain from using it. if an application calls for the fifo to be disabled then the configure command should be used. the lock command defines whether the efifo, fifothr, and pretrk parameters of the configure command can be reset by the dor and dsr registers. when the lock bit is set to logic ?1? all subsequent ?software resets by the dor and dsr registers will not change the previously set parameters to their default values . all ?hardware? reset from the pci_reset# pin will set the lock bit to logic ?0? and return the efifo, fifothr, and pretrk to their default values. a status byte is returned immediately after issuing a lock command. this byte reflects the value of the lock bit set by the command byte. enhanced dumpreg the dumpreg command is designed to support system run-time diagnostics and application software development and debug. to accommodate the lock command and the enhanced perpendicular mode command the eighth byte of the dumpreg command has been modified to contain the additional data from these two commands. compatibility the sch311x was designed with soft ware compatibility in mind. it is a fu lly backwards- compatible solution with the older generation 765a/b disk controllers. the fdc also implements on-board registers for compatibility with the ps/2, as we ll as pc/at and pc/xt, floppy disk controller subsystems. after a hardware rese t of the fdc, all registers, f unctions and enhancements default to a pc/at, ps/2 or ps/2 model 30 compatible operating mode, depending on how the ident and mfm bits are configured by the system bios. table 7.25 effects of wgate and gap bits wgate gap mode length of gap2 format field portion of gap 2 written by write data operation 0 0 1 1 0 1 0 1 conventional perpendicular (500 kbps) reserved (conventional) perpendicular (1 mbps) 22 bytes 22 bytes 22 bytes 41 bytes 0 bytes 19 bytes 0 bytes 38 bytes
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 94 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 95 revision 0.4 (06-03-05) datasheet chapter 8 serial port (uart) the sch3112 incorporates two full function uarts. the sch3114 incorporates four full function uarts. the sch3116 incorporates four full function uarts, and two, 4 pin uarts. they are compatible with the ns16450, the 16450 ace registers and the ns16c550a. the uarts perform serial-to-parallel conversion on re ceived characters and parallel-t o-serial conversion on transmit characters. the data rates are independently progra mmable from 460.8k baud down to 50 baud. the character options are programmable for 1 start; 1, 1. 5 or 2 stop bits; even, odd, sticky or no parity; and prioritized interrupts. the uarts each contain a programmable baud rate generator that is capable of dividing the input clock or crystal by a number from 1 to 65535. the uarts are also capable of supporting the midi data rate. refer to the configuration registers for information on disabling, power down and changing the base address of the ua rts. the interrupt from a uart is enabled by programming out2 of that uart to a logic ?1?. out2 being a logic ?0? disables that uart?s interrupt. the second uart also supports irda, hp-sir and ask-ir modes of operation. register description addressing of the accessible registers of the serial port is shown below. the base addresses of the serial ports are defined by the configuration registers (see chapter 25, "config registers," on page 287 ). the serial port registers are located at sequentially increasing addresses above these base addresses. the register set of the uarts are described below. note: * dlab is bit 7 of the line control register the following section describes the operation of the registers. receive buffer register (rb) address offset = 0h, dlab = 0, read only this register holds the received incoming data by te. bit 0 is the least significant bit, which is transmitted and received first. received data is double buffered; this uses an additional shift register table 8.1 addressing the serial port dlab* a2 a1 a0 register name 0 0 0 0 receive buffer (read) 0 0 0 0 transmit buffer (write) 0 0 0 1 interrupt enable (read/write) x 0 1 0 interrupt identification (read) x 0 1 0 fifo control (write) x 0 1 1 line control (read/write) x 1 0 0 modem control (read/write) x 1 0 1 line status (read/write) x 1 1 0 modem status (read/write) x 1 1 1 scratchpad (read/write) 1 0 0 0 divisor lsb (read/write) 1 0 0 1 divisor msb (read/write
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 96 smsc sch311x datasheet to receive the serial data stream and convert it to a parallel 8 bit word which is transferred to the receive buffer register. the sh ift register is not accessible. transmit buffer register (tb) address offset = 0h, dlab = 0, write only this register contains the data by te to be transmitted. the transmi t buffer is double buffered, utilizing an additional shift register (not accessible) to convert the 8 bit data word to a serial format. this shift register is loaded from the transmit buffer when the transmission of the previous byte is complete. interrupt enable register (ier) address offset = 1h, dlab = 0, read/write the lower four bits of this register control the enables of the five interrupt sources of the serial port interrupt. it is possible to totally disable the interrupt system by resetting bits 0 through 3 of this register. similarly, setting the appropriate bits of this register to a high, selected interrupts can be enabled. disabling the interrupt system inhibits the interrupt identification register and disables any serial port interrupt out of the sch311x. all ot her system functions operate in their normal manner, including the line status and modem status registers. the contents of the interrupt enable register are described below. bit 0 this bit enables the received data available interrupt (and timeout interrupts in the fifo mode) when set to logic ?1?. bit 1 this bit enables the transmitter holding register empty interrupt when set to logic ?1?. bit 2 this bit enables the received line status interrupt when set to logic ?1?. the error sources causing the interrupt are overrun, parity, framing and break. the line status register must be read to determine the source. bit 3 this bit enables the modem status interrupt when set to logic ?1?. this is caused when one of the modem status register bits changes state. bits 4 through 7 these bits are always logic ?0?. fifo control register (fcr) address offset = 2h, dlab = x, write this is a write only register at the same location as the iir. this register is used to enable and clear the fifos, set the rcvr fifo trigger level. note: dma is not supported. the uart1 and uart2 fcrs are shadowed in the uart1 fifo control shadow register (runtime register at offset 0x20) and uart2 fifo control shadow register (runtime register at offset 0x21). bit 0 setting this bit to a logic ?1? enables both the xmit and rcvr fifos. clearing this bit to a logic ?0? disables both the xmit and rcvr fifos and clears all bytes from both fifos. when changing from fifo mode to non-fifo (16450) mode, data is autom atically cleared from the fifos. this bit must be a 1 when other bits in this register are writ ten to or they will not be properly programmed.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 97 revision 0.4 (06-03-05) datasheet bit 1 setting this bit to a logic ?1? clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 2 setting this bit to a logic ?1? clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. this bit is self-clearing. bit 3 writing to this bit has no effect on the operatio n of the uart. the rxrdy and txrdy pins are not available on this chip. bit 4,5 reserved bit 6,7 these bits are used to set the trigger level for the rcvr fifo interrupt. interrupt identification register (iir) address offset = 2h, dlab = x, read by accessing this register, the host cpu can determi ne the highest priority interrupt and its source. four levels of priority interrupt exist. they are in descending order of priority: 1. receiver line status (highest priority) 2. received data ready 3. transmitter holding register empty 4. modem status (lowest priority) information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the interrupt identification register (refer to table 8.2 on page 98 ). when the cpu accesses the iir, the serial port freezes all interrupts and indicates the highest priority pending interrupt to the cpu. during this cpu access, even if the serial port records new interrupts, the current indication does not change until access is completed. the contents of the iir are described below. bit 0 this bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. when bit 0 is a logic ?0?, an interrupt is pending and the contents of the iir may be used as a pointer to the appropriate internal service routine. when bit 0 is a logic ?1?, no interrupt is pending. bits 1 and 2 these two bits of the iir are used to identify the hi ghest priority interrupt pending as indicated by the interrupt control table ( table 8.2 ). bit 3 in non-fifo mode, this bit is a logic ?0?. in fifo mode this bit is set along with bit 2 when a timeout interrupt is pending. bits 4 and 5 these bits of the iir are always logic ?0?. bits 6 and 7 these two bits are set when the fifo control register bit 0 equals 1.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 98 smsc sch311x datasheet line control register (lcr) address offset = 3h, dlab = 0, read/write figure 8.1 serial data bit 7 bit 6 rcvr fifo trigger level (bytes) 00 1 01 4 10 8 11 14 table 8.2 interrupt control fifo mode only interrupt identification register interrupt set and reset functions bit 3bit 2bit 1bit 0priority level interrupt type interrupt source interrupt reset control 0 0 0 1 - none none - 0 1 1 0 highest receiver line status overrun error, parity error, framing error or break interrupt reading the line status register 0100secondreceived data available receiver data available read receiver buffer or the fifo drops below the trigger level. 1 1 0 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time reading the receiver buffer register 0010thirdtransmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing the transmitter holding register 0 0 0 0 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register start lsb data 5-8 bits msb parity stop
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 99 revision 0.4 (06-03-05) datasheet this register contains the format information of the serial line. the bit definitions are: bits 0 and 1 these two bits specify the number of bits in each transmitted or received serial character. the encoding of bits 0 and 1 is as follows: the start, stop and parity bits are not included in the word length. bit 2 this bit specifies the number of stop bits in each transmitted or received serial character. the following table summarizes the information. note: the receiver will ignore all st op bits beyond the first, r egardless of the number used in transmitting. bit 3 parity enable bit. when bit 3 is a logic ?1?, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and the first stop bit of the serial data. (the parity bit is used to generate an even or odd number of 1s when the data word bits and the parity bit are summed). bit 4 even parity select bit. when bit 3 is a logic ?1? and bit 4 is a logic ?0?, an odd number of logic ?1??s is transmitted or checked in the data word bits and the parity bit. when bit 3 is a logic ?1? and bit 4 is a logic ?1? an even number of bits is transmitted and checked. bit 5 this bit is the stick parity bit. when parity is enabl ed it is used in conjunction with bit 4 to select mark or space parity. when lcr bits 3, 4 and 5 are 1 the parity bit is transmitted and checked as a 0 (space parity). if bits 3 and 5 are 1 and bit 4 is a 0, then the parity bit is transmitted and checked as 1 (mark parity). if bit 5 is 0 stick parity is disabled. bit 6 set break control bit. when bit 6 is a logic ?1?, the transmit data output (txd) is forced to the spacing or logic ?0? state and remains there (until reset by a low level bit 6) regardless of other transmitter activity. this feature enables the serial port to alert a terminal in a communications system. bit 1 bit 0 word length 0 0 1 1 0 1 0 1 5 bits 6 bits 7 bits 8 bits bit 2 word length number of stop bits 0-- 1 1 5 bits 1.5 16 bits 2 17 bits 2 18 bits 2
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 100 smsc sch311x datasheet bit 7 divisor latch access bit (dlab). it must be set high (logic ?1?) to access the divisor latches of the baud rate generator during read or write operations. it must be set low (logic ?0?) to access the receiver buffer register, the transmitter holding register, or the interrupt enable register. modem control register (mcr) address offset = 4h, dlab = x, read/write this 8 bit register controls the interface with th e modem or data set (or device emulating a modem). the contents of the modem control register are described below. bit 0 this bit controls the data terminal ready (ndtr) output. when bit 0 is set to a logic ?1?, the ndtr output is forced to a logic ?0?. when bit 0 is a logic ?0?, the ndtr output is forced to a logic ?1?. bit 1 this bit controls the request to send (nrts) out put. bit 1 affects the nrts output in a manner identical to that described above for bit 0. bit 2 this bit controls the output 1 (out1) bit. this bit does not have an output pin and can only be read or written by the cpu. bit 3 output 2 (out2). this bit is used to enable an uart interrupt. when out2 is a logic "0", the serial port interrupt output is forced to a high impedance state - disabled. when out2 is a logic "1", the serial port interrupt outputs are enabled. bit 4 this bit provides the loopback feature for diagnostic testing of the serial port. when bit 4 is set to logic ?1?, the following occur: 1. the txd is set to the marking state (logic ?1?). 2. the receiver serial input (rxd) is disconnected. 3. the output of the transmitter shift register is ?looped back? into the receiver shift register input. 4. all modem control inputs (ncts, ndsr, nri and ndcd) are disconnected. 5. the four modem control outputs (ndtr, nrts, out1 and out2) are internally connected to the four modem control inputs (ndsr, ncts, ri, dcd). 6. the modem control output pins are forced inactive high. 7. data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the serial port. in the diagnostic mode, the receiver and the transmi tter interrupts are fully operational. the modem control interrupts are also operational but the interrupts? sources are now the lower four bits of the modem control register instead of the modem control inputs. the interrupts are still controlled by the interrupt enable register. bits 5 through 7 these bits are permanently set to logic zero.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 101 revision 0.4 (06-03-05) datasheet line status register (lsr) address offset = 5h, dlab = x, read/write bit 0 data ready (dr). it is set to a logic ?1? whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to a logic ?0? by reading all of the data in the receive buffer register or the fifo. bit 1 overrun error (oe). bit 1 indicates that data in t he receiver buffer register was not read before the next character was transferred into the register, ther eby destroying the previous character. in fifo mode, an overrun error will occur only when the fifo is full and the next character has been completely received in the shift register, the char acter in the shift register is overwritten but not transferred to the fifo. the oe indicator is set to a logic ?1? immediately upon detection of an overrun condition, and reset whenever the line status register is read. bit 2 parity error (pe). bit 2 indicate s that the received data character does not have the correct even or odd parity, as selected by the even parity select bit. the pe is set to a logic ?1? upon detection of a parity error and is reset to a logic ?0? whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. bit 3 framing error (fe). bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to a logic ?1? whenever the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). the fe is reset to a logic ?0? whenever the line status register is read. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associat ed character is at the top of the fifo. the serial port will try to resynchronize after a framing error. to do this, it assumes that the framing error was due to the next start bit, so it samples this ?start? bit twice and then takes in the ?data?. bit 4 break interrupt (bi). bit 4 is set to a logic ?1? whenever the received data input is held in the spacing state (logic ?0?) for longer than a full word transmission time (that is, the total time of the start bit + data bits + parity bits + stop bits). the bi is reset after the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is indicated when the associated character is at the top of the fifo. when break occurs only one zero character is loaded into the fifo. restarting after a break is received, requires the serial data (rxd) to be logic ?1? for at least ? bit time. note: bits 1 through 4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. bit 5 transmitter holding register empty (thre). bit 5 indicates that the serial port is ready to accept a new character for transmission. in addition, this bi t causes the serial port to issue an interrupt when the transmitter holding register interrupt enable is set high. the thre bit is set to a logic ?1? when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic ?0? whenever the cpu loads the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty, it is cleared when at least 1 byte is written to the xmit fifo. bit 5 is a read only bit. bit 6 transmitter empty (temt). bit 6 is set to a logic ?1? whenever the transmitter holding register (thr) and transmitter shift register (tsr) are both empty. it is reset to logic ?0? whenever either the thr
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 102 smsc sch311x datasheet or tsr contains a data character. bit 6 is a read on ly bit. in the fifo mode this bit is set whenever the thr and tsr are both empty, bit 7 this bit is permanently set to logic ?0? in the 450 mode. in the fifo mode, this bit is set to a logic ?1? when there is at least one parity error, framing error or break indication in the fifo. this bit is cleared when the lsr is read if there are no subsequent errors in the fifo. modem status register (msr) address offset = 6h, dlab = x, read/write this 8 bit register provides the current state of the control lines from the modem (or peripheral device). in addition to this current state informatio n, four bits of the modem status register (msr) provide change information. these bits are set to logic ?1? whenever a control input from the modem changes state. they are reset to logic ?0? whenever the modem status register is read. bit 0 delta clear to send (dcts). bit 0 indicates that the ncts input to the chip has changed state since the last time the msr was read. bit 1 delta data set ready (ddsr). bit 1 indicates that the ndsr input has changed state since the last time the msr was read. bit 2 trailing edge of ring indicator (teri). bit 2 indicates that the nri input has changed from logic ?0? to logic ?1?. bit 3 delta data carrier detect (ddcd). bit 3 indicates that the ndcd input to the chip has changed state. note: whenever bit 0, 1, 2, or 3 is set to a logic ?1?, a modem status interrupt is generated. bit 4 this bit is the complement of the clear to send (ncts) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to nrts in the mcr. bit 5 this bit is the complement of the data set ready (ndsr) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to dtr in the mcr. bit 6 this bit is the complement of the ring indicator (nri) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivalent to out1 in the mcr. bit 7 this bit is the complement of the data carrier detect (ndcd) input. if bit 4 of the mcr is set to logic ?1?, this bit is equivale nt to out2 in the mcr. scratchpad register (scr) address offset =7h, dlab =x, read/write this 8 bit read/write register has no effect on the operation of the serial port. it is intended as a scratchpad register to be used by the programmer to hold data temporarily.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 103 revision 0.4 (06-03-05) datasheet programmable baud rate generator (a nd divisor latches dlh, dll) the serial port contains a programmable baud rate generator that is capable of dividing the internal pll clock by any divisor from 1 to 65535. the internal pll clock is divided down to generate a 1.8462mhz frequency for baud rates less than 38.4k, a 1.8432mhz frequency for 115.2k, a 3.6864mhz frequency for 230.4k and a 7.3728mhz frequency for 460.8k. this output frequency of the baud rate generator is 16x the baud rate. two 8 bit latches store the divisor in 16 bit binary format. these divisor latches must be loaded during initialization in order to insure desired operation of the baud rate generator. upon loading either of the divisor latches, a 16 bit baud counter is immediately loaded. this prevents long counts on initial load. if a 0 is loaded into the brg registers the output divides the clock by the number 3. if a 1 is loaded the output is the inverse of the input oscillator. if a two is loaded the output is a divide by 2 signal with a 50% duty cycle. if a 3 or greater is loaded the output is low for 2 bits and high for the remainder of the count. the input clock to the brg is a 1.8462 mhz clock. programming high speed serial port baud rates the sch311x and sch310x family of devices sup ports serial ports with speeds up to 1.5mb/s. changing the serial ports baud rates between standard speeds (115k baud and slower) during runtime is possible with standard drivers. in order to change baud rates to high speed (230k, 460k, 921k and 1.5m bauds) on the sch311x devices during runtim e, registers in both configuration space and runtime space must be programmed. note that this applies only if the application requir es a serial port baud rate to change during runtime. standard windows drivers could be used to select the specific high speed rate if it will remain unchanged during runtime table 8.4 on page 105 shows the baud rates possible. effect of the reset on the register file the reset function (details the effect of the reset input on each of the registers of the serial port. fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr bit 0 = ?1?, ier bit 0 = ?1?), rcvr interrupts occur as follows: the receive data available interrupt will be issued when the fifo has reached its programmed trigger level; it is cleared as soon as t he fifo drops below its programmed trigger level. the iir receive data available indication also occurs when the fifo trigger level is reached. it is cleared when the fifo drops below the trigger level. the receiver line status interrupt (iir=06h), has higher priority than the received data available (iir=04h) interrupt. the data ready bit (lsr bit 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo timeout interrupts occur as follows: a fifo timeout interrupt occurs if all the following conditions exist: at least one character is in the fifo. the most recent serial character received was longer than 4 continuous character times ago. (if 2 stop bits are programmed, the second one is included in this time delay). the most recent cpu read of the fifo was longer than 4 continuous character times ago. this will cause a maximum character received to in terrupt issued delay of 160 msec at 300 baud with a 12-bit character. character times are calculated by using the rclk input for a clock signal (this makes the delay proportional to the baud rate). when a timeout interrupt has occurred it is cleared and the timer reset when the cpu reads one character from the rcvr fifo.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 104 smsc sch311x datasheet when a timeout interrupt has not occurred the timeout timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr bit 0 = ?1?, ier bit 1 = ?1?), xmit interrupts occur as follows: the transmitter holding register interrupt (02h) occu rs when the xmit fifo is empty; it is cleared as soon as the transmitter holding register is writ ten to (1 of 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre=1 and there have not been at least two bytes at the same time in the transmitter fifo since the last thre=1. the transmitter interrupt after changing fcr0 will be immediate, if it is enabled. character timeout and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt. fifo polled mode operation with fcr bit 0 = ?1? resetting ier bits 0, 1, 2 or 3 or all to zero puts the uart in the fifo polled mode of operation. since the rcvr and xmitter are controlled separately, either one or both can be in the polled mode of operation. in this mode, the user?s program will check rcvr and xmitter status via the lsr. lsr definitions for the fifo polled mode are as follows: bit 0=1 as long as there is one byte in the rcvr fifo. bits 1 to 4 specify which error(s) have occurred. character error status is handled the same way as when in the interrupt mode, the iir is not affected since eir bit 2=0. bit 5 indicates when the xmit fifo is empty. bit 6 indicates that both the xmit fifo and shift register are empty. bit 7 indicates whether there are any errors in the rcvr fifo. there is no trigger level reached or timeout condition indicated in the fifo polled mode, however, the rcvr and xmit fifos are still fully capable of holding characters. frequency selection each serial port mode register (at offset 0xf0 in logical devices 0x4, 0x5, 0xb - 0xe) the frequency is selected as shown in ta b l e 8 . 3 . figure 8.2 illustrates the effect of programming bits[3:0] of the mode register (at offset 0xf0 in the respective logical device) on the baud rate. ta b l e 8 . 4 summarizes this functionality. table 8.3 serial ports mode register serial port 1-6 mode register default = 0x00 on vcc por, vtr por and pci reset 0xf0 r/w in all of the sp logical devices bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled (default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[7:4] refer to section 8.2, "interrupt sharing" for more detail.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 105 revision 0.4 (06-03-05) datasheet note 8.1 31250 khz is the midi frequency. it is possible to program other baud rates when the midi bit is set by changing the divisor register, but the device will not be midi compliant. note 8.2 the percentage error for all baud rates, except where indicated otherwise, is 0.2%. table 8.4 baud rates desired baud rate divisor used to generate 16x clock percent error difference between desired and actual note 8.2 midi mode high speed enhanced frequency select bit bit 15 bit14 bit13 bits[12:0] bit[0] bit[1] bit[2] bit[3] 50 0 0 0 2304 0.001 0 0 x x 75 0 0 0 1536 - 0 0 x x 110 0 0 0 1047 - 0 0 x x 134.5 0 0 0 857 0.004 0 0 x x 150 0 0 0 768 - 0 0 x x 300 0 0 0 384 - 0 0 x x 600 0 0 0 192 - 0 0 x x 1200 0 0 0 96 - 0 0 x x 1800 0 0 0 64 - 0 0 x x 2000 0 0 0 58 0.005 0 0 x x 2400 0 0 0 48 - 0 0 x x 3600 0 0 0 32 - 0 0 x x 4800 0 0 0 24 - 0 0 x x 7200 0 0 0 16 - 0 0 x x 9600 0 0 0 12 - 0 0 x x 19200 0 0 0 6 - 0 0 x x 38400 0 0 0 3 0.030 0 0 x x 57600 0 0 0 2 0.16 0 0 x x 115200 0 0 0 1 0.16 0 0 x x 230400 1 0 0 2 0.16 0 1 x x 460800 1 0 0 1 0.16 0 1 x x 921600 1 1 0 1 0.16 0 1 1 x 1500000 0 0 1 1 0.16 0 x x 1 31250 ( note 8.1 ) 4 0.16 1 0 0 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 106 smsc sch311x datasheet figure 8.2 baud rate selection table 8.5 register reset register bit reset control reset state interrupt enable regi ster reset all bits low interrupt identif ication reg. reset bit 0 is high; bits 1 - 7 low fifo control reset all bits low line control reg. reset all bits low modem control reg. reset all bits low line status reg. reset all bits low except 5, 6 high modem status reg. reset bits 0 - 3 low; bits 4 - 7 input intrpt (rcvr errs) reset/read lsr low intrpt (rcvr data ready) reset/read rbr low intrpt (thre) reset/r ead iir/write thr low rcvr fifo reset/ fcr1*fcr0/_fcr0 all bits low xmit fifo reset/ fcr1*fcr0/_fcr0 all bits low mux 96m 24m reg 0xf0 bit[1] divide by 13 user programmed divisor (13 bit) baud rate divide by 6.5 divide by 12 midi sel reg 0xf0 bit[0] reg 0xf0 bit[3] divisor bit[15] hsp1 hsp1 divisor bit[14] divisor bit[13] reg 0xf0 bit[2] hsp2 hsp3 x 16 hsp2 hsp3 0 1 3:2 frequency select note: high speed mode . when configured for high speed operation, the f0 bits[3:1] are set to 1 and the hsp bit [3:1] are controlled by the divisor bits[15:13].
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 107 revision 0.4 (06-03-05) datasheet note 8.3 serial ports 1 and 2 may be placed in the powerdown mode by clearing the associated activate bit located at cr30 or by clearing the associated power bit located in the power control register at cr22. serial ports 3,4,5,6 (if available) may be placed in the powerdown mode by clearing the associated activate bit located at cr30. when in the powerdown mode, the serial port outputs are tristated. in cases where the serial port is multiplexed as an alternate function, the corresponding output will only be tristated if the serial port is the selected alternate function. table 8.6 pin reset pin signal reset control reset state txdn reset high-z ( note 8.3 ) nrtsx reset high-z ( note 8.3 ) ndtrx reset high-z ( note 8.3 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 108 smsc sch311x datasheet table 8.7 register summary fo r an individual uart channel register address ( note 8.4 ) register name register symbol bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr = 0 dlab = 0 receive buffer regis- ter (read only) rbr data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 ( note 8.5 ) addr = 0 dlab = 0 transmitter holding register (write only) thr data bit 7 data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 addr = 1 dlab = 0 interrupt enable regis- ter ier 0 0 0 0 enable modem status interrupt (emsi) enable receiver line status interrupt (elsi) enable transmit- ter holding register empty interrupt (ethrei) enable received data avail- able inter- rupt (erdai) addr = 2 interrupt ident. register (read only) iir fifos enabled ( note 8.9 ) fifos enabled (note 6) 0 0 interrupt id bit ( note 8.9 ) interrupt id bit interrupt id bit ?0? if inter- rupt pend- ing addr = 2 fifo control register (write only) fcr ( note 8.11 ) rcvr trig- ger msb rcvr trig- ger lsb reserved reserved dma mode select ( note 8.10 ) xmit fifo reset rcvr fifo reset fifo enable addr = 3 line control register lcr divisor latch access bit (dlab) set break stick parity even par- ity select (eps) parity enable (pen) number of stop bits (stb) word length select bit 1 (wls1) word length select bit 0 (wls0) addr = 4 modem control regis- ter mcr 0 0 0 loop out2 ( note 8.7 ) out1 ( note 8.7 ) request to send (rts) data termi- nal ready (dtr) addr = 5 line status register lsr error in rcvr fifo ( note 8.9 ) transmit- ter empty (temt) ( note 8.6 ) transmit- ter holding register (thre) break inter- rupt (bi) framing error (fe) parity error (pe) overrun error (oe) data ready (dr)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 109 smsc sch311x datasheet addr = 6 modem status regis- ter msr data car- rier detect (dcd) ring indi- cator (ri) data set ready (dsr) clear to send (cts) delta data carrier detect (ddcd) trailing edge ring indicator (teri) delta data set ready (ddsr) delta clear to send (dcts) addr = 7 scratch register ( note 8.8 ) scr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr = 0 dlab = 1 divisor latch (ls) ddl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr = 1 dlab = 1 divisor latch (ms) dlm bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 note 8.4 dlab is bit 7 of the line control register (addr = 3). note 8.5 bit 0 is the least significant bit. it is the first bit serially transmitted or received. note 8.6 when operating in the xt mode, this bit will be set any time that the transmitter shift register is empty. note 8.7 this bit no longer has a pin associated with it. note 8.8 when operating in the xt mode, this register is not available. note 8.9 these bits are always zero in the non-fifo mode. note 8.10 writing a one to this bit has no effect. dma modes are not supported in this chip. note 8.11 the uarts fcr?s are shadowed uart fifo control shadow registers. see chapter 26, runtime register for more details. table 8.7 register summary for an individual uart channel (continued) register address ( note 8.4 ) register name register symbol bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 110 smsc sch311x datasheet notes on serial port operation fifo mode operation: general the rcvr fifo will hold up to 16 bytes r egardless of which trig ger level is selected. tx and rx fifo operation the tx portion of the uart transmits data through txd as soon as the cpu loads a byte into the tx fifo. the uart will prevent loads to the tx fifo if it currently holds 16 characters. loading to the tx fifo will again be enabled as soon as the next character is transferred to the tx shift register. these capabilities account for the largely autonomous operation of the tx. the uart starts the above operations typically with a tx interrupt. the chip issues a tx interrupt whenever the tx fifo is empty and the tx interrupt is enabled, except in the following instance. assume that the tx fifo is empty and the cpu starts to load it. when the first byte enters the fifo the tx fifo empty interrupt will transition from active to inactive. depending on the execution speed of the service routine software, the uart may be able to transfer this byte from the fifo to the shift register before the cpu loads another byte. if th is happens, the tx fifo will be empty again and typically the uart?s interrupt line would transition to the active state. this could cause a system with an interrupt control unit to record a tx fifo empty condition, even though the cpu is currently servicing that interrupt. therefore, after the first byte has been loaded into the fifo the uart will wait one serial character transmission time before issuing a new tx fifo empty interrupt. this one character tx interrupt delay will remain active until at least two bytes have been loaded into the fifo, concurrently. when the tx fifo empties after this condition, the tx interrupt will be activated without a one character delay. rx support functions and operation are quite differen t from those described for the transmitter. the rx fifo receives data until the number of bytes in the fifo equals the selected interrupt trigger level. at that time if rx interrupts are enabled, the uart will issue an interrupt to the cpu. the rx fifo will continue to store bytes until it holds 16 of them. it will not accept any more data when it is full. any more data entering the rx shift register will set the overrun error flag. normally, the fifo depth and the programmable trigger levels will give the cpu ample time to empty the rx fifo before an overrun occurs. one side-effect of having a rx fifo is that the selected interrupt trigger level may be above the data level in the fifo. this could occur when data at the end of the block contains fewer bytes than the trigger level. no interrupt would be issued to the cpu and the data would remain in the uart. to prevent the software from having to check for this si tuation the chip incorporates a timeout interrupt. the timeout interrupt is activated when there is a least one byte in the rx fifo, and neither the cpu nor the rx shift register has accessed the rx fifo within 4 character times of the last byte. the timeout interrupt is cleared or reset when the cpu reads the rx fifo or another character enters it. these fifo related features allow optimization of cpu/uart transactions and are especially useful given the higher baud rate capability (256 kbaud). txd2 pin the txd2 signal is located on the gp53/txd2(irtx) pin. the operation of this pin following a power cycle is defined in section 8.1.1, "ir transmit pin," on page 111 . 8.1 infrared interface the infrared interface provides a two-way wi reless communications port using infrared as a transmission medium. two ir implementations have been provided for the second uart in this chip (logical device 5), irda and amplitude shift keye d ir. the ir transmission can use the standard uart2 txd2 and rxd2 pins. these can be selected through the configuration registers. irda 1.0 allows serial communication at baud rates up to 115.2 kbps. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a single ir pulse at the beginning
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 111 revision 0.4 (06-03-05) datasheet of the serial bit time. a one is signaled by sending no ir pulse during the bit time. please refer to the ac timing for the parameters of these pulses and the irda waveform. the amplitude shift keyed ir allows asynchronous serial communication at baud rates up to 19.2k baud. each word is sent serially beginning with a zero value start bit. a zero is signaled by sending a 500khz waveform for the duration of the seri al bit time. a one is signaled by sending no transmission during the bit time. pl ease refer to the ac timing for the parameters of the ask-ir waveform. if the half duplex option is chosen, there is a time-out when the direction of the transmission is changed. this time-out starts at the last bit transferred during a transmission and blocks the receiver input until the timeout expires. if the transmit buffer is loaded with more data before the time-out expires, the timer is restarted after the new byte is transmitted. if data is loaded into the transmit buffer while a character is being received, the transmission will not start until the time-out expires after the last receive bit has been received. if the start bit of another character is received during this time-out, the timer is restarted after the new character is re ceived. the ir half duplex time-out is programmable via crf2 in logical device 5. this register allows the time-out to be programmed to any value between 0 and 10msec in 100usec increments. figure 8.3 block diagram of the ir components in the sch311x 8.1.1 ir transmit pin the following description describes the state of the gp53/txd2(irtx) pin following a power cycle. gp53/txd2(irtx) pin. this pin defaults to the gpio input function on a vtr por. the gp53/txd2(irtx) pin will be tristate following a vcc por, vtr por, soft reset, or pci reset when it is configured for the txd2 (irtx) function. it will remain tristate until the uart is powered. once the uart is powered, the state of the pin will be determined by the uart block. if vcc>2.4v and gp53 function is selected the pin will reflect the current state of gp53. note: external hardware should be implemented to protect the transceiver when the irtx2 pin is tristated. 8.2 interrupt sharing multiple sharing options are available are for th e sch311x devices. sharing an interrupt requires the following: 1. configure the uart to be the generator to the desired irq. 2. configure other shared uarts to use no irq selected. 3. set the desired share irq bit. application note: if both uarts are configured to use differen t irqs and the share irq bit is set, then both of the uart irqs will assert when either uart generates an interrupt. ace uart irda sir sharp ask com ace registers output mux ir com host interface ir options register, bit 6
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 112 smsc sch311x datasheet table 8.8 , summarizes the various irq sharing configuratio ns. in this table, the following nomenclature is used: n/a - not applicable ns - port not shared s12 - uart 1 and uart 2 share an irq s34 - uart 3 and uart 4 share an irq s56 - uart 5 and uart 6 share an irq s1234 - uarts 1,2,3,4 share the same irq s1256 - uarts 1,2,5,6 share the same irq s3456 - uarts 3,4,5,6 share the same irq s123456 - all uarts share the same irq table 8.8 sch311x irq sharing summary device sp1 mode reg (0xf0) bit6 all share bit table 25.1 2 on page 304 sp1 mode reg (0xf0) bit7 sp12 share bit table 25.1 2 on page 304 sp3 mode reg (0xf0) bit7 sp34 share bit ta b l e 2 5 . 1 6 on page 307 sp5 mode reg (0xf0) bit7 sp56 share bit table 25.1 8 on page 308 sp1 sp2 sp3 sp4 sp5 sp6 sch3112 0 0 n/a n/a ns ns n/a n/a n/a n/a 0 1 n/a n/a s12 s12 n/a n/a n/a n/a 1 0 n/a n/a ns ns n/a n/a n/a n/a 1 1 n/a n/a s12 s12 n/a n/a n/a n/a sch3114 0 0 0 n/a nsnsnsnsn/an/a 010n/as12s12nsnsn/an/a 001n/ansnss34s34n/an/a 0 1 1 n/a s12 s12 s34 s34 n/a n/a 1 0 0 n/a nsnsnsnsn/an/a 110n/as12s12nsnsn/an/a 101n/ansnss34s34n/an/a 111n/as12 34 s12 34 s12 34 s12 34 n/a n/a
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 113 revision 0.4 (06-03-05) datasheet 8.3 rs485 auto direction control the purpose of this function is to save the effort to deal with direction control in software. a direction control signal (usually nrts) is used to tristate the transmitter when no other data is available, so that other nodes can use the shared lines. it is prefe rred to have this function on all six serial ports. this will affect the nrts and ndtr signals for each seri al port in the dev ice. each serial port will have the following additional characteristics: an option register for the serial port in the runtime registers with following bits: an enable bit to turn on/off the direction control an enable bit to select which bit nrts or ndtr, of the serial port is affected. a bit to select the polarity - high or low, that the selected signal is driven to when the output buffer of the corresponding serial port is empty or full. sch3116 0 0 0 0 nsnsnsnsnsns 0 1 0 0 s12s12nsnsnsns 0 0 1 0 nsnss34s34nsns 0 1 1 0 s12 s12 s34 s34 ns ns 0 0 0 1 nsnsnsnss56s56 0 1 0 1 s12 s12 ns ns s56 s56 0 0 1 1 ns ns s34 s34 s56 s56 0 1 1 1 s12 s12 s34 s34 s56 s56 1 0 0 0 nsnsnsnsnsns 1 1 0 0 s12s12nsnsnsns 1 0 1 0 nsnss34s34nsns 1110s12 34 s12 34 s12 34 s12 34 ns ns 1 0 0 1 nsnsnsnss56s56 1101s12 56 s12 56 ns ns s12 56 s12 56 1011nsnss34 56 s34 56 s34 56 s34 56 1111s12 345 6 s12 345 6 s12 345 6 s12 345 6 s12 345 6 s12 345 6 table 8.8 sch311x irq sharing summary (continued) device sp1 mode reg (0xf0) bit6 all share bit table 25.1 2 on page 304 sp1 mode reg (0xf0) bit7 sp12 share bit table 25.1 2 on page 304 sp3 mode reg (0xf0) bit7 sp34 share bit ta b l e 2 5 . 1 6 on page 307 sp5 mode reg (0xf0) bit7 sp56 share bit table 25.1 8 on page 308 sp1 sp2 sp3 sp4 sp5 sp6
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 114 smsc sch311x datasheet when automatic direction control is enabled, the device monitors the local output buffer for not empty and empty conditions. if enabled, the direction control will force the nrts or ndtr signal (selected via programming) to the desired polarity under the empty or not empty condition. ta b l e 8 . 9 summarizes the possible programming states. automatic direction control of the serial ports is only valid when the fifo is enabled. the multi-function gpio pins do not automatically set the direction when selected as serial port pins. the high speed baud rates will only work if the msb of the ms divisor is set. note: note that n/a indicates the signal is not affected under these conditions and maintains normal operation. a typical application using hw automatic direction control is shown in the following figure 8.4 on page 115 . in this figure the nrts signal is used to control direction. table 8.9 nrts/ndtr automatic direction control options local tx buffer state flow count en bit nrts/ ndtr sel bit polarity sel bit nrts ndtr x0xxn/an/a empty 1100n/a empty1111n/a not empty1101n/a not empty1110n/a empty 1 0 0 n/a 0 empty 1 0 1 n/a 1 not empty 1 0 0 n/a 1 not empty 1 0 1 n/a 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 115 revision 0.4 (06-03-05) datasheet figure 8.4 half duplex operat ion with direction control more detail on the programming of the autodirection control can be found in chapter 26, "runtime register," on page 311 . sp12 is the option register for serial port 1 and 2. sp34 is the option register for serial port 3 and 4. sp5 is the option register for serial port 5. sp6 is the option register for serial port 6. 8.4 reduced pin serial ports (sch3116 only) the sch3116 contains two, 4 pin serial ports (5/6), which will have multiplexed control signals. for each 4 pin port, there is a transmit, receive, input control and output control. the selection of the input and output control is done via a bit in the sp5/6 option register. figure 8.5 illustrates the how programming these bits selects the corresponding control signals. transmit receive receive transmit rx data tx data nrts / ndtr driver enable tx data rx data ncts / ndcd master device client device
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 116 smsc sch311x datasheet figure 8.5 reduce pin serial port control signal selection for sp5, the port signals are nrts5, ndtr5, nscout5 and nscin5. the nscout5 signal may be either nrts5 or ndtr5, selected via an sp5 option bit in a register. nscin mux ndcd mux nri (defa u mux ncts mux ndsr nrts ndtr (defa mux nscout "1" sp5/6 option register bit 0 6 option register bit[2:1] de mux =00 =01 =10 =11 1 0 1 0 1 0 1 0 "0" "0" "0" 1 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 117 revision 0.4 (06-03-05) datasheet the nscin5 signal may be either the ndsr5, ncts5, nri5 or ndcd5 signals, as selected via a bit in the sp5 option register. for sp6, the nscout6 signal may be either nrts6 or ndtr6, selected via sp6 option bit. the nscin6 signal may be either the ndsr6, ncts6, nri6 or ndcd6 signals, as selected via a bit in thesp6 option register. the programming for the sp5 and sp6 option register is given in chapter 26, "runtime register," on page 311 .
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 118 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 119 revision 0.4 (06-03-05) datasheet chapter 9 parallel port the sch311x incorporates an ibm xt/at compatible parallel port. this supports the optional ps/2 type bi-directional parallel port (spp), the enhanc ed parallel port (epp) and the extended capabilities port (ecp) parallel port modes. refer to the c onfiguration registers for information on disabling, power- down, changing the base address of the parallel port, and selecting the mode of operation. the parallel port also incorporates smsc?s chiprotect circuitry, which prevents possible damage to the parallel port due to printer power-up. the functionality of the parallel port is achieved through the use of eight addressable ports, with their associated registers and control gating. the control and data port are read/write by the cpu, the status port is read/write in th e epp mode. the address map of the parallel port is shown below: data port base address + 00h status port base address + 01h control port base address + 02h epp addr port base address + 03h epp data port 0 base address + 04h epp data port 1 base address + 05h epp data port 2 base address + 06h epp data port 3 base address + 07h the bit map of these registers is: d0 d1 d2 d3 d4 d5 d6 d7 note data port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 1 status port tmout 0 0 nerr slct pe nack nbusy 1 control port strobe autofd ninit slc irqe pcd 0 0 1 epp addr port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 0 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 2 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 epp data port 3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2 notes: 1. these registers are available in all modes. 2. these registers are onl y available in epp mode.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 120 smsc sch311x datasheet note: for the cable interconnection required for ecp support and the slave connector pin numbers, refer to the ieee 1284 extended capabilities port pr otocol and isa standard, rev. 1.14 , july 14, 1993. this document is available from microsoft. 9.1 ibm xt/at compatible, bi-directional and epp modes data port address offset = 00h the data port is located at an offset of ?00h? from the base address. the data register is cleared at initialization by reset. during a write operati on, the data register latches the contents of the internal data bus. the contents of this register are buffered (non inverting) and output onto the pd0 - pd7 ports. during a read operation in spp mode, pd0 - pd7 ports are buffered (not latched) and output to the host cpu. status port address offset = 01h the status port is located at an offset of ?01h? from the base address. the contents of this register are latched for the duration of a read cycle. the bits of the status port are defined as follows: bit 0 tmout - time out this bit is valid in epp mode only and indicates that a 10 usec ti me out has occurred on the epp bus. a logic o means that no time out error has occurred; a logic 1 means that a time out error has been detected. this bit is cleared by a reset. if the timeout_select bit (bit 4 of the paralle l port mode register 2, 0xf1 in logical device 3 configuration registers) is ?0?, writing a one to this bit clears the tmout status bit. writing a zero to this bit has no effect. if the timeout_select bit (bit 4 of the table 9.1 parallel port connector host connector pin number standard epp ecp 1 83 nstrobe nwrite nstrobe 2-9 68-75 pd<0:7> pdata<0:7> pdata<0:7> 10 80 nack intr nack 11 79 busy nwait busy, periphack(3) 12 78 pe (user defined) perror, nackreverse (3) 13 77 slct (user defined) select 14 82 nalf ndatastb nautofd, hostack(3) 15 81 nerror (user defined) nfault (1) nperiphrequest (3) 16 66 ninit nreset ninit(1) nreverserqst(3) 17 67 nslctin naddrstrb nselectin(1,3) (1) = compatible mode (3) = high speed mode
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 121 revision 0.4 (06-03-05) datasheet parallel port mode register 2, 0xf1 in logical device 3 configuration registers) is ?1?, the tmout bit is cleared on the trailing edge of a read of the epp status register. bits 1, 2 - are not implemented as register bits, during a read of the printer status register these bits are a low level. bit 3 nerr ? nerror the level on the nerror input is read by the cpu as bit 3 of the printer status register. a logic 0 means an error has been detected; a logic 1 means no error has been detected. bit 4 slt - printer selected status the level on the slct input is read by the cpu as bit 4 of the printer status register. a logic 1 means the printer is on line; a logic 0 means it is not selected. bit 5 pe - paper end the level on the pe input is read by the cpu as bit 5 of the printer status register. a logic 1 indicates a paper end; a logic 0 indicates the presence of paper. bit 6 nack - acknowledge the level on the nack input is read by the cpu as bit 6 of the printer status register. a logic 0 means that the printer has received a character and can now accept another. a logic 1 means that it is still processing the last char acter or has not received the data. bit 7 nbusy - nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the printer status register. a logic 0 in this bit means that the printer is busy and cannot accept a new character. a logic 1 means that it is ready to accept the next character. control port address offset = 02h the control port is located at an offset of ?02h? from the base address. the control register is initialized by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output onto the nautofd output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 ninit - initiate output this bit is output onto the ninit output without inversion. bit 3 slctin - printer select input this bit is inverted and output onto the nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 irqe - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu. an interrupt request is generated on the irq port by a positive going nack input. when the irqe bit is programmed low the irq is disabled.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 122 smsc sch311x datasheet bit 5 pcd - parallel control direction parallel control direction is not valid in printer mode. in printer mode, the direction is always out regardless of the state of this bit. in bi-directional, epp or ecp mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. epp address port address offset = 03h the epp address port is located at an offset of ?03h? from the base address. the address register is cleared at initialization by reset. during a wr ite operation, the contents of the internal data bus db0-db7 are buffered (non inverting) and out put onto the pd0 - pd7 ports. an lpc i/o write cycle causes an epp address write cycle to be performed, during which the data is latched for the duration of the epp write cycle. du ring a read operation, pd0 - pd7 ports are read. an lpc i/o read cycle causes an epp address read cycle to be performed and the data output to the host cpu, the deassertion of addrstb latches the pdata for the duration of the read cycle. this register is only available in epp mode. epp data port 0 address offset = 04h the epp data port 0 is located at an offset of ? 04h? from the base address. the data register is cleared at initialization by reset. during a writ e operation, the contents of the internal data bus db0-db7 are buffered (non inverting) and out put onto the pd0 - pd7 ports. an lpc i/o write cycle causes an epp data write cycle to be performed, during which the data is latched for the duration of the epp write cycle. during a r ead operation, pd0 - pd7 ports ar e read. an lpc i/o read cycle causes an epp read cycle to be performed and the data output to the host cpu, the deassertion of datastb latches the pdata for the du ration of the read cycle. this register is only available in epp mode. epp data port 1 address offset = 05h the epp data port 1 is located at an offset of ?05h? from the base address. refe r to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 2 address offset = 06h the epp data port 2 is located at an offset of ?06h? from the base address. refe r to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 3 address offset = 07h the epp data port 3 is located at an offset of ?07h? from the base address. refe r to epp data port 0 for a description of operation. this register is only available in epp mode. epp 1.9 operation when the epp mode is selected in the configuration register, th e standard and bi-directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10usec have elapsed from
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 123 revision 0.4 (06-03-05) datasheet the start of the epp cycle to nwait being deassert ed (after command). if a time-out occurs, the current epp cycle is aborted and the time-out condition is in dicated in status bit 0. during an epp cycle, if strobe is active, it overrides the epp write signal forcing the pdx bus to always be in a write mode and the nwrite signal to always be asserted. software constraints before an epp cycle is executed, the software must ensure that the c ontrol register bit pcd is a logic ?0? (i.e., a 04h or 05h should be written to the co ntrol port). if the user leaves pcd as a logic ?1?, and attempts to perform an epp write, the chip is una ble to perform the write (because pcd is a logic ?1?) and will appear to perform an epp read on the parallel bus, no error is indicated. epp 1.9 write the timing for a write operation (address or data) is shown in timing diagram epp write data or address cycle. the chip inserts wa it states into the lpc i/o writ e cycle until it has been determined that the write cycle can complete . the write cycle can complete under the following circumstances: if the epp bus is not ready (nwait is active lo w) when ndatastb or nad drstb goes active then the write can complete when nwait goes inactive high. if the epp bus is ready (nwait is inactive high) then the chip must wait for it to go active low before changing the state of ndatastb, nwrite or naddrstb. the write can complete once nwait is determined inactive. write sequence of operation 1. the host initiates an i/o write cycle to the selected epp register. 2. if wait is not asserted, the chip must wait until wait is asserted. 3. the chip places address or data on pd ata bus, clears pdir, and asserts nwrite. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. 5. peripheral deasserts nwait, indicating that any setup requirements have been satisfied and the chip may begin the termination phase of the cycle. 6. a. the chip deasserts ndatastb or naddrstrb, this marks the beginning of the termination phase. if it has not already done so, the peripheral should latch the information byte now. b. the chip latches the data from the internal data bus for the pdata bus and drives the sync that indicates that no more wait stat es are required followed by the tar to complete the write cycle. 7. peripheral asserts nwait, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 8. chip may modify nwrite and npda ta in preparation for the next cycle. epp 1.9 read the timing for a read operation (data) is show n in timing diagram epp read data cycle. the chip inserts wait states into the lpc i/o read cycle un til it has been determined that the read cycle can complete. the read cycle can complete under the following circumstances: if the epp bus is not ready (nwait is active low) when ndatastb goes active then the read can complete when nwait goes inactive high. if the epp bus is ready (nwait is inactive high) then the chip must wait for it to go active low before changing the state of nwrite or before ndatastb goes active. the read can complete once nwait is determined inactive. read sequence of operation 1. the host initiates an i/o read cycle to the selected epp register. 2. if wait is not asserted, the chip must wait until wait is asserted.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 124 smsc sch311x datasheet 3. the chip tri-states the pdata bus and deasserts nwrite. 4. chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. 5. peripheral drives pdata bus valid. 6. peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phase of the cycle. 7. a. the chip latches the data from the pdata bus for the internal data bus and deasserts ndatastb or naddrstrb. this marks the beginning of the termination phase. b. the chip drives the sync that indicates that no mo re wait states are required and drives valid data onto the lad[3:0] signals, followed by the tar to complete the read cycle. 8. peripheral tri-states the pdata bus and asserts nwait, indicating to the host that the pdata bus is tri-stated. 9. chip may modify nwrite, pdir and npdata in preparation for the next cycle. epp 1.7 operation when the epp 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10usec have elapsed from the start of the epp cycle to the en d of the cycle. if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0. software constraints before an epp cycle is executed, the software must ensure that the co ntrol register bits d0, d1 and d3 are set to zero. also, bit d5 (pcd) is a logic ?0? for an epp write or a logic ?1? for and epp read. epp 1.7 write the timing for a write o peration (address or data) is shown in timing diagram epp 1.7 write data or address cycle. the chip inserts wait states into the i/o write cycle when nwait is active low during the epp cycle. this can be used to extend the cycle time. the write cycle can complete when nwait is inactive high. write sequence of operation the host sets pdir bit in the control register to a logic ?0?. this asserts nwrite. the host initiates an i/o write cycle to the selected epp register. the chip places address or data on pdata bus. chip asserts ndatastb or naddrstrb indicating that pdata bus contains valid information, and the write signal is valid. if nwait is asserted, the chip in serts wait states into i/o write cycle until the peripheral deasserts nwait or a time-out occurs. the chip drives the final sync, deasserts ndatastb or naddrstrb and latches the data from the internal data bus for the pdata bus. chip may modify nwrite, pdir and npdata in preparation of the next cycle. epp 1.7 read the timing for a read operation (data) is shown in timing diagram epp 1.7 re ad data cycle. the chip inserts wait states into the i/o read cycle when nwait is active low during the epp cycle. this can be used to extend the cycle time. the read cycle can complete when nwai t is inactive high.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 125 revision 0.4 (06-03-05) datasheet read sequence of operation the host sets pdir bit in the control register to a logic ?1?. this deasserts nwrite and tri-states the pdata bus. the host initiates an i/o read cycle to the selected epp register. chip asserts ndatastb or naddrstrb indicating that pdata bus is tri-stated, pdir is set and the nwrite signal is valid. if nwait is asserted, t he chip inserts wait states into the i/o read cycle unt il the peripheral deasserts nwait or a time-out occurs. the peripheral drives pdata bus valid. the peripheral deasserts nwait, indicating that pdata is valid and the chip may begin the termination phas e of the cycle. the chip drives the final sync and deasserts ndatastb or naddrstrb. peripheral tri-states the pdata bus. chip may modify nwrite, pdir and npdata in preparation of the next cycle. table 9.2 epp pin descriptions epp signal epp name type epp description nwrite nwrite o this signal is active low. it denotes a write operation. pd<0:7> address/data i/o bi-directional epp byte wide address and data bus. intr interrupt i this signal is active high and positive edge triggered. (pass through with no inversion, same as spp). nwait nwait i this signal is active low. it is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. it is driven active as an indication that the device is ready for the next transfer. ndatastb ndata strobe o this signal is active low. it is used to denote data read or write operation. nreset nreset o this signal is active low. when driven active, the epp device is reset to its initial operational mode. naddrstb address strobe o this signal is active low. it is used to denote address read or write operation. pe paper end i same as spp mode. slct printer selected status i same as spp mode. nerr error i same as spp mode. notes: 1. spp and epp can use 1 common register. 2. nwrite is the only epp output that can be over-rid den by spp control port during an epp cycle. for correct epp read cycles, pcd is required to be a low.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 126 smsc sch311x datasheet 9.2 extended capabi lities parallel port ecp provides a number of advantages, some of whic h are listed below. the individual features are explained in greater detail in the remainder of this section. high performance half-duplex forward and revers e channel interlocked handshake, for fast reliable transfer optional single byte rle compression for improved throughput (64:1) channel addressing for low-cost peripherals maintains link and data layer separation permits the use of active output drivers permits the use of adaptive signal timing peer-to-peer capability. vocabulary the following terms are used in this document: assert: when a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward: host to peripheral communication. reverse: peripheral to host communication pword: a port word; equal in size to the width of the lpc interface. for this implementation, pword is always 8 bits. 1 a high level. 0 a low level. these terms may be considered synonymous: periphclk, nack hostack, nautofd periphack, busy nperiphrequest, nfault nreverserequest, ninit nackreverse, perror xflag, select ecpmode, nselectln hostclk, nstrobe reference document: ieee 1284 extended capabilities port protocol and isa interface standard , rev 1.14, july 14, 1993. this document is available from microsoft.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 127 revision 0.4 (06-03-05) datasheet the bit map of the extended parallel port registers is: ecp implementation standard this specification describes the standard interface to the extended capabilities port (ecp). all lpc devices supporting ecp must meet the requirements contained in this section or the port will not be supported by microsoft. for a description of the ecp protocol, please refer to the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.14 , july 14, 1993. this document is available from microsoft. description the port is software and hardware compatible with ex isting parallel ports so that it may be used as a standard lpt port if ecp is not required. the po rt is designed to be simple and requires a small number of gates to implement. it does not do any ?protocol? negotiation, rather it provides an automatic high burst-bandwidth channel that supports dma for ecp in both the forward and reverse directions. small fifos are employed in both forward and reve rse directions to smooth data flow and improve the maximum bandwidth requirement. the size of the fifo is 16 bytes deep. the port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the port also supports run length encoded (rle ) decompression (required) in hardware. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. hardware support for compression is optional. d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/rle address or rle field 2 dsr nbusy nack perror select nfault 0 0 0 1 dcr 0 0 direction ackinten selecti n ninit autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue parallel port irq parallel port dma ecr mode nerrintre n dmaen service intr full empty notes: 1. these registers are available in all modes. 2. all fifos use one common 16 byte fifo. 3. the ecp parallel port config reg b reflects the irq and dma channel selected by the configuration registers.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 128 smsc sch311x datasheet register definitions the register definitions are based on the standard ibm addresses for lpt. all of the standard printer ports are supported. the additional registers attach to an upper bit decode of the standard lpt port definition to avoid conflict with standard isa devices. the port is equivalent to a generic parallel port interface and may be operated in that mode. the port registers vary depending on the mode field in the ecr. ta b l e 9 . 4 lists these dependencies. operation of the devices in modes other that those specified is undefined. table 9.3 ecp pin descriptions name type description nstrobe o during write operations nstrobe regist ers data or address into the slave on the asserting edge (handshakes with busy). pdata 7:0 i/o contains address or data or rle data. nack i indicates valid data driven by the peripheral when asserted. this signal handshakes with nautofd in reverse. periphack (busy) i this signal deasserts to indicate that the peripheral can accept data. this signal handshakes with nstrobe in the forward direction. in the reverse direction this signal indicates whether the data lines contain ecp command information or data. the peripheral us es this signal to automatic direction control in the forward direction. it is an ?interlocked? handshake with nstrobe. periphack also provides command information in the reverse direction. perror (nackreverse) i used to acknowledge a change in the direction the transfer (asserted = forward). the peripheral drives this signal low to acknowledge nreverserequest. it is an ?interlo cked? handshake with nreverserequest. the host relies upon nackreverse to determine when it is permitted to drive the data bus. select i indicates printer on line. nautofd (hostack) o requests a byte of data from the peripheral when asserted, handshaking with nack in the reverse direction. in the forward direction this signal indicates whether the data lines contain ecp addres s or data. the host drives this signal to automatic direction control in the reverse direction. it is an ?interlocked? handshake with nack. hostack also provides command information in the forward phase. nfault (nperiphrequest) i generates an error interrupt when asserted. this signal provides a mechanism for peer-to-peer communication. this signal is valid only in the forward direction. during ecp mode the peripheral is permitted (but not required) to drive this pin low to request a reverse tr ansfer. the request is merely a ?hint? to the host; the host has ultimate control over the transfer direction. this signal would be typically used to generate an interrupt to the host cpu. ninit o sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the channel in the reverse direction. the peripheral is only allowed to drive the bi-directional data bus while in ecp mode and hostack is low and nselectin is high. nselectin o always deasserted in ecp mode.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 129 revision 0.4 (06-03-05) datasheet data and ecpafifo port address offset = 00h modes 000 and 001 (data port) the data port is located at an offset of ?00h? from the base address. the data register is cleared at initialization by reset. during a write operation, the data register latche s the contents of the data bus. the contents of this register are buffered (non inverting) and output onto the pd0 - pd7 ports. during a read operation, pd0 - pd7 ports are read and output to the host cpu. table 9.4 ecp register definitions name address (note 1) ecp modes function data +000h r/w 000-001 data register ecpafifo +000h r/w 011 ecp fifo (address) dsr +001h r/w all status register dcr +002h r/w all control register cfifo +400h r/w 010 parallel port data fifo ecpdfifo +400h r/w 011 ecp fifo (data) tfifo +400h r/w 110 test fifo cnfga +400h r 111 configuration register a cnfgb +401h r/w 111 configuration register b ecr +402h r/w all extended control register notes: 1. these addresses are added to the parallel port base addre ss as selected by configuration register or jumpers. 2. all addresses are qualified with aen. refer to the aen pin definition. table 9.5 mode descriptions mode description* 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the configur ation registers) 101 reserved 110 test mode 111 configuration mode *refer to ecr register description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 130 smsc sch311x datasheet mode 011 (ecp fifo - address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits this byte to the peripheral automatically. the operation of this register is only defined for the forward direction (direction is 0). refer to pme_sts1, located in pme_sts1 of this data sheet. device status register (dsr) address offset = 01h the status port is located at an offset of ?01h? from the base address. bits0 - 2 are not implemented as register bits, during a read of the printer status register these bits are a low level. the bits of the status port are defined as follows: bit 3 nfault the level on the nfault input is read by the cpu as bit 3 of the device status register. bit 4 select the level on the select input is read by the cpu as bit 4 of the device status register. bit 5 perror the level on the perror input is read by the cpu as bit 5 of the device status register. printer status register. bit 6 nack the level on the nack input is read by the cpu as bit 6 of the device status register. bit 7 nbusy the complement of the level on the busy input is read by the cpu as bit 7 of the device status register. device control register (dcr) address offset = 02h the control register is located at an offset of ?02h? from the base address. the control register is initialized to zero by the reset in put, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the nstrobe output. bit 1 autofd - autofeed this bit is inverted and output onto the nautofd output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 ninit - initiate output this bit is output onto the ninit output without inversion. bit 3 selectin this bit is inverted and output onto the nslctin output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 ackinten - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the nack input. refer to the description of the interrupt under operation, interrupts.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 131 revision 0.4 (06-03-05) datasheet bit 5 direction if mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. in all other modes, direction is vali d and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. cfifo (parallel port data fifo) address offset = 400h mode = 010 bytes written or dmaed from the system to this fi fo are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. transfers to the fifo are byte aligned. this mode is only defined for the forward direction. ecpdfifo (ecp data fifo) address offset = 400h mode = 011 bytes written or dmaed from the system to this fi fo, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ec p parallel port protocol. transfers to the fifo are byte aligned. data bytes from the peripheral are read under autom atic hardware handshake from ecp into this fifo when the direction bit is 1. reads or dmas from the fifo will retu rn bytes of ecp data to the system. tfifo (test fifo mode) address offset = 400h mode = 110 data bytes may be read, written or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the to the parallel port lines using a hardware protocol handshake. however, data in the tfifo may be displayed on the parallel port data lines. the tfifo will not stall when overwritten or underrun . if an attempt is made to write data to a full tfifo, the new data is not accepted into the tfifo. if an attempt is made to read data from an empty tfifo, the last data byte is re-read again. the full and empty bits must always keep track of the correct fifo state. the tfifo will transfer data at the maximum isa rate so that software may generate performance metrics. the fifo size and interrupt threshold can be deter mined by writing bytes to the fifo and checking the full and serviceintr bits. the writeintrthreshold can be determined by starting with a full tfifo, setting the direction bit to 0 and emptying it a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. the readintrthreshold can be determined by setting the directi on bit to 1 and filling the empty tfifo a byte at a time until serviceintr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. data bytes are always read from the head of tfifo regardless of the value of the direction bit. for example if 44h, 33h, 22h is written to the fifo, then reading the tfifo will return 44h, 33h, 22h in the same order as was written.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 132 smsc sch311x datasheet cnfga (configuration register a) address offset = 400h mode = 111 this register is a read only register. when read, 10h is retu rned. this indicates to the system that this is an 8-bit implementation. (pword = 1 byte) cnfgb (configuration register b) address offset = 401h mode = 111 bit 7 compress this bit is read only. during a read it is a low level. this means that this chip does not support hardware rle compression. it does support hardware de-compression. bit 6 intrvalue returns the value of the interrupt to determine possible conflicts. bit [5:3] parallel port irq (read-only) to table 9.7 on page 134 . bits [2:0] parallel port dma (read-only) to table 9.8 on page 134 . ecr (extended control register) address offset = 402h mode = all this register controls the extended ecp parallel port functions. bits 7,6,5 these bits are read/write and select the mode. bit 4 nerrintren read/write (valid only in ecp mode) 1: disables the interrupt generated on the asserting edge of nfault. 0: enables an interrupt pulse on the high to low edge of nfault. note that an interrupt will be generated if nfault is asserted (interrupting) and th is bit is written from a 1 to a 0. this prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. bit 3 dmaen read/write 1: enables dma (dma starts when serviceintr is 0). 0: disables dma unconditionally. bit 2 serviceintr read/write 1: disables dma and all of the service interrupts.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 133 revision 0.4 (06-03-05) datasheet 0: enables one of the following 3 cases of interrupts. once one of the 3 service interrupts has occurred serviceintr bit shall be set to a 1 by hardware. it must be reset to 0 to re-enable the interrupts. writing this bit to a 1 will not cause an interrupt. case dmaen=1: during dma (this bit is set to a 1 when terminal count is reached). case dmaen=0 direction=0: this bit shall be set to 1 whenever there are wr iteintrthreshold or more bytes free in the fifo. case dmaen=0 direction=1: this bit shall be set to 1 whenever there are read intrthreshold or more valid bytes to be read from the fifo. bit 1 full read only 1: the fifo cannot accept another byte or the fifo is completely full. 0: the fifo has at least 1 free byte. bit 0 empty read only 1: the fifo is completely empty. 0: the fifo contains at least 1 byte of data. table 9.6 extended control register (a) r/w mode 000: standard parallel port mode. in this mode the fifo is reset and common drain drivers are used on the control lines (nstrobe, nautofd, ninit and nselectin). setting the direction bit will not tri-state the output drivers in this mode. 001: ps/2 parallel port mode. same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. all drivers have active pull-ups (push-pull). 010: parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data is automatically transmitted using the stan dard parallel port protocol. note that this mode is only useful when direction is 0. al l drivers have active pull-ups (push-pull). 011: ecp parallel port mode. in the forward direction (dir ection is 0) bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protocol. in the reverse direction (direction is 1) bytes are moved from the ecp parallel port and packed into bytes in the ecpdfifo. all drivers have active pull-ups (push-pull). 100: selects epp mode: in this mode, epp is select ed if the epp supported option is selected in configuration register l3-crf0. all drivers have active pull-ups (push-pull). 101: reserved 110: test mode. in this mode the fifo may be writt en and read, but the data will not be transmitted on the parallel port. all drivers have active pull-ups (push-pull). 111: configuration mode. in this mode the confga, confgb registers are accessible at 0x400 and 0x401. all drivers have active pull-ups (push-pull).
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 134 smsc sch311x datasheet operation mode switching/software control software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001). hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (modes 011 or 010). setting the mode to 011 or 010 will cause the hardware to initiate data transfer. if the port is in mode 000 or 001 it may switch to any other mode. if the port is not in mode 000 or 001 it can only be switched into mode 000 or 001. the direction can only be changed in mode 001. once in an extended forward mode the software should wait for the fifo to be empty before switching back to mode 000 or 001. in this case all control signals will be deasserted before the mode switch. in an ecp reverse mode the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. since the automatic hardware ecp reverse handshake only cares about the state of the fifo it may have acquired extra data which will be discarded. it may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. in this case the port will deassert nautofd independent of the state of the transfer. the design shall not cause glitches on the handshake signals if the software meets the constraints above. table 9.7 extended control register (b) irq selected config reg b bits 5:3 15 110 14 101 11 100 10 011 9 010 7 001 5 111 all others 000 table 9.8 extended control register (c) irq selected config reg b bits 5:3 3011 2 010 1 001 all others 000
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 135 revision 0.4 (06-03-05) datasheet ecp operation prior to ecp operation the host must negotiate on the parallel port to determine if the peripheral supports the ecp protocol. this is a so mewhat complex negotiation carried out under program control in mode 000. after negotiation, it is necessary to initialize some of the port bits. the following are required: set direction = 0, enabling the drivers. set strobe = 0, causing the nstrobe signal to default to the deasserted state. set autofd = 0, causing the nautofd signal to default to the deasserted state. set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo respectively. note that all fifo data transfers are byte wide and by te aligned. address/rle transfers are byte-wide and only allowed in the forward direction. the host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. when direction is 1 the hardware shall handshake for each ecp read data byte and attempt to fill the fifo. bytes may then be read from the ecpdfifo as long as it is not empty. ecp transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. termination from ecp mode termination from ecp mode is similar to the termi nation from nibble/byte modes. the host is permitted to terminate from ecp mode only in specific well-defined states. the termination can only be executed while the bus is in the forward direction. to terminate while the channel is in the reverse direction, it must first be transitioned into the forward direction. command/data ecp mode supports two advanced features to improv e the effectiveness of the protocol for some applications. the features are im plemented by allowing the transfer of normal 8 bit data or 8 bit commands. when in the forward direction, normal data is transferred when hostack is high and an 8 bit command is transferred when hostack is low. the most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. when in the reverse direction, normal data is transferred when periphack is high and an 8 bit command is transferred when periphack is low. the most significant bit of the command is always zero. reverse channel addresses are seldom used and may not be supported in hardware. table 9.9 channel/data commands supported in ecp mode forward channel commands (hostack low) reverse channel commands (peripack low) d7 d[6:0] 0 run-length count (0-127) (mode 0011 0x00 only) 1 channel address (0-127)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 136 smsc sch311x datasheet data compression the ecp port supports run length encoded (rle ) decompression in hardware and can transfer compressed data to a peripheral. run length encoded (rle) compression in hardware is not supported. to transfer compressed data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. when a run-length count is received from a peripheral, the subsequent data byte is replicated th e specified number of times. a run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. to prevent data expansion, however, run-length counts of zero should be avoided. pin definition the drivers for nstrobe, nautofd, ninit and nselectin are open-drain in mode 000 and are push-pull in all other modes. lpc connections the interface can never stall causing the host to hang. the width of data transfers is strictly controlled on an i/o address basis per this specification. all fi fo-dma transfers are byte wide, byte aligned and end on a byte boundary. (the pword value can be obtained by reading configuration register a, cnfga, described in the next section). single byte wide transfers are always possible with standard or ps/2 mode using program control of the control signals. interrupts the interrupts are enabled by serviceintr in the ecr register. serviceintr = 1 disables the dma and all of the service interrupts. serviceintr = 0 enables the selected interrupt condition. if the interrupting condition is valid, then the interrupts generated immediately when this bit is changed from a 1 to a 0. this can occur during programmed i/o if the number of bytes removed or added from/to the fifo does not cross the threshold. an interrupt is generated when: 1. for dma transfers: when serv iceintr is 0, dmaen is 1 a nd the dma tc cycle is received. 2. for programmed i/o: a. when serviceintr is 0, dmaen is 0, direction is 0 and there are writeintrthreshold or more free bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are writeintrthreshold or more free bytes in the fifo. b. when serviceintr is 0, dmaen is 0, direction is 1 and there are readintrthreshold or more bytes in the fifo. also, an interrupt is generated when serviceintr is cleared to 0 whenever there are readintrthreshold or more bytes in the fifo. 3. when nerrintren is 0 and nfault transitions from high to low or when nerrintren is set from 1 to 0 and nfault is asserted. 4. when ackinten is 1 and the nack signal transitions from a low to a high. fifo operation the fifo threshold is set in the chip configuration r egisters. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non- dma) mode as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port mode. (fifo test mode will be addressed separately.) after a reset, the fifo is disabled. each data byte is transferred by a programmed i/o cycle or dma cycle dependi ng on the selection of dma or programmed i/o mode.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 137 revision 0.4 (06-03-05) datasheet the following paragraphs detail the operation of the fifo automatic direction control. in these descriptions, ranges from 1 to 16. th e parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and wr ite cases. the host must be very responsive to the service request. this is the desired case for use with a ?fast? system. a high value of threshold (i.e. 12) is used with a ?sluggish? system by affording a long latency period after a service request, but results in more frequent service requests. dma transfers dma transfers are always to or from the ecpdfifo, tfifo or cfif o. dma utilizes the standard pc dma services. to use the dma transfers, the host first sets up the direction and state as in the programmed i/o case. then it programs the dma controller in the host with the desired count and memory address. lastly it sets dmaen to 1 and serviceintr to 0. the ecp requests dma transfers from the host by encoding the ldrq# pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma c ontroller is reached, an interrupt is generated and serviceintr is asserted, disabling dma. in order to prevent possible blocking of refresh requests a dma cycle shall not be requested for more than 32 dma cy cles in a row. the fifo is enabled directly by the host initiating a dma cycle for the requested channel, and addresses need not be valid. an interrupt is generated when a tc cycle is received. (note: the only way to properly terminate dma transfers is with a tc cycle.) dma may be disabled in the middle of a transfer by first disabling the host dma controller. then setting serviceintr to 1, followed by setting dmaen to 0, and waiting for the fifo to become empty or full. restarting the dma is accomplished by enabling dma in the host, setting dmaen to 1, followed by setting serviceintr to 0. dma mode - transfers from the fifo to the host note: in the reverse mode, the peripheral may not continue to fill the fifo if it runs out of data to transfer, even if the chip continues to request more data from the peripheral.) the ecp requests a dma cycl e whenever there is data in the fifo. the dma controller must respond to the request by reading data from the fifo. the ecp stops re questing dma cycles when the fifo becomes empty or when a tc cycle is received, indicating that no mo re data is required. if the ecp stops requesting dma cycles due to the fifo goi ng empty, then a dma cycle is requested again as soon as there is one byte in th e fifo. if the ecp stops requesti ng dma cycles due to the tc cycle, then a dma cycle is requested again when there is one byte in the fifo, and serviceintr has been re-enabled. programmed i/o mode or non-dma mode the ecp or parallel port fifos may also be operated using interrupt driven programmed i/o. software can determine the writeintrthreshold, readintrthreshold, and fifo depth by accessing the fifo in test mode. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. to use the programmed i/o transfers, the host first sets up the direction and state, sets dmaen to 0 and serviceintr to 0. the ecp requests programmed i/o transfers from the host by activating the interrupt. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. note: a threshold of 16 is equivalent to a threshold of 15. these two cases are treated the same. programmed i/o - transfers fr om the fifo to the host in the reverse direction an interrupt occurs when serviceintr is 0 and readintrthreshold bytes are available in the fifo. if at this time the fifo is full it can be emptied completely in a single burst, otherwise readintrthreshold bytes may be read from the fifo in a single burst.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 138 smsc sch311x datasheet readintrthreshold =(16-) data bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is greater than or equal to (16-). (if the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the fifo). the host must respond to the request by reading data from the fifo. this process is repeated until the last byte is transferred out of the fi fo. if at this time the fifo is full, it can be completely emptied in a single burst, otherwise a minimum of (16-) bytes may be read from the fifo in a single burst. programmed i/o - transfers fr om the host to the fifo in the forward direction an interrupt occurs when serviceintr is 0 and there are writeintrthreshold or more bytes free in the fifo . at this time if the fifo is empty it can be filled with a single burst before the empty bit needs to be re-read. otherwise it may be filled with writeintrthreshold bytes. writeintrthreshold = (16-) free bytes in fifo an interrupt is generated when serviceintr is 0 and the number of bytes in the fifo is less than or equal to . (if the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the fifo.) the host must respond to the request by writing data to the fifo. if at this time the fifo is empty, it can be completely filled in a single burst, otherwise a minimum of (16- ) bytes may be written to the fifo in a si ngle burst. this process is repeated until the last byte is transferred into the fifo. 9.3 parallel port fl oppy disk controller the floppy disk control signals are available optio nally on the parallel port pins. when this mode is selected, the parallel port is not available. there are two modes of operation, ppfd1 and ppfd2. these modes can be selected in the fdc on pp register, as defined in logical device 0xa, at 0xf1. ppfd1 has only drive 1 on the parallel port pins; ppfd2 has drive 0 and 1 on the parallel port pins. the fdc pins associated with the parallel port pins are summarized in ta b l e 9 . 1 0 . there are 3 possible modes of operation: normal mode (default) - drive 0 is on the fdc pins, the parallel port acts as a parallel port mode 1 -drive 0 is on the fdc pins, drive 1 is on the pp pins mode 2 -drive 0/1 are on the pp pins. table 9.10 parallel port floppy pin out connector pin # parallel port spp mode fdc mode 1 fdc mode 2 signal name pin direction signal name pin direction signal name pin direction 1 nstrobe i/o - tristate nds0 o 2 pd0 i/o nindex i nindex i 3 pd1 i/o ntrk0 i ntrk0 i 4 pd2 i/o nwp i nwp i 5 pd3 i/o nrdata i nrdata i 6 pd4 i/o ndskchg i ndskchg i 7 pd5 i/o-- -- 8 pd6 i/o - tristate nmtr0 o 9 pd7 i/o-- --
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 139 revision 0.4 (06-03-05) datasheet 9.3.1 buffer types the buffer types of the parallel port pins are summarized in ta b l e 9 . 11 . 10 nack i nds1 o nds1 o 11 busy i nmtr1 o nmtr1 o 12 pe i nwdata o nwdata o 13 slct i nwgate o nwgate o 14 nalf i/o drvden0 o drvden0 o 15 nerr i nhdsel o nhdsel o 16 ninit i/o ndir o ndir o 17 nslctin i/o nstep o nstep o table 9.11 pp buffer types parallel port i/f fdc i/f pp buffer fdc buffer ninit ndir (od14/op14) od14 nslctin nstep (od14/op14) od14 pd0 nindex iop14 i pd1 ntrk0 iop14 i pd2 nwp iop14 i pd3 nrdata iop14 i pd4 ndskchg iop14 i pd5 - iop14 - pd6 nmtr0 iop14 i pd7 - iop14 - slct nwgate i od12 pe nwdata i od12 busy nmtr1 i nmtr1 nack nds1 i nds1 nerror nhdsel i od12 nalf drvden0 (od14/op14) od14 nstrobe nds0 (od14/op14) od14 table 9.10 parallel port floppy pin out (continued) connector pin # parallel port spp mode fdc mode 1 fdc mode 2 signal name pin direction signal name pin direction signal name pin direction
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 140 smsc sch311x datasheet 9.3.2 fdc/pp control bits parallel port fdc control bits are in the fdc on pp register (configuration register 0xf1 in logical device 0xa). refer to table 25.15 on page 306 for more details.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 141 revision 0.4 (06-03-05) datasheet chapter 10 power management power management capabilities are provided for the following logical devices: floppy disk, uart 1, uart 2 and the parallel port. note: each logical device may be place in powerdown mode by clearing the associated activate bit located at cr30 or by clearing the associated power bit located in the power control register at cr22. fdc power management direct power management is controlled by cr22. refer to cr22 for more information. fdd interface pins all pins in the fdd interface which can be connected directly to the floppy disk drive itself are either disabled or tristated. table 10.1, "state of floppy disk drive interface pins in powerdown" depicts the state of the floppy disk drive interface pins in the powerdown state. table 10.1 state of floppy disk drive interface pins in powerdown fdd pins state in powerdown input pins nrdata input nwrtprt input ntrk0 input nindex input ndskchg input output pins nmtr0 tristated nds0 tristated ndir tristated nstep tristated nwdata tristated nwgate tristated nhdsel tristated drvden[0:1] tristated
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 142 smsc sch311x datasheet uart power management direct power management is controlled by cr22. refer to cr22 for more information. parallel port direct power management is controlled by cr22. refer to cr22 for more information.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 143 revision 0.4 (06-03-05) datasheet chapter 11 serial irq the sch311x supports the serial interrupt to transmit in terrupt information to the host system. the serial interrupt scheme adheres to the serial irq specification for pci systems, version 6.0. timing diagrams for ser_irq cycle a. start frame timing with source sampled a low pulse on irq1 notes: 1. h=host control; r=recovery; t=turn-around; sl=slave control; s=sample 2. start frame pulse can be 4-8 clocks wide depending on the location of the device in the pci bridge hierarchy in a synchronous bridge design. b. stop frame timing with host using 17 ser_irq sampling period notes: 1. h=host control; r=recovery; t=turn-around; s=sample; i=idle 2. the next ser_irq cycle? s start frame pulse may or may not start immediately after the turn- around clock of the stop frame. 3. there may be none, one or more idle states during the stop frame. 4. stop pulse is 2 clocks wide for quiet mode, 3 clocks wide for continuous mode. ser_irq cycle control there are two modes of operation for the ser_irq start frame 1. quiet (active) mode : any device may initiate a start frame by driving the ser_irq low for one clock, while the ser_irq is idle. after driving low for one clock the ser_irq must immediately be tri-stated without at any time driving high. a start frame may not be initiated while the ser_irq is active. the ser_irq is idle betw een stop and start frames. the ser_irq is active between start and stop frames. this mode of operati on allows the ser_irq to be idle when there are no irq/data transitions which should be most of the time. rt s rt s ser_irq pci_clk host controller irq1 irq1 drive source rt none irq0 frame irq1 frame s rt irq2 frame none start start frame h sl or h 1 s r t s ser_irq pci_clk host controller irq15 driver r t none irq14 irq15 s r t iochck# none stop r t stop frame h i start next cycle 1 2 3 frame frame frame
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 144 smsc sch311x datasheet once a start frame has been initia ted the host controller will take over driving the ser_irq low in the next clock and will continue dr iving the ser_irq low fo r a programmable perio d of three to seven clocks. this makes a total low pulse width of four to eight clocks. fi nally, the host controller will drive the ser_irq back high for one clock, then tri-state. any ser_irq device (i.e., the sch311x which detects any transition on an irq/data line for which it is responsible must initiate a start frame in order to update the host controller unless the ser_irq is already in an ser_irq cycle and the irq/data transition can be delivered in that ser_irq cycle 2. continuous (idle) mode : only the host controller can initiate a start frame to update irq/data line information. all other ser_irq agents become passive and may not initiate a start frame. ser_irq will be driven low for four to eight cloc ks by host controller. this mode has two functions. it can be used to stop or idle the ser_irq or the host controller can operate ser_irq in a continuous mode by initiating a st art frame at the end of every stop frame. an ser_irq mode transition can only occur durin g the stop frame. upon reset, ser_irq bus is defaulted to continuous mode, therefore only the host controller can initiate the first start frame. slaves must continuously sample the stop frames pulse width to determine the next ser_irq cycle?s mode. ser_irq data frame once a start frame has been initiated, the sch311x will watch for the rising edge of the start pulse and start counting irq/data frames from there. each irq/data fram e is three clocks: sample phase, recovery phase, and turn-around phase. during the sample phase the sch311x must drive the ser_irq low, if and only if, its last detected irq/ data value was low. if it s detected irq/data value is high, ser_irq must be left tri-stated. during the recovery phase the sch311x must drive the ser_irq high, if and only if, it had driven the ser_irq low during the previous sample phase. during the turn-around phase the sch311x must tri-state the ser_irq. the sch311x will drive the ser_irq line low at the appropriate sample point if its associated irq/data line is low, regardless of which device initiated the start frame. the sample phase for each irq/data follows the low to high transition of the start frame pulse by a number of clocks equal to the irq/data frame times three, minu s one. (e.g. the irq5 sample clock is the sixth irq/data frame, (6 x 3) - 1 = 17 th clock after the rising edge of the start pulse). ser_irq samp ling periods ser_irq period signal sample d # of clocks past start 1 not used 2 2irq1 5 3 nio_smi/irq2 8 4irq3 11 5irq4 14 6irq5 17 7irq6 20 8irq7 23 9irq8 26 10 irq9 29 11 irq10 32 12 irq11 35
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 145 revision 0.4 (06-03-05) datasheet the ser_irq data frame supports irq2 from a logica l device on period 3, which can be used for the system management interrupt (nsmi). when using period 3 for irq2 the user should mask off the smi via the smi enable register. likewise, when using period 3 for nsmi the user should not configure any logical devices as using irq2. ser_irq period 14 is used to transfer irq13. logical devices 0 (fdc), 3 (par port), 4 (ser port 1), 5 (ser port 2), and 7 (kbd) shall have irq13 as a choice for their primary interrupt. the smi is enabled onto the smi frame of the serial irq via bit 6 of smi enable register 2 and onto the nio_smi pin via bit 7 of the smi enable register 2. stop cycle control once all irq/data frames have completed the host controller will terminate ser_irq activity by initiating a stop frame. only the host controller can initiate the stop frame. a stop frame is indicated when the ser_irq is low for two or three clocks. if the stop frame?s low time is two clocks then the next ser_irq cycle?s sampled mode is the quiet mode; and any ser_irq device may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. if the stop frame?s low time is three clocks then the next ser_irq cycle?s sampled mode is the continuos mode; and only the host controller may initiate a start frame in the second clock or more after the rising edge of the stop frame?s pulse. latency latency for irq/data updates over the ser_irq bus in bridge-less systems with the minimum host supported irq/data frames of seventeen, will range up to 96 clocks (3.84 s with a 25mhz pci bus or 2.88us with a 33mhz pci bus). if one or more pci to pci bridge is added to a system, the latency for irq/data updates from the secondary or tertiary buses will be a few clocks longer for synchronous buses, and approximately double for asynchronous buses. eoi/isr read latency any serialized irq scheme has a potential implementation issue related to irq latency. irq latency could cause an eoi or isr read to precede an irq transition that it should have followed. this could cause a system fault. the host interr upt controller is responsible for ensuring that th ese latency issues are mitigated. the recommended solution is to delay eois and isr reads to the interrupt controller by the same amount as the ser_irq cycle latency in order to ensure that these events do not occur out of order. ac/dc specification issue all ser_irq agents must drive / sample ser_irq synchronously related to the rising edge of pci bus clock. the ser_irq pin uses the electrical specification of pci bus. electrical parameters will follow pci spec. section 4, sustained tri-state. reset and in itialization the ser_irq bus uses pci_reset# as its reset signa l. the ser_irq pin is tri-stated by all agents while pci_reset# is active. with reset, ser_irq slaves are put into the (continuous) idle mode. the host controller is responsible for starting the initial ser_i rq cycle to collect system?s irq/data default values. the system then follows with the continuous/quiet mode protocol (stop frame pulse 13 irq12 38 14 irq13 41 15 irq14 44 16 irq15 47 ser_irq samp ling periods ser_irq period signal sample d # of clocks past start
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 146 smsc sch311x datasheet width) for subsequent ser_irq cycles. it is host controller?s responsibility to provide the default values to 8259?s and other system logic before the first ser_irq cycle is performed. for ser_irq system suspend, insertion, or re moval application, the host controller shoul d be programmed into continuous (idle) mode first. this is to guarantee ser_irq bus is in idle state before the system configuration changes.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 147 revision 0.4 (06-03-05) datasheet chapter 12 8042 keyboard controller description the sch311x is a super i/o and universal keyboa rd controller that is designed for intelligent keyboard management in desktop computer applications. the universal keyboard controller uses an 8042 microcontroller cpu core. this section concentrates on the sch311x enhancements to the 8042. for general information about the 8042, refer to the ?hardware description of the 8042? in the 8-bit embedded controller handbook . figure 12.1 sch311x keyboard and mouse interface kirq is the keyboard irq mirq is the mouse irq port 21 is used to create a gatea20 signal from the sch311x. 12.1 keyboard interface the sch311x lpc interface is functionally compatible with the 8042 style host interface. it consists of the d0-7 data signals; the read and write signals and the status register, input data register, and output data register. table 12.1 shows how the interface decodes the control signals. in addition to the above signals, the host interface includes keyboard and mouse irqs. 8042a p27 p10 p26 tst0 p23 tst1 p22 p11 kdat kclk mclk mdat keyboard and mouse interface ls05
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 148 smsc sch311x datasheet keyboard data write this is an 8 bit write only register. when written, th e c/d status bit of the status register is cleared to zero and the ibf bit is set. keyboard data read this is an 8 bit read only register. if enabled by ?enable flags?, when read, the kirq output is cleared and the obf flag in the status register is cleared. if not enabled, the kirq and/or auxobf1 must be cleared in software. keyboard command write this is an 8 bit write only register. when written, the c/d status bit of the status register is set to one and the ibf bit is set. keyboard status read this is an 8 bit read only register. refer to the description of the status register for more information. cpu-to-host communication the sch311x cpu can write to the output data register via register dbb. a write to this register automatically sets bit 0 (obf) in the status register. see ta b l e 1 2 . 2 . host-to-cpu communication the host system can send both commands and data to the input data register. the cpu differentiates between commands and data by reading the value of bit 3 of the status register. when bit 3 is ?1?, the cpu interprets the register contents as a command. when bit 3 is ?0?, the cpu interprets the register contents as data. during a host write operati on, bit 3 is set to ?1? if sa2 = 1 or reset to ?0? if sa2 = 0. kirq if ?en flags? has been executed and p24 is set to a one: the obf flag is gated onto kirq. the kirq signal can be connected to syst em interrupt to signify that th e sch311x cpu has written to the output data register via ?out dbb,a?. if p24 is set to a zero, kirq is forced low. on power-up, after table 12.1 i/o address map address command block function (see note) 0x60 write kdata keyboard data write (c/d=0) read kdata keyboard data read 0x64 write kdctl keyboard command write (c/d=1) read kdctl keyboard status read note: these registers consist of three separate 8-bit registers. status, data/command write and data read. table 12.2 host interface flags 8042 instruction flag out dbb set obf, and, if enabled, the kirq output signal goes high
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 149 revision 0.4 (06-03-05) datasheet a valid rst pulse has been delivered to the device, kirq is reset to 0. kirq will normally reflects the status of writes ?dbb?. (kirq is normally selected as irq1 for keyboard support.) if ?en flags? has not been executed: kirq can be controlled by writing to p24. writing a zero to p24 forces kirq low; a high forces kirq high. mirq if ?en flags? has been executed and p25 is set to a one:; ibf is inverted and gated onto mirq. the mirq signal can be connected to system interr upt to signify that the sch311x cpu has read the dbb register. if ?en flags? has not been executed, mirq is controlled by p25, writing a zero to p25 forces mirq low, a high forces mirq high. (mir q is normally selected as irq12 for mouse support). gate a20 a general purpose p21 is used as a software controlled gate a20 or user defined output. 8042 pins the 8042 functions p17, p16 and p12 are implemented as in a true 8042 part. reference the 8042 spec for all timing. a port signal of 0 drives the ou tput to 0. a port signal of 1 causes the port enable signal to drive the output to 1 within 20-30nsec. after 500nsec (six 8042 clocks) the port enable goes away and the external pull-up maintains the output signal as 1. in 8042 mode, the pins can be programmed as open drain. when programmed in open drain mode, the port enables do not come into play. if the port signal is 0 the output will be 0. if the port signal is 1, the output tristates: an external pull-up c an pull the pin high, and the pin can be shared. in 8042 mode, the pins cannot be programmed as input nor inverted through the gp configuration registers. 12.2 external keyboard and mouse interface industry-standard pc-at-compatible keyboards employ a two-wire, bidirectional ttl interface for data transmission. several sources also supply ps/2 mouse products that employ the same type of interface. to facilitate system expansion, the sch311x provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. the sch311x has four high-drive, open-drain output, bidirectional port pins that can be used for external serial interfaces, such as external keyb oard and ps/2-type mouse interfaces. they are kclk, kdat, mclk, and mdat. p26 is inverted and output as kclk. the kclk pin is connected to test0. p27 is inverted and output as kdat. the kdat pin is connected to p10. p23 is inverted and output as mclk. the mclk pin is connected to test1. p22 is inverted and output as mdat. the mdat pin is connected to p11. note: external pull-ups may be required. 12.2.1 keyboard/mouse swap bit there is a kbd/mouse swap bit in the keyboard select configuration register located at 0xf1 in logical device 7. this bit can be used to swap the keyboard and mouse clock and data pins into/out of the 8042. the default value of this bit is ?0? on vcc por, vtr por and pci reset. 1=internally swap the kclk pin and the mclk pin, and the kdat pin and the mdat pin into/out of the 8042. 0=do not swap the keyboard and mouse clock and data pins 12.3 keyboard power management the keyboard provides support for two power-sav ing modes: soft power-down mode and hard power- down mode. in soft power-down mode, the clock to the alu is stopped but the timer/counter and interrupts are still active. in hard power down mode the clock to the 8042 is stopped.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 150 smsc sch311x datasheet soft power-down mode this mode is entered by executing a halt instruction. the execution of program code is halted until either reset is driven active or a data byte is wr itten to the dbbin register by a master cpu. if this mode is exited using the interrupt, and the ibf inte rrupt is enabled, then program execution resumes with a call to the interrupt routine, otherwise the next instruction is executed. if it is exited using reset then a normal reset sequence is initiated a nd program execution starts from program memory location 0. hard power-down mode this mode is entered by executing a stop instruct ion. the oscillator is stopped by disabling the oscillator driver cell. when either reset is dr iven active or a data byte is written to the dbbin register by a master cpu, this mode will be exited (as above). however, as the oscillator cell will require an initialization time, either reset must be he ld active for sufficient ti me to allow the oscillator to stabilize. program exec ution will resume as above. 12.4 interrupts the sch311x provides the two 8042 interrupts: ibf and the timer/counter overflow. 12.5 memory configurations the sch311x provides 2k of on-chip rom and 256 bytes of on-chip ram. 12.6 register definitions host i/f data register the input data register and output data register are each 8 bits wide. a write to this 8 bit register will load the keyboard data read buffer, set the obf flag and set the kirq output if enabled. a read of this register will read the data fr om the keyboard data or command write buff er and clear the ibf flag. refer to the kirq and status register descriptions for more information. host i/f status register the status register is 8 bits wide. table 12.3 shows the contents of the status register. status register this register is cleared on a reset. this register is read-only for the host and read/write by the sch311x cpu. ud writable by sch311x cpu. these bits are user-definable. c/d (command data)-this bit specifies whether the input data register contains data or a command (0 = data, 1 = command). during a host data/command write operation, this bit is set to ?1? if sa2 = 1 or reset to ?0? if sa2 = 0. ibf (input buffer full)- this flag is set to 1 whenever the host system wr ites data into the input data register. setting this flag activates the sch311x cpu?s nibf (mirq) interrupt if enabled. table 12.3 status register d7 d6 d5 d4 d3 d2 d1 d0 ud ud ud ud c/d ud ibf obf
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 151 revision 0.4 (06-03-05) datasheet when the sch311x cpu reads the input data regist er (dbb), this bit is automatically reset and the interrupt is cleared. there is no output pin associated with this internal signal. obf (output buffer full) - this flag is set to whenever the sch311x cpu write to the output data register (dbb). when the host syst em reads the output data regi ster, this bit is automatically reset. 12.7 external clock signal the sch311x keyboard controller clock source is a 12 mhz clock generated from a 14.318 mhz clock. the reset pulse must last for at least 24 16 mhz clock periods. the pulse-width requirement applies to both internally (vcc por) and external ly generated reset signals. in power-down mode, the external clock signal is not loaded by the chip. 12.8 default r eset conditions the sch311x has one source of har dware reset: an external reset via the pci_reset# pin. refer to table 12.4 for the effect of each type of reset on the internal registers. gatea20 and keyboard reset the sch311x provides two options for gatea20 and keyboard reset: 8042 software generated gatea20 and kreset and port 92 fast gatea20 and kreset. port 92 fast gatea20 and keyboard reset port 92 register this port can only be read or written if port 92 has been enabled via bit 2 of the krst_ga20 register (logical device 7, 0xf0) set to 1. this register is used to support the alternate rese t (nalt_rst) and alternate a20 (alt_a20) functions. table 12.4 resets description hardware reset (pci_reset#) kclk low kdat low mclk low mdat low host i/f data reg n/a host i/f status reg 00h note: n/a = not applicable
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 152 smsc sch311x datasheet bit 0 of port 92, which generates the nalt_rst signal, is used to reset the cpu under program control. this signal is and?ed together externally with the reset signal (nkbdrst) from the keyboard controller to provide a software means of resetting the cpu. this provides a faster means of reset than is provided by the keyboard controller. writing a 1 to bit 0 in the port 92 register causes this signal to pulse low for a minimum of 6s, after a delay of a minimum of 14s. before another nalt_rst pulse can be gener ated, bit 0 must be set to 0 either by a system reset of a write to port 92. upon reset, this signal is driven inactive high (bit 0 in the port 92 register is set to 0). name port 92 location 92h default value 24h attribute read/write size 8 bits port 92 register bit function 7:6 reserved. returns 00 when read 5 reserved. returns a 1 when read 4 reserved. returns a 0 when read 3 reserved. returns a 0 when read 2 reserved. returns a 1 when read 1 alt_a20 signal control. writing a 0 to this bit causes the alt_a20 signal to be driven low. writing a 1 to this bit causes the alt_a20 signal to be driven high. 0 alternate system reset. this read/write bit provides an alternate system reset function. this function provides an alternate means to reset the system cpu to effect a mode switch from protected virtual address mode to the real address mode. this provides a faster means of reset than is provided by the keyboard cont roller. this bit is set to a 0 by a system reset. writing a 1 to this bit will cause the nalt_rst signal to pulse active (low) for a minimum of 1 s after a delay of 500 ns. before another nalt_rst pulse can be generated, this bit must be written back to a 0. ngatea20 8042 p21 alt_a20 system na20m 000 011 101 111
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 153 revision 0.4 (06-03-05) datasheet if port 92 is enabled, i.e., bit 2 of krst_ga20 is set to 1, then a pulse is generated by writing a 1 to bit 0 of the port 92 register and this pulse is and?ed with the pulse generated from the 8042. this pulse is output on pin kreset and its polarity is controlled by the gpi/o polarity configuration. figure 12.2 gpi/o polarity configuration bit 1 of port 92, the alt_a20 signal, is used to force na20m to the cpu low for support of real mode compatible software. this signal is externally or?ed with the a20gate signal from the keyboard controller and cpurst to control the na20m input of the cpu. writing a 0 to bit 1 of the port 92 register forces alt_a20 low. alt_a20 low drives na20m to the cpu low, if a20gate from the keyboard controller is also low. writing a 1 to bit 1 of the port 92 register forces alt_a20 high. alt_a20 high drives na20m to the cpu high, regardl ess of the state of a20gate from the keyboard controller. upon reset, this signal is driven low. latches on keyboard and mouse irqs the implementation of the latches on the keyboard and mouse interrupts is shown below. figure 12.3 keyboard latch 8042 p92 pulse gen kbdrst krst_ga2 bit 2 bit 0 p20 krst nalt_rst 6us 14us ~ ~ 6us 14us ~ ~ note: when port 92 is writes are ignored and return undefined 8042 vcc d q kint kint new rd 60 clr klatch bit
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 154 smsc sch311x datasheet figure 12.4 mouse latch the klatch and mlatch bits are located in the krst_ga20 register, in logical device 7 at 0xf0. these bits are defined as follows: bit[4]: mlatch ? mouse interrupt latch control bit. 0=mint is the 8042 mint anded with latched mint (default), 1=mint is the latched 8042 mint. bit[3]: klatch ? keyboard interrupt latch control bit. 0=kint is the 8042 kint anded with latched kint (default), 1=kint is the latched 8042 kint. see table 25.14, ?kybd. logical de vice 7 [logical device numb er = 0x07],? on page 306 for a description of this register. 12.9 keyboard and mouse pme generation the sch311x sets the associated pme status bits when the following conditions occur: keyboard interrupt mouse interrupt active edge on keyboard data signal (kdat) active edge on mouse data signal (mdat) these events can cause a pme to be generated if th e associated pme wake enable register bit and the global pme_en bit are set. refer to chapter 15, "pme support," on page 171 for more details on the pme interface logic and refer to chapter 26, "runtime register," on page 311 for details on the pme status and enable registers. the keyboard interrupt and mouse interrupt pmes can be generated when the part is powered by vcc. the keyboard data and mouse data pmes can be generated both when the part is powered by vcc, and when the part is powered by vtr (vcc=0). when using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the keyboard signals (kclk, kdat, mclk, mdat) from the 8042 prior to entering certain system sleep states. this is due to the fact that the norma l operation of the 8042 ca n prevent the system from entering a sleep state or trigger false pme events. the sch311x has ?isolation? bits for the keyboard and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but block the clock and data signals from the 8042. these bits may be used anytime it is necessary to isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state. see the pme_sts1 fo r more information. 8042 vcc d q mint mint new rd 60 clr mlatch bit
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 155 revision 0.4 (06-03-05) datasheet the bits used to isolate the keyboard and mouse signals from the 8042 are located in logical device 7, register 0xf0 (krst_ga20) and are defined below. these bits reset on vtr por only. bit[6] m_iso. enables/disables isolation of mouse signals into 8042. does not affect the mdat signal to the mouse wakeup (pme) logic. 1 = block mouse clock and data signals into 8042 0 = do not block mouse clock and data signals into 8042 bit[5] k_iso. enables/disables isolation of keyboard signals into 8042. does not affect the kdat signal to the keyboard wakeup (pme) logic. 1 = block keyboard clock and data signals into 8042 0 = do not block keyboard clock and data signals into 8042 when the keyboard and/or mouse isolation bits are used, it may be necessary to reset the 8042 upon exiting the sleep state. if either of the isolation bits is set prior to entering a sleep state where vcc goes inactive (s3-s5), then the 8042 must be reset upon exiting the sleep mode. write 0x40 to global configuration register 0x2c to reset the 8042. the 8042 must then be taken out of reset by writing 0x00 to register 0x2c since the bit that resets the 8042 is not self-clearing. caution: bit 6 of configuration register 0x2c is used to put the 8042 into reset - do not set any of the other bits in register 0x2c, as this may produce undesired results. it is not necessary to reset the 8042 if the isolation bits are used for a sleep state where vcc does not go inactive (s1, s2). user?s note: regarding external keyboard and mouse: this is an application matter resulting from the behavior of the external 8042 in the keyboard. when the external keyboard and external mouse ar e powered up, the kdat and mdat lines are driven low. this sets the kbd bit (d3) and the mouse bit (d4) of the pme wake status register since the kdat and mdat signals cannot be isolated internal to the part. this causes an nio_pme assertion to be generated if the keyboard and/or mouse pme events are enabled. note that the keyboard and mouse isolation bits only prevent the internal 8042 in the part from setting these status bits. case 1: keyboard and/or mouse powered by vtr the kbd and/or mouse status bits will be se t upon a vtr por if the keyboard and/or mouse are powered by vtr. in this case, a nio_pme will not be generated, since the keyboard and mouse pme enable bits are reset to zero on a vtr por. the bios software needs to clear these pme status bits after power-up. in this case, an nio_pme will be generated if the enable bits were set for wakeup, since the keyboard and mouse pme enable bits are bvat powered. therefore, if the keyboard and mouse are powered by vtr, the enable bits for keyboard and mouse events should be cleared prior to entering a sleep state where vtr is removed (i.e., s4 or s5) to prevent a false pme from being generated. in this case, the keyboard and mouse should only be used as pme and/or wake events from the power states s3 or below. case 2: keyboard and/or mouse powered by vcc the kbd and/or mouse status bits will be set upo n a vcc por if the keyboard and/or mouse are powered by vcc. in this case, a nio_pme and a nio_pme will be generated if the enable bits were set for wakeup, since the keyboard and mouse pme enable bits are vtror vbat powered. therefore, if the keyboard and mouse are powered by vcc, the enable bits for keyboard and mouse events should be cleared prior to entering a sleep state w here vcc is removed (i.e., s3) to prevent a false pme from being generated. in this case, the keyb oard and mouse should only be used as pme and/or wake events from the s0 and/or s1 states. the bios software needs to clear these pme status bits after power-up.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 156 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 157 revision 0.4 (06-03-05) datasheet chapter 13 general purpose i/o (gpio) the sch311x provides a set of flexible input/outpu t control functions to t he system designer through the 40 independently programmable general purpose i/o pins (gpio). the gpio pins can perform basic i/o and many of them can be individually enabled to generate an smi and a pme. 13.1 gpio pins the following pins include gpio functionality. these pins are defined in the table below. all gpios default to the gpio function except on indicated by note 13.3 . table 13.1 gpio pin functionality gpio pin pin # pin name (default func/ alternate funcs) gpio pwrwell vtr por smi/pme note 1. 85 gp10 gp10 / rxd3 vcc 0x01 13.3 2. 86 gp11 gp11 / txd3 vtr 0x01 13.3 3. 96 gp12 gp12 / ndcd3 vtr 0x01 13.3 4. 95 gp13 gp13 / nri3 vtr 0x01 pme 13.3 , 13.4 5. 87 gp14 gp14 / ndsr3 vtr 0x01 13.3 6. 92 gp15 gp15 / ndtr3 vcc 0x01 13.3 7. 89 gp16 gp16 / ncts3 vcc 0x01 13.3 8. 88 gp17 gp17 / nrts3 vcc 0x01 13.3 9. 37 kdat/gp21 vcc 0x8c smi/pme 13.1 , 13.3 10. 38 kclk/gp22 vcc 0x8c smi/pme 13.1 , 13.3 11. 36 gp27/nio_smi /p17 vcc 0x01 nio_smi/pm e 13.1 12. 110 nfprst / gp30 vtr 0x05 13.3 13. 97 gp31 gp31 / nri4 vtr 0x01 pme 13.3 , 13.4 14. 39 mdat/gp32 vcc 0x84 smi/pme 13.1 13.3 15. 40 mclk/gp33 vcc 0x84 smi/pme 13.1 13.3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 158 smsc sch311x datasheet 16. 107 gp34 gp34 / ndtr4 vtr 0x01 13.3 17. 41 gp36/nkbdrst vcc 0x01 - 18. 42 gp37/a20m vcc 0x01 - 19. 3 gp40/drvden0 vcc 0x01 - 20. 90 gp42/nio_pme vtr 0x01 smi 21. 30 nide_rstdrv / gp44 gp44 / txd6 vcc 0x01 13.3 22. 31 npci_rst1 / gp45 gp45 / rxd6 vtr 0x01 13.3 23. 32 npci_rst2 / gp46 gp46 / nscin6 vtr 0x01 pme 13.3 , 13.4 24. 33 npci_rst3 / gp47 gp47 / nscout6 vtr 0x01 13.3 25. 71 gp50/nri2 vcc 0x01 pme 13.1 26. 74 gp51/ndcd2 vcc 0x01 pme 13.1 27. 75 gp52/rxd2(irrx) vcc 0x01 pme 13.1 28. 76 gp53/txd2 (irtx) vcc 0x01 pme 13.1 29. 77 gp54/ndsr2 vcc 0x01 smi/pme 13.1 30. 78 gp55/nrts2 vcc 0x01 smi/pme 13.1 31. 79 gp56/ncts2 vcc 0x01 smi/pme 13.1 32. 80 gp57/ndtr2 vcc 0x01 smi/pme 13.1 33. 94 gp60/nled1/wdt vtr 0x01 smi/pme 13.1 34. 93 gp61/nled2/ clko vtr 0x01 smi/pme 13.1 35. 106 gp62 gp62 / ncts4 vtr 0x01 13.3 36. 98 gp63 gp63 / ndcd4 vtr 0x01 13.3 37. 102 gp64 gp64 / rxd4 vtr 0x01 13.3 38. 103 gp65 gp65 / txd4 vtr 0x01 13.3 39. 104 gp66 gp66 / ndcr4 vtr 0x01 13.3 table 13.1 gpio pin functionality (continued) gpio pin pin # pin name (default func/ alternate funcs) gpio pwrwell vtr por smi/pme note
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 159 revision 0.4 (06-03-05) datasheet note 13.1 these pins are inputs to vcc and vtr powered logic.. the logic for the gpio is on vcc - it is also a wake event which goes to vtr powered logic. note 13.2 this pin?s primary function (power up default function) is not gpio function; however, the pin can be configured a gpio alternate function. note 13.3 not all alternate functions are available in all sch311x devices. refer to table 13.2, ?sch311x general purpose i/o port assignments,? on page 160 for more details. note 13.4 the pme is for the ri signal only. note that this may not be available for all sch311x devices. refer to table 13.2, ?sch311x general purpose i/o port assignments,? on page 160 for more details. 13.2 description each gpio port has a 1-bit data register and an 8-bit configuration control register. the data register for each gpio port is represented as a bit in one of the 8-bit gpio data registers, gp1 to gp6. the bits in these registers reflect the value of the associated gpio pin as follows. pin is an input: the bit is the value of the gpio pin. pin is an output: the value written to the bit goes to the gpio pin. latched on read and write. all of the gpio registers are located in the pme block see chapter 26, "runtime register," on page 311 . the gpio ports with their alternate functions and configuration state register addresses are listed in table 13.2 . 40. 105 gp67 gp67 / nrts4 vtr 0x01 13.3 table 13.1 gpio pin functionality (continued) gpio pin pin # pin name (default func/ alternate funcs) gpio pwrwell vtr por smi/pme note
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 160 smsc sch311x datasheet table 13.2 sch311x general purpose i/o port assignments run- time reg off- set sch3112 sch3114 sch3116 gp data reg gp data bit def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3 23 gpio10 gpio10 rxd3 gpio10 rxd3 gp1 offse t 4b 0 24 gpio11 gpio11 txd3 gpio11 txd3 1 25 gpio12 gpio12 ndcd3 gpio12 ndcd3 2 26 gpio13 gpio13 nri3 gpio13 nri3 3 27 gpio14 gpio14 ndsr3 gpio14 ndsr3 4 29 gpio15 gpio15 ndtr3 gpio15 ndtr3 5 2a gpio16 gpio16 ncts3 gpio16 ncts3 6 2b gpio17 gpio17 nrts3 gpio17 nrts3 7
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 161 smsc sch311x datasheet reserve d reserv ed reserv ed gp2 offse t 4c 0 2c kdat (see note 13. 5 ) gpio21 kdat (see note 13 .5 ) gpio21 kdat (see note 13 .5 ) gpio21 1 2d kclk (see note 13. 5 ) gpio22 kclk (see note 13 .5 ) gpio22 kclk (see note 13 .5 ) gpio22 2 reserve d reserv ed reserv ed 4:3 reserve d reserv ed reserv ed 5 reserve d reserv ed reserv ed 6 32 gpio27 smi output p17 (see note 13 .5 ) gpio27 smi output p17 (see note 13 .5 ) gpio27 smi output p17 (see note 13 .5 ) 7 table 13.2 sch311x general purpose i/o port assignments (continued) run- time reg off- set sch3112 sch3114 sch3116 gp data reg gp data bit def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 162 smsc sch311x datasheet 33 nfprst gpio30 nfprs t gpio30 nfprs t gpio30 gp3 offse t 4d 0 34 gpio31 gpio31 nri4 gpio31 nri4 1 35 mdat (see note 13. 5 ) gpio32 mdat (see note 13 .5 ) gpio32 mdat (see note 13 .5 ) gpio32 2 36 mclk (see note 13. 5 ) gpio33 mclk (see note 13 .5 ) gpio33 mclk (see note 13 .5 ) gpio33 3 37 gpio34 gpio34 ndtr4 gpio34 ndtr4 4 reserve d reserv ed reserv ed 5 39 gpio36 keyboa rd reset gpio36 keyboar d reset gpio36 keyboa rd reset 6 3a gpio37 gate a20 gpio37 gate a20 gpio37 gate a20 7 table 13.2 sch311x general purpose i/o port assignments (continued) run- time reg off- set sch3112 sch3114 sch3116 gp data reg gp data bit def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 163 smsc sch311x datasheet 3b gpio40 drive density select 0 gpio40 drive density select 0 gpio40 drive density select 0 gp4 offse t 4e 0 reserve d reserv ed reserv ed 1 3d gpio42 nio_p me gpio42 nio_pm e gpio42 nio_pm e 2 reserve d reserv ed reserv ed 3 6e nidr_r stdrv gpio44 nidr_r stdrv gpio44 gpio44 txd6 4 6f npcirs t1 gpio45 npcirs t1 gpio45 gpio45 rxd6 5 72 npci_r st2 gpio46 npci_r st2 gpio46 gpio46 nscin6 6 73 npci_r st3 gpio47 npci_r st3 gpio47 gpio47 nscou t6 7 table 13.2 sch311x general purpose i/o port assignments (continued) run- time reg off- set sch3112 sch3114 sch3116 gp data reg gp data bit def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 164 smsc sch311x datasheet 3f gpio50 ring indicato r 2 gpio50 ring indicator 2 gpio50 ring indicato r 2 gp5 offse t 4f 0 40 gpio51 data carrier detect 2 gpio51 data carrier detect 2 gpio51 data carrier detect 2 1 41 gpio52 receive serial data 2 gpio52 receive serial data 2 gpio52 receive serial data 2 2 42 gpio53 transmi t serial data 2 gpio53 transmit serial data 2 gpio53 transmi t serial data 2 3 43 gpio54 data set ready 2 gpio54 data set ready 2 gpio54 data set ready 2 4 44 gpio55 reques t to send 2 gpio55 request to send 2 gpio55 reques t to send 2 5 45 gpio56 clear to send 2 gpio56 clear to send 2 gpio56 clear to send 2 6 46 gpio57 date te r m i n a l ready gpio57 date terminal ready gpio57 date te r m i n a l ready 7 table 13.2 sch311x general purpose i/o port assignments (continued) run- time reg off- set sch3112 sch3114 sch3116 gp data reg gp data bit def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 165 smsc sch311x datasheet note 13.5 when this pin function is selected, the associat ed gpio pins have bi-directional functionality. note 13.6 these pins have either edge triggered interrupt (eeti) functionality. see section 13.5, "gpio pme and smi functionality," on page 167 for more details. note 13.7 these pins have vid compatible inputs. 47 gpio60 note 13. 6 nled1 wdt wdt gpio60 note 13 .6 nled1 wdt wdt gpio60 note 13 .6 nled1 wdt wdt gp6 offse t 50 0 48 gpio61 note 13. 6 nled2 clko gpio61 note 13 .6 nled2 clko gpio61 note 13 .6 nled2 clko 1 54 gpio62 note 13. 7 ncts4 gpio62 note 13 .7 ncts4 gpio62 note 13 .7 ncts4 2 55 gpio63 note 13. 7 ndcd4 gpio63 note 13 .7 ndcd4 gpio63 note 13 .7 ndcd4 3 56 gpio64 note 13. 7 rxd4 gpio64 note 13 .7 rxd4 gpio64 note 13 .7 rxd4 4 57 gpio65 note 13. 7 txd4 gpio65 note 13 .7 txd4 gpio65 note 13 .7 txd4 5 58 gpio66 note 13. 7 ndsr4 gpio66 note 13 .7 ndsr4 gpio66 note 13 .7 ndsr4 6 59 gpio67 note 13. 7 nrts4 gpio67 note 13 .7 nrts4 gpio67 note 13 .7 nrts4 7 table 13.2 sch311x general purpose i/o port assignments (continued) run- time reg off- set sch3112 sch3114 sch3116 gp data reg gp data bit def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3def alt. func. 1 alt. func. 2 alt. func. 3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 166 smsc sch311x datasheet 13.3 gpio control each gpio port has an 8-bit control register that cont rols the behavior of the pin. these registers are defined in chapter 26, "runtime register," on page 311 section of this specification. each gpio port may be configured as either an input or an output. if the pin is configured as an output, it can be programmed as open-drain or pus h-pull. inputs and outputs can be configured as non-inverting or inverting. bit[0] of each gpio configuration register determines the port direction, bit[1] determines the signal polarity, and bit[7] det ermines the output driver type select. the gpio configuration register output type select bit[7] applies to gpio functions and the nsmi alternate functions the basic gpio configuration options are summarized in table 13.3, "gpio configuration option" . the following gpio have limited functionality as indicated in the notes in table 13.1, ?gpio pin functionality,? on page 157 : gp10, gp11, gp12, gp13, gp14, gp42. the corresponding gpio control register have read only bits in position 0, 1, and/or 7. 13.4 gpio operation the operation of the gpio ports is illustrated in figure 13.1 . when a gpio port is programmed as an input, readin g it through the gpio data register latches either the inverted or non-inverted logic va lue present at the gpio pin. writing to a gpio port that is programmed as an input has no effect ( table 13.4 ) when a gpio port is programmed as an output, the logic value or the inverted logic value that has been written into the gpio data register is output to the gpio pin. reading from a gpio port that is programmed as an output returns the last value written to the data register ( ta b l e 1 3 . 4 ). when the gpio is programmed as an output, the pin is excluded from the pme and smi logic. table 13.3 gpio configuration option selected function direction bit polarity bit description b0 b1 gpio 0 0 pin is a non-inverted output. 0 1 pin is an inverted output. 1 0 pin is a non-inverted input. 1 1 pin is an inverted input.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 167 revision 0.4 (06-03-05) datasheet figure 13.1 gpio function illustration note: figure 13.1 is for illustration purposes only and is not intended to suggest specific implementation details. 13.5 gpio pme and smi functionality the sch311x provides gpios that can directly gener ate a pme. the polarity bit in the gpio control registers select the edge on these gpio pins that will set the associated status bit in a pme status. for additional description of pme behavior see chapter 15, "pme support," on page 171 . the default is the low-to-high transition. in addition, the s ch311x provides gpios that can directly generate an smi. the following gpios are dedicated wakeup gpios with a status and enable bit in the pme status and enable registers: gp21-gp22,gp27, gp32-gp33 are controlled by pme_sts1 , pme_sts3, pme_en1, pme_en3 registers. gp50-gp57 are controlled by pme_sts5, pme_en5 registers. table 13.4 gpio read/write behavior host operation gpio inpu t port gpio output port read latched value of gpio pin last write to gpio data register write no effect bit placed in gpio data register gpio pin gpio data register bit-n sd-bit gpx_nior gpio configuration register bit-1 (polarity) gpio configuration register bit-0 (input/output) 1 0 d-type transparen t gpx_niow dq qd
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 168 smsc sch311x datasheet gp60, gp61 are controlled by pme_sts6, and pme_en6 registers. the following gpios can directly generate an smi and have a status and enable bit in the smi status and enable registers. gp21, gp22, gp54, gp55, gp56, gp57, gp60 are controlled by smi_sts3, and smi_en3 registers. gp32, gp33, gp42, gp61 are controlled by smi_sts4, and smi_en4 registers. the following gpios have "either edge triggered inte rrupt" (eeti) input capability: gp21, gp22, gp60, gp61. these gpios can generate a pme and an smi on both a high-to-low and a low-to-high edge on the gpio pin. these gpios have a status bit in the pme_sts1 status register that is set on both edges. the corresponding bits in the pme and smi status registers are also set on both edges. 13.6 either edge triggered interrupts three gpio pins are implemented such that they a llow an interrupt (pme or smi) to be generated on both a high-to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit. the either edge triggered interrupts (eeti) function as follows: if the eeti function is selected for the gpio pin, then the bits that control input/output, polarity and open drain/push-pull have no effect on the function of the pin. however, the polarity bit does affect the value of the gp bit (i.e., register pme_sts1, bit 2 for gp22). a pme or smi interrupt occurs if the pme or smi enable bit is set for the corresponding gpio and the eeti function is selected on the gpio. the pme or smi status bits are set when the eeti pin transitions (on either edge) and are cleared on a write of '1'. there are also status bits for the eetis located in the pme_stsx register, which are also cleared on a write of '1'. the msc_sts register provides the status of all of the eeti interrupts within one register. the pme, smi or msc status is valid whether or not the interrupt is enabled and whether or not the eeti function is selected for the pin. miscellaneous status register (msc_sts) is for the either edge triggered interrupt status bits. if the eeti function is selected for a gpio then both a high-to-low and a low-to-high edge will set the corresponding msc status bits. status bits are cleared on a write of '1'. see chapter 26, "runtime register," on page 311 for more information. the configuration register for the either edge triggered interrupt status bits is defined in chapter 26, "runtime register," on page 311 . 13.7 led functionality the sch311x provides led functionality on tw o gpios, gp60 and gp61. these pins can be configured to turn the led on and off and blink independent of each other through the led1 and led2 runtime registers at offset 0x5d and 0x5e from the base address lo cated in the primary base i/o address in logical device a. the led pins (gp60 and gp61) are able to control the led while the part is under vtr power with vcc removed. in order to control a led while the part is under vtr power, the gpio pin must be configured for the led function and either open drain or push-pull buffer type. in the case of open- drain buffer type, the pin is capable of sinking current to control the led. in the case of push-pull buffer type, the part will source current. the part is also able to blink the led under vtr power. the led will not blink under vtr power (vcc removed) if the external 32khz clock is not connected. the led pins can drive a led when the buffer ty pe is configured to be push-pull and the part is powered by either vcc or vtr, since the buffers fo r these pins are powered by vtr. this means they will source their specified current from vtr even when vcc is present. the led control registers are defined in chapter 26, "runtime register," on page 311 .
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 169 revision 0.4 (06-03-05) datasheet chapter 14 system management interrupt (smi) the sch311x implements a ?group? nio_smi output pin. the system management interrupt is a non- maskable interrupt with the highest priority level used for os transparent power management. the nsmi group interrupt output c onsists of the enabled interrupts from each of the functional blocks in the chip and many of the gpios and the fan tach ometer pins. the gp27 /nio_smi/p17 pin, when selected for the nio_smi function, can be programmed to be active high or active low via the polarity bit in the gp27 register. the output buffer ty pe of the pin can be programmed to be open-drain or push-pull via bit 7 of the gp27 register. the nio_sm i pin function defaults to active low, open-drain output. the interrupts are enabled onto the group nsmi output via the smi enable registers 1 to 4. the nsmi output is then enabled onto the group nio_smi output pin via bit[7] in the smi enable register 2. the smi output can also be enabled onto the serial irq stream (irq2) via bit[6] in the smi enable register 2. the internal smi can also be enabled onto the nio_pme pin. bit[5] of the smi enable register 2 (pme_sts1) is used to enable the smi output onto the nio_pme pin (gp42). this bit will enable the internal smi output into the pme logic through the devint_sts bit in pme_sts3. see pme_sts1 for more details. an example logic equation for the nsmi output for smi registers 1 and 2 is as follows: nsmi = (en_pint and irq_pint) or (en_u2int and irq_u2int) or (en_u1int and irq_u1int) or (en_fint and irq_fint) or (en_mint and irq_mint) or (en_kint and irq_kint) or (en_irint and irq_irint) or (enp12 and irq_p12) or (spemse_en and spemse_sts) note: the prefixes en and irq are used above to indicate smi enable bit and smi status bit respectively. smi registers the smi event bits for the gpios and the fan tachometer events are located in the smi status and enable registers 3-5. the polarity of the edge us ed to set the status bit and generate an smi is controlled by the polarity bit of the control registers. for non-inverted polarity (default) the status bit is set on the low-to-high edge. if the eeti function is selected for a gpio then both a high-to-low and a low-to-high edge will set the corresponding smi status bit. status bits for the gpios are cleared on a write of ?1?. the smi logic for these events is implemented such that the output of the status bit for each event is combined with the corresponding enable bit in order to generate an smi. the smi registers are accessed at an offset from pme_blk (see chapter 26, "runtime register," on page 311 for more information). the smi event bits for the super i/o devices are located in the smi status and enable register 1 and 2. all of these status bits are cleared at the s ource except for irint, which is cleared by a read of the smi_sts2 register; these status bits are not cleared by a write of ?1?. the smi logic for these events is implemented such that each event is directly combined with the corresponding enable bit in order to generate an smi. see the chapter 26, "runtime register," on page 311 for the definition of these registers.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 170 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 171 revision 0.4 (06-03-05) datasheet chapter 15 pme support the sch311x offers support for power management events (pmes), also referred to as a system control interrupt (sci) events in an acpi system . a power management event is indicated to the chipset via the assertion of the nio_pme signal when in s5 or below power states. application note: software must properly configure the enable and status bits for the individual pme events in the registers described below. . table 15.1 describes the pme interface. 15.1 pme events all pme the events asserted on nio_pme are listed in table 15.2 . table 15.1 pme interface name buffer power well description nio_pme (o12/od12) vtr general purpose i/o. power management event output. this active low power management event signal allows this device to request wakeup in s5 and below. table 15.2 pme events events pme comment mouse by irq y (from group smi) data pin edge sensitive y specific mouse click y see section 15.5, "wake on specific mouse click," on page 174 for details keyboard any key y specific key y by irq y (from group smi) power button input last state before power loss y fdc y (from group smi) pio y (from group smi) uart-1 by irq y (from group smi) by nri1 pin y
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 172 smsc sch311x datasheet the pme function is controlled by the pme status and enable registers in the runtime registers block, which is located at the address programmed in configuration registers 0x60 and 0x61 in logical there are four types of registers which control pme events: 1. pme wake status register ( pme_sts1 , pme_sts3 , pme_sts5 , pme_sts6 .) provides the status of individual wake events. 2. pme wake enable ( pme_en1 , pme_en3 , pme_en5 , pme_en6 ) provides the enable for individual wake events. 3. pme pin enable register ( pme_en ,) provides an enable for the pme output pins. 4. pme pin status register ( pme_sts ) provides the status for the pme output pins. see chapter 26, "runtime register," on page 311 for detailed register description the following describes the behavior to the pme status bits for each event: each wake source has a bit in a pme wake status register which indicates that a wake source has occurred. the pme wake status bits are ?sticky?(unless otherwise stated in bit description in chapter 26, "runtime register," on page 311 ): once a status bit is set by the wake-up event, the bit will remains set until cleared by writing a ?1? to the bit. each pme wake status register has a corresponding pme wake enable register. uart-2 by irq y (from group smi) by nri2 pin y uart-3 by irq y (from group smi) by nri2 pin y uart-4 by irq y (from group smi) by nri2 pin y uart-5 by irq y (from group smi) by nri2 pin y uart-6 by irq y (from group smi) by nri2 pin y hardware monitor nhwm_int watch dog timer y gpio, total 15 pins y low-battery y detect on vcc por only not a s3 wakeup either table 15.2 pme events (continued) events pme comment
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 173 revision 0.4 (06-03-05) datasheet if the corresponding bit in both in a pme wake status register and the pme wake enable register are set then the pme pin status register bit is set. if both corresponding pme pin status and the pme pin enable register bit are set then the io_pme pinio_pme pin will asserted. for the gpio events, the polarity of the edge used to set the status bit and generate a pme is controlled by the polarity bit of the gpio control r egister. for non-inverted polarity (default) the status bit is set on the low-to-high edge. if the eeti function is selected for a gpio then both a high-to-low and a low-to-high edge will set the corresponding pm e status bits. status bits are cleared on a write of '1'. the pme wake registers also include status and enable bits for the hw monitor block. see section 12.9, "keyboard and mouse pme generation," on page 154 for information about using the keyboard and mouse signals to generate a pme. 15.2 enabling smi events onto the pme pin there is a bit in the pme status register 3 to show the status of the internal ?group? smi signal in the pme logic (if bit 5 of the smi_en2 register is set). this bit, devint_sts, is at bit 3 of the pme_sts3 register. when this bit is clear, the group smi output is inactive. when bit is set, the group smi output is active.the corresponding wake-up enable bit is devint_en, is at bit 3 of the pme_en3 register. bit 5 of the smi_en2 register must also be set. this bit is cleared on a write of '1'. 15.3 pme function pin control the gp42/nio_pme pin, when selected for the nio_pme function, can be programmed to be active high or active low via the polarity bit in the gp42 register. the output buffer type of the pin can be programmed to be open-drain or push-pull via bit 7 of the gp42 register. the nio_pme pin function defaults to active low, open-drain output; ho wever the gp42/nio_pme pin defaults to the gp42 function. in the sch311x the nio_pme pin can be programmed to be an open drain, active low, driver. the sch311x nio_pme pin are fully isolated from other external devices that might pull the signal low; i.e., the nio_pme pin are capable of being driven hi gh externally by another active device or pull-up even when the sch311x vcc is grounded, providing vtr power is active. the io_pme pin driver sinks 6ma at 0.55v max (see section 4.2.1.1 dc specifications in the "pci local bus specification, revision 2.2, december 18, 1998). 15.4 wake on specific key code the sch311x wake on specific key code feature is enabled for the assertion of the nio_pme signal in sx power states by the spekey bit in the pme_sts6 register. this bit defaults to enabled and is vbat powered. at vbat por the wake on specific key code feature is disabled. during the first vtr por and vcc por the wake on specific key code feature remains disabled. software selects the precise specific key code event (configuration) to wake the syst em and then enables the feature via the spekey bit in the pme_sts6 register. the system then may go the sleep and/or have a power failure. after returning to or remaining in s5 sleep, the system will fully awake by a wake on specific key code the specific key code configuration and the enabl e for the nio_pme are retained via vbat por backed registers. the sch311x wake on specific key code feature is enabled for assertion of the nio_pme signal when in s3 power state or below by the spekey bit in the pme_en6 register. this bit defaults to disabled and is vtr powered.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 174 smsc sch311x datasheet 15.5 wake on specific mouse click the spesme select field in the mouse_specific_wake register selects which mouse event is routed to the pme_sts6 if enabled by pme_en6 . the kb_mse_swap bit in the mouse_specific_wake register can swap the mouse port and keyboard interfaces internally. the lock bit in the mouse_specific_wake register provides a means of changing access to read only to prevent tampering with the wake on mouse settings. the other bits in the mouse_specific_wake register are vbat powered and reset on vbat por; therefore, the mouse event settings are maintained through a power failure. the lock bit also controls access to the dblclick register. the dblclick register contains a numeric value that determines the time interval used to check for a double mouse click. the value is the time in terval between mouse clicks. for example, if dblclick is set to 0.5 seconds, you have one half second to click twice for a double-click. the larger the value in the dblclick register, the longer you can wait between the first and second click for the sch311x to interp ret the two clicks as a double-cl ick mouse wake event. if the dblclick value is set to a very small val ue, even quick double clicks may be interpreted as two single clicks. the dblclick register has a six bit weighted sum valu e from 0 to 0x3fh which provides a double click interval between 0.0859375 and 5.5 seconds. each incremental digit has a weight of 0.0859375 seconds. the dblclick register is vbat powered and reset on vbat por; therefore, the double click setting is maintained through a power failure. the defaul t setting provides a 1.03125 second time interval. dblclick writing to the dblclick register shall reset the mouse wake-up internal logic and initialize the mouse wake-up state machines.the spemse_en bi t in of the clocki32 configuration register at 0xf0 in logical device a is used to control th e ?wake on specific mouse click? feature. this bit is used to turn the logic for this feature on and off. it will disable the 32khz clock input to the logic. the logic will draw no power when disabled. the bit is defined as follows: 0= "wake on specific mouse click" logic is on (default) 1= "wake on specific mouse click" logic is off the generation of a pme for this event is controlled by the pme enable bits (spemse_en bit in the pme_en6 register and in the smi_en2 register) when the logic for feature is turned on. see section 15.5, "wake on specific mouse click," on page 174 . application note: the wake on specific mouse click feature requ ires use of the m_iso bit in the krst_ga20 register. smsc application note 8.8 titled ?keyboard and mouse wake-up functionality?. when using the wake on specific mouse event, it may be necessary to isolate the mouse port signals (mclk, mdat) from the 8042 prior to entering cert ain system sleep states. this is due to the fact that the normal operation of the 8042 can prevent the system from entering a sleep state or trigger false pme events. sch311x has an ?isolation? bit fo r the mouse signals, which allows the mouse data signals to go into the wake-up logic but block the clock and data signals from the 8042. when the mouse isolation bit are used, it may be necessary to reset the 8042 upon exiting the sleep state. if m_sio bit is set prior to entering a sl eep state where vcc goes inactive (s3-s5), then the 8042 must be reset upon exiting the sleep mode. writ e 0x40 to global configuration register 0x2c to reset the 8042. the 8042 must then be taken out of reset by writing 0x00 to register 0x2c since the bit that resets the 8042 is not self-clearing. caution: bit 6 of configuration register 0x2c is used to put the 8042 into reset - do not set any of the other bits in register 0x2c, as this may produce undesired results.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 175 revision 0.4 (06-03-05) datasheet figure 15.1 8042 isolation and keyboard and mouse port swap representation note: this figure is for illustration purposes only and not meant to imply specific implementation details 8042 kdat_out kdat_in k_iso iso_ kdat_in kclk_out kclk_in iso_kclk_in iso kdat_out iso_kclk_out iso_mdat_out kb_mse_swap pin_kdat_in pin_kdat_out pin_kclk_out iso_mclk_out pin_kclk_in k d a t k c l k mdat_out mdat_in m_iso iso_ mdat_in mclk_out mclk_in iso_mclk_in iso mdat_out iso_ mclk_out iso_kdat_out pin_mdat_in pin_mdat_out pin_mclk_out iso_kclk_out pin_mclk_in m d a t m c l k wake on non- specifc key wake on specifc key iso_ kdat_in spekey kbd wake on non- specifc key wake on specifc key spemse mouse iso_ kdat _in
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 176 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 177 revision 0.4 (06-03-05) datasheet chapter 16 watchdog timer the sch311x contains a watchdog timer (wdt). the watchdog time-out status bit may be mapped to an interrupt through the wdt_cfg runtime register. the sch311x wdt has a programmable time-out ranging from 1 to 255 minutes with one minute resolution, or 1 to 255 seconds with 1 second resolution. the units of the wdt timeout value are selected via bit[7] of the wdt_timeout register. the wdt time-out value is set through the wdt_val runtime register. setting the wdt_val register to 0x00 disables the wdt function (this is its power on default). setting the wdt_val to any other non-zero value will cause the wdt to reload and begin counting down from the value loaded. when the wdt count value reaches zero the counter stops and sets the watchdog time-out status bit in the wdt_ctrl runtime register. note: regardless of the current state of the wdt, the wdt time-out status bit can be directly set or cleared by the host cpu. two system events can reset the wdt: a keyboard interr upt or a mouse interrupt. the effect on the wdt for each of these system events may be indi vidually enabled or disabled through bits in the wdt_cfg runtime register. when a system event is enabled through the wdt_cfg register, the occurrence of that event will cause the wdt to reload the value stored in wdt_val and reset the wdt time-out status bit if set. if both system even ts are disabled, the wdt_ val register is not re- loaded. the watchdog timer may be configured to generate an interrupt on the rising edge of the time-out status bit. the wdt interrupt is mapped to an interrupt channel through the wdt_cfg runtime register. when mapped to an interrupt the interrupt request pin reflects the value of the wdt time- out status bit. the host may force a watchdog time-out to occur by writing a "1" to bit 2 of the wdt_ctrl (force wd time-out) runtime register. writing a "1" to this bit forces the wdt count value to zero and sets bit 0 of the wdt_ctrl (watchdog status). bit 2 of the wdt_ctrl is self-clearing. see the chapter 26, "runtime register," on page 311 for description of these registers.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 178 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 179 revision 0.4 (06-03-05) datasheet chapter 17 programmable clock output a clk_out pin is available on the sch311x. this will output a programm able frequency between 0.5 hz to 16 hz, and have the following characteristics: must run when vcc if off - could use 32khz clock accuracy is not an issue clock_out register at offset 3ch in runtime registers with the following programming: options for 0.25, 0.5, 1, 2, 4, 8, or 16 hz application note: no attempt has been made to synchronize the clock. as a result, glitches will occur on the clock output when different frequencies are selected. clock output control register vtr por = 0x00 3c (r/w) bit[0] enable 1= output enabled 0= disable clock output bit[3:1] frequency select 000= 0.25 hz 001= 0.50 hz 010= 1.00 hz 011= 2.00 hz 100= 4.00 hz 101= 8.00 hz 110= 16 hz 111 = reserved bit[7:4] reserved
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 180 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 181 revision 0.4 (06-03-05) datasheet chapter 18 reset generation the sch311x device has a reset generator with the following characteristics: output is open-drain pwrgd_out 3.3v, 3.3v vtr and 5v voltage trip monitors are always a source for the pwrgd_out. an internal version of nthermtrip signal from the hw monitor block, can be a source of pwrgd_out, selectable via a bit in the resgen register. a 1.6 sec watchdog timer can be a source for pwrgd_out, selectable via a bit in the resgen register. see section 18.1, "watchdog timer for resets on vcc_por," on page 182 for more details. the output pulse width is selectable via a strap option (see ), between 200 msec (default) or 500 msec. this pulse is applied to pwrgd_ out. the resgen strap is sampled at the deaserting edge of pcirst# or vcc por. the following table summarizes the strap option programmming. the programming for the resgen function is in t he regen register, runtime register offset 1dh as shown in table 18.2 . output must be low for at least 100 msec after 5v and 3.3v rails are valid. table 18.1 resgen strap option resgen delay 1 200 msec delay (approximate) default 0 500 msec delay (approximate) table 18.2 resgen programming resgen default = 00h 1dh (r/w) reset generator bit[0] wdt2_en: enable watchdog timer generation / select 0= wdt enabled - source for pwrgd_out (default) 1= wdt disabled - not source for pwrgd_out bit[1] thermtrip source select 0 = thermtrip not source for pwrgd_out ((default) 1 = thermtrip source for pwrgd_out bit[2] wdt2_ctl: wdt input bit bit[7:3] reserved
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 182 smsc sch311x datasheet figure 18.1 reset generation circuit (for illustrative purposes only) 18.1 watchdog timer for resets on vcc_por the watchdog timer is a mechanism to monitor the host?s activity. it is part of the reset generation circuitry. the watchdog timer has the following characteristics: feature enable/disable via a bit in a control register, accessible from the lpc. when enabled, the resgen wdt output is selected as a source for the pwrgd_out signal. watchdog input bit in a the resgen register, wdt2_ctl, reset to 0 via vcc_por, accessible from the lpc. the counter is reset by vcc_por. the counter w ill remain reset as long as vcc_por is active. counter will start when the following conditions are met: vcc_por is released if the host toggles the wdt2_ctl bit in resgen register, by writing a 0 followed by a 1, before the wdt has timed out, a 100 msec pulse is output.. after a timeout has occurred, a new timeout cycle does not begin until the host toggles the wdt2_ctl bit in resgen register, by writing a 0 followed by a 1. . this causes the counter to be reset to 1.6 seconds and begins to count again comparator and reset logic approx 140 msec delay 3.3vtr threshold comparator and reset logic 3.3v threshold1 comparator and reset logic 5v threshold2 reset # reset # nfprst pwrgd_ps ps_on strap = 1: 200 msec delay strap = 0: 500 msec delay (delays are approximate) rsmrst# pwrgd_out wdt (125 msec) vcc_porb resgen bit[0] wdt2_en debounce pwrok internal thermtrip# resgen bit[1] thermtrip sel clki32 resetb resgen bit[2] wdt2_ctl set to '1' for sch3116
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 183 revision 0.4 (06-03-05) datasheet 18.2 pwrgd_out timing the following figure illustrates the reset generation pulse timing based on normal power down and voltage trip conditions. figure 18.2 pwrgd_out timing table 18.3 wdt operation following vcc_por or edt2_ctl writing wdt2_ctl vcc_porb rst_wdt2 b counter reset condition x0 x yespower on 0 1 1 no state after vcc_porb. counter starts counting 0->1 1 1 yes write 1 to wdt2_ctl. counter reset and starts counting. 1->0 1 1 no write 0 to wdt2_ctl. no affect - counter running. x 1 0 yes counter timeout under normal conditions. pwrgd_out ps_on# (a) normal power down due to ps_on# deasserted pwrgd_out 3.3v or 5v or 12v threshold (b) power down due to drop in power supply rsmrst#=1 rsmrst#=1 t1 t2
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 184 smsc sch311x datasheet note: the time from the input pin to the output pin includes the output buffer delay. 18.3 power supply voltag e scaling and tolerances the 5v supply is scaled internally. the input resistance is 20kohms (min). the voltage trip point is 4.45v (nominal) with a tolerance of 0.15v (range: 4.3v-4.6v). for the 3.3v vtr and 3.3v supplies, the voltage trip point is 2.8v (nominal) with a tolerance of 0.1v (range: 2.7v-2.9v). table 18.4 pwrgd_out timing name description typical value units t1 ps_on# pin high to pwrgd_out pin low 3 ns t2 power supply (at pin) drop below threshold to pwrgd_out pin low 1 15 ns
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 185 revision 0.4 (06-03-05) datasheet chapter 19 buffered pci outputs 19.1 buffered pci outputs interface the sch3112 and sch3114 devices provide three software controlled pcirst# outputs and one buffered ide reset. application note: these outputs are note available on the sch3116. table 19.1 describes the interface. 19.1.1 ide reset output nide_rstdrv is an open drain buffered copy of pci_reset#. this signal requires an external 1k ? pull-up to vcc or 5v. this pin is an output only pin which floats when vcc=0. the pin function?s default state on vtr por is the nide_rst function; however the pin function can be programmed to the a gpo pin function by bit 2 in the pme_sts1 gpio control register. the nide_rstdrv output has a programmable forced reset. the software control of the programmable forced reset function is located in the gp4 gpio data register. when the gp44 bit (bit 4) is set, the nide_rstdrv output follows the pci_reset# input; this is the default state on vtr por. when the gp44 bit is cleared, the nide_rstdrv output stays low. see gp44 and gp4 for runtime register description ( chapter 26, "runtime register," on page 311 ). table 19.1 buffered pci outputs interface name buffer power well description pci_reset# pci_i vcc pci reset input nide_rstdrv io8 vcc ide reset output npcirst1 io8 vtr buffered pci reset output npcirst2 io8 vtr buffered pci reset output npcirst3 io8 vtr buffered pci reset output table 19.2 nide_rstdrv truth table pci_reset# (input) nide_rstdrv (output) 00 1hi-z table 19.3 nide_rstdrv timing name description min typ max units tf nide_rstdrv high to low fall time. measured form 90% to 10% 15 ns
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 186 smsc sch311x datasheet 19.1.2 npcirstx output logic the npcirst1, npcirst2, and npcirst3 outputs are 3.3v balance buffer push-pull buffered copies of pci_reset# input. each pin fu nction?s default state on vtr por is the npcirstx function; however, the pin function can be programmed to the a gpo pin (output only) function by bit 2 in the corresponding gpio control register (gp45, gp46, gp47). each npcirstx output has a programmable force reset. the software control of the programmable forced reset function is located in the gp4 gpio data register. when the corresponding (gp45, gp46 gp47) bit in the gp4 gpio data register is set, the npcirstx output follows the pci_reset# input; this is the default state on vtr por. when the corresponding (gp45, gp46, gp47) bit in the gp4 gpio data register is cleared, the npcirstx output stays low. see gp4 for runtime register description. when the vtr power is applied, vcc is powered down, and the gpio control register?s contents are default, the npcirstx pin output is low. the figure 19.1 illustrates the npcirstx function. the fi gure is for illustration purposes only and in not intended to suggest specific implementation details. figure 19.1 npcirstx logic tpropf nide_rstdrv high to low propagation time. measured from pci_reset# to nide_rstdrv. 22 ns co output capacitance 25 pf cl load capacitance 40 pf table 19.3 nide_rstdrv timing (continued) name description min typ max units vtr pci_reset# pci_i(vcc) internal vcc active high power good signal vtr one bit in the gp4 gpio data default = 1 on vtr por this signal is 0 when vcc=0 npcirstx note: this figure is for illustration purposes only and not meant to imply specific implementation details
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 187 revision 0.4 (06-03-05) datasheet chapter 20 power control features application note: the following function is not available in the sch3116 device. the sch3112 and sch3114 devices are able to turn on the power supply when the power button located on the pc chassis is pressed, when the power button located on the keyboard is pressed, or when recovering from a power failure. the signals used to support these features are: pb_in# pb_out# slp_sx# ps_on# table 20.1 and figure 20.1 describe the interface and connectivity of the following power control features: 1. front panel reset with input debounce, power supply gate, and powergood output signal generation 2. ac recovery circuit 3. keyboard wake on mouse. 4. slp_sx# pme wakeup table 20.1 power control interface name device(s) support directio n description pb_in# sch3112, sch3114 input power button input pb_out# sch3112, sch3114 output power good output ps_on# sch3112, sch3114 output power supply on output slp_sx# sch3112, sch3114 input from south bridge pwrgd_ps sch311x input power go od input from power supply nfprst sch311x input reset input from front panel pwrgd_out sch311x output power good output ? open drain nio_pme sch311x output power management event output signal allows this device to request wakeup.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 188 smsc sch311x datasheet figure 20.1 power control block diagram notes: the ps_on# level will be latched in the previous state bit located in the power recovery register on the falling edge of vtr pwr_gd, vcc pwr_gd, or pwr_ok, which ever comes first. if mode 1 is enabled, this bit will be used to determine the previous state. the previous state is equal to the previous state bit located in the power recover register, if configured for mode 1. if mode 2 is enabled, t he previous state is determined by one of the bits power failure recovery logic keyboard controller w/ modified logic for keyboard power button pb_out# control logic wake on specific key power supply on logic pb_en kb_en pb_in# apf bit[0] apf bit[1] vtr pwr_gd q q set clr d l pulse width > 0.5 sec pb_out# sampled ps_on# value (battery powered) 0=off, 1=on slp_sx# ps_on# ps_on# latch 1 min 1 sec delay previous state 2 0=off 1=on delay pfr_en key- board con- troller nio_pme wakeup wake on specific key pme_sts6 (sticky bits) (vtr) pme_en6 (vbat) spekey other sx wake up sources pulse width > 0.5 sec. kb_pb_sts combina- torial logic pb_in# nio_pme (vtr) pwrok debounce ckt reset generation logic other reset generator sources nfprst pwrgd_ps pwrgd_out
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 189 revision 0.4 (06-03-05) datasheet in the 8-bit shift register, which is stored in the ps_on register located in the runtime register block at 4ah. the bit selected in mode 2 is determined by the the state of the ps_on# previous state select bits located in runtime register 53h. 20.1 nio_pme pin use in power control the nio_pme signal can be used to control the state of the power supply. the nio_pme signal will be asserted when a pme event occurs and the pme logic is enabled. the following is a summary of the power control pme events (see figure 20.1 ): 1. pb_in# input signal assertion. (sch3112, sch3114 devices only) 2. when the wake on specific key logic detects the programmed keyboard event it will generate a wake event (kb_pb_sts). 3. upon returning from a power failure. each pme wake event sets a status bit in the pme_sts6 register. if the corresponding enable bit in the pme_en6 register is set then the nio_pme pin will be asserted. the enable bits in the pme_en6 register default to set and are vbat powered. refer to chapter 15, "pme support," on page 171 for description of the pme support for this pme event. 20.2 front panel reset the inputs, pwrgd_ps and nfprst have hysteresis and are internally pulled to vtr through a 30ua resistor. the nfprst is debounced internally. the nfprst input has internal debounce circuitry that is valid on both edges for at least 16ms before the output is changed. the 32.768khz is used to meet the timing requirement. see figure 20.2 for nfprst debounce timing. note: the actual minimum debounce time is 15.8msec the 32.768 khz trickle input must be connected to supply the clock signal for the nfprst debounce circuitry. the sch311x has a legacy feature which is incompatible with use of the nfprst input signal. an internal 32khz clock source derived fr om the 14mhz (vcc powered) can be selected when the external 32khz clock is not connected. application note: the 32.768 khz trickle input must be connected to supply the clock signal for the nfprst debounce circuitry. table 20.2 internal pwrok truth table inputs output nfprst pwrgd_ps internal pwrok 000 010 100 111
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 190 smsc sch311x datasheet figure 20.2 nfprst debounce timing 20.3 a/c power failure recover y control (sch3112 and sch3114 devices only) the power failure recovery control logic, which is powered by vtr, is used to return a system to a pre-defined state after a power failure (vtr=0v). the power control register, which is powered by vbat, contains two bits defined as apf (after power failure). these bits are used to determine if the power supply should be powered on, powered off, or set to the previous power state before vtr was removed as shown in table 20.3 . power failure recovery registers that are required to retain their state through a power failure are powered by vbat. two modes may be used to determine the previous state: mode 1: (suggested if pwr_ok is selected& enabled), which is enabled when bit[3] ps_on# sampling is disabled, latches the current value of the ps_on# pin when vcc, vtr, or pwr_ok (if enabled) transition to the inactive state, whicheve r comes first. this value is latched into bit[4] previous state bit located in the power recovery register located at offset 49h and is used to determine the state of the ps_on# pin when vtr becomes active. mode 2 is enabled when bit[3] ps_on# sampling is enabled. to determine the previous power state, the ps_on# pin is sampled every 0.5 seconds while vtr is greater than ~2.2volts. this sample is inserted into a battery powered 8-bit shift register. the hardware will select a bit from the shift register depending on the value of the ps_on# previous state select bits located in the runtime register block at offset 53h to determine the state of the ps_on# pin when vtr becomes active. the value in the 8-bit shift register is latched into the ps_on register at offset 4ah in the runtime register block after vtr power is returned to the system, but before the internal shift register is cleared and activated. the ps_on register is a battery powered register that is only reset on a vbat por. notes: in mode 2, when vtr falls below ~2.2volts the current value of the ps_on# pin will be latched into bit [4] previous state bit located in the power recovery register at offset 49h. this bit will nfprst (before debounce) press release 15.8msec min 15.8msec min the next nfprst press will be detected starting here internal nfprst (after debounce)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 191 revision 0.4 (06-03-05) datasheet not be used by hardware, but may be read by software to determine the state of the ps_on# pin when the power failure occurred. the time selected for the ps_on# previous state bits should be greater than or equal to the time it takes for resume reset to go inactive to the time vtr is less than ~2.2 volts. if a power failure occurs and the power supply should be in the on state, the power failure recovery logic will assert the pb_out# pin active low for a minimum pulse width of 0.5sec when vtr powers on. if the power supply should remain off, the power failure recovery logic will have no effect on the pb_out# pin. the following table defines the possible states of pb_out# after a power failure for each configuration of the apf bits. note: it is a requirement that the afterg3 bit located in the ich controller be programmed to 1 for this ac recovery logic to be used. 20.3.1 pb_out# and ps_on# the pb_out# and ps_on# signals are used to control the state of the power supply. the pb_out# signal will be asserted low if the pb_in# is asserted and enabled, if the kb_in# is asserted and enabled, or if recovering from a power failure and the power supply should be turned on. refer to figure 20.1 . the following is a summary of these signals: 1. if the pb_in# signal is enabled and asserted low, the pb_out# signal should be held low for as long as the pb_in# signal is held low. 2. if the internal kb_pb_sts# signal (see figure 14) is asserted low, the pb_out# signal is held low for as long as the kb_ pb_sts# signal is held low. 3. if returning from a power failure and the power supply need to be turned on, a minimum of a ~0.5sec pulse is asserted on the pb_out# pin. note: this pulse width is less than 4 seconds, since a 4 second pulse width signifies a power button override event. the ps_on# signal is the inverse of the slp_sx# input signal. this signal goes directly to the power supply to turn the supply on or off. the sch#11x indirectly controls the ps_on# signal by asserting the pb_out#. pb_out# will be interpreted by an external device (i.e., ich controller), which will use this information to control the slp_sx# signal. note: two modes have been added to save the state of the ps_on# pin in the event of a power failure. this allows the system to recover from a pow er failure. see section 20.3, "a/c power failure recovery control (sch3112 and sch3114 devices only)," on page 190 . table 20.3 definition of apf bits apf[1:0] definition of apf bits afterg3 bit (located in ich) pb_out# 00 11 power supply off 1 ???? 01 power supply on 1 10 power supply set to previous state (on) 1 10 power supply set to previous state (off) 1 ????
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 192 smsc sch311x datasheet 20.3.2 power supply timing diagrams the following diagrams show the relative timing for the i/o pins associated with the power control logic. these are conceptual diagrams to show the flow of events. figure 20.3 power supply during normal operation figure 20.4 power supply after power failure (return to off) pb_in# pb_out# vtr (on) ps_on# slp_sx# vcc pb_in# (high) pb_out# (high) vtr ps_on# (high) slp_sx# (low) vcc(off) power failure
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 193 revision 0.4 (06-03-05) datasheet figure 20.5 power supply after power failure (return to on) 20.4 resume reset signal generation nrsmrst signal is the reset output for the ich resume well. this signal is used as a power on reset signal for the ich. the sch311x detects when vtr voltage raises above v trip and provides a delay before generating the rising edge of nrsmrst. see section 29.10, "resume reset signal generation," on page 383 for a detailed description of how the nrsmrst signal is generated. 20.5 keyboard power button the sch311x has logic to detect a keyboard make/break scan codes that may be used for wakeup (pme generation). the scan codes are programmed in the keyboard scan code registers, located in the runtime register block, from offset 0x5f to 0x63 from the base address located in the primary base i/o address in logical device a. these regist ers are powered by vbat and are reset on a vbat por. the following sections will describe the format of the keyboard data, the methods that may be used to decode the make codes, and the methods that may be used to decode the break codes. the wake on specific key code feature is enabled for the assertion of the nio_pme signal when in sx power state or below see pme_sts1. 20.5.1 keyboard data format data transmissions from the keyboard consist of an 11-bit serial data stream. a logic 1 is sent at an active high level. the following table shows the functions of the bits. pb_in# pb_out# vtr ps_on# slp_sx# vcc power failure
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 194 smsc sch311x datasheet the process to find a match for the scan code stor ed in the keyboard scan code register meets the timing constraints as defined by the ibm personal system/2? model 50 and 60 technical reference, dated april 1987. the timing for the keyboard clock and data signals are shown in chapter 29, "timing diagrams," on page 365 . (see section 29.9, "keyboard/mouse interface timing," on page 382 ). 20.5.1.1 method for receiving data is as follows: the wake on specific key logic snoops the keyboard interface for a particular incoming scan code, which is used to wake the system through a pme event. these scan code s may be comprised of a single byte or multiple bytes. to determine when the first key code is being received, the wake on specific key logic begins sampling the data at the first falling edge of the keyboard clock for the start bit. the data is sampled on each falling edge of t he clock. the hardware decodes the byte received and determines if it is valid (i.e., no parity error). valid scan code bytes received are compared to the programmed scan code as determined by bits [3:2] spekey scan code located in the pme_sts1 runtime register located at offset 0x64. if the scan code(s) received matches the value(s) programmed in the keyboard scan code registers then a wake on specific key status event has occurred. the wake on specific key status event is mapped to the pme and power button logic. the snooping logic always checks the incoming data byte for a parity error. the hardware samples the parity bit and checks t hat the 8 data bits plus the parity bi t always have an odd number of 1?s (odd parity) . if a parity error is detected the state machine used to decode the incoming scan code is reset and begins looking for the first byte in the keyboard scan code sequence. this process is repeated until a match is found. see section 20.5.2, "system for decoding scan code make bytes received from the keyboard," on page 195 and section 20.5.3, "system for decoding scan code break bytes received from the keyboard," on page 196 . if the scan code received matches the programmed make code stored in the keyboard scan code registers and no parity error is detected, then it is considered a match. when a match is found and if the stop bit is 1, a pm e wake event (kb_pb_sts-see figure 20.1 ) will be generated within 100usec of the falling edge of clock 10 of the last byte of the sequence.this wake event may be used to generate the assertion of the nio_pme signal when in sx power state or below. pme_sts1 for description of the pme support for this pme event. the state machine will reset and repeat the proce ss until it is shut off by setting the spekey_en bit in the pme_sts1 register to ?1?. bit function 1 start bit (always 0) 2 data bit 0 (least significant bit) 3 data bit 1 4 data bit 2 5 data bit 3 6 data bit 4 7 data bit 5 8 data bit 6 9 data bit 7 (most significant bit) 10 parity bit (odd parity) 11 stop bit (always 1)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 195 revision 0.4 (06-03-05) datasheet the spekey_en bit at bit 1 of the pme_sts1 register at 0xf0 in logical device a is used to control the ?wake-on-specific feature. this bit is used to turn the logic for this feature on and off. it will disable the 32khz clock input to the logic. the logic will draw no power when disabled. the bit is defined as follows: 0= ?wake on specific key? logic is on (default) 1= ?wake on specific key? logic is off the state machine used to snoop the incoming data from the keyboard is synchronized by the clock high and low time. if the kclk signal remain s high or low for a nominal 125usec during the transmission of a byte, a timeout event is gener ated causing the snooping and scan code decoding logic to be reset, such that it will look for the first byte of the make or break scan code. 20.5.1.2 description of scan 1 and scan 2 scan 1: many standard keyboards (pc/xt, mfii, etc.) generate scan 1 make and break codes per key press. these codes may be generated as a single byte or mu lti-byte sequences. if a single byte is generated, the make code, which is used to indicate when a key is pressed, is a value between 0h and 7fh. the break code, which is used to indicate when a key is released, is equal to the make code plus 80h (i.e. 80h break code ffh). if a multi-byte sequence is sent it will send e0h before the make or break. example of single byte scan 1: make code = 37h, break code=b7h example of multi-byte scan 1: make code = e0h 37h, break code = e0h b7h. scan 2: the scan 2 make and break codes used in at and ps/2 keyboards, which are defined by the pc 8042 keyboard controller, use the same scan code when a key is pressed and when the key is released. a reserved release code, 0xf0, is sent by the keyboard immediately before the key specific portion of the scan code to indicate when that the key is released. example of single byte scan 2: make code = 37h, break code=f0h 37h example of multi-byte scan 2: make code = e0h 37h, break code = e0h f0h 37h. 20.5.2 system for decodi ng scan code make bytes received from the keyboard bit [3:2] of the spekey scan code, located in pme_ sts1 register, is used to determine if the hardware is required to detect a single byte make code or a multi-byte make code. table 20.4 summarizes how single byte and multi-byte scan codes are decoded. figure 20.6 sample single-byte make code figure 20.7 sample multi-byte make code keyboard scan code - make byte 1 37h keyboard scan code - make byte 1 keyboard scan code - make byte 2 msb lsb e0h 37h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 196 smsc sch311x datasheet note: in multi-byte scan codes the most significant byte (msb) will be received first. notes: x? represents a don?t care. by default, any time the kclk signal is high or low for a nominal 125usec during the transmission of a byte the scan code decode cycle will be reset and the next byte receiv ed will be treated as the first byte received in the scan code byte sequence. once a valid make code is detected the wake on specific key logic w ill generate a kb_pb_sts wake event (see figure 20.1 ). this wake event may be used to generate the assertion of the nio_pme signal when in sx power state or below. pme_sts1 for description of the pme support for this pme event 20.5.3 system for decodi ng scan code break by tes received from the keyboard to accommodate different keyboards, there are three options for determining when the wake on specific key logic deasserts th e kb_pb_sts wake event (see in figure 20.1 ) going to the sticky bits in pme_sts1 and pme_sts1. dea ssertion of the kb_pb_sts internally does not deasset the pme status bit. the keyboard power button release bits (bits [4:5]) in pme_sts1 register may select these kb_pb_sts options. see chapter 26, "runtime register," on page 311 . a detailed description of each option is shown below. table 20.4 decoding keyboard scan code for make code spekey scan code number of bytes in make code description bit[3] bit[2] x 0 1 byte the wake on specif ic key logic will compare each valid data byte received with the keyboard scan code ? make byte 1 located in the runtime register block at offset 5fh. if the data byte received matches the value stored in the register, a wake on specific key status event will be generated. this wake event may be used to generate the assertion of the nio_pme si gnal. pme_sts1. note: if the value programmed in keyboard scan code ? make byte 1 is 00h it is treated as a don?t care and any valid scan code being compared to this byte will be a match. x 1 2 byte the wake on specific key logic compares each valid data byte received with the value programmed in the keyboard scan code ? make byte 1 located in the runtime register block at offset 5fh. if the data byte received matches the value stored in the register, the hardware compares the next byte received with the value programmed in the keyboard scan code ? make byte 2 located in the runtime register block at offset 60h. if the consecutive bytes received match the programmed values, a wake on specific key status event is generated. if the values do not match, if a parity error occurs, or if a timeout occurs, the state machine is reset and the process is repeated. if a specific key status event is generated then it may be used to generate the assertion of the nio_pme signal. pme_sts1 note: if the value programmed in keyboard scan code ? make byte 1 or keyboard scan code -make byte2 is 00h it is treated as a don?t care and any valid scan code being compared to this byte will be a match.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 197 revision 0.4 (06-03-05) datasheet option 1 (00): de-assert kb_pb_sts 0.5sec after it is asserted. this option allows the user to program any sc an code into the keyboard scan code ? make byte register(s). when a valid scan code is received that matches the value programmed in the keyboard scan code register(s), a 0.5sec pulse is generated on the kb_pb_sts wake event. regardless of the state of the spekey bits in pme_sts1 and pm e_sts1, no additional wake events will no additional wake events will occur for 0.5sec. figure 20.8 option 1: kb_pb_sts wake event fixed pulse width option 2 (01): de-assert kb_pb_sts after scan code not equal programmed make code this option may be used by keyboards that emit singl e byte or multi-byte make codes for each key pressed. when a valid scan code is received that matches the value programmed in the keyboard scan code ? make byte register(s), the kb_pb_sts wake event signal will be held asserted low until another valid scan code is received that is not equal to the programmed make code. regardless of the state of the spekey bits in pme_sts1 and pm e_sts1, no additional wake events will no additional wake events will occur until another valid scan code is received that is not equal to the programmed make code. figure 20.9 option 2: assert kb_pb_sts wake event until scan code not programmed make code notes: the valid scan code may be 1 or 2 bytes depending on the spekey scancode bits located in the pme_sts1 runtime register at offset 64h. a valid scan code for single byte codes means that no parity error exists. a valid scan code for multi-byte scan codes requires that no parity erro r exists and that the first byte received matches the value programmed in the keyboard scan code ? make byte 1 located in the runtime register block at offset 5fh. this value is typically e0h for scan 1 and scan 2 type keyboards. (example: the acpi power scan 2 make code is e0h, 37h) section 20.5.1.2, "description of scan 1 and scan 2," on page 195 option 3 (10): de-assert kb_pb_sts after scan code equal break code this option may be used with single byte and multi-byte scan 1 and scan 2 type keyboards. the break code can be configured for a specific br eak code or for any valid break code. the kb_pb_sts wake event signal w ill be held asserted low until a valid break code is detected. the break code can be configured for a specific break code or for any valid break code. regardless of the kb_pb_sts valid scan code (1 or 2 bytes) scan code keyboard input pulse width=0.5sec kb_pb_sts valid scan code= programmed make code keyboard input pulse width valid scan code not = programmed make code invalid scan code
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 198 smsc sch311x datasheet state of the spekey bits in pme_sts1 and pme_st s1, no additional wake events will occur until another until a valid break code is detected. note: table 20.5 defines how the scan code will be decoded for the break code. once a valid break code is detected, the keyboard power butt on event will be de-ass erted as shown in figure 20.10 . figure 20.10 option 3: de-assert kb_pb_sts when scan code equal break code note: the spekey scancode bits are located in the pme_sts1 register keyboard pwrbtn/spekey located at offset 64h. table 20.5 decoding keyboard scan code for break code spekey scan code scan code number of bytes in break code description bit[3] bit[2] 0 0 scan 1 1 byte the wake on specific key logic will compare each valid data byte received with the keyboard scan code ? break byte 1 located in the runtime register block at offset 61h. if the data byte received matches the value stored in the register, the wake on specific key status event ( kb_pb_sts) will be de-asserted. deassertion of the kb_pb_sts internally does not deasset the pme status bit. 0 1 scan 1 2 bytes the wake on specific key logic will compare each valid data byte received with the keyboard scan code ? break byte 1 located in the runtime register block at offset 61h. if the data byte received matches the value stored in the register, the next byte received will be compared to keyboard scan code ? break byte 2 located in the runtime register block at offset 62h. if this byte is a valid scan code and it matches the value programmed, the wake on specific key status (kb_pb_sts) will be de-asserted. deassertion of the kb_pb_sts internally does not deasset the pme status bit. if the values do not match, if a parity error occurs, or if a timeout occurs, the state machine will be reset and rep eat the process. 1 0 scan 2 2 bytes the wake on specific key logic will compare each valid data byte received with the keyboard scan code ? break byte 1 located in the runtime register block at offset 61h. if the data byte received matches the value stored in the register, the next byte received will be compared to keyboard scan code ? break byte 2 located in the runtime register block at offset 62h. if this byte is a valid scan code and it matches the value programmed, the wake on specific key status event (kb_pb_sts) will be de- asserted. deassertion of the kb_pb_sts internally does not deasset the pme status bit. if the values do not match, if a parity error occurs, or if a timeout occurs, the state machine will be reset and repeat the process. kb_pb_sts valid scan code= programmed make code keyboard input pulse width valid scan code = programmed break code invalid scan code
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 199 revision 0.4 (06-03-05) datasheet note: to de-assert wake on specific key status event (kb_pb_sts) on any valid break key the register containing the lsb of the break code should be programmed to 00h. if a keyboard scan code ? break byte register is programm ed to 00h then any valid scan code will be a match. the value 00h is treated as a don?t care. 20.6 wake on specific mouse event the device can generate sx wake events (where sx is the sleep state input) based on detection of specific mouse button clicks on a mouse connected to the mous e port interface (mdat and mclk pins). the following specific mouse events can be used for wake-up events: 1. any button click (left/right/middle) or any movement 2. any one click of left/right/middle button 3. one click of left button 4. one click of right button 5. two times click of left button 6. two times click of right button in addition to the idle detection logic there is st art bit time-out logic which detects any time mclk stays high for more that 115-145us. 1 1 scan 2 3 bytes the wake on specific key logic will compare each valid data byte received with the keyboard scan code ? break byte 1 located in the runtime register block at offset 61h. if the data byte received matches the value stored in the register, the next byte received will be compared to keyboard scan code ? break byte 2 located in the runtime register block at offset 62h. if the data byte received matches the value stored in the register, the next byte received will be compared to keyboard scan code ? break byte 3 located in the runtime register block at offset 63h. if this byte is a valid scan code and it matches the value (kb_pb_sts) will be de-asse rted. deassertion of the kb_pb_sts internally does not deasset the pme status bit. if the values do not match, if a parity error occurs, or if a timeout occurs, the state machine will be reset and rep eat the process. table 20.5 decoding keyboard scan code for break code (continued) spekey scan code scan code number of bytes in break code description bit[3] bit[2]
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 200 smsc sch311x datasheet
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 201 revision 0.4 (06-03-05) datasheet chapter 21 low battery detection logic the low battery detection logic monitors the battery voltage to detect if this voltage drops below 2.2v and/or 1.2v. if the device is powered by vbat only and the battery voltage is below approximately 1.2v, a vbat por will occur upon a vtr por. if the device detects the battery voltage is below approximately 2.2v while it is powered by vbat only or vtr (vcc=0v) the low_bat pme and smi status bits will be set upon a vcc por. when the external diode vo ltage drop is taken into account, these numbers become 1.5v and 2.5v, respectively. the low_bat pme event is indicated and enabled via the pme_sts1 and pme_sts1 registers. see pme_sts1 for a description of these registers. the low_bat smi event is indicated and enabled via the smi_sts1 and smi_en1 registers. see the chapter 26, "runtime register," on page 311 section for a description of these registers. the following figure illustrate s external battery circuit. figure 21.1 external battery circuit note that the battery voltage of 2.2v nominal is at the vbat pin of the device, not at the source. 21.1 vbat por when vbat drops below approximately 1.2v while both vtr and vcc are off, a vbat por will occur upon a vtr por. the low_bat pme and smi status bits is set to ?1? upon a vbat por. since the pme enable bit is not battery backed up and is cleared on vtr por, the vbat por event is not a wakeup event. when vcc returns, if the pme or smi enable bit (and other associated enable bits) are set, then the corresponding event will be generated. 21.2 low battery 21.2.1 under battery power if the battery voltage drops below approximately 2.2v under battery power (vtr and vcc off) then the low_bat pme and smi status bits will be set upon a vcc por. this is due to the fact that the low_bat event signal is only active upon a vcc po r, and therefore the low battery event is not a wakeup event. when vcc returns, if the pme or smi enable bit (and other associated enable bits) are set, then a corresponding event will be generated. ich lpc47m292 battery v batlow ~2.2v vbat sch311x
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 202 smsc sch311x datasheet 21.2.2 under vtr power if the battery voltage drops below approximately 2.2v under vtr power (vcc off) then the low_bat pme and smi status bits will be set upon a vcc por. the co rresponding enable bit (and other associated enable bits) must be set to generate a pme or an smi. if the pme enable bit (and other associated enable bits) were set prior to vcc going away, then the low battery event will generate a pme when vcc becomes active again. it will not generate a pme under vtr power and will not cause a wakeup event. if the smi enable bit (and other associated enable bits) were set prior to vcc going away, then the low battery event will generate an smi when vcc becomes active again. 21.2.3 under vcc power the low_bat pme and smi bits are not set when the part is under vcc power. they are only set upon a vcc por. see the section 21.2.2 .
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 203 revision 0.4 (06-03-05) datasheet chapter 22 battery backed security key register located at the secondary base i/o address of logical device a is a 32 byte cmos memory register dedicated to security key storage. this security key register is battery powered and has the option to be read protected, write protected, and lockable. the secondary base i/o address is programmable at offsets 0x62 and 0x63. see pme_sts1. table 22.1, "security key register summary" is a complete list of the security key registers. table 22.1 security key register summary register offset (hex) vbat por register 00 0x00 security key byte 0 01 0x00 security key byte 1 02 0x00 security key byte 2 03 0x00 security key byte 3 04 0x00 security key byte 4 05 0x00 security key byte 5 06 0x00 security key byte 6 07 0x00 security key byte 7 08 0x00 security key byte 8 09 0x00 security key byte 9 0a 0x00 security key byte 10 0b 0x00 security key byte 11 0c 0x00 security key byte 12 0d 0x00 security key byte 13 0e 0x00 security key byte 14 0f 0x00 security key byte 15 10 0x00 security key byte 16 11 0x00 security key byte 17 12 0x00 security key byte 18 13 0x00 security key byte 19 14 0x00 security key byte 20 15 0x00 security key byte 21 16 0x00 security key byte 22 17 0x00 security key byte 23 18 0x00 security key byte 24 19 0x00 security key byte 25
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 204 smsc sch311x datasheet access to the security key register block is controlled by bits [2:1] of the security key control (skc) register located in the configuration register block, logical device a, at offset 0xf2. the following table summarizes the function of these bits. note: when bit[1] (read-lock) is ?1? all reads to this re gister block will return 00h. as an added layer of protection, bit [0] skc register lock bit has been added to the security key control register. this lock bit is used to block write access to the write-lock and read-lock bits defined in the table above. once this bit is set it can only be cleared by a vtr por, vcc por, and pci reset. see pme_sts1 for the definition of the security key register. 1a 0x00 security key byte 26 1b 0x00 security key byte 27 1c 0x00 security key byte 28 1d 0x00 security key byte 29 1e 0x00 security key byte 30 1f 0x00 security key byte 31 table 22.2 description of security ke y control (skc) register bits[2:1] bit[2] (write-lock) bit[1] (read-lock) description 0 0 security key bytes[31:0] are read/write registers 0 1 security key bytes[31:0] are write-only registers 1 0 security key bytes[31:0] are read-only registers 1 1 security key bytes[31:0] are no t accessible. all reads/write access is denied. table 22.1 security key register summary (continued) register offset (hex) vbat por register
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 205 revision 0.4 (06-03-05) datasheet chapter 23 temperature monitoring and fan control the hardware monitoring (hwm) block contains the temperature monitoring and fan control functions. the following sub-sections describe the hwm block features. 23.1 block diagram figure 23.1 hwm block embedded in sch311x hwm block digital sio logic analog tach1 tach2 tach3 remote2+ remote2- remote1+ remote1- pwm1 pwm2 pwm3 nhwm_int fan control & monitoring interrupt generation logic thermtrip monitoring logic hwm registers lpc interface index data lpc interface block runtime reg's (logical device a)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 206 smsc sch311x datasheet 23.2 hwm interface the sch311x hwm block registers are accessed throu gh an index and data register located at offset 70h and 71h, respectively, from the the address programmed in the base i/o address in logical device a (also referred to as the runtime register set). figure 23.2 hwm register access 23.3 power supply the hwm block is powered by standby power, hvtr , to retain the register settings during a main power (sleep) cycle. the hwm block does not operate when vcc=0 and hvtr is on. in this case, the h/w monitoring logic will be held in reset and no monitoring or fan control will be provided. following a vcc por, the h/w monitoring logic will begin to operate based on programmed parameters and limits. the fan tachometer input pins are protected agai nst floating inputs and the pwm output pins are held low when vcc=0. note: the pwm pins will be forced to ?spinup? (if enabled) when pwrg d_ps goes active. see ?pwm fan speed control? on page 218. 23.4 resetting the sch311 x hardware monitor block 23.4.1 vtr power-on reset all the registers in the hardware monitor block, except the reading registers, reset to a default value when vtr power is applied to the block. the default state of the register is shown in the register summary table located in pme_sts1. the default state of reading registers are not shown because these registers have indeterminate power on values. note: usually the first action after power up is to write limits into the limit registers. hwm registers 00h ffh base + 70h hwm_index base + 71h hwm_data logical device 0ah runtime registers
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 207 revision 0.4 (06-03-05) datasheet 23.4.2 vcc power-on reset the pwrgd_ps signal is used by the hardware-mo nitoring block to determine when a vcc por has occurred. the pwrgd_ps signal indicates that the vcc power supply is within operation range and the 14.318mhz clock source is valid. note: throughout the description of the hardware monitoring block vcc por and pwrgd_ps are used interchangeably, since the pwrgd_ps is used to generate a vcc por. all the hwm registers will retain their value through a sleep cycle unless otherwise specified. if a vcc por is preceded by a vtr por the registers will be reset to their default values (see pme_sts1). the following is a list of the registers and bits that are reset to their default values following a vcc por. fantach1 lsb register at offset 28h fantach1 msb register at offset 29h fantach2 lsb register at offset 2ah fantach2 msb register at offset 2bh fantach3 lsb register at offset 2ch fantach3 msb register at offset 2dh bit[1] lock of the ready/lock/start register at offset 40h zone 1 low temp limit at offset 67h zone 2 low temp limit at offset 68h zone 3 low temp limit at offset 69h bit[3] trdy of the configuration register at offset 7fh top temperature remote diode 1 (zone 1) register at offset aeh top temperature remote diode 2 (zone 3) register at offset afh top temperature ambient (zone 2) register at offset b3h 23.4.3 soft reset (initialization) setting bit 7 of the configuration register (7fh) performs a soft reset on all the hardware monitoring registers except the reading registers. this bit is self-clearing. 23.5 clocks the hardware monitor logic operates on a 90khz nominal clock frequency derived from the 14mhz clock input to the sio block. the 14mhz clock source is also used to derive the high pwm frequencies. 23.6 input monitoring the sch311x device?s monitoring function is started by writing a ?1? to the start bit in the ready/lock/start register (0x40). measured values from the temperature sensors are stored in reading registers. the values in the reading registers can be accessed via the lpc interface. these values are compared to the programmed limits in the limit registers. the out-of-limit and diode fault conditions are stored in the interrupt status registers. note: all limit and parameter registers must be set before the start bit is set to ?1?. once the start bit is set, these registers become read-only.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 208 smsc sch311x datasheet 23.7 monitoring modes the hardware monitor block supports two monitoring modes: continuous mode and cycle mode. these modes are selected using bit 1 of the special function register (7ch). the following subsections contain a description of these monitoring modes. the time to complete a conversion cycle depends upon the number of inputs in the conversion sequence to be measured and the amount of averaging per input, which is selected using the avg[2:0] bits in the special function register (s ee the special function register, 7ch). for each mode, there are four options for the num ber of measurements that are averaged for each temperature reading. these options are selected using bits[7:5] of the special function register (7ch). these bits are defined as follows: bits [7:5] avg[2:0] the avg[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware monitor before the reading registers are updated (). the avg[2:0] bits are priority encoded where the most significant bit has highest priority. for example, when the avg2 bit is asserted, 32 averages will be performed for each measurement bef ore the reading registers are updated regardless of the state of the avg[1:0] bits. note: the default for the avg[2:0] bits is ?010?b. 23.7.1 continuous monitoring mode in the continuous monitoring mode, the sampling and conversion process is performed continuously for each temperature reading after the start bit is set high. the time for each temperature reading is shown above for each measurement option. the continuous monitoring function is started by doing a write to the ready/lock/start register, setting the start bit (bit 0) high. the part then performs a ?round robin? sampling of the inputs, in the order shown below (see table 23.2 ). sampling of all values occurs in a nominal 150.8 ms (default - see table 23.2 ). when the continuous monitoring function is started, it cycles through each measurement in sequence, and it continuously loops through the sequence appr oximately once every 150.8 ms (default - see ). table 23.1 avg[2:0] bit decoder sftr[7:5] measurements per reading nominal total conversion cycle time (msec) avg2 avg1 avg0 remote diode 1 remote diode 2 ambient 0 0 0 128 128 8 587.4 001 16 16 1 73.4 01x161616 150.8 1xx323232 301.5 table 23.2 adc conversion sequence sampling order register 1 remote diode temp reading 1 2 ambient temperature reading 3 remote diode temp reading 2
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 209 revision 0.4 (06-03-05) datasheet each measured value is compared to values stored in the limit registers. when the measured value violates the programmed limit the hardware monitor block will set a corresponding status bit in the interrupt status registers. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. the results of the sampling and conversions can be found in the reading registers and are available at any time. 23.7.2 cycle monitoring mode in cycle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to repeat the process. it repeats the sampling and conversion pr ocess typically every 1.151 seconds (1.3 sec max - default averaging enabled). the sampling and conversion of each temperature reading is performed on ce every monitoring cycle. th is is a power saving mode. the cycle monitoring function is started by doing a wr ite to the ready/lock/start register, setting the start bit (bit 0) high. the part then performs a ?round robin? sampling of the inputs, in the order shown above. when the cycle monitoring function is started, it cycles through each measurement in sequence, and it produces a converted temperature reading for each input. the state machine waits approximately one second before repeating this process. each measured value is compared to values stored in the limit registers. when the measured value violates (or is equal to) the programmed limit the hardware monitor block will set a corresponding status bit in the interrupt status registers. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. the results of each sampling and conversion can be found in the reading registers and are available at any time, however, they are onl y updated once per conversion cycle. 23.8 interrupt status registers the hardware monitor block contains two primary interrupt status registers (isrs): interrupt status register 1 (41h) interrupt status register 2 (42h) there is also a secondary set of interrupt status registers: interrupt status register 1 - secondary (a5h) interrupt status register 2 - secondary (a6h) notes: the status events in the primary set of interrupt status registers is mapped to a pme bit, an smi bit, to serial irq (see interrupt event on serial irq on page 214 ), and to the nhwm_int pin. the nhwm_int pin is deasserted when all of the bits in the primary isrs (41h, 42h) are cleared. the secondary isrs do not affect the nhwm_int pin. the primary and secondary isrs share all of the interrupt enable bits for each of the events. these registers are used to reflect the state of all temperature and fan violation of limit error conditions and diode fault conditions that the hardware monitor block monitors. when an error occurs during the conversion cycle, its corresponding bit is set (if enabled) in its respective interrupt status register. the bit remains set until the register bit is written to ?1? by software, at which time the bit will be cleared to ?0? if the associated error event no longer violates the limit conditions or if the diode fault condition no longer exists. writing ?1? to the register bit will not cause a bit to be cleared if the source of the status bit remains active. these registers default to 0x00 on a vcc por, vtr por, and initialization. (see resetting the sch311x hardware monitor block on page 206 .)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 210 smsc sch311x datasheet see the description of the interrupt status registers in pme_sts1. the following section defines the interrupt enable bits that correspond to the interrupt status registers listed above. setting or clearing these bits affects the operation of the interrupt status bits. 23.8.1 interrupt enable bits each interrupt event can be enabled into the interrupt status registers. see the figure below for the status and enable bits used to control the interrupt bits and nhwm_int pin. note that a status bit will not be set if the individual enable bit is not set. the following is a list of the interrupt enable registers: interrupt enable register - fan tachs (80h) interrupt enable register - temp (82h) note: clearing the individual enable bits will clear the corresponding individual status bit. clearing the individual enable bits. there are two cases and in both cases it is not possible to change the individual interrupt enable while the start bit is set. 1. the interrupt status bit will never be set when the individual interrupt enable is cleared. here the interrupt status bit will not get set when the start bit is set, regardless of whether the limits are violated during a measurement. 2. if an interrupt status bit had been set from a pr evious condition, clearing the start bit and then clearing the individual interrupt enable bit will not clear the associated interrupts status bit immediately. it will be cleared when the start bit is set, when th e associated reading register is updated.
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 211 revision 0.4 (06-03-05) datasheet figure 23.3 interrupt control int1 reg tach_en (ier2[0]) voltage_en (ier1[0]) temp_en (ier3[0]) int2 reg int3 reg nhwm_int int_en (sftr[2]) vtr_error_en (ier1[4]) vbat_error_en (ier1[1]) tach1 out-of-limit tach2 out-of-limit tach3 out-of-limit diode 1 fault vtr_error vbat_error 12v_error_en (ier1[6]) 12v_error diode 2 fault 2.5v_error_en (ier1[2]) vccp_error_en (ier1[3]) vcc_error_en (ier1[7]) 5v_error_en (ier1[5]) 2.5v_error vccp_error vcc_error 5v_error diode 1 limit ambient limit diode 2 limit int2 event int3 event pme status bits in sio block diode 1_en (ier3[2]) diode 2_en (ier3[3]) ambient_en (ier3[1]) tach1_en (ier2[1]) tach2 _en (ier2[2]) tach3 _en (ier2[3]) diode 1_en (ier3[2]) diode 2_en (ier3[3]) 2.5v_error (int1[0]) vccp_error (int1[1]) vcc_error (int1[2]) 5v_error (int1[3]) diode 1 limit (int1[4]) ambient limit (int1[5]) diode 2 limit (int1[6]) tach1 (int2[2]) tach2 (int2[3]) tach3 (int2[4]) vtr_error (int3[0]) vbat_error (int3[1]) 12v_error (int2[0]) diode 2 fault (int2[7]) diode 1 fault (int2[6]) int23 (int1[7]) + + + + from amta interrupt logic
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 212 smsc sch311x datasheet notes: the primary interrupt status registers, and the to p temp status register may be used to generate a hwm interrupt event (hwm_event). a hwm interrupt event may be used to generate a pme, smi, serial irq, or nhwm_int event. figure 23.3, "interrupt control" shows the interrupt status registers generating an interrupt event. to see how the top temp status register generates a top_temp_event see figure 23.14 amta interrupt mapping on page 234 . . the diode fault bits are not mapped directly to the nhwm_int pin. a diode fault condition forces the diode reading register to a value of 80h, which will generate a diode error condition. see section diode fault on page 212 . 23.8.2 diode fault the sch311x chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on the remote diode pins: the positive and negative terminal are an open circuit positive terminal is connected to vcc positive terminal is connected to ground negative terminal is connected to vcc negative terminal is connected to ground the occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the negative terminal is connected to ground. a temperature reading of 80h will cause the corresponding diode error bit to be set. this will cause the nhwm_int pin to become active if the individual, group (temp), and global enable (inten) bits are set. notes: the individual remote diode enable bits and the temp bit are located in the interrupt enable register 1 (7eh). the inten bit is located in bit[2] of special function register (7ch). when 80h is loaded into the remote diode reading register the pwm output(s) controlled by the zone associated with that diode inpu t will be forced to full on. see thermal zones on page 216 . if the diode is disabled, the fault bit in the interrupt status register will not be set. in this case, the occurrence of a fault will cause 00h to be loaded in to the associated reading register. the limits must be programmed accordingly to prevent unwanted fan speed changes based on this temperature reading. if the diode is disabled and a fault condi tion does not exist on the diode pins, then the associated reading register will contain a ?valid? read ing (e.g. a reading that is not produced by a fault condition.). 23.9 interrupt signal the hardware monitoring interrupt signal, which is us ed to indicate out-of-limit temperature, and/or fan errors, can be generated via a dedicated pin (nhwm_in t) or through pme status bits or smi status bits located in the runtime register block. to enable temperature event and/or fan events onto th e nhwm_int pin or the pme status bits or smi status bits, the following group enable bits must be set: to enable out-of-limit temperature events set bit[0] of the interrupt enable - temp register (82h) to ?1?. to enable fan tachometer error events set bit[0] of the interrupt enable - fan tachs register (80h) to ?1?.
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 213 revision 0.4 (06-03-05) datasheet 23.9.1 interrupt pin (nhwm_int) the nhwm_int function is used as an interrupt output for out-of-limit temperature and/or fan errors. the nhwm_int signal is on pin 114. to enable the interrupt pin to go active, set bit 2 of the special function register (7ch) to ?1?. note: if the nhwm_int pin is not enabled the pin will be tristate if the nhwm_int function is selected on the pin. see figure 23.3 on page 211 . the following description assumes that the interrupt enable bits for all events are set to enable the interrupt status bits to be set and no events are being masked. if the internal or remote temperature reading vi olates the low or high temperature limits, nhwm_int will be forced active low (if all the corresponding enable bits are set: individual enable bits (d1_en, d2_en, and/or amb_en), group enable bit (temp_en) and the global enable bit (inten)). this pin will remain low while the internal temp error bi t or one or both of the remote temp error bits in interrupt status 1 register is set and the corresponding enable bit(s) are set. the nhwm_int pin will not become active low as a result of the remote diode fault bits becoming set. however, the occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding diode error bit to be set. this will cause the nhwm_int pin to become active if enabled. the nhwm_int pin can be enabled to indicate fan errors. bit[0] of the interrupt enable 2 (fan tachs) register (80h) is used to enable this option. this pin will remain low while the associated fan error bit in the interrupt status register 2 is set. the nhwm_int pin will remain low while any bit is set in any of the interrupt status registers. reading the interrupt status registers will ca use the logic to attempt to clear th e status bits; however, the status bits will not clear if the interrup t stimulus is still active. the inte rrupt enable bit (special function register bit[2]) should be cleared by software before reading the interrupt status registers to insure that the nhwm_int pin will be re-asserted while an interrupt event is active, when the int_en bit is written to ?1? again. the nhwm_int pin may only become active while the monitor block is operational. 23.9.2 interrupt as a pme event the hardware monitoring interrupt signal is routed to the sio pme block. for a description of these bits see the section defining pme events. this signal is unaffected by the nhwm_int pin enable (int_en) bit (see figure 23.3 interrupt control on page 211 .) the therm pme status bit is located in the pme_sts1 runtime register at offset 04h located in the sio block. when a temperature or fan tachometer event causes a status bit to be set, the therm pme status bits will be set as long as the corresponding group enable bit is set. the enable bit is located in the pme_en1 register at offset 0ah. 23.9.3 interrupt as an smi event the hardware monitoring interrupt signal is routed to the sio smi block. for a description of these bits see the section defining smi events. this signal is unaffected by the nhwm_int pin enable (int_en) bit (see figure 23.3 interrupt control on page 211 .) the therm smi status bit is located in the smi_sts5 runtime register at offset 14h located in the sio block. when a temperature or fan tachometer event causes a status bit to be set, the therm smi status bits will be set as long as the corresponding group enable bit is set.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 214 smsc sch311x datasheet the enable bit is located in the smi_en5 register at offset 1ah. the smi is enabled onto the serirq (irq2) via bit 6 of the smi_en2 register at 17h. 23.9.4 interrupt event on serial irq the hardware monitoring interrupt signal is routed to the serial irq logic. this signal is unaffected by the nhwm_int pin enable (int_en) bit (see figure 23.3 interrupt control on page 211 .) this operation is configured via the interrupt select register (0x70) in logical device a. this register allows the selection of any serial irq frame to be used for the hwm nhwm_int interrupt (serirq9 slot will be used). see interrupt event on serial irq on page 214 . 23.10 low power mode the hardware monitor has two modes of operat ion: monitoring and sleep. when the start bit, located in bit[0] of the ready/lock/start register (0x40), is set to zero the hardware monitor is in sleep mode. when this bit is set to one the hardware monitor is fully functional and monitors the analog inputs to this device. sleep mode is a low power mode in which bias currents are on and the internal oscillator is on, but the the a/d converter and monitoring cycle are turned off. serial bus communication is still possible with any register in the hardware monitor block while in this low-power mode. notes: in sleep mode the pwm pins are held high forc ing the pwm pins to 100% duty cycle (256/256). the start a bit cannot be modified when the lock bit is set. 23.11 temperature measurement temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor pins (for measuring two ex ternal temperatures). see subsections below. note: the temperature sensing circuitry for the two remote diode sensors is calibrated for a 3904 type diode. 23.11.1 internal temperature measurement internal temperature can be measured by bandgap temperature sensor. the measurement is converted into digital format by internal adc. this data is converted in two?s complement format since both negative and positive temperature can be measured. this value is stored in internal temperature reading register (26h) and compared to the temperatur e limit registers (50h ? 51h). if this value violates the programmed limits in the internal hi gh temperature limit register (51h) and the internal low temperature limit register (50h) the corresponding status bit in interrupt status register 1 is set. if auto fan option is selected, the hardware will adjust the operation of the fans accordingly. see the section titled auto fan control operating mode on page 219 . 23.11.2 external temperature measurement the hardware monitor block also provides a way to measure two external temperatures using diode sensor pins (remote x+ and remote x-). the value is stored in the register (25h) for remote1+ and remote1- pins. the value is stored in the remote temperature reading register (27h) for remote2+ and remote2- pins. if these values violate the progr ammed limits in the associated limit registers, then the corresponding remote diode 1 (d1) or remote diode 2 (d2) status bits will be set in the interrupt status register 1.
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 215 revision 0.4 (06-03-05) datasheet if auto fan option is selected, t he hardware will adjust the operation of the fans accordingly. see auto fan control operating mode on page 219 . there are remote diode (1 or 2) fault status bits in interrupt status register 2 (42h), which, when one, indicate a short or open-circuit on remote thermal diode inputs (remote x+ and remote x-). before a remote diode conversion is updated, the status of the remote diode is checked. in the case of a short or open-circuit on the remote thermal diode inputs, the value in the corresponding reading register will be forced to 80h. note that this will cause the associated remote diode limit exceeded status bit to be set (i.e. remote diode x limit error bits (d1 and d2) are located in the interrupt status 1 register at register address 41h). the temperature change is computed by measuring th e change in vbe at two different operating points of the diode to which the remote x+ and remote x- pins are connected. but accuracy of the measurement also depends on non-ideality factor of the process the diode is manufactured on. 23.11.3 temperature data format temperature data can be read from the three temperature registers: internal temp reading register (26h) remote diode 1 temp reading register (25h) remote diode 2 temp reading register (27h) the following table shows several examples of the fo rmat of the temperature digital data, represented by an 8-bit, two?s complement word with an lsb equal to 1.0 0 c. table 23.3 temperature data format temperature reading (dec) re ading (hex) digital output -127 0 c -127 81h 1000 0001 ? ? ? ? -50 0 c -50 ceh 1100 1110 ? ? ? ? -25 0 c -25 e7h 1110 0111 ? ? ? ? -1 0 c -1 ffh 1111 1111 0 0 c 0 00h 0000 0000 +1 0 c 1 01h 0000 0001 ? ? ? ? +25 0 c 25 19h 0001 1001 ? ? ? ? +50 0 c 50 32h 0011 0010 ? ? ? ? +127 0 c 127 7fh 0111 1111 sensor error 128 80h 1000 0000
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 216 smsc sch311x datasheet 23.12 thermal zones each temperature measurement input is assigned to a thermal zone to control the pwm outputs in auto fan control mode. these zone assignments are as follows: zone 1 = remote diode 1 (processor) zone 2 = ambient temperature sensor zone 3 = remote diode 2 the auto fan control logic uses the zone temperature reading to control the duty cycle of the pwm outputs. the following sections describe the various fan control and monitoring modes in the part. 23.13 fan control this fan control device is capable of driving mu ltiple dc fans via three pwm outputs and monitoring up to three fans equipped with tachometer outputs in either manual fan control mode or in auto fan control mode. the three fan control outputs (pwmx pins) are controlled by a pulse width modulation (pwm) scheme. the three pins dedicated to monitoring the operation of each fan are the fantach[1:3] pins. fans equipped with fan tachom eter outputs may be connected to these pins to monitor the speed of the fan. 23.13.1 limit and conf iguration registers at power up, all the registers are reset to their default values and pwm[1:3] are set to ?fan always on full? mode. before initiating the monitoring cycle for either manual or auto mode, the values in the limit and configuration registers should be set. the limit and configuration registers are: registers 54h ? 5bh: tachx minimum registers 5fh ? 61h: zone x range/fanx frequency registers 5ch ? 5eh: pwmx configuration registers 62h ? 63h: pwm 1 ramp rate control registers 64h ? 66h: pwmx minimum duty cycle registers 67h ? 69h: zone x low temp limit registers 6ah ? 6ch: zone x temp absolute limit ? all fans in auto mode are set to full register 81h: tach_pwm association registers 90h ? 92h: tachx option registers registers 94h ? 96h: pwmx option registers the limit and configuration registers are defined in pme_sts1. notes: the start bit in register 40h ready/lock/start re gister must be set to ?1? to start temperature monitoring functions. setting the pwm configuration register to auto mode will not take effect until after the start bit is set 23.13.2 device set-up bios will follow the steps listed below to configur e the fan registers on this device. the registers corresponding to each function are listed. all st eps may not be necessary if default values are acceptable. regardless of all changes made by the bios to the limit and parameter registers during
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 217 revision 0.4 (06-03-05) datasheet configuration, the sch311x will continue to operate based on default values until the start bit, in the ready/lock/start register, is set. once the start bit is set, the sch311x will operate according to the values that were set by bios in the limit and parameter registers. following a vtr power-on-reset (loss of a/c power) the following steps must be taken: 1. set limits and parameters (not necessarily in this order) a. [5f-61h] set pwm frequencies and auto fan control range. b. [62-63h] set ramp rate control. c. [5c-5eh] set the fan spin-up delays. d. [5c-5eh] match each pwm output with a corresponding thermal zone. e. [67-69h] set the zone temperature low limits. f. [6a-6ch] set the zone temperature absolute limits. g. [64-66h] set the pwm minimum duty cycle. h. [81h] associate a tachometer input to a pwm output register i. [90-92h] select the tach mode of operation (mode 1 or mode 2) j. [90-92h] set the number of edges per tach reading k. [90-92h] set the ignore first 3 edges of tach input bit l. [90-92h] set the slow bit if tach reading should indicated slow fan event as fffeh and stalled fan event as ffffh. m. [94-96h] set the tach reading update rate n. [94-96h] set the tach reading guard time (mode 2 only) o. [94-96h] set the tach reading logic for opportunistic mode (mode 2 only) p. [94-96h] set the szen bit, which determines if the pwm output will ramp to off or jump to off. q. [abh] set the tach 1-3 mode r. [aeh, afh, b3h] set the top temperature remote 1, 2, ambient s. [b4h - b6h] min temp adjust temp remote 1-2, min temp adjust temp and delay amb, and min temp adjust delay 1-2 t. [b7h] tmin adjust enable u. [c4h, c5h, c9h] thermtrip temp limit remote 1, 2, ambient v. [ceh] thermtrip output enable w. [d1h, d6h, dbh] pwm1, 2, 3 max duty cycle 2. [40h] set bit 0 (start) to start monitoring 3. [40h] set bit 1 (lock) to lock the limit and parameter registers (optional). following a vcc power-on-reset (exiting sleep mode) the following steps must be taken. these steps are required for most systems in or der to prevent improper fan start-up due to the reset of the top temperature and zone low limit registers to their default values on active pwrgd_ps. 1. set the ramp rate to the min value [registers 62h and 63h]. 2. clear the start bit (bit 0 of register 40h) to stop monitoring 3. set the top temperature remote 1, 2, ambient registers [aeh, afh, b3h] to their initial values 4. set the zone temperature low limit registers [67-69h] to their initial values 5. set the start bit (bit 0 of register 40h) to start monitoring 6. set the lock bit (bit 1of register 40h) to lock the limit and parameter registers (optional) note: if not locked, the ramp rate can be set to a new value at a later time if desired [registers 62h and 63h].
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 218 smsc sch311x datasheet 23.13.3 pwm fan speed control the following description applies to pwm1, pwm2, and pwm3. note: the pwm output pins are held low when vcc=0. the pwm pins will be forced to ?spinup? when pwrgd_ps goes active. see ?spin up? on page 222. the pwm pin reflects a duty cycle that is determined based on 256 pwm duty cycle intervals. the minimum duty cycle is ?off?, when the pin is low, or ?full on? when the pin is high for 255 intervals and low for 1 interval. the invert bit (bit 4 of the pwmx configuration registers at 80h-82h) can be used to invert the pwm output, however, the default operation (following a vcc por) of the part is based on the pwm pin active high to turn the fans ?on?. when the invert bit is set, as long as power is not removed from the part, the inversion of the pin will apply thereafter. when describing the operat ion of the pwms, the terms ?full on ? and ?100% duty cycle? means that the pwm output will be high for 2 55 clocks and low for 1 clock (invert bit = 0). the exception to this is during fan spin-up when the pwm pin will be forced high for the duration of the spin-up time. the sch311x can control each of the pwm outputs in one of two modes: manual fan control operating mode: software controls the speed of the fans by directly programming the pwm duty cycle. auto fan control mode: the device automatically adjusts the duty cycle of the pwm outputs based on temperature, according to programmed parameters. these modes are described in sections that follow. 23.13.3.1 manual fan control operating mode (test mode) when operating in manual fan control operating mode, software controls the speed of the fans by directly programming the pwm duty cycle. the operation of the fa ns can be monitored based on reading the temperature and tachometer reading registers and/or by polling the interrupt status registers. the sch311x offers the option of generating an interrupt indicated by the nhwm_int signal. to control the pwm outputs in manual mode: to set the mode to operate in manual mode, write ?111? to bits[7:5] zone/mode, located in registers 5ch-5eh: pwmx configuration. the speed of the fan is controlled by the duty cyc le set for that pwm ou tput. the duty cycle must be programmed in registers 30h-32h: current pwm duty to monitor the fans: fans equipped with tachometer outputs can be monitored via the fantachx input pins. see section 23.14.2, "fan speed monitoring," on page 235 . if an out-of-limit condition occurs, the corresponding status bit will be set in the interrupt status registers. setting this status bit will generate an interrupt signal on the nhwm_int pin (if enabled). software must handle the interrupt condition and modify the operation of the device accordingly. software can evaluate the operation of the fan control device through the temperature and fan tachometer reading registers. when in manual mode, the current pwm duty cycle regi sters can be written to adjust the speed of the fans, when the start bit is set. these register s are not writable when the lock bit is set. note: the pwmx current duty cycle register is implemented as two separate registers: a read-only and a write-only. when a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software. the hardware updates the read- only pwmx current duty cycl e register on the beginning of a pwm cycle. if ramp rate control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(pwm frequency) seconds. typically, the delay will be 1/(2*pwm frequency) seconds.
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 219 revision 0.4 (06-03-05) datasheet 23.13.3.2 auto fan control operating mode the sch311x implements automatic fan control. in auto fan mode, this device automatically adjusts the pwm duty cycle of the pwm outputs, according to the flow chart on the following page (see figure 23.4 automatic fan control flow diagram on page 220). pwm outputs are assigned to a thermal zone base d on the pwmx configuration registers (see thermal zones on page 216 ). it is possible to have more than one pwm output assigned to a thermal zone. for example, pwm outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. at any time, if the temperature of a zone exceeds its absolute limit, all pwm outputs go to 100% duty cycle to provide maximum cooling to the system (except those fans that are disabled or in manual mode). it is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on its individual settings. if the start bit is one, the auto fan control block will evaluate the temperature in the zones configured for each fan in a round robin method. the auto fan control block completely evaluates the zones for all three fans in a maximum of 0.25sec.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 220 smsc sch311x datasheet figure 23.4 automatic fan control flow diagram *see pme_sts1 for details. when in auto fan control operating mode the hardware controls the fans directly based on monitoring of temperature and speed. to control the fans: 1. set the minimum temperature that will turn the fans on. this value is programmed in registers 67h- 69h: zone x low temp limit (auto fan mode only). the speed of the fan is controlled by the duty cycle set for that device. the duty cycle for the minimum fan speed must be programmed in registers 64h-66h: pwmx minimum duty cycle. this value corresponds to the speed of the fan when the temperature reading is equal to the minimum temperature limit setting. as the actual temperature increases and is above the zone limit temperature and below the absolute temperatur e limit, the pwm will be determined by a linear function based on the auto fan speed range bits in registers 5fh-61h. auto fan mode initiated temp >= abslimit (69~6b) override all pwm outputs to 100% duty cycle except if disabled or in manual mode temp >= limit (66~68) no no fan output at 0%? yes set fan speed based on auto fan range algorithm* no begin fan spin- up yes set fan output to 100% fan spinning up? spin up time elapsed? (5c-5e) yes begin polling cycle end polling cycle no no end fan spin up yes set fan to min pwm yes
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 221 revision 0.4 (06-03-05) datasheet the maximum speed of the fan for the linear auto fan function is programmed in the pwmx max registers (0d1h, 0d6h, 0dbh). when the temperature reaches the top of the linear fan function for the sensor (zone x low temp limit plus temperature range) the fan will be at the pwm maximum duty cycle. set the absolute temperature for each zone in regi sters 6ah-6ch: zone x temp absolute limit (auto fan mode only). if the actual temperature is equal to or exceeds the absolute temperature in one or more of the associated zones, all fans operating in auto mode will be set to full on, regardless of which zone they are operating in (except those that are disabled or configured for manual mode). note: fans can be disabled via the pwmx configuration re gisters and the absolute temperature safety feature can be disabled by writing 80h into the zone x temp absolute limit registers. to set the mode to operate in auto mode, set bits[7:5] zone/mode, located in registers 5ch-5eh: pwm configuration bits[7:5]=?000? for pwm on zone 1; bits[7:5]=?001? for pwm on zone 2; bits[7:5]=?010? for pwm on zone 3. if the ?hottest? option is chosen (101 or 110), then the pwm output is controlled by the zone that results in t he highest pwm duty cycle value. notes: software can be alerted of an out-of-limit condition by the nhwm_int pin if an event status bit is set and the event is enabled and the interrupt function is enabled onto the nhwm_int pin. software can monitor the operation of the fans through the fan tachometer reading registers and by the pwm x current pwm duty registers. it can also monitor current temperature readings through the temperature limit registers if hardware monitoring is enabled. fan control in auto mode is implemented wi thout any input from external processor . in auto ?zone? mode, the speed is adjusted automat ically as shown in t he figure below. fans are assigned to a zone(s). it is possible to have more than one fan assigned to a thermal zone or to have multiple zones assigned to one fan. figure 23.5 on page 222 shows the control for the auto fan algorithm. the part allows a minimum temperature to be set, below which the fan will run at minimum speed. the minimum speed is programmed in the pwmx minimum duty cycle regi sters (64h-66h) and may be zero. a temperature range is specified over wh ich the part will automatically adjust the fan speed. the fan will go to a duty cycle computed by the auto fan algori thm. as the temperature rises, th e duty cycle will increase until the fan is running at full-speed when the temperatur e reaches the minimum plus the range value. the effect of this is a temperature feedback loop, wh ich will cause the temperature to reach equilibrium between the minimum temperature and the minimum te mperature plus the range. provided that the fan has adequate cooling capacity for all environmental and power dissipation conditions, this system will maintain the temperature within acceptable limits, while allowing the fan to run slower (and quieter) when less cooling is required.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 222 smsc sch311x datasheet figure 23.5 automatic fan control 23.13.3.3 spin up when a fan is being started from a stationary state (pwm duty cycle =00h), the part will cause the fan to ?spin up? by going to 100% duty cycle for a progr ammable amount of time to overcome the inertia of the fan (i.e., to get t he fan turning). followi ng this spin up time, the fa n will go to the duty cycle computed by the auto fan algorithm. during spin-up, the pwm dut y cycle is reported as 0%. to limit the spin-up time and thereby reduce fan no ise, the part uses feedback from the tachometers to determine when each fan has started spinni ng properly. the following tachometer feedback is included into the auto fan algorithm during spin-up. auto fan operation during spin up: the pwm goes to 100% duty cycle until the tachomet er reading register is below the minimum limit (see figure 23.6 ), or the spin-up time expires, whichever comes first. this causes spin-up to continue until the tachometer enters the valid count range, unless the spin up time expires. if the spin up expires before the tachometer enters the valid range, an interrupt status bit will be set once spin-up expires. note that more than one tachometer may be associated with a pwm, in which case all tachometers associated with a pwm must be in the valid range for spin-up to end. (fan stays on w hen tem perature is below m inim um tem p.) tem p tim e tm ax = tm in + trange tm in pw m duty cycle tim e max min
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 223 revision 0.4 (06-03-05) datasheet figure 23.6 spin up reduction enabled this feature defaults to enabled; it can be disabled by clearing bit 4 of the configuration register (7fh). if disabled, the all fans go to 100% duty cycle for the duration of their associated spin up time. note that the tachometer x minimum registers must be programmed to a value less than ffffh in order for the spin up reduction to work properly. notes: the tachometer reading register always gives the actual reading of the tachometer input. no interrupt bits are set during spin-up. 23.13.3.4 hottest option if the ?hottest? option is chosen (101 or 110), then the fan is controlled by the limits and parameters associated with the zone that requires the highest pwm duty cycle value, as calculated by the auto fan algorithm. 23.13.3.5 ramp rate control logic the ramp rate control logic, if enabled, limits the amount of change in the pwm duty cycle over a specified period of time. this period of time is programmable in the ramp rate control registers located at offsets 62h and 63h. ramp rate control disabled: (default) the auto fan control logic determines the duty cycle for a particular temp erature. if pwm ramp rate control is disabled, the pwm output will be set to this calculated duty cycle. ramp rate control enabled: if pwm ramp rate control is enabled, the pwm duty cycle will ramp up or down to the new duty cycle computed by the auto fan control logic at the programm ed ramp rate. the pwm ramp rate control logic compares the current duty cycle comput ed by the auto fan logic with the previous ramp rate duty cycle. if the current duty cycle is gr eater than the previous ra mp rate duty cycle the ramp rate duty cycle is incremented by ?1? at the progra mmed ramp rate until it is greater than or equal to the current calculated duty cycle. if the current duty cycle is less than the previous ramp rate duty cycle, the ramp rate duty cycle is decremented by ?1? until it is less than or equ al to the current duty cycle. if the current pwm duty cycle is equal to t he calculated duty cycle the pwm output will remain unchanged. note : when spin up reduction is enabled (suren), the spin up time will be less than or equal to the programmed time for spin up. once the tachometer(s) associated with a pwm output are operating within the programmed limits or the spin up time expires, whichever comes first, the pwm output is reduced to the calculated duty cycle. pwm output spin up time tach reading vs. tach limit ffffh tach reading > tach limit tach reading < tach limit duty cycle = 100% duty cycle = 0% programmed spin up time
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 224 smsc sch311x datasheet internally, the pwm ramp rate control logi c will increment/decrement the internal pwm duty cycle by ?1? at a rate determined by t he ramp rate control register (see ). the actual duty cycle output is changed once per the period of the pwm output, which is determined by the frequency of the pwm output. (see figure 23.7 illustration of pwm ramp rate control on page 225 .) if the period of the pwm output is less than the step size created by the pwm ramp rate, the pwm output will hold the duty cycle constant until the ramp rate logic increments /decrements the duty cycle by ?1? again. for example, if the pw m frequency is 87.7hz (1/87.7hz = 11.4msec) and the pwm step time is 206msec, the pwm duty cycle will be held constant for a minimum of 18 periods (206/11.4 = 18.07) until the ramp logic increments/decre ments the actual pwm duty cycle by ?1?. if the period of the pwm output is greater than the step size created by the pwm ramp rate, the ramp rate logic will force the pwm output to increment/decrement th e actual duty cycle in increments larger than 1/255. for example, if the pwm frequency is 11hz (1/11hz = 90.9msec) and the pwm step time is 5msec, the pwm duty cycl e output will be increm ented 18 or 19 out of 255 (i.e., 90.9/5 = 18.18) until it reaches the calculated duty cycle. note: the step size may be less if the calculated duty cycle minus t he actual duty cycle is less than 18. note: the calculated pwm duty cycle reacts immedi ately to a change in the temperature reading value. the temperature reading value may be updated once in tbdmsec (default) (see table 23.2, ?adc conversion sequence,? on page 208 ). the internal pwm duty cycle generated by the ramp rate co ntrol logic gradually ramps up/dow n to the calculated duty cycle at a rate pre-determined by the value programmed in the pwm ramp rate control bits . the pwm output latches the internal duty cycle generated by the ramp rate control block every 1/(pwm frequency) seconds to determine the actual duty cycle of the pwm output pin. pwm output transiti on from off to on when the calculated pwm duty cycle generated by the auto fan control logic trans itions from the ?off? state to the ?on? state (i.e., current pwm duty c ycle>00h), the internal pwm duty cycle in the ramp rate control logic is in itialized to the calculated duty cycle without any ramp time and the pwmx current duty cycle register is set to this value. the pwm output will latch the current duty cycle value in the ramp rate control block to control the pwm output. pwm output transition from on to off each pwm output has a control bit to determine if the pwm output will transition immediately to the off state (default) or if it will gr adually step down to off at the prog rammed ramp rate. these control bits (szen) are located in the pwmx options registers at offsets 94h-96h. table 23.4 pwm ramp rate rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from 0% duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz) 000 35 52.53 206 msec 4.85 001 17.6 26.52 104 msec 9.62 010 11.8 17.595 69 msec 14.49 011 7.0 10.455 41 msec 24.39 100 4.4 6.63 26 msec 38.46 101 3.0 4.59 18 msec 55.56
lpc io with 8042 kbc, reset generati on, hwm and multiple serial ports datasheet smsc sch311x 225 revision 0.4 (06-03-05) datasheet figure 23.7 illustration of pwm ramp rate control notes: the pwm duty cycle latches the ramping duty cycle on the rising edge of the pwm output. the calculated duty cycle, ramping duty cycle, and the pwm output duty cycle are asynchronous to each other, but are all synchronized to the internal 90khz clock source. it should be noted t hat the actual duty cycle on the pin is created by t he pwm ramp rate control block and latched on the rising edge of the pwm ou tput. therefore, the current pwm duty cycle may lag the pwm calculated duty cycle. 110 1.6 2.55 10 msec 100 111 0.8 1.275 5 msec 200 table 23.4 pwm ramp rate (continued) rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from 0% duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz) example 1: pwm period < ramp rate step size pwm frequency = 87.7hz (11.4msec) & pwm ramp rate = 38.46hz (26msec) calculate duty cycle 70h 74h pwm duty cycle 70h 11.4ms 1 1 . 4 m s 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 71h 71h 71h 72h 72h 73h 73h 73h 74h 74h 74h example 2: pwm period > ramp rate step size pwm frequency = 11hz (90.9msec) & pwm ramp rate = 38.46hz (26msec) calculate duty cycle 70h 74h ramping duty cycle pwm duty cycle 70h 70h 71h 72h 73h 74h 26ms 26ms 2 6 m s 2 6 m s ramping duty cycle 70h 71h 72h 73h 74h 26ms 26ms 2 6 m s 2 6 m s 90.9msec 71h 74h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 226 smsc sch311x datasheet 23.13.4 operation of pwm pin following a power cycle this device has special features to control the level and operation of the pwm pin following a power cycle. these features are pwm clamping and forced spinup. 23.13.4.1 pwm clamp the pwm pin has the option to be held low for 0 seconds or 2 seconds following a vcc por. this feature is selectable by a vbat powered regist er bit in the sio runtime register block. bit[7] of the dblclick register at offset 5bh is used to select the 0 or 2 second option. this bit is defined as follows: bit[3] zero_spinup 1=zero delay for spin up 0 = delay spinup by 2 seconds (default) following pwrgd_ps being asserted the pwm pin will be held low until either the trdy signal is asserted or the delay counter expires, whichever comes first. the delay counter performs two functions when set to the 2 second delay option. 1. following a vtr por & vcc por, the bios has up to 2 seconds to program the hwm registers and enable autofan before the fans are turned on full. this is a noise reduction feature 2. following a vcc por only (return from sleep) the hardware requires 150.8 ms (default - see table 23.2 ) to load the temperature reading registers. the trdy signal is used to indicate when these values have been updated. trdy is reset to zero on a vcc por, which forces the fans to be set to ffh. if the delay counter is enabled for up to a 2 second delay, the pwms will be held low until the reading registers are valid. once the registers are updated, the hardware will initiate a forced spinup (if enabled) and enter automode. see forced spinup on page 226 . the timing diagrams in the section titled timing diagrams for pwm clamp and forced spinup operation on page 227 show the effect of the 2 second pwm hold-off counter on the pwm pin. 23.13.4.2 forced spinup spinup is a feature of the auto fan control mode. any time the pwm pin transitions from a 0% duty cycle to a non zero duty cycle the pwm pin will be forc ed high for the duration of spinup or until the fan are spinning within normal operating parameters as determined by the tach limit registers. see spin up on page 222 for a more detailed description of spinup. this feature can also be initiated by the pwrgd_ps signal transitioning high following a main (vcc) power cycle if the trdy bit is set to one before the pwm clamp is released. notes: in this device, a forced spinup will be generated the first time trdy is detected as a ?1? following the pwrgd_ps signal transitioning from low to high (if enabled). to enable this feature, set bit[3] of the pwmx configuration registers to one. these registers are located at offsets 5ch, 5dh, and 5eh. if the trdy bit is ?1? and cleared by software after being set to and then set again while the pwrgd_ps signal is high, the act of trdy being asserted will not cause a forced spinup event. the duration of the forced spin-up time is controlled by the spin[2:0] bits located in the pwm x configuration registers (5ch - 5eh). the forced spinup enable bit is located in bit[3] suenx of the pwmx configuration registers. forced spinup defaults to disabled on a vtr por. start of spin-up on main (vcc) power cycle the pwm spin-up supports the scenario where the pa rt is powered by vtr and the fans are powered by a main power rail. if the start bit is not cl eared on a main power cycle, then the pwm will remain at a level that may not start the fan when the main supply ramps up. this spinup will force each pwm into spin-up (if enabled) when the trdy bit goes active.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 227 revision 0.4 (06-03-05) datasheet start of spin-up on standby (vtr) power cycle the two second pwm clamping feature may be used to delay the fans from being turned on full until the bios has the opportunity to program the limit and configuration registers for the auto fan control mode. (see pwm clamp on page 226 ) this is a noise reduction feature. once the trdy bit goes high the clamp will be released and the fans will be forced into spinup. note: if the two second pwm clamping period expires before trdy is asserted, the pwms will be set to full on. 23.13.4.3 timing diagrams for pwm clamp and forced spinup operation figure 23.8 case 1 spinup operation pwrgd_ps pwm timer duty cycle start trdy spinup ~ ~ vcc vtr case 1: spinup operation following pwrgd_ps active after vtr por. start bit and trdy go high during 2 sec delay. 2 seconds pwm clamp spinup time
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 228 smsc sch311x datasheet figure 23.9 case 2 spinup operation pwrgd_ps ffh pwm timer start trdy spinup ~ ~ vcc vtr case 2: spinup operation following pwrgd_ps active after vtr por. start bit goes high during 2 sec delay, trdy goes high after 2 sec delay. 2 seconds pwm clamp duty cycle spinup time
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 229 revision 0.4 (06-03-05) datasheet figure 23.10 case 3 spinup operation pwrgd_ps pwm timer start trdy spi nup ~ ~ vcc vtr case 3: spi nup operati on fol l owi ng pwrgd_ps acti ve after vtr por. start bit and trdy go high after 2 sec delay. 2 seconds pwm cl amp duty cycle ffh spi nup time
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 230 smsc sch311x datasheet figure 23.11 case 4 spinup operation pwrgd_ps pwm timer start trdy spinup ~ ~ vcc vtr case 4: spinup operation following pwrgd_ps active after vtr por. start bit and trdy do not go high. 2 seconds pwm cl amp ffh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 231 revision 0.4 (06-03-05) datasheet figure 23.12 case 5 spinup operation 23.13.5 active minimum temper ature adjustment (amta) the amta operation in the sch311x consists of a ?top temperature? register (for each zone) that defines the upper bound of the operating temperatur e for the zone. if the temperature exceeds this value, the minimum temperature (low temp limit) for the zone is adjusted down. this keeps the zone operating in the lower portion of the temperature range of the fan control function (pwm duty cycle vs. temperature), thereby limiting fan noise by pr eventing the fan from going to the higher pwm duty cycles. pwrgd_ps pwm timer start trdy spinup ~ ~ vcc vtr case 5: spinup operation following pwrgd_ps active after vcc por. start bit and trdy high before 2 sec delay. 2 sec pwm clamp ~ ~ ~ ~ 2 sec this is the time to complete one monitoring cycle. duty cycle spinup time duty cycle
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 232 smsc sch311x datasheet 23.13.5.1 adjusting minimum temper ature based on top temperature this describes the option for adjusting the mini mum temperature based on the top temperature. the amta option automatically adjusts the prepr ogrammed value for the minimum temperature and shifts the temperature range for th e autofan algorithm to better suit the environ ment of the system, that is, to bias the operating range of the autofan algor ithm toward the low end of the temperature range. it uses a programmed value for the ?top temperatur e? for the zone to shift the temperature range of the autofan algorithm, and therefore the speed of the fan, toward the middle of the fan control function (pwm duty cycle vs. temperature) . this feature will effectively pr event the fans from going on full, thereby limiting the noise produced by the fans. the value of the top temperature for each zone can be programmed to be near the center of the temperature range for the zone, or near the maximum as defined by the low temp limit plus range. the implementation of the amta feature is defined as follows: this feature can be individually enabled to operate for each zone. each zone has a separate enable bit for this feature (register 0b7h). note that if the piecewise linear fan function is used, the minimum temperature for the zone (zone x low temp limit register) is shifted down, which will result in each segment being shifted down. this feature adjusts the minimum temperature for each zone for the autofan algorithm based on the current temperature reading for the zone exceeding the top temperature. when the current temperature for the zone exceeds the top temperature for the zone, the minimum temperature value is reloaded with the value of the minimum temperature limit minus a programmable temperature adjustment value for the zone, as programmed in the min temp adjust registers. the temperature adjustment value is programmable for each zone. the zone must exceed the limits set in the associated top temp zone [3:1] register for two successive monitoring cycles in order for the minimum temperature value to be adjusted (and for the associated status bit to be set). the new minimum temperature value is loaded into the low temp limit register for each zone (zone x low temp limit). this will cause the temperature range of the autofan algorithm to be biased down in temperature. note: when the minimum temperature for the zone is adjusted, the autofan algorithm will operate with a new fan control function (pwm duty cycle vs. temperature), which will result in a new pwm duty cycle value. the pwm will move to the new value smoothly, so there is little audible effect when the pwm ramp rate control is enabled. this process will repeat after a delay until the cu rrent temperature for the zone no longer exceeds the top temperature for the zone. once the minimum temp value is ad justed, it will no t adjust again until after a programmable time delay. the delay is programmed for each zone in the min temp adjust delay registers. the adjust times are as follows: 1, 2, 3, and 4 minutes. figure 8.5 illustrates the operation of the amta for one adjustment down in minimum temperature resulting from the temperature exceeding the top temperature. the effect on the linear fan control function (pwm duty cycle vs. temperature) is shown.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 233 revision 0.4 (06-03-05) datasheet figure 23.13 amta illustration, adjusting minimum temperature note: if the amta feature is not enabled for a zone, then the top temperature register for that zone is not used. interrupt generation the following figure illustrates the operation of the interrupt mapping for the amta feature in relation to the status bits and enable bits. pwm duty cycle temperature max min t min range new t min = t min ?t min adjust t op range increasing temp t min adjust initial operating range
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 234 smsc sch311x datasheet figure 23.14 amta interrupt mapping 23.14 nthermtrip the nthermtrip output pin can be configured to assert when any of the temperature sensors (remote diodes 1-2, internal) is above its associated temperature limit. the thermtrip enable register at offset ceh se lects which reading(s) will cause the nthermtrip signal to be active, when the selected temperature(s) exceed in the associated limit registers (c4h for remote diode 1, c5h for remote diode 2, and c9h for ambient temp) their pre-programmed limit. an internal version of th is output will also be used by the resgen block to generate a system reset pulse. more details can be found in chapter 18, "reset generation," on page 181 . 23.14.1 nthermtrip operation the nthermtrip pin can be configured to assert when one of the temperature zones is above its associated nthermtrip temperature limit (thermtrip temp limit zone[3:1]). the thermtrip temperature limit is a separate limit register from the high limit used for setting the interrupt status bits for each zone. the thermtrip limit zone[3:1] registers represent the upper temperature limit for asserting nthermtrip for each zone. these registers are defined as follows: if the monitored temperature for the zone exceeds the value set in the associ ated thermtrip temp limit zone[3:1], the corresponding bit in the thermtrip status register will be set. the nthermtrip pin may or may not be set depending on the state of the associated enable bits (in the therm output enable register). each zone may be individually enabled to assert the nthermtrip pin (as an output). the zone must exceed the limits set in the associated thermtrip temp limit zone [3:1] register for two successive monitoring cycles in order for the nthermtrip pin to go active (and for the associated st atus bit to be set). the following figures summarize the thermtrip operation in relation to the thermtrip status bits. top temp exceeded status reg o r to int pin (and'd with inten bit) top_int_en (tmin adjust enable reg [0]) tmin_adj_en1 (tmin adjust enable [1]) tmin_adj_en2 (tmin adjust enable [2]) tmin_adj_en3 (tmin adjust enable [3]) to zone 1-3 low temp limit adjust logic zone 3 (tte status [2]) zone 1 (tte status [0]) zone 2 (tte status [1]) zone 3 top limit exceeded zone 2 top limit exceeded zone 1 top limit exceeded top_temp_event
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 235 revision 0.4 (06-03-05) datasheet figure 23.15 nthermtrip output operation 23.14.2 fan speed monitoring the chip monitors the speed of th e fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. the fan tachometer in puts are monitored by using the fan tachometer registers. these signals, as well as the f an tachometer registers, are described below. the tachometers will operate in one of two modes: mode 1: standard tachometer reading mode. this mode is used when the fan is always powered when the duty cycle is greater than 00h. mode 2: enhanced tachometer reading mode. this mode is used when the pwm is pulsing the fan. 23.14.2.1 tach inputs the tachometer inputs are implemented as digital input buffers with logic to filter out small glitches on the tach signal. 23.14.2.2 selecting the mode of operation: the mode is selected through the mode select bits located in the tach option register. this mode select bit is defined as follows: 0=mode 1: standard tachometer reading mode 1=mode 2: enhanced tachometer reading mode. default mode of operation: mode 1 slow interrupt disabled (don't force fffeh) tach interrupt enabled via enable bit tach limit = ffffh tach readings updated once a second 23.14.2.3 mode 1 ? always monitoring mode 1 is the simple case. in this mode, the fan is always powered when it is ?on? and the fan tachometer output always has a valid output. this mode is typically used if a linear dc voltage control circuit drives the fan. in this mode, the fan tachometer simply counts the number of 90khz pulses between the programmed number of edges (def ault = 5 edges). the fan tachometer reading registers are continuously updated. thermtrip status reg zone 3 thermtrip limit exceeded zone 2 thermtrip limit exceeded zone 1 thermtrip limit exceeded or zone 3 out_en (thermtrip output enable [2]) zone 1 out_en (thermtrip output enable [0]) zone 2 out_en (thermtrip output enable [1]) to nthermtrip pin thermtrip_ctrl (thermtrip control [0])
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 236 smsc sch311x datasheet the counter is used to determine the period of th e fan tachometer input pulse. the counter starts counting on the first edge and continues counting until it detects the last edge or until it reaches ffffh. if the programmed number of edges is detected on or before the counter reaches ffffh, the reading register is updated with that count value. if th e counter reaches ffffh and no edges were detected a stalled fan event has occurred and the tach reading register will be set to ffffh. if one or more edges are detected, but less than the programmed number of edges, a slow fan event has occurred and the tach reading register will be set to either fffeh or ffffh d epending on the state of the slow tach bits located in the tachx options registers at offsets 90h - 93h. software can easily compute the rpm value using the tachometer reading value if it knows the number of edges per revolution. notes: if the pwm output associated with a tach input is configured for the high frequency option then the tach input must be configured for mode 1. some enhanced features added to support mode 2, are available to mode 1 also. they are: programmable number of tach edges and force tach reading register to fffeh to indicate a slow fan. five edges or two tach pulses are generated per revolution. if a tach input is left unconnected it must be configured for mode 1. 23.14.2.4mode 2 ? monitor ta ch input when pwm is ?on? in this mode, the pwm is used to pulse the fan motor of a 3-wire fan. 3-wire fans use the same power supply to drive the fan motor and to drive th e tachometer output logic. when the pwm is ?on? the fan generates valid tach pulses. when the pwm is not driving the fan, the tachometer signal is not generated and the tach signal becomes indetermi nate or tristate. therefore, mode 2 only makes tachometer measurements when th e associated pwm is driving high during an upda te cycle. as a result, the fan tachometer measurement is ?synchroni zed? to the pwm output, such that it only looks for tach pulses when the pwm is ?on?. note: any fan tachometer input may be associated with any pwm output (see linking fan tachometers to pwms on page 241 .) during an update cycle, if an insuff icient number of tac hometer pulses are detected during this time period, the following applies: if at least one edge but less than the programmed number of edges is detected, the fan is considered slow. if no e dge is detected, the fan is considered stopped. notes: the interrupt status bits are set, if enabled, to indicate that a slow or stopped fan event has occurred when the tach reading registers ar e greater than the tach limit registers. at some duty cycles, the programmed number of edges will appear during some pwm high times, but not all. if opportunistic mode is enabled, the tach logic will latch the count value any time it detects the programmed number of edges and reset the update counter. (see bit[5] of pme_sts1.) an interrupt will only be generated if no vali d readings were made during the programmed update time. assumptions (refer to figure 4 - pwm and tachometer concept): the tachometer pulse generates 5 transitions per f an revolution (i.e., two fan tachometer periods per revolution, edges 2 6). one half of a revolution (one tachometer period) is equivalent to three edges (2 4 or 3 5). one quarter of a revolution (one-half tach ometer period) is equivalent to two edges. to obtain the fan speed, count the number of 90khz pulses that occurs between 2 edges i.e., 2 3, between 3 edges i.e., 2 4, or between 5 edges, i.e. 2 6 (the case of 9 edges is not shown). the time from 1-2 occurs through the guard time and is not to be used. for the discussion below, an edge is a high-to-low or low-to-high transition (edges are numbered ? refer to figure 4 - pwm and tachometer concept
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 237 revision 0.4 (06-03-05) datasheet the tachometer circuit begins monitoring the tach when the associated pwm output transitions high and the guard time has expired. each tach circuit will continue monitoring until either the ?on? time ends or the programmed number of edges has been detected, whichever comes first. the fan tachometer value may be updated every 300ms, 500ms, or 1000ms. figure 23.16 pwm and tachometer concept fan tachometer options for mode 2 2, 3, 5 or 9 ?edges? to calculate the fan speed (figure 4) guard time a is programmable (8-63 clocks) to account for delays in the system (figure 4) suggested pwm frequencies for mode 2 are: 11.0 hz, 14.6 hz, 21.9 hz, 29.3 hz, 35.2 hz, 44.0 hz, 58.6 hz, 87.7hz option to ignore first 3 tachometer edges after guard time option to force tach reading register to fffeh to indicate a slow fan. 23.14.2.5 fan tachometer reading registers: the tachometer reading registers are 16 bits, uns igned. when one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. the order is lsb first, msb second. the value ffffh indicate s that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter ov erflow). these registers are read only ? a write to these registers has no effect. notes: the fan tachometer reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional. ffffh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). the tachometer registers are read only ? a write to these registers has no effect. internal pwm signal window for valid tach pulses guard time a tach pulses tach pulses 2 3 4 5 1 6 bd f a ce pwm ?on?
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 238 smsc sch311x datasheet mode 1 should be enabled and the tachometer limit register should be set to ffffh if a tachometer input is left unconnected. 23.14.2.6 programming options for each tachometer input the features defined in this section are programmable via the tachx option registers located at offsets 90h-92h and the pwmx option registers located at offsets 94h-96h. tach reading update time in mode 1, the fan tachometer reading regist ers are continuously updated. in mode 2, the fan tachometer registers are updat ed every 300ms, 500msec, or 1000ms ec. this option is programmed via bits[1:0] in the pwmx option register. the pw m associated with a particular tach(s) determines the tach update time. programmed number of tach edges in modes 1 & 2, the number of edges is programmable for 2, 3, 5 or 9 edges (i.e., ? tachometer pulse, 1 tachometer pulse, 2 tachometer pulses, 4 tachomet er pulses). this option is programmed via bits[2:1] in the tachx option register. note: the ?5 edges? case corresponds to two tachometer pulses, or 1 rpm for most fans. using the other edge options will require software to scale the values in the reading register to correspond to the count for 1 rpm. guard time (mode 2 only) the guard time is programmable from 8 to 63 clocks (90khz). this option is programmed via bits[4:3] in the tachx option register. ignore first 3 tachometer edges (mode 2 only) option to ignore first 3 tachometer edges after guard time. this option is programmed for each tachometer via bits[2:0] in the tachx option regist er. default is do not ignore first 3 tachometer edges after guard time. 23.14.2.7 summary of operation for modes 1 & 2 the following summarizes the detection cases: no edge occurs during the pwm ?on? time: indicate this condition as a stalled fan ? the tachometer reading register contains ffffh. one edge (or less than programmed number of edges) occurs during the pwm ?on? time: indicate this condition as a slow fan. ? if the slow bit is enabled, the tachometer reading register will be set to fffeh to indicate that this is a slow fan instead of a seized fan. note: this operation also pertains to the case where the tachometer counter reaches ffffh before the programmed number of edges occurs. ? if the slow bit is disabled, the tachometer reading register will be set to ffffh. in this case, no distinction is made between a slow or seized fan. note: the slow interrupt enable feature (slow) is configured in the tachx options registers at offsets 90h to 93h. the programmed number of edges occurs: -mode 1: if the programmed number of edges occurs before the counter reaches ffffh latch the tachometer count -mode 2: if the programmed number of edges occurs during the pwm ?on? time: latch the tachometer count (see note below).
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 239 revision 0.4 (06-03-05) datasheet notes: whenever the programmed number of edges is detected, the edge detection ends and the state machine is reset. the tachometer reading register is updated with the tachometer count value at this time. see detection of a stalled fan on page 240 for the exception to this behavior. in the case where the programmed number of edges occurs during the ?on?, the tachometer value is latched when the last required edge is detected. 23.14.2.8 examples of minimum rpms supported the following tables show minimum rpms that can be supported with the different parameters. the first table uses 3 edges and the second table uses 2 edges. note 23.1 100% duty cycle is 255/256 note 23.2 rpm=60/t revolution , t ta c h p u l s e = t revolution /2. using 3 edges for detection, t ta c h p u l s e = (pwm ?on? time ? guard time). minimum rpm values shown use minimum guard time (88.88usec). table 23.5 minimum rpm detectable using 3 edges pwm frequency pulse width at duty cycle (pwm ?on? time) minimum rpm at duty cycle (note 23.2) (30/t tachpulse ) (hz) 25% (msec) 50% (msec) 100% (msec) (note 23.1) 25% 50% 100% 87.7 2.85 5.7 11.36 10865 5347 2662 58.6 4.27 8.53 17 7175 3554 1774 44 5.68 11.36 22.64 5366 2662 1330 35.2 7.1 14.2 28.3 4279 2126 1063 29.3 8.53 17.06 34 3554 1768 885 21.9 11.42 22.83 45.48 2648 1319 661 14.6 17.12 34.25 68.23 1761 878 440 11 22.73 45.45 90.55 1325 661 332 table 23.6 minimum rpm detectable using 2 edges pwm frequency pulse width at duty cycle (pwm ?on? time) minimum rpm at duty cycle (note 23.4) (30/t tachpulse ) (hz) 25% (msec) 50% (msec) 100% (msec) (note 23.3) 25% 50% 100% 87.7 2.85 5.7 11.36 5433 2673 1331 58.6 4.27 8.53 17 3588 1777 887 44 5.68 11.36 22.64 2683 1331 665 35.2 7.1 14.2 28.3 2139 1063 532 29.3 8.53 17.06 34 1777 884 442
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 240 smsc sch311x datasheet note 23.3 100% duty cycle is 255/256 note 23.4 rpm=60/t revolution , t ta c h p u l s e = t revolution /2. using 2 edges for detection, t ta c h p u l s e = 2*(pwm ?on? time-guard time). minimum rpm values shown use minimum guard time (88.88usec). 23.14.2.9 detection of a stalled fan there is a fan failure bit (tachx) in the interrupt status register used to indicate that a slow or stalled fan event has occurred. if the tach reading value exceeds the value programmed in the tach limit register the interrupt status bit is set. see interrupt status register 2 at offset 42h. notes: the reading register will be forced to ffffh if a stalled event occurs (i.e., stalled event =no edges detected.) the reading register will be forced to either ffffh or fffeh if a slow fan event occurs. (i.e., slow event: 0 < #edges < programmed #edges). if the control bit, slow, located in the tachx options registers at offsets 90h - 93h, is set then fffeh will be forced into the corresponding tach reading register to indicate that the fan is spinning slowly. the fan tachometer reading register stays at ffffh in the event of a stalled fan. if the fan begins to spin again, the tachometer logic will reset and latch the next valid reading into the tachometer reading register. 23.14.2.10 fan interrupt status bits the status bits for the fan events are in interrupt status register 2 (42h). these bits are set when the reading register is above the tachometer minimum and the interrupt enable 2 (fan tachs) register bits are configured to enable fan tach events. no interrupt status bits are set for fan events (even if the fan is stalled) if the associated tachometer minimum is set to ffffh (registers 54h-5bh). note: the interrupt enable 2 (fan tachs) register at offset 80h defaults to enabled for the individual tachometer status events bits. the group fan tach nhwm_int bit defaults to disabled. this bit needs to be set if fan tach interrupts are to be generated on the external nhwm_int pin. see figure 23.3 interrupt control on page 211 . 23.14.3 locked rotor support for tachometer inputs all tachometer inputs support locked rotor input mode. in this mode, the tachometer input pin is not used as a tachometer signal, but as a level signal. t he active state of this signal (high or low) is the state that the fan?s locked rotor signal indicates the locked condition. the locked rotor signals that are supported are active high level and active low level. they are selectable for each tachometer. if the pin goes to its programmed active state, the associated interrupt 21.9 11.42 22.83 45.48 1324 660 330 14.6 17.12 34.25 68.23 881 439 220 11 22.73 45.45 90.55 663 331 166 table 23.6 minimum rpm detectable using 2 edges (continued) pwm frequency pulse width at duty cycle (pwm ?on? time) minimum rpm at duty cycle (note 23.4) (30/t tachpulse ) (hz) 25% (msec) 50% (msec) 100% (msec) (note 23.3) 25% 50% 100%
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 241 revision 0.4 (06-03-05) datasheet status bit will be set. in addition, if properly configured, the nhwm_int pin can be made to go active when the status bit is set. the locked rotor input option is configured through the following bits: tach1 mode, bits[7:6] of tach 1-3 mode register. tach2 mode, bits[5:4]of tach 1-3 mode register. tach3 mode, bit[3:2] of tach 1-3 mode register. these bits are defined as follows: 00=normal operation (default) 01=locked rotor mode, active high signal 10=locked rotor mode, active low signal 11=undefined. 23.14.4 linking fan ta chometers to pwms the tach/pwm association register at offset 81h is used to associate a tachometer input with a pwm output. this association has three purposes: 1. the auto fan control logic supports a feature called spinup reduction. if spinup reduction is enabled (suren bit), the auto fan control logic will stop driving the pwm output high if the associated tach input is operating within normal parameters. (note: suren bit is located in the configuration register at offset 7fh) 2. to measure the tachometer input in mode 2, the tachometer logic must know when the associated pwm is ?on?. 3. inhibit fan tachometer interrupts when the associated pwm is ?off?. see the description of the pwm_tach register. the default configuration is: pwm1 -> fantach1. pwm2 -> fantach2. pwm3 -> fantach3. note: if a fantach is associated with a pwm operating in high frequency mode (see the zonex range/fanx frequency registers (5fh-61h)) the tach monitoring logic must be configured for mode 1 (see bit[3] mode in fantachx option registers, 90h-92h). 23.15 high frequency pwm options note: if a fan with a tachometer output is driven by the high frequency pwm option, the tachometer must be monitored in mode 1 only. 23.15.1 pwm frequencies supported the sch311x supports low frequency and high frequency pwms. the low frequency options are 11.0hz, 14.6hz, 21.9hz, 29.3hz, 35.2hz, 44.0hz, 58.6hz and 87.7hz. the high frequency options are 15khz, 20khz, 25khz and 30khz. all pwm frequencies are derived from the 14.318mhz clock input. the frequency of the pwm output is determined by the frequency select bits[3:0] as shown in pme_sts1. the default pwm frequency is 25khz.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 242 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 243 revision 0.4 (06-03-05) datasheet chapter 24 hardware monitoring register set these registers are accessed through an index and data register scheme using the hw_reg_index and hw_reg_data registers located in the runtime register block at offset 70h and 71h from the address programmed in logical device a. the hardware monitor block registers are located at the indexed address shown in table 24.1, "register summary" . definition for the lock column: yes = register is made read-only when the lock bit is set; no = register is not made read-only when the lock bit is set. table 24.1 register summary reg addr read/ write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock 10h r/w smsc test register 7 6 5 4 3 2 1 0 00h no 1dh r reserved n/a res res res res res res res res 00h 1eh r reserved n/a res res res res res res res res 00h 1fh r reserved n/a res res res res res res res res 00h 20h r +2.5v 7 6 5 4 3 2 1 0 00h no 21h r +1.5v reading from vccp pin 7 6 5 4 3 2 1 0 00h no 22h r vcc 7 6 5 4 3 2 1 0 00h no 23h r 5v 7 6 5 4 3 2 1 0 00h no 24h r 12v 7 6 5 4 3 2 1 0 00h no 25h r remote diode 1 (zone 1) temp reading 7 6 5 4 3 2 1 0 00h no 26h r internal temp (zone 2) reading 7 6 5 4 3 2 1 0 00h no 27h r remote diode 2 (zone 3) temp reading 7 6 5 4 3 2 1 0 00h no 28h r fantach1 lsb 7 6 5 4 3 2 1 0 ffh note 24.8 no 29h r fantach1 msb 15 14 13 12 11 10 9 8 ffh note 24.8 no 2ah r fantach2 lsb 7 6 5 4 3 2 1 0 ffh note 24.8 no 2bh r fantach2 msb 15 14 13 12 11 10 9 8 ffh note 24.8 no 2ch r fantach3 lsb 7 6 5 4 3 2 1 0 ffh note 24.8 no 2dh r fantach3 msb 15 14 13 12 11 10 9 8 ffh note 24.8 no 2eh r reserved res res res res res res res res 00h no 2fh r reserved res res res res res res res res 00h no 30h r/w note 2 4.1 pwm1 current duty cycle 7 6 5 4 3 2 1 0 n/a note 24.1 0 00 ye s note 24 .1 31h r/w note 2 4.1 pwm2 current duty cycle 7 6 5 4 3 2 1 0 n/a note 24.1 0 00 ye s note 24 .1 32h r/w note 2 4.1 pwm3 current duty cycle 7 6 5 4 3 2 1 0 n/a note 24.1 0 00 ye s 33-3ch r reserved res res res res res res res res 00h no 3dh r device id 7 6 5 4 3 2 1 0 8ch no 3eh r company id 7 6 5 4 3 2 1 0 5ch no 3fh r revision 7 6 5 4 3 2 1 0 01h no 40h r/w note 2 4.2 ready/lock/start res res res vbat mon ovrid ready lock note 24. 9 start 04h ye s note 24 .2 41h r/wc note 2 4.3 interrupt status register 1 int23 d2 amb d1 5v vcc vccp 2.5v 00h note 24.8 no
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 244 smsc sch311x datasheet 42h r/wc note 2 4.3 interrupt status register 2 err2 err1 res fanta ch3 fanta ch2 fanta ch1 res 12v 00h no 43h r reserved res res res res res res res res 00h no 44h r 2.5v low limit 7 6 5 4 3 2 1 0 00h n/a 45h r 2.5v high limit 7 6 5 4 3 2 1 0 ffh n/a 46h r vccp low limit 7 6 5 4 3 2 1 0 00h n/a 47h r vccp high limit 7 6 5 4 3 2 1 0 ffh n/a 48h r vcc low limit 7 6 5 4 3 2 1 0 00h n/a 49h r vcc high limit 7 6 5 4 3 2 1 0 ffh n/a 4ah r 5v low limit 7 6 5 4 3 2 1 0 00h n/a 4bh r 5v high limit 7 6 5 4 3 2 1 0 ffh n/a 4ch r 12v low limit 7 6 5 4 3 2 1 0 00h n/a 4dh r 12v high limit 7 6 5 4 3 2 1 0 ffh n/a 4eh r/w remote diode 1 low temp 7 6 5 4 3 2 1 0 81h no 4fh r/w remote diode 1 high temp 7 6 5 4 3 2 1 0 7fh no 50h r/w internal diode low temp 7 6 5 4 3 2 1 0 81h no 51h r/w internal diode high temp 7 6 5 4 3 2 1 0 7fh no 52h r/w remote diode 2 low temp 7 6 5 4 3 2 1 0 81h no 53h r/w remote diode 2 high temp 7 6 5 4 3 2 1 0 7fh no 54h r/w fantach1 minimum lsb 7 6 5 4 3 2 1 0 ffh no 55h r/w fantach1 minimum msb 15 14 13 12 11 10 9 8 ffh no 56h r/w fantach2 minimum lsb 7 6 5 4 3 2 1 0 ffh no 57h r/w fantach2 minimum msb 15 14 13 12 11 10 9 8 ffh no 58h r/w fantach3 minimum lsb 7 6 5 4 3 2 1 0 ffh no 59h r/w fantach3 minimum msb 15 14 13 12 11 10 9 8 ffh no 5ah r reserved res res res res res res res res 00h no 5bh r reserved res res res res res res res res 00h no 5ch r/w pwm 1 configuration zon2 zon1 zon0 inv suen1 spin2 spin1 spin0 62h ye s 5dh r/w pwm 2 configuration zon2 zon1 zon0 inv suen2 spin2 spin1 spin0 62h ye s 5eh r/w pwm 3 configuration zon2 zon1 zon0 inv suen3 spin2 spin1 spin0 62h ye s 5fh r/w zone 1 range/pwm 1 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 cbh ye s 60h r/w zone 2 range/pwm 2 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 cbh ye s 61h r/w zone 3 range/pwm 3 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 cbh ye s 62h r/w pwm1 ramp rate control res1 note 2 4.7 res1 note 2 4.7 res1 note 2 4.7 res rr1e rr1-2 rr1-1 rr1-0 00h ye s 63h r/w pwm 2, pwm3 ramp rate control rr2e rr2-2 rr2-1 rr2-0 rr3e rr3-2 rr3-1 rr3-0 00h ye s 64h r/w pwm 1 minimum duty cycle 7 6 5 4 3 2 1 0 80h ye s 65h r/w pwm 2 minimum duty cycle 7 6 5 4 3 2 1 0 80h ye s 66h r/w pwm 3 minimum duty cycle 7 6 5 4 3 2 1 0 80h ye s 67h r/w zone 1 (remote diode 1) low temp limit 7 6 5 4 3 2 1 0 80h note 24.8 ye s 68h r/w zone 2 (ambient) low temp limit 7 6 5 4 3 2 1 0 80h note 24.8 ye s 69h r/w zone 3 (remote diode 2) low temp limit 7 6 5 4 3 2 1 0 80h note 24.8 ye s 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64h ye s 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64h ye s 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64h ye s 6dh r reserved res res res res res res res res 00h no 6eh r smsc test register 7 6 5 4 3 2 1 0 44h no 6fh r smsc test register 7 6 5 4 res res res res 40h no 70h r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 n/a no 71h r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 n/a no 72h r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 n/a no table 24.1 register summary (continued) reg addr read/ write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 245 revision 0.4 (06-03-05) datasheet 73h r smsc test register res res res res tst3 tst2 tst1 tst0 09h no 74h r/w smsc test register res res res res tst3 tst2 tst1 tst0 09h ye s 75h r smsc test register res res res res tst3 tst2 tst1 tst0 09h no 76h r/w smsc test register res res res res tst3 tst2 tst1 tst0 09h ye s 77h r smsc test register res res res res tst3 tst2 tst1 tst0 09h no 78h r/w smsc test register res res res res tst3 tst2 tst1 tst0 09h ye s 79h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h ye s 7ah r reserved res res res res res res res res 00h no 7bh r reserved res res res res res res res res 00h no 7ch r/w note 2 4.4 special function register avg2 avg1 avg0 smsc note 24. 6 smsc note 24. 6 inten mon- md res 40h ye s note 24 .4 7dh r reserved res res res res res res res res 00h no 7eh r/w interrupt enable voltages vcc 12v 5v vtr vccp 2.5v vbat volt ech ye s 7fh r/w configuration init smsc note 24. 6 smsc note 24. 6 suren trdy note 24. 9 mon _dn res res 14h ye s com- plete monitor cycle 80h r/w interrupt enable (fan tachs) res res res res fanta ch3 fanta ch2 fanta ch1 fan- tach 0eh ye s 81h r/w tach_pwm association res res t3h t3l t2h t2l t1h t1l 24h ye s 82h r/w interrupt enable (temp) res res res res d2en d1en amb temp 0eh ye s 83h rwc interrupt status register 3 res res res res res res vbat vtr 00h no 84h r a/d converter lsbs reg 5 vtr.3 vtr.2 vtr.1 vtr.0 vbat.3 vbat.2 vbat.1 vbat.0 00h no 85h r a/d converter lsbs reg 1 rd2.3 rd2.2 rd2.1 rd2.0 rd1.3 rd1.2 rd1.1 rd1.0 00h no 86h r a/d converter lsbs reg 2 v12.3 v12.2 v12.1 v12.0 am.3 am.2 am.1 am.0 00h no 87h r a/d converter lsbs reg 3 v50.3 v50.2 v50.1 v50.0 v25.3 v25.2 v25.1 v25.0 00h no 88h r a/d converter lsbs reg 4 vcc.3 vcc.2 vcc.1 vcc.0 vcp.3 vcp.2 vcp.1 vcp.0 00h no 89h r reserved res res res res res res res res 00h no 8ah r smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh no 8bh r/w smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh ye s 8ch r smsc test register res res res tst4 tst3 tst2 tst1 tst0 09h no 8dh r/w smsc test register res res res tst4 tst3 tst2 tst1 tst0 09h ye s 8eh r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 n/a no 8fh r reserved res res res res res res res res 00h no 90h r/w fantach1 option smsc smsc smsc 3edg mode edg1 edg0 slow 04h no 91h r/w fantach2 option smsc smsc smsc 3edg mode edg1 edg0 slow 04h no 92h r/w fantach3 option smsc smsc smsc 3edg mode edg1 edg0 slow 04h no 93h r reserved res res res res res res res res 00h no 94h r/w pwm1 option res note 24. 5 res note 24. 5 opp grd1 grd0 szen updt1 updt0 0ch no 95h r/w pwm2 option res note 24. 5 res note 24. 5 opp grd1 grd0 szen updt1 updt0 0ch no 96h r/w pwm3 option res note 24. 5 res note 24. 5 opp grd1 grd0 szen updt1 updt0 0ch no 97h r/w smsc test register tst7 tst 6 tst 5 tst 4 tst3 tst2 tst1 tst0 5ah yes 98h r smsc test register tst7 tst 6 tst 5 tst 4 tst3 tst2 tst1 tst0 f1h yes 99h r vtr reading 7 6 5 4 3 2 1 0 00h no 9ah r vbat reading 7 6 5 4 3 2 1 0 00h no 9bh r vtr limit low 7 6 5 4 3 2 1 0 00h no 9ch r/w vtr limit hi 7 6 5 4 3 2 1 0 ffh no 9dh r/w vbat limit low 00h no 9eh r/w vbat limit hi 7 6 5 4 3 2 1 0 ffh no 9fh r reserved res res res res res res res res 00h no a0h r reserved res res res res res res res res 00h no a1h r reserved res res res res res res res res 00h no table 24.1 register summary (continued) reg addr read/ write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 246 smsc sch311x datasheet a2h r reserved res res res res res res res res 00h no a3h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h n/a ye s a4h r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 02h no a5h r/wc interrupt status 1 secondary int23 d2 amb d1 5v vcc vccp 2.5v 00h note 24.8 no a6h r/wc interrupt status 2 secondary err2 err1 res fanta ch3 fanta ch2 fanta ch1 res 12v 00h note 24.8 no a7h rwc interrupt status 3 secondary ins3 res res res res res res vbat vtr 00h no a8h r reserved res res res res res res res res 00h no a9h r/w smsc test register 7654321000hyes aah r/w smsc test register 7654321000hyes abh r/w tach 1-3 mode t1m1 t1m0 t2m1 t2m0 t3m1 t3m0 res res 00h no ach r reserved res res res res res res res res 00h no adh r smsc test register 76543210 00h no aeh r/w top temperature remote diode 1 (zone 1) 765432102dh note 24.8 ye s afh r/w top temperature remote diode 2 (zone 3) 765432102dh note 24.8 ye s b0h r smsc test register res res res res res res res res 00h no b1h r smsc test register res res res res res res res res 00h no b2h r smsc test register res res res res res res res res 00h no b3h r/w top temperature ambient (zone 2) 765432102dh note 24.8 ye s b4h r/w min temp adjust temp rd1, rd2 r1atp1 r1atp0 r2atp1 r2atp0 res res res res 00h yes b5h r/w min temp adjust temp and delay amb res res amatp 1 amatp 0 res res amad1 amad0 00h yes b6h r/w min temp adjust delay 1-2 r1ad1 r1ad0 r2ad1 r2ad0 res res res res 00h yes b7h r/w tmin adjust enable res res res res tmin_ adj_ en2 tmin_ adj_ en1 tmin_ adj_ ena top_ int_ en 00h yes b8h r/wc top temp exceeded status res res res res res sts2 sts1 stsa 00h note 24.8 no b9h r reserved res res res res res res res res 00h no bah r/w smsc reserved res res res res res res res res 04h ye s bbh r smsc reserved 7 6 5 4 3 2 1 0 00h no bch r reserved res res res res res res res res 00h no bdh r smsc reserved 7 6 5 4 3 2 1 0 00h no beh r reserved res res res res res res res res 00h no bfh r/w smsc reserved res res res res res res res res 00h yes c0h r/w smsc reserved res res res res res res res res 00h ye s c1h r/w thermtrip control res res res res res res res therm trip_c trl 01h ye s c2h r reserved res res res res res res res res 00h no c3h r reserved res res res res res res res res 00h no c4h r/w thermtrip temp limit rd1 (zone 1) 765432107fhyes c5h r/w thermtrip temp limit rd2 (zone 3) 765432107fhyes c6h r reserved res res res res res res res res 00h no c7h r reserved res res res res res res res res 00h no c8h r reserved res res res res res res res res 00h no c9h r/w thermtrip temp limit amb (zone 2) 765432107fhyes cah r/wc thermtrip status res res res res res rd 2 rd 1 amb 00h note 24.8 no cbh r/w thermtrip output enable res res res res res rd 2 rd 1 amb 00h yes cch r reserved res res res res res res res res 00h no cdh r reserved res res res res res res res res 00h no table 24.1 register summary (continued) reg addr read/ write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 247 revision 0.4 (06-03-05) datasheet note: smsc test registers may be read/write registers. writing these registers can cause unwanted results. note 24.1 the pwmx current duty cycle registers are only writable when the associated fan is in manual mode. in this case, the register is writable when the start bit is set, but not when the lock bit is set. note 24.2 the lock and start bits in the ready/lock/start register are locked by the lock bit. the ovrid bit is always writable when the lock bit is set. note 24.3 the interrupt status register bits are clear ed on a write of 1 if the corresponding event is not active. note 24.4 the inten bit in register 7ch is always writable, both when the start bit is set and when the lock bit is set. note 24.5 these reserved bits are read/write bits. writing these bits to a ?1? has no effect on the hardware. note 24.6 smsc bits may be read/write bits. writing these bits to a value other than the default value may cause unwanted results note 24.7 res1 bits are defined as reads return 1, writes are ignored. note 24.8 this register is reset to its default value when the pwrgd_ps signal transitions high. note 24.9 this bit is reset to its default value when the pwrgd_ps signal transitions high. note 24.10 this register always reflects the state of the pin, unless it is in spinup. during spinup this register is forced to 00h. ceh r/w smsc reserved res res res res res res res res 00h yes cf- d0h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h no d1h r/w pwm1 max 76543210ffhyes d2h- d5h r reserved res res res res res res res res 00h no d6h r/w pwm2 max 76543210ffhyes d7h- dah r reserved res res res res res res res res 00h no dbh r/w pwm3 max 76543210ffhyes dch- dfh r reserved res res res res res res res res 00h no e0h r/w enable lsbs for autofan res res pwm3_ n1 pwm3_ n0 pwm2_ n1 pwm2_ n0 pwm1_ n1 pwm1_ n0 00h no e1- e8h r reserved res res res res res res res res 00h no e9h r/w smsc reserved 7 6 5 4 3 2 1 0 00h ye s eah r smsc reserved 7 6 5 4 3 2 1 0 00h no ebh r smsc reserved 7 6 5 4 3 2 1 0 00h no ech r/w smsc reserved 7 6 5 4 3 2 1 0 00h ye s edh r/w smsc reserved 7 6 5 4 3 2 1 0 00h ye s eeh r/w smsc reserved res res res res res res res res 00h ye s ffh r smsc test register tst7 tst 6 tst 5 tst 4 tst3 tst2 tst1 tst0 n/a no table 24.1 register summary (continued) reg addr read/ write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 248 smsc sch311x datasheet 24.1 undefined registers the registers shown in the table above are the defined registers in the part. any reads to undefined registers always return 00h. writes to undefined registers have no effect and do not return an error. 24.2 defined registers 24.2.1 register 10h: smsc test register setting the lock bit has no effect on this registers this register must not be written. writing this register may produce unexpected results. 24.2.2 registers 20-24h, 99-9ah: voltage reading the voltage reading registers reflect the current voltage of the voltage monitoring inputs. voltages are presented in the registers at ? full scale for the nominal voltage, meaning that at nominal voltage, each register will read c0h, except for the vbat input. vbat is nominally a 3.0v input that is implemented on a +3.3v (nominal) analog input. therefore, the nominal reading for vbat is aeh. note: vbat will only be monitored when the vbat monitoring enable bit is set to ?1?. updating the vbat register automatically clears the vbat monitoring enable bit. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 10h r/w smsc test tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 20h r 2.5v reading 7 6 5 4 3 2 1 0 n/a 21h r vccp reading 7 6 5 4 3 2 1 0 n/a 22h r vcc reading 7 6 5 4 3 2 1 0 n/a 23h r +5v reading 7 6 5 4 3 2 1 0 n/a 24h r +12v reading 7 6 5 4 3 2 1 0 n/a 99h r vtr reading 7 6 5 4 3 2 1 0 n/a 9ah r vbat reading 7 6 5 4 3 2 1 0 n/a
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 249 revision 0.4 (06-03-05) datasheet note 24.11 vbat is a nominal 3.0v input source that has been implemented on a 3.3v analog voltage monitoring input. the voltage reading registers will be updated automatically by the device with a minimum frequency of 4hz if the average bits located in the special function register at offset 7ch are set to 001. these registers are read only ? a write to these registers has no effect. 24.2.3 registers 25-27h: temperature reading the temperature reading registers reflect the current temperatures of the internal and remote diodes. remote diode 1 temp reading register reports the temperature measured by the remote1- and remote1+ pins, remote diode 2 temp reading register reports the temperature measured by the remote2- and remote2+ pins, and the internal diod e temp reading register reports the temperature measured by the internal (ambient) temperature sensor. current temperatures are represented as 12 bit, 2?s complement, signed numbers in celsius. th e 8msbs are accessible in the temperature reading registers. table 24.3 shows the conversion for the 8-bit reading value shown in these registers. the extended precision bits for these readings are acce ssible in the a/d converter lsbs register (85h- 86h). the temperature reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or are not functi oning properly (this corresponds to the diode fault interrupt status bits). the temperature reading registers will be updated automatically by the sch311x chip with a minimum frequency of 4hz. note: these registers are read only ? a write to these registers has no effect. each of the temperature reading registers are mapped to a zone. each pwm may be programmed to operate in the auto fan control operating mode by associating a pwm with one or more zones. the following is a list of the zone associations. zone 1 is controlled by remote diode 1 temp reading zone 2 is controlled by internal temp reading (ambient temperature sensor) zone 3 is controlled by remote diode 2 temp reading table 24.2 voltage vs. register reading input nominal voltage register reading at nominal voltage maximum voltage register reading at maximum voltage minimum voltage register reading at minimum voltage vtr 3.3v c0h 4.38v ffh 0v 00h vbat ( note 24.11 ) 3.0v aeh 4.38v ffh 0v 00h 5.0v 5.0v c0h 6.64v ffh 0v 00h vccp 1.5v c0h 2.00v ffh 0v 00h vcc 3.3v c0h 4.38v ffh 0v 00h 2.5v 2.5v c0h 6.64v ffh 0v 00h 12v 12.0v c0h 16.00v ffh 0v 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 25h r remote diode 1 (zone 1) temp reading 7 6 5 4 3 2 1 0 n/a 26h r internal diode (zone 2) temp reading 7 6 5 4 3 2 1 0 n/a 27h r remote diode 2 (zone 3) temp reading 7 6 5 4 3 2 1 0 n/a
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 250 smsc sch311x datasheet note: to read a 12-bit reading value, software must read in the order of msb then lsb. if several readings are being read at the same time, software can read all the msb registers then the corresponding lsb registers. for example: read rd1 reading, rd2 reading, then a/d converter lsbs reg1, which contains the lsbs for rd1 and rd2. 24.2.4 registers 28-2dh: fan tachometer reading this register is reset to its default value when pwrgd_ps is asserted. the fan tachometer reading registers contain the number of 11.111 s periods (90khz) between full fan revolutions. fans produce two tachometer pulses per full revolution. these registers are updated at least once every second. this value is represented for each fan in a 16 bit, unsigned number. the fan tachometer reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, including when the start bit=0. when one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. the order is lsb first, msb second. ffffh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). table 24.3 temperature vs. register reading temperature reading (dec) reading (hex) -127 c -127 81h . . . . . . . . . -50 c -50 ceh . . . . . . . . . 0 c 0 00h . . . . . . . . . 50 c 50 32h . . . . . . . . . 127 c 127 7fh (sensor error) 80h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 28h r fantach1 lsb 7 6 5 4321 0 ffh 29h r fantach1 msb 15 14 13 12 11 10 9 8 ffh 2ah r fantach2 lsb 7 6 5 4 3 2 1 0 ffh 2bh r fantach2 msb 15 14 13 12 11 10 9 8 ffh 2ch r fantach3 lsb 7 6 5 4 3 2 1 0 ffh 2dh r fantach3 msb 15 14 13 12 11 10 9 8 ffh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 251 revision 0.4 (06-03-05) datasheet these registers are read only ? a write to these registers has no effect. 24.2.5 registers 30-32h: current pwm duty note 24.12 these registers are only writable when the associated fan is in manual mode. these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. the current pwm duty registers store the duty cycle t hat the chip is currentl y driving the pwm signals at. at initial power-on, the duty cycle is 100% and thus, when read, this register will return ffh. after the ready/lock/start register start bit is set, th is register and the pwm signals are updated based on the algorithm described in the auto fan control operating mode section and the ramp rate control logic, unless the associated fan is in manual mode ? see below. note: when the device is configured for manual mode, the ramp rate control logic should be disabled. when read, the current pwm duty registers return the current pwm duty cycle for the respective pwm signal. these registers are read only ? a write to these registers has no effect. note: if the current pwm duty cycle registers are writt en while the part is no t in manual mode or when the start bit is zero, the data will be stored in internal registers that will only be active and observable when the start bit is set and the fan is configured for manual mode. while the part is not in manual mode and the start bit is zero, the current pwm duty cycle registers will read back ffh. manual mode (test mode) in manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writeable to control the pwms. note: when the lock bit is set to 1, the current duty cycle registers are read-only. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 30h r /w (note 24.12 ) pwm1 current duty cycle 7 6 5 4 3 2 1 0 n/a 31h r /w (note 24.12 ) pwm2 current duty cycle 7 6 5 4 3 2 1 0 n/a 32h r /w (note 24.12 ) pwm3 current duty cycle 7 6 5 4 3 2 1 0 n/a
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 252 smsc sch311x datasheet the pwm duty cycle is represented as follows: during spin-up, the pwm dut y cycle is reported as 0%. notes: the pwmx current duty cycle always reflects the current duty cycle on the associated pwm pin. the pwmx current duty cycle register is implem ented as two separate registers: a read-only and a write-only. when a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software . the hardware updates the read-only pwmx current duty cycle register on th e beginning of a pwm cycle. if ramp rate contro l is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(pwm frequency) seconds. typically, the delay will be 1/(2*pwm frequency) seconds. 24.2.6 register 3dh: device id the device id register contains a unique value to allow software to identify which device has been implemented in a given system. 24.2.7 register 3eh: company id the company id register contains a unique value to allow software to identify smsc devices that been implemented in a given system. table 24.4 pwm duty vs register reading current duty value (decimal) value (hex) 0% 0 00h ? ? ? 25% 64 40h ? ? ? 50% 128 80h ? ? ? 100% 255 ffh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3dh r device id 7 6 5 432108ch register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3eh r company id 7 6 5 432105ch
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 253 revision 0.4 (06-03-05) datasheet 24.2.8 register 3fh: revision the revision register contains the current version of this device. the register is used by application software to identify which version of the device has been implemented in the given system. based on this in formation, software can determine which registers to read from and write to. further, application software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping. this register is read only ? a write to this register has no effect. 24.2.9 register 40h: read y/lock/start monitoring note 24.13 this lock bit is cleared when pwrgd_ps is asserted. setting the lock bit makes the lock and start bits read-only. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3fh r revision 7 6 5 4321001h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 40h r/w ready/lock/start res res res res ovrid ready lock note 24.13 start 04h bit name r/w default description 0 start r/w 0 when software writes a 1 to this bit, the sch311x enables monitoring and pwm output control functions based on the limit and parameter registers. before this bit is set, the part does not update register values. whenever this bit is set to 0, the monitoring and pwm output control functions are based on the default limits and parameters, regardless of the current values in the limit and parameter registers. the sch311x preserves the values currently stored in the limit and parameter registers when this bit is set or cleared. this bit becomes read only when the lock bit is set. notes: when this bit is 0, all fans are on full 100% duty cycle, i.e., pwm pins are high for 255 clocks, low for 1 clock. when this bit is 0, the part is not monitoring. it is suggested that software clear the start bit and exit auto fan control mode before modifying any fan configuration registers. after clearing the start bit, software should wait for a period of one 90khz-10% clock (~12.5usec) before setting the start bit back to ?1? to ensure the fan logic exited auto mode when start was cleared. 1 lock r/w note 24.14 0 setting this bit to 1 locks sp ecified limit and parameter registers. once this bit is set, limit and parameter registers become read only and will remain locked until the device is powered off. this register bit becomes read only once it is set.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 254 smsc sch311x datasheet note 24.14 this bit is set by software and cleared by hardware. writing a ?0? to this register has no effect. note 24.15 there is a start-up time of up to tbd ms (default - see pme_sts1) for monitoring after the start bit is set to ?1?, during which time the reading registers are not valid. software can poll the trdy bit located in the configur ation register (7fh) to determine when the voltage and temperature readings are valid.the following summarizes the operation of the part based on the start bit: 1. if start bit = '0' then: a. fans are set to full on. b. no temperature or fan tach monitoring is performed. the values in the reading registers will be n/a (not applicable), which means these values will not be considered valid readings until the start bit = '1'. the exception to this is the tachometer reading registers, which always give the actual reading on the tach pins. c. no status bits are set. 2. if start bit = '1' a. all fan control and monitoring will be based on the current values in the registers. there is no need to preserve the default values after software has programmed these registers because no monitoring or auto fan control will be done when start bit = '0'. b. status bits may be set. note: once programmed, the register values will be saved when start bit is reset to ?0?. 24.2.10 register 41h: inte rrupt status register 1 2 ready r 0 the sch311x sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all a/d converters are functioning (all bias conditions for the a/ds have stabilized and the a/ds are in operational mode). (always reads back ?1?.) 3 ovrid r/w 0 if this bit is set to 1, all pw m outputs go to 100% duty cycle regardless of whether or not the lock bit is set. 4 vbat mon r/w 0 the vbat monitoring enable bit determines if vbat will be monitored on the next available monitoring cycle. this is a read/write bit. writi ng this bit to a ?1? will enable the vbat input to be monitored on the next available monitoring cycle. writing this bit to a ?0? has no effect. this bit is cleared on an hvtr por or when the vbat register is updated. software can poll this bit for a ?0? after setting it to a ?1? to determine when the vbat register has been updated. 0 = vbat input is not being monitored (default) 1 = vbat input is being monitored note: the lock bit has no effect on this register bit. 5-7 reserved r 0 reserved register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 41h r/wc interrupt status 1 int2 note 24.16 d2 amb d1 5v vcc vccp 2.5v 00h bit name r/w default description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 255 revision 0.4 (06-03-05) datasheet note 24.16 this is a read-only bit. writing ?1? to this bit has no effect. notes: this register is reset to its default value when the pwrgd_ps signal transitions high. the is a read/write-to-clear register. bits[6:4] are cleared on a write of one if the temperature event is no longer active. writing a zero to these bits has no effect. bit[7] int2 this bit indicates that a status bit is set in the in terrupt status register 2 register. therefore, s/w can poll this register, and only if bit 7 is set does the other registers need to be read. this bit is cleared (set to 0) automatically by the device if there ar e no bits set in the interrupt status register 2. bits[6:0] individual status bits bits[6:0] of the interrupt status register 1 are aut omatically set by the device whenever the measured temperature on remote diode 1, internal diode, or the remote diode 2 temperature violates the limits set in the corresponding temperature limit registers. these individual status bits remain set until the bit is written to one by software or until the individual enable bit is cleared, even if the temperatures no longer violate the limits se t in the limit registers. clearing the status bits by a write of ?1? the voltage status bits are cleared (set to 0) au tomatically by the sch311x after they are written to one by software, if the voltage readings no longer violate the limit set in the limit registers. see registers 44-4dh, 9b-9eh: voltage limit registers on page 257 . the temperature status bits are cleared (set to 0) automatically by the sch311x after they are written to one by software, if the temperature readings no longer violate the limit set in the limit registers. see registers 4e-53h: temperature limit registers on page 258 . clearing the status bits by clearing the individual enable bits. clearing or setting the individual enable bits does not take effect unless the start bit is 1. no interrupt status events can be generated when start=0 or when the individual enable bit is cleared. if the status bit is one and the start bit is one then clearing the individual enable bit will immediately clear the status bit. if the status bit is one and the start bit is zero then clearing the individual enable bit will have no effect on the status bit until the start bit is set to one. setting the start bit to one when the individual enable bit is zero will clear the status bit. setting or clearing the start bit when the individual enable bit is one has no effect on the status bits. notes: the individual enable bits for d2, amb, and d1 are located in the interrupt enable 3 (temp) register at offset 82h. clearing the group temp enable bit or the global inten enable bit has no effect on the status bits.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 256 smsc sch311x datasheet 24.2.11 register 42h: interrupt status register 2 notes: this register is reset to its default value when the pwrgd_ps signal transitions high. this is a read/write-to-clear register. the status bits are cleared on a write of one if the event causing the interrupt is no longer active. writing a zero to these bits has no effect. the interrupt status register 2 bits is automatica lly set by the device whenever a tach reading value is above the minimum value set in the tachometer minimum registers or when a remote diode fault occurs. when a remote diode fault occurs (if the start bit is set) 80h will be loaded into the associated temperature reading register, whic h causes the associated diode limit error bit to be set (see register 41h: interrupt status register 1 on page 254 ) in addition to the diode fault bit (errx). these individual status bits remain set until the bit is written to one by software or until the individual enable bit is cleared, even if the event no longer persists. clearing the status bits by a write of ?1? the fantachx status bits are cleared (set to 0) automatically by the sch311x after they are written to one by software, if the fantachx reading register no longer violates the programmed fantach limit. (see registers 28-2dh: fan tachometer reading on page 250 and registers 54- 59h: fan tachometer low limit on page 259 ) the errx status bits are cleared (set to 0) auto matically by the sch311x after they are written to one by software, if the diode fault condition no longer exists. the remote diode fault bits do not get cleared while the fault condition exists. bit name r/w default description 0 2.5v_error r/wc 0 the sch311x automatically sets this bit to 1 when the 2.5v input voltage is less than or equal to the limit set in the 2.5v low limit register or greater than the limit set in the 2.5v high limit register. 1 vccp_error r/wc 0 the sch311x automatically sets this bit to 1 when the vccp input voltage is less than or equal to the limit set in the vccp low limit register or greater than the limit set in the vccp high limit register. 2 vcc_error r/wc 0 the sch311x automatically sets this bit to 1 when the vcc input voltage is less than or equal to the limit set in the vcc low limit register or greater than the limit set in the vcc high limit register. 3 5v_error r/wc 0 the sch311x automatically sets this bit to 1 when the 5v input voltage is less than or equal to the limit set in the 5v low limit register or greater than the limit set in the 5v high limit register. 4 remote diode 1 limit error r/wc 0 the sch311x automatically sets this bit to 1 when the temperature input measured by the remote1- and remote1+ is less than or equal to the limit set in the remote diode 1 low temp register or greater than the limit set in remote diode 1 high temp register. 5 internal sensor limit error r/wc 0 the sch311x automatically sets this bit to 1 when the temperature input measured by the internal temperature sensor is less than or equal to the limit set in the internal low temp register or greater than the limit set in the internal high temp register. 6 remote diode 2 limit error r/wc 0 the sch311x automatically sets this bit to 1 when the temperature input measured by the remote2- and remote2+ is less than or equal to the limit set in the remote diode 2 low temp register or greater than the limit set in the remote diode 1 high temp register. 7 int2 event active r/wc 0 the device automatically sets this bit to 1 when a status bit is set in the interrupt status register 2. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 42h r/wc interrupt status register 2 err2 err1 res fanta ch3 fanta ch2 fanta ch1 res 12v 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 257 revision 0.4 (06-03-05) datasheet clearing the status bits by clearing the individual enable bits. clearing or setting the individual enable bits does not take effect unless the start bit is 1. no interrupt status events can be generated when start=0 or when the individual enable bit is cleared. if the status bit is one and the start bit is one then clearing the individual enable bit will immediately clear the status bit. if the status bit is one and the start bit is zero then clearing the individual enable bit will have no effect on the status bit until the start bit is set to one. setting the start bit to one when the individual enable bit is zero will clear the status bit. setting or clearing the start bit when the individual enable bit is one has no effect on the status bits. notes: the individual enable bits for fantach[1:3] are located in register 80h: interrupt enable 2 register on page 270 . the errx bits are enabled by the remote diode limit error bits located in register 82h: interrupt enable 3 register on page 272 clearing the group fantach or temp enable bits or the global inten enable bit has no effect on the status bits. 24.2.12 registers 44-4dh, 9b-9 eh: voltage limit registers bit name r/w default description 0 +12v_error r 0 the sch311x automatically sets this bit to 1 when the 12v input voltage is less than or equal to the limit set in the 12v low limit register or greater than the limit set in the 12v high limit register. 1 reserved r 0 reserved 2 fantach1 slow/stalled r/wc 0 the sch311x automatically sets this bit to 1 when the fantach1 input reading is above the value set in the tach1 minimum msb and lsb registers. 3 fantach2 slow/stalled r/wc 0 the sch311x automatically sets this bit to 1 when the fantach2 input reading is above the value set in the tach2 minimum msb and lsb registers. 4 fantach3 slow/stalled r/wc 0 the sch311x automatically sets this bit to 1 when the fantach3 input reading is above the value set in the tach3 minimum msb and lsb registers. 5 reserved r 0 reserved 6 remote diode 1 fault r/wc 0 the sch311x automatically sets this bi t to 1 when there is either a short or open circuit fault on the remote1+ or remote1- thermal diode input pins as defined in the sectionpme_sts1. if the start bit is set and a fault condition exists, the remote diode 1 reading register will be forced to 80h. 7 remote diode 2 fault r/wc 0 the sch311x automatically sets this bi t to 1 when there is either a short or open circuit fault on the remote2+ or remote2- thermal diode input pins as defined in the sectionpme_sts1. if the start bit is set and a fault condition exists, the remote diode 2 reading register will be forced to 80h. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 44h r/w 2.5v low limit 7 6 5 4 3 2 1 0 00h 45h r/w 2.5v high limit 7 6 5 4 3 2 1 0 ffh 46h r/w vccp low limit 7 6 5 4 3 2 1 0 00h 47h r/w vccp high limit 7 6 5 4 3 2 1 0 ffh 48h r/w vcc low limit 7 6 5 4 3 2 1 0 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 258 smsc sch311x datasheet setting the lock bit has no effect on these registers. if a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in the voltage low limit register, the corresponding bit will be set automatically in the interrupt status registers (41-42h, 83h). voltages are presented in the registers at ? full scale for the nominal voltage, meaning that at nominal voltage, each register will read c0h, except for the vbat input. vbat is nominally a 3.0v input that is implemented on a +3.3v (nominal) analog input. therefore, the nominal reading for vbat is aeh. note: vbat will only be monitored when the vbat monitoring enable bit is set to ?1?. updating the vbat reading register automatically clears the vbat monitoring enable bit. note 24.17 vbat is a nominal 3.0v input source that has been implemented on a 3.3v analog voltage monitoring input. 24.2.13 registers 4e-53h: te mperature limi t registers 49h r/w vcc high limit 7 6 5 4 3 2 1 0 ffh 4ah r/w 5v low limit 7 6 5 4 3 2 1 0 00h 4bh r/w 5v high limit 7 6 5 4 3 2 1 0 ffh 4ch r/w 12v low limit 7 6 5 4 3 2 1 0 00h 4dh r/w 12v high limit 7 6 5 4 3 2 1 0 ffh 9bh r/w vtr low limit 7 6 5 4 3 2 1 0 00h 9ch r/w vtr high limit 7 6 5 4 3 2 1 0 ffh 9dh r/w vbat low limit 7 6 5 4 3 2 1 0 00h 9eh r/w vbat high limit 7 6 5 4 3 2 1 0 ffh table 24.5 voltage limits vs. register setting input nominal voltage register reading at nominal voltage maximum voltage register reading at maximum voltage minimum voltage register reading at minimum voltage vtr 3.3v c0h 4.38v ffh 0v 00h vbat ( note 2 4.17 ) 3.0v aeh 4.38v ffh 0v 00h 2.5v 5.0v c0h 6.64v ffh 0v 00h vccp 2.25v c0h 3.00v ffh 0v 00h vcc 3.3v c0h 4.38v ffh 0v 00h 5v 5.0v c0h 6.64v ffh 0v 00h 12v 12.0v c0h 16.00v ffh 0v 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 4eh r/w remote diode 1 low temp 7 6 5 4 3 2 1 0 81h 4fh r/w remote diode 1 high temp 7 6 5 4 3 2 1 0 7fh 50h r/w ambient low temp 7 6 5 4 3 2 1 0 81h 51h r/w ambient high temp 7 6 5 4 3 2 1 0 7fh 52h r/w remote diode 2 low temp 7 6 5 4 3 2 1 0 81h 53h r/w remote diode 2 high temp 7 6 5 4 3 2 1 0 7fh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 259 revision 0.4 (06-03-05) datasheet setting the lock bit has no effect on these registers. if an external temperature input or the internal temp erature sensor either exceeds the value set in the high limit register or is less than or equal to the value set in the low limit register, the corresponding bit will be set automatically by the sch311x in the interrupt stat us register 1 (41h). for example, if the temperature reading from the remote1- and re mote1+ inputs exceeds the remote diode 1 high temp register limit setting, bit[4] d1 of the interrupt stat us register 1 will be se t. the temperature limits in these registers are represented as 8 bit, 2?s complement, signed numbers in celsius, as shown below in table 24.6 . 24.2.14 registers 54-59h: fa n tachometer low limit setting the lock bit has no effect on these registers. the fan tachometer low limit registers indi cate the tachometer reading under which the corresponding bit will be set in the interrupt status register 2 register. in auto fan control mode, the fan can run at high speeds (100% duty cycle), so care should be taken in software to ensure that the limit is low enough not to cause sporadic alerts. note that an interrupt status event will be generated when the tachometer reading is greater than the minimum tachometer limit. the fan tachometer will not cause a bit to be set in the interrupt status register if the current value in the associated current pwm duty registers is 00h or if the pwm is disabled via the pwm configuration register. table 24.6 temperature limi ts vs. register settings temperature limit (dec) limit (hex) -127 c-127 81h . . . . . . . . . -50 c-50 ceh . . . . . . . . . 0 c000h . . . . . . . . . 50 c50 32h . . . . . . . . . 127 c127 7fh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 54h r/w fantach1 minimum lsb 7 6 5 4 3 2 1 0 ffh 55h r/w fantach1 minimum msb 15 14 13 12 11 10 9 8 ffh 56h r/w fantach2 minimum lsb 7 6 5 4 3 2 1 0 ffh 57h r/w fantach2 minimum msb 15 14 13 12 11 10 9 8 ffh 58h r/w fantach3 minimum lsb 7 6 5 4 3 2 1 0 ffh 59h r/w fantach3 minimum msb 15 14 13 12 11 10 9 8 ffh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 260 smsc sch311x datasheet interrupts will never be generated for a fan if its tachometer minimum is set to ffffh. 24.2.15 registers 5c-5eh: pwm configuration these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. bits [7:5] zone/mode bits [7:5] of the pwm configuration registers associate each pwm with a temperature zone. when in auto fan mode, the pwm will be assigned to a zo ne, and its pwm duty cycle will be adjusted according to the temperature of that zone. if ?hottest? option is selected (101 or 110), the pwm will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. if one of these options is selected, the pwm is controlled by the limits and parameters for the zone that requires the highest pwm duty cycle, as co mputed by the auto fan algorithm. when in manual control mode, the pwmx current duty cycle registers (30h-32h) become read/write. it is then possible to control the pwm outputs with software by writing to these registers. see pwmx current duty cycle registers description. when the fan is disabled (100) the corresponding pwm output is driven low (or high, if inverted). when the fan is full on (011) the corresponding pwm output is driven high (or low, if inverted). notes: zone 1 is controlled by remote diode 1 temp reading register zone 2 is controlled by the ambient reading register. zone 3 is controlled by remote diode 2 temp reading register bit [4] pwm invert bit [4] inverts the pwm output. if set to 1, 100% duty cycle will yi eld an output that is low for 255 clocks and high for 1 clock. if set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock. register address read/write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 5ch r/w pwm 1 configuration zon2 zon1 zon0 inv suen1 spin2 spin1 spin0 62h 5dh r/w pwm 2 configuration zon2 zon1 zon0 inv suen2 spin2 spin1 spin0 62h 5eh r/w pwm 3 configuration zon2 zon1 zon0 inv suen3 spin2 spin1 spin0 62h table 24.7 fan zone setting zon[7:5] pwm configuration 000 fan on zone 1 auto 001 fan on zone 2 auto 010 fan on zone 3 auto 011 fan always on full 100 fan disabled 101 fan controlled by hottest of zones 2,3 110 fan controlled by hottest of zones 1,2,3 111 fan manually controlled
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 261 revision 0.4 (06-03-05) datasheet bit [3] forced spin-up enable bit [3] enables the forced spin up option for a particular pwm. if set to 1, the forced spin-up feature is enabled for the associated pwm. if set to 0, the forced spin-up feature is disabled for the associated pwm. application note: this bit should always be enabled (set) to prevent fan tachometer interrupts during spinup. bits [2:0] spin up bits [2:0] specify the ?spin up? time for the fan. when a fan is being started from a stationary state, the pwm output is held at 100% duty cycle for the time specified in the table below before scaling to a lower speed. note: during spin-up, the pwm pin is forced high for the duration of the spin-up time (i.e., 100% duty cycl e = 256/256) note: to reduce the spin-up time, this device has implemented a feature referred to as spin up reduction. spin up reduction uses feedback from the tachometers to determine when each fan has started spinning properly. spin up for a pwm will end when the tachometer reading register is below the minimum limit, or the spin-up time expires, whichever comes first. all tachs associated with a pwm must be below min. for spin-up to end prematurely. this feature can be disabled by clearing bit 4 (suren) of the conf iguration register (7fh). if disabled, the all fans go on full for the duration of their associated spin up time. note that the tachx minimum registers must be programmed to a value less than ffffh in order for the spin-up reduction to work properly. 24.2.16 registers 5f-61h: zone temperature range, pwm frequency these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. in auto fan mode, when the temperature for a zone is above the low temperature limit (registers 67-69h) and below the absolute temperature limit (registers 6a-6ch) the speed of a fan assigned to that zone is determined as follows by the auto fan control logic. when the temperature reaches the temperature va lue programmed in the zone x low temp limit register, the pwm output assigned to that zone is at pwmx minimum duty cycle. between zone x table 24.8 fan spin-up register spin[2:0] spin up time 000 0 sec 001 100ms 010 250ms (default) 011 400ms 100 700ms 101 1000ms 110 2000ms 111 4000ms register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 5fh r/w zone 1 range / fan 1 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 cbh 60h r/w zone 2 range / fan 2 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 cbh 61h r/w zone 3 range / fan 3 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 cbh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 262 smsc sch311x datasheet low temp limit and (zone x low temp limit + zone x range), the pwm duty cycle increases linearly according to the temperature as shown in the figure below. figure 24.1 fan activity above fan temp limit example for pwm1 assigned to zone 1: zone 1 low temp limit (register 67h) is set to 50 c (32h). zone 1 range (register 5fh) is set to 8 c (7h) pwm1 minimum duty cycle (register 64h) is set to 50% (80h) in this case, the pwm1 duty cycle will be 50% at 50 c. since (zone 1 low temp limit) + (zone 1 range) = 50 c + 8 c = 58 c, the fan controlled by pwm1 will run at 100% duty cycle when the temper ature of the zone 1 sensor is at 58 c. since the midpoint of the fan control range is 54 c, and the median duty cycle is 75% (halfway between the pwm minimum and 100%), pwm1 duty cycle would be 75% at 54 c. above (zone 1 low temp limit) + (zon e 1 range), the duty cycle must be 100%. the pwm frequency bits [3:0] determine the pwm frequency for the fan. if the high frequency option is selected the associated fantach inputs must be configured for mode 1. 24.2.16.1 pwm frequency selection (default =1011 bits=25khz) table 24.9 pwm frequency selection frequency select bits[3:0] frequency 14.318mhz clock source 0000 11.0 hz 0001 14.6 hz 0010 21.9 hz 0011 29.3 hz 0100 35.2 hz 0101 44.0 hz 0110 58.6 hz 0111 87.7 hz 1000 15khz 1001 20khz 1010 30khz 1011 25khz (default) temperature below fan temp limit: fan is off or at fan pwm minimum depending on bi t[7:5] of r egister 62h and bit 2 of register 7fh temperature limit: pwm output at min fan speed limit+ range: pwm output at 100% duty pwm duty is linear over this range
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 263 revision 0.4 (06-03-05) datasheet 24.2.16.2 range selection (default =1100=32 c) note: the range numbers will be used to calculate the slope of the pwm ramp up. for the fractional entries, the pwm will go on full when the temp reaches the next integer value e.g., for 3.33, pwm will be full on at (min. temp + 4). 24.2.17 register 62h, 63h: pwm ramp rate control these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. res1 bits are set to ?1? and are read only, writes are ignored. 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 24.10 register setting vs. temperature range ran[3:0] range ( c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 1101 40 1110 53.33 1111 80 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 62h r/w pwm 1 ramp rate control r es1 res1 res1 res rr1e r r1-2 rr1-1 rr1-0 e0h 63h r/w pwm 2, pwm 3 ramp rate control rr2e rr2-2 rr2-1 rr2-0 rr3e rr3-2 rr3-1 rr3-0 00h table 24.9 pwm frequency selection (continued) frequency select bits[3:0] frequency 14.318mhz clock source
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 264 smsc sch311x datasheet description of ramp rate control bits: if the remote1 or remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the part. the auto fan control logic calculates the pwm duty cycle for all temperature readings. if ra mp rate control is disabled, the pw m output will jump or oscillate between different pwm duty cycles causing the fan to suddenly change speeds, which creates unwanted fan noise. if enabled, the pwm ramp rate control logic will prevent the pwm output from jumping, instead the pwm will ramp up/dow n towards the new duty cycle at a pre-determined ramp rate. ramp rate control the ramp rate control logic limits the amount of change to the pwm duty cycle over a period of time. this period of time is programmable via the ramp rate control bits. for a detailed description of the ramp rate control bits see table 24.11 . for a description of the ramp rate control logic seepme_sts1. notes: rr1e, rr2e, and rr3e enable pwm ramp rate control for pwm 1, 2, and 3 respectively. rr1-2, rr1-1, and rr1-0 contro l ramp rate time for pwm 1 rr2-2, rr2-1, and rr2-0 contro l ramp rate time for pwm 2 rr3-2, rr3-1, and rr3-0 contro l ramp rate time for pwm 3 note: this assumes the ramp rate enable bit (rrxe) is set. 24.2.18 registers 64-66h: minimum pwm duty cycle table 24.11 pwm ramp rate control rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from 0% duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz) 000 35 52.53 206 msec 4.85 001 17.6 26.52 104 msec 9.62 010 11.8 17.595 69 msec 14.49 011 7.0 10.455 41 msec 24.39 100 4.4 6.63 26 msec 38.46 101 3.0 4.59 18 msec 55.56 110 1.6 2.55 10 msec 100 111 0.8 1.275 5 msec 200 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 64h r/w pwm1 minimum duty cycle 7 6 5 4 3 2 1 0 80h 65h r/w pwm2 minimum duty cycle 7 6 5 4 3 2 1 0 80h 66h r/w pwm3 minimum duty cycle 7 6 5 4 3 2 1 0 80h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 265 revision 0.4 (06-03-05) datasheet these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. these registers specify the mi nimum duty cycle that the pw m will output when the measured temperature reaches the temper ature limit register setting in auto fan control mode. 24.2.19 registers 67-69h: zone low temperature limit note 24.18 this register is reset to the default value following a vcc por when the pwrgd_ps signal is asserted. these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. these are the temperature limits for the individual zones. when the current temperature equals this limit, the fan will be turned on if it is not alre ady. when the temperature exceeds this limit, the fan speed will be increased according to the auto fan algorithm based on the setting in the zone x range / pwmx frequency register. default = 90 c=5ah table 24.12 pwm duty vs. register setting minimum pwm duty value (decimal) value (hex) 0% 0 00h . . . . . . . . . 25% 64 40h . . . . . . . . . 50% 128 80h . . . . . . . . . 100% 255 ffh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 67h r/w zone 1 (remote diode 1) low tem p li m i t 7 6 5 4 3 2 1 0 80h note 24 .18 68h r/w zone 2 (ambient) low temp limit 7 6 5 4 3 2 1 0 80h note 24 .18 69h r/w zone 3 (remote diode 2) low tem p li m i t 7 6 5 4 3 2 1 0 80h note 24 .18 table 24.13 temperature limit vs. register setting limit limit (dec) limit (hex) -127 c-127 81h . . . . . . . . . -50 c-50 ceh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 266 smsc sch311x datasheet 24.2.20 registers 6a-6ch: ab solute temperature limit these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. in auto fan mode, if any zone associated with a pwm output exceeds the temperature set in the absolute limit register, all pwm outputs will increase their duty cycle to 100% except those that are disabled via the pwm configuration registers. this is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. if an absolute limit register set to 80h (-128 c), the safety feature is disabled for the associated zone. that is, if 80h is written into the zone x temp absolute limit register, then regardless of the reading register for the zone, the fans will not turn on-full based on the absolute temp condition. default =100 c=64h. when any fan is in auto fan mode, then if the temperature in any zone exceeds absolute limit, all fans go to full, including any in manual mode, except those that are disabled. therefore, even if a zone is not associated with a fan, if that zone exceeds abs olute, then all fans go to full. in this case, the absolute limit can be chosen to be 7fh for those zones that are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees. . . . . . . . . . 0 c000h . . . . . . . . . 50 c50 32h . . . . . . . . . 127 c127 7fh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64h 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64h 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64h table 24.14 absolute limit vs. register setting absolute limit abs limit (dec) abs limit (hex) -127 c-127 81h . . . . . . . . . -50 c-50 ceh . . . . . . . . . table 24.13 temperature limit vs . register setting (continued) limit limit (dec) limit (hex)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 267 revision 0.4 (06-03-05) datasheet 24.2.21 registers 6d-6eh: smsc test registers 24.2.22 register 70-72h: smsc test register this is a read-only smsc test register. writing to this register has no effect. 24.2.23 register 73-78h : smsc test register these are smsc test registers. writing to these registers may cause unwanted results. 0 c000h . . . . . . . . . 50 c50 32h . . . . . . . . . 127 c127 7fh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6dh r/w smsc test register 7 6 5 4 3 2 1 0 44h 6eh r/w smsc test register 7 6 5 4 res res res res 40h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 70h r smsc test register 7 6 5 4 3 2 1 0 n/a 71h r smsc test register 7 6 5 4 3 2 1 0 n/a 72h r smsc test register 7 6 5 4 3 2 1 0 n/a register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 73h r smsc test register res res res res tst3 tst2 tst1 tst0 09h 74h r/w smsc test register res res res res tst3 tst2 tst1 tst0 09h 75h r smsc test register res res res res tst3 tst2 tst1 tst0 09h 76h r/w smsc test register res res res res tst3 tst2 tst1 tst0 09h 77h r smsc test register res res res res tst3 tst2 tst1 tst0 09h 78h r/w smsc test register res res res res tst3 tst2 tst1 tst0 09h table 24.14 absolute limit vs. register setting (continued) absolute limit abs limit (dec) abs limit (hex)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 268 smsc sch311x datasheet 24.2.24 register 79h: smsc test register this is a read/write register. writing this register may produce unwanted results. this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. 24.2.25 register 7ch: sp ecial function register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register contains the following bits: bit[0] reserved bit[1] monitoring mode select 0= continuous monitor mode (default) 1= cycle monitor mode bit[2] interrupt (nhwm_int pin) enable 0=disables nhwm_int pin output function (default) 1=enables nhwm_int pin output function bit[3] smsc reserved this is a read/write bit. reading this bit has no effect. writing this bit to ?1? may cause unwanted results. bit [4] smsc reserved this is a read/write bit. reading this bit has no effect. writing this bit to ?1? may cause unwanted results. bits [7:5] avg[2:0] the avg[2:0] bits determine the amount of averaging for each of the measurements that are performed by the hardware monitor before the reading register s are updated (table 22). the avg[2:0] bits are priority encoded where the most significant bit has highest priority. for example, when the avg2 bit is asserted, 32 averages will be performed fo r each measurement before the reading registers are updated regardless of the state of the avg[1:0] bits. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 79h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7ch r/w special function avg2 avg1 avg0 smsc smsc int_e n monmd res e0h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 269 revision 0.4 (06-03-05) datasheet note: the default for the avg[2:0] bits is ?010?b. 24.2.26 register 7eh: inte rrupt enable 1 register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register is used to enable individual voltage error events to set the corresponding status bits in the interrupt status registers. this register also contains the group voltage enable bit (bit[0] volt), which is used to enable voltage events to force the interrupt pin (nhwm_int) low if interrupts are enabled (see bit[2] inten of the special function register at offset 7ch). this register contains the following bits: bit[0] group interrupt voltage enable (volt) 0=out-of-limit voltages do not affect the state of the nhwm_int pin (default) 1=enable out-of-limit voltages to make the nhwm_int pin active low bit[1] vbat error enable bit[2] 2.5v error enable bit[3] vccp error enable bit[4] vtr error enable bit[5] 5v error enable bit[6] 12v error enable bit[7] vcc error enable the individual voltage error event bits are defined as follows: 0=disable 1=enable. see figure 23.3 interrupt control on page 211 . table 24.15 avg[2:0] bit decoder sftr[7:5] averages per reading avg2 avg1 avg0 rem diode 1 rem diode 2 internal diode 000 128 128 8 001 16 16 1 01x 16 16 16 1xx 32 32 32 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7eh r/w interrupt enable 1 (voltages) vcc 12v 5v vtr vccp 2.5v vbat volt ech
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 270 smsc sch311x datasheet 24.2.27 register 7fh: configuration register note 24.19 trdy is cleared when the pwrgd_ps signal is asserted. these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register contains the following bits: bit[0] reserved bit[1] reserved bit[2] mon_dn: this bit is used to detect when the monitoring cycle is completed following the start bit being set to 0. when the start bit is cleared, the hardware monitoring block always completes the monitoring cycle. 0= monitoring cycl e active, 1= monitoring cycle complete. application note: when the start bit is 1, and the device is monitoring, this bit will toggle each time it completes the monitoring cycle. it is intended that the user only read this bit when the start bit is 0. bit[3] trdy: temperature reading ready. this bit indicates that the temperature reading registers have valid values. this bit is used after writin g the start bit to ?1?. 0= not valid, 1=valid. bit[4] suren: spin-up reduction enable. this bit enables the reduction of the spin-up time based on feedback from all fan tachometers associated with each pwm. 0=disable, 1=enable (default) bit[5] smsc reserved this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. bit[5] smsc reserved this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. bit[6] smsc reserved this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. bit[7] initialization setting the init bit to ?1? performs a soft reset. this bit is self-clearing. soft reset sets all the registers except the reading registers to their default values. 24.2.28 register 80h: inte rrupt enable 2 register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7fh r/w configuration init smsc smsc suren trdy note 24.19 mon_ dn res res 10h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 80h r/w interrupt enable 2 (fan tachs) res res res res fanta ch3 fanta ch2 fanta ch1 fan- tach 1eh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 271 revision 0.4 (06-03-05) datasheet these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to enable individual fan tach error events to set the corresponding status bits in the interrupt status registers. this register also contains the group fan tach enable bit (bit[0] tach), which is used to enable fan tach events to force t he interrupt pin (nhwm_int) low if interrupts are enabled (see bit[2] inten of the special function register at offset 7ch). this register contains the following bits: bit[0] fantach (group tach enable) 0=out-of-limit tachometer readings do not affect the state of the nhwm_int pin (default) 1=enable out-of-limit tachometer readings to make the nhwm_int pin active low bit[1] fantach 1 event enable bit[2] fantach 2 event enable bit[3] fantach 3 event enable bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved the individual fan tach error event bits are defined as follows: 0=disable 1=enable. see pme_sts1. 24.2.29 register 81h: tach _pwm association register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to associate a pwm with a tachometer input. this association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status registers. the fan tachometer will not cause a bit to be set in the interrupt status register: a. if the current value in current pwm duty registers is 00h or b. if the fan is disabled via the fan configuration register. note: a bit will never be set in the interrupt status for a fan if its tachometer minimum is set to ffffh. see bit definition below. bits[1:0] tach1. these bits determine the pwm associated with this tach. see bit combinations below. bits[3:2] tach2. these bits determine the pwm associated with this tach. see bit combinations below. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 81h r/w tach_pwm association res res t3h t3l t2h t2l t1h t1l 24h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 272 smsc sch311x datasheet bits[5:4] tach3. these bits determine the pwm associated with this tach. see bit combinations below. bits[7:6] reserved notes: any pwm that has no tach inputs associated with it must be configured to operate in mode 1. all tach inputs must be associated with a pwm output. if the tach is not being driven by the associated pwm output it should be configured to operate in mode 1 and the associated tach interrupt must be disabled. 24.2.30 register 82h: inte rrupt enable 3 register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status registers. this register also contains the group thermal enable bit (bit[0] temp), which is used to enable thermal events to force the interrupt pin (nhwm_int) low if interrupts are enabled (see bit[2] inten of the special function register at offset 7ch). this register contains the following bits: bit[0] temp. group temperature enable bit. 0=out-of-limit temperature readings do not affect the state of the nhwm_int pin (default) 1=enable out-of-limit temperature readings to make the nhwm_int pin active low bit[1] zone 2 temperature status enable bit. bit[2] zone 1 temperature status enable bit. bit[3] zone 3 temperature status enable bit bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved the individual thermal error event bits are defined as follows: 0=disable 1=enable bits[1:0], bits[3:2], bits[5:4], bits[7:6] pwm associated with tachx 00 pwm1 01 pwm2 10 pwm3 11 reserved register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 82h r/w interrupt enable 3 (temp) res res res res d2en d1en amb temp 0eh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 273 revision 0.4 (06-03-05) datasheet 24.2.31 register 83h: inte rrupt status register 3 note: this is a read/write-to-clear register. the status bits are cleared on a write of one if the event causing the interrupt is no longer active. writing a zero to these bits has no effect. the interrupt status register 3 bits[1:0] are automa tically set by the device whenever a voltage event occurs on the vtr or vbat inputs. a voltage event occurs when any of these inputs violate the limits set in the corresponding limit registers. this register holds a set bit until the event is cleared by software or until the individual enable bit is cleared. once set, the interrupt status register 3 bi ts remain set until the individual enable bits is cleared, even if the voltage or tachometer reading no longer violate the limits set in the limit registers. note that clearing the group temp, fan, or volt enable bits or the global inten enable bit has no effect on the status bits. note: the individual enable bits for vtr and vbat are located in the interrupt enable 1 register at offset 7eh. this register is read only ? a write to this register has no effect. 24.2.32 registers 84h-88h: a/ d converter lsbs registers there is a 10-bit analog to digital converter (a dc) located in the hardware monitoring block that converts the measured voltages into 10-bit reading values. depending on the averaging scheme enabled (i.e., 16x averaging, 32x averaging, etc. ), the hardware monitor may take multiple readings and average them to create 12-bit reading values. the 8 msb?s of the reading values are placed in the reading registers. when the upper 8-bits loca ted in the reading registers are read the 4 lsb?s are latched into their respective bits in the a/d converter lsbs register. this give 12-bits of resolution register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 83h rwc 1 interrupt status 3 res res res res res res vbat vtr 00h bit name r/w default description 0 vtr_error r 0 the device automatically sets this bit to 1 when the vtr input voltage is less than or equal to the limit set in the vtr low limit register or greater than the limit set in the vtr high limit register. 1 vbat_error r 0 the device automatically sets this bit to 1 when the vbat input voltage is less than or equal to the limit set in the vbat low limit register or greater than the limit se t in the vbat high limit register. 2-7 reserved r 0 reserved register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 84h r a/d converter lsbs reg 5 vtr.3 vtr.2 vtr.1 vtr.0 vbt.3 vbt.2 vbt.1 vbt.0 n/a 85h r a/d converter lsbs reg 1 rd2.3 rd2 .2 rd2.1 rd2.0 rd1.3 rd1.2 rd1.1 rd1.0 n/a 86h r a/d converter lsbs reg 2 v12.3 v12.2 v12.1 v12.0 am.3 am.2 am.1 am.0 n/a 87h r a/d converter lsbs reg 3 v50.3 v5 0.2 v50.1 v50.0 v25.3 v25.2 v25.1 v25.0 n/a 88h r a/d converter lsbs reg 4 vcc.3 vcc.2 vcc.1 vcc.0 vcp.3 vcp.2 vcp.1 vcp.0 n/a
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 274 smsc sch311x datasheet with a minimum value of 1/16 th per unit measured. (i.e., temperature range: -127.9375 oc < temp < 127.9375 oc and voltage range: 0 < voltage < 256.9375). see the dc characteristics for the accuracy of the reading values. the eight most significant bits of the 12-bit averaged readings are stored in reading registers and compared with limit registers. the interrupt stat us register bits are asserted if the corresponding measured value(s) on the inputs violate their programmed limits. 24.2.33 registers registers 89h : smsc test register this is a read-only smsc test register. writing to this register has no effect on the hardware. 24.2.34 registers 8ah: smsc test register 24.2.35 registers 8bh: smsc test register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register must not be written. writing this register may produce unexpected results. 24.2.36 registers 8ch: smsc test register 24.2.37 registers 8dh: smsc test register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register must not be written. writing this register may produce unexpected results. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 89h r smsc test register 7 6 5 4 3 2 1 0n/a register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ah r smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8bh r/w smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ch r smsc test register res res res tst4 tst3 tst2 tst1 tst0 0eh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8dh r/w smsc test register res res res tst4 tst3 tst2 tst1 tst0 0eh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 275 revision 0.4 (06-03-05) datasheet 24.2.38 registers 8eh: smsc test register this register is an smsc test register. 24.2.39 registers 90h-92h: fantachx option registers these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. bit[0] slow 0= force tach reading register to ffffh if number of tach edges detected is greater than 0, but less than programmed number of edges. (default) 1=force tach reading register to fffeh if number of tach edges detected is greater than 0, but less than programmed number of edges. bit[2:1] the number of edges for tach reading: 00=2 edges 01=3 edges 10=5 edges (default) 11=9 edges bit[3] tachometer reading mode 0=mode 1 standard (default) 1=mode 2 enhanced. notes: unused fantach inputs must be configured for mode 1. tach inputs associated with pwm outputs that are configured for high frequency mode must be configured for mode 1. bit[4] 3 edge detection (mode 2 only) 0=don?t ignore first 3 edges (default) 1=ignore first 3 tachometer edges after guard time note: this bit has been added to support a small sampling of fans that emit irregular tach pulses when the pwm transitions ?on?. typically, the guard time is sufficient for most fans. bit[7:5] reserved register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8eh r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 n/a register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 90h r/w fantach1 option res res res 3edg mode edg1 edg0 slow 04h 91h r/w fantach2 option res res res 3edg mode edg1 edg0 slow 04h 92h r/w fantach3 option res res res 3edg mode edg1 edg0 slow 04h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 276 smsc sch311x datasheet 24.2.40 registers 94h-96h: pwmx option registers these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. bits[1:0] tachs reading registers associated with pwmx are updated: (mode 2 only) 00=once a second (default) 01=twice a second 1x=every 300msec bit[2] snap to zero (szen) this bit determines if the pwm output ramps down to off or if it is immediately set to zero. 0=step down the pwmx output to off at the programmed ramp rate 1=transition pwmx to off immediately when the calculated duty cycle is 00h (default) bit[4:3] guard time (mode 2 only) 00=63 clocks (90khz clocks ~ 700usec) 01=32 clocks (90khz clocks ~ 356usec) (default) 10=16 clocks (90khz clocks ~ 178usec) 11=8 clocks (90khz clocks ~ 89usec) bit[5] opportunistic mode enable 0= opportunistic mode disabled. update tach reading once per pwmx update period (see bits[1:0] in this register) 1=opportunistic mode is enabled. the tachometer reading register is updated any time a valid tachometer reading can be made during the ?on? time of the pwm output signal. if a valid reading is detected prior to the u pdate cycle, then the upda te counter is reset. bit[7:6] reserved 24.2.41 register 97h: smsc test register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 94h r/w pwm1 option res res opp grd1 grd0 szen updt1 updt0 0ch 95h r/w pwm2 option res res opp grd1 grd0 szen updt1 updt0 0ch 96h r/w pwm3 option res res opp grd1 grd0 szen updt1 updt0 0ch register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 97h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 5ah
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 277 revision 0.4 (06-03-05) datasheet this is an smsc test register. writing to this register may cause unwanted results. 24.2.42 register 98h: smsc test register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this is an smsc test register. writing to this register may cause unwanted results. 24.2.43 registers 99h-9ah:vo ltage reading registers see section 24.2.2, "registers 20-24h, 99-9ah: voltage reading," on page 248 . 24.2.44 registers 9b-9eh: voltage limit registers see pme_sts1. 24.2.45 register a3h: smsc test register this is an smsc test register. writing to this register may cause unwanted results. 24.2.46 register a4h: smsc test register this register is an smsc test register. 24.2.47 register a5h: interrupt status register 1 - secondary note 24.20 this is a read-only bit. writing ?1? to this bit has no effect. notes: this register is reset to its default value when the pwrgd_ps signal transitions high. this is a read/write-to-clear register. bits[6:4] ar e cleared on a write of one if the temperature event is no longer active. writing a zero to these bits has no effect. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 98h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 glitch f1h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value a3h r/w smsc test register tst7 ts t6 tst5 tst4 tst3 tst2 tst1 tst0 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value a4h r smsc test register tst7 ts t6 tst5 tst4 tst3 tst2 tst1 tst0 02h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value a5h r/wc interrupt status 1 - secondary int2 note 2 4.20 d2 amb d1 5v vcc vccp 2.5v 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 278 smsc sch311x datasheet see definition of register 41h: interrupt status register 1 on page 254 for setting and clearing bits. note: only the primary status registers generate an interrupt event. 24.2.48 register a6h: interrupt status register 2 - secondary notes: this register is reset to its default value when the pwrgd_ps signal transitions high. this is a read/write-to-clear register. the status bits in this register are cleared on a write of one if the event causing the interrupt is no longer active. writing a zero to these bits has no effect. see definition of register 42h: interrupt status register 2 on page 256 for setting and clearing bits. note: only the primary status registers generate an interrupt event. 24.2.49 register a7h: interrupt status register 3 - secondary notes: this register is reset to its default value when the pwrgd_ps signal transitions high. this is a read/write-to-clear register. the status bits in this register are cleared on a write of one if the event causing the interrupt is no longer active. writing a zero to these bits has no effect. see definition of register 83h: interrupt status register 3 on page 273 for setting and clearing bits. note: only the primary status registers generate an interrupt event. 24.2.50 register abh: tach 1-3 mode register the following defines the mode control bits: bits[7:6]: tach1 mode bits[5:4]: tach2 mode. bits[3:2]: tach3 mode. bits[1:0]: reserved. for bits[7:2], these bits are defined as follows: 00=normal operation (default) regis- ter address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value a6h r/wc interrupt status register 2 - secondary err2 err1 res fanta ch3 fanta ch2 fanta ch1 res 12v 00h regis- ter address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value a7h r/wc interrupt status register 3- secondary res res res res res res vbat vtr 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value abh r/w tach 1-3 mode t1m1 t1m0 t2m1 t2m0 t3m1 t3m0 res res 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 279 revision 0.4 (06-03-05) datasheet 01=locked rotor mode, active high signal 10=locked rotor mode, active low signal 11=undefined. for bits[1:0], these bi ts are defined as reserved. writes have no affect, reads return 00. 24.2.51 register adh: smsc test register this is a read-only smsc test register. writing to this register has no effect. 24.2.52 registers ae-afh, b3h: t op temperature limit registers note: these registers are reset to their default values when the powergood_ps signal transitions high. this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. the top temperature registers define the upper b ound of the operating temperature for each zone. if the temperature of the zone exceeds this va lue, the minimum temperature for the zone can be configured to be adjusted down. the top temperature registers are used as a comparison point for the amta feature, to determine if the low temp limit register for a zone should be adj usted down. the top temp register for a zone is not used if the amta feature is not enabled for the zone. the amta feature is enabled via the tmin adjust enable register at 0b7h. 24.2.53 register b4h: min temp ad just temp rd1, rd2 (zones 1& 3) this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. bits[7:4] are used to select the temperature adjustm ent values that are subtracted from the zone low temp limit for zones 1& 3. there is a 2-bit value for each of the remote zones that is used to program the value that is subtracted from the low temp limit temperature register when the temperature reading for the zone reaches the top temperature for the am ta feature. the amta feature is enabled via the tmin adjust enable register at b7h. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value adh r smsc test register 7 654321000h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value aeh r/w top temperature remote diode 1 (zone 1) 7 6 5 4321 0 2dh afh r/w top temperature remote diode 2 (zone 3) 7 6 5 4321 0 2dh b3h r/w top temperature ambient (zone 2) 7 6 5 4321 0 2dh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value b4h r/w min temp adjust temp rd1, rd2 (zones 1&3) r1at p1 r1at p0 r2at p1 r2at p0 res res res res 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 280 smsc sch311x datasheet these bits are defined as follows: zxatp[1:0]: 00=2oc (default) 01=4oc 10=6oc 11=8oc note: the zones are hardwired to the sensors in the following manner: r1atp[1:0] = zone 1 = remote diode 1 amatp[1:0] = zone 2 = ambient r2atp[1:0] = zone 3 = remote diode 2 24.2.54 register b5h: min temp ad just temp and delay amb (zone 2) this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. bits[5:4] min temp adjust for ambient temp sensor (zone 2) see register b4h: min temp adjust temp rd1, rd2 (zones 1& 3) on page 279 for a definition of the min temp adjust bits. bits[1:0] min temp adjust delay for ambient temp sensor (zone 2) see register b6h: min temp adjust delay rd1, rd2 (zone 1 & 3) register on page 280 for a definition of the min temp delay bits. 24.2.55 register b6h: min temp adjust delay rd1, rd2 (zone 1 & 3) register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. bits[7:4] are the bits to program the time delay for subsequently adjusting the low temperature limit value for zones 1&3 once an adjustment is made. these bits are defined as follows: rxad[1:0]: 00=1min (default) 01=2min 10=3min 11=4min note: the zones are hardwired to the sensors in the following manner: r1ad[1:0] = zone 1 = remote diode 1 amad[1:0] = zone 2 = ambient r2ad[1:0] = zone 3 = remote diode 2 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value b5h r/w min temp adjust temp and delay (zone 2) res res ama tp1 ama tp0 res res ama d1 ama d0 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value b6h r/w min temp adjust temp and delay rd1, rd2 (zones 1 & 3) r1 ad1 r1 ad0 r2 ad1 r2 ad0 res res res res 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 281 revision 0.4 (06-03-05) datasheet 24.2.56 register b7h: min te mp adjust enable register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register is used to enable the automatic mi nimum temperature adjustment (amta) feature for each zone. amta allows for an adjustment of the low temp limit temperature register for each zone when the current temperature for the zone exceeds the top temperature. bits[3:1] are used to enable an adjustment of the low temp limit for each of zones 1-3. this register also contains the bit (top_int_en) to enable an interrupt to be generated anytime the top temp for any zone is exceeded. this interrupt is generated based on a bit in the top temp exceeded status register (0b8h) being set. note t hat the int_en bit (register 7ch) must also be set for an interrupt to be generated on the therm pin. note: the zones are hardwired to the sensors in the following manner: tmin_ adj_ en1 = zone 1 = remote diode 1 tmin_ adj_ ena = zone 2 = ambient tmin_ adj_ en2 = zone 3 = remote diode 2 24.2.57 register b8h: top te mp exceeded status register note: this register is reset to its default value when the pwrgd_ps signal transitions high. the top temp exceeded status register bits are automatically set by the device whenever the temperature value in the reading register for a zone exceeds the value in the top temperature register for the zone. this register holds a bit set until the bit is written to 1 by software. the contents of this register are cleared (set to 0) automatically by the device after it is written by software, if the temperature no longer exceeds the value in the top temperature register for the zone. once set, the status bits remain set until written to 1, even if the if the temperature no longer exceeds the value in the top temperature register for the zone. note: if a bit is set in this register, an interrupt can be generated if the top_int_en bit (register b7h) and, for the nhwm_int pin to go active, the int_en bit (7ch) is set. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value b7h r/w tmin adjust enable res res res res tmin _ adj_ en2 tmin _ adj_ en1 tmin _ adj_ ena top_ int_ en 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value b8h r/wc top temp exceeded status res res res res res sts2 sts1 stsa 00h note: each bit in this register is cleared on a write of 1 if the event is not active.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 282 smsc sch311x datasheet 24.2.58 register bah: smsc reserved register this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. 24.2.59 register bbh: smsc reserved register this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. 24.2.60 register 0bdh: sm sc reserved register this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. 24.2.61 register bfh: smsc reserved register this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. 24.2.62 register c0h: smsc reserved register this is an smsc reserved bit. writing this bit to a value different than the default value may cause unwanted results. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value bah r/w smsc reserved res res res res res res res res 03h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value bbh r smsc reserved 7 6 5 4 3 2 1 0 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value bdh r smsc reserved 7 6 5 4 3 2 1 0 n/a register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value bfh r/w smsc reserved res res res res res res res res 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value c0h r/w smsc reserved res res res res res res res res 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 283 revision 0.4 (06-03-05) datasheet 24.2.63 register c1h: smsc reserved register thermtrip_ctrl: bit 1 in the thermtrip control register. may be enabled to assert the thermtrip# pin if programmed limits are exceeded as indicated by the thermtrip status register 1=enable, 0=disable (default). 24.2.64 registers c4-c5, c9h: thermtri p temperature limit zone registers these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. the nthermtrip pin can be configured to assert when one of the temperature zones is above its associated thermtrip temperature limit (thermtrip temp limit zones 1-3). the thermtrip temperature limit is a separate limit register from the high limit used for setting the interrupt status bits for each zone. the thermtrip temp limit zone 1-3 registers represent the upper temperature limit for asserting nthermtrip pin for each zone. these registers are defined as follows: if the monitored temperature for the zone exceeds the value set in the associated thermtrip temp limit zone 1-3 registers, the corresponding bit in the thermtrip status register will be set. the nthermtrip pin may or may not be set depending on the state of the associated enable bits (in the thermtrip output enable register). note: the zone must exceed the limits set in the associated thermtrip temp limit zone 1-3 register for two successive monitoring cycles in order for the nthermtrip pin to go active (and for the associated status bit to be set). 24.2.65 register cah: thermtrip status register note: this register is reset to its default value when the pwrgd_ps signal transitions high. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value c1h r/w thermtrip control res res res res res res therm trip_c trl res 01h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value c4h r/w thermtrip temp limit zone 1 (remote diode 1) 7 6 5 4321 0 7fh c9h r/w thermtrip temp limit zone 2 (ambient) 7 6 5 4321 0 7fh c5h r/w thermtrip temp limit zone 3 (remote diode 2) 7 6 5 4321 0 7fh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value cah r/wc thermtrip status res res res res res rd 2 rd 1 amb 00h note: each bit in this register is cleared on a write of 1 if the event is not active.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 284 smsc sch311x datasheet this register holds a bit set until the bit is written to 1 by software. the contents of this register are cleared (set to 0) automatically by the device after it is written by software, if the nthermtrip pin is no longer active. once set, the status bits remain set until written to 1, even if the nthermtrip pin is no longer active. bits[2:0] thermtrip zone status bits (one bit per zone). a status bit is set to ?1? if the associated zone temp exceeds the associated thermtrip temp limit register value. 24.2.66 register cbh: thermtrip output enable register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. bits[2:0] in thermtrip output enable register, thermtrip output enable bits (one bit per zone). each zone may be individually enabled to assert the nthermtrip pin if the zone temperature reading exceeds the associated thermtrip temp limit register value. 1=enable, 0=disable (default) 24.2.67 register ceh: smsc reserved register 24.2.68 registers d1,d6,dbh: pwm max segment registers these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. registers 0d1h, 0d6h and 0dbh are used to program the max pwm duty cycle for the fan function for each pwm. 24.2.69 register e0h: enable lsbs for auto fan register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value cbh r/w thermtrip output enable res res res res res rd2 rd1 amb 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value ceh r/w res res res res res rd2 _int _en rd1 _int _en amb _ int_ en 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 0d1h r/w pwm1 max 7 6 5 4321 0 ffh 0d6h r/w pwm2 max 7 6 5 4321 0 ffh 0dbh r/w pwm3 max 7 6 5 4321 0 ffh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value e0h r/w enable lsbs for autofan res res pwm3 _n1 pwm3 _n0 pwm2 _n1 pwm2 _n0 pwm1 _n1 pwm1 _n0 00h
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 285 revision 0.4 (06-03-05) datasheet bits[7:6] reserved bits[5:4] pwm3_n[1:0] bits[3:2] pwm2_n[1:0] bits[1:0] pwm1_n[1:0] the pwmx_n[1:0] configuration bits allow the autofan control logic to utilize the extended resolution bits in the temperature reading. increasing the pr ecision reduces the programmable temperature range that can be used to control the pwm outputs. fo r a description of the programmable temperature ranges see registers 5f-61h: zone temperature range, pwm frequency on page 261 . note: increasing the precision does not limit the range of temperature readings supported. the active region for the autofan control is bound by the minimum zone limit + range, where the minimum zone limit can be any integer value from -127 to +127 degrees. 24.2.70 registers e1h: smsc test register 24.2.71 registers e2h: smsc test register 24.2.72 registers e3h: smsc test register table 24.16 programming options for the pwmx_n[1:0] bits pwmx_n[1:0] degree of resolution per lsb used in autofan max theoretical temperature range supported max programmable temperature range supported 00 1 255 80 01 0.5 128.5 80 10 0.25 64.75 53.33 11 reserved reserved reserved register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ah r smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ah r smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 8ah r smsc test register res tst6 tst5 tst4 tst3 tst2 tst1 tst0 4dh
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 286 smsc sch311x datasheet 24.2.73 register e9-eeh: smsc test registers these are smsc test registers. writing to these registers may cause unwanted results. 24.2.74 register ffh: smsc test register this register is an smsc test register. register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value e9h r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h eah r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h ebh r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h ech r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h edh r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h eeh r/w smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 00h register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value ffh r smsc test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 n/a
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 287 revision 0.4 (06-03-05) datasheet chapter 25 config registers the configuration of the sch311x is very flexible and is based on the configuration architecture implemented in typical plug-and-play component s. the sch311x is designed for motherboard applications in which the resources required by thei r components are known. with its flexible resource allocation architecture, the sch311x allows the bios to assign resources at post. system elements primary configuration address decoder after a pci reset or vcc power on reset the sch311x is in the run mode with all logical devices disabled. the logical devices may be configured through two standard configuration i/o ports (index and data) by placing the sch311x into configuration mode. the bios uses these configuration ports to initialize the logical devices at post. the index and data ports are only valid when the sch311x is in configuration mode. strap options must be added to allow four configuration register base address options: 0x002e, 0x004e, 0x162e, or 0x164e. at the deasertting edge of pcirst# or vcc por the nrts1/sysopt0 pin is latched to determine the configuration base address: 0 = index base i/o address bits a[7:0]= 0x2e 1 = index base i/o address bits a[7:0]= 0x4e at the deasertting edge of pcirst# or vcc por the ndtr1/sysopt1 pin is latched to determine the configuration base address: 0 = index base i/o address bits a[15:8]= 0x16; 1 = index base i/o address bits a[15:8]= 0x00 the above strap options will allow the configuration access ports (config port, the index port, and data port) to be controlled by the nrts 1/sysopt0 and ndtr1/syso pt1 pins and by the configuration port base address registers at offset 0x26 and 0x27. the configuration base address at power-up is determined by the sysopt strap option. the sysopt strap option is latched state of the nrts1/sysopt0 and ndtr1/sysopt1 pins at the deasserting edge of pcirst#. the nrts1/sysopt0 pin determine s the lower byte of the base ad dress and the ndtr1/sysopt1 pin determines the upper byte of the base addres s. the following table summarizes the base configuration address selected by the sysopt strap option. application note: the nrts1/sysopt0 and the ndtr1/sysopt1 pins requires external pullup/pulldown resistors to set the default base i/o address for configuration to 0x002e, 0x004e, 0x162e, or 0x164e. note: an external pull-down resistor is required for th e base io address to be 0x02e for configuration. an external pull-up resistor is required to move the base io address for configuration to 0x04e. the index and data ports are effective only when the chip is in the configuration state. table 25.1 sysopt strap option configuration address select sysopt1 sysopt0 default config port/ index port address data port 1 0 0x002e index port + 1 1 1 0x004e 0 0 0x162e 0 1 0x164e
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 288 smsc sch311x datasheet note 25.1 the configuration port base address can be relocated through cr26 and cr27. entering the configuration state the device enters the configuration state when the following config key is successfully written to the config port. config key = <0x55> exiting the configuration state the device exits the configuration state when the following config key is successfully written to the config port. config key = <0xaa> configuration sequence to program the configuration registers, the following sequence must be followed: 1. enter configuration mode 2. configure the configuration registers 3. exit configuration mode. enter configuration mode to place the chip into the configuration state the config key is sent to the chip?s config port. the config key consists of 0x55 written to the config port. once the configuration key is received correctly the chip enters into the configuration state (the auto config ports are enabled). configuration mode the system sets the logical device information and ac tivates desired logical devices through the index and data ports. in configuration mode, the index port is located at the config port address and the data port is at index port address + 1. the desired configuration registers are accessed in two steps: 1. write the index of the logical device number configuration register (i.e., 0x07) to the index port and then write the number of the desired logical device to the data port 2. write the address of the desired configuration register within the logical device to the index port and then write or read the configurat ion register through the data port. note: if accessing the global configuration registers, step (a) is not required. exit configuration mode to exit the configurati on state the system writes 0xaa to the config port. the chip returns to the run state. note: only two states are defined (run and configuration). in the run state the chip will always be ready to enter the configuration state. programming example the following is an example of a configuration program in intel 8086 assembly language. ;----------------------------. ; enter configuration mode | ;----------------------------? mov dx,02eh mov ax,055h out dx,al ;----------------------------. ; configure register cre0, |
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 289 revision 0.4 (06-03-05) datasheet ; logical device 8 | ;----------------------------? mov dx,02eh mov al,07h out dx,al ;point to ld# config reg mov dx,02fh mov al, 08h out dx,al;point to logical device 8 ; mov dx,02eh mov al,e0h out dx,al; point to cre0 mov dx,02fh mov al,02h out dx,al; update cre0 ;-----------------------------. ; exit configuration mode | ;-----------------------------? mov dx,02eh mov ax,0aah out dx,al notes: : soft reset: bit 0 of configuration control register set to one. all host accesses are blocked for 500s after vcc por (see figure 29.1 power-up timing on page 366 .) 25.1 configurat ion registers the following table summarizes the logical device allocation for the different varieties of sch311x devices. table 25.2 sch311x logical device summary logical device sch3112 sch3114 sch3116 0 fdd fdd fdd 1 reserved reserved reserved 2 reserved reserved reserved 3 parallel port parallel port parallel port 4 serial port1 serial port1 serial port1 5 serial port 2 serial port 2 serial port 2 6 reserved reserved reserved 7 keyboard keyboard keyboard 8 reserved reserved reserved 9 reserved reserved reserved ah runtime registers runtime registers runtime registers bh reserved serial port3 serial port3 ch reserved serial port 4 serial port 4
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 290 smsc sch311x datasheet dh reserved reserved serial port 5 eh reserved reserved serial port 6 fh reserved reserved reserved table 25.3 configuration register summary index type pci reset vcc por vtr por soft reset configuration register global configuration registers 0x02 w 0x00 0x00 0x00 - config control 0x03 r - - - - reserved ? reads return 0 0x07 r/w 0x00 0x00 0x00 0x00 logical device number 0x20 r 0x7c- 0x7f 0x7c- 0x7f 0x7c- 0x7f 0x7c- 0x7f device id - hard wired sch3112 - 0x7c sch3114 - 0x7d reserved - 0x7e sch3116 - 0x7f 0x19 r/w - 0x00 0x00 - test8 0x21 r current revision device rev - hard wired 0x22 r/w 0x00 0x00 0x00 0x00 power control 0x23 r/w (pme_st s1) 0x00 0x00 0x00 - reserved 0x24 r/w 0x44 0x44 0x44 - osc 0x25 r/w - 0x00 0x00 - test9 0x26 r/w see pme_st s1 - - - configuration port address byte 0 (low byte) 0x27 r/w see pme_st s1 - - - configuration port address byte 1 (high byte) 0x28 r - - - - reserved 0x29 r/w - 0x00 0x00 - test 0x2a r/w - 0x00 0x00 - test 6 0x2b r/w - 0x00 0x00 - test 4 0x2c r/w - 0x00 0x00 - test 5 0x2d r/w - 0x00 0x00 - test 1 0x2e r/w - 0x00 0x00 - test 2 table 25.2 sch311x logical device summary (continued) logical device sch3112 sch3114 sch3116
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 291 revision 0.4 (06-03-05) datasheet 0x2f r/w - 0x00 0x00 - test 3 logical device 0 config uration registers (fdd) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x03 0x03 0x03 0x03 primary base i/o address high byte 0x61 r/w 0xf0 0xf0 0xf0 0xf0 primary base i/o address low byte 0x70 r/w 0x06 0x06 0x06 0x06 primary interrupt select 0x74 r/w 0x02 0x02 0x02 0x02 dma channel select 0xf0 r/w 0x0e 0x0e 0x0e - fdd mode register 0xf1 r/w 0x00 0x00 0x00 - fdd option register 0xf2 r/w 0xff 0xff 0xff - fdd type register 0xf4 r/w 0x00 0x00 0x00 - fdd0 0xf5 r/w 0x00 0x00 0x00 - fdd1 logical device 1 configur ation registers (reserved) logical device 2 configur ation registers (reserved) logical device 3 configurati on registers (parallel port) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0x74 r/w 0x04 0x04 0x04 0x04 dma channel select 0xf0 r/w 0x3c 0x3c 0x3c - parallel port mode register 0xf1 r/w 0x00 0x00 0x00 - parallel port mode register 2 logical device 4 configuration registers (serial port 1) 0x30 r/w 0x00 0x00 0x00 0x00 activate note 25.2 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 1 mode register table 25.3 configuration register summary (continued) index type pci reset vcc por vtr por soft reset configuration register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 292 smsc sch311x datasheet logical device 5 configuration registers (serial port 2) 0x30 r/w 0x00 0x00 0x00 0x00 activate note 25.2 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 2 mode register 0xf1 r/w 0x02 0x02 0x02 - ir options register 0xf2 r/w 0x03 0x03 0x03 - ir half duplex timeout logical device 6 configur ation registers (reserved) logical device 7 configura tion registers (keyboard) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select (keyboard) 0x72 r/w 0x00 0x00 0x00 0x00 secondary interrupt select (mouse) 0xf0 r/w 0x00 0x00 0x00 - kreset and gatea20 select logical device 8 configur ation registers (reserved) logical device 9 configur ation registers (reserved) logical device a configuration registers (runtime registers) 0x30 r/w 0x00 0x00 0x00 0x00 activate 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x62 r/w 0x00 0x00 0x00 0x00 secondary base i/o address high byte 0x63 r/w 0x00 0x00 0x00 0x00 secondary base i/o address low byte 0xf0 r/w - - 0x00 - clocki32 0xf1 r/w 0x00 0x00 0x00 0x00 fdc on pp mode register 0xf2 pme_st s1 0x04 0x04 0x04 - security key control register table 25.3 configuration register summary (continued) index type pci reset vcc por vtr por soft reset configuration register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 293 revision 0.4 (06-03-05) datasheet logical device b configuratio n registers (serial port 3) sch3114, sch3116 devices only reserved in sch3112 device 0x30 r/w 0x00 0x00 0x00 0x00 activate note 25.2 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 3 mode register logical device c configuratio n registers (serial port 4) sch3114, sch3116 devices only reserved in sch3112 device 0x30 r/w 0x00 0x00 0x00 0x00 activate note 25.2 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 4 mode register logical device d configuratio n registers (serial port 5) sch3116 device only reserved in sch3112 and sch3114 devices 0x30 r/w 0x00 0x00 0x00 0x00 activate note 25.2 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select 0xf0 r/w 0x00 0x00 0x00 - serial port 5 mode register logical device e configuratio n registers (serial port 6) sch3116 device only reserved in sch3112 and sch3114 devices 0x30 r/w 0x00 0x00 0x00 0x00 activate note 25.2 0x60 r/w 0x00 0x00 0x00 0x00 primary base i/o address high byte 0x61 r/w 0x00 0x00 0x00 0x00 primary base i/o address low byte 0x70 r/w 0x00 0x00 0x00 0x00 primary interrupt select table 25.3 configuration register summary (continued) index type pci reset vcc por vtr por soft reset configuration register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 294 smsc sch311x datasheet note 25.2 serial ports 1 and 2 may be placed in th e powerdown mode by clearing the associated activate bit located at cr30 or by clearing the associated po wer bit located in the power control register at cr22. serial ports 3, 4,5,6 (if available) may be placed in the powerdown mode by clearing the associated activate bit located at cr30. when in the powerdown mode, the serial port outputs are tristated. in cases where the serial port is multiplexed as an alternate function, the corres ponding output will only be tristated if the serial port is the selected alternate function. 25.1.1 global config registers the chip-level (global) registers lie in the address range [0x00-0x2f]. the design must use all 8 bits of the address port for register selection. all uni mplemented registers and bits ignore writes and return zero when read. the index port is used to select a configuration register in the chip. the data port is then used to access the selected register. these registers are accessible only in the configuration mode. 0xf0 r/w 0x00 0x00 0x00 - serial port 6 mode register logical device f configura tion registers (reserved) table 25.4 chip-level (globa l) configuration registers register address description chip (global) cont rol registers 0x00 - 0x01 reserved - writes are ignored, reads return 0. config control default = 0x00 on vcc por, vtr por and pci reset 0x02 w the hardware automatically clears this bit after the write, there is no need for software to clear the bits. bit 0 = 1: soft reset. refer to the table 25.3, ?configuration register summary,? on page 290 for the soft reset value for each register. 0x03 - 0x06 reserved - writes are ignored, reads return 0 . logical device # default = 0x00 on vcc por, vtr por, soft reset and pci reset 0x07 r/w a write to this register sele cts the current logical device. this allows access to the control and configuration registers for each logical device. note: the activate command operates only on the selected logical device. reserved 0x08 - 0x18, 0x1a-0x1f reserved - writes are ig nored, reads return 0 . chip-level, smsc defined table 25.3 configuration register summary (continued) index type pci reset vcc por vtr por soft reset configuration register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 295 revision 0.4 (06-03-05) datasheet device id - hard wired default = 0x7c on vcc por, vtr por, soft reset and pci reset 0x20 r a read only register which provides device identification. device rev hard wired = current revision 0x21 r a read only register which provides device revision information. bits[7:0] = current revision when read. power control default = 0x00 on vcc por, vtr por, soft reset and pci reset 0x22 r/w bit[0] fdc power bit[1] reserved bit[2] reserved bit[3] parallel port power bit[4] serial port 1 power bit[5] serial port 2 power bit[6] reserved bit[7] reserved 0: power off or disabled 1: power on or enabled reserved default = 0x00 on vcc por, vtr por and pci reset 0x23 r/w reserved. this is a read/write register. writing to this register may cause unwanted results. osc default = 0x44, on on vcc por, vtr por and pci reset 0x24 r/w bit[0] reserved bit [1] pll control = 0 pll is on (backward compatible) = 1 pll is off bits[3:2] osc = 01 osc is on, brg clock is on. = 10 same as above (01) case. = 00 osc is on, brg clock enabled. = 11 osc is off, brg clock is disabled. bit [5:4] reserved, set to zero bit [6] 16-bit address qualification = 0 12-bit address qualification = 1 16-bit address qualification note: for normal operation, bit 6 should be set. bit[7] reserved configuration address byte 0 default =0x002e (sysopt01=10) =0x004e (sysopt01=11) on vcc por and pci reset 0x26 bit[7:1] configuration address bits [7:1] bit[0] = 0 ( note 25.3 ) configuration address byte 1 default =0x162e (sysopt01=00) =0x164e (sysopt01=01) on vcc por and pci reset 0x27 bit[7:0] configuration address bits [15:8] ( note 25.3 ) table 25.4 chip-level (global) configuration registers (continued) register address description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 296 smsc sch311x datasheet note 25.3 to allow the selection of the configuration address to a user defined location, these configuration address bytes are used. ther e is no restriction on the address chosen, except that a0 is 0, that is, the address must be on an even byte boundary. as soon as both bytes are changed, the configuration space is moved to the specified location with no delay ( note: write byte 0, then byte 1; writing cr27 changes the base address). the configuration address is only reset to its default address upon a pci reset or vcc por. note: the default configuration address is either 02e h or 04eh, as specified by the sysopt pin. 25.1.2 test registers the following test registers are used in the sch311x devices. default = 0x00 on vcc por, soft reset and pci reset 0x28 bits[7:0] reserved - writes are ignored, reads return 0. table 25.5 test register summary test 8 default = 0x00, on vcc por and vtr por 0x19 r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 9 default = 0x00, on vcc por and vtr por 0x25 r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test default = 0x00 note on vtr_por bit0/7 are reset bit1-6 reset on tst_porb from resgen block 0x29 r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 6 default = 0x00, on vcc por and vtr por 0x2a r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 4 default = 0x00, on vcc por and vtr por 0x2b r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 5 default = 0x00, on vcc por and vtr por 0x2c r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. table 25.4 chip-level (global) configuration registers (continued) register address description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 297 revision 0.4 (06-03-05) datasheet logical device conf iguration/control re gisters [0x30-0xff] used to access the registers that are assigned to each logical unit. this chip supports six logical units and has eight sets of logical device registers. the eight logical devices are floppy, parallel, serial 1, serial 2, keyboard controller, and runtime registers. a separate set (bank) of control and configuration registers exists for each logical device and is selected with the logical device # register (0x07). the index port is used to select a specific l ogical device register. these registers are then accessed through the data port. the logical device registers are accessible only wh en the device is in the configuration state. the logical register addresses are shown in ta b l e 2 5 . 6 . test 1 default = 0x00, on vcc por and vtr por 0x2d r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 2 default = 0x00, on vcc por and vtr por 0x2e r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. test 3 default = 0x00, on vcc por and vtr por 0x2f r/w test modes: reserved for smsc. users should not write to this register, may produce undesired results. table 25.6 logical device registers logical device register address description activate ( note 25.4 ) default = 0x00 on vcc por, vtr por, pci reset and soft reset (0x30) bits[7:1] reserved, set to zero. bit[0] = 1 activates the logical device currently selected through the logical device # register. = 0 logical device currently selected is inactive logical device control (0x31-0x37) reserved ? writes are ignored, reads return 0. logical device control (0x38-0x3f) vendor define d - reserved - writes are ignored, reads return 0. memory base address (0x40-0x5f) reserved ? writes are ignored, reads return 0. i/o base address ( note 25.5 ) (see table 25.7, ?base i/o range for logical devices,? on page 299 ) default = 0x00 on vcc por, vtr por, pci reset and soft reset (0x60-0x6f) 0x60,2,... = addr[15:8] 0x61,3,... = addr[7:0] registers 0x60 and 0x61 set the base address for the device. if more than one base address is required, the second base address is set by registers 0x62 and 0x63. refer to table 25.7 on page 299 for the number of base address registers used by each device. unused registers will ignore writes and return zero when read. table 25.5 test register summary (continued)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 298 smsc sch311x datasheet note 25.4 a logical device will be active and powered up according to the following equation unless otherwise specified: device on (active) = (activate bi t set or pwr/control bit set). the logical device?s activate bit and its pwr/control bit are linked such that setting or clearing one sets or clears the other. note 25.5 if the i/o base addr of the logical device is not within the base i/o range as shown in the logical device i/o map, then read or write is not valid and is ignored. note 25.6 the default value of the primary interrupt select register for logical device 0 is 0x06. note 25.7 the default value of the dma channel select register for logical device 0 (fdd) is 0x02 and for logical device 3 and 5 is 0x04. interrupt select defaults: 0x70 = 0x00 or 0x06 ( note 25.6 ) on vcc por, vtr por, pci reset and soft reset 0x72 = 0x00, on vcc por, vtr por, pci reset and soft reset (0x70,0x72) 0x70 is implemented for each logical device. refer to interrupt configuration register description. only the keyboard controller uses interrupt select register 0x72. unused register (0x72) will igno re writes and return zero when read. interrupts default to edge high (isa compatible). (0x71,0x73) reserved - not implemented. these register locations ignore writes and return zero when read. dma channel select default = 0x02 or 0x04 ( note 25.7 ) on vcc por, vtr por, pci reset and soft reset (0x74,0x75) only 0x74 is implemented for fdc and parallel port. 0x75 is not implemented and ignores writes and returns zero when read. refer to dma channel configuration. 32-bit memory space configuration (0x76-0xa8) reserved - not implemented. these register locations ignore writes and return zero when read. logical device (0xa9-0xdf) reserved - not implemented. these register locations ignore writes and return zero when read. logical device configuration (0xe0-0xfe) reserved ? vendor defined (see smsc defined logical device configuration registers). reserved 0xff reserved table 25.6 logical device registers (continued) logical device register address description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 299 revision 0.4 (06-03-05) datasheet table 25.7 base i/o range for logical devices logical device number logical device register index base i/o range (note e.10) fixed base offsets 0x00 fdc 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : sra +1 : srb +2 : dor +3 : tdr +4 : msr/dsr +5 : fifo +7 : dir/ccr 0x01 reserved n/a n/a n/a 0x02 reserved n/a n/a n/a 0x03 parallel port 0x60,0x61 [0x0100:0x0ffc] on 4 byte boundaries (epp not supported) or [0x0100:0x0ff8] on 8 byte boundaries +0 : data/ecpafifo +1 : status +2 : control +400h : cfifo/ecpdfifo/tfifo/cnfga +401h : cnfgb +402h : ecr (all modes supported, epp is only available when the base address is on an 8-byte boundary) +3 : epp address +4 : epp data 0 +5 : epp data 1 +6 : epp data 2 +7 : epp data 3 0x04 serial port 1 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x05 serial port 2 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x06 reserved n/a n/a n/a 0x07 kybd n/a not relocatable fixed base address: 60,64 +0 : data register +4 : command/status reg. 0x08 reserved n/a n/a n/a 0x09 reserved n/a n/a n/a 0x0a runtime register block 0x60,0x61 [0x0000:0x0f7f] on 128-byte boundaries +00 : pme status . . . +5f : keyboard scan code (see table 26.2, ?runtime register por summary,? on page 315 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 300 smsc sch311x datasheet note 25.8 this chip uses address bits [a11:a0] to decode the base address of each of its logical devices. this device performs 16 bit address qual ification, therefore address bits [a15:a12] must be ?0?. note 25.9 the configuration port is at either 0x 02e or 0x04e (for sysopt=0 or sysopt=1) at power up and can be relocated via cr12 and cr13. security key register 0x62, 0x63 [0x0000:0x0fdf on 32-byte boundaries +00 : security key byte 0 . . . +1f: security key byte 31 0x0b serial port 3 sch3114 and sch3116 devices only reserved in sch3112 device 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x0c serial port 4 sch3114 and sch3116 devices only reserved in sch3112 device 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x0d serial port 5 sch3116 device only reserved in sch3112 and sch3114 devices 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr 0x0e serial port 6 sch3116 device only reserved in sch3112 and sch3114 devices 0x60,0x61 [0x0100:0x0ff8] on 8 byte boundaries +0 : rb/tb/lsb div +1 : ier/msb div +2 : iir/fcr +3 : lcr +4 : msr +5 : lsr +6 : msr +7 : scr config. port config. port 0x26, 0x27 ( note 25.9 ) 0x0100:0x0ffe on 2 byte boundaries see description configuration register summary and description. accessed through the index and data ports located at the configuration port address and the configuration port address +1 respectively. table 25.7 base i/o range for logical devices (continued) logical device number logical device register index base i/o range (note e.10) fixed base offsets
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 301 revision 0.4 (06-03-05) datasheet notes: : an interrupt is activated by setting the interrupt request level select 0 register to a non-zero value and: - for the fdc logical device by setting dmaen, bit d3 of the digital output register. - for the pp logical device by setting irqe, bit d4 of the control port and in addition - for the pp logical device in ecp mode by clearing serviceintr, bit d2 of the ecr. - for the serial port logical device by setting any combination of bits d0-d3 in the ier and by setting the out2 bit in the uart's modem control (mcr) register. - for the kybd logica l device (refer to chapter 12, "8042 keyboard controller description," on page 147 ). irqs are disabled if not used/selected by any logical device. refer to note 25.11 on page 302 . nsmi must be disabled to use irq2. all irq?s are available in serial irq mode. note 25.10 the default value of the primary interrupt select register for logical device 0 is 0x06. notes: a dma channel is activated by setting the dma channel select register to [0x01-0x03] and : for the fdc logical device by setting dmaen, bit d3 of the digital output register. table 25.8 primary interrupt select register name reg index definition primary interrupt select default=0x00 or 0x06 ( note 25.10 ) on vcc por, vtr por, pci reset and soft reset 0x70 (r/w) bits[3:0] selects which interrupt is used for the primary interrupt. 0x00= no interrupt selected 0x01= irq1 0x02= irq2/nsmi 0x03= irq3 0x04= irq4 0x05= irq5 0x06= irq6 0x07= irq7 0x08= irq8 0x09= irq9 0x0a= irq10 0x0b= irq11 0x0c= irq12 0x0d= irq13 0x0e= irq14 0x0f= irq15 notes: 1. all interrupts are edge high (except ecp/epp) 2. nsmi is active low table 25.9 dma channel select name reg index definition dma channel select default=0x02 or 0x04 (see notes) on vcc por, vtr por, pci reset and soft reset 0x74 (r/w) bits[2:0] select the dma channel. 0x00= reserved 0x01= dma1 0x02= dma2 0x03= dma3 0x04-0x07= no dma active
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 302 smsc sch311x datasheet for the pp logical device in ecp mode by setting dmaen, bit d3 of the ecr. the dma channel must be disabled if not used/selected by any logical device. refer to note a. the default value of the dma channel select register for logical device 0 (fdd) is 0x02 and for logical device 3 and 5 is 0x04. the fdc must always be assigned to dma channel 2. note 25.11 logical device irq and dma operation. irq and dma enable and disable: any time the irq or dma channel for a logical block is disabl ed by a register bit in that logical block, the irq and/or dma channel must be disabled. this is in addition to the irq and dma channel disabled by the configuration regi sters (active bit or address not valid). fdc: for the following cases, the irq and dma channel used by the fdc are disabled. digital output register (base+2) bit d3 (dmaen) set to ?0?. the fdc is in power down (disabled). serial ports: modem control register (mcr) bit d2 (out2) - when ou t2 is a logic ?0?, the serial port interrupt is disabled. disabling dma enable bit, disables dma for uart2. refer to the ircc specification. parallel port: spp and epp modes: control port (base+2) bit d4 (irqe) set to ?0?, irq is disabled. ecp mode: (dma) dmaen from ecr register. see table. irq - see table. keyboard controller: refer to the 8042 keyboard controller description on page 147 of this document. smsc defined logical device configuration registers the smsc specific logical device configuration registers reset to their default values only on pci resets generated by vcc or vtr por (a s shown) or the pci_reset # signal. these registers are not affected by soft resets. mode (from ecr register) irq controlled by dma controlled by 000 printer irqe dmaen 001 spp irqe dmaen 010 fifo (on) dmaen 011 ecp (on) dmaen 100 epp irqe dmaen 101 res irqe dmaen 110 test (on) dmaen 111 config irqe dmaen
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 303 revision 0.4 (06-03-05) datasheet table 25.10 floppy disk controller, logical device 0 [logical device number = 0x00 name reg index definition fdd mode register default = 0x0e on vcc por, vtr por and pci reset 0xf0 r/w bit[0] floppy mode = 0 normal floppy mode (default) = 1 enhanced floppy mode 2 (os2) bit[1] fdc dma mode = 0 burst mode is enabled = 1 non-burst mode (default) bit[3:2] interface mode = 11 at mode (default) = 10 (reserved) = 01 ps/2 = 00 model 30 bit[4] reserved (read/write bit) bit[5] reserved, set to zero bit[6] fdc output type control = 0 fdc outputs are od12 open drain (default) = 1 fdc outputs are o12 push-pull bit[7] fdc output control = 0 fdc outputs active (default) = 1 fdc outputs tri-stated fdd option register default = 0x00 on vcc por, vtr por and pci reset 0xf1 r/w bit[0] forced write protect = 0 inactive (default) = 1 fdd nwrtprt input is forced active when either of the drives has been selected. nwrtprt (to the fdc core) = wp (fdc sra register, bit 1) = (nds0 and forced write protect) or (nds1 and forced write protect) or nwrtprt (from the fdd interface) or floppy write protect notes: the floppy write protect bit is in the device disable register. boot floppy is always drive 0. bit[1] reserved bits[3:2] density select = 00 normal (default) = 01 normal (reserved for users) = 10 1 (forced to logic ?1?) = 11 0 (forced to logic ?0?) bit[7:4] reserved. (read/write bits) fdd type register default = 0xff on vcc por, vtr por and pci reset 0xf2 r/w bits[1:0] floppy drive a type bits[3:2] floppy drive b type bits[5:4] reserved (could be used to store floppy drive c type) bits[7:6] reserved (could be used to store floppy drive d type) note: the sch311x supports two floppy drives 0xf3 r reserved, read as 0 (read only) fdd0 default = 0x00 on vcc por, vtr por and pci reset 0xf4 r/w bits[1:0] drive type select: dt1, dt0 bits[2 read as 0 (read only) bits[4:3] data rate table select: drt1, drt0 bits[5] read as 0 (read only) bits[6] precompensation disable pts =0 use precompensation =1 no precompensation bits[7] read as 0 (read only) fdd1 0xf5 r/w refer to definition and default for 0xf4
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 304 smsc sch311x datasheet table 25.11 parallel port, logical device 3 [logical device number = 0x03] name reg index definition pp mode register default = 0x3c on vcc por, vtr por and pci reset 0xf0 r/w bits[2:0] parallel port mode = 100 printer mode (default) = 000 standard and bi-directional (spp) mode = 001 epp-1.9 and spp mode = 101 epp-1.7 and spp mode = 010 ecp mode = 011 ecp and epp-1.9 mode = 111 ecp and epp-1.7 mode bit[6:3] ecp fifo threshold 0111b (default) bit[7] pp interrupt type not valid when the parallel port is in the printer mode (100) or the standard & bi-directional mode (000). = 1 pulsed low, released to high-z. = 0 irq follows nack when parallel port in epp mode or [printer, spp, epp] under ecp. irq level type when the paralle l port is in ecp, test, or centronics fifo mode. pp mode register 2 default = 0x00 on vcc por, vtr por and pci reset 0xf1 r/w bit [3:0] reserved. set to zero. bit [4] timeout_select = 0 tmout (epp status reg.) cleared on write of ?1? to tmout. = 1 tmout cleared on trailing edge of read of epp status reg. bits[7:5] reserved. set to zero. table 25.12 serial port 1, logical de vice 4 [logical device number = 0x04 name reg index definition serial port 1 mode register default = 0x00 on vcc por, vtr por and pci reset 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[5:4] reserved, set to zero bit[6] all share irq =0 use bit 7 to determine sharing =1 share all serial ports on the sch311x device. sch3112 - share 2 serial ports sch3114 - share 4 serial ports sch3116 - share 6 serial ports bit[7]: share irq =0 uarts 1,2 use different irqs =1 uarts 1,2 share a common irq ( note 25.12 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 305 revision 0.4 (06-03-05) datasheet note 25.12 to properly share and irq: 1. configure uart1 (or uart2) to use the desired irq. 2. configure uart2 (or uart1) to use no irq selected. 3. set the share irq bit. note: if both uarts are configured to use different irqs and the share irq bit is set, then both of the uart irqs will assert when either uart generates an interrupt. note 25.13 the txd2_mode bit is a vtr powered bit that is reset on vtr por only. table 25.13 serial port 2. logical device 5 [logical device number = 0x05] name reg index definition serial port 2 mode register default = 0x00 on vcc por, vtr por and pci reset 0xf0 r/w bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[4] reserved, set to zero bit[5] txd2_mode (see note 25.13 .) =0 txd2 pin reflects current configuration state =1 override current pin configuration and force txd2 pin tristate. bits[7:6] reserved. set to zero. ir option register default = 0x02 on vcc por, vtr por and pci reset 0xf1 r/w bit[0] receive polarity = 0 active high (default) = 1 active low bit[1] transmit polarity = 0 active high = 1 active low (default) bit[2] duplex select = 0 full duplex (default) = 1 half duplex bits[5:3] ir mode = 000 standard com functionality (default) = 001 irda = 010 ask-ir = 011 reserved = 1xx reserved bit[6] reserved set to 0. bit[7] reserved, write 0. ir half duplex timeout default = 0x03 on vcc por, vtr por and pci reset 0xf2 bits [7:0] these bits set the half duplex time-out for the ir port. this value is 0 to 10msec in 100usec increments. 0= blank during transmit/receive 1= blank during transmit/receive + 100usec
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 306 smsc sch311x datasheet table 25.14 kybd. logical device 7 [logical device number = 0x07] name reg index definition krst_ga20 default = 0x00 on vcc por, vtr por and pci reset bits[6:5] reset on vtr por only 0xf0 r/w kreset and gatea20 select bit[7] polarity select for p12 = 0 p12 active low (default) = 1 p12 active high bit[6] m_iso. enables/disables isolation of mouse signals into 8042. does not affect mdat signal to mouse wakeup (pme) logic. 1= block mouse clock and data signals into 8042 0= do not block mouse clock and data signals into 8042 bit[5] k_iso. enables/disables isolation of keyboard signals into 8042. does not affect kdat signal to keyboard wakeup (pme) logic. 1= block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 bit[4] mlatch = 0 mint is the 8042 mint anded with latched mint (default) = 1 mint is the latched 8042 mint bit[3] klatch = 0 kint is the 8042 kint anded with latched kint (default) = 1 kint is the latched 8042 kint bit[2] port 92 select = 0 port 92 disabled = 1 port 92 enabled bit[1] reserved (read/write bit) bit[0] reserved (read/write bit) table 25.15 logical device a [logical device number = 0x0a] name reg index definition clocki32 default = 0x00 on vtr por 0xf0 (r/w) bit[0] (clk32_prsn) 0 = 32khz clock is connected to the clki32 pin (default) 1 = 32khz clock is not connected to the clki32 pin (pin is grounded) bit[1] spekey_en. this bit is used to turn the logic for the ?wake on specific key? featur e on and off. it will disable the 32khz clock input to the logic when turned off. the logic will draw no power when disabled. 0 = ?wake on specific key? logic is on (default) 1 = ?wake on specific key? logic is off bit[2] reserved (read-only bit) reads return 0. writes have no effect. bit[3] spemse_en this bit is used to turn the logic for the ?wake on specific mouse click? feature on and off. it will disable the 32 khz clock input to the logic when turned off. the logic will draw no power when disabled. 0 = ?wake on specific mouse click? logic is on (default) 1 = ?wake on specific mouse click? logic is off bits[7:4] are reserved fdc on pp mode register default = 0x00 on vcc por, vtr por and pci reset 0xf1 r/w fdc on pp mode register bit [1:0] parallel port fdc 00=normal pp and fdc mode 01 =mode 1 - drive 0 on fdc, drive 1 on pp 10 = mode 2 - drive 0/1 on pp 11 = reserved bits[7:3] reserved. set to zero.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 307 revision 0.4 (06-03-05) datasheet note: the registers located in logical device a are runtime registers. security key control (skc) register default=0x04 on a vtr por, vcc por, pci reset 0xf2 r/w when bit[0]= 0 read-only when bit[0]=1 bit[0] skc register lock this bit blocks write access to th e security key control register. 0 = security key control register is a read/write register (default) 1 = security key control register is a read-only register bit[1] read-lock this bit prevents reads from the security key registers located at an offset from the secondary base i/o address in logical device a 0 = permits read operations in the security key block (default) 1 = prevents read operations in the security key block (reads return 00h.) bit[2] write-lock this bit prevents writes to the security key registers located at an offset from the secondary base i/o address in logical device a 0 = permits write operations in the security key block 1 = prevents write operations in the security key block (default) bit[3] reserved bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved table 25.16 serial port 3, logical device b [logical device number = 0x0b name reg index definition serial port 3 mode register default = 0x00 on vcc por, vtr por and pci reset sch3112 device. 0xf0 r/w bit[7:0] smsc test bit must be written with zero for proper operation. serial port 3 mode register default = 0x00 on vcc por, vtr por and pci reset sch3114 and the sch3116 device. 0xf0 r/w sch 3114, sch3116 devices bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[5:4] reserved, set to zero bit[6] smsc test bit must be written with zero for proper operation. bit[7]: share irq =0 uarts 3,4 use different irqs =1 uarts 3,4 share a common irq ( note 25.12 ) table 25.15 logical device a [logical device number = 0x0a] (continued) name reg index definition
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 308 smsc sch311x datasheet table 25.17 serial port 4, logical device c logical device number = 0x0c name reg index definition serial port 4 mode register default = 0x00 on vcc por, vtr por and pci reset sch3112 device. 0xf0 r/w sch3112 device bit[7:0] smsc test bit must be written with zero for proper operation. serial port 4 mode register default = 0x00 on vcc por, vtr por and pci reset note: this register will only be used for the sch3114 and the sch3116 device. 0xf0 r/w sch 3114, sch3116 devices bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[5:4] reserved, set to zero bit[7:6] smsc test bit must be written with zero for proper operation. table 25.18 serial port 5, logical de vice d [logical device number = 0x0d] name reg index definition serial port 5 mode register default = 0x00 on vcc por, vtr por and pci reset sch3112 and sch3114 devices. 0xf0 r/w sch3112, sch3114 devices bit[7:0] smsc test bit must be written with zero for proper operation.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 309 revision 0.4 (06-03-05) datasheet serial port 5 mode register default = 0x00 on vcc por, vtr por and pci reset sch3116 device 0xf0 r/w sch3116 devices bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[5:4] reserved, set to zero bit[6] smsc test bit must be written with zero for proper operation. bit[7]: share irq =0 uarts 5,6 use different irqs =1 uarts 5,6 share a common irq ( note 25.12 ) table 25.19 serial port 6, logical device e logical device number = 0x0e name reg index definition serial port 6 mode register default = 0x00 on vcc por, vtr por and pci reset sch3112 and sch3114 devices 0xf0 r/w sch3112, sch3114 devices bit[7:0] smsc test bit must be written with zero for proper operation.n. serial port 6 mode register default = 0x00 on vcc por, vtr por and pci reset sch3116 device 0xf0 r/w sch3116 devices bit[0] midi mode = 0 midi support disabled (default) = 1 midi support enabled bit[1] high speed = 0 high speed disabled(default) = 1 high speed enabled bit [3:2] enhanced frequency select = 00 standard mode (default) = 01 select 921k = 10 select 1.5m = 11 reserved bit[5:4] reserved, set to zero bit[7:6] smsc test bit must be written with zero for proper operation. table 25.18 serial port 5, logical device d [logical device number = 0x0d] (continued) name reg index definition
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 310 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 311 revision 0.4 (06-03-05) datasheet chapter 26 runtime register 26.1 runtime register the following registers are runtime registers in the sch311x. they are located at the address programmed in the base i/o address in logical device a (also referred to as the runtime register) at the offset shown. these registers are powered by vtr. table 26.1 summarizes the runtime register differences between the 311x family of devices. table 26.2 gives the por information for each of the registers. a complete description of each of the registers is given in section 26.2, "runtime register description," on page 321 . table 26.1 sch311x runtime register summary register offset (hex) sch3112 register sch3114 register sch3116 register 00 pme_sts pme_sts pme_sts 01 reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 02 pme_en pme_en pme_en 03 reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 04 pme_sts1 pme_sts1 pme_sts1 05 pme_sts3 pme_sts3 pme_sts3 06 pme_sts5 ( note 26.1 )pme_sts5 ( note 26.1 ) pme_sts5 ( note 26.1 ) 07 pme_sts6 pme_sts6 pme_sts6 ( note 26.2 ) 08 pme_en1 pme_en1 pme_en1 09 pme_en3 pme_en3 pme_en3 0a pme_en5 pme_en5 pme_en5 0b pme_en6 pme_en6 pme_en6 ( note 26.2 ) 0c pme_sts7 ( note 26.3 )pme_sts7 ( note 26.3 ) pme_sts7 ( note 26.3 ) 0d reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 0e reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 0f reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 10 pme_en7 ( note 26.3 )pme_en7 ( note 26.3 )pme_en7 ( note 26.3 ) 11 reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 12 sp12 sp12 sp12 13 reserved ? reads return 0 sp34 sp34 14 smi_sts1 smi_sts1 smi_sts1 15 smi_sts2 smi_sts2 smi_sts2 16 smi_sts3 smi_sts3 smi_sts3
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 312 smsc sch311x datasheet 17 smi_sts4 ( note 26.4 ) smi_sts4 ( note 26.4 ) smi_sts4 ( note 26.4 ) 18 smi_en1 smi_en1 smi_en1 19 smi_en2 smi_en2 smi_en2 1a smi_en3 smi_en3 smi_en3 1b smi_en4 ( note 26.4 ) smi_en4 ( note 26.4 ) smi_en4 ( note 26.4 ) 1c msc_sts msc_sts msc_sts 1d resgen resgen resgen 1e force disk change force disk change force disk change 1f floppy data rate select shadow floppy data rate select shadow floppy data rate select shadow 20 uart1 fifo control shadow uart1 fifo control shadow uart1 fifo control shadow 21 uart2 fifo control shadow uart2 fifo control shadow uart2 fifo control shadow 22 reserved - read returns 0 uart3 fifo control shadow uart3 fifo control shadow 23 gp10 gp10 ( note 26.6 ) gp10 ( note 26.6 ) 24 gp11 gp11 ( note 26.6 ) gp11 ( note 26.6 ) 25 gp12 gp12 ( note 26.6 ) gp12 ( note 26.6 ) 26 gp13 gp13 ( note 26.6 ) gp13 ( note 26.6 ) 27 gp14 gp14 ( note 26.6 ) gp14 ( note 26.6 ) 28 reserved - reads return 0 uart4 fifo control shadow uart4 fifo control shadow 29 gp15 gp15 ( note 26.6 )gp15 ( note 26.6 ) 2a gp16 gp16 ( note 26.6 )gp16 ( note 26.6 ) 2b gp17 gp17 ( note 26.6 )gp17 ( note 26.6 ) 2c gp21 gp21 gp21 2d gp22 gp22 gp22 2e reserved - reads return 0 reserved - reads return 0 uart5 fifo control shadow 2f reserved - reads return 0 reserved - reads return 0 uart6 fifo control shadow 30 reserved - reads return 0 reserved - reads return 0 sp5 option 31 reserved - reads return 0 reserved - reads return 0 sp6 option 32 gp27 gp27 gp27 33 gp30 gp30 gp30 34 gp31 gp31( note 26.6 )gp31( note 26.6 ) 35 gp32 gp32 gp32 table 26.1 sch311x runtime register summary (continued) register offset (hex) sch3112 register sch3114 register sch3116 register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 313 revision 0.4 (06-03-05) datasheet 36 gp33 gp33 gp33 37 gp34 gp34 ( note 26.6 )gp34 ( note 26.6 ) 38 reserved reserved reserved 39 gp36 gp36 gp36 3a gp37 gp37 gp37 3b gp40 gp40 gp40 3c clk_out register clk_out register clk_out register 3d gp42 gp42 gp42 3e reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 3f gp50 gp50 gp50 40 gp51 gp51 gp51 41 gp52 gp52 gp52 42 gp53 gp53 gp53 43 gp54 gp54 gp54 44 gp55 gp55 gp55 45 gp56 gp56 gp56 46 gp57 gp57 gp57 47 gp60 gp60 gp60 48 gp61 gp61 gp61 49 pwr_rec pwr_rec reserved ? reads return 0 ( note 26.2 ) 4a ps_on register ps_on register reserved ? reads return 0 ( note 26.2 ) 4b gp1 gp1 gp1 4c gp2 gp2 gp2 4d gp3 gp3 gp3 4e gp4 gp4 gp4 4f gp5 gp5 gp5 50 gp6 gp6 gp6 51 reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 52 reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 53 ps_on# previous state ps_on# previous state reserved ? reads return 0 ( note 26.2 ) table 26.1 sch311x runtime register summary (continued) register offset (hex) sch3112 register sch3114 register sch3116 register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 314 smsc sch311x datasheet 54 gp62 gp62 ( note 26.6 )gp62 ( note 26.6 ) 55 gp63 gp63 ( note 26.6 )gp63 ( note 26.6 ) 56 gp64 gp64( note 26.6 )gp64( note 26.6 ) 57 gp65 gp65( note 26.6 )gp65( note 26.6 ) 58 gp66 gp66( note 26.6 )gp66( note 26.6 ) 59 gp67 gp67 ( note 26.6 )gp67 ( note 26.6 ) 5a test test test 5b dblclick dblclick dblclick 5c mouse_specific_wake mouse_specific_wake mouse_specific_wake 5d led1 led1 led1 5e led2 led2 led2 5f keyboard scan code ? make byte 1 keyboard scan code ? make byte 1 keyboard scan code ? make byte 1 60 keyboard scan code ? make byte 2 keyboard scan code ? make byte 2 keyboard scan code ? make byte 2 61 keyboard scan code ? break byte 1 keyboard scan code ? break byte 1 keyboard scan code ? break byte 1 62 keyboard scan code ? break byte 2 keyboard scan code ? break byte 2 keyboard scan code ? break byte 2 63 keyboard scan code ? break byte 3 keyboard scan code ? break byte 3 keyboard scan code ? break byte 3 64 keyboard pwrbtn/spekey keyboard pwrbtn/spekey keyboard pwrbtn/spekey 65 wdt_time_out wdt_time_out wdt_time_out 66 wdt_val wdt_val wdt_val 67 wdt_cfg wdt_cfg wdt_cfg 68 wdt_ctrl wdt_ctrl wdt_ctrl 69 reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 6a reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 6b reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 table 26.1 sch311x runtime register summary (continued) register offset (hex) sch3112 register sch3114 register sch3116 register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 315 revision 0.4 (06-03-05) datasheet 6c reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 6d reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 6e reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 6f gp45 ( note 26.7 )gp45 ( note 26.7 )gp45 ( note 26.8 ) 70 hwm index register hwm index register hwm index register 71 hwm data register hwm data register hwm data register 72 gp46 ( note 26.7 )gp46 ( note 26.7 )gp46 ( note 26.8 ) 73 gp47 ( note 26.7 )gp47 ( note 26.7 )gp47 ( note 26.8 ) 74-7fh reserved ? reads return 0 reserved ? reads return 0 reserved ? reads return 0 table 26.2 runtime register por summary register offset (hex) type pci reset vcc por vtr por soft reset vbat por register 00 r/wc - - 0x00 - - pme_sts 01 r - - - - - reserved ? reads return 0 02 r/w - - 0x00 - - pme_en 03 r - - - - - reserved ? reads return 0 04 r/wc - - 0x00 - - pme_sts1 05 r/wc - - 0x00 - - pme_sts3 06 r/wc - - 0x00 - - pme_sts5 ( note 26.1 ) 07 r/wc - - note 26. 9 - - pme_sts6 08 r/w - - 0x00) - - pme_en1 09 r/w - - 0x00 - - pme_en3 0a r/w - - 0x00 - - pme_en5 0b r/w - - 0x00 - - pme_en6 0c r - - 0x00 - - reserved (sch3112) 0c r/wc - - 0x00 - - pme_sts7 (sch3114 and sch3116) 0d r - - - - - reserved ? reads return 0 0e r - - - - - reserved ? reads return 0 0f r - - - - - reserved ? reads return 0 table 26.1 sch311x runtime register summary (continued) register offset (hex) sch3112 register sch3114 register sch3116 register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 316 smsc sch311x datasheet 10 r - - 0x00 - reserved (sch3112) 10 r/w - - 0x00 - pme_en7 (sch3114 and sch3116) 11 r - - 0x00 - reserved 12 r/w - - 0x44 - sp12 13 r - - 0x00 - reserved (sch3112) 13 r/w - - 0x00 - sp34 (sch3114 and sch3116) 14 note 26.16 -- note 26. 9 - - smi_sts1 15 note 26.16 - - 0x00 - - smi_sts2 16 r/wc - - 0x00 - - smi_sts3 17 r/wc - - 0x00 - - smi_sts4 18 r/w - - 0x00 - - smi_en1 19 r/w - - 0x00 - - smi_en2 1a r/w - - 0x00 - - smi_en3 1b r/w - - 0x00 - - smi_en4 1c r/w - - 0x00 - - msc_sts 1d r/w - - 0x00 - - resgen 1e r/w 0x03 0x03 0x03 - - force disk change 1f r - - - - - floppy data rate select shadow 20 r - - - - - uart1 fifo control shadow 21 r - - - - - uart2 fifo control shadow 22 r - - - - - reserved 22 r - - - - - uart3 fifo control shadow (sch3114 and sch3116) 23 r/w - - 0x01 - - gp10 24 r/w - - 0x01 - - gp11 25 r/w - - 0x01 - - gp12 26 r/w - - 0x01 - - gp13 table 26.2 runtime register por summary (continued) register offset (hex) type pci reset vcc por vtr por soft reset vbat por register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 317 revision 0.4 (06-03-05) datasheet 27 r/w - - 0x01 - - gp14 28 r - - 0x00 - - reserved (sch3112) 28 r - - 0x00 - - uart4 fifo control shadow (sch3114 and sch3116) 29 r - - 0x01 - - gp15 2a r - - 0x01 - - gp16 2b r - - 0x01 - - gp17 2c r/w - - 0x8c - - gp21 2d r/w - - 0x8c - - gp22 2e r - - 0x00 - - reserved (sch3112 and sch3114) 2e r - - 0x00 - - uart5 fifo control shadow (sch3116) 2f r - - 0x00 - - reserved (sch3112 and sch3114) 2f r - - 0x00 - - uart6 fifo control shadow (sch3116) 30 r - - 0x00 - - reserved (sch3112 and sch3114) 30 r/w - - 0x04 - - sp5 option (sch3116) 31 r - - 0x00 - - reserved (sch3112 and sch3114) 31 r/w - - 0x04 - - sp6 option (sch3116) 32 r/w - - 0x01 - - gp27 33 r/w - - 0x05 - - gp30 34 r/w - - 0x01 - - gp31 35 r/w - - 0x84 - - gp32 36 r/w - - 0x84 - - gp33 37 r/w - - 0x01 - - gp34 38 r - - - - - reserved 39 r/w - - 0x01 - - gp36 3a r/w - - 0x01 - - gp37 table 26.2 runtime register por summary (continued) register offset (hex) type pci reset vcc por vtr por soft reset vbat por register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 318 smsc sch311x datasheet 3b r/w - - 0x01 - - gp40 3c r - - 0x00 - - clk_out register 3d r/w - - 0x01 - - gp42 3e r - - - - - reserved ? reads return 0 3f r/w - - 0x01 - - gp50 40 r/w - - 0x01 - - gp51 41 r/w - - 0x01 - - gp52 42 r/w - - 0x01 - - gp53 43 r/w - - 0x01 - - gp54 44 r/w - - 0x01 - - gp55 45 r/w - - 0x01 - - gp56 46 r/w - - 0x01 - - gp57 47 r/w - - 0x01 - - gp60 48 r/w - - 0x01 - - gp61 49 note 26.11 0xxxxxxx xb note 26. 12 - 0xxxxxx 11b note 26. 12 - 0x00000 xxb note 26. 12 pwr_rec (sch3112 and sch3114) 49 r 0xxxxxxx xb note 26. 12 - 0xxxxxx 11b note 26. 12 - 0x00000 xxb note 26. 12 reserved (sch3116) 4a r - - - - 0x00 ps_on register (sch3112 and sch3114) 4a r - - - - 0x00 reserved (sch3116) 4b r/w - - 0x00 - - gp1 4c r/w - - 0x00 - - gp2 4d r/w - - 0x00 - - gp3 4e r/w - - 0x00 - - gp4 4f r/w - - 0x00 - - gp5 50 r/w - - 0x00 - - gp6 51 r - - - - - reserved ? reads return 0 52 r - - - - - reserved ? reads return 0 53 r/w - - - - 0x00 ps_on# previous state (sch3112 and sch3114) table 26.2 runtime register por summary (continued) register offset (hex) type pci reset vcc por vtr por soft reset vbat por register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 319 revision 0.4 (06-03-05) datasheet 53 r - - - - 0x00 reserved (sch3116) 54 r - - 0x01 - - gp62 55 r - - 0x01 - - gp63 56 r - - 0x01 - - gp64 57 r - - 0x01 - - gp65 58 r - - 0x01 - - gp66 59 r - - 0x01 - - gp67 5a r - - - - - test 5b note 26.17 ---- 0x0c dblclick 5c note 26.17 note 26. 9 note 2 6.9 note 26. 9 -- mouse_specific_wake 5d r/w - - 0x00 - - led1 5e r/w - - 0x00 - - led2 5f note 26.13 - - - - 0xe0 keyboard scan code ? make byte 1 60 note 26.13 - - - - 0x37 keyboard scan code ? make byte 2 61 note 26.13 - - - - 0xe0 keyboard scan code ? break byte 1 62 note 26.13 - - - - 0xf0 keyboard scan code ? break byte 2 63 note 26.13 - - - - 0x37 keyboard scan code ? break byte 3 64 note 26.13 note 26. 9 note 2 6.9 note 26. 9 - note 26. 9 keyboard pwrbtn/spekey 65 r/w 0x00 0x00 0x00 - - wdt_time_out 66 r/w 0x00 0x00 0x00 - - wdt_val 67 r/w 0x00 0x00 0x00 - - wdt_cfg 68 r/w note 26.15 0x00 note 26. 14 0x00 0x00 - - wdt_ctrl 69 r - - - - - reserved ? reads return 0 6a r - - - - - reserved ? reads return 0 6b r - - - - - reserved ? reads return 0 6c r - - - - - reserved ? reads return 0 table 26.2 runtime register por summary (continued) register offset (hex) type pci reset vcc por vtr por soft reset vbat por register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 320 smsc sch311x datasheet note 26.1 bit 3 of the pme_sts5 register may be set on a vcc por. if gp53 are configured as input, then their corresponding pme and smi status bits will be set on a vcc por. note 26.2 this register does not support the power failure recovery status. note 26.3 this register supports ring indicator status bits for serial ports 3-6 if required by the particular device. note 26.4 this register supports additional uart interrupt status bits for serial ports 3-6 if required by the particular device note 26.5 this register supports alternate functions for serial port 3. note 26.6 this register supports alternate functions for serial port 4. note 26.7 this register supports alternate functions for pci reset outputs. note 26.8 this register supports alternate functions for serial port 6. note 26.9 see the register description for the default value. note 26.10 bit[0] cannot be written to '1'. bit[1] and bit[7] are read-only. note 26.11 this register is a read/write register when bit[ 7]=0, except bit[4]. bit[4] is a read-only bit. this register is a read-only register when bit7]=1. note 26.12 this is a binary number. the x's denote a bit that is not affected by the reset condition. note 26.13 this register is re ad/write when bit [7] keyboard pwrbtn/spekey lock of the keyboard pwrbtn/spekey register at offset 64h is set to '0' and read-only when bit [7] is set to '1'. 6d r - - - - - reserved ? reads return 0 6e r - - - - - reserved ? reads return 0 6e r/w - - 0x01 - - gp44 (sch3116) 6f r/w - - 0x00 - - gp45 (sch3112 and sch3114) 6f r/w - - 0x01 - - gp45 (sch3116) 70 r/w - - 0x00 - - hwm index register 71 r/w - - 0x00 - - hwm data register 72 r/w - - 0x00 - - gp46 (sch3112 and sch3114) 72 r/w - - 0x01 - - gp46 (sch3116 73 r/w - - 0x00 - - gp47 (sch3112 and sch3114) 73 r/w - - 0x01 - - gp47 (sch3116) 74-7fh r - - - - - reserved ? reads return 0 table 26.2 runtime register por summary (continued) register offset (hex) type pci reset vcc por vtr por soft reset vbat por register
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 321 revision 0.4 (06-03-05) datasheet note 26.14 bit 0 is not cleared by pci reset. note 26.15 this register contains some bits that are read or write only. note 26.16 see the register description for the bit-wise access type. note 26.17 this register is read/write when bit [7] in the mouse_specific_wake register is set to '0' and read-only when bit [7] is set to '1'. 26.2 runtime register description the following registers are located at an offset from (pme_blk) the address programmed into the base i/o address register for logical device a. table 26.3 detailed runtime register description name reg offset (hex) description pme_sts default = 0x00 on vtr por 00 (r/wc) pme pin status register bit[0] pme_status = 0 (default) = 1 autonomously set when a wakeup event occurs that normally asserts the nio_pme signal. this bit is set independent of the state of the pme_en bit bit[7:1] reserved pme_status is not affected by vc c por, soft reset or pci reset. writing a ?1? to pme_status will clear it and cause the device to stop asserting nio_pme, in enabled. writing a ?0? to pme_status has no effect. pme_en default = 0x00 on vtr por 02 (r/w) pme pin enable register bit[0] pme_en = 0 nio_pme signal assertion is disabled (default) = 1 enables this device to assert nio_pme signal bit[7:1] reserved pme_en is not affected by v cc por, soft reset or pci reset pme_sts1 default = 0x00 on vtr por 04 (r/wc) pme wake status register 1 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] hw_monitor bit[1] ri2 bit[2] ri1 bit[3] kbd bit[4] mouse bit[5] reserved bit[6] irint. this bit is set by a transition on the ir pin (irrx) bit[7] reserved the pme wake status register is no t affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 322 smsc sch311x datasheet pme_sts3 default = 0x00 on vtr por 05 (r/wc) pme wake status register 3 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] wdt bit[1] gp21 bit[2] gp22 bit[3] devint_sts (status of group smi signal for pme) bit[4] gp27 bit[5] gp32 bit[6] gp33 bit[7] reserved the pme wake status register is no t affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_sts5 default = 0x00 on vtr por 06 (r/wc) pme wake status register 5 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] gp50 bit[1] gp51 bit[2] gp52 bit[3] gp53 bit[4] gp54 bit[5] gp55 bit[6] gp56 bit[7] gp57 the pme wake status register is no t affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_sts6 default = 0x00 or 0x01 on vtr por the default will be 0x01 if there is a low_bat event under vbat power only, 0x00 if the event does not occurs. bit[0] will be set to ?1? on a vcc por if the battery voltage drops below 2.4v under vtr power (vcc=0) or under battery power only. sch3112, sch3114 devices 07 (r/wc) this register indicates the state of the individual pme sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] low_bat, cleared by a write of ?1?. when the battery is removed and replaced or the if the battery voltage drops below 1.2v under battery power, then the low_bat pme status bit is set on vtr por. when the battery voltage drops below 2.4 volts under vtr power (vcc=0) or under battery power only, the low_bat pme status bit is set on vcc por. the corresponding enable bit must be set to generate a pme. the low battery event is not a pme wakeup event. bit[1] reserved. bit[2] gp60 bit[3] gp61 bit[4] spemse_sts (wake on specific mouse click) bit[5] spekey_sts (wake on specific key) bit[6] pb_sts bit[7] pfr_sts power fa ilure recovery status the pme status register is not affected by vc c por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme status register has no effect. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 323 revision 0.4 (06-03-05) datasheet pme_sts6 default = 0x00 or 0x01 on vtr por the default will be 0x01 if there is a low_bat event under vbat power only, 0x00 if the event does not occurs. bit[0] will be set to ?1? on a vcc por if the battery voltage drops below 2.4v under vtr power (vcc=0) or under battery power only. sch3116 device only 07 (r/wc) this register indicates the state of the individual pme sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] low_bat, cleared by a write of ?1?. when the battery is removed and replaced or the if the battery voltage drops below 1.2v under battery power, then the low_bat pme status bit is set on vtr por. when the battery voltage drops below 2.4 volts under vtr power (vcc=0) or under battery power only, the low_bat pme status bit is set on vcc por. the corresponding enable bit must be set to generate a pme. the low battery event is not a pme wakeup event. bit[1] reserved. bit[2] gp60 bit[3] gp61 bit[4] spemse_sts (wake on specific mouse click) bit[5] spekey_sts (wake on specific key) bit[6] pb_sts bit[7] reserved the pme status register is not affected by vc c por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme status register has no effect. pme_en1 default = 0x00 on vtr por 08 (r/w) pme wake enable register 1 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] hw_monitor bit[1] ri2 bit[2] ri1 bit[3] kbd bit[4] mouse bit[5] reserved bit[6] irint bit[7] reserved the pme wake enable register is not affected by vcc por, soft reset or pci reset. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 324 smsc sch311x datasheet pme_en3 default = 0x00 on vtr por 09 (r/w) pme wake status register 3 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] wdt bit[1] gp21 bit[2] gp22 bit[3] devint_en (enable bit for group smi signal for pme) bit[4] gp27 bit[5] gp32 bit[6] gp33 bit[7] reserved the pme wake enable register is not affected by vcc por, soft reset or pci reset. pme_en5 default = 0x00 on vtr por 0a (r/w) pme wake enable register 5 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] gp50 bit[1] gp51 bit[2] gp52 bit[3] gp53 bit[4] gp54 bit[5] gp55 bit[6] gp56 bit[7] gp57 the pme wake enable register is not affected by vcc por, soft reset or pci reset. pme_en6 default = 0x00 on vtr por sch3112, sch3114 devices only note: bit 7 of this register needs to be vbat powered 0b (r/w) pme enable register 6 this register is used to enable indi vidual pme sources onto the nio_pme signal. when the pme enable register bit for a pme source is active (?1?), if the source asserts a pme event and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme enable register bit for a pme source is inactive (?0?), the pme status register will indicate t he state of the pme source but will not assert the nio_pme signal. bit[0] low_bat bit[1] reserved bit[2] gp60 bit[3] gp61 bit[4] spemse_en (wake on specific mouse click) bit[5] spekey_en (wake on specific key) bit[6] pb_en bit[7] pfr_sts power fa ilure recovery enable the pme enable register 6 is not affe cted by vcc por, soft reset or pci reset. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 325 revision 0.4 (06-03-05) datasheet pme_en6 default = 0x00 on vtr por sch3116 device only note: bit 7 of this register needs to be vbat powered 0b (r/w) pme enable register 6 this register is used to enable indi vidual pme sources onto the nio_pme signal. when the pme enable register bit for a pme source is active (?1?), if the source asserts a pme event and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme enable register bit for a pme source is inactive (?0?), the pme status register will indicate t he state of the pme source but will not assert the nio_pme signal. bit[0] low_bat bit[1] reserved bit[2] gp60 bit[3] gp61 bit[4] spemse_en (wake on specific mouse click) bit[5] spekey_en (wake on specific key) bit[6] pb_en bit[7] reserved the pme enable register 6 is not affe cted by vcc por, soft reset or pci reset. pme_sts7 default = 0x00 on vtr por sch3112 device only 0c (r/wc) reserved bit[7:0] reserved pme_sts7 default = 0x00 on vtr por sch3114 device only 0c (r/wc) pme wake status register 7 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] ri3 bit[1] ri4 bit[2] reserved bit[3] reserved bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved the pme wake status register is no t affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 326 smsc sch311x datasheet pme_sts7 default = 0x00 on vtr por sch3116 device only 0c (r/wc) pme wake status register 7 this register indicates the state of the individual pme wake sources, independent of the individual source enables or the pme_en bit. if the wake source has asserted a wake event, the associated pme wake status bit will be a ?1?. if enabled, any set bit in this register asserts the nio_pme pin. bit[0] ri3 bit[1] ri4 bit[2] ri5 bit[3] ri6 bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved the pme wake status register is no t affected by vcc por, soft reset or pci reset. writing a ?1? to bit[7:0] will clear it. writing a ?0? to any bit in pme wake status register has no effect. pme_en7 default = 0x00 on vbat por sch3112 device only 10 (r/w) reserved bit[7:0] reserved pme_en7 default = 0x00 on vbat por sch3114 device only 10 (r/w) pme wake enable register 1 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] ri3 bit[1] ri4 bit[2] reserved bit[3] reserved bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved the pme wake enable register is not affected by vcc por, soft reset or pci reset. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 327 revision 0.4 (06-03-05) datasheet pme_en7 default = 0x00 on vbat por sch3116 device only 10 (r/w) pme wake enable register 1 this register is used to enable individual pme wake sources onto the nio_pme wake bus. when the pme wake enable register bit for a wake source is active (?1?), if the source asserts a wake event so that the associated status bit is ?1? and the pme_en bit is ?1?, the source will assert the nio_pme signal. when the pme wake enable register bit for a wake source is inactive (?0?), the pme wake status register will indicate the state of the wake source but will not assert the nio_pme signal. bit[0] ri3 bit[1] ri4 bit[2] ri5 bit[3] ri6 bit[4] reserved bit[5] reserved bit[6] reserved bit[7] reserved the pme wake enable register is not affected by vcc por, soft reset or pci reset. sp12 option default = 0x44 on vtr por 0x12 (r/w) sp options for sp1 and sp2 bit[0] automatic direction control select sp1 1=fc on 0=fc off bits[1] signal select sp1 1=nrts control 0=ndtr control bits[2] polarity sp1 0= drive low when enabled 1= drive 1 when enabled bits[3] reserved bit[4] automatic direction control select sp2 1=fc on 0=fc off bits[5] signal select sp2 1=nrts control 0=ndtr control bits[6] polarity sp2 0= drive low when enabled 1= drive 1 when enabled bits[7] reserved sp34 option default = 0x44 on vtr por this register is reserved for sch3112 device 0x13 (r/w) sch3112 device bits[7:0] reserved table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 328 smsc sch311x datasheet sp34 option default = 0x44 on vtr por sch3114 and sch3116 device only. 0x13 (r/w) sch3114 and sch3116 device sp options for sp3 and sp4 bit[0] automatic direction control select sp3 1=fc on 0=fc off bits[1] signal select sp3 1=nrts control 0=ndtr control bits[2] polarity sp3 0= drive low when enabled 1= drive 1 when enabled bits[3] reserved bit[4] automatic direction control select sp4 1=fc on 0=fc off bits[5] signal select sp4 1=nrts control 0=ndtr control bits[6] polarity sp4 0= drive low when enabled 1= drive 1 when enabled bits[7] reserved smi_sts1 default = 0x02, or 0x03 on vtr por. the default will be 0x03 if there is a low_bat event under vbat power only, or 0x02 if this event does not occur. bit 0 will be set to ?1? on a vcc por if the battery voltage drops below 2.4v under vtr power (vcc=0) or under battery power only. bit 1 is set to ?1? on vcc por, vtr por, pci reset and soft reset. 14 bits[0] are r/wc. bits[1:4,7] are ro. smi status register 1 this register is used to read the status of the smi inputs. the following bits must be cleared at their source except as shown. bit[0] low_bat. cleared by a write of ?1?. when the battery is removed and replaced or if the battery voltage drops below 1.2v (nominal) under battery power only (vbat por), then the low_bat smi status bit is set on vtr por. when the battery voltage drops below 2.4 volts (nominal) under vtr power (vcc=0) or under battery power only, the low_bat smi status bit is set on vcc por. bit[1] pint. the parallel port interrupt defaults to ?1? when the parallel port activate bit is cleared. when the parallel port is activated, pint follows the nack input. bit[2] u2int bit[3] u1int bit[4] fint bit[5] reserved bit[6] reserved bit[7] wdt smi_sts2 default = 0x00 on vtr por 15 (r/w) bits[0,1] are ro bits[2] is read-clear. smi status register 2 this register is used to read the status of the smi inputs. bit[0] mint. cleared at source. bit[1] kint. cleared at source. bit[2] irint. this bit is set by a transition on the ir pin (irrx). cleared by a read of this register. bit[3] reserved bit[4] spemse_sts (wake on specific mo use click) - clea red by writing a ?1? bit[7:5] reserved table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 329 revision 0.4 (06-03-05) datasheet smi_sts3 default = 0x00 on vtr por 16 (r/wc) smi status register 3 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] reserved bit[1] gp21 bit[2] gp22 bit[3] gp54 bit[4] gp55 bit[5] gp56 bit[6] gp57 bit[7] gp60 smi_sts4 default = 0x00 on vtr por ( note 26.23 ) sch3112 device only 17 (r/wc) sch3112 device smi status register 4 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] reserved bit[1] reserved bit[2] gp32 bit[3] gp33 bit[4] reserved bit[5] gp42 bit[6] reserved bit[7] gp61 smi_sts4 default = 0x00 on vtr por ( note 26.23 ) sch3114 device only 17 (r/wc) sch3114 device only: smi status register 4 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] u3int bit[1] u4int bit[2] gp32 bit[3] gp33 bit[4] reserved bit[5] gp42 bit[6] reserved bit[7] gp61 smi_sts4 default = 0x00 on vtr por ( note 26.23 ) sch3116 device only 17 (r/wc) sch3116 device only: smi status register 4 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] u3int bit[1] u4int bit[2] gp32 bit[3] gp33 bit[4] u5int bit[5] gp42 bit[6] u6int bit[7] gp61 smi_en1 default = 0x00 on vtr por 18 (r/w) smi enable register 1 this register is used to enable the diff erent interrupt sources onto the group nio_smi output. 1=enable 0=disable bit[0] en_low_bat bit[1] en_pint bit[2] en_u2int bit[3] en_u1int bit[4] en_fint bit[5] reserved bit[6] reserved bit[7] en_wdt table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 330 smsc sch311x datasheet smi_en2 default = 0x00 on vtr por 19 (r/w) smi enable register 2 this register is used to enable the diff erent interrupt sources onto the group nsmi output, and the group nsmi output onto the nio_smi gpi/o pin, the serial irq stream or into the pme logic. unless otherwise noted, 1=enable 0=disable bit[0] en_mint bit[1] en_kint bit[2] en_irint bit[3] reserved bit[4] en_spesme bit[5] en_smi_pme (enable group smi into pme logic) bit[6] en_smi_s (enable group smi onto serial irq) bit[7] en_smi (enable group smi onto nio_smi pin) smi_en3 default = 0x00 on vtr por 1a (r/w) smi enable register 3 this register is used to enable the diff erent interrupt sources onto the group nsmi output. 1=enable 0=disable bit[0] reserved bit[1] gp21 bit[2] gp22 bit[3] gp54 bit[4] gp55 bit[5] gp56 bit[6] gp57 bit[7] gp60 smi_en4 default = 0x00 on vtr por this is for the sch3112 device only 1b (r/w) sch3112 device smi status register 4 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] reserved bit[1] reserved bit[2] gp32 bit[3] gp33 bit[4] reserved bit[5] gp42 bit[6] reserved bit[7] gp61 smi_en4 default = 0x00 on vtr por this is for the sch3114 device only 1b (r/w) sch3114 device only: smi status register 4 this register is used to read the status of the smi inputs. the following bits are cleared on a write of ?1?. bit[0] u3int bit[1] u4int bit[2] gp32 bit[3] gp33 bit[4] reserved bit[5] gp42 bit[6] reserved bit[7] gp61 table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 331 revision 0.4 (06-03-05) datasheet smi_en4 default = 0x00 on vtr por this is for the sch3116 device only 1b (r/w) sch3116 device only: smi enable register 4 this register is used to enable the diff erent interrupt sources onto the group nsmi output. 1=enable 0=disable bit[0] en_u3int bit[1] en_u4int bit[2] gp32 bit[3] gp33 bit[4] en_u5int bit[5] gp42 bit[6] en_u6int bit[7] gp61 msc_sts default = 0x00 on vtr por 1c (r/w) miscellaneous status register bits[5:0] can be cleared by writing a 1 to their position (writing a 0 has no effect). bit[0] either edge triggered interrupt input 0 status. this bit is set when an edge occurs on the gp21 pin. bit[1] either edge triggered interrupt input 1 status. this bit is set when an edge occurs on the gp22 pin. bit[2] reserved bit[3] reserved bit[4] either edge triggered interrupt input 4 status. this bit is set when an edge occurs on the gp60 pin. bit[5] either edge triggered interrupt input 5 status. this bit is set when an edge occurs on the gp61 pin. bit[7:6] reserved. this bit always returns zero. resgen vtr por default = 00h 1dh (r/w) reset generator bit[0] wdt2_en: enable watchdog timer generation / select 0= wdt disabled - not source for pwrgd_out (default) 1= wdt enabled - source for pwrgd_out bit[1] thermtrip source select 0 = thermtrip not source for pwrgd_out ((default) 1 = thermtrip source for pwrgd_out bit[2] wdt2_ctl: wdt input bit bit[7:3] reserved force disk change default = 0x03 on vcc por, pci reset and vtr por 1e (r/w) force disk change bit[0] force disk change for fdc0 0=inactive 1=active bit[1] force disk change for fdc1 0=inactive 1=active force change 0 and 1 can be written to 1 but are not clearable by software. force change 0 is cleared on nstep and nds0 force change 1 is cleared on nstep and nds1 dskchg (fdc dir register, bit 7) = (nds0 and force change 0) or (nds1 and force change 1) or ndskchg setting either of the force disk change bits active ?1? forces the fdd ndskchg input active when the appropriate drive has been selected. bit[7:2] reserved table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 332 smsc sch311x datasheet floppy data rate select shadow 1f (r) floppy data rate select shadow bit[0] data rate select 0 bit[1] data rate select 1 bit[2] precomp 0 bit[3] precomp 1 bit[4] precomp 2 bit[5] reserved bit[6] power down bit[7] soft reset uart1 fifo control shadow 20 (r) uart fifo control shadow 1 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) uart2 fifo control shadow 21 (r) uart fifo control shadow 2 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) uart3 fifo control shadow this register is reserved for sch3112 device 22 (r) sch3112 device bits[7:0] reserved uart3 fifo control shadow sch3114 and sch3116 device only. 22 (r) sch3114 and sch3116 device uart fifo control shadow 3 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) gp10 default = 0x01 on vtr por sch3112 device only 23 (r/w) general purpose i/o bit 1.0 bit[0] i n/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp10 default = 0x01 on vtr por sch3114,sch3116 devices only 23 (r/w) general purpose i/o bit 1.0 bit[0] i n/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= rxd3 0=gp10 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 333 revision 0.4 (06-03-05) datasheet gp11 default = 0x01 on vtr por sch3112 device only 24 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp11 default = 0x01 on vtr por sch3114,sch3116 devices only 24 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=txd3 0=gp11 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp12 default = 0x01 on vtr por sch3112 device only 25 (r/w) general purpose i/o bit 1.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp12 default = 0x01 on vtr por sch3114,sch3116 devices only 25 (r/w) general purpose i/o bit 1.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ndcd3 0=gp12 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp13 default = 0x01 on vtr por sch3112 device only 26 (r/w) general purpose i/o bit 1.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp13 default = 0x01 on vtr por sch3114,sch3116 devices only 26 (r/w) general purpose i/o bit 1.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= nri3 0=gp13 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 334 smsc sch311x datasheet gp14 default = 0x01 on vtr por sch3112 device only 27 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp14 default = 0x01 on vtr por sch3114,sch3116 devices only 27 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ndsr3 0=gp14 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull uart4 fifo control shadow this register is reserved for sch3112 device 28 (r) sch3112 device bits[7:0] reserved uart4 fifo control shadow sch3114 and sch3116 device only. 28 (r) sch3114 and sch3116 device uart fifo control shadow 4 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) gp15 default = 0x01 on vtr por sch3112 device only 29 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp15 default = 0x01 on vtr por sch3114,sch3116 devices only 29 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ndtr3 0=gp15 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp16 default = 0x01 on vtr por sch3112 device only 2a (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 335 revision 0.4 (06-03-05) datasheet gp16 default = 0x01 on vtr por sch3114,sch3116 devices only 2a (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ncts3 0=gp16 bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp17 default = 0x01 on vtr por sch3112 device only 2b (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp17 default = 0x01 on vtr por sch3114,sch3116 devices only 2b (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= nrts3 0=gp17 bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp21 default =0x8c on vtr por 2c (r/w) general purpose i/o bit 2.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[3:2] alternate function select 11= kdat (default) 10=either edge triggered interrupt input 0 ( note 26.20 ) 01=reserved 00=basic gpio function bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull (default) application note: when bits[3:2] are programmed to ?11? to select the kdat function, bit[0] should always be programmed to ?0?. the kdat function will not operate properly when bit[0] is set. gp22 default =0x8c on vtr por 2d (r/w) general purpose i/o bit 2.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[3:2] alternate function select 11= kclk (default) 10=either edge triggered interrupt input 1 ( note 26.20 ) 01= reserved 00=basic gpio function bits[6:4] reserved bit[7] output type select 1=open drain (default) 0=push pull application note: when bits[3:2] are programmed to ?11? to select the kclk function, bit[0] should always be programmed to ?0?. the kclk function will not operate properly when bit[0] is set. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 336 smsc sch311x datasheet uart5 fifo control shadow this register is reserved for sch3112 and sch3115 devices 2e (r) sch3112 and sch3114 devices bits[7:0] reserved uart5 fifo control shadow sch3116 device only. 2e (r) sch3116 device uart fifo control shadow 5 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) uart6 fifo control shadow this register is reserved for sch3112 and sch3114 devices 2f (r) sch3112 and sch3114 devices bits[7:0] reserved uart6 fifo control shadow sch3116 device only. 2f (r) sch3116 device uart fifo control shadow 6 bit[0] fifo enable bit[1] rcvr fifo reset bit[2] xmit fifo reset bit[3] dma mode select bit[5:4] reserved bit[6] rcvr trigger (lsb) bit[7] rcvr trigger (msb) sp5 option default = 0x04 on vtr por this register is reserved for sch3112 and sch3114 devices 30 (r/w) sch3112 and sch3114 devices bits[7:0] reserved sp5 option default = 0x04 on vtr por sch3116 device only. 30 (r/w) sch3116 device - sp options for sp5 bit[0] nscout5 select: 1= nrts5 0= ndtr5 bit[2:1] nscin select: 11= ndcd5 10= nri5 01= ncts5 00= ndsr5 bit[3] automatic direction control select 1=fc on 0=fc off bits[4] signal select 1=nrts control 0=ndtr control bits[5] polarity 0= drive low when enabled 1= drive 1 when enabled bit[7:6] reserved table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 337 revision 0.4 (06-03-05) datasheet sp6 option default = 0x04 on vtr por this register is reserved for sch3112 and sch3114 devices 31 (r/w) sch3112 and sch3114 devices bits[7:0] reserved sp6 option default = 0x04 on vtr por sch3116 device only. 31 (r/w) sch3116 device - sp options for sp6 bit[0] nscout6 select: 1= nrts6 0= ndtr6 bit[2:1] nscin select: 11= ndcd6 10= nri6 01= ncts6 00= ndsr6 bit[3] automatic direction control select 1=fc on 0=fc off bits[4] signal select 1=nrts control 0=ndtr control bits[5] polarity 0= drive low when enabled 1= drive 1 when enabled bit[7:6] reserved gp27 default = 0x01 on vtr por 32 (r/w) general purpose i/o bit 2.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[3:2] alternate function select 11=reserved 10=8042 p17 function ( note 26.19 ) 01=nio_smi ( note 26.22 ) 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp30 default = 0x05 on vtr por 33 (r/w) general purpose i/o bit 3.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nfprst (default) 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain (default) 0=push pull gp31 default = 0x01 on vtr por sch3112 device only 34 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select read only returns 1= open drain note: the pin can only be an open drain output. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 338 smsc sch311x datasheet gp31 default = 0x01 on vtr por sch3114, sch3116 devices only 34 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= nri4 0=gp31 bits[6:3] reserved bit[7] output type select read only returns 1= open drain note: the pin can only be an open drain output. gp32 default = 0x84 on vtr por 35 (r/w) general purpose i/o bit 3.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=mdat (default) 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain (default) 0=push pull application note: when bit[2] are programmed to ?1? to select the mdat function, bit[0] should always be programmed to ?0?. the mdat function will not operate properly when bit[0] is set. gp33 default = 0x84 on vtr por 36 (r/w) general purpose i/o bit 3.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=mclk (default) 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain (default) 0=push pull application note: when bit[2] are programmed to ?1? to select the mclk function, bit[0] should always be programmed to ?0?. the mclk function will not operate properly when bit[0] is set. gp34 default = 0x01 on vtr por sch3112 device only 37 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select read only returns 1= open drain note: the pin can only be an open drain output. gp34 default = 0x01 on vtr por sch3114, sch3116 devices only 37 (r/w) general purpose i/o bit 1.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= ndtr4 0=gp34 bits[6:3] reserved bit[7] output type select read only returns 1= open drain note: the pin can only be an open drain output. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 339 revision 0.4 (06-03-05) datasheet gp36 default = 0x01 on vtr por 39 (r/w) general purpose i/o bit 3.6 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1= nkbdrst 0=basic gpio function bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp37 default = 0x01 on vtr por 3a (r/w) general purpose i/o bit 3.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=a20m 0=basic gpio function bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp40 default =0x01 on vtr por 3b (r/w) general purpose i/o bit 4.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=drvden0 ( note 26.21 ) 0=basic gpio function bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull clock output control register vtr por = 0x00 3c (r/w) bit[0] enable 1= output enabled 0= disable clock output bit[3:1] frequency select 000= 0.25 hz 001= 0.50 hz 010= 1.00 hz 011= 2.00 hz 100= 4.00 hz 101= 8.00 hz 110= 16 hz 111 = reserved bit[7:4] reserved gp42 default =0x01 on vtr por 3d (r/w) general purpose i/o bit 4.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nio_pme note: configuring this pin function as output with non-inverted polarity will give an active low output signal. the output type can be either open drain or push-pull. 0=basic gpio function bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 340 smsc sch311x datasheet gp50 default = 0x01 on vtr por 3f (r/w) general purpose i/o bit 5.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nri2 ( note 26.18 ) 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp51 default = 0x01 on vtr por 40 (r/w) general purpose i/o bit 5.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ndcd2 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp52 default = 0x01 on vtr por 41 (r/w) general purpose i/o bit 5.2 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=rxd2 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp53 default = 0x01 on vtr por 42 (r/w) general purpose i/o bit 5.3 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=txd2 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp54 default = 0x01 on vtr por 43 (r/w) general purpose i/o bit 5.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ndsr2 0=gpio bit[3] reserved bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 341 revision 0.4 (06-03-05) datasheet gp55 default = 0x01 on vtr por 44 (r/w) general purpose i/o bit 5.5 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nrts2 0=gpio bit[3] reserved bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp56 default = 0x01 on vtr por 45 (r/w) general purpose i/o bit 5.6 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ncts2 0=gpio bit[3] reserved bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp57 default = 0x01 on vtr por 46 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ndtr2 0=gpio bit[3] reserved bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp60 default = 0x01 on vtr por 47 (r/w) general purpose i/o bit 6.0 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[3:2] alternate function select 11=wdt 10=either edge triggered interrupt input 4 ( note 26.20 ) 01=led1 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull gp61 default = 0x01 on vtr por 48 (r/w) general purpose i/o bit 6.1 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[3:2] alternate function select 11=clko - programmable clock output as described in 10=either edge triggered interrupt input 5 ( note 26.20 ) 01=led2 00=gpio bits[6:4] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 342 smsc sch311x datasheet pwr_rec power recovery register default = 0xxxxx11b on vtr por default =x00000xxb on a vbat por default = 0xxxxxxxb on a vcc por and pci reset note: x indicates that the bit is not effected by this reset condition. sch3112 and sch3114 devices only. 49 r/w when bit[7] =0 (default), except for bit[4] bit[4] is a read-only bit. read-only when bit[7]=1 sch3112 and sch3114 devices a/c power control/recovery register bit[0] power button enable 0=disabled 1=enabled (default) bit[1] keyboard power button enable 0=disabled 1=enabled (default) bit[2] power failure recovery enable 0=disabled (default) 1=enabled bit[3] ps_on# sampling enable 0=sampling is disabled (mode 1) 1=sampling is enabled (mode 2) when sampling is enabled the ps_on# pin is sampled every 0.5 seconds and stored in an 8-bit shift register for up to a maximum of 4 seconds. bit[4] previous state bit (this read-only bit is powered by vbat) (note: this bit is not reset on a vtr por) this bit contains the state of the ps_on# pin when vtr power is removed from the device. 0=off (ps_on# signal was high) 1=on (ps_on# signal was low) bit[6:5] apf (after power failure) (these bits are powered by vbat) (note: this bit is not reset on a vtr por) when vtr transitions from the off state to the on state, the power recovery logic will look at the apf bi ts to determine if the power supply should be off or on. if the logic determines that the power supply should be place in the on state it will genera te a pulse on the pb_out# pin. the auto recovery logic does not directly control the ps_on# pin. the ps_on# pin is controlled by the slp_sx# pin. 00=power supply off 01=power supply on 10=power supply set to previous state 11=power supply off bit[7] register recovery r/w control this bit is used to control write acce ss to the power reco very register at offset 49h. 0=read/write 1=read-onlya/c power control/recovery register table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 343 revision 0.4 (06-03-05) datasheet pwr_rec power recovery register default = 0xxxxx11b on vtr por default =x00000xxb on a vbat por default = 0xxxxxxxb on a vcc por and pci reset note: x indicates that the bit is not effected by this reset condition. this register is reserved in the sch3116 device 49 r/w when bit[7] =0 (default), except for bit[4] bit[4] is a read-only bit. read-only when bit[7]=1 sch3116 devices bits[7:0] reserved ps_on register default = 0x00 on a vbat por default = value latched on power failure on a vtr por sch3112 and sch3114 devices only. 4a (r) sch3112 and sch3114 devices ps_on shift register this 8-bit register is used to read the ps_on sample values loaded in the shift register in a/c power recovery control - mode 2. bit[0] = ps_on# sampled 0 - 0.5sec before power failure bit[1] = ps_on# sampled 0.5 - 1.0sec before power failure bit[2] = ps_on# sampled 1.0 - 1.5sec before power failure bit[3] = ps_on# sampled 1.5 - 2.0sec before power failure bit[4] = ps_on# sampled 2.0 - 2.5sec before power failure bit[5] = ps_on# sampled 2.5 - 3.0sec before power failure bit[6] = ps_on# sampled 3.0 - 3.5sec before power failure bit[7] = ps_on# sampled 3.5 - 4.0sec before power failure bit definition 0=off (ps_on# signal was high) 1=on (ps_on# signal was low) note: this register is powered by vbat ps_on register default = 0x00 on a vbat por default = value latched on power failure on a vtr por this register is reserved in the sch3116 device 4a (r) sch3116 devices bits[7:0] reserved note: this register is powered by vbat table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 344 smsc sch311x datasheet gp1 default = 0x00 on vtr por 4b (r/w) general purpose i/o data register 1 bit[0] gp10 bit[1] gp11 bit[2] gp12 bit[3] gp13 bit[4] gp14 bit[5] gp15 bit[6] gp16 bit[7] gp17 gp2 default = 0x00 on vtr por 4c (r/w) general purpose i/o data register 2 bit[0] reserved bit[1] gp21 bit[2] gp22 bit[3] reserved bit[4] reserved bit[5] reserved bit[6] reserved bit[7] gp27 gp3 default = 0x00 on vtr por 4d (r/w) general purpose i\o data register 3 bit[0] gp30 bit[1] gp31 bit[2] gp32 bit[3] gp33 bit[4] gp34 bit[5] reserved bit[6] gp36 bit[7] gp37 gp4 default = 0xf0 on vtr por 4e (r/w) general purpose i/o data register 4 bit[0] gp40 bit[1] reserved bit[2] gp42 bit[3] reserved bit[4] gp44 bit[5] gp45 bit[6] gp46 bit[7] gp47 gp5 default = 0x00 on vtr por 4f (r/w) general purpose i/o data register 5 bit[0] gp50 bit[1] gp51 bit[2] gp52 bit[3] gp53 bit[4] gp54 bit[5] gp55 bit[6] gp56 bit[7] gp57 gp6 default = 0x00 on vtr por 50 (r/w) general purpose i/o data register 6 bit[0] gp60 bit[1] gp61 bit[2] gp62 bit[3] gp63 bit[4] gp64 bit[5] gp65 bit[6] gp66 bit[7] gp67 n/a 51 (r) bits[7:0] reserved ? reads return 0 table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 345 revision 0.4 (06-03-05) datasheet ps_on# previous state select default = 0x00 on vbat por sch3112 and sch3114 devices only. 53 (r/w) sch3112 and sch3114 devices bits[7:4] reserved ? reads return 0 bit[3] smsc reserved, should be programmed to 0 for proper operation bits[2:0] ps_on# previous state select the ttl level of the ps_on# pin is sampled every 0.5 seconds and placed into an 8-bit shift register while vtr and vcc are on. the ps_on# previous state select bits determine which bit is used as the previous state bit following a power failure (vtr ~2.2v). 000 = ps_on# sampled 0 - 0.5sec before power failure 001 = ps_on# sampled 0.5 - 1.0sec before power failure 010 = ps_on# sampled 1.0 - 1.5sec before power failure 011 = ps_on# sampled 1.5 - 2.0sec before power failure 100 = ps_on# sampled 2.0 - 2.5sec before power failure 101 = ps_on# sampled 2.5 - 3.0sec before power failure 110 = ps_on# sampled 3.0 - 3.5sec before power failure 111 = ps_on# sampled 3.5 - 4.0sec before power failure ps_on# previous state select default = 0x00 on vbat por this register is reserved in the sch3116 device 53 (r/w) sch3116 device bits[7:0] reserved gp62 default = 0x01 on vtr por sch3112 device only 54 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp62 default = 0x01 on vtr por sch3114, sch3116 devices only 54 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ncts4 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp63 default = 0x01 on vtr por sch3112 device only 55 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 346 smsc sch311x datasheet gp63 default = 0x01 on vtr por sch3114, sch3116 devices only 55 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ndcd4 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp64 default = 0x01 on vtr por sch3112 device only 56 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp64 default = 0x01 on vtr por sch3114, sch3116 devices only 56 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=rxd4 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp65 default = 0x01 on vtr por sch3112 device only 57 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp65 default = 0x01 on vtr por sch3114, sch3116 devices only 57 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=txd4 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp66 default = 0x01 on vtr por sch3112 device only 58 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 347 revision 0.4 (06-03-05) datasheet gp66 default = 0x01 on vtr por sch3114, sch3116 devices only 58 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=ndsr4 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp67 default = 0x01 on vtr por sch3112 device only 59 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bits[6:2] reserved bit[7] output type select 1=open drain 0=push pull gp67 default = 0x01 on vtr por sch3114, sch3116 devices only 59 (r/w) general purpose i/o bit 5.7 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nrts4 0=gpio bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull test default = 0x00 on vbat por 5a (r) bits[0:1,5] smsc reserved bit. must be written as a ?0?. bits[2:4,6:7] reserved read only. dblclick default = 0x0c on vbat por 5b bits [5:0] are r/w when mouse_spe cific_wake register- bit [7] is ?0? bits [5:0] are read only when mouse_spe cific_wake register- bit [7] is ?1? double click for specific wake on mouse select register the dblclick contains a numeric value that determines the time interval used to check for a double mouse click. dblclick is the time interval between mouse clicks. for example, if dblclick is set to 0.5 seconds, you have one half second to click twice for a double-click. bit[0:5] this field contains a six bit weighted sum value from 0 to 0x3fh which provides a double click interval between 0.0859375 and 5.5 seconds. each incremental digit has a weight of 0.0859375 seconds. bit[6] reserved - returns zero when read bit[7] spinup delay 1= zero delay for spinup following vtr por 0 = spinup delay by 2 seconds (default) table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 348 smsc sch311x datasheet mouse_specific_w ake default = 00h on vbat por default = 0xxxxxxxb on vtr por, vcc por, and pci reset note: the ?x? indicates bit is not effected by reset 5c r/w when bit [7] is ?0? read only when bit [7] is ?1? specific wake on mouse click control register bit[0:1] smsc reserved bit. must be written as a ?0?. bits[4:2] spesme select. these bits se lect which mouse event is/are routed to trigger a pme wake event. 000 = any button click or any movement (left/right/middle) 001 = one click of left button. 010 = one click of right button. 011 = any one click of left/right/middle button. 100 = reserved 101 = two times click of left button. 110 = two times click of right button. 111 = reserved bit[5] reserved. read only zero. bit[6] kb_mse_swap. this bit swap s the keyboard and mouse port interfaces. 0 = the keyboard and mouse ports are not swapped. 1 = the keyboard and mouse ports are swapped. bit [7] mouse_specific_wake lock (note) (this bit is reset on a vbat por, vtr por, vcc por, and pci reset) 0 = mouse_specific_wake , and dblclick registers are read/write. 1 = mouse_specific_wake and dblclick registers are read only. led1 default = 0x00 on vtr por 5d (r/w) led1 bit[1:0] led1 control 00=off 01=blink at 1hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=blink at ? hz rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on bits[7:2] reserved led2 default = 0x00 on vtr por 5e (r/w) led2 bit[1:0] led2 control 00=off 01=blink at 1hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off) 10=blink at ? hz rate with a 25% duty cycle (0.5 sec on, 1.5 sec off) 11=on bits[7:2] reserved keyboard scan code ? make byte 1 (msb) default = 0xe0 on vbat por 5f (r/w) keyboard scan code this register is used to decode the first byte received from keyboards that generate multi-byte make codes and for single byte make codes. bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code note: the keyboard scan code registers default to the acpi scan 2 power make/break codes. (i.e., make=e0_37, break=e0_f0_37). note: programming this register to 0x00 indicates that this register a don?t care. any valid scan code t hat is received will be a match. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 349 revision 0.4 (06-03-05) datasheet keyboard scan code ? make byte 2 (lsb) default = 0x37 on vbat por 60 (r/w) keyboard scan code this register is used only for multi-byte make codes. it is used to decode the second byte received. bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code note: the keyboard scan code registers default to the acpi scan 2 power make/break codes. (i.e., make=e0_37, break=e0_f0_37). note: programming this register to 0x00 indicates that this register a don?t care. any valid scan code t hat is received will be a match. keyboard scan code ? break byte 1 (msb) default = 0xe0 on vbat por 61 (r/w) keyboard scan code this register is used to decode the first byte received from keyboards that generate multi-byte make codes and for single byte break codes. bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code note: the keyboard scan code registers default to the acpi scan 2 power make/break codes. (i.e., make=e0_37, break=e0_f0_37). note: programming this register to 0x00 indicates that this register a don?t care. any valid scan code t hat is received will be a match. keyboard scan code ? break byte 2 default = 0xf0 on vbat por 62 (r/w) keyboard scan code this register is used to decode the second byte received in multi-byte break codes. bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code note: the keyboard scan code registers default to the acpi scan 2 power make/break codes. (i.e., make=e0_37, break=e0_f0_37). note: programming this register to 0x00 indicates that this register a don?t care. any valid scan code t hat is received will be a match. keyboard scan code ? break byte 3 (lsb) default = 0x37 on vbat por 63 (r/w) keyboard scan code this register is used to decode the thir d byte received in scan 2 multi-byte break codes. bit[0] lsb of scan code . . . . . . . . . bit[7] msb of scan code note: the keyboard scan code registers default to the acpi scan 2 power make/break codes. (i.e., make=e0_37, break=e0_f0_37). note: programming this register to 0x00 indicates that this register a don?t care. any valid scan code t hat is received will be a match. table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 350 smsc sch311x datasheet keyboard pwrbtn/spekey default = 6ch on vbat por default = 0xxxxxxxb on vtr por, vcc por, and pci reset note: the ?x? indicates bit is not effected by reset 64 r/w when bit [7] is ?0? read only when bit [7] is ?1? bit[0] smsc reserved bit. must be written as a ?0?. bit[1] smsc reserved bit. must be written as a ?0?. bits[3:2] spekey scancode. this bit is used to config ure the hardware to decode a particular type of scan code. 00 = single byte, scan code set 1 (ex. make=37h and break=b7h) 01 =multi-byte, scan code set 1 (ex. make = e0h, 37h and break = e0h, b7h) 10 = single byte, scan code set 2 (ex. make=37h and break=f0h 37h) 11 = multi-byte, scan code set 2 (ex. make = e0h, 37h and break = e0h f0h 37h) (default) bits[5:4] keyboard power button release these bits are used to determine the pulse width of the power button event from the keyboard (kb_pb_sts). the wake on specific key can be configured to generate a pme event and/or power button event. if it is used to generate a power button event, the following bits will determine when the kb_pb_sts event is de-asserted. 00=de-assert kb_pb_sts 0.5sec after it is asserted (default) 01=de-assert kb_pb_sts after any valid scan code not equal to the programmed make code. 10=de-assert kb_pb_sts when scan code received is equal to programmed break code 11=reserved bit[6] smsc reserved bit. must be written as a ?1?. keyboard pwrbtn/spekey (continued) bit [7] keyboard pwrbtn/spekey lock (n ote) (this bit is reset on a vbat por, vtr por, vcc por, and pci reset) 0 = keyboard pwrbtn/spekey and keyb oard scan code registers are read/write 1 = keyboard pwrbtn/spekey and keyb oard scan code registers are read only note: the following registers become read-only when bit [7] is ?1?: keyboard scan code ? make byte 1 at offset 5fh keyboard scan code ? make byte 2 at offset 60h keyboard scan code ? break byte 1 at offset 61h keyboard scan code ? break byte 2 at offset 62h keyboard scan code ? break byte 3 at offset 63h keyboard pwrbtn/spekey at offset 64h wdt_time_out default = 0x00 on vcc por, vtr por, and pci reset 65 (r/w) watch-dog timeout bit[0] reserved bit[1] reserved bits[6:2] reserved, = 00000 bit[7] wdt time-out value units select = 0 minutes (default) = 1 seconds wdt_val default = 0x00 on vcc por, vtr por, and pci reset 66 (r/w) watch-dog timer time-out value binary coded, units = minutes (default) or seconds, selectable via bit[7] of wdt_time_out register (0x52). 0x00 time out disabled 0x01 time-out = 1 minute (second) ......... 0xff time-out = 255 minutes (seconds) table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 351 revision 0.4 (06-03-05) datasheet wdt_cfg default = 0x00 on vcc por, vtr por, and pci reset 67 (r/w) watch-dog timer configuration bit[0] reserved bit[1] keyboard enable =1 wdt is reset upon a keyboard interrupt. =0 wdt is not affected by keyboard interrupts. bit[2] mouse enable =1 wdt is reset upon a mouse interrupt. =0 wdt is not affected by mouse interrupts. bit[3] reserved bits[7:4] wdt interrupt mapping 1111 = irq15 ......... 0011 = irq3 0010 = irq2 (note) 0001 = irq1 0000 = disable note: irq2 is used for generating smi events via the serial irq?s stream. the wdt should not be configured for irq2 if the irq2 slot is enabled for generating an smi event. wdt_ctrl default = 0x00 on vcc por and vtr por default = 0000000xb on pci reset note: bit[0] is not cleared by pci reset 68 (r/w) bit[2] is write-only watch-dog timer control bit[0] watch-dog status bit, r/w =1 wd timeout occurred =0 wd timer counting bit[1] reserved bit[2] force timeout, w =1 forces wd timeout event; this bit is self-clearing bit[3] p20 force timeout enable, r/w = 1 allows rising edge of p20, from the keyboard controller, to force the wd timeout event. a wd timeout event may still be forced by setting the force timeout bit, bit 2. note : if the p20 signal is high when the enable bit is set a wd timeout event will be generated. = 0 p20 activity does not generate the wd timeout event. note: the p20 signal will remain high for a minimum of 1us and can remain high indefinitely. therefore, when p20 forced timeouts are enabled, a self- clearing edge-detect circuit is used to generate a signal which is or?ed with the signal generated by the force timeout bit. bit[7:4] reserved. set to 0 test default=0x00 on vbat por 6d (r/w) test register. test registers are reserved for smsc. users should not write to this register, may produce undesired results. gp44 default = 0x80 on vtr por sch3112, sch3114 only 6eh (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=gpio 0=nide_rstdrv (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 352 smsc sch311x datasheet gp44 default = 0x01 on vtr por sch3116 only 6eh (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=txd6 0=gpio (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp45 default = 0x00 on vtr por sch3112, sch3114 only 6fh (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=gpio 0=npci_rst1 (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp45 default = 0x01 on vtr por sch3116 only 6fh (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=rxd6 0=gpio (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull hw_reg index default=0x00 on vtr por 70 (r/w) the register is used to access the registers located in the h/w monitoring register block. the value in this register is the register index (address), which determines the register currently accessible. hw_reg data default=0x00 on vtr por 71 (r/w) this register is used to read/write the data in the hardware monitoring register that is currently index?d. (see the hw_reg index register at offset 60h.) gp46 default = 0x00 on vtr por sch3112, sch3114 only 72h (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=gpio 0=npci_rst2 (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp46 default = 0x01 on vtr por sch3116 only 72h (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nscin6 0=gpio (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 353 revision 0.4 (06-03-05) datasheet note: when selecting an alternate function for a gpio pin, all bits in the gpio register must be properly programmed, including in/out, polarity and output type. application note: note 26.18 if this pin is used for ring indicator wakeup, either the nri2 event can be enabled via bit 1 in the pme_en1 register or the gp50 pme event can be enabled via bit 0 in the pme_en5 register. note 26.19 in order to use the p17 functions, the corresponding gpio must be programmed for output, non-invert, and push-pull output type. note 26.20 if the eeti function is selected for this gpio then both a high-to-low and a low-to-high edge will set the pme, smi and msc status bits. note 26.21 if the fdc function is selected on this pin (drvden0) then bit 6 of the fdd mode register (configuration register 0xf0 in logical device 0) will override bit 7 in the gpio control register. bit 7 of the fdd mode register will also affect the pin if the fdc function is selected. note 26.22 the nio_smi pin is inactive when the internal group smi signal is inactive and when the smi enable bit (en_smi, bit 7 of the smi_en2 register) is '0'. when the output buffer type is od, nio_smi pin is floating when inactive; when the output buffer type is push-pull, the nio_smi pin is high when inactive. note 26.23 bit3 of the pme_sts5 register may be set on a vcc por. if gp53 is configured as input, then the corresponding pme status bits will be set on a vcc por. these bits are r/w but have no effect on circuit operation. note 26.24 these bits are r/w but have no effect on circuit operation. gp47 default = 0x00 on vtr por sch3112, sch3114 only 73h (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=gpio 0=npci_rst3 (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull gp47 default = 0x01 on vtr por sch3116 only 73h (r/w) general purpose i/o bit 4.4 bit[0] in/out : =1 input, =0 output bit[1] polarity : =1 invert, =0 no invert bit[2] alternate function select 1=nscout6 0=gpio (default) bits[6:3] reserved bit[7] output type select 1=open drain 0=push pull n/a 74-7f (r) bits[7:0] reserved ? reads return 0 table 26.3 detailed runtime register description (continued) name reg offset (hex) description
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 354 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 355 revision 0.4 (06-03-05) datasheet chapter 27 valid power modes the following table shows the valid power states for each power supply to the device. note 27.1 although this is not considered normal operat ing mode, vbat = off is a valid power state. when vbat is off all battery backed system context will be lost. table 27.1 valid power states power supply power state s0-s2s3s4-s5 vbat on off ( note 27.1 ) on off ( note 27.1 ) on off ( note 27.1 ) vtrononon vcc on off off hvtr on (hvtr=vtr) on (hvtr=vtr) on (hvtr=vtr)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 356 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 357 revision 0.4 (06-03-05) datasheet chapter 28 operational description 28.1 maximum guaranteed ratings operating temperature range ........................................................................................ -40 o c to +85 o c storage temperature range............................................................................................. -55 o to +150 o c lead temperature range ............................................................... refer to jedec spec. j-std-020b note: stresses above those listed above and below could cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. when powering this device from laboratory or system power supplies, it is impo rtant that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this possibility exists, it is suggested that a clamp circuit be used. 28.1.1 super i/o section (pins 3 to 112) maximum v cc ............................................................................................................................... .... +5.0v positive voltage on any pin, with respect to ground ................................................................. v cc +0.3v negative voltage on any pin, with respect to ground ..................................................................... -0.3v 28.1.2 hardware monitoring block (p ins 1 and 2 and pins 113 to 128) maximum hvtr ................................................................................................................... ............ +5.0v positive voltage on any pin, with respect to ground (except analog inputs) ...................... hvtr+0.3v negative voltage on any pin, with respect to ground (except analog inputs)................................ -0.3v 28.2 dc electri cal characteristics table 28.1 buffer operational ratings super i/o block (t a = -40 o c ? +85 o c, v cc = +3.3 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 5.0 v v ttl levels is type input buffer low input level high input level schmitt trigger hysteresis v ilis v ihis v hys 2.2 100 0.8 5.0 v v mv schmitt trigger schmitt trigger
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 358 smsc sch311x datasheet o6 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 6ma i oh = -3ma o8 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 8ma i oh = -4ma od4 type buffer low output level high output level v ol v oh 0.4 vcc+0.3 v v i ol = 4ma open drain; vcc=3.3v od8 type buffer low output level high output level v ol v oh 0.4 vcc+0.3 v v i ol = 8ma open drain; vcc=3.3v o12 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 12ma i oh = -6ma od12 type buffer low output level high output level v ol v oh 0.4 vcc+0.3 v v i ol = 12ma open drain; vcc=3.3v od14 type buffer low output level high output level v ol v oh 0.4 vcc+0.3 v v i ol = 14ma open drain; vcc=3.3v op14 type buffer low output level high output level v ol v oh 2.4 0.4 v v i ol = 14ma i oh = -14ma io8 type buffer low input level high input level low output level high output level v ili v ihi v ol v oh 2.0 2.4 0.8 5.0 0.4 v v v v ttl levels i ol = 8ma i oh = -4ma table 28.1 buffer operational ratings (continued) super i/o block (t a = -40 o c ? +85 o c, v cc = +3.3 v 10%) parameter symbol min typ max units comments
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 359 revision 0.4 (06-03-05) datasheet is/o8 type buffer low input level high input level schmitt trigger hysteresis low output level high output level v ili v ihi v hys v ol v oh 2.2 2.4 100 0.8 5.0 0.4 v v mv v v schmitt trigger schmitt trigger i ol = 8ma i oh = -4ma io12 type buffer low input level high input level low output level high output level v ili v ihi v ol v oh 2.0 2.4 0.8 5.0 0.4 v v v v ttl levels i ol = 12ma i oh = -6ma iop14 type buffer low input level high input level low output level high output level v ili v ihi v ol v oh 2.0 2.4 0.8 5.0 0.4 v v v v ttl levels i ol = 14ma i oh = -14ma iod16 type buffer low input level high input level low output level high output level v ili v ihi v ol v oh 2.0 0.8 5.0 0.4 vcc+0.3 v v v v ttl levels i ol = 16ma open drain; vcc=3.3v od_ph type buffer vol 0.3 v rload is 40ohms to 1.2v max output impedance is 10ohms pci type buffers (pci_iclk, pci_i, pci_o, pci_io) 3.3v pci 2.1 compatible. leakage current (all) input high current input low current ileak ih ileak il 10 -10 a a ( note 28.1 ) v in = v cc v in = 0v table 28.1 buffer operational ratings (continued) super i/o block (t a = -40 o c ? +85 o c, v cc = +3.3 v 10%) parameter symbol min typ max units comments
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 360 smsc sch311x datasheet backdrive protect/chiprotect (all signal pins excluding lad[3:0], ldrq#, lframe#) input high current input low current ileak ih ileak il 10 -10 a a v cc = 0v v in = 5.5v max v in = 0v 5v tolerant pins (all signal pins excluding lad[3:0], ldrq#, lframe#) inputs and outputs in high impedance state input high current input low current ileak ih ileak il 10 -10 a a v cc = 0v v in = 5.5v max v in = 0v lpc bus pins (lad[3:0], ldrq#, lframe#) input high current input low current ileak ih ileak il 10 -10 a a v cc = 0v and v cc = 3.3v v in = 3.6v max v in = 0v v cc supply current active i cc 1 ( note 28.2 ) ma all outputs open, all inputs transitioning from/to 0v to/from 3.3v. trickle supply voltage v tr 2.97 ( note 28.3 ) 3.3 3.63 v v tr supply current active i tr 25 ( note 28.2 , note 28.4 ) ma all outputs, all inputs transitioning from/to 0v to/from 3.3v. battery supply voltage v bat 2.2 3.0 3.6 v v bat average supply current active v bat monitoring active v bat monitoring disabled i bat, avg i bat, avg 1.5 1.0 a all outputs open, all inputs transitioning to/from 0v from/to 3.0v). see pme_sts1. v bat peak supply current active v bat monitoring active i bat, peak 10 a all outputs open, all inputs transitioning to/from 0v from/to 3.0v). see pme_sts1. table 28.1 buffer operational ratings (continued) super i/o block (t a = -40 o c ? +85 o c, v cc = +3.3 v 10%) parameter symbol min typ max units comments
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 361 revision 0.4 (06-03-05) datasheet hardware monitoring block (t a = -40 o c ? +85 o c, hvtr = +3.3 v 10%) parameter symbol min typ max units comments temperature-to-digital converter characteristics internal temperature accuracy external diode sensor accuracy -3 -2 -5 -3 0.25 0.25 +3 +2 +5 +3 o c o c o c o c o c o c 0 o c <= t a <= 70 o c 40 o c <= t a <= 70 o c resolution -40 o c <= t s <= 125 o c 40 o c <= t s <= 100 o c resolution analog-to-digit al converter characteristics total unadjusted error differential non-linearity power supply sensitivity total monitoring cycle time (cycle mode, default averaging) conversion time (continuous mode, default averaging) input resistance adc resolution tue dnl pss t c(cycle) t c(cts) 225 1 1 1.25 247 140 2 1.4 275 200 % lsb %/v sec msec k ? note 28.5 note 28.6 note 28.7 10 bits note 28.10 input buffer (i) (fantach1-fantach4) low input level high input level v ili v ihi 2.0 0.8 vcc+0.3 v v i_vid type buffer (gp62* to gp67*) low input level high input level v ili v ihi 0.8 0.4 vcc+0.3 v v ( note 28.11 ) iod type buffer (scl, sda, pwm1, pwm2, pwm3/address enable, nhwm_int low input level high input level hysteresis low output level v ili v ihi v hys v ol 2.0 500 0.8 vcc+0.3 0.4 v v mv v i ol = +4.0 ma ( note 28.9 )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 362 smsc sch311x datasheet notes: voltages are measured from the local ground potential, unless otherwise specified. typicals are at ta=25c and represent most likely parametric norm. the maximum allowable power dissipation at any temperature is pd = (tjmax - ta) / qja. timing specifications are tested at the ttl logic levels, vil=0.4v for a falling edge and vih=2.4v for a rising edge. tri-state output voltage is forced to 1.4v. note 28.1 all leakage currents are measured with all pins in high impedance. note 28.2 these values are estimated. they will be updated after characterization. contact smsc for the latest values. note 28.3 the minimum value given for v tr applies when v cc is active. when v cc is 0v, the minimum v tr is 0v. note 28.4 max i tri with v cc = 3.3v (nominal) is 10ma max i tri with v cc = 0v (nominal) is 250ua note 28.5 tue (total unadjusted error) includes offset, gain and linearity errors of the adc. note 28.6 total monitoring cycle time for cycle mode includes a one second delay plus all temperature conversions and all analog input voltage conversions. note 28.7 see pme_sts1 for conversion cycle timing for all averaging options. only the nominal default case is shown in this section. note 28.8 all leakage currents are measured with all pins in high impedance. note 28.9 the low output level for pwm pins is actually +8.0ma. note 28.10 the h/w monitor analog block implements a 10-bit adc. the output of this adc goes to an average block, which can be configured to accumulate the averaged value of the analog inputs. the amount of averaging is progra mmable. the output of the averaging block produce a 12-bit temperature or voltage read ing value. the 8 msbits go to the reading register and the 4 lsbits to the a/d lsb register. note 28.11 other platform components may use vid inputs and may require tighter limits. leakage current (all - digital) input high current input low current digital input capacitance ileak ih ileak il c in 10 -10 10 a a pf ( note 28.8 ) v in = v cc v in = 0v v cc supply current active mode sleep mode shutdown mode i cc i cc i cc 3 500 3 ma a a all outputs open, all inputs transitioning from/to 0v to/from 3.3v. hardware monitoring block (t a = -40 o c ? +85 o c, hvtr = +3.3 v 10%) parameter symbol min typ max units comments
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 363 revision 0.4 (06-03-05) datasheet 28.3 capacitance values for pins the input and output capacitance applies to both the super i/o block and the hardware monitoring block digital pins. note: the input capacitance of a port is measured at the connector pins. table 28.2 capacitance t a = 25; fc = 1mhz; v cc = 3.3v 10 % limits parameter symbol min typ m ax unit test condition clock input capacitance c in 20 pf all pins except pin under test tied to ac ground input capacitance c in 10 pf output capacitance c out 20 pf
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 364 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 365 revision 0.4 (06-03-05) datasheet chapter 29 timing diagrams for the timing diagrams shown, the following capacitive loads are used on outputs. name capacitance total (pf) ser_irq 50 lad [3:0] 50 ldrq# 50 ndir 240 nstep 240 nds0 240 pd[0:7] 240 nstrobe 240 nalf 240 kdat 240 kclk 240 mdat 240 mclk 240 led1 50 led2 50 txd1 50 txd2 50 txd3 50 txd4 50 txd5 50 txd6 50
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 366 smsc sch311x datasheet 29.1 power up timing figure 29.1 power-up timing note 29.1 internal write-protection period after vcc passes 2.7 volts on power-up 29.2 input clock timing figure 29.2 input clock timing name description min typ max units t1 vcc slew from 2.7v to 0v 300 ?s t2 vcc slew from 0v to 2.7v 100 ?s t3 all host accesses after power-up (see note 29.1 )125 500 ?s name description min typ max units t1 clock cycle time for 14.318mhz 69.84 ns t2 clock high time/low time for 14.318mhz 20 35 ns clock rise time/fall time (not shown) 5 ns t3 vcc all host a ccesses t2 t1 t1 t2 t2 clocki
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 367 revision 0.4 (06-03-05) datasheet 29.3 lpc interface timing figure 29.3 pci clock timing figure 29.4 reset timing name description min typ max units t1 period 30 33.3 nsec t2 high time 12 nsec t3 low time 12 nsec t4 rise time 3nsec t5 fall time 3nsec name description min typ max units t1 pci_reset# width 1 ms t1 t3 t2 pci_clk t5 t4 t1 pci_reset#
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 368 smsc sch311x datasheet figure 29.5 output timing meas urement conditions, lpc signals figure 29.6 input timing measure ment conditions, lpc signals note: l1=start; l2=cyctyp+dir; l3=sync of 0000 name description min typ max units t1 clk to signal valid delay ? bused signals 2 11 ns t2 float to active delay 2 11 ns t3 active to float delay 28 ns name description min typ max units t1 input set up time to clk ? bused signals 7 ns t2 input hold time from clk 0 ns t3 t2 t1 clk output delay tri-state output inputs valid t2 t1 clk input
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 369 revision 0.4 (06-03-05) datasheet figure 29.7 i/o write figure 29.8 i/o read figure 29.9 dma request assertion through ldrq# figure 29.10 dma write (first byte) figure 29.11 dma read (first byte) l1 l2 address data tar sync=0110 l3 tar pci_clk lframe# lad[3:0] l1 l2 address tar sync=0110 l3 data tar pci_clk lframe# lad[3:0] note: l1=start; l2=cyctyp+dir; l3=sync of 0000 start msb lsb act pci_clk ldrq# start c+d chl size tar sync=0101 l1 data tar pci_clk lframe# lad[3:0] note: l1=sync of 0000 start c+d chl size data tar sync=0101 l1 tar pci_clk lframe# lad[3:0] note : l1=sync of 0000
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 370 smsc sch311x datasheet 29.4 floppy disk controller timing figure 29.12 floppy disk drive timing (at mode only) mclk = 16 x data rate (at 500 kb/s mclk = 8 mhz) wclk = 2 x data rate (at 500 kb/s wclk = 1 mhz) note 29.2 the ds0 setup and hold times must be met by software. name description min typ max units t1 ndir set up to step low 4 x* t2 nstep active time low 24 x* t3 ndir hold time after nstep 96 x* t4 nstep cycle time 132 x* t5 nds0 hold time from nstep low ( note 29.2 )20x* t6 nindex pulse width 2 x* t7 nrdata active time low 40 ns t8 nwdata write data width low .5 y* t9 nds0 setup time ndir low ( note 29.2 )0 ns *x specifies one mclk period and y specifies one wclk period. t3 t1 t2 t4 t5 t6 t7 t8 ndir nstep nds0 nindex nrdata nwdata t9
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 371 revision 0.4 (06-03-05) datasheet 29.5 parallel port timing figure 29.13 epp 1.9 data or address write cycle note 29.3 nwait must be filtered to compensate for ringing on the parallel bus cable. nwait is considered to have settled after it does not transition for a minimum of 50 nsec name description min typ max units t1 nwait asserted to nwrite asserted (see note 29.3 ) 60 185 ns t2 nwait asserted to nwrite change (see note 29.3 ) 60 185 ns t3 nwait asserted to pdata invalid (see note 29.3 )0 ns t4 pdata valid to command asserted 10 ns t5 nwrite to command asserted 5 35 ns t6 nwait asserted to command asserted (see note 29.3 ) 60 210 ns t7 nwait deasserted to command deasserted (see note 29.3 ) 60 190 ns t8 command asserted to nwait deasserted 0 10 ?s t9 command deasserted to nwait asserted 0 ns t9 t8 t7 t6 t4 t5 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 372 smsc sch311x datasheet figure 29.14 epp 1.9 data or address read cycle name description min typ max units t1 nwait asserted to nwrite deasserted 0 185 ns t2 nwait asserted to nwrite modified (notes 1,2) 60 190 ns t3 nwait asserted to pdata hi-z (note 1) 60 180 ns t4 command asserted to pdata valid 0 ns t5 command deasserted to pdata hi-z 0 ns t6 nwait asserted to pdata driven (note 1) 60 190 ns t7 pdata hi-z to command asserted 0 30 ns t8 nwrite deasserted to command 1 ns t9 nwait asserted to command asserted 0 195 ns t10 nwait deasserted to command deasserted (note 1) 60 180 ns t11 pdata valid to nwait deasserted 0 ns t12 pdata hi-z to nwait asserted 0 s notes: 1. nwait is considered to have settled after it does not transition for a minimum of 50 ns. 2. when not executing a write cycle, epp nwrite is inactive high. t12 t11 t10 t9 t7 t8 t6 t5 t4 t3 t2 t1 nwrite pd<7:0> datastb a ddrstb nwait
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 373 revision 0.4 (06-03-05) datasheet figure 29.15 epp 1.7 data or address write cycle figure 29.16 epp 1.7 data or address read cycle name description min typ max units t1 command deasserted to nwrite change 0 40 ns t2 command deasserted to pdata invalid 50 ns t3 pdata valid to command asserted 10 35 ns t4 nwrite to command 5 35 ns t5 command deasserted to nwait deasserted 0 ns name description min typ max units t1 command asserted to pdata valid 0 ns t2 command deasserted to pdata hi-z 0 ns t3 command deasserted to nwait deasserted 0 ns t5 t4 t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait t3 t2 t1 nwrite pd<7:0> ndatastb naddrstb nwait
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 374 smsc sch311x datasheet ecp parallel port timing parallel port fifo (mode 101) the standard parallel port is run at or near the peak 500kbytes/sec allowed in the forward direction using dma. the state machine does not examine na ck and begins the next transfer based on busy. refer to figure 29.17 on page 375 . ecp parallel port timing the timing is designed to allow operation at appr oximately 2.0 mbytes/sec over a 15ft cable. if a shorter cable is used then the bandwidth will increase. forward-idle when the host has no data to send it keeps hostclk (nstrobe) high and the peripheral will leave periphclk (busy) low. forward data transfer phase the interface transfers data and commands from th e host to the peripheral using an interlocked periphack and hostclk. the peripheral may indicate its desire to send data to the host by asserting nperiphrequest. the forward data transfer phase may be entered from the forward-idle phase. while in the forward phase the peripheral may asynchronously assert t he nperiphrequest (nfault) to request that the channel be reversed. when the peripheral is not busy it sets periphack (busy) low. the host then sets hostclk (nstrobe) low when it is prepared to send data. the data must be stable for the specified setup time prior to the falling edge of hostclk. the peripheral then sets periphack (busy) high to acknowledge the handshake. the host then sets host clk (nstrobe) high. the peripheral then accepts the data and sets periphack (busy) low, completing the transfer. this sequence is shown in figure 29.18 on page 376 . the timing is designed to provi de 3 cable round-trip times for data setup if data is driven simultaneously with hostclk (nstrobe). reverse-idle phase the peripheral has no data to send and keeps periphclk high. the host is idle and keeps hostack low. reverse data transfer phase the interface transfers data and commands from the peripheral to the host using an interlocked hostack and periphclk. the reverse data transfer phase may be entered from the reverse-idle phase. after the previous byte has been accepted the host sets hostack (nalf) low. the peripheral then sets periphclk (nack) low when it has data to send. the data must be stable for the specified setup time prior to the falling edge of periphclk. when the host is ready to acc ept a byte it sets hostack (nalf) high to acknowledge the handshake. the peripheral then sets periphclk (nack) high. after the host has accepted the data, it sets hostack (nalf) low, co mpleting the transfer. this sequence is shown in figure 29.19 on page 377 . output drivers to facilitate higher performance data transfer, the use of balanced cmos ac tive drivers for critical signals (data, hostack, hostclk, periphack, periphclk) are used in ecp mode. because the use of active drivers can present compatibility problems in compatible mode (the control signals, by tradition, are specified as open-drain), the drivers are dynam ically changed from open-drain to push-pull. the timing for the dynamic driver change is specified in the ieee 1284 extended capabilities port protocol and isa interface standard, rev. 1.14 , july 14, 1993, available fr om microsoft. the dynamic driver change must be implemented properly to prevent glitching the outputs.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 375 revision 0.4 (06-03-05) datasheet figure 29.17 parallel port fifo timing note 29.4 the data is held until busy goes inactive or for time t3, whichever is longer. this only applies if another data transfer is pending. if no other data transfer is pending, the data is held indefinitely. name description min typ max units t1 pdata valid to nstrobe active 600 ns t2 nstrobe active pulse width 600 ns t3 pdata hold from nstrobe inactive (see note 29.4 ) 450 ns t4 nstrobe active to busy active 500 ns t5 busy inactive to nstrobe active 680 ns t6 busy inactive to pdata invalid (see note 29.4 )80 ns t3 t6 t1 t2 t5 t4 pd<7:0> nstrobe busy
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 376 smsc sch311x datasheet figure 29.18 ecp parallel port forward timing name description min typ max units t1 nalf valid to nstrobe asserted 0 60 ns t2 pdata valid to nstrobe asserted 0 60 ns t3 busy deasserted to nalf changed (notes 1,2) 80 180 ns t4 busy deasserted to pdata changed (notes 1,2) 80 180 ns t5 nstrobe asserted to busy asserted 0 ns t6 nstrobe deasserted to busy deasserted 0 ns t7 busy deasserted to nstrobe asserted (notes 1,2) 80 200 ns t8 busy asserted to nstrobe deasserted (note 2) 80 180 ns notes: 1. maximum value only applies if there is data in the fifo waiting to be written out. 2. busy is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. t3 t4 t1 t2 t7 t8 t6 t5 t6 nalf pd<7:0> busy nstrobe
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 377 revision 0.4 (06-03-05) datasheet figure 29.19 ecp paralle l port reverse timing name description min typ max units t1 pdata valid to nack asserted 0 ns t2 nalf deasserted to pdata changed 0 ns t3 nack asserted to nalf deasserted (notes 1,2) 80 200 ns t4 nack deasserted to nalf asserted (note 2) 80 200 ns t5 nalf asserted to nack asserted 0 ns t6 nalf deasserted to nack deasserted 0 ns notes: 1. maximum value only applies if there is room in the fifo and terminal count has not been received. ecp can stall by keeping nalf low. 2. nack is not considered asserted or deasserted until it is stable for a minimum of 75 to 130 ns. t1 t5 t6 t4 t3 t4 pd<7:0> nack nalf
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 378 smsc sch311x datasheet 29.6 ir timing figure 29.20 irda receive timing t1 t2 t2 t1 0 101 0 0 11011 data irrx n irrx t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 parameter min typ max units 1.4 1.4 1.4 1.4 1.4 1.4 1.4 2.71 3.69 5.53 11.07 22.13 44.27 88.55 s s s s s s s s s s s s s s pulse width at 115kbaud pulse width at 57.6kbaud pulse width at 38.4kbaud pulse width at 19.2kbaud pulse width at 9.6kbaud pulse width at 4.8kbaud pulse width at 2.4kbaud bit time at 115kbaud bit time at 57.6kbaud bit time at 38.4kbaud bit time at 19.2kbaud bit time at 9.6kbaud bit time at 4.8kbaud bit time at 2.4kbaud 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 notes: 1. receive pulse detection criteria: a received pulse is considered detected if the received pulse is a minimum of 1.41s. 2. irrx: l5, crf1 bit 0 = 1 nirrx: l5, crf1 bit 0 = 0 ( default )
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 379 revision 0.4 (06-03-05) datasheet figure 29.21 irda transmit timing t1 t1 t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t2 t2 parameter min 1.41 1.41 1.41 1.41 1.41 1.41 1.41 max 2.71 3.69 5.53 11.07 22.13 44.27 88.55 units s s s s s s s s s s s s s s pulse width at 115kbaud pulse width at 57.6kbaud pulse width at 38.4kbaud pulse width at 19.2kbaud pulse width at 9.6kbaud pulse width at 4.8kbaud pulse width at 2.4kbaud bit time at 115kbaud bit time at 57.6kbaud bit time at 38.4kbaud bit time at 19.2kbaud bit time at 9.6kbaud bit time at 4.8kbaud bit time at 2.4kbaud typ 1.6 3.22 4.8 9.7 19.5 39 78 8.68 17.4 26 52 104 208 416 t1 t2 t2 t1 0 10 1 0 0 11 0 11 data irtx n irtx notes: 1. irda @ 115k is hpsir compatible. irda @ 2400 will allow compatibility with hp95lx and 48sx. 2. irtx: l5, crf1 bit 1 = 1 (default) nirtx: l5, crf1 bit 1 = 0
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 380 smsc sch311x datasheet figure 29.22 amplitude shift-keyed ir receive timing t1 t2 t3 t4 t5 t6 parameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s modulated output bit time off bit time modulated output "on" modulated output "off" modulated output "on" modulated output "off" 1 1 1 1 notes: 1. irrx: l5, crf1 bit 0 = 1 nirrx: l5, crf1 bit 0 = 0 (default) mirrx, nmirrx are the modulated out p uts t1 t2 t3 t4 t5 t6 01010011011 data irrx n irrx mirrx nmirrx
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 381 revision 0.4 (06-03-05) datasheet figure 29.23 amplitude shift-keyed ir transmit timing 29.7 serial irq timing figure 29.24 setup and hold time name description min typ max units t1 ser_irq setup time to pci_clk rising 7 nsec t2 ser_irq hold time to pci_clk rising 0 nsec t1 t2 t3 t4 t5 t6 parameter min typ max units 0.8 0.8 0.8 0.8 1.2 1.2 1.2 1.2 s s s s s s modulated output bit time off bit time modulated output "on" modulated output "off" modulated output "on" modulated output "off" 1 1 1 1 notes: 1. irtx: l5, crf1 bit 1 = 1 (default) nirtx: l5, crf1 bit 1 = 0 mirtx, nmirtx are the modulated outputs t1 t2 t3 t4 t5 t6 01010 011011 data irtx n irtx mirtx nmirtx t2 t1 pci_clk ser_irq
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 382 smsc sch311x datasheet 29.8 uart interface timing figure 29.25 serial port data 29.9 keyboard/mouse interface timing figure 29.26 keyboard/mouse receive/send data timing name description min typ max units t1 serial port data bit time t br 1 nsec t br is 1/baud rate. the baud rate is programmed through the divisor latch registers. baud rates have percentage errors indicated in the ?baud rate? table in the ?serial port? section. name description min typ max units t1 time from data transition to falling edge of clock (receive) 525sec t2 time from rising edge of clock to data transition (receive) 5 t4-5 sec t3 duration of clock inactive (receive/send) 30 50 sec t4 duration of clock active (receive/send) 30 50 sec t5 time to keyboard inhibit after clock 11 to ensure the keyboard does not start another transmission (receive) >0 50 sec t6 time from inactive to active clock transition, used to time when the auxiliary device samples data (send) 525sec data (5-8 bits) t1 data txd1, 2 start parity stop (1-2 bits) kclk/ mclk kdat/ mdat start bit bit 0 bit 7 clk 1 clk 2 clk 9 clk 10 t1 t6 t4 t3 clk 11 t5 parity bit stop bit t2
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 383 revision 0.4 (06-03-05) datasheet 29.10 resume reset signal generation nrsmrst signal is the reset output for the ich resume well. this signal is used as a power on reset signal for the ich. sch311x detects when vtr voltage raises above vtrip , provides a delay before generating the rising edge of nrsmrst. see definition of vtrip on page 383 . this delay, treset_delay, ( t1 on page 383 ) is nominally 32ms, starts when vtr voltage rises above the vtrip trip point. if the vtr voltage falls below vtrip the during treset_delay then the following glitch protection behavior is im plemented:. when the vtr voltage rises above vtrip , nrsmrst will remain asserted the full treset _delay after which nrsmrst is deasserted. on the falling edge there is minimal delay, treset_fall. timing and voltage parameters are shown in figure 29.27 and table 29.1 . figure 29.27 resume reset sequence application note: the 5 volt standby power supply must power up before or simultaneous with vtr, and must power down simultaneous with or after vtr (from ich2 data sheet.) sch311x does not have a 5 volt standby power supply input and does not respond to incorrect 5 volt standby power - vtr sequencing. table 29.1 resume reset timing name description min typ max units notes t1 treset_delay: vtr active to nrsmrst inactive 140 350 560 msec t2 treset_fall: vtr inactive to nrsmrst active (glitch width allowance) 100 nsec t3 treset_rise 100 nsec v trip vtr low trip voltage 2.7 2.8 2.9 v nrsmrst t1 max min vtrip t2 t3 vtr (3.3v)
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 384 smsc sch311x datasheet 29.11 nledx timing figure 29.28 nledx timing 29.12 pwm outputs the following section shows the timing for the pwm[1:3] outputs. figure 29.29 pwmx output timing name description min typ max units t1 period 1 or 2 2 5.88 1 sec t2 blink on time 0 0.5 2 1.52 1 sec 1. these max values are due to internal ring oscillator. if 1hz blink rate is selected for led1 pin, the range will vary from 0.33hz to 1.0hz. if 0.5hz blink rate is selected for led1 pin, the range will vary from 0.17hz to 0.5hz. 2. the blink rate is programmed through bits[1:0] in ledx register. when bits[1:0]=00, led is off. bits[1:0]=01 indicates led blink at 1hz rate with a 50% duty cycle (0.5 sec on, 0.5 sec off). bits[1:0]=10 indicates led blink at ? hz rate with a 25% duty cycle (0.5 sec on , 1.5 sec off). when bits[1:0]=11, led is on. table 29.2 timing for pwm[1:3] outputs name description min typ max units t1 pwm period (note 1) - low frequency option - high frequency option 11.4 10.7 90.9 42.7 msec usec t2 pwm high time (note 2) 0 99.6 % notes: 1. this value is programmable by the pwm frequency bits located in the frfx registers. 2. the pwm high time is based on a percentage of the total pwm period (min=0/256*t pwm , max =255/256*t pwm ). during spin-up the pwm high time can reach a 100% or full on. (t pwm = t1). t2 t1 nledx t1 t2 fanx
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 385 smsc sch311x datasheet chapter 30 package outline figure 30.1 128 pin vtqfp package outline; 14x14x1.0 body, 2mm footprint - see spec front page for revision history -- notes: 1. all dimensions are in millimeter. 2. true position spread tolerance of each lead is 0.035mm maximum. 3. dimensions "d1" and "e1" do not include mold protrusions. maximum allowed protrusion is 0.25 mm per side. 4. dimension "l" is measured at the gauge plane, 0.25mm above the seating plane. 5. details on pin 1 identifier are optional but must be located within the zone indicated. top view e1/4 d d1 e1 e 3 d1/4 5 std compliance i nte rp re t dim an d t ol p e r as me y 14.5m - 1994 dwg number print with "s cale to fit" do not scale drawing material finish approved checked dra wn scale sheet rev 80 arkay drive haup pauge, ny 11 788 usa angular unles s otherwi se specified dimensions are i n millimeters and tolerances are: decimal x.x x.xx x.xxx third angle projection name date title revision date description revision history released by jedec: ms-026 (d) package outline 1:1 - - s.k.iliev s.k.iliev s.k.iliev 12/17/04 12/17/04 12/17/04 128 vtqfp-14x14x1.0mm body-0.4mm pitch mo-128-vtqfp-14x14x1.0 1 of 1 c 1 0.1 0.05 0.025 0.25 r1 r2 gauge plane 0-7 4 detail "a" b e 2 3 see detail "a" side view a2 c a1 ccc c a seating plane c l l1 3-d view
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 386 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 387 revision 0.4 (06-03-05) datasheet appendix a adc voltage conversion table a.1 analog-to-digital voltage conversions for hardware monitoring block input voltage a/d output +12 v +5 v note 30.1 +3.3 v note 30.2 v ccpin decimal binary <0.062 <0.026 <0.0172 <0.012 0 0000 0000 0.062?0.125 0.026?0.052 0.017?0.034 0.012?0.023 1 0000 0001 0.125?0.188 0.052?0.078 0.034?0.052 0.023?0.035 2 0000 0010 0.188?0.250 0.078?0.104 0.052?0.069 0.035?0.047 3 0000 0011 0.250?0.313 0.104?0.130 0.069?0.086 0.047?0.058 4 0000 0100 0.313?0.375 0.130?0.156 0.086?0.103 0.058?0.070 5 0000 0101 0.375?0.438 0.156?0.182 0.103?0.120 0.070?0.082 6 0000 0110 0.438?0.500 0.182?0.208 0.120?0.138 0.082?0.093 7 0000 0111 0.500?0.563 0.208?0.234 0.138?0.155 0.093?0.105 8 0000 1000 ? ? ? ? ? ? 4.000?4.063 1.666?1.692 1.100?1.117 0.749?0.761 64 (1/4 scale) 0100 0000 ? ? ? ? ? ? 8.000?8.063 3.330?3.560 2.200?2.217 1.499?1.511 128 (1/2 scale) 1000 0000 ? ? ? ? ? ? 12.000?12.063 5.000?5.026 3.300?3.317 2.249?2.261 192 (3/4 scale) 1100 0000 ? ? ? ? ? ? 15.312?15.375 6.380?6.406 4.210?4.230 2.869?2.881 245 1111 0101 15.375?15.437 6.406?6.432 4.230?4.245 2.881?2.893 246 1111 0110 15.437?15.500 6.432?6.458 4.245?4.263 2.893?2.905 247 1111 0111 15.500?15.563 6.458?6.484 4.263?4.280 2.905?2.916 248 1111 1000 15.625?15.625 6.484?6.510 4.280?4.300 2.916?2.928 249 1111 1001 15.625?15.688 6.510?6.536 4.300?4.314 2.928?2.940 250 1111 1010 15.688?15.750 6.536?6.562 4.314?4.330 2.940?2.951 251 1111 1011 15.750?15.812 6.562?6.588 4.331?4.348 2.951?2.964 252 1111 1100 15.812?15.875 6.588?6.615 4.348?4.366 2.964?2.975 253 1111 1101 15.875?15.938 6.615?6.640 4.366?4.383 2.975?2.987 254 1111 1110 >15.938 >6.640 >4.383 >2.988 255 1111 1111
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 388 smsc sch311x datasheet note 30.1 the 5v input is a +5v nominal inputs. 2.5v input is a 2.5v nominal input. note 30.2 the vcc, vtr, and vbat inputs are +3.3v nominal inputs. vcc and vtr are nominal 3.3v power supplies. vbat is a nominal 3.0v power supply.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 389 revision 0.4 (06-03-05) datasheet appendix b example fan circuits the following figures show examples of circuitry on the board for the pwm outputs, tachometer inputs, and remote diodes. figure b.1 shows how the part can be used to control four fans by connecting two fans to one pwm output. note: these examples represent the minimum requi red components. some designs may require additional components. figure b.1 fan drive circuitry for low frequency option (apply to pwm driving two fans) mmbt3904 mmbt2222 mmbt2222 10 10 2.2k 1k 3.3v 3.3v fan1 fan2 m m 12v pwmx empty empty
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 390 smsc sch311x datasheet figure b.2 fan drive circuitry for low freque ncy option (apply to pwm driving one fan) figure b.3 fan tachometer circuitry (apply to each fan) mmbt2222 0 470 3.3v fan m 12v pwmx empty note : for fans controlled directly by a pwm, it is suggested to implement the optional diode (d1) to protect the tachometer input from large voltage spikes generated by the fan. 10k 3.3v tach output from fan tach input d1 in4148
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 391 revision 0.4 (06-03-05) datasheet figure b.4 remote diode (apply to remote2 lines) notes: 1. 2.2nf cap is optional and should be placed close to the sch311x f used. 2. the voltage at pwm3 must be at least 2.0v to avoid triggering address enable. 3. the remote diode + and remote diode - tracks sh ould be kept close together, in parallel with grounded guard tracks on each side. using wide tracks will help to mi nimize inductance and reduce noise pickup. a 10 mil track minimum widt h and spacing is recommended. see figure b.5, "suggested minimum track width and spacing". figure b.5 suggested minimum track width and spacing remote diode + remote diode - 2.2nf external temperature sensing diode (mmbt3904) gnd gnd d+ d- 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 392 smsc sch311x datasheet
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 393 revision 0.4 (06-03-05) datasheet appendix c test mode the sch311x provides board test capability through the implementation of one xnor chain and one xor chain. the xnor chain is dedicated to the super i/o portion and the hardware monitoring block of the device. c.1 xnor-chain test mode overview xnor-chain test structure allows users to confirm t hat all pins are in contact with the motherboard during assembly and test operations. see figure c.1 . when the chip is in the xnor chain test mode, setting the state of any of the input pins to the opposite of its current state will cause the output of the chain to toggle. the xnor-chain test structure must be activated to perform these tests. when the xnor-chain is activated, the sch311x pin functions are disconnec ted from the device pins, which all become input pins except for one output pin at the end of xnor-chain. the tests that are performed when the xnor-chain test structure is activated require the board-level test hardware to control the device pins and observe the results at the xnor-chain output pin. figure c.1 xnor-chain test structure c.1.1 board test mode board test mode can be entered as follows: on the rising (deasserting) edge of pci_reset#, drive lframe# low and drive lad[0] low. exit board test mode as follows: on the rising (deasserting) edge of pci_reset#, drive either lframe# or lad[0] high. see pme_sts1 for a description of this board test mode. the pci_reset# pin is not include d in the xnor-chain. the xnor -chain output pin# is txd1. see the following subsections for more details. pin list of xnor chain pins 1-128 on the chip are inputs to the first xnor chain, with the exception of the following: all power supply pins - hvtr, hvss, vcc, vtr, and vbat vss and avss all analog inputs: remote2-, remote2+, remote1-, remote1+, vccp_in, +12v_in, +5v_in, +2.5v_in i/o#1 i/o#2 i/o#3 i/o#n xnor out
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet revision 0.4 (06-03-05) 394 smsc sch311x datasheet txd1 this is the chain output. pci_reset#. to put the chip in the first xnor chain test mode, tie lad0 and lframe# low. then toggle pci_reset# from a low to a high stat e. once the chip is put into xnor chain test mode, lad0 and lframe# become part of the chain. to exit the sio xnor chain test mode tie lad0 or lframe# high. then toggle pci_reset# from a low to a high state. a vcc por will also cause th e xnor chain test mode to be exited. to verify the test mode has been exited, observe the output at txd1. toggling any of the input pins in the chain should not cause its state to change. setup of super i/o xnor chain warning: ensure power supply is off during setup. connect the vss, the avss, hvss pins to ground. connect the vcc, the vtr, and hvtr pins to 3.3v. connect an oscilloscope or voltmeter to txd1. all other pins should be tied to ground. testing 1. turn power on. 2. with lad0 and lframe# low, bring pci_reset# high. the chip is now in xnor chain test mode. at this point, all inputs to the first xnor chain are low. the output, on txd1 should also be low. refer to initial config on ta b l e c . 1 . 3. bring pin 110 high. the output on txd1 (pin66) should go toggle. refer to step one in table c.1 . 4. in descending pin order, bring each input high. the output should switch states each time an input is toggled. continue until all inputs are high. the output on txd1 should now be low. refer to end config in ta b l e c . 1 . 5. the current state of the chip is now represented by initial config in ta b l e c . 2 . 6. each input should now be brought low, starting at pin one and continuing in ascending order. continue until all inputs are low. the output on txd1 should now be low. refer to table c.2 . 7. to exit test mode, tie lad0 (pin 19) or lframe# high, and toggle pci_reset# from a low to a high state.
lpc io with 8042 kbc, reset generation, hwm and multiple serial ports datasheet smsc sch311x 395 revision 0.4 (06-03-05) datasheet table c.1 toggling inputs in descending order pin 128 pin 109 pin 108 pin 107 pin 106 pin ... pin 1 output pin 66 initial config llll l l l h step 1 hlll l l l l step 2 hh l l l l l h step 3 hh h l l l l l step 4 hhhh l l l h step 5 hhhh h l l l ? ?? ? ? ? ? ? ? step n hhhh h h l h end config hhhh h h h l table c.2 toggling inputs in ascending order pin 1 pin 2 pin 3 pin 4 pin 5 pin ... pin 128 output pin 66 initial config hhhhh h h l step 1 lhhhh h h h step 2 l lhhh h h l step 3 lllhh h h h step 4 llllh h h l step 5 lllll h h h ????? ? ? ? step n lllll l h h end config lllll l l h

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