RT9514 1 ds9514-01 april 2011 www.richtek.com features z z z z z 18v maximum rating for ac adapter z z z z z internal integrate p-mosfets z z z z z ac adapter power good status indicator z z z z z charge status indicator z z z z z under voltage protection z z z z z over voltage protection z z z z z automatic recharge feature z z z z z small 10-lead wdfn package z z z z z thermal feedback optimizing charge rate z z z z z rohs compliant and halogen free pin configurations applications z digital cameras z cellular phones z personal data assistants (pdas) z mp3 players z handheld pcs ordering information general description the RT9514 is a fully integrated low cost single-cell li- ion battery charger ic ideal for portable applications. the RT9514 is capable of being powered up from ac adapter. the RT9514 enters sleep mode when ac adapter is removed. the RT9514 optimizes the charging task by using a control algorithm including preconditioning mode, fast charge mode and constant voltage mode. the charging task is terminated as the charge current drops below the preset threshold. the ac adapter charge current can be programmed up to 1a with an external resister. the internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures. the RT9514 features 18v maximum rating voltages for ac adapter. the other features are under voltage protection, over voltage protection for ac adapter supply. (top view) wdfn-10l 3x3 note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. linear single cell li-ion battery charger ic acin nc gnd batt nc iseta nc 9 8 7 9 1 2 3 4 5 10 gnd chg_s pgood en 11 typical application circuit RT9514 1uf ac adapter acin gnd batt + battery pack 1 3 4 5, exposed pad (11) 10 chg_s pgood to system to system 8 en chip shutdown chip enable iseta r set 6 RT9514 package type qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free)
RT9514 2 ds9514-01 april 2011 www.richtek.com functional pin description pin no. pin name pin function 1 acin wall adaptor charge input supply. 2, 7, 9 nc no internal connection. 3 chg_s charge status indicator output (open drain). 4 pgood power good indicator output (open drain). 5 gnd ground. 6 iseta wall adaptor supply charge current set point. 8 en charge enable input (activ e low). 10 batt battery charge current output. 11 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. function block diagram precharge + - 2.5v recharge + - 2.5v v ref 2.5v 0.25v 0.5v + - charge done 0.25v logic + - charge disable 0.9v 1ua precharge comparator recharge comparator acin iseta batt tcrmination comparator vcc chg_s pgood en charge input selection ovp + - 2.5v ovp comparator acin pfet sense fet gnd loop controller v ref 125 c
RT9514 3 ds9514-01 april 2011 www.richtek.com any state if v in < uvlo or v in > ovp or en = high or v in < batt power off state pfet = off no batt > 2.8v yes pre-chg state i pchg = 0.1 x i chg_f fast-chg state i chg_f = 500ma @r set = 1.5k charge done state ichg = 0a no yes yes operation state diagram for charger function (RT9514) yes batt < 4.1v no no uvlo batt ichg < 0.1 x i chg_f
RT9514 4 ds9514-01 april 2011 www.richtek.com absolute maximum ratings (note 1) z ac input voltage ----------------------------------------------------------------------------------------------------------- ? 0.3v to 18v z en input voltage ----------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z output current ------------------------------------------------------------------------------------------------------------- 1.2a z power dissipation, p d @ t a = 25 c wdfn-10l 3x3 ------------------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wdfn-10l 3x3, ja ------------------------------------------------------------------------------------------------------- 60 c/w wdfn-10l 3x3, jc ------------------------------------------------------------------------------------------------------- 8.2 c/w z lead temperature (soldering, 10 se c.) ------------------------------------------------------------------------------- 260 c z junction te mperature ---------------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v electrical characteristics (acin = 5v, t a = 25 c, unless otherwise specification) to be continued parameter symbol test conditions min typ max units supply input acin u vlo threshold voltage v uv lo rising -- 3 3.5 v acin uvlo hysteresis v uv lo_hys 50 80 120 mv acin standby current i stby v batt = 4.5v -- 300 500 ua acin shutdown current i shdn v en = high -- 50 100 ua acin quiescent current i q v acin = 4v, v batt = 3v -- 150 250 ua batt sleep leakage current i sleep v acin = 4 v, v batt = 4.5v -- -- 10 ua voltage regulation batt regulation voltage v re g i batt = 60ma 4.168 4.21 4.252 v r egulation voltage accuracy ? 1 -- +1 % acin mosfet r ds(on )_aci n i batt = 500ma -- 600 -- m current regulation iseta set volta ge (fast charge phase) v iseta v batt = 3.5v 2.45 2.5 2.55 v full charge setting range i ch g_f 100 -- 1200 ma ac charge current accuracy i ch g_f v batt = 3.8v, r iset = 1.5k -- 500 -- ma recommended operating conditions (note 4) z acin input voltage range ----------------------------------------------------------------------------------------------- 4.5v to 6v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c
RT9514 5 ds9514-01 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (4 layers, 2s2p) of jedec 51-7 thermal measurement standard. the case point of jc is on the expose pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max units precharge bat t pre-charge rising threshold v prech 2.6 2.8 3 v batt pre-charge threshold h y steresis v pre ch 50 100 200 mv pre-charge current i pchg v batt = 2v 8 10 12 % r echarge threshold batt re-charge falling threshold h ysteresis v rec h_ l v reg ? v batt 60 100 170 mv charge termination detection termination current ratio (default) i ter m v batt = 4.2v -- 10 -- % logic input/output chg_s pull down voltage v chg_s tbd, i chg_s = 5ma -- 65 -- mv pgood pull down voltage v pgood tbd, i pgood = 5ma -- 220 -- mv en threshold logic-high voltage v ih 1.5 -- -- v logic-low voltage v il -- -- 0.4 v en pin input current i en v en = 2v -- -- 2 ua protection thermal regulation -- 125 -- c ovp set internal default -- 6.5 -- v
RT9514 6 ds9514-01 april 2011 www.richtek.com typical operating characteristics acin ovp time (1ms/div) v acin (10v/div) v acin = 5v to 8v to 5v, v batt = 3.7v v batt (5v/div) i chg_s (1a/div) v chg_s (5v/div) acin ovp time (1ms/div) v acin (10v/div) v acin = 0v to 10v, v batt = 3.7v v batt (5v/div) i chg_s (1a/div) v chg_s (5v/div) i chg_s (1a/div) acin power off time (250us/div) v acin (5v/div) v chg_s (2v/div) v batt (5v/div) v batt = 3.7v v chg_s (2v/div) i chg_s (1a/div) acin power on time (250us/div) v acin (5v/div) v batt (5v/div) v batt = 3.7v
RT9514 7 ds9514-01 april 2011 www.richtek.com the parameter k = 300 ; v iseta = 2.5v (typ.). r set is the resistor connected between the iseta and gnd. pre- charge current setting during a charge cycle if the battery voltage is below the vprech threshold, the RT9514 applies a pre-charge mode to the battery. this feature revives deeply discharged cells and protects battery life. the RT9514 internally determines the pre-charge rate as 10% of the fast-charge current. battery voltage regulation the RT9514 monitors the battery voltage through the batt pin. once the battery voltage level closes to the vreg threshold, the RT9514 voltage enters constant phase and the charging current begins to taper down. when battery voltage is over the vreg threshold, the RT9514 will stop charge and keep to monitor the battery voltage. however, when the battery voltage decreases 100mv below the v reg , it will be recharged to keep the battery voltage. charge status outputs the open-drain chg_s and pgood outputs indicate various charger operations as shown in the following table. these status pins can be used to drive leds or communicate to the host processor. note that on indicates the open-drain transistor is turned on and led is bright. application information automatically power source selection the RT9514 is a battery charger ic which is designed for li-ion battery with 4.21v rated voltage. ac mode : when the ac input voltage (acin) is higher than the uvp voltage level and lower than the ovp protection (3v), the RT9514 will enter ac mode. in the ac mode, acin p-mosfet is turned on. sleep mode : the RT9514 will enter sleep mode when ac input voltage are removed. this feature provides low leakage current from the battery during the absence of input supply. acin over voltage protection the ac input voltage is monitored by an internal ovp comparator. the comparator has an accurate reference of 2.5v from the band-gap reference. the ovp threshold is set by the internal resistive. the protection threshold is set to 6.5v. when the input voltage exceeds the threshold, the comparator outputs a logic signal to turn off the power p-mosfet to prevent the high input voltage from damaging the electronics in the handheld system. when the input over oltage condition is removed (acin < 6v), the comparator re-enables the output by running through the soft-start. iseta chg_f set v i = k r figure 1. charge current setting 0 200 400 600 800 1000 1200 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 charge current (ma) r set (k ) charge state chg_s pgood acin ch arge on on charge done off on fast-charge current setting the RT9514 offers iseta pin to determine the charge current from 100ma to 1.2a. the charge current can be calculated as following equation.
RT9514 8 ds9514-01 april 2011 www.richtek.com temperature regulation in order to maximize the charge rate, the RT9514 features a junction temperature regulation loop. if the power dissipation of the ic results in a junction temperature greater than the thermal regulation threshold (125 c), the RT9514 throttles back on the charge current in order to maintain a junction temperature around the thermal regulation threshold (125 c). the RT9514 monitors the junction temperature, t j , of the die and disconnects the battery from the input if t j exceeds 125 c. this operation continues until junction temperature falls below thermal regulation threshold (125 c) by the hysteresis level. this feature prevents the chip from damaging. selecting the input and output capacitors in most applications, the most important is the high- frequency decoupling capacitor on the input of the RT9514. a 1uf ceramic capacitor, placed in close proximity to input pin and gnd pin is recommended. in some applications depending on the power supply characteristics and cable length, it may be necessary to add an additional 10uf ceramic capacitor to the input. the RT9514 requires a small output capacitor for loop stability. a 1uf ceramic capacitor placed between the batt pin and gnd is typically sufficient. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) - t a ) / ja where t j(max) is the maximum operation junction temperature 125 c, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification, where t j(max) is the maximum junction temperature of the die (125 c) and t a is the ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wdfn-10l 3x3 packages, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-10l 3x3 packages the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for wdfn-10l 3x3 package, the figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wdfn-10l 3x3 four layers pcb figure 2. derating curves for RT9514 package layout considerations for the best performance of the RT9514, the following pcb layout guidelines must be strictly followed. ` place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. ` keep the main power traces as wide and short as possible. ` the connection of r seta should be isolated from other noisy traces. the short wire is recommended to prevent emi and noise coupling. ` connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection.
RT9514 9 ds9514-01 april 2011 www.richtek.com figure 3. pcb layout guide acin nc gnd batt nc iseta nc 9 8 7 9 1 2 3 4 5 10 gnd chg_s pgood en 11 c2 r seta c1 v acin gnd gnd v batt connect the exposed pad to a ground plane. input/output capacitors must be placed as close as possible to the input/output pins. place the r seta as close as possible to the iseta pin. the connection of r seta should be isolated from other noisy traces.
RT9514 10 ds9514-01 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
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