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general description the max3670 is a low-jitter 155mhz/622mhz reference clock generator ic designed for system clock distribution and frequency synchronization in oc-48 and oc-192 sonet/sdh and wdm transmission systems. the max3670 integrates a phase/frequency detector, an operational amplifier (op amp), prescaler dividers and input/output buffers. using an external vco, the max3670 can be configured easily as a phase-lock loop with bandwidth programmable from 15hz to 20khz. the max3670 operates from a single +3.3v or +5.0v supply, and dissipates 150mw (typ) at 3.3v. the operat- ing temperature range is from -40? to +85?. the chip is available in a 5mm ? 5mm, 32-pin qfn package. applications oc-12 to oc-192 sonet/wdm transport systems clock jitter clean-up and frequency synchronization frequency conversion system clock distribution features ? single +3.3v or +5.0v supply ? power dissipation: 150mw at +3.3v supply ? external vco center frequencies (f vco ): 155mhz to 670mhz ? reference clock frequencies: f vco , f vco /2, f vco /8 ? main clock output frequency: f vco ? optional output clock frequencies: f vco , f vco /2, f vco /4, f vco /8 ? low intrinsic jitter: < 0.4ps rms ? loss-of-lock indicator ? pecl clock output interface max3670 low-jitter 155mhz/622mhz clock generator ________________________________________________________________ maxim integrated products 1 ordering information max3670 155mhz 142 142 100 332 500k 500k 3.3v 3.3v 4700pf 4700pf 0.01 f setup for 10khz loop bandwidth 3.3v n.c. n.c. n.c. 142 142 refclk+ refclk- vcoin+ vcoin- vc opamp- opamp+ polar gnd mout+ mout- rsel vsel gsel1 gsel2 gsel3 vco k vco = 25khz/v 155mhz represents a controlled-impedance transmission line. vccd max3892 16:1 serializer typical application circuit 19-2166; rev 2; 9/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. part temp range pin-package max3670egj -40c to +85c 32 qfn-ep* MAX3670ETJ+ -40c to +85c 32 thin qfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad.
max3670 low-jitter 155mhz/622mhz clock generator 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.3v ?0% or v cc = +5.0v ?0%, t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless other- wise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage range..............................................-0.5v to +7v voltage range at c2+, c2-, thadj, cth, gsel1, gsel2, gsel3, lol , rsel, refclk-, refclk+, vsel, vcoin+, vcoin-, vc, polar, psel1, psel2, comp, opamp+, opamp- ..................................-0.5v to (v cc + 0.5v) continuous power dissipation (t a = +70?) 32 qfn (derate 33.3mw/? above +70?) .....................2.7w 32 thin qfn (derate 34.5mw/? above +70?)..............2.8w pecl output current (mout+, mout-, pout+, pout-).................................................56ma operating temperature range ...........................-40? to +85? storage temperature range. ............................-65? to +160? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply current i cc (note 2) 48 72 ma input specifications (refclk? vcoin? input high voltage v ih v cc - 1.16 v cc - 0.88 v input low voltage v il v cc - 1.81 v cc - 1.48 v input bias voltage v cc - 1.3 v common-mode input resistance 7.5 11.5 17.5 k differential input resistance 12.8 21.0 32.5 k differential input voltage swing ac-coupled 300 1900 mvp-p pecl output specifications 0? to +85? v cc - 1.025 v cc - 0.88 output high voltage v oh -40? to 0? v cc - 1.085 v cc - 0.88 v 0? to +85? v cc - 1.81 v cc - 1.62 output low voltage v ol -40? to 0? v cc - 1.83 v cc - 1.556 v ttl specifications output high voltage v oh sourcing 20? 2.4 v cc v output low voltage v ol sinking 2ma 0.4 v
max3670 low-jitter 155mhz/622mhz clock generator _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc = +3.3v ?0% or v cc = +5.0v ?0%, t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless other- wise noted.) (note 1) parameter symbol conditions min typ max units operational amplifier specifications (note 3) v cc = +3.3v ?0% 0.3 v cc - 0.3 op amp output voltage range v o v cc = +5.0v ?0% 0.5 v cc - 0.5 v op amp input offset voltage | v os | 3mv op amp open-loop gain a ol 90 db phase frequency detector (pfd)/charge-pump (cp) specifications (note 4) high gain 16 20 24.4 full-scale pfd/cp output current | i pd | low gain 4 5 6.2 ? high gain 0.80 pfd/cp offset current low gain 1.08 % | i pd | ac electrical characteristics (v cc = +3.3v ?0% or v cc = +5.0v ?0%, t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless other- wise noted.) (note 5) parameter symbol conditions min typ max units clock output specifications clock output frequency 670 mhz f vco = 622mhz 622/311/ 155/78 optional clock output frequency f vco = 155mhz 155/78/ 38/19 mhz clock output rise/fall time measured from 20% to 80% 280 ps clock output duty cycle (note 6) 45 55 % noise specifications random noise voltage at loop- filter output v noise freq > 1khz (note 7) 1.14 ? rms / hz spurious noise voltage at loop- filter output (note 8) 50 ? rms power-supply rejection at loop- filter output psr (note 9) 30 db reference clock input specifications reference clock frequency 622/ 155/78 670 mhz reference clock duty cycle 30 70 %
note 1: specifications at -40? are guaranteed by design and characterization. note 2: measured with pecl outputs unterminated. note 3: opamp specifications met with 10k load to ground or 5k load to v cc (polar = 0 and polar = v cc ). note 4: pfd/cp currents are measured from pins opamp+ to opamp-. see table 3 for gain settings. note 5: ac characteristics are guaranteed by design and characterization. note 6: measured with 50% vco input duty cycle. note 7: random noise voltage at op amp output with 800k resistor connected between vc and opamp-, pfd/cp gain (k pd ) = 5?/ui, and polar = 0. measured with the pll open loop and no refclk or vco input. note 8: spurious noise voltage due to pfd/cp output pulses measured at op amp output with r 1 = 800k , k pd = 5?/ui, and compare frequency 400 times greater than the higher-order pole frequency (see design procedure ). note 9: psr measured with a 100mvp-p sine wave on v cc in a frequency range from 100hz to 2mhz. external resistors r 1 matched to within 1%, external capacitors c 1 matched to within 10%. measured closed loop with pll bandwidth set to 200hz. note 10: the pll 3db bandwidth is adjusted from 15hz to 20khz by changing external components r 1 and c 1 , by selecting the inter- nal programmable divider ratio and phase-detector gain. measured with vco gain of 220ppm/v and c 1 limited to 2.2?. note 11: measured at bw = 20khz. when input jitter frequency is above pll transfer bandwidth (bw), the jitter transfer function rolls off at -20db/decade. max3670 low-jitter 155mhz/622mhz clock generator 4 _______________________________________________________________________________________ ac electrical characteristics (continued) (v cc = +3.3v ?0% or v cc = +5.0v ?0%, t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless other- wise noted.) (note 5) parameter symbol conditions min typ max units pll specifications pll jitter transfer bandwidth bw (note 10) 15 20,000 hz jitter transfer function f jitter bw (note 11) 0.1 db op amp specification unity-gain bandwidth 7 mhz vco input specification vco input frequency f vco 622/155 670 mhz vco input slew rate 0.5 v/ns
max3670 low-jitter 155mhz/622mhz clock generator _______________________________________________________________________________________ 5 20 30 40 50 60 supply current vs. temperature max3670 toc01 temperature ( c) supply current (ma) -40 20 40 -20 0 60 80 5.0v 3.3v 150 170 160 180 190 200 210 220 230 240 250 260 270 280 max3670 toc02 temperature ( c) edge speed 20%-80% (ps) edge speed vs. temperature -40 0 40 20 -20 60 80 155.52mhz 622.08mhz -60 -40 -50 -20 -30 -10 0 1k 100k 10k 1m 10m power-supply rejection vs. frequency max3670 toc03 frequency (hz) supply rejection (db) bw = 1khz hop = 5khz loop filter output 200mv/ div 500ps/div 622mhz clock output (differential output) max3670 toc04 200mv/ div 2.0ns/div 155mhz clock output (differential output) max3670 toc05 typical operating characteristics (t a = +25?, unless otherwise noted.)
max3670 low-jitter 155mhz/622mhz clock generator 6 _______________________________________________________________________________________ pin description pin name function 1 c2+ positive filter input. external capacitor connected between c2+ and c2- used for setting the higher- order pole frequency (see setting the higher-order poles ). 2 c2- negative filter input. external capacitor connected between c2+ and c2- used for setting the higher- order pole frequency (see setting the higher-order poles ). 3, 9, 15 vccd positive digital supply voltage 4 thadj threshold adjust input. used to adjust the loss-of-lock threshold (see lol setup ). 5 cth threshold capacitor input. a capacitor connected between cth and ground used to control the loss- of-lock conditions (see lol setup ). 6 gsel1 gain select 1 input. three-level pin used to set the phase-detector gain (k pd ) and the frequency- divider ratio (n 2 ) (see table 3). 7 gsel2 gain select 2 input. three-level pin used to set the phase-detector gain (k pd ) and the frequency- divider ratio (n 2 ) (see table 3). 8 gsel3 gain select 3 input. three-level pin used to set the phase-detector gain (k pd ) and the frequency- divider ratio (n 2 ) (see table 3). 10 lol loss-of-lock. lol signals a ttl low when the reference frequency differs from the vco frequency. lol signals a ttl high when the reference frequency equals the vco frequency. 11 gnd supply ground 12 rsel reference clock select input. three-level pin used to set the predivider ratio (n 3 ) for the input reference clock (see table 1). 13 refclk positive reference clock input 14 refclk- negative reference clock input 16 vsel vco clock select input. three-level pin used to set the predivider ratio (n 1 ) for the input vco clock (see table 2). 17 pout- negative optional clock output, pecl 18 pout+ positive optional clock output, pecl 19, 22 vcco positive supply voltage for pecl outputs 20 mout- negative main clock output, pecl 21 mout+ positive main clock output, pecl 23 vcoin- negative vco clock input 24 vcoin+ positive vco clock input 25 vc control voltage output. the voltage output from the op amp that controls the vco. 26 polar polarity control input. polarity control of op amp input. polar = gnd for vcos with positive gain transfer. polar = v cc for vcos with negative gain transfer. 27 psel1 optional clock select 1 input. used to set the divider ratio for the optional clock output (see table 4). 28 psel2 optional clock select 2 input. used to set the divider ratio for the optional clock output (see table 4). 29 vcca positive analog supply voltage for the charge pump and op amp 30 comp compensation control input. op amp compensation reference control input. comp = gnd for vcos whose control pin is v cc referenced. comp = v cc for vcos whose control pin is gnd referenced. 31 opamp- negative op amp input (polar = 0), positive op amp input (polar = 1) 32 opamp+ positive op amp input (polar = 0), negative op amp input (polar = 1) ep exposed pad. the exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance.
detailed description the max3670 contains all the blocks needed to form a pll except for the vco, which must be supplied sepa- rately. the max3670 consists of input buffers for the ref- erence clock and vco, input and output clock-divider circuitry, lol detection circuitry, gain-control logic, a phase-frequency detector and charge pump, an op amp, and pecl output buffers. this device is designed to clean up the noise on the reference clock input and provide a low-jitter system clock output. input buffer for reference clock and vco the max3670 contains differential inputs for the refer- ence clock and the vco. these inputs can be dc-cou- pled and are internally biased with high impedance so that they can be ac-coupled (figure 1 in the interface schematic section). a single-ended vco or reference clock can also be applied. input and output clock-divider circuitry the reference clock and vco input buffers are followed by a pair of clock dividers that prescale the input fre- quency of the reference clock and vco to 77.76mhz. max3670 low-jitter 155mhz/622mhz clock generator _______________________________________________________________________________________ 7 max3670 vco k vco c3 r3 thadj cth vc comp polar opamp- opamp+ c1 r1 c1 r1 opamp lol refclk+ refclk- rsel vsel vcoin+ vcoin- gsel1 gsel2 gsel3 psel1 psel2 pout- pout+ mout+ c2+ c2- mout- pecl pecl div (n1) div (n2) div 1/2/4/8 gain-control logic lol div (n3) div (n2) pfd/cp k pd functional diagram
max3670 depending on the input clock frequency of 77.76mhz, 155.52mhz, or 622.08mhz, the clock divider ratio must be set to 1, 2, or 8, respectively. the pout output buffer is preceded by a clock divider that scales the main clock output by 1, 2, 4, or 8 to provide an optional clock. lol detection circuitry the max3670 incorporates a loss-of-lock ( lol ) monitor that consists of an xor gate, filter, and comparator with adjustable threshold (see ?ol setup?in the applications section). a loss-of-lock condition is sig- naled with a ttl low when the reference clock frequen- cy differs from the vco frequency. gain-control logic the gain-control circuitry facilitates the tuning of the loop bandwidth by setting phase-detector gain and fre- quency-divider ratio. the gain-control logic can be pro- grammed to divide from 1 to 1024, in binary multiples, and to adjust the phase detector gain to 5?/ui or 20?/ui (see table 3 in setting the loop bandwidth section). phase-frequency detector and charge pump the phase-frequency detector incorporated into the max3670 produces pulses proportional to the phase difference between the reference clock and the vco input. the charge pump converts this pulse train to a current signal that is fed to the op amp. op amp the op amp is used to form an active pll loop filter capable of driving the vco control voltage input. using the polar input, the op amp input polarity can be select- ed to work with vcos having positive or negative gain- transfer functions. the comp pin selects the op amp internal compensation. connect comp to ground if the vco control voltage is v cc referenced. connect comp to v cc if the vco control voltage is ground referenced. design procedure setting up the vco and reference clock the max3670 accepts 77.76mhz, 155.52mhz, or 622.08mhz (including fec rates) reference clock fre- quencies. the rsel input must be set so that the refer- ence clock is prescaled to 77.76mhz (or fec rate), to provide the proper range for the pfd and lol detec- tion circuitry. table 1 shows the divider ratio for the dif- ferent reference frequencies. the max3670 is designed to accept 77.76mhz, 155.52mhz, or 622.08mhz (including fec rates) volt- age-controlled oscillator (vco) frequencies. the vsel input must be set so that the vco input is prescaled to 77.76mhz (or fec rate), to provide the proper range for the pfd and lol detection circuitry. table 2 shows the divider ratio for the different vco frequencies. setting the loop bandwidth to eliminate jitter present on the reference clock, the proper selection of loop bandwidth is critical. if the total output jitter is dominated by the noise at the reference clock input, then lowering the loop bandwidth will reduce system jitter. the loop bandwidth (k) is a func- tion of the vco gain (k vco ), the gain of the phase detector (k pd ), the loop filter resistor (r 1 ), and the total feedback-divider ratio (n = n1 ? n2). the loop band- width of the max3670 can be approximated by for stability, a zero must be added to the loop in the form of resistor r 1 in series with capacitor c 1 (see functional diagram ). the location of the zero can be approximated as due to the second-order nature of the pll jitter trans- fer, peaking will occur and is proportional to f z /k. for certain applications, it may be desirable to limit jitter f rc z = 1 2 11 k krk n pd vco = 1 2 low-jitter 155mhz/622mhz clock generator 8 _______________________________________________________________________________________ input pin rsel reference clock input freq. (mhz) divider ratio n 3 predivider output freq. (mhz) v cc 77.76 1 77.76 open 155.52 2 77.76 gnd 622.08 8 77.76 table 1. reference clock divider input pin vsel vco clock input freq. (mhz) divider ratio n 1 predivider output freq. (mhz) v cc 77.76 1 77.76 open 155.52 2 77.76 gnd 622.08 8 77.76 table 2. vco clock divider
peaking in the pll passband region to less than 0.1db. this can be achieved by setting f z k/100. the three-level gsel pins (see functional diagram ) select the phase-detector gain (k pd ) and the frequency- divider ratio (n 2 ). table 3 summarizes the settings for the gsel pins. a more detailed analysis of the loop filter is located in application note hfdn-13.0 on www.maxim-ic.com. setting the higher-order poles spurious noise is generated by the phase detector switching at the compare frequency, where f compare = f vco /(n 1 ? n 2 ). reduce the spurious noise from the digital phase detector by placing a higher-order pole (hop) at a frequency much less than the compare fre- quency. the hop should, however, be placed high enough in frequency that it does not decrease the over- all loop-phase margin and impact jitter peaking. these two conditions can be met by selecting the hop fre- quency to be (k ? 4) < f hop f compare , where k is the loop bandwidth. the hop can be implemented either by providing a compensation capacitor c 2 , which produces a pole at or by adding a lowpass filter, consisting of r 3 and c 3 , directly on the vco tuning port, which produces a pole at using r 3 and c 3 may be preferable for filtering more noise in the pll, but it may still be necessary to provide filtering via c 2 when using large values of r 1 and n 1 ? n 2 to prevent clipping in the op amp. setting the optional output the max3670 optional clock output can be set to bina- ry subdivisions of the main clock frequency. the psel1 and psel2 pins control the binary divisions. table 4 shows the pin configuration along with the possible divider ratios. applications information pecl interfacing the max3670 outputs (mout+, mout-, pout+, pout-) are designed to interface with pecl signal lev- els. it is important to bias these ports appropriately. a circuit that provides a th?venin equivalent of 50 to v cc - 2v can be used with fixed-impedance transmis- sion lines with proper termination. to ensure best per- formance, the differential outputs must have balanced loads. it is important to note that if optional clock output is not used, it should be left unconnected to save power (see figure 2). f rc hop = 1 2 33 f kc hop = 1 220 2 ()() max3670 low-jitter 155mhz/622mhz clock generator _______________________________________________________________________________________ 9 input pin gsel1 input pin gsel2 input pin gsel3 kpd (?/ui) divider ratio n 2 v cc v cc v cc 20 1 open v cc v cc 20 2 gnd v cc v cc 20 4 v cc open v cc 20 8 open open v cc 20 16 gnd open v cc 20 32 v cc gnd v cc 20 64 open gnd v cc 20 128 gnd gnd v cc 20 256 v cc v cc gnd 20 512 open v cc gnd 20 1024 v cc v cc open 5 1 open v cc open 5 2 gnd v cc open 5 4 v cc open open 5 8 open open open 5 16 gnd open open 5 32 v cc gnd open 5 64 open gnd open 5 128 gnd gnd open 5 256 v cc open gnd 5 512 open open gnd 5 1024 table 3. gain logic pin setup input pin psel1 input pin psel2 vco to pout divider ratio v cc v cc 1 gnd v cc 2 v cc gnd 4 gnd gnd 8 table 4. setting the optional clock output driver
max3670 layout the max3670 performance can be significantly affect- ed by circuit board layout and design. use good high- frequency design techniques, including minimizing ground inductance and using fixed-impedance trans- mission lines on the reference and vco clock signals. power-supply decoupling should be placed as close to v cc pins as possible. take care to isolate the input from the output signals to reduce feedthrough. vco selection the max3670 is designed to accommodate a wide range of vco gains, positive or negative transfer slopes, and v cc -referenced or ground-referenced con- trol voltages. these features allow the user a wide range of options in vco selection; however, the proper vco must be selected to allow the clock generator cir- cuitry to operate at the optimum levels. when selecting a vco, the user needs to take into account the phase noise and modulation bandwidth. phase noise is impor- tant because the phase noise above the pll bandwidth will be dominated by the vco noise performance. the modulation bandwidth of the vco contributes an additional higher-order pole (hop) to the system and should be greater than the hop set with the external fil- ter components. noise performance optimization depending on the application, there are many different ways to optimize the pll performance. the following are general guidelines to improve the noise on the sys- tem output clock. 1) if the reference clock noise dominates the total sys- tem-clock output jitter, then decreasing the loop bandwidth (k) reduces the output jitter. 2) if the vco noise dominates the total system clock output jitter, then increasing the loop bandwidth (k) reduces the output jitter. 3) smaller total divider ratio (n1 ? n2), lower hop, and smaller r 1 reduce the spurious output jitter. 4) smaller r 1 reduces the random noise due to the op amp. lol setup the lol output indicates if the pll has locked onto the reference clock using an xor gate and comparator. the comparator threshold can be adjusted with thadj, and the xor gate output can be filtered with a capaci- tor between cth and ground (figure 3 in the interface schematic section). when the voltage at pin cth exceeds the voltage at pin thadj, then the lol output goes low and indicates that the pll is not locked. note that excessive jitter on the reference clock input at fre- quencies above the loop bandwidth may degrade lol functionality. the user can set the amount of frequency or phase dif- ference between vco and reference clock at which lol indicates an out-of-lock condition. the frequency difference is called the beat frequency. the cth pin can be connected to an external capacitor, which sets the lowpass filter frequency to approximately this lowpass filter frequency should be set about 10 times lower than the beat frequency to make sure the filtered signal at cth does not drop below the thadj threshold voltage. the internal compare frequency of the part is 77.78mhz. for a 1ppm sensitivity (beat fre- quency of 77hz), the filter needs to be at 7.7hz, and cth should be at 0.33?. the voltage at thadj will determine the level at which the lol output flags. thadj is set to a default value of 0.6v which corresponds in a 45 phase difference. this value can be overridden by applying the desired threshold voltage to the pin. the range of thadj is from 0v (0? to 2.4v (180?. f ck l th = 1 260 low-jitter 155mhz/622mhz clock generator 10 ______________________________________________________________________________________ v cc - 1.3v v cc 10.5k 10.5k reflck+ reflck- max3670 figure 1. input interface interface schematics
max3670 low-jitter 155mhz/622mhz clock generator ______________________________________________________________________________________ 11 out+ out- v cc max3670 figure 2. output interface 0.6v 60k 60k refclk vco lol thadj cth max3670 figure 3. loss-of-lock indicator 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10111213141516 opamp+ opamp- comp vcca psel2 psel1 polar vc vcoin+ vcoin- vcco mout+ mout- vcco pout+ pout- vccd gnd rsel refclk+ refclk- vccd vsel c2+ c2- vccd thadj cth gsel1 gsel2 gsel3 *ep lol *the exposed pad must be soldered to supply ground. max3670 qfn/tqfn pin configuration interface schematics (continued) chip information transistor count: 2478 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code document no. 32 qfn-ep g3255-1 21-0091 32 tqfn-ep t3255+3 21-0140
max3670 low-jitter 155mhz/622mhz clock generator maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/01 initial release. 1 5/03 added the pkg code column to the ordering information table; updated the package outline drawing in the package information section. 1, 12 2 9/09 added the lead(pb)-free tqfn package to the ordering information table; replaced the package outline drawing with a table in the package information section. 1, 11

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