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? semiconductor msm7586-01/03 1/42 ? semiconductor msm7586-01/03 p /4 shift qpsk modem/adpcm codec general description the msm7586 is a cmos ic developed for use with digital cordless telephones. the device provides a p /4 shift qpsk modem function and a codec function which performs transcoding between the voice band analog signal and 32 kbps adpcm data. the msm7586 performs dtmf tone and several types of tone generation, transmit/receive data, mute and gain control, side-tone pass and its gain control, and vox function. features ( p /4 shift qpsk modem unit) ? 384 kbps transmission speed ? built-in root nyquist digital filter for the baseband band limiter ? built-in d/a converters for the analog outputs of the quadrature signal component i and q ? the dc offset and gain can be adjusted with respect to the differential i and q analog outputs ? completely digitized p /4 shift qpsk demodulator system (adpcm codec unit) ? adpcm system: built-in itu-t recommendations g.726 (32kbps, 24 kbps, 16 kbps) ? transmit/receive full-duplex capability ? pcm interface code format: selectable between m -law and a-law ? serial adpcm and pcm transmission rate: 64 kbps to 2,048 kbps ? transmit/receive mute function; transmit/receive programmable gain setting ? side tone generator (8-step level adjustment) ? built-in dtmf tone, ringing tone, and various ringing tone generators ? built-in vox function (common unit) ? operate with a single 3 v power supply (v dd : 2.7 v to 3.6 v) ? low power consumption when entire system is operating: 20 ma typ. when powered down: 0.02 ma typ. ? package: 100-pin plastic tqfp (tqfp100-p-1414-0.50-k) (product name: msm7586-01ts-k) (product name: MSM7586-03ts-k) e2u0034-28-82 this version: aug. 1998 previous version: nov. 1996
? semiconductor msm7586-01/03 2/42 block diagram phase detector delay detector afc sl2 sl1 to each block +1 C1 +1 C1 root nyquist lpf pll 3.84m to d/a s/p mapping 1/10 384k C + C + C1 C + 4 tout3 pdn0 pdn1 pdn2 ifin ifck x2 x1 i+ iC q+ qC sgcr ain1C ain1+ gsx1 ain2C gsx2 aout+ aoutC pwi vfro rxd rxc sls rpr rcw afc txd txw txci txco rsync ir pcmro pcmso bclk pcmsi xsync is voxo vdam agm vddm dgm rxsc mck modem mcu interface exckm doutm denm dinm r7, r6 r5, r4 to each block bsto sgm sgct io2 io1 sw1 sw2 vdac sao C + gsx3 ain3 C + gsx4 ain4 codec mcu interface to each block voxi tout2 tout1 reset pdn3 agc dgc vdac vddc io7 io6 sw5 io5 sw4 io4 io3 sw3 exckc denc dinc doutc vref dpll dec sl2 sl1 lpf lpf dc adjust dc adjust d/a d/a att att crm1-b7 to b4 crm1-b3 to b0 receiver transmitter crc5-b7 crc5-b6 r r t crc5-b5 crc5-b4 voice detect compa nder adpcm coder p / s s / p p / s s / p p / s s / p dtmf /tone generator bpf rc filter a/d convertor lpf rc filter d/a convertor noise generator power detect + expan der att att crc3-b7 to b5 crc2-b2 to b0 crc3-b3 to b0 sign bit att crc4-b6 crc2-b6 to b4 pcmri adpcm de- coder crc4-b5 t r t crm0-b6 decision to each block +
? semiconductor msm7586-01/03 3/42 pin configuration (top view) 100 vddm rxsc sls ifin nc x1 nc nc x2 ifck mck pdn0 pdn1 pdn2 nc rcw afc rpr rxc rxd nc denm exckm doutm dinm sao ain3 gsx3 vdac vddc nc ain4 gsx4 nc io3 io4 nc tout1 tout2 tout3 pdn3 reset nc dinc doutc exckc denc nc voxi voxo vdam qC q+ iC i+ nc sgm agm agc sgcr sgct ain1+ ain1C gsx1 io5 io6 io7 ain2 gsx2 io1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 io2 vfro pwi aoutC aout+ 21 22 23 24 25 nc txw txd txco txci nc bsto dgm dgc r7 r6 r5 r4 nc bclk xsync rsync nc pcmso pcmsi 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 is nc ir pcmro pcmri 55 54 53 52 51 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 nc : no connect pin 100-pin plastic tqfp
? semiconductor msm7586-01/03 4/42 pin and functional descriptions ( modem unit ) txd transmit data input for 384 kbps. txci transmit clock input. when the control register crm0 - b6 is "0", a 384 khz clock pulse synchronous with txd should be input to this pin. this clock pulse should be continuous because this device use apll to generate an internal clock pulse. when crm0 - b6 is "1", a 3.84 mhz clock pulse should be input to this pin. when the 3.84 mhz clock pulse is applied to txcl, txco outputs a 384 khz clock pulse, which is generated by dividing the txcl input by 10. the transmit data, synchronous to the 384 khz clock pulse, should be input to the txd. in this case the devices do not use apll, and the 3.84 mhz clock pulse need not be continuous. (refer to fig. 1.) txco transmit clock output. when crm0 - b6 is "0", txco outputs the 384 khz clock pulse (apll output) for monitoring purposes. when crm0 - b6 is "1", this pin outputs a 384 khz clock pulse generated by dividing the txci input by 10. (refer to fig. 1.) txw transmit data window signal input. the transmit timing signal for the burst data is input to this pin. if txw is "1", the modulation data is output. (refer to fig. 1)
? semiconductor msm7586-01/03 5/42 figure 1 transmit timing diagram (1) crm0 C b6 = "0" ramp rise-up 2 symbols ramp fall-down 2 symbols (2) crm0 C b6 = "1" d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d n -1 d n d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d n -1 d n ramp rise-up 2 symbols ramp fall-down 2 symbols delay of 6.25 symbols delay of 6.25 symbols delay of 6.25 symbols delay of 6.25 symbols txd txci (384 khz) txw txco (384 khz) i, q txd txci (3.84 mhz) txw txco (3.84 khz) i, q
? semiconductor msm7586-01/03 6/42 bsto bsto is the modulator side burst window output. the burst position of the i and q baseband modulator output is output. i+, iC quadrature modulation signal i component differential analog output. their output levels are 500 mv pp (when txd = "0": 360 mv pp typ.) with 1.6 vdc as the center value. the output pin load conditions are: r 3 10 k w , c 20 pf. the gain of these pins can be adjusted using the control register crm1 - b7 to b4, and the offset voltage at the iC pin can be adjusted using crm3 - b7 to b3. q+, qC quadrature modulation signal q component differential analog outputs. their output levels are 500 mv pp (when txd = "0": 360 mv pp typ.) with 1.6 vdc as the center value. the output pin load conditions are: r 3 10 k w , c 20 pf. the gain of these pins can be adjusted using the control register crm1 - b3 to b0, and the offset voltage at the qC pin can be adjusted by using crm4 - b7 to b3. sgm internal reference voltage output. the output voltage value is approximately 2.0 v. insert a bypass capacitor between this pin and the agm pin. during power down, this output is at 0 v. the external sg voltage if necessary should be used via a buffer.
? semiconductor msm7586-01/03 7/42 pdn0, pdn1, pdn2 various power down control. pdn0 controls the standby mode/communication mode; pdn1 controls the modulator unit; and pdn2 controls the demodulator unit. refer to table 1 for details. the control register reset input width should be 200ns or more. modulator unit is powered off. (vref and pll are powered on.) i and q outputs are in a high impedance state. only the demodulator clock regenerator unit is powered on. pdn0 pdn2 pdn1 mode name operation state 0 0/1 1 mode a 1 0 0 mode d 1 1 1 mode g standby mode entire system is powered down. the control register is reset. 0 0 0 mode b entire system is powered down. the control register is not reset. 1 1 0 mode f modulator unit is powered off. (vref and pll are powered off.) i and q outputs are in a high impedance state. demodulator unit is powered on. 1 0 1 mode e modulator unit is powered on. only the demodulator clock regenerator unit is powered on. modulator unit is powered on. demodulator unit is powered on. commu- nication mode 0 1 0 mode c modulator unit is powered off. (vref and pll also powered off.) demodulator unit is powered on. table 1: description of modem power down control
? semiconductor msm7586-01/03 8/42 vddm, vdam +3 v power supply for the modem unit. supplied to the digital circuits through the vddm pin and to the analog circuits through the vdam pin. vddm and vdam, and vddc and vdac should be connected as close as possible on the pc board. dgm, agm ground pins for the modem unit. dgm is the ground pin of the digital system, and agm is the ground pin of the analog system. since dgm and agm are isolated inside the ic, connect them as close as possible on the circuit board. mck master clock input. the clock frequency is 19.2 mhz. ifin modulated signal input for the demodulator block. select the if frequency can be selected from 1.2 mhz, 10.7 mhz, 10.75 mhz, and 10.8 mhz, based on crm0 - b4 and b3. ifck clock frequency 19.0222 mhz input for demodulator block if frequencies of 10.7 mhz. if the if frequency is 1.2 mhz or 10.8 mhz, set this pin to "0" or "1". (refer to fig. 2.) x1, x2 crystal oscillator connection pins. when supplying a 19.0222 mhz clock to ifck, use these pins. (refer to fig. 2.) figure 2 how to use ifck, x1, and x2 when ifin = 10.7 mhz msm7586 x1 x2 ifck 19.0222 mhz when ifin = 1.2 mhz or 10.8 mhz msm7586 x1 x2 ifck
? semiconductor msm7586-01/03 9/42 rxd, rxc, rxsc receive data and receive clock outputs. when the modem unit is powered on, rxd, rxc and rxsc are selected based on sls as shown in figure 3. these outputs are used by the clock regenerator circuit. figure 3 timing diagram of rxd, rxc, and rxsc sls receive side operation slot selection signal. this device has two clock regenerator circuits and two afc data memory registers. if sls is "0", slot 1 is selected, if sls is "1", slot 2 is selected. rpr high-speed phase clock control signal input for the clock recovery circuit. if this pin is at "0", the circuit is always in the low-speed phase clock mode. if this pin is at "1", the clock recovery circuit enters the high-speed phase clock mode. when the phase difference is less than a defined value, the circuit shifts to the low-speed phase clock mode automatically. rxd rxc rxsc sls 1 symbol the regenerated data and clock are selected asynchronously by the sls signal.
? semiconductor msm7586-01/03 10/42 afc afc operation range specification signal input. as shown in fig. 4, the afc information is reset when both afc and rpr are set to "1". afc operation starts after a fixed number of clock cycles and the afc information is reset. if rpr is set to "1", an average number of times that afc turns on is low. if rpr is "0", afc is high. if afc is "0", frequency error is not calculated, but the frequency is corrected using an error that is held. rcw clock recovery circuit operation on/off control signal input. if rcw this pin is "0", dpll does not make any phase corrections. afc afc information is reset. rpr average number of times afc is low. afc information is maintained. afc rpr afc information is maintained. the clock recovery circuit starts with the previous afc information. "0" (case1) (case2) average number of times afc is high. average number of times afc is high. figure 4 afc control timing diagram denm , exckm, dinm, doutm serial control ports for the microprocessor interface. the device contains a 6-byte control register (crm0 - 5). an external cpu uses these pins to read data from and write data to the control register. denm is the "enable" signal input pin. exckm is a data shift clock pulse input pin. dinm is an address and data input pin. doutm is a data output pin. figure 5 shows input/output timing diagram.
? semiconductor msm7586-01/03 11/42 high impedance high impedance (a) write data timing diagram (b) read data timing diagram denm w exckm dinm a2 doutm a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r a2a1a0 b7 b6 b5 b4 b3 b2 b1 b0 denm exckm dinm doutm figure 5 modem unit mcu interface i/o timing the register map is shown below. table 2: modem unit control register (crm0 to 5) map r/w: read/write enable r: read-only register r7, r6, r5, r4 these are the control register data output pins. these output the data crm2 - b7, b6, b5, and b4, respectively. register name address a2 a1 a0 data description r/w b7 b6 b5 b4 b3 b2 b1 b0 crm0 000 r/w txc sel mod off ifsel1 ifsel0 test1 test0 crm1 001 r/w ich gain3 ich gain2 ich gain1 ich gain0 qch gain3 qch gain2 qch gain1 qch gain0 crm2 010 r/w r7 r6 r5 r4 crm3 011 r/w ich offset4 ich offset3 ich offset2 ich offset1 ich offset0 crm4 100 r/w qch offset3 qch offset2 qch offset1 qch offset0 crm5 101 r/w ict5 ict4 ict3 ict2 local inv1 local inv0 ict1 ict0 qch offset4
? semiconductor msm7586-01/03 12/42 (codec unit) ain1+, ain1-, ain2, gsx1, gsx2 the transmit analog input and the output for transmit gain adjustment. the pin ain1C(ain2) connects to the inverting input of the internal transmit amplifier, and the pin ain1+ connects to the non-inverting input of the internal transmit amplifier. the pin gsx1 (gsx2) connects to output of the internal transmit amplifier. see fig. 6 for gain adjustment. vfro, aout+, aout-, pwi used for the receive analog output and the output for receive gain adjustment. vfro is an output of the receive filter. aout+ and aoutC are differential analog signal outputs which can directly drive z l = 350 w +120 nf or the 1.2 k w load. see fig. 6 for gain adjustment. however, these outputs are in high impedance state during power down. sao, ain3, ain4, gsx3, gsx4 input pins for the internal operational amp. refer to fig. 6 for connection information. however, these output pins are in the high impedance state during power down.
? semiconductor msm7586-01/03 13/42 transmit gain : (v gsx2 /vi) = (r2/r1) (r4/r3) ain1C gsx1 r2 c1 to encoder r1 analog output signal vo receive gain : (v o /v vfro ) = 2 (r6/r5) z l = 120 nf + 350 w ain2 gsx2 r4 c2 r3 aout+ r6 aoutC ain1+ C1 C + C + C + c1 r1 r2 reference voltage generator sgct from decoder + C vi differential analog input signal r5 +1 vfro +1 sao C + r7 r8 ain3 gsx3 sounder output gain : (v gsx3 ) = v sao (r8/r7) sounder output signal figure 6 codec unit analog interface
? semiconductor msm7586-01/03 14/42 io1 to io7 i/o pins of the internal analog switch. refer to the control register description table (crc5) and the block diagram for connection information and control methods. tout1 to tout3 sign bit output pins of the tone generator. output control of each pin is performed by the control register. refer to the control register description table (crc5) and the block diagram for connection information and control methods. sgct, sgcr output pins of the codec unit analog signal ground voltage. sgct outputs the analog signal ground voltage of the transmit system, and sgcr outputs the same for the receive system. the output voltage value is approximately 1.4 v. connect 10 m f and 0.1 m f bypass capacitors (ceramic type) between these pins and the agc pin. during power down, the output changes to 0 v. the external sg voltage if necessary should be used via a buffer. vddc, vdac codec unit +3 v power supply. vddc is supplied to the digital system power supply, and vdac is supplied to the analog system power supply. vddc and vdac, and vddm and vdam must be connected as possible on the pc board. dgc, agc codec unit ground. dgc is the digital system ground pin, and agc is the analog system ground pin. since dgc and agc are unconnected in the device, place them as close together as possible on the circuit board. pdn3 codec unit power-down control input. the codec unit changes to the power - down state when set to a digital "0." since the power- down control is handled by an or with control register crc0 - b5, set crc0 - b5 to digital "0" when using this pin. reset reset control input pin of the codec unit control register. when set to digital "0," each bit of the control register is reset. during normal operation, set this pin to digital "1." a more than 200ns reset signal should be input.
? semiconductor msm7586-01/03 15/42 pcmso transmit pcm data output. this pcm output signal is output from msb synchronous with the rising edge of bclk and xsync. pcmsi transmit pcm data input. this signal is converted to the adpcm data. the pcm signal is shifted on the falling edge of bclk. normally, this pin is connected to pcmso. pcmro receive pcm data output. the pcm signal is the output signal after adpcm decoder processing. this signal is serially output from the msb synchronous with the rising edge of bclk and rsync. pcmri receive pcm data input. the pcm input signal is shifted on the falling edge of bclk and input from msb. normally, this pin is connected to pcmro. is transmit adpcm signal output. this signal is the output signal after adpcm encoding, and is serially output from msb synchronous with the rising edge of bclk and xsync. this pin is an open drain output which remains in a high impedence state during power-down, and requires a pull-up resistor. ir receive adpcm signal input. input data is shifted serially from msb on the falling edge of bclk synchronous with rsync. bclk shift clock input for the pcm data (pcmso, pcmsi, pcmro, pcmri) and the adpcm data(is, ir) . the frequency ranges from 64 khz to 2048 khz. xsync transmit pcm and adpcm data 8 khz synchronous signal input. this signal should be synchronous with bclk. xsync is used for indicating msb of the transmit serial pcm and adpcm data stream. rsync receive pcm and adpcm data 8 khz synchronous signal input. this signal should be synchronous with bclk signal. rsync is used for indicating msb of the receive serial pcm and adpcm data stream.
? semiconductor msm7586-01/03 16/42 voxo transmit vox function signal output. vox function is used to recognize the presence or absence of the transmit voice signal by detecting the signal energy. "h" and "l" levels on this pin correspond to the presence and the absence, respectively. this result also appears at the register data crc7 - b7. the signal energy detect threshold is set by the control register data crc6 - b6, b5. voxi signal input for receive vox function. the "h" level on voxi indicates the presence of voice signal, the decoder block processes normal receive signal, and the voice signal appears at analog output pins . the "l" level indicates the absence of voice signal, the background noise generated in this device is transferred to the analog output pins. the background noise amplitude is set by the control register crc6. because this signal is ored with the register data crc6 - b3, the control register data crc6 - b3 should be set to digital "0". input voice signal gsx2 pin regenerated voice vfro pin voxo pin voxi pin voice silience voice voice silience voice voice detection time tvxon silence detection time (hangover time) tvxoff (a) transmission side vox function timing diagram (b) receive side vox function timing diagram regenerated voice signal generation time internal background noise generation time note: the voxo and voxi pin function are enabled when crc6 - b7 is set to "1". figure 7 vox function
? semiconductor msm7586-01/03 17/42 denc, exckc, dinc, doutc serial control ports for mcu interface. reading and writing data are performed by an external mcu through these pins. the 8-byte control registers (crc0 - 7) are provided for the codec unit in this device. denc is the "enable" control signal input, exckc is the data shift clock input, dinc is the address and data input, and doutc is the data output. figure 8 shows input/output timing diagram. table 3: codec unit control register (crc0 to 7) map r/w: read/write enable r: read-only register high impedance high impedance (a) write data timing diagram (b) read data timing diagram denc w exckc dinc a2 doutc a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 r a2a1a0 b7 b6 b5 b4 b3 b2 b1 b0 denc exckc dinc doutc figure 8 codec unit mcu interface i/o timing the register map is shown below. register name address a2 a1 a0 data description r/w b7 b6 b5 b4 b3 b2 b1 b0 crc0 000 r/w a/ m sel pdn all pdn sao/aout crc1 001 r/w mode1 mode0 tx reset rx reset tx mute rx mute rx pad crc2 010 r/w tx on/off tx gain2 tx gain1 tx gain0 rx on/off rx gain2 rx gain1 rx gain0 crc3 011 r/w side tone gain2 side tone gain1 side tone gain0 tone on/off tone gain3 tone gain2 tone gain1 tone gain0 crc4 100 r/w dtmf/ others sel tone send sao/ vfro tone4 tone3 tone2 tone1 tone0 crc5 101 r/w sw1 cont sw2 cont sw3 cont sw4/5 cont tout3 cont tout2 cont tout1 cont crc6 110 r/w vox on/off on lvl1 on lvl0 off time vox in rx noise level sel rx noise lvl1 rx noise lvl0 crc7 111 r vox out tx noise lvl1 tx noise lvl0
? semiconductor msm7586-01/03 18/42 absolute maximum ratings parameter power supply voltage analog input voltage digital input voltage storage temperature symbol v dd v ain v din t stg condition rating C0.3 to +5 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C55 to +150 unit v v v c recommended operating conditions modem unit (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) codec unit parameter power supply voltage operating temperature input high voltage input low voltage digital input rise time digital input fall time digital output load bypass capacitor for sg master clock frequency master clock duty ratio modulator side input frequency demodulator side input frequency clock duty ratio if input duty ratio transmit sync pulse setting time bit clock frequency synchronous signal frequency clock duty ratio transmit sync pulse setting time receive sync pulse setting time synchronous signal width pcm, adpcm set-up time pcm, adpcm hold time symbol v dd ta v ih v il t ir t if r dl c dl c sg f mck d mck f txc1 f txc2 f ifck1 f ifck2 d ckm d cif t xsm , t sxm t sdm , t dhm f bck f sync d ckc t xsc, t sxc t rsc, t src t wsc t dsc t dhc conditon voltage must be fixed input pins fully digital input pins fully digital input pins fully digital input pins fully digital is (pull-up resistance) input pins fully digital between sgm and agm, and between sgct/r and agc mck mck txci (when crm0 - b6 = "0") txci (when crm0 - b6 = "1") ifck (when ifin = 10.7 mhz) ifck (when ifin = 10.75 mhz) ifck, txci, exckm ifin txci ? txw txci ? txd bclk xsync, rsync bclk, exckc bclk ? xsync bclk ? rsync xsync, rsync fig.9 fig.12 min. typ. max. unit 2.7 3.6 v C25 +25 +70 c 0.45 v dd v dd v 0 0.16 v dd v 50ns 50ns 500 w 100 pf 10 + 0.1 m f C0.01% +0.01% mhz 40 60 % khz mhz mhz mhz 40 60 % 45 55 % 200 ns 19.2 50 384 3.84 19.0222 19.1111 50 50 200 ns 64 2048 khz khz 8.0 40 60 % 50 100 ns 100 ns 1 bclk 100 m s 100 ns 100 ns
? semiconductor msm7586-01/03 19/42 electrical characteristics dc characteristics parameter output high voltage output low voltage output leakage current input capacitance symbol v oh v ol i o condition i oh = 0.4 ma i ol = C1.2 ma (is pin is 500 w pull-up) is pin min. 0.5 v dd 0 typ. 0.2 max. v dd 0.4 10 unit v v m a c in 5pf (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) 0.8 v dd i dd1 mode a, mode b (when v dd = 3.0 v) 0.02 0.1 ma i dd2 mode c ( when v dd = 3.0 v ) 5.5 11.0 ma i dd3 mode d ( when v dd = 3.0 v ) 5.5 11.0 ma i dd4 mode e ( when v dd = 3.0 v ) 11.5 23.0 ma i dd5 mode f ( when v dd = 3.0 v ) 9.5 19.0 ma i dd6 mode g ( when v dd = 3.0 v ) 14.0 28.0 ma power supply current (modem unit) * when codec unit is in a power down state input leakage current i ih i il v i = v dd v i = 0 v 2.0 0.5 m a m a power supply current (codec unit) * when modem unit is in a power down state i dd7 i dd9 when operating * (when no signal, and v dd = 3.0 v) when powered down (when v dd = 3.0 v) 12.0 0.02 19.0 0.1 ma ma i dd8 i oh = 1 m av dd v 8.0 16.0 ma *i dd7 applies when crc0 - b0 = "0" and crc4 - b5 = "0"; i dd8 applies when operating at other times.
? semiconductor msm7586-01/03 20/42 parameter output resistance load symbol r liq condition i+, iC, q+, qC min. 10 typ. max. unit k w (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) output capacitance load c liq i+, iC, q+, qC 20 pf output dc voltage level v dcm i+, iC, q+, qC (txw = 0) 1.55 1.6 1.65 v output ac voltage level v acm i+, iC, q+, qC 340 360 380 mv pp (for txd = 0 continuous input) output dc voltage adjustment level range d cvl 45 mv output ac voltage adjustment level range a cvl 4% out-of-band spectrum p600 600 khz detuning (continuous) 60 db p900 900 khz detuning (continuous) 65 db modulation accuracy e vm 1.0 3.0 % rms demodulator side if input level i fv ifin input level 0.4 v dd v pp ifin input impedance r if 20k w sgm output voltage v sgm 2.0 v sgm output impedance r sgm 1.5 k w dc impedance master clock external input level i x11 1.5 v dd v pp x1 input level (when crm5 C b1 = "0") i x12 0.7 v dd v pp x1 input level (when crm5 C b1 = "1") x1 input impedande rx1 2.0 m w x1 input capacitance cx1 10 pf offset voltage difference v off C20 +20 mv difference among i+, iC, q+ and qC modulator d/a conversion sampling frequency f sda 1.92 mhz modulator d/a conversion offset frequency f cda 380 khz analog interface characteristics (modem unit)
? semiconductor msm7586-01/03 21/42 digital interface characteristics (modem unit) parameter transmit digital i/o setting time symbol t xdm1,2 condition min. 0 typ. max. 200 unit ns (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) t xdm3,4 0 400 ns reference c load = 50 pf fig. 9 receive digital i/o setting time t rdm1,2 c load = 50 pf fig. 10 0 200 ns t m1 50ns t m2 50ns t m3 50ns t m4 50ns serial port digital i/o setting time t m5 c load = 50 pf fig. 11 100 ns t m6 50ns t m7 50ns t m8 0 100 ns t m9 50ns t m10 50ns t m11 0 50 ns exck clock frequency feckm exckm 10 mhz t m12 200 ns
? semiconductor msm7586-01/03 22/42 analog interface characteristics (codec unit) parameter input resistance output resistance load output capacitance load output voltage level ( * 1) offset voltage symbol r inc r lc1 c lc1 v oc1 v ofc1 condition ain+, ainC, ain2, pwi, ain3, ain4 min. 10 20 C100 typ. max. 100 1.3 +100 unit m w k w pf v pp mv gsx1, gsx2, vfro, sao gsx1, gsx2, vfro, sao gsx1, gsx2, vfro, sao(rl = 20 k w ) vfro, sao (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) r lc2 aout+, aoutC, gsx4 c lc2 aout+, aoutC, gsx4 v ofc2 C20 +20 mv gsx1, gsx2, aout+, aoutC, gsx3, gsx4 1.2 k w r lc3 gsx3 150 w 100 pf c lc3 gsx3 100 pf v oc2 1.3 v pp aout+, aoutC, gsx4 (rl = 1.2 k w ) v oc3 1.3 v pp gsx3(rl = 150 w ) analog switch off resistance r swof 50m w sw1 to sw5 analog switch on resistance r swon 100 400 w sw1 to sw5 sgcr output impedance r sgcr 4 8k w sgcr sgct output impedance r sgct 4080k w sgct sgct, sgcr output voltage v sgc 1.4 v sgct, sgcr sgct rise time t sgct 600 ms for the recommended circuit (rise time to 90% of max. level) sgcr rise time t sgcr 15ms for the recommended circuit (rise time to 90% of max. level) note : *1 C7.7 dbm (600 w ) = 0 dbm0, +3.14 dbm0 = 1.30 v pp (a-law) C7.7 dbm (600 w ) = 0 dbm0, +3.17 dbm0 = 1.30 v pp ( m -law)
? semiconductor msm7586-01/03 23/42 digital interface characteristics (codec unit) 1 lsttl + 100 pf pull-up : 500 w items in parenthesis ( ) mean c load = 10 pf, and the pull-up 2 k w parameter digital output delay time pcm, adpcm interface symbol t sdxc, t sdrc condition min. 0 typ. max. 200 (100) unit ns (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) t xdc1, t rdc1 0 ns reference t xdc2, t rdc2 fig. 12 0 ns t c1 50 ns t c2 50 ns t c3 50 ns t c4 50 ns serial port digital i/o timing characteristics t c5 c load = 50 pf fig. 13 100 ns t c6 50 ns t c7 50 ns t c8 0 100 ns t c9 50 ns t c10 50 ns t c11 0 50 ns exck clock frequency feckc exckc 10 mhz t xdc3, t rdc3 0 ns 200 (100) 200 (100) 200 (100) t c12 200 ns
? semiconductor msm7586-01/03 24/42 ac characteristics (codec unit) note: *2 p-message filter used parameter transmit frequency response symbol l oss t1 min. 25 typ. max. unit db l oss t2 C0.15 +0.20 db l oss t3 reference db l oss t4 C0.15 +0.80 db l oss t5 0 0.80 db l oss t6 13 db receive frequency response C0.15 +0.20 db reference db C0.15 +0.80 db 0 0.80 db 13 db transmit signal to distortion ratio (*2) sd t1 35 sd t2 35 sd t3 35 sd t4 28 sd t5 23 receive signal to distortion ratio (*2) sd r1 sd r2 sd r3 sd r4 sd r5 transmit gain tracking gt t1 C0.2 +0.2 gt t2 reference gt t3 C0.2 +0.2 gt t4 C0.5 +0.5 gt t5 C1.2 +1.2 receive gain tracking gt r1 C0.2 +0.2 gt r2 reference gt r3 0 to 60 frequency (hz) 300 to 3 k 1020 3300 3400 3968.75 0 to 3000 1020 3300 3400 3968.75 1020 1020 1020 1020 C0.2 +0.2 gt r4 C0.5 +0.5 gt r5 C1.2 +1.2 level dbm0 0 0 3 0 C30 C40 C45 3 0 C30 C40 C45 C40 3 C10 C50 C55 C40 3 C10 C50 C55 condition l oss r1 l oss r2 l oss r3 l oss r4 l oss r5 35 35 35 28 23 db db db db db db db db db db db db db db db db db db db db (v dd = 2.7 v to 3.6 v, ta = C25c to +70c)
? semiconductor msm7586-01/03 25/42 ac characteristics (codec unit) notes: *2 p-message filter used *3 pcmri input: "11010101" (a-law), "11111111" ( m -law) *4 0.320 vrms = 0 dbm0 = C7.7 dbm (600 w) adpcm unit characteristics are fully compliant with itu-t recommendation g.726. ac characteristics (dtmf and other tones) note: *5 not including programmable gain set values ac characteristics (gain settings) d g for all gain set values C1 0 +1 db transmit/receive gain setting accuracy parameter symbol min. typ. max. unit (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) condition C2.5 db t vxon silence ? voice 10ms transmit vox detection time (voice and silence test time) t vxof parameter symbol min. typ. max. unit (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) condition 140/300 160/320 180/340 ms voice ? silence d vx for detection level set values by crm6 - b6, b5 voxo pin: see fig. 7 0 +2.5 transmit vox detection level accuracy (voice detection level) voice/silence differential: 10 db *6 ac characteristics (vox function) p srrt noise frequency: 0 khz to 50 khz 30db power supply noise rejection ratio noise level: 50 mvpp p srrr parameter symbol level dbm0 min. typ. max. unit (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) frequency (hz) other condition 30db n idlt C68 (C75.7) dbm0p (dbmp) n idlr 1020 a vt 0.285 0.320 0.359 0 a vr 0.285 0.320 0.359 C72 (C79.7) idle channel noise (*2) ain = sg vrms vrms gsx2 absolute level (*4) vfro (*3) C18 C16 C10 C8 dbm0 d ft1 dtmf tones C7+7hz frequency deviation d ft2 parameter symbol min. typ. max. unit (v dd = 2.7 v to 3.6 v, ta = C25c to +70c) condition C7+7hz dbm0 dbm0 dbm0 other various tones v tl transmit side tone (gain setting 0db) v th v rl receive side tone (tone generator gain setting C6db) v rh 1db r dtmf v th /v tl , v rh /v rl tone reference output level (*5) dtmf tone level relative value dtmf (low group) dtmf (high group), other dtmf (low group) dtmf (high group), other C16 C14 C8 C6 2 C14 C12 C6 C4 3 note: *6 when single tone is input at 1000hz
? semiconductor msm7586-01/03 26/42 timing diagram (modem unit) transmit data input timing transmit clock (txco) timing (when crm0 - b6 = 1) transmit burst position (bsto) output timing (when crm0 - b6 = 0) figure 9 modem unit transmit side (modulator side) digital i/o timing receive side data i/o timing figure 10 modem unit receive side (demodulator side) digital i/o timing serial port timing for microcontroller interface figure 11 modem unit serial control port interface t xsm t dsm t dhm 123 n-2 n-1 n n+1 txci [txco*] (384 khz) txw txd 1 t sxm 2 3 n-2 n n-1 t xsm t sxm txco in brackets [ ] is when crm0 - b6 = 1 t xdm1 1234 5678910 txci (3.84 mhz) txco (384 khz) t xdm2 t xdm1 txci (384 khz) txw t xdm3 12 9 10 n n+1 n+16 n+17 n+18 bsto t xdm4 rxc rxd t rdm2 sls t rdm1 t m1 t m3 t m4 t m2 123456 t m6 t m7 t m5 11 12 t m10 t m11 w/r a2 a1 a0 b7 b7 t m8 b1 b0 b1 b0 t m9 denm exckm dinm doutm t m12
? semiconductor msm7586-01/03 27/42 (codec unit) transmit side pcm, adpcm timing receive side pcm, adpcm timing figure 12 codec unit pcm, adpcm interface serial port timing for microcontroller interface figure 13 codec unit serial control port interface 123456 78910 123456 78910 0 t xdc1 t xdc2 t wsc t sxc t xsc t sdxc msb lsb t xsc t sxc t xdc1 t xdc2 msb lsb t xdc3 t xdc3 t sdxc bclk xsync pcmso bclk xsync is 0 123456 78910 123456 78910 0 t rdc1 t rdc2 t wsc t src t rsc t sdxc msb lsb t rsc t src t rdc3 bclk rsync pcmro bclk rsync msb lsb ir t dhc t dsc t xdc3 t c1 t c3 t c4 t c2 123456 t c6 t c7 t c5 11 12 t c10 t c11 w/ra2 a1a0b7 b7 t c8 b1 b0 b1 b0 t c9 denc exckc dinc doutc t c12
? semiconductor msm7586-01/03 28/42 modem unit mode state transition time figure 14 modem unit power down state transition time mode b mode c 1 ms mode d 5 ms mode f 5 m s pdn1 = 0 pdn2 = 0 pdn1 = 0 pdn2 = 1 mode e 40 m s pdn1 = 1 pdn2 = 0 mode g pdn1 = 1 pdn2 = 1 standby mode (pdn0 = 0) communication mode (pdn0 = 1) note: 40 m s 5 m s mode a* pdn1 = 1 pdn1 = 0 pdn2 = 0 pdn1 = 0 pdn2 = 1 values not indicated are less than 1 m s. * note that this state clears the re g ister.
? semiconductor msm7586-01/03 29/42 modem unit demodulator control timing diagram (example) figure 15 modem unit demodulator timing diagram example gr1 1st slot g "0" demodulator unit modulator input data pdn2 sls afc rxd rxc rxd g g g g g g g g r r r r ss ss pr pr pr uw cr cr g g g g g g gg afc* rpr rcw* rxd afc rpr rcw 240 bits 625 m s 64 bits 56 bits (1) control ch/ synchronous burst (ss + pr = 64 bits) afc* rpr rcw* g g g g g g g g r r r r ss ss pr pr pr uw cr cr g g g g g g gg 8 bits less than 30 bits "0" g: guard bit r: ramp bit ss: start symbol bit pr: preamble bit uw: unique word bit cr: crc bit r1 (2) when synchronization is not yet established (3) communication ch (ss + pr = 8 bits) *afc and rcw may be controlled at the same timing.
? semiconductor msm7586-01/03 30/42 functional description control register description table (modem unit) (1) crm0 (basic operation mode setting) note: the initial value is the value set when a reset is applied by the reset pin. b7, b2: ..... not used b6: ............ transmission timing clock selection 0: txci input: 384 khz txco output: apll 384 khz output transmission data txd is input synchronized to the rise of txci. apll is on. 1: txci input: 3.84 mhz txco output: 384 khz (txci divided by 10) transmission data txd is input synchronized to the rise of txco. apll is off. b5: modulation off/on control 0: modulation on 1: modulation off b4, b3: ..... receive side input if frequency selection (0,0), (0,1): 1.2 mhz (1,0): 10.8 mhz (1,1): 10.7 mhz/10.75 mhz b1, b0: ..... device test control bit since it is used for lsi testing, it is normally set to "0." b0 b1 b2 b3 b4 b5 b6 b7 test0 0 test1 0 0 ifsel0 0 ifsel1 0 mod off 0 txc sel 0 0 crm0 initial value (note)
? semiconductor msm7586-01/03 31/42 (2) crm1 (i and q gain adjustment) b7 to b4: .... i+ and i- output gain setting: 3 mv steps (refer to table 4) b3 to b0: .... q+ and q- output gain setting: 3 mv steps (refer to table 4) table 4: i and q gain setting table (3) crm2 (output to r7 to r4 pins) b7 to b4: .... output to r7 to r4 pin b0 b1 b2 b3 b4 b5 b6 b7 qch gain0 0 0 0 0 0 0 0 ich gain3 0 crm1 initial value ich gain2 ich gain1 ich gain0 qch gain3 qch gain2 qch gain1 crm1 - b7 b6 b5 b4 description crm1 - b3 b2 b1 b0 0 111 amplitude value: 1.042 reference value 0 110 1.036 0 101 1.030 0 100 1.024 0 011 1.018 0 010 1.012 0 001 1.006 0 000 1.000 (reference value) 1 111 0.994 1 110 0.988 1 101 0.982 1 100 0.976 1 011 0.970 1 010 0.964 1 001 0.958 1 000 0.952 b7 r7 0 b6 r6 0 b5 r5 0 b4 r4 0 b3 0 b2 0 b1 0 b0 0 crm2 initial value
? semiconductor msm7586-01/03 32/42 (4) crm3 (i- output offset voltage adjustment) b7 to b3: .... i- output pin offset voltage adjustment (refer to table 5) b2 to b0: .... not used (5) crm4 (q- output offset voltage adjustment) b7 to b3: .... q- output pin offset voltage adjustment (refer to table 5) b2 to b0: .... not used table 5: ich and qch offset adjustment values crm3 - b7 b6 b5 b4 b3 offset voltage crm3 - b7 b6 b5 b4 b3 offset voltage crm4 - b7 b6 b5 b4 b3 crm4 - b7 b6 b5 b4 b3 0 1111 +45 mv 1 C3 mv 0 1110 +42 mv 1 C6 mv 0 1101 +39 mv 1 C9 mv 0 1100 +36 mv 1 C 12 mv 0 1011 +33 mv 1 C15 mv 0 1010 +30 mv 1 C18 mv 0 1001 +27 mv 1 C21 mv 0 1000 +24 mv 1 C24 mv 0 0111 +21 mv 1 C27 mv 0 0110 +18 mv 1 C30 mv 0 0101 +15 mv 1 C33 mv 0 0100 +12 mv 1 C36 mv 0 0011 +9 mv 1 C39 mv 0 0010 +6 mv 1 C42 mv 0 0001 +3 mv 1 C45 mv 0 0000 0 mv 1 C48 mv 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 b0 b1 b2 b3 b4 b5 b6 b7 0 0 0 0 0 0 0 ich offset4 0 crm3 initial value ich offset3 ich offset2 ich offset1 ich offset0 b0 b1 b2 b3 b4 b5 b6 b7 0 0 0 0 0 0 0 qch offset4 0 crm4 initial value qch offset3 qch offset2 qch offset1 qch offset0
? semiconductor msm7586-01/03 33/42 (6) crm5 (ic test) b7 to b4: .... lsi test control bit note: since b7 to b4 of crm5 are used for lsi testing, they should normally be set to "0". b3, b2: .......local inverted mode setting bit (use if the phase of the demodulator side if input is inverted due to the system configuration.) (0,0): normal mode(1,1): local inverted mode b1: .............. waveform shaping mode switching bit of the oscillator circuit unit clock (when using a master clock external input, increase the x1 pin input sensitivity.) 0: normal mode 1: clock waveform shaping mode b0: .............. oscillator circuit unit power on control bit 0: normal mode 1: oscillator circuit unit is always powered on b0 b1 b2 b3 b4 b5 b6 b7 0 0 0 0 0 0 0 ict5 0 crm5 initial value ict4 ict3 ict2 local inv1 local inv0 ict1 ict0
? semiconductor msm7586-01/03 34/42 (codec unit) (1) crc0 (basic operation mode settings) b7: ........................... pcm interface companding selection 0: m -law 1: a-law b6, b4, b3, b2, b1: . not used (these pins are used to test the device. they should be set to "0" during normal operation.) b5: ........................... power down (entire unit) 0: power on 1: power down ored with the inverse of the external power down signal. when using this data, set pdn3 to "1." b0: ........................... the sounder output amp (sao, gsx3) and receiver system output amp (vfro, aout+, aout-) power down control 0: the output amp of the side not selected by crc4 - b5 is powered down. 1: the sounder system output amp and receiver system output amp are both powered on. (2) crc1 (adpcm unit operation mode settings) b7, b6: .......adpcm unit compression algorithm selection (0,0): 32 kbps (0,1): 64 kbps (g.711 through) (1,0): 24 kbps (1,1): 16 kbps b5: .............. transmit side adpcm reset (according to the g.726 specifications): 1: reset the adpcm reset input width should be 125 m s or more. b4: .............. receive side adpcm reset (according to the g.726 specifications): 1: reset the adpcm reset input width should be 125 m s or more. b3: .............. transmit side adpcm data mute: 1: mute b2: .............. receive side adpcm data mute: 1: mute b1: .............. not used b0: .............. receive side pad 0: no pad 1: a pad with a 12 db loss is inserted in the receive side voice path b0 b1 b2 b3 b4 b5 b6 b7 0 0 0 0 0 pdn all 0 0 0 crc0 initial value pdn sao/aout a/ m sel b0 b1 b2 b3 b4 b5 b6 b7 0 0 rx mute 0 0 0 0 0 0 crc1 initial value mode0 rx pad tx reset rx reset tx mute mode1
? semiconductor msm7586-01/03 35/42 (3) crc2 (pcm codec unit operation mode settings and transmit/receive gain adjustment) b0 b1 b2 b3 b4 b5 b6 b7 1 1 0 0 1 1 0 0 crc2 initial value rx on/off tx on/off rx gain2 tx gain2 rx gain1 tx gain1 rx gain0 tx gain0 b7: .............. transmit side pcm signal on/off 0: on 1: off when off, transmits a pcm idle pattern. b6, b5, b4: transmit side signal gain adjustment (refer to table 6) b3: .............. receive side pcm signal on/off 0: on 1: off when off transmits a pcm idle pattern. b2, b1, b0: .receive side signal gain adjustment (refer to table 6) table 6: receive/transmit gain settings ? msm7586-01 ? MSM7586-03 b6 b5 b4 transmit side gain b2 b1 b0 receive side gain 0 0 0 C6 db 0 0 0 C6 db 001 C4 db 001 010 C2 db 010 0 1 1 0 db 0 1 1 100 +2 db 100 101 +4 db 101 110 +6 db 110 111 +8 db 111 C4 db C2 db 0 db +2 db +4 db +6 db +8 db b6 b5 b4 transmit side gain b2 b1 b0 receive side gain 0 0 0 C6 db 0 0 0 C12 db 001 C4 db 001 010 C2 db 010 0 1 1 0 db 0 1 1 100 +2 db 100 101 +4 db 101 110 +6 db 110 111 +8 db 111 C9 db C6 db C3 db 0 db +3 db +6 db +9 db the above gain settings table shows the transmit/receive voice signal gain settings and the transmit side gain settings for dtmf tones and other tones. tone signal transmission is enabled by crc4 - b6 (discussed later), and the gain setting is set to the levels shown below. dtmf tones (low group): ................................. C16 dbm0 dtmf tones (high group) and other tones: ... C14 dbm0 for example, if the transmit gain set value is set to +8 db (b6, b5, b4) = (1, 1, 1), then the following tones appear at the pcmso pin. dtmf tones (low group): ................................. C8 dbm0 dtmf tones (high group) and other tones: ... C6 dbm0
? semiconductor msm7586-01/03 36/42 however, the gain of the receive side tone and the gain of the side tones (path from transmit side to receive side) are set by the crc3 register. (4) crc3 (side tone and tone generator gain adjustment) b7, b6, b5: ........ side tone gain adjustment (refer to table 7) b4: ..................... tone generator on/off 0: off 1: on b3, b2, b1, b0: . tone generator receive side gain adjustment (refer to table 8) table 7: side tone gain settings ? msm7586-01 b0 tone gain0 0 b1 tone gain1 b2 tone gain2 b3 tone gain3 b4 tone on/off b5 side tone gain0 b6 side tone gain1 b7 side tone gain2 0 0 0 0 0 0 0 crc3 initial value b7 b6 b5 side tone gain 000 off 0 0 1 C21 db 0 1 0 C19 db 0 1 1 C17 db 1 0 0 C15 db 1 0 1 C13 db 1 1 0 C11 db 1 1 1 C 9 db ? MSM7586-03 b7 b6 b5 side tone gain 000 off 001 C15 db 010 C13 db 011 C11 db 100 C 9 db 101 C 7 db 110 C 5 db 111 C 3 db
? semiconductor msm7586-01/03 37/42 table 8: receive side tone generator gain settings ? msm7586-01 b3 b2 b1 tone generator gain tone generator gain 0 0 0 C36 db C20 db 0 0 0 C34 db 0 0 1 C32 db 0 0 1 C30 db 010 C28 db 010 C26 db 011 C24 db 111 C22 db C18 db C16 db C14 db C12 db C10 db C 8 db C 6 db b0 0 1 0 1 0 1 0 1 b3 b2 b1 100 100 101 101 110 110 111 111 b0 0 1 0 1 0 1 0 1 ? MSM7586-03 b3 b2 b1 tone generator gain tone generator gain 0 0 0 C20 db 0 0 0 C34 db 0 0 1 C32 db 0 0 1 C30 db 010 C28 db 010 C26 db 011 C24 db 111 C22 db C18 db C16 db C14 db C12 db C10 db C 8 db C 6 db b0 0 1 0 1 0 1 0 1 b3 b2 b1 100 100 101 101 110 110 111 111 b0 0 1 0 1 0 1 0 1 off the receive side tone generator gain settings shown in table 8 are set with the following levels as a reference. dtmf tones (low group): ................................. C2 dbm0 dtmf tones (high group) and other tones: ... 0 dbm0 for example, if the tone generator gain set value is set to -6 db (b3, b2, b1, b0)=(1, 1, 1, 1), then tones at the following levels appear at the sao or vfro pin. dtmf tones (low group): ................................. C8 dbm0 dtmf tones (high group) and other tones: ... C6 dbm0
? semiconductor msm7586-01/03 38/42 (5) crc4 (tone generator operation mode and frequency settings) b7: ........................... selection of dtmf signal and other tones (s tone, f tone, r tone, etc.) 0: other tones 1: dtmf tones b6: ........................... transmission side tone transmit 0: voice signal transmit 1: tone transmit b5: ........................... receive side tone output pin selection 0: vfro output 1: sao output b4, b3, b2, b1, b0: . tone frequency setting (refer to table 9) table 9: tone generator frequency settings (a) when b7 = 1 (dtmf tones) (b) when b7 = 0 (outside of dtmf tones) b4 b3 b2 b1 b0 description 00000 2730 hz/2500 hz 8 hz wamble 00001 2000 hz/2667 hz 8 hz wamble 00010 1000 hz/1333 hz 8 hz wamble 00011 00100 00101 00110 00111 01000 0 1 0 0 1 400 hz single tone 01010 01011 01100 01101 01110 0 1 1 1 1 1000 hz single tone b4 b3 b2 b1 b0 description 10000 0001 1300 hz single tone 0010 1333 hz single tone 0011 0100 0101 2000 hz single tone 0110 0111 1000 1001 1010 1011 1100 2667 hz single tone 1101 1110 2730 hz single tone 1111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b0 b1 b2 b3 b4 b5 b6 b7 0 tone1 0 tone2 0 0 0 0 0 dtmf/ot hers sel 0 crc4 initial value tone0 tone send sao/ vfro tone4 tone3 b4 b3 b2 b1 b0 description * 0 0 0 0 697 hz + 1209 hz * 0 0 0 1 697 hz + 1336 hz * 0 0 1 0 697 hz + 1477 hz * 0 0 1 1 697 hz + 1633 hz * 0 1 0 0 770 hz + 1209 hz * 0 1 0 1 770 hz + 1336 hz * 0 1 1 0 770 hz + 1477 hz * 0 1 1 1 770 hz + 1633 hz b4 b3 b2 b1 b0 description *1000 852 hz + 1209 hz *1001 852 hz + 1336 hz *1010 852 hz + 1477 hz *1011 852 hz + 1633 hz *1100 941 hz + 1209 hz *1101 941 hz + 1336 hz *1110 941 hz + 1477 hz *1111 941 hz + 1633 hz
? semiconductor msm7586-01/03 39/42 (6) crc5 (control of switches, etc.) b7, b6: .......sw1, sw2 control 0: open 1: closed b5: .............. sw3 control 0: open 1: closed b4: .............. sw4/5 control 0: sw4 open, sw5 closed 1: sw4 closed, sw5 open b2, b1, b0: .tout3 to 1 control 0: tout3 to 1 disable 1: tout3 to 1 enable (7) crc6 (vox function control) b7: .............. vox function on/off 0: off 1: on b6, b5: .......transmit side voice/silence detector level settings (for the signal of 1khz) msm7586-01 (0,0): C30 dbm0 (0,1): C35 dbm0 (1,0): C40 dbm0 (1,1): C45 dbm0 MSM7586-03 (0,0): C20 dbm0 (0,1): C26 dbm0 (1,0): C32 dbm0 (1,1): C38 dbm0 b4: .............. hangover time (refer to fig. 7) settings 0: 160 ms 1: 320 ms b3: .............. receive side vox input signal 0: internal background noise transmit 1: voice receive signal transmit when using this data, set the voxi pin to "0." b2: .............. receive side background noise level setting 0: internal automatic setting 1: external (by b1, b0) setting internal automatic setting ? sets to the voice signal level when b3 (voxi) changes from "1" to "0." b1, b0: .......external setting background noise level (0,0): no noise (0,1): C55 dbm0 (1,0): C45 dbm0 (1,1): C35 dbm0 b0 b1 b2 b3 b4 b5 b6 b7 0 0 tout3 cont 0 0 0 0 0 sw1 cont 0 crc5 initial value sw2 cont sw3 cont sw4/5 cont tout2 cont tout1 cont b0 b1 b2 b3 b4 b5 b6 b7 0 0 rx noise level sel 0 0 0 0 0 vox on/off 0 crc6 initial value vox in on lvl1 on lvl0 off time rx noise lvl1 rx noise lvl0
? semiconductor msm7586-01/03 40/42 (8) crc7 (detect register: read-only) b7: ........................... transmit side voice/silence detection 0: silence 1: voice b6, b5: .................... transmit side silence level (indicator) msm7586-01 (0,0):below C60 dbm0 (0,1): C50 to C60 dbm0 (1,0): C40 to C50 dbm0 (1,1): above C40 dbm0 MSM7586-03 (0,0):below C50 dbm0 (0,1): C40 to C50 dbm0 (1,0): C30 to C40 dbm0 (1,1): above C30 dbm0 note: these outputs are enabled when the vox function is turned on by crc6 - b7. b4, b3, b2, b1, b0: . not used b0 b1 b2 b3 b4 b5 b6 b7 * * * * * 0 0 vox out 0 crc7 initial value silent level 1 silent level 0
? semiconductor msm7586-01/03 41/42 application circuit 87 msm7586 pdn2 88 pdn1 89 pdn0 79 denm 78 exckm 77 doutm 76 dinm 69 bsto 71 txci 72 txco 73 txd 74 txw 81 rxd 82 rxc 83 rpr 84 afc 85 rcw 98 sls 99 rxsc 41 pdn3 42 reset 44 dinc 45 doutc 46 exckc 47 denc 61 bclk 60 xsync 59 rsync 57 pcmso 56 pcmsi 55 is 53 ir 52 pcmro 51 pcmri 49 voxi 50 voxo vddm vdam vddc vdac sgm sgcr sgct agc dgc agm dgm ifin qC q+ iC i+ ain1+ ain1C gsx1 ain2 gsx2 aout+ aoutC pwi vfro sao ain3 gsx3 ain4 gsx4 tout1 tout2 tout3 mck ifck x1 100 1 30 29 7 10 11 9 67 8 68 97 2 3 4 5 12 13 14 18 19 25 24 23 22 26 27 28 32 33 38 39 40 90 91 95 x2 92 modem cont. adpcm codec cont. vddc 500 w 19.2 mhz ringer sounder r8 r7 r5 r6 speaker r4 r3 r2 r1 1 m f mic sgct rf 1000 pf 10 m f + C 1 m f 1 m f 10 m f + C 1 m f 1 m f 10 m f + C 1 m f r1 3 output drive resistance of mic r2//r3 3 20 k w r4, r5, r7 3 20 k w r6//input resistance of speaker 3 1.2 k w r8//input resistance of sounder 3 150 w
? semiconductor msm7586-01/03 42/42 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp100-p-1414-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.55 typ. mirror finish

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