w2465 8k 8 cmos static ram publication release date: april 1997 - 1 - revision a8 general description the w2465 is a slow-speed, low-power cmos static ram organized as 8192 8 bits that operates on a single 5-volt power supply. this device is manufactured using winbond's high performance cmos technology. features ? low power consumption: ? active: 250 mw (max.) ? standby: 100 w (max.)(ll-version) 250 w (max.)(l-version) ? access time: 70/100 ns (max.) ? single +5v power supply ? fully static operation ? all inputs and outputs directly ttl compatible ? three-state outputs ? battery back-up operation capability ? data retention voltage: 2v (min.) ? available packages: 28-pin 600 mil dip, 330 mil sop and 300 mil skinny dip pin configuration a8 a9 1 2 3 4 5 25 26 27 28 nc a7 a6 a5 a12 a4 a3 a2 a1 6 7 8 920 21 22 23 a11 a10 i/o8 i/o7 i/o6 i/o5 10 11 12 13 16 17 18 19 a0 i/o2 i/o3 i/o1 14 15 i/o4 cs cs oe we v dd v ss 24 block diagram a0 . cs1 a12 we i/o1 i/o8 oe v v . . data i/o array decoder core cs2 . control dd ss pin description symbol description a0 ? a12 address inputs i/o1 ? i/o8 data inputs/outputs cs1, cs2 chip select inputs we write enable input oe output enable input v dd power supply v ss ground nc no connection
w2465 - 2 - truth table cs1 cs2 oe we mode i/o1 ? i/o8 v dd current h x x x not selected high z i sb , i sb 1 x l x x not selected high z i sb , i sb 1 l h h h output disable high z i dd l h l h read data out i dd l h x l write data in i dd dc characteristics absolute maximum ratings parameter rating unit supply voltage to v ss potential -0.5 to +7.0 v input/output to v ss potential -0.5 to v dd +0.5 v allowable power dissipation 1.0 w storage temperature -65 to +150 c operating temperature 0 to +70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. operating characteristics (v dd = 5v 10%, v ss = 0v, t a = 0 to 70 c) parameter sym. test conditions min. typ. max. unit input low voltage v il - -0.5 - +0.8 v input high voltage v ih - +2.2 - v dd +0.5 v input leakage current i li v in = v ss to v dd -2 - +2 a output leakage current i lo v i/o = v ss to v dd cs1 = v ih (min.) or cs2 = v il (max.) or oe = v ih (min.) or we = v il (max.) -2 - +2 a output low voltage v ol i ol = +4.0 ma - - 0.4 v output high voltage v oh i oh = -1.0 ma 2.4 - - v operating power supply current i dd cs1 = v il (max.), cs2 = v ih (min.) 70 - - 70 ma i/o = 0 ma, cycle = min. duty = 100% 100 - - 60 ma standby power supply current i sb cs1 = v ih (min.) or cs2 = v il (max.), cycle = min. duty = 100% -- 3 ma i sb 1 cs1 v dd -0.2v ll - - 20 a or cs2 0.2v l-- 50 a note: typical characteristics are at v dd = 5 v, t a = 25 c.
w2465 publication release date: april 1997 - 3 - revision a8 capacitance (v dd = 5v, t a = 25 c, f = 1 mhz) parameter sym. conditions max. unit input capacitance c in v in = 0v 6 pf input/output capacitance c i/o v out = 0v 8 pf note: these parameters are sampled but not 100% tested. ac characteristics ac test conditions parameter conditions input pulse levels 0.6v to 2.4v input rise and fall times 5 ns input and output timing reference level 1.5v output load c l = 100 pf, i oh /i ol = -1 ma/4 ma ac test loads and waveform 90% 90% 5 ns 10% 5 ns 10% r1 1000 ohm 5v output r2 660 ohm 100 pf including jig and scope 2.4v 0.6v 5v output r1 1000 ohm 5 pf including jig and scope r2 660 ohm (for t clz1, clz2, olz, chz1, chz2, ohz, whz, ow ttttttt )
w2465 - 4 - ac characteristics, continued (v dd = 5v 10%, v ss = 0v, t a = 0 to 70 c) read cycle parameter sym. w2465-70 w2465-10 unit min. max. min. max. read cycle time t rc 70 - 100 - ns address access time t aa - 70 - 100 ns chip select access time cs1 t acs 1 - 70 - 100 ns cs2 t acs 2 - 70 - 100 ns output enable to output valid t aoe -35-50ns chip selection to output in low z cs1 t clz1 *5 - 10 - ns cs2 t clz2 *5 - 10 - ns output enable to output in low z t olz *5 - 5 - ns chip deselection to output in high z cs1 t chz1 *- 30 - 35 ns cs2 t chz2 *- 30 - 35 ns output disable to output in high z t ohz *- 30 - 35ns output hold from address change t oh 10 - 10 - ns * these parameters are sampled but not 100% tested. write cycle parameter sym. w2465-70 w2465-10 unit min. max. min. max. write cycle time t wc 70 - 100 - ns chip selection to end of write cs1 t cw1 60 - 80 - ns cs2 t cw2 60 - 80 - ns address valid to end of write t aw 60 - 80 - ns address setup time t as 0-0-ns write pulse width t wp 45 - 60 - ns write recovery time cs1 , we t wr1 0-0-ns cs2 t wr2 0-0-ns data valid to end of write t dw 30 - 40 - ns data hold from end of write t dh 0-0-ns write to output in high z t whz *- 30 - 30 ns output disable to output in high z t ohz *- 30 - 30ns output active from end of write t ow 0-0-ns * these parameters are sampled but not 100% tested.
w2465 publication release date: april 1997 - 5 - revision a8 timing waveforms read cycle 1 (address controlled) address t d out oh t aa t rc t oh read cycle 2 (chip select controlled) cs1 cs2 d out t acs1 t acs2 t clz1 t clz2 t chz1 t chz2 read cycle 3 (output enable controlled) address oe cs1 cs2 d out t clz2 t acs2 t clz1 t olz t acs1 t aoe t aa t rc t oh t chz1 t ohz t chz2
w2465 - 6 - timing waveforms, continued write cycle 1 address oe cs1 cs2 we (1, 4) d out d in t wr1 t wc t cw1 t cw2 t wr2 t wp t as t ohz t dw t dh t aw write cycle 2 ( oe = v il fixed) address cs1 cs2 we (2) (3) d out d in t dw t dh t ow t oh t wr2 t wc t cw1 t wr1 t cw2 t aw t wp t as t whz(1, 4) notes: 1. during this period, i/o pins are in the output state, so input signals of opposite phase to the outputs should not be applie d. 2. the data output from d out are the same as the data written to d in during the write cycle. 3. d out provides the read data for the next address. 4. transition is measured 500 mv from steady state with c l = 5 pf. this parameter is guaranteed but not 100% tested.
w2465 publication release date: april 1997 - 7 - revision a8 data retention characteristics (t a = 0 to 70 c) parameter sym. test conditions min. typ. max. unit v dd for data retention v dr cs1 v dd -0.2v, or cs2 0.2v 2.0 - - v data retention current i dddr cs1 v dd -0.2v, or cs2 0.2v ll - - 10 a v dd = 3v l - - 20 a chip deselect to data retention time t cdr see data retention waveforms 0- -ns operation recovery time t r t rc *- - ns t rc * = read cycle time data retention waveforms 4.5v v > 2v data retention mode cs1 4.5v cs2 < 0.2v cs2 = = = dr - 0.2v cs1 > v dd v dd t r t cdr v ih v il v ih v il ordering information part no. access time (ns) operating current max. (ma) standby current max. ( a) package w2465-70ll 70 70 20 600 mil dip w2465-10l 100 60 50 600 mil dip W2465S-70ll 70 70 20 330 mil sop W2465S-10l 100 60 50 330 mil sop w2465k-70ll 70 70 20 300 mil skinny w2465k-10l 100 60 50 300 mil skinny notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
w2465 - 8 - bonding pad diagram 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 20 22 23 24 25 26 x y a12 a7 a6 a5 a4 a3 a2 a1 a0 o0 o1 o2 o4 o5 o6 19 o7 cs1 a10 oe a11 a9 a8 cs2 we v ss v ss v dd 27s-1 27s-2 21 v dd 18 13s-1 13s-2 03 pad no. x y 1 -226.95 1526.15 2 -350.95 1526.15 3 -484.10 1526.15 4 -608.10 1526.15 5 -739.75 1526.15 6 -741.75 1315.10 7 -741.75 -1231.85 8 -741.75 -1456.30 9 -610.60 -1456.30 10 -481.50 -1466.30 11 -343.80 -1466.30 12 -206.10 -1466.30 13s-1 -73.00 -1401.10 13s-2 -8.35 -1212.80 14 60.10 -1466.30 15 193.30 -1466.30 16 332.40 -1466.30 17 465.60 -1466.30 18 603.30 -1466.30 19 738.15 -1456.30 20 740.15 -1221.45 21 740.15 1310.80 22 738.15 1526.15 23 606.50 1526.15 24 482.50 1526.15 25 349.35 1526.15 26 225.35 1526.15 27s-1 94.20 1526.15 27s-2 -50.40 1456.10 note: for bare chip form (c.o.b.) applications, the substrate must be connected to v dd or left floating in the pcb layout.
w2465 publication release date: april 1997 - 9 - revision a8 package dimensions 28-pin p-dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. 1.63 1.47 0.064 0.058 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.460 1.470 37.08 37.34 015 0.090 2.29 0.650 0.630 16.00 16.51 4. dimension b1 does not include dambar protrusion/intrusion. 5. controlling dimension: inches. 15 0 e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 28 1 15 14 28-pin p-dip skinny 1.63 1.47 0.064 0.058 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.370 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.293 0.288 0.283 7.44 7.32 7.19 9.40 7.87 7.62 8.13 0.310 0.300 0.320 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.388 1.400 35.26 35.56 015 0.055 1.40 0.350 0.330 8.38 8.89 15 0 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. notes: 4. dimension b1 does not include dambar protrusion/intrusion. 5. controlling dimension: inches. e a a a c e base plane mounting plane 1 a 1 e l a s 1 e d 1 b b 28 15 1 14 2
w2465 - 10 - package dimensions, continued 28-pin so wide body 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension b does not include dambar protrusion/intrusion. 3. dimension d & e include mold mismatch and determined at the mold parting line. . 0.25 0.20 0.010 0.008 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a l e 1 2 e 0.014 0.36 0.112 2.85 0.004 0.093 0.014 0.098 0.016 0.103 0.020 2.36 0.36 0.10 2.49 0.41 2.62 0.51 0.059 0.004 0 10 0.713 0.067 0.733 0.075 1.50 18.11 1.70 18.62 1.91 0.477 0.465 0.453 12.12 11.81 11.51 10 0 0.10 8.53 8.41 8.28 0.336 0.331 0.326 0.71 0.91 1.12 0.028 0.036 0.044 4. controlling dimension: inches. 5. general appearance spec should be based on final visual inspection spec. 1.12 1.27 1.42 0.044 0.050 0.056 s 1.19 0.047 2 1 a 28 15 14 1 e s eh b seating plane a a y l l e c see detail f d e e 1 1 e detail f headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792647 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.
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