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? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 ? high-current, high- and low-side, gate-drive ic fan7392 rev. 1.0.3 february 2010 fan7392 high-current, high- and low-side, gate-drive ic features ? floating channel for bootstrap operation to +600v ? 3a/3a sourcing/sinking current driving capability ? common-mode dv/dt noise canceling circuit ? 3.3v logic compatible ? separate logic supply (v dd ) range from 3.3v to 20v ? under-voltage lockout for v cc and v bs ? cycle-by-cycle edge-triggered shutdown logic ? matched propagation delay for both channels ? outputs in-phase with input signals ? available in 14-dip and 16-sop (wide) packages applications ? high-speed power mosfet and igbt gate driver ? server power supply ? uninterrupted power supply (ups) ? telecom system power supply ? distributed power supply ? motor drive inverter description the fan7392 is a monolithic high- and low-side gate drive ic, that can drive high-speed mosfets and igbts that operate up to +600v. it has a buffered output stage with all nmos transistors designed for high pulse current driving capability and minimu m cross-conduction. fair- child?s high-voltage process and common-mode noise canceling techniques provi de stable operation of the high-side driver under high dv /dt noise circumstances. an advanced level-shift circuit offers high-side gate driver operation up to v s =-9.8v (typical) for v bs =15v. logic inputs are compatible with standard cmos or lsttl output, down to 3.3v logic. the uvlo circuit prevents malfunction when v cc and v bs are lower than the speci- fied threshold voltage. the high-current and low-output voltage drop feature makes this device suitable for half- and full-bridge inverters, lik e switching-mode power sup- ply and high-power dc-dc converter applications. ordering information for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . 14-pdip 16-sop part number operating temperature range package eco status packing method fan7392n -40c to +125c 14-pdip rohs tube fan7392m 16-sop tube fan7392mx tape and reel
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 2 fan7392 ? high-current, high- and low-side, gate-drive ic typical appli cation diagrams figure 1. typical application circuit (referenced 14-dip) figure 2. typical applicatio n circuit (referenced 16-sop) d boot q1 r boot c boot 15v q2 c1 r2 r1 up to 600v controller hin lin lo com v b v s v dd sd hin nc 13 nc ho v ss nc 12 14 11 10 9 8 2 3 1 4 7 5 6 lin v cc sd 15v load d boot q1 r boot c boot 15v q2 c1 r2 r1 up to 600v controller hin lin lo com v b v s v dd sd hin nc 15 nc ho v ss nc 14 16 13 12 11 10 2 3 1 4 8 6 7 lin v cc sd 15v load nc 5 nc 9
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 3 fan7392 ? high-current, high- and low-side, gate-drive ic internal block diagram figure 3. functional block diagram (referenced 14-pin) figure 4. functional block diagram (referenced 16-sop) uvlo driver pulse generator hin v cc com v b v s r r s q driver hs(on/off) ls(on/off) delay lin uvlo ho lo schmitt trigger input cycle-by-cycle edge triggered shutdown noise canceller vss/com level shift v ss 10 12 13 pin 4, 8, and 14 are no connection sd 11 v dd 9 3 2 6 5 1 7 uvlo driver pulse generator hin v cc com v b v s r r s q driver hs(on/off) ls(on/off) delay lin uvlo ho lo schmitt trigger input cycle-by-cycle edge triggered shutdown noise canceller vss/com level shift v ss 12 14 15 pin 4, 5, 9,10 and 16 are no connection sd 13 v dd 11 3 2 7 6 1 8
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 4 fan7392 ? high-current, high- and low-side, gate-drive ic pin configuration figure 5. pin configurations (top view) pin definitions 14-pin 16-pin name description 1 1 lo low-side driver output 2 2 com low-side return 33v cc low-side supply voltage 56v s high-voltage floating supply return 67v b high-side floating supply 7 8 ho high-side driver output 911v dd logic supply voltage 10 12 hin logic input for high-side gate driver output 11 13 sd logic input for shutdown function 12 14 lin logic input for low-side gate driver output 13 15 v ss logic ground 4,8,14 4, 5, 9, 10, 16 nc no connect lo nc fan7392 hin ho nc v dd com v b v s v ss 1 2 3 4 5 6 7 14 13 12 11 10 9 8 sd nc v cc lin lo nc fan7392m hin ho nc v dd com v b v s v ss 1 2 3 4 5 6 7 16 15 14 13 sd nc v cc lin 12 11 10 9 8 nc nc (a) 14-dip (b) 16-sop (wide body)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 5 fan7392 ? high-current, high- and low-side, gate-drive ic absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera- ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi- tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. t a =25c unless otherwise specified. notes: 1. mounted on 76.2 x 114.3 x 1.6mm pcb (fr-4 glass epoxy material). 2. refer to the following standards: jesd51-2: integral circuits thermal test method environmental conditions, natural convection; and jesd51-3: low effective thermal conductivity test board for leaded surface-mount packages. 3. do not exceed power dissipation (p d ) under any circumstances. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual dev ice operation. recommended operating conditions are specified to ensure optimal perfor mance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol characteristics min. max. unit v b high-side floating supply voltage -0.3 625.0 v v s high-side floating offset voltage v b -25.0 v b +0.3 v v ho high-side floating output voltage v s -0.3 v b +0.3 v v cc low-side supply voltage -0.3 25.0 v v lo low-side floating output voltage -0.3 v cc +0.3 v v dd logic supply voltage -0.3 v ss +25.0 v v ss logic supply offset voltage v cc -25.0 v cc +0.3 v v in logic input voltage (hin, lin and sd) v ss -0.3 v dd +0.3 v dv s /dt allowable offset voltage slew rate 50 v/ns p d power dissipation (1, 2, 3) 14-pdip 1.6 w 16-sop 1.3 ja thermal resistance 14-pdip 75 c/w 16-sop 95 t j maximum junction temperature +150 c t stg storage temperature -55 +150 c symbol parameter min. max. unit v b high-side floating supply voltage v s +10 v s +20 v v s high-side floating supply offset voltage 6-v cc 600 v v ho high-side output voltage v s v b v v cc low-side supply voltage 10 20 v v lo low-side output voltage 0 v cc v v dd logic supply voltage v ss +3 v ss +20 v v ss logic supply offset voltage -5 5 v v in logic input voltage v ss v dd v t a operating ambient temperature -40 +125 c
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 6 fan7392 ? high-current, high- and low-side, gate-drive ic electrical characteristics v bias (v cc , v bs , v dd )=15.0v, v ss =com=0v and t a =25c, unless otherwise specified. the v ih , v il , and i in parameters are referenced to v ss and are applicable to the respective in put leads: hin, lin, and sd. the v o and i o parameters are referenced to v s and com and are applicable to the re spective output leads: ho and lo. symbol characteristics test condition min. typ. max. unit low-side power supply section i qcc quiescent v cc supply current v in =0v or v dd 40 80 a i qdd quiescent v dd supply current v in =0v or v dd 10 a i pcc operating v cc supply current f in =20khz, rms, v in =15v pp 430 a i pdd operating v dd supply current f in =20khz, rms, v in =15v pp 300 a i sd shutdown supply current s d =v dd 120 a v ccuv+ v cc supply under-voltage positive-going threshold voltage v cc =sweep 7.7 8.8 9.9 v v ccuv- v cc supply under-voltage negative-going threshold voltage v cc =sweep 7.3 8.4 9.5 v v ccuvh v cc supply under-voltage lockout hysteresis voltage v cc =sweep 0.4 v bootstrapped supply section i qbs quiescent v bs supply current v in =0v or v dd 60 130 a i pbs operating v bs supply current f in =20khz, rms value 500 a v bsuv+ v bs supply under-voltage positive-going threshold voltage v bs =sweep 7.7 8.8 9.9 v v bsuv- v bs supply under-voltage negative-going threshold voltage v bs =sweep 7.3 8.4 9.5 v v bsuvh v bs supply under-voltage lockout hysteresis voltage v bs =sweep 0.4 v i lk offset supply leakage current v b =v s =600v 50 a input locic section (hin, lin, and sd) v ih logic ?1? input threshold voltage v dd =3v 2.4 v v dd =15v 9.5 v v il logic ?0? input threshold voltage v dd =3v 0.8 v v dd =15v 4.5 v i in+ logic input high bias current v in =v dd 20 40 a i in- logic input low bias current v in =0v 3 a r in logic input pull-down resistance 375 750 k gate driver output section v oh high-level output voltage (v bias - v o ) no load (i o =0a) 1.5 v v ol low-level output voltage no load (i o =0a) 200 mv i o+ output high, short-circuit pulsed current (4) v o =0v, pw 10s 2.5 3.0 a i o- output low, short-circuit pulsed current (4) v o =15v, pw 10s 2.5 3.0 a v ss /com v ss -com/com-v ss voltage educability -5.0 5.0 v - v s allowable negative v s pin voltage for hin signal propagation to ho -9.8 -7.0 v
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 7 fan7392 ? high-current, high- and low-side, gate-drive ic dynamic electrical characteristics v bias (v cc , v bs , v dd )=15.0v, v ss =com=0v, c load =1000pf, t a =25c, unless otherwise specified. note: 4. these parameters guaranteed by design. symbol parameter conditions min. typ. max. unit t on turn-on propagation delay time v s =0v 130 180 ns t off turn-off propagation delay time v s =0v 150 200 ns t sd shutdown propagation delay time (4) 130 180 ns t r turn-on rise time 25 50 ns t f turn-off fall time 20 45 ns mt delay matching, ho & lo turn-on/off 35 ns
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 8 typical characteristics figure 6. turn-on propagation delay vs. temperature figure 7. turn-off propagation delay vs. temperature figure 8. turn-on rise time vs. temperature figure 9. turn-off fall time vs. temperature figure 10. turn-on delay matching vs. temperature fig ure 11. turn-off delay matching vs. temperature -40-20 0 20406080100120 80 100 120 140 160 180 t on [ns] temperature [c] -40-20 0 20406080100120 100 120 140 160 180 200 t off [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 t r [ns] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 t f [ns] temperature [c] -40-20 0 20406080100120 0 10 20 30 mt on [ns] temperature [c] -40-20 0 20406080100120 0 10 20 30 mt off [ns] temperature [c]
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 9 typical characteristics (continued) figure 12. shutdown propagation delay vs. temperature figure 13. logic input high bias current vs. temperature figure 14. quiescent v cc supply current vs. temperature figure 15. quiescent v bs supply current vs. temperature figure 16. operating v cc supply current vs. temperature figure 17. operating v bs supply current vs. temperature -40-20 0 20406080100120 80 100 120 140 160 180 t sd [ns] temperature [c] -40-20 0 20406080100120 0 10 20 30 40 i in+ [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 80 i qcc [ a ] temperature [c] -40 -20 0 20 40 60 80 100 120 0 20 40 60 80 100 120 i qbs [ a ] temperature [c] -40-20 0 20406080100120 0 200 400 600 800 1000 i pcc [ a ] temperature [c] -40-20 0 20406080100120 0 200 400 600 800 1000 i pbs [ a ] temperature [c]
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 10 typical characteristics (continued) figure 18. v cc uvlo+ vs. temperature figure 19. v cc uvlo- vs. temperature figure 20. v bs uvlo+ vs. temperature figure 21. v bs uvlo- vs. temperature figure 22. high-level output voltage vs. temperature figure 23. low-level output voltage vs. temperature -40-20 0 20406080100120 8.0 8.5 9.0 9.5 v ccuv+ [v] temperature [c] -40-20 0 20406080100120 7.5 8.0 8.5 9.0 9.5 v ccuv- [v] temperature [c] -40-20 0 20406080100120 8.0 8.5 9.0 9.5 v bsuv+ [v] temperature [c] -40-20 0 20406080100120 7.5 8.0 8.5 9.0 9.5 v bsuv- [v] temperature [c] -40-20 0 20406080100120 0.0 0.5 1.0 1.5 v oh [v] temperature [c] -40 -20 0 20 40 60 80 100 120 -20 -15 -10 -5 0 5 10 15 20 v ol [mv] temperature [c]
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 11 typical characteristics (continued) figure 24. logic high input voltage vs. temperature figure 25. logic low input voltage vs. temperature figure 26. allowable negative v s voltage vs. temperature f i g u r e 2 7 . i n p u t l o g i c ( h i n & l i n ) t h r e s h o l d v o l t a g e vs. v dd supply voltage . figure 28. allowable negative vs voltage for hin signal propagation to high side vs. supply voltage -40 -20 0 20 40 60 80 100 120 6 7 8 9 10 11 v dd = 15v v ih [v] temperature [c] -40-20 0 20406080100120 3 4 5 6 7 8 9 10 v dd = 15v v il [v] temperature [c] -40-20 0 20406080100120 -12 -11 -10 -9 -8 -7 v s [v] temperature [c] 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 v ih v il logic threshold voltage [v] v dd logic supply voltage [v] 10 11 12 13 14 15 16 17 18 19 20 -16 -14 -12 -10 -8 -6 -4 vs [v] supply voltage [v] v cc =v bs com=0v t a =25 c
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 12 fan7392 ? high-current, high- and low-side, gate-drive ic switching time definitions figure 29. switching time test circuit (referenced 14-dip) figure 30. input/output timing diagram figure 31. switching time waveform definitions 1nf 100nf 1nf 100nf 15v lo com v b v s v dd sd hin nc 13 nc ho v ss nc 14 11 10 9 8 lin v cc 15v 12 2 3 1 4 7 5 6 15v lo ho (0 to 600v) hin sd lin 10 f 10 f 10 f shutdown skip hin lin ho lo sd 50% 90% 50% t on 10% t r t off t f 10% 90% hin lin ho lo
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 13 fan7392 ? high-current, high- and low-side, gate-drive ic switching time definitions (continued) figure 32. shutdown waveform definition figure 33. delay matchi ng waveform definitions 90% 50% t sd ho lo sd hin lin lo 50% 50% 10% 90% ho mt ho lo mt 90% 10%
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 14 application information negative v s transient the bootstrap circuit has the advantage of being simple and low cost, but has some limitations. the biggest diffi- culty with this circuit is the negative voltage present at the emitter of the high-side switching device when high- side switch is turned-off in half-bridge application. if the high-side switch, q1, turns-off while the load cur- rent is flowing to an indu ctive load, a current commuta- tion occurs from high-side switch, q1, to the diode, d2, in parallel with the low-side switch of the same inverter leg. then the negative voltage present at the emitter of the high-side switching device, just before the freewheel- ing diode, d2, starts clamping, causes load current to suddenly flow to the low-side freewheeling diode, d2, as shown in figure 34. figure 34. half-bridge application circuits this negative voltage can be trouble for the gate driver?s output stage, there is the possibility to develop an over- voltage condition of the bootstrap capacitor, input signal missing and latch-up problems because it directly affects the source v s pin of the gate driver, as shown in figure 35. this undershoot voltage is called ?negative v s tran- sient?. figure 35. v s waveforms during q1 turn-off figure 36 and figure 37 show the commutation of the load current between high-side switch, q1, and low-side freewheelling diode, d3, in same inverter leg. the para- sitic inductances in the inverter circuit from the die wire bonding to the pcb tracks are jumped together in l c and l e for each igbt. when the high-side switch, q1, and low-side switch, q4, are turned on, the v s1 node is below dc+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the cir- cuit due to load current is flows from q1 and q4, as shown in figure 36. when the high-side switch, q1, is turned off and q4, remained turned on, the load current to flows the low-side freewheeling diode, d3, due to the inductive load connected to vs1 as shown in figure 37. the current flows from ground (which is connected to the com pin of the gate driver) to the load and the negative voltage present at the emitte r of the high-side switching device. in this case, the com pin of the gate driver is at a higher potential than the v s pin due to the voltage drops associ- ated with freewheeling diode, d3, and parasitic ele- ments, l c3 and l e3 . figure 36. q1 and q4 turn-on figure 37. q1 turn-off and d3 conducting q1 q2 dc+ bus v s i load i freewheeling load d1 d2 q1 v s freewheeling gnd gnd q1 q3 dc+ bus v s1 i load i freewheeling q2 q4 v s2 l c2 l e2 l c4 l e4 l c1 l e1 l c3 l e3 v lc1 v le1 v lc4 v le4 load d1 d3 d2 d4 q1 q3 dc+ bus v s1 i load i freewheeling q2 q4 v s2 l c2 l e2 l c4 l e4 l c1 l e1 l c3 l e3 v lc3 v le3 v lc4 v le4 d1 d3 d2 d4 load
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 15 the fan7392 has a negative v s transient performance curve, as shown in figure 38. figure 38. negative v s transient chracteristic even though the fan7392 has been shown able to han- dle these negative v s tranient conditions, it is strongly recommended that the circuit designer limit the negative v s transient as much as possible by careful pcb layout to minimized the value of parasitic elements and compo- nent use. the amplitude of negative v s voltage is pro- portional to the parasitic inductances and the turn-off speed, di/dt, of the switching device. general guidelines printed circuit board layout the relayout recommended for minimized parasitic ele- ments is as follows: ? direct tracks between switches with no loops or devia- tion. ? avoid interconnect links. these can add significant inductance. ? reduce the effect of lead-inductance by lowering package height above the pcb. ? consider co-locating both power switches to reduce track length. ? to minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side. ? to reduce the em coupling and improve the power switch turn-on/off performa nce, the gate drive loops must be reduced as much as possible. placement of components the recommended placement and selection of compo- nent as follows: ? place a bypass capacitor between the v dd and v ss pins. a ceramic 1f capaci tor is suitable for most applications. this component should be placed as close as possible to the pins to reduce parasitic ele- ments. ? the bypass capacitor from v cc to com supports both the low-side driver and bootstrap capacitor recharge. a value at least ten times higher than the bootstrap capacitor is recommended. ? the bootstrap resistor, r boot , must be considered in sizing the bootstrap resistance and the current devel- oped during initial bootstrap charge. if the resistor is needed in series with the bootstrap diode, verify that v b does not fall below com (ground). recommended use is typically 5 ~ 10 that increase the v bs time constant. if the votage drop of of bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used. ? the bootstrap capacitor, c boot , uses a low-esr capacitor, such as ceramic capacitor. it is stongly recommended t hat the placement of compo- nents is as follows: ? place components tied to the floating voltage pins (v b and v s ) near the respective high-voltage portions of the device and the fan7392. nc (not connected) pins in this package maximize the distance between the high-voltage and low-voltage pins ( see figure 5 ). ? place and route for bypass capacitors and gate resis- tors as close as possible to gate drive ic. ? locate the bootstrap diode, d boot , as close as possi- ble to bootstrap capacitor, c boot . ? the bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode. 0 -10 100 200 300 400 500 600 700 800 900 1000 pulse width [ns] v s [v] -20 -30 -40 -50 -60 -70 -80 -90 -100 0
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 16 fan7392 ? high-current, high- and low-side, gate-drive ic physical dimensions . figure 39. 14-lead dual in-line package (dip) package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . 14 8 7 1 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and tolerances per asme y14.5-1994 e) drawing file name: mkt-n14arev7 6.60 6.09 8.12 7.62 0.35 0.20 19.56 18.80 3.56 3.30 5.33 max 0.38 min 1.77 1.14 0.58 0.35 2.54 3.81 3.17 8.82 (1.74)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 17 fan7392 ? high-current, high- and low-side, gate-drive ic physical dimensions (continued) . figure 40. 16-lead small outline package (sop) package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . pdip8_dim.pdf 2.65 max m16brev2 0.200.10 0.10 c c 10.300.20 a see detail a 0.33 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-013, issue e, dated sept 2005. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p1030x265-16l 9.44 pin one indicator 0.25 1 1.27 0.51 0.35 8 b c a m 10.325 16 9 8.890 7.500.10 b x 45 0.75 0.25 (r0.10) (r0.10) 0.40~1.27 8 0 seating plane (1.40) 0.25 gage plane detail a scale: 2:1 seating plane 1.27 typ 0.55 typ land pattern recommendation 1.75 typ 9.2 10.95 e) drawing filename: mkt-16brev2
fan7392 ? high-current, high- and low-side, gate-drive ic ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan7392 rev. 1.0.3 18

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