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1/18 may 2002 M68AR512DL 8 mbit (512k x16) 1.8v asynchronous sram features summary n supply voltage: 1.65 to 1.95v n 512k x 16 bits sram with output enable n equal cycle and access times: 70ns n single byte read/write n low standby current n low v cc data retention: 1.0v n tri-state common i/o n automatic power down n dual chip enable for easy depth expansion figure 1. packages bga tfbga48 (zb) 8 x 10 mm
M68AR512DL 2/18 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 3. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. address controlled, read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 8. chip enable or output enable controlled, read mode ac waveforms . . . . . . . . . . . . . . 9 figure 9. chip enable or ub/lb controlled, standby mode ac waveforms . . . . . . . . . . . . . . . . . . 9 table 7. read and standby mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10. write enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 11. chip enable controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 12. ub/lb controlled, write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. write mode ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13. e1 controlled, low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . 14 figure 14. e2 controlled, low vcc data retention ac waveforms . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. low vcc data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 tfbga48 8x10mm - 6x8 ball array, 0.75 mm pitch, bottom view package outline. . . . . . . . . . . . 15 tfbga48 8x10mm - 6x8 ball array, 0.75 mm pitch, package mechanical data. . . . . . . . . . . . . . . 15 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3/18 M68AR512DL summary description the M68AR512DL is an 8 mbit (8,388,608 bit) cmos sram, organized as 524,288 words by 16 bits. the device features fully static operation re- quiring no external clocks or timing strobes, with equal address access and cycle times. it requires a single 1.8v ( 150mv) supply. this device has a chip select pin (e2) for easy memory expansion; when it is active (e2 high) the device has an auto- matic power-down feature, reducing the power consumption by over 99%. the M68AR512DL is available in tfbga48 (0.75 mm ball pitch) package. figure 2. logic diagram table 1. signal names ai03953 19 a0-a18 w dq0-dq15 v cc M68AR512DL g 16 e1 ub lb v ss e2 a0-a18 address inputs dq0-dq15 data input/output e1 , e2 chip enable g output enable w write enable ub upper byte enable input lb lower byte enable input v cc supply voltage v ss ground nc not connected du dont use as internally connected
M68AR512DL 4/18 figure 3. tfbga connections (top view through package) ai03960 a 6 5 4 3 2 1 e b f a1 a0 g lb a17 dq7 w a12 du a11 a8 a18 dq0 a3 a6 a5 a4 e1 a10 a9 a13 a7 a2 e2 c dq4 d dq5 a14 a15 g h dq11 nc ub dq10 dq12 dq13 v ss dq15 dq8 dq9 dq14 dq3 dq2 dq1 v cc v cc v ss v ss dq6 a16
5/18 M68AR512DL figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings" table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 2. absolute maximum ratings note: 1. one output at a time, not to exceed 1 second duration. 2. up to a maximum operating v cc of 1.95v only. ai05452 row decoder a8 a18 (8) dq0 dq15 (8) column decoder i/o circuits a0 a7 w g memory array lb lb ub (8) (8) ub lb e1 e2 ex ub lb symbol parameter value unit i o (1) output current 20 ma t a ambient operating temperature C55 to 125 c t stg storage temperature C65 to 150 c v cc supply voltage C0.5 to 2.5 v v io (2) input or output voltage C0.5 to v cc +0.5 v p d power dissipation 1 w
M68AR512DL 6/18 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit parameter M68AR512DL v cc supply voltage 1.65 to 1.95v ambient operating temperature range 1 0 to 70c range 6 C40 to 85c load capacitance (c l ) 30pf output circuit protection resistance (r 1 ) 15.3k w load resistance (r 2 ) 11.3k w input rise and fall times 1ns/v input pulse voltages 0 to v cc input and output timing ref. voltages v cc /2 output transition timing ref. voltages v rl = 0.3v cc ; v rh = 0.7v cc ai04831 v cc i/o timing reference voltage 0v v cc /2 v cc output timing reference voltage 0v 0.7v cc 0.3v cc ai03853 v cc out c l includes probe and 1ttl capacitance device under test c l r 1 r 2
7/18 M68AR512DL table 4. capacitance note: 1. sampled only, not 100% tested. 2. at t a = 25c, f = 1 mhz, v cc = 1.8v. table 5. dc characteristics note: 1. average ac current, cycling at t avav minimum. 2. e1 = v il , e2 = v ih , ub or/and lb = v il , v in = v ih or v il . 3. e1 0.2v or e2 3 v cc C0.2v, lb or/and ub 0.2v, v in 0.2v or v in 3 v cc C0.2v. 4. output disabled. symbol parameter (1,2) test condition min max unit c in input capacitance on all pins (except dq) v in = 0v 6pf c out output capacitance v out = 0v 8pf symbol parameter test condition min typ max unit i cc1 (1,2) operating supply current v cc = 1.95v, f = 1/t avav , i out = 0ma 12 ma i cc2 (3) operating supply current v cc = 1.95v, f = 1mhz, i out = 0ma 2ma i li input leakage current 0v v in v cc C1 1 a i lo (4) output leakage current 0v v out v cc C1 1 a i sb (3) standby supply current cmos v cc = 1.95v, e1 3 v cc C0.2v or e2 0.2v or ub =lb 3 v cc C0.2v, f = 0 115a v ih input high voltage 1.4 v cc + 0.4 v v il input low voltage C0.5 0.4 v v oh output high voltage i oh = C100a 1.5 v v ol output low voltage i ol = 100a 0.2 v
M68AR512DL 8/18 operation the M68AR512DL has a chip enable power down feature which invokes an automatic standby mode whenever chip enable is de-asserted (e1 = high) or chip select is asserted (e2 = low), or ub /lb are de-asserted (ub /lb = high). an output en- able (g ) signal provides a high speed tri-state con- trol, allowing fast read/write cycles to be achieved with the common i/o data bus. operational modes are determined by device control inputs w , e1 , lb and ub as summarized in the operating modes ta- ble (see table 6). table 6. operating modes note: x = v ih or v il . read mode the M68AR512DL, when chip select (e2) is high, is in the read mode whenever write enable (w ) is high with output enable (g ) low, and chip en- able (e1 ) is asserted. this provides access to data from eight or sixteen, depending on the status of the signal ub and lb , of the 8,388,608 locations in the static memory array, specified by the 19 ad- dress inputs. valid data will be available at the eight or sixteen output pins within t avqv after the last stable address, providing g is low and e1 is low. if chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t elqv , t glqv or t blqv ) rather than the address. data out may be indeter- minate at t elqx , t glqx and t blqx , but data lines will always be valid at t avqv . figure 7. address controlled, read mode ac waveforms note: e1 = low, e2 = high, g = low, w = high, ub = low and/or lb = low. operation e1 e2 w g lb ub dq0-dq7 dq8-dq15 power deselected/power-down v ih xxxxx hi-z hi-z standby (i sb ) deselected/power-down x v il xxxx hi-z hi-z standby (i sb ) deselected/power-down xxxx v ih v ih hi-z hi-z standby (i sb ) lower byte read v il v ih v ih v il v il v ih data output hi-z active (i cc ) lower byte write v il v ih v il x v il v ih data input hi-z active (i cc ) output disabled v il v ih x v ih x x hi-z hi-z active (i cc ) upper byte read v il v ih v ih v il v ih v il hi-z data output active (i cc ) upper byte write v il v ih v il x v ih v il hi-z data input active (i cc ) word read v il v ih v ih v il v il v il data output data output active (i cc ) word write v il v ih v il x v il v il data input data input active (i cc ) ai03961 tavav tavqv taxqx a0-a18 dq0-dq7 and/or dq8-dq15 valid data valid
9/18 M68AR512DL figure 8. chip enable or output enable controlled, read mode ac waveforms note: write enable (w ) = high figure 9. chip enable or ub /lb controlled, standby mode ac waveforms ai05994 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a18 e1 g dq0-dq15 valid tblqv tblqx tbhqz ub, lb e2 ai05990 tpd i cc tpu i sb 50% e1, ub, lb e2
M68AR512DL 10/18 table 7. read and standby mode ac characteristics note: 1. test conditions assume transition timing reference level = 0.3v ccq to 0.7v ccq . 2. at any given temperature and voltage condition, t ghqz is less than t glqx , t bhqz is less than t blqx and t ehqz is less than t elqx for any given device. 3. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. 4. tested initially and after any design or process changes that may affect these parameters. symbol parameter M68AR512DL unit 70 t avav read cycle time min 70 ns t avqv address valid to output valid max 70 ns t axqx (1) data hold from address change min 5 ns t bhqz (2, 3) upper/lower byte enable high to output hi-z max 25 ns t blqv upper/lower byte enable low to output valid max 70 ns t blqx (1) upper/lower byte enable low to output transition min 5 ns t ehqz (2, 3) chip enable high to output hi-z max 25 ns t elqv chip enable low to output valid max 70 ns t elqx (1) chip enable low to output transition min 5 ns t ghqz (2, 3) output enable high to output hi-z max 25 ns t glqv output enable low to output valid max 35 ns t glqx (1) output enable low to output transition min 5 ns t pd (4) chip enable high to power down max 0 ns t pu (4) chip enable low to power up min 70 ns
11/18 M68AR512DL write mode the M68AR512DL, when chip select (e2) is high, is in the write mode whenever the w and e1 are low. either the chip enable input (e1 ) or the write enable input (w ) must be de-asserted during ad- dress transitions for subsequent write cycles. when e1 or w is low, and ub or lb is low, write cycle begins on the w or e1 falling edge. when e1 and w are low, and ub = lb = high, write cycle begins on the first falling edge of ub or lb . there- fore, address setup time is referenced to write en- able, chip enables and ub /lb as t avwl , t avel and t avbl respectively, and is determined by the latter occurring falling edge. the write cycle can be terminated by the earlier rising edge of e1 , w , ub and lb . if the output is enabled (e1 = low, e2 = high, g = low, lb or ub = low), then w will return the out- puts to high impedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of operation. data input must be valid for t dvwh before the rising edge of write enable, or for t dveh before the rising edge of e1 or for t d- vbh before the rising edge of ub /lb , whichever occurs first, and remain valid for t whdx , t ehdx and t bhdx respectively. figure 10. write enable controlled, write ac waveforms ai05995 tavav twhax tdvwh data input a0-a18 e1 w dq0-dq15 valid tavwh tavel twlwh tavwl twlqz twhdx twhqx tblbh ub, lb e2 telwh
M68AR512DL 12/18 figure 11. chip enable controlled, write ac waveforms figure 12. ub /lb controlled, write ac waveforms note: 1. during this period dq0-dq15 are in output state and input signals should not be applied. ai05996 tavav tehax tdveh a0-a18 e1 w dq0-dq15 valid taveh tavel tavwl teleh tehdx data input tblbh ub, lb e2 twleh ai05997 tavav tbhax tdvbh data input a0-a18 e1 w dq0-dq15 valid tavbh tavwl twlqz tbhdx tblbh ub, lb data (1) tavbl e2 twlbh
13/18 M68AR512DL table 8. write mode ac characteristics note: 1. at any given temperature and voltage condition, t whqz is less than t wlqx for any given device. 2. these parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to o utput voltage levels. symbol parameter M68AR512DL unit 70 t avav write cycle time min 70 ns t av bh address valid to lb , ub high min 60 ns t avb l addess valid to lb , ub low min 0 ns t av eh address valid to chip enable high min 60 ns t ave l address valid to chip enable low min 0 ns t av wh address valid to write enable high min 60 ns t avw l address valid to write enable low min 0 ns t bhax lb , ub high to address transition min 0 ns t bhdx lb , ub high to input transition min 0 ns t blbh lb , ub low to lb , ub high min 60 ns t bleh lb , ub low to chip enable high min 60 ns t blwh lb , ub low to write enable high min 60 ns t dvbh input valid to lb , ub high min 30 ns t dveh input valid to chip enable high min 30 ns t dvwh input valid to write enable high min 30 ns t ehax chip enable high to address transition min 0 ns t ehdx chip enable high to input transition min 0 ns t elbh chip enable low to lb , ub high min 60 ns t eleh chip enable low to chip enable high min 60 ns t elwh chip enable low to write enable high min 60 ns t whax write enable high to address transition min 0 ns t whdx write enable high to input transition min 0 ns t whqx (1) write enable high to output transition min 5 ns t wlbh write enable low to lb , ub high min 60 ns t wleh write enable low to chip enable high min 60 ns t wlqz (1, 2) write enable low to output hi-z max 20 ns t wlwh write enable low to write enable high min 60 ns
M68AR512DL 14/18 figure 13. e1 controlled, low v cc data retention ac waveforms figure 14. e2 controlled, low v cc data retention ac waveforms table 9. low v cc data retention characteristics note: 1. all other inputs at v ih 3 v cc C0.2v or v il 0.2v. 2. tested initially and after any design or process changes that may affect these parameters. t avav is read cycle time. 3. no input may exceed v cc +0.3v. symbol parameter test condition min typ max unit i ccdr (1) supply current (data retention) v cc = 1.0v, e1 3 v cc C0.2v or e2 0.2v or ub /lb 3 v cc C0.2v, f = 0 (3) 0.1 8 a t cdr (2) chip deselected to data retention time 0ns t r (2) operation recovery time t avav ns v dr (1) supply voltage (data retention) e1 3 v cc C0.2v or e2 0.2v or ub /lb 3 v cc C0.2v, f=0 1.0 v ai05455 data retention mode tr 1.95v tcdr v cc 1.65v v dr > 1.0v e1, ub/lb e1 3 v dr C0.2v or ub=lb > v dr C0.2v ai05475 data retention mode 1.95v v cc 1.65v v dr > 1.0v e2 0.2v tcdr e2 tr
15/18 M68AR512DL package mechanical figure 15. tfbga48 8x10mm - 6x8 ball array, 0.75 mm pitch, bottom view package outline note: drawing is not to scale. table 10. tfbga48 8x10mm - 6x8 ball array, 0.75 mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 3.750 C C 0.1476 C C ddd 0.100 0.0039 e 10.000 9.900 10.100 0.3937 0.3898 0.3976 e1 5.250 C C 0.2067 C C e 0.750 C C 0.0295 C C fd 2.125 C C 0.0837 C C fe 2.375 C C 0.0935 C C sd 0.375 C C 0.0148 C C se 0.375 C C 0.0148 C C e1 e d1 d eb sd se bga-z28 ddd ball "a1" fd fe a2 a1 a
M68AR512DL 16/18 part numbering table 11. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m68ar512 d l 70 zb 6 t device type m68 mode a = asynchronous operating voltage r = 1.65 to 1.95v array organization 512 = 8 mbit (512k x16) option 1 d = 2 chip enable; write and standby from ub and lb option 2 l = low leakage speed class 70 = 70 ns package zb = tfbga48: 0.75 mm pitch operative temperature 1 = 0 to 70 c 6 = C40 to 85 c shipping t = tape & reel packing
17/18 M68AR512DL revision history table 12. document revision history date version revision details august 2001 -01 first issue 08-oct-2001 -02 document status moved to preliminary data 18-mar-2002 -03 document status moved to data sheet temperature range 1 (0 to 70c) added tables 3, 5, 6, 7, 8 and 9 clarified figures 7, 8, 9, 10, 11 and 12 clarified 17-may-2002 -04 document globally revised
M68AR512DL 18/18 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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