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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is n ecessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein.
hitachi 16-bit single-chip microcomputer h8s/2600 series, h8s/2000 series programming manual ade-602-083b rev. 3.0 7/14/2000 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products.
rev. 3.0, 07/00, page iii of 12 preface the h8s/2600 series and the h8s/2000 series are built around an h8s/2000 cpu core. the h8s/2600 and h8s/2000 cpus have the same internal 32-bit architecture. both cpus execute basic instructions in one state, have sixteen 16-bit registers, and have a concise, optimized instruction set. they can address a 16-mbyte linear address space.programs coded in the high- level language c can be compiled to high-speed executable code. for easy migration, the instruction set is upward-compatible with the h8/300h, h8/300, and h8/300l series at the object-code level. the h8s/2600 cpu is upward-compatible with the h8s/2000 cpu at the object-code level, and supports sum of products instructions. this manual gives details of the h8s/2600 and h8s/2000 instructions and can be sued with all microcontrollers in the h8s/2600 series and the h8s/2000 series. for hardware details, refer to the relevant microcontroller hardware manuals.
rev. 3.0, 07/00, page iv of 12
rev. 3.0, 07/00, page v of 12 main revisions and additions in this edition page item revisions (see manual for details) all notes on tas instruction added only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 3.0, 07/00, page vi of 12
rev. 3.0, 07/00, page vii of 12 contents section 1 cpu .................................................................................................................... 1 1.1 overview .................................................................................................................... ....... 1 1.1.1 features ................................................................................................................ 1 1.1.2 differences between h8s/2600 cpu and h8s/2000 cpu................................... 2 1.1.3 differences from h8/300 cpu............................................................................. 3 1.1.4 differences from h8/300h cpu .......................................................................... 4 1.2 cpu operating modes ...................................................................................................... 5 1.3 address space ............................................................................................................... .... 10 1.4 register configuration ...................................................................................................... 11 1.4.1 overview .............................................................................................................. 11 1.4.2 general registers ................................................................................................. 12 1.4.3 control registers.................................................................................................. 13 1.4.4 initial register values .......................................................................................... 15 1.5 data formats ................................................................................................................ ..... 16 1.5.1 general register data formats ............................................................................ 16 1.5.2 memory data formats ......................................................................................... 18 1.6 instruction set ............................................................................................................. ...... 19 1.6.1 overview .............................................................................................................. 19 1.6.2 instructions and addressing modes ..................................................................... 20 1.6.3 table of instructions classified by function........................................................ 22 1.6.4 basic instruction formats..................................................................................... 32 1.7 addressing modes and effective address calculation ..................................................... 33 section 2 instruction descriptions ................................................................................ 41 2.1 tables and symbols.......................................................................................................... .41 2.1.1 assembly-language format ................................................................................ 42 2.1.2 operation.............................................................................................................. 43 2.1.3 condition code .................................................................................................... 44 2.1.4 instruction format................................................................................................ 44 2.1.5 register specification .......................................................................................... 45 2.1.6 bit data access in bit manipulation instructions ................................................ 46 2.2 instruction descriptions .................................................................................................... 47 2.2.1 (1) add (b) .......................................................................................................... 48 2.2.1 (2) add (w)......................................................................................................... 49 2.2.1 (3) add (l) .......................................................................................................... 50 2.2.2 adds .............................................................................................................. 51 2.2.3 addx ............................................................................................................. 52 2.2.4 (1) and (b) .......................................................................................................... 53 2.2.4 (2) and (w)......................................................................................................... 54
rev. 3.0, 07/00, page viii of 12 2.2.4 (3) and (l) .......................................................................................................... 55 2.2.5 (1) andc.............................................................................................................. 56 2.2.5 (2) andc.............................................................................................................. 57 2.2.6 band.............................................................................................................. 58 2.2.7 bcc................................................................................................................... 60 2.2.8 bclr............................................................................................................... 62 2.2.9 biand ............................................................................................................ 64 2.2.10 bild................................................................................................................ 66 2.2.11 bior ............................................................................................................... 68 2.2.12 bist ................................................................................................................ 70 2.2.13 bixor............................................................................................................. 72 2.2.14 bld ................................................................................................................. 74 2.2.15 bnot .............................................................................................................. 76 2.2.16 bor................................................................................................................. 78 2.2.17 bset ............................................................................................................... 80 2.2.18 bsr ................................................................................................................. 82 2.2.19 bst.................................................................................................................. 84 2.2.20 btst ............................................................................................................... 86 2.2.21 bxor.............................................................................................................. 88 2.2.22 clrmac ........................................................................................................ 90 2.2.23 (1) cmp (b) .......................................................................................................... 91 2.2.23 (2) cmp (w) ......................................................................................................... 92 2.2.23 (3) cmp (l) .......................................................................................................... 93 2.2.24 daa ................................................................................................................ 94 2.2.25 das ................................................................................................................. 96 2.2.26 (1) dec (b)........................................................................................................... 98 2.2.26 (2) dec (w).......................................................................................................... 99 2.2.26 (3) dec (l)........................................................................................................... 100 2.2.27 (1) divxs (b) ...................................................................................................... 101 2.2.27 (2) divxs (w) ..................................................................................................... 103 2.2.28 (1) divxu (b)...................................................................................................... 105 2.2.28 (2) divxu (w)..................................................................................................... 107 2.2.29 (1) eepmov (b) .................................................................................................. 109 2.2.29 (2) eepmov (w) ................................................................................................. 110 2.2.30 (1) exts (w)........................................................................................................ 112 2.2.30 (2) exts (l)......................................................................................................... 113 2.2.31 (1) extu (w)....................................................................................................... 114 2.2.31 (2) extu (l) ........................................................................................................ 115 2.2.32 (1) inc (b)............................................................................................................ 11 6 2.2.32 (2) inc (w)........................................................................................................... 117 2.2.32 (3) inc (l) ............................................................................................................ 11 8 2.2.33 jmp.................................................................................................................. 119 2.2.34 jsr................................................................................................................... 120
rev. 3.0, 07/00, page ix of 12 2.2.35 (1) ldc (b)........................................................................................................... 122 2.2.35 (2) ldc (b)........................................................................................................... 123 2.2.35 (3) ldc (w).......................................................................................................... 124 2.2.35 (4) ldc (w).......................................................................................................... 126 2.2.36 ldm ................................................................................................................ 128 2.2.37 ldmac........................................................................................................... 130 2.2.38 mac................................................................................................................ 131 2.2.39 (1) mov (b) ......................................................................................................... 134 2.2.39 (2) mov (w) ........................................................................................................ 135 2.2.39 (3) mov (l).......................................................................................................... 136 2.2.39 (4) mov (b) ......................................................................................................... 137 2.2.39 (5) mov (w) ........................................................................................................ 139 2.2.39 (6) mov (l).......................................................................................................... 141 2.2.39 (7) mov (b) ......................................................................................................... 143 2.2.39 (8) mov (w) ........................................................................................................ 145 2.2.39 (9) mov (l).......................................................................................................... 147 2.2.40 movfpe......................................................................................................... 149 2.2.41 movtpe......................................................................................................... 150 2.2.42 (1) mulxs (b)..................................................................................................... 151 2.2.42 (2) mulxs (w).................................................................................................... 152 2.2.43 (1) mulxu (b) .................................................................................................... 153 2.2.43 (2) mulxu (w) ................................................................................................... 154 2.2.44 (1) neg (b) .......................................................................................................... 155 2.2.44 (2) neg (w) ......................................................................................................... 156 2.2.44 (3) neg (l)........................................................................................................... 157 2.2.45 nop ................................................................................................................. 158 2.2.46 (1) not (b) .......................................................................................................... 159 2.2.46 (2) not (w) ......................................................................................................... 160 2.2.46 (3) not (l)........................................................................................................... 161 2.2.47 (1) or (b) ............................................................................................................. 16 2 2.2.47 (2) or (w) ............................................................................................................ 163 2.2.47 (3) or (l) ............................................................................................................. 16 4 2.2.48 (1) orc................................................................................................................. 1 65 2.2.48 (2) orc................................................................................................................. 1 66 2.2.49 (1) pop (w) .......................................................................................................... 167 2.2.49 (2) pop (l)............................................................................................................ 16 8 2.2.50 (1) push (w) ....................................................................................................... 169 2.2.50 (2) push (l)......................................................................................................... 170 2.2.51 (1) rotl (b) ........................................................................................................ 171 2.2.51 (2) rotl (b) ........................................................................................................ 172 2.2.51 (3) rotl (w) ....................................................................................................... 173 2.2.51 (4) rotl (w) ....................................................................................................... 174 2.2.51 (5) rotl (l) ........................................................................................................ 175
rev. 3.0, 07/00, page x of 12 2.2.51 (6) rotl (l) ........................................................................................................ 176 2.2.52 (1) rotr (b) ........................................................................................................ 177 2.2.52 (2) rotr (b) ........................................................................................................ 178 2.2.52 (3) rotr (w)....................................................................................................... 179 2.2.52 (4) rotr (w)....................................................................................................... 180 2.2.52 (5) rotr (l) ........................................................................................................ 181 2.2.52 (6) rotr (l) ........................................................................................................ 182 2.2.53 (1) rotxl (b) ..................................................................................................... 183 2.2.53 (2) rotxl (b) ..................................................................................................... 184 2.2.53 (3) rotxl (w) .................................................................................................... 185 2.2.53 (4) rotxl (w) .................................................................................................... 186 2.2.53 (5) rotxl (l)...................................................................................................... 187 2.2.53 (6) rotxl (l)...................................................................................................... 188 2.2.54 (1) rotxr (b) ..................................................................................................... 189 2.2.54 (2) rotxr (b) ..................................................................................................... 190 2.2.54 (3) rotxr (w) .................................................................................................... 191 2.2.54 (4) rotxr (w) .................................................................................................... 192 2.2.54 (5) rotxr (l) ..................................................................................................... 193 2.2.54 (6) rotxr (l) ..................................................................................................... 194 2.2.55 rte ................................................................................................................. 195 2.2.56 rts.................................................................................................................. 197 2.2.57 (1) shal (b) ........................................................................................................ 198 2.2.57 (2) shal (b) ........................................................................................................ 199 2.2.57 (3) shal (w) ....................................................................................................... 200 2.2.57 (4) shal (w) ....................................................................................................... 201 2.2.57 (5) shal (l) ........................................................................................................ 202 2.2.57 (6) shal (l) ........................................................................................................ 203 2.2.58 (1) shar (b) ........................................................................................................ 204 2.2.58 (2) shar (b) ........................................................................................................ 205 2.2.58 (3) shar (w)....................................................................................................... 206 2.2.58 (4) shar (w)....................................................................................................... 207 2.2.58 (5) shar (l) ........................................................................................................ 208 2.2.58 (6) shar (l) ........................................................................................................ 209 2.2.59 (1) shll (b)......................................................................................................... 210 2.2.59 (2) shll (b)......................................................................................................... 211 2.2.59 (3) shll (w)........................................................................................................ 212 2.2.59 (4) shll (w)........................................................................................................ 213 2.2.59 (5) shll (l)......................................................................................................... 214 2.2.59 (6) shll (l)......................................................................................................... 215 2.2.60 (1) shlr (b) ........................................................................................................ 216 2.2.60 (2) shlr (b) ........................................................................................................ 217 2.2.60 (3) shlr (w) ....................................................................................................... 218 2.2.60 (4) shlr (w) ....................................................................................................... 219
rev. 3.0, 07/00, page xi of 12 2.2.60 (5) shlr (l)......................................................................................................... 220 2.2.60 (6) shlr (l)......................................................................................................... 221 2.2.61 sleep ............................................................................................................. 222 2.2.62 (1) stc (b) ........................................................................................................... 223 2.2.62 (2) stc (b) ........................................................................................................... 224 2.2.62 (3) stc (w) .......................................................................................................... 225 2.2.62 (4) stc (w) .......................................................................................................... 227 2.2.63 stm................................................................................................................. 229 2.2.64 stmac ........................................................................................................... 231 2.2.65 (1) sub (b)........................................................................................................... 233 2.2.65 (2) sub (w).......................................................................................................... 235 2.2.65 (3) sub (l) ........................................................................................................... 236 2.2.66 subs ............................................................................................................... 237 2.2.67 subx .............................................................................................................. 238 2.2.68 tas ................................................................................................................. 239 2.2.69 trapa............................................................................................................ 240 2.2.70 (1) xor (b) .......................................................................................................... 242 2.2.70 (2) xor (w) ......................................................................................................... 243 2.2.70 (3) xor (l) .......................................................................................................... 244 2.2.71 (1) xorc.............................................................................................................. 245 2.2.71 (2) xorc.............................................................................................................. 246 2.3 instruction set ............................................................................................................. ...... 247 2.4 instruction code ............................................................................................................ .... 263 2.5 operation code map ......................................................................................................... 2 74 2.6 number of states required for instruction execution ...................................................... 278 2.7 bus states during instruction execution........................................................................... 290 2.8 condition code modification............................................................................................ 304 section 3 processing states ............................................................................................ 309 3.1 overview .................................................................................................................... ....... 309 3.2 reset state ................................................................................................................. ........ 310 3.3 exception-handling state.................................................................................................. 31 1 3.3.1 types of exception handling and their priority ................................................. 311 3.3.2 reset exception handling.................................................................................... 312 3.3.3 trace..................................................................................................................... 312 3.3.4 interrupt exception handling and trap instruction exception handling............. 312 3.4 program execution state ................................................................................................... 31 3 3.5 bus-released state .......................................................................................................... .. 314 3.6 power-down state............................................................................................................ . 314 3.6.1 sleep mode........................................................................................................... 314 3.6.2 software standby mode ....................................................................................... 314 3.6.3 hardware standby mode...................................................................................... 314
rev. 3.0, 07/00, page xii of 12 section 4 basic timing .................................................................................................... 315 4.1 overview .................................................................................................................... ....... 315 4.2 on-chip memory (rom, ram) ...................................................................................... 315 4.3 on-chip supporting module access timing.................................................................... 317 4.4 external address space access timing............................................................................ 318
rev. 3.0, 07/00, page 1 of 320 section 1 cpu 1.1 overview the h8s/2600 cpu and the h8s/2000 cpu are high-speed central processing units with a common an internal 32-bit architecture. each cpu is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2600 cpu and h8s/2000 cpu have sixteen 16-bit general registers, can address a 4-gbyte linear address space, and are ideal for realtime control. 1.1.1 features the h8s/2600 cpu and h8s/2000 cpu have the following features. upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) sixty-nine basic instructions (h8s/2000 cpu has sixty-five) ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? multiply-and-accumulate instruction (h8s/2600 cpu only) eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @Cern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] 4-gbyte address space ? program: 16 mbytes ? data: 4 gbytes
rev. 3.0, 07/00, page 2 of 320 high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock frequency: 20 mhz ? 8/16/32-bit register-register add/subtract: 50 ns ? 8 8-bit register-register multiply: 150 ns (h8s/2000 cpu: 600 ns) ? 16 ? 8-bit register-register divide: 600 ns ? 16 16-bit register-register multiply: 200 ns (h8s/2000 cpu: 1000 ns) ? 32 ? 16-bit register-register divide: 1000 ns two cpu operating modes ? normal mode ? advanced mode power-down modes ? transition to power-down state by sleep instruction ? cpu clock speed selection 1.1.2 differences between h8s/2600 cpu and h8s/2000 cpu differences between the h8s/2600 cpu and the h8s/2000 cpu are as follows. register configuration ? the mac register is supported only by the h8s/2600 cpu. for details, see section 1.4, register configuration. basic instructions ? the mac, clrmac, ldmac, and stmac instructions are supported only by the h8s/2600 cpu. for details, see section 1.6, instruction set, and section 2, instruction descriptions. number of states required for execution ? the number of states required for execution of the mulxu and mulxs instructions. for details, see section 2.6, number of states required for execution. in addition, there may be defferences in address spaces, exr register functions, power-down states, and so on. for details, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 3 of 320 1.1.3 differences from h8/300 cpu in comparison with the h8/300 cpu, the h8s/2600 cpu and h8s/2000 cpu have the following enhancements. more general registers and control registers ? eight 16-bit registers, one 8-bit and two 32-bit control registers have been added. expanded address space ? normal mode supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 4-gbyte address space. enhanced addressing ? the addressing modes have been enhanced to make effective use of the 4-gbyte address space. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? a multiply-and-accumulate instruction has been added. (h8s/2600cpu only) ? two-bit shift and rotate instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast.
rev. 3.0, 07/00, page 4 of 320 1.1.4 differences from h8/300h cpu in comparison with the h8/300h cpu, the h8s/2600 cpu and h8s/2000 cpu have the following enhancements. additional control register ? one 8-bit and two 32-bit control registers have been added. expanded address space ? advanced mode supports a maximum 4-gbyte data address space. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? a multiply-and-accumulate instruction has been added (h8s/2600 cpu only). ? two-bit shift and rotate instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast.
rev. 3.0, 07/00, page 5 of 320 1.2 cpu operating modes like the h8/300h cpu, the h8s/2600 cpu has two operating modes: normal and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 4-gbyte total address space, of which up to 16 mbytes can be used for program code and up to 4 gbytes for data. the mode is selected with the mode pins of the microcontroller. for further information, refer to the relevant microcontroller hardware manual. cpu operating modes normal mode advanced mode maximum 64 kbytes, program and data areas combined maximum 16-mbyte program area and 4-gbyte data area, maximum 4 gbytes for program and data areas combined figure 1.1 cpu operating modes (1) normal mode the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed, as in the h8/300 cpu. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (r0 to r7) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@Crn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register will be affected. instruction set: all additional instructions and addressing modes not found in the h8/300 cpu can be used. only the lower 16 bits of effective addresses (ea) are valid.
rev. 3.0, 07/00, page 6 of 320 exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits (figure 1.2). the exception vector table differs depending on the microcontroller. refer to the relevant microcontroller hardware manual for further information. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b power-on reset exception vector manual reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 1.2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16-bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table.
rev. 3.0, 07/00, page 7 of 320 stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 1.3. when exr is invalid, it is not pushed onto the stack. for details, see the relevant hardware manual. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1, * 3 ccr ccr * 3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored on return. (sp ) * 2 figure 1.3 stack structure in normal mode (2) advanced mode in advanced mode the data address space is larger than for the h8/300h cpu. address space: the 4-gbyte maximum address space provides linear access to a maximum 16 mbytes of program code and maximum 4 gbytes of data. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used.
rev. 3.0, 07/00, page 8 of 320 exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 1.4). the exception vector table differs depending on the microcontroller. refer to the relevant microcontroller hardware manual for further information. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved power-on reset exception vector (reserved for system use) reserved exception vector 1 reserved manual reset exception vector h'00000010 h'00000008 h'00000007 figure 1.4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the top area from h'00000000 to h'000000ff. note that this area is also used for the exception vector table.
rev. 3.0, 07/00, page 9 of 320 stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 1.5. when exr is invalid, it is not pushed onto the stack. for details, see the relevant hardware manual. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1, * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored on return. (sp ) * 2 reserved figure 1.5 stack structure in advanced mode
rev. 3.0, 07/00, page 10 of 320 1.3 address space figure 1.6 shows a memory map of the h8s/2600 cpu. the h8s/2600 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 4-gbyte address space in advanced mode. the address space differs depending on the operating mode. for details, refer to the relevant microcontroller hardware manual. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode data area program area figure 1.6 memory map
rev. 3.0, 07/00, page 11 of 320 1.4 register configuration 1.4.1 overview the cpus have the internal registers shown in figure 1.7. there are two types of registers: general registers and control registers. the h8s/2000 cpu does not support the mac register. t i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit sp: pc: exr: t: i2 to i0: ccr: i: ui: er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 sign extension 63 32 41 0 31 mac macl half-carry flag user bit negative flag zero flag overflow flag carry flag multiply-accumulate register h: u: n: z: v: c: mac: mach figure 1.7 cpu registers
rev. 3.0, 07/00, page 12 of 320 1.4.2 general registers the cpus have eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 1.8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 1.8 usage of general registers
rev. 3.0, 07/00, page 13 of 320 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 1.9 shows the stack. free area stack area sp (er7) figure 1.9 stack 1.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), 8-bit condition-code register (ccr), and 64-bit multiply-accumulate register (mac: h8s/2600 cpu only). (1) program counter (pc) this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant pc bit is ignored. when an instruction is fetched, the least significant pc bit is regarded as 0. (2) extended control register (exr) this 8-bit register contains the trace bit (t) and three interrupt mask bits (i2 to i0). bit 7trace bit (t): selects trace mode. when this bit is cleared to 0, instructions are executed in sequence. when this bit is set to 1, a trace exception is generated each time an instruction is executed. bits 6 to 3reserved: these bits are reserved, always read as 1. bits 2 to 0interrupt mask bits (i2 to i0): these bits designate the interrupt mask level (0 to 7). for details refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 14 of 320 operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. all interrupts, including nmi, are disabled for three states after one of these instructions is executed, except for stc. (3) condition-code register (ccr) this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7interrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception- handling sequence. bit 6user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. this bit can also be used as an interrupt mask bit. for details refer to the relevant microcontroller hardware manual. bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to the detailed descriptions of the instructions starting in section 2.2.1.
rev. 3.0, 07/00, page 15 of 320 operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. (4) multiply-accumulate register (mac) the mac register is supported only by the h8s/2600 cpu. this 64-bit register stores the results of multiply-and-accumulate operations. it consists of two 32-bit registers denoted mach and macl. the lower 10 bits of mach are valid; the upper bits are a sign extension. 1.4.4 initial register values reset exception handling loads the cpus program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset.
rev. 3.0, 07/00, page 16 of 320 1.5 data formats the cpus can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 1.5.1 general register data formats figure 1.10 shows the data formats in general registers. 76543210 dont care 70 dont care 76543210 43 70 70 dont care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb dont care upper lower 43 70 dont care 70 dont care 70 figure 1.10 general register data formats
rev. 3.0, 07/00, page 17 of 320 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern figure 1.10 general register data formats (cont)
rev. 3.0, 07/00, page 18 of 320 1.5.2 memory data formats figure 1.11 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 1.11 memory data formats when the stack pointer (er7) is used as an address register to access the stack, the operand size should be word size or longword size.
rev. 3.0, 07/00, page 19 of 320 1.6 instruction set 1.6.1 overview the h8s/2600 cpu has 69types of instructions, while the h8s/2000 cpu has 65 types. the instructions are classified by function as shown in table 1.1. for a detailed description of each instruction, see section 2.2, instruction descriptions. table 1.1 instruction classification function instructions size types mov bwl pop * 2 , push * 2 wl ldm, stm l data transfer movfpe, movtpe b 5 add, sub, cmp, neg bwl addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas * 4 b 19 arithmetic operations mac, ldmac, stmac, clrmac * 1 4 * 1 logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 3 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 h8s/2600 cpu: total 69 types h8s/2000 cpu: total 65 types notes: bbyte size; wword size; llongword size. 1. the mac, ldmac, stmac, and clrmac instructions are supported only by the h8s/2600 cpu. 2. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @C sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @Csp. 3. bcc is the generic designation of a conditional branch instruction. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 3.0, 07/00, page 20 of 320 1.6.2 instructions and addressing modes table 1.2 indicates the combinations of instructions and addressing modes that the h8s/2600 cpu and h8s/2000 cpu can use. table 1.2 combinations of instructions and addressing modes addressing modes function instruction data mov bwl bwl bwl bwl bwl bwl b bwl bwl transfer pop, push wl ldm, stm l movepe, b movtpe arithmetic add, cmp bwl bwl operations sub wlbwl addx, subx b b adds, subs l inc, dec bwl daa, das b mulxu, bw divxu mulxs, bw divxs neg bwl extu, exts wl tas * 2 b mac * 1 clrmac * 1 ldmac * 1 , l stmac * 1 #xx rn @ern @(d:16,ern) @(d:32,ern) @Cern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8
rev. 3.0, 07/00, page 21 of 320 addressing modes function instruction logic and, or, bwl bwl operations xor not bwl shift bwl bit manipulation b b b b b branch bcc, bsr jmp, jsr rts system trapa control rte sleep ldc b b wwwwww stc b wwwwww andc, b orc, xorc nop block data transfer bw legend b: byte w: word l: longword notes: 1. supported only by the h8s/2600 cpu 2. only register er0, er1, er4, or er5 should be used when using the tas instruction. #xx rn @ern @(d:16,ern) @(d:32,ern) @Cern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8
rev. 3.0, 07/00, page 22 of 320 1.6.3 table of instructions classified by function table 1.3 summarizes the instructions in each functional category. the notation used in table 1.3 is defined next. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication ? division logical and logical or ? logical exclusive or ? move ? logical not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
rev. 3.0, 07/00, page 23 of 320 table 1.3 instructions classified by function type instruction size * 1 function mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b (eas) ? rd moves external memory contents (addressed by @aa:16) to a general register in synchronization with an e clock. movtpe b rs ? (eas) moves general register contents to an external memory location (addressed by @aa:16) in synchronization with an e clock. pop w/l @sp+ ? rn pops a register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn ? @Csp pushes a register onto the stack. push.w rn is identical to mov.w rn, @Csp. push.l ern is identical to mov.l ern, @Csp. ldm l @sp+ ? rn (register list) pops two or more general registers from the stack. data transfer stm l rn (register list) ? @Csp pushes two or more general registers onto the stack.
rev. 3.0, 07/00, page 24 of 320 type instruction size * 1 function add sub b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx brd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 ? rd, rd 2 ? rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs lrd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust ? rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4- bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. divxu b/w rd ? rs ? rd performs unsigned division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. arithmetic operations divxs b/w rd ? rs ? rd performs signed division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder.
rev. 3.0, 07/00, page 25 of 320 type instruction size * 1 function cmp b/w/l rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 C rd ? rd takes the twos complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd C 0, 1 ? ( of @erd) * 2 tests memory contents, and sets the most significant bit (bit 7) to 1. mac (eas) (ead) + mac ? mac performs signed multiplication on memory contents and adds the result to the multiply-accumulate register. the following operations can be performed: 16 bits 16 bits +32 bits ? 32 bits, saturating 16 bits 16 bits + 42 bits ? 42 bits, non-saturating supported by h8s/2600 cpu only. clrmac 0 ? mac clears the multiply-accumulate register to zero. supported by h8s/2600 cpu only. arithmetic operations ldmac stmac lrs ? mac, mac ? rd transfers data between a general register and the multiply-accumulate register. supported by h8s/2600 cpu only.
rev. 3.0, 07/00, page 26 of 320 type instruction size * 1 function and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. logic operations not b/w/l ? (rd) ? (rd) takes the ones complement of general register contents. shal shar b/w/l rd (shift) ? rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) ? rd performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) ? rd rotates general register contents. 1-bit or 2-bit rotation is possible. shift operations rotxl rotxr b/w/l rd (rotate) ? rd rotates general register contents through the carry bit. 1-bit or 2-bit rotation is possible.
rev. 3.0, 07/00, page 27 of 320 type instruction size * 1 function bset b 1 ? ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ? ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ? ( of ) ? ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ? ( of ) ? z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band b c ( of ) ? c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. biand b c ? ( of ) ? c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor b c ( of ) ? c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. bit-manipulation instructions bior b c ? ( of ) ? c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data.
rev. 3.0, 07/00, page 28 of 320 type instruction size * 1 function bxor b c ? ( of ) ? c exclusive-ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. bixor b c ? ? ( of ) ? c exclusive-ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld b ( of ) ? c transfers a specified bit in a general register or memory operand to the carry flag. bild b ? ( of ) ? c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst b c ? ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. bit-manipulation instructions bist b ? c ? ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data.
rev. 3.0, 07/00, page 29 of 320 type instruction size * 1 function branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear (high or same) c = 0 bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 bcc jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. branch instructions rts returns from a subroutine
rev. 3.0, 07/00, page 30 of 320 type instruction size * 1 function trapa starts trap-instruction exception handling. rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ? ccr, (eas) ? exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr ? (ead), exr ? (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ? ccr, exr #imm ? exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ? ccr, exr #imm ? exr logically ors the ccr or exr contents with immediate data. xorc b ccr ? #imm ? ccr, exr ? #imm ? exr logically exclusive-ors the ccr or exr contents with immediate data. system control instructions nop pc + 2 ? pc only increments the program counter.
rev. 3.0, 07/00, page 31 of 320 type instruction size * 1 function eepmov.b if r4l 1 0 then repeat @er5+ ? @er6+ r4l C 1 ? r4l until r4l = 0 else next; eepmov.w if r4 1 0 then repeat @er5+ ? @er6+ r4 C 1 ? r4 until r4 = 0 else next; block data transfer instruction transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed. notes: 1. size refers to the operand size. b: byte w: word l: longword 2. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 3.0, 07/00, page 32 of 320 1.6.4 basic instruction formats the h8s/2600 or h8s/2000 instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc). operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. condition field: specifies the branching condition of bcc instructions. figure 1.12 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:8, etc figure 1.12 instruction formats
rev. 3.0, 07/00, page 33 of 320 1.7 addressing modes and effective address calculation (1) addressing modes the cpus support the eight addressing modes listed in table 1.4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 1.4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) register indirect with post-increment @ern+ 4 register indirect with pre-decrement @Cern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 1. register directrn: the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 2. register indirect@ern: the register field of the instruction code specifies an address register (ern) which contains the address of the operand in memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). 3. register indirect with displacement@(d:16, ern) or @(d:32, ern): a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added.
rev. 3.0, 07/00, page 34 of 320 4. register indirect with post-increment or pre-decrement@ern+ or @Cern: register indirect with post-increment@ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. register indirect with pre-decrement@Cern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. for word or longword access, the register value should be even. 5. absolute address@aa:8, @aa:16, @aa:24, or @aa:32: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 1.5 indicates the accessible absolute address ranges. table 1.5 absolute address access ranges absolute address normal mode advanced mode 8 bits (@aa:8) h'ff00 to h'ffff h'ffffff00 to h'ffffffff 16 bits (@aa:16) h'00000000 to h'00007fff, h'ffff8000 to h'ffffffff data address 32 bits (@aa:32) h'00000000 to h'ffffffff program instruction address 24 bits (@aa:24) h'0000 to h'ffff h'00000000 to h'00ffffff for further details on the accessible range, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 35 of 320 6. immediate#xx:8, #xx:16, or #xx:32: the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 7. program-counter relative@(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is C126 to +128 bytes (C63 to +64 words) or C32766 to +32768 bytes (C16383 to +16384 words) from the branch instruction. the resulting value should be an even number. 8. memory indirect@@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction specifies a memory operand by an 8-bit absolute address. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff in normal mode, h'00000000 to h'000000ff in advanced mode). in normal mode the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details refer to the relevant microcontroller hardware manual. (a) normal mode (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address figure 1.13 branch address specification in memory indirect mode
rev. 3.0, 07/00, page 36 of 320 if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or an instruction code to be fetched at the address preceding the specified address. (for further information, see section 1.5.2, memory data formats.) (2) effective address calculation table 1.6 indicates how effective addresses are calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
rev. 3.0, 07/00, page 37 of 320 table 1.6 effective address calculation register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 ? register indirect with pre-decrement @Cern 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp
rev. 3.0, 07/00, page 38 of 320 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffffff sign extension h'00
rev. 3.0, 07/00, page 39 of 320 31 0 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 ? normal mode ? advanced mode 0 no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 31 8 7 0 15 0 31 8 7 0 23 disp h'000000 abs h'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs sign extension pc contents abs memory contents memory contents reserved h'00 h'0000 h'00
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rev. 3.0, 07/00, page 41 of 320 section 2 instruction descriptions 2.1 tables and symbols this section explains how to read the tables in section 2.2, describing each instruction. note that the descriptions of some instructions extend over more than one page. [1] mnemonic (full name) [2] type [3] operation [4] assembly-language format [5] operand size [6] condition code [7] description [8] available registers [9] operand format and number of states required for execution [10] notes [1] mnemonic (full name): gives the full and mnemonic names of the instruction. [2] type: indicates the type of instruction. [3] operation: describes the instruction in symbolic notation. (see section 2.1.2, operation.) [4] assembly-language format: indicates the assembly-language format of the instruction. (see section 2.1.1, assembler format.) [5] operand size: indicates the available operand sizes. [6] condition code: indicates the effect of instruction execution on the flag bits in the ccr. (see section 2.1.3, condition code.) [7] description: describes the operation of the instruction in detail. [8] available registers: indicates which registers can be specified in the register field of the instruction. [9] operand format and number of states required for execution: shows the addressing modes and instruction format together with the number of states required for execution. [10] notes: gives notes concerning execution of the instruction.
rev. 3.0, 07/00, page 42 of 320 2.1.1 assembly-language format example: add. b , rd destination operand source operand size mnemonic the operand size is byte (b), word (w), or longword (l). some instructions are restricted to a limited set of operand sizes. the symbol indicates that two or more addressing modes can be used. the h8s/2600 cpu supports the eight addressing modes listed next. effective address calculation is described in section 1.7, addressing modes and effective address calculation. symbol addressing mode rn register direct @ern register indirect @(d:16, ern)/@(d:32, ern) register indirect with displacement (16-bit or 32-bit) @ern+/@Cern register indirect with post-increment or pre-decrement @aa:8/@aa:16/@aa:24/@aa:32 absolute address (8-bit, 16-bit, 24-bit, or 32-bit) #xx:8/#xx:16/#xx:32 immediate (8-bit, 16-bit, or 32-bit) @(d:8, pc)/@(d:16, pc) program-counter relative (8-bit or 16-bit) @@aa:8 memory indirect the suffixes :8, :16, :24, and :32 may be omitted. in particular, if the :8, :16, :24, or :32 designation is omitted in an absolute address or displacement, the assembler will optimize the length according to the value range. for details, refer to the h8s, h8/300 series cross assembler users manual. note: :2 and :3 in #xx (:2) and #xx (:3) indicate the specifiable bit length. do not include (:2) or (:3) in the assembler notation. example: trapa #3
rev. 3.0, 07/00, page 43 of 320 2.1.2 operation the symbols used in the operation descriptions are defined as follows. rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) mac multiply-accumulate register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement +add C subtract multiply ? divide logical and logical or ? logical exclusive or ? transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ? logical not (logical complement) ( ) < > contents of effective address of the operand :8/:16/ :24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h and r0l to r7l), 16-bit registers (r0 to r7 and e0 to e7), and 32-bit registers (er0 to er7).
rev. 3.0, 07/00, page 44 of 320 2.1.3 condition code the symbols used in the condition-code description are defined as follows. symbol meaning ? changes according to the result of instruction execution * undetermined (no guaranteed value) 0 always cleared to 0 1 always set to 1 not affected by execution of the instruction d varies depending on conditions; see the notes for details on changes of the condition code, see section 2.8, condition code modification. 2.1.4 instruction format the symbols used in the instruction format descriptions are listed below. symbol meaning imm immediate data (2, 3, 8, 16, or 32 bits) abs absolute address (8, 16, 24, or 32 bits) disp displacement (8, 16, or 32 bits) rs, rd, rn register field (4 bits). the symbols rs, rd, and rn correspond to operand symbols rs, rd, and rn. ers, erd, ern register field (3 bits). the symbols ers, erd, and ern correspond to operand symbols ers, erd, and ern.
rev. 3.0, 07/00, page 45 of 320 2.1.5 register specification address register specification: when a general register is used as an address register [@ern, @(d:16, ern), @(d:32, ern), @ern+, or @Cern], the register is specified by a 3-bit register field (ers or erd). data register specification: a general register can be used as a 32-bit, 16-bit, or 8-bit data register. when used as a 32-bit register, it is specified by a 3-bit register field (ers, erd, or ern). when used as a 16-bit register, it is specified by a 4-bit register field (rs, rd, or rn). the lower 3 bits specify the register number. the upper bit is set to 1 to specify an extended register (en) or cleared to 0 to specify a general register (rn). when used as an 8-bit register, it is specified by a 4-bit register field (rs, rd, or rn). the lower 3 bits specify the register number. the upper bit is set to 1 to specify a low register (rnl) or cleared to 0 to specify a high register (rnh). this is shown next. address register 32-bit register 16-bit register 8-bit register register field general register register field general register register field general register 000 001 . . 111 er0 er1 er7 0000 0001 0111 1000 1001 1111 r0 r1 r7 e0 e1 e7 0000 0001 0111 1000 1001 1111 r0h r1h r7h r0l r1l r7l
rev. 3.0, 07/00, page 46 of 320 2.1.6 bit data access in bit manipulation instructions bit data is accessed as the n-th bit (n = 0, 1, 2, 3, , 7) of a byte operand in a general register or memory. the bit number is given by 3-bit immediate data, or by the lower 3 bits of a general register value. example 1: to set bit 3 in r2h to 1 bset r1l, r2h r1l 011 dont care 001 r2h 1 0 1 1 0 bit number set to 1 example 2: to load bit 5 at address h'ffff02 into the bit accumulator bld #5, @h'ffff02 h'ffff02 110 0 0 1 0 1 #5 load c the operand size and addressing mode are as indicated for register or memory operand data.
rev. 3.0, 07/00, page 47 of 320 2.2 instruction descriptions the instructions are described starting in section 2.2.1.
rev. 3.0, 07/00, page 48 of 320 2.2.1 (1) add (b) add (add binary) add binary operation rd + (eas) ? rd assembly-language format add.b , rd operand size byte condition code i ? ? ? ? ? ? ? ? uihunzvc h: set to 1 if there is a carry at bit 3; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a carry at bit 7; otherwise cleared to 0. description this instruction adds the source operand to the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate add.b #xx:8, rd 8 rd imm 1 register direct add.b rs, rd 0 8 rs rd 1 notes
rev. 3.0, 07/00, page 49 of 320 2.2.1 (2) add (w) add (add binary) add binary operation rd + (eas) ? rd assembly-language format add.w < eas>, rd operand size word condition code i ? ? ? ? ? ? ? ? uihunzvc h: set to 1 if there is a carry at bit 11; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a carry at bit 15; otherwise cleared to 0. description this instruction adds the source operand to the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate add.w #xx:16, rd 7 9 1 rd imm 2 register direct add.w rs, rd 0 9 rs rd 1 notes
rev. 3.0, 07/00, page 50 of 320 2.2.1 (3) add (l) add (add binary) add binary operation erd + (eas) ? erd assembly-language format add.l < eas>, erd operand size longword condition code i ? ? ? ? ? ? ? ? uihunzvc h: set to 1 if there is a carry at bit 27; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a carry at bit 31; otherwise cleared to 0. description this instruction adds the source operand to the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte no. of states immediate add.l #xx:32, erd 7 a 1 0 erd imm 3 register direct add.l ers, erd 0 a 1 ers 0 erd 1 notes
rev. 3.0, 07/00, page 51 of 320 2.2.2 adds adds (add with sign extension) add binary address data operation rd + 1 ? erd rd + 2 ? erd rd + 4 ? erd assembly-language format adds #1, erd adds #2, erd adds #4, erd operand size longword condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction adds the immediate value 1, 2, or 4 to the contents of a 32-bit register erd (destination operand). unlike the add instruction, it does not affect the condition code flags. available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct adds #1, erd 0 b 0 0 erd 1 register direct adds #2, erd 0 b 8 0 erd 1 register direct adds #4, erd 0 b 9 0 erd 1 notes
rev. 3.0, 07/00, page 52 of 320 2.2.3 addx addx (add with extend carry) add with carry operation rd + (eas) + c ? rd assembly-language format addx < eas>, rd operand size byte condition code i ? ? ? ? ? ? ? ? uihunzvc h: set to 1 if there is a carry at bit 3; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a carry at bit 7; otherwise cleared to 0. description this instruction adds the source operand and carry flag to the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate addx #xx:8, rd 9 rd imm 1 register direct addx rs, rd 0 e rs rd 1 notes
rev. 3.0, 07/00, page 53 of 320 2.2.4 (1) and (b) and (and logical) logical and operation rd (eas) ? rd assembly-language format and.b < eas>, rd operand size byte condition code i ? ? ? ? ? ?0? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction ands the source operand with the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate and.b #xx:8, rd e rd imm 1 register direct and.b rs, rd 1 6 rs rd 1 notes
rev. 3.0, 07/00, page 54 of 320 2.2.4 (2) and (w) and (and logical) logical and operation rd (eas) ? rd assembly-language format and.w < eas>, rd operand size word condition code i ? ? ? ? ? ?0? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction ands the source operand with the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate and.w #xx:16, rd 7 9 6 rd imm 2 register direct and.w rs, rd 6 6 rs rd 1 notes
rev. 3.0, 07/00, page 55 of 320 2.2.4 (3) and (l) and (and logical) logical and operation erd (eas) ? erd assembly-language format and.l < eas>, erd operand size longword condition code i ? ? ? ? ? ?0? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction ands the source operand with the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte no. of states immediate and.l #xx:32, erd 7 a 6 0 erd imm 3 register direct and.l ers, erd 0 1 f 0 6 6 0 ers 0 erd 2 notes
rev. 3.0, 07/00, page 56 of 320 2.2.5 (1) andc andc (and control register) logical and with ccr operation ccr #imm ? ccr assembly-language format andc #xx:8, ccr operand size byte condition code i ? ? ? ? ? ? ? ? uihunzvc i: stores the corresponding bit of the result. ui: stores the corresponding bit of the result. h: stores the corresponding bit of the result. u: stores the corresponding bit of the result. n: stores the corresponding bit of the result. z: stores the corresponding bit of the result. v: stores the corresponding bit of the result. c: stores the corresponding bit of the result. description this instruction ands the contents of the condition-code register (ccr) with immediate data and stores the result in the condition-code register. no interrupt requests, including nmi, are accepted immediately after execution of this instruction. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate andc #xx:8, ccr 0 6 imm 1 notes
rev. 3.0, 07/00, page 57 of 320 2.2.5 (2) andc andc (and control register) logical and with exr operation exr #imm ? exr assembly-language format andc #xx:8, exr operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction ands the contents of the extended control register (exr) with immediate data and stores the result in the extended control register. no interrupt requests, including nmi, are accepted for three states after execution of this instruction. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate andc#xx:8, exr014106 imm 2 notes
rev. 3.0, 07/00, page 58 of 320 2.2.6 band band (bit and) bit logical and operation c ( of ) ? c assembly-language format band #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: stores the result of the operation. description this instruction ands a specified bit in the destination operand with the carry flag and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. c c 70 specified by #xx:3 bit no. available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 59 of 320 band (bit and) bit logical and operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register band #xx:3, rd 7 6 0 imm rd 1 direct register band #xx:3, @erd 7 c 0 erd 0 7 6 0 imm 03 indirect absolute band #xx:3, @aa:8 7 e abs 7 6 0 imm 03 address absolute band #xx:3, @aa:16 6 a 1 0 abs 7 6 0 imm 04 address absolute band #xx:3, @aa:32 6 a 3 0 abs 7 6 0 imm 05 address
rev. 3.0, 07/00, page 60 of 320 2.2.7 bcc bcc (branch conditionally) conditional branch operation if condition is true, then pc + disp ? pc else next; assembly-language format bcc disp condition field operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description if the condition specified in the condition field (cc) is true, a displacement is added to the program counter (pc) and execution branches to the resulting address. if the condition is false, the next instruction is executed. the pc value used in the address calculation is the starting address of the instruction immediately following the bcc instruction. the displacement is a signed 8-bit or 16-bit value. the branch destination address can be located in the range from C126 to +128 bytes or C 32766 to +32768 bytes from the bcc instruction. mnemonic meaning cc condition signed/unsigned * bra (bt) always (true) 0000 true brn (bf) never (false) 0001 false bhi high 0010 c z = 0 x > y (unsigned) bls low or same 0011 c z = 1 x y (unsigned) bcc (bhs) carry clear (high or same) 0100 c = 0 x 3 y (unsigned) bcs (blo) carry set (low) 0101 c = 1 x < y (unsigned) bne not equal 0110 z = 0 x 1 y (unsigned or signed) beq equal 0111 z = 1 x = y (unsigned or signed) bvc overflow clear 1000 v = 0 bvs overflow set 1001 v = 1 bpl plus 1010 n = 0 bmi minus 1011 n = 1 bge greater or equal 1100 n ? v = 0 x 3 y (signed) blt less than 1101 n ? v = 1 x < y (signed) bgt greater than 1110 z (n ? v) = 0 x > y (signed) ble less or equal 1111 z (n ? v) = 1 x y (signed) note: * if the immediately preceding instruction is a cmp instruction, x is the general register contents (destination operand) and y is the source operand.
rev. 3.0, 07/00, page 61 of 320 bcc (branch conditionally) conditional branch operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states d:8 4 0 disp 2 program-counter relative bra (bt) d:16 5800 disp 3 d:8 4 1 disp 2 program-counter relative brn (bf) d:16 5810 disp 3 d:8 4 2 disp 2 program-counter relative bhi d:16 5820 disp 3 d:8 4 3 disp 2 program-counter relative bls d:16 5830 disp 3 d:8 4 4 disp 2 program-counter relative bcc (bhs) d:16 5840 disp 3 d:8 4 5 disp 2 program-counter relative bcs (blo) d:16 5850 disp 3 d:8 4 6 disp 2 program-counter relative bne d:16 5860 disp 3 d:8 4 7 disp 2 program-counter relative beq d:16 5870 disp 3 d:8 4 8 disp 2 program-counter relative bvc d:16 5880 disp 3 d:8 4 9 disp 2 program-counter relative bvs d:16 5890 disp 3 d:8 4 a disp 2 program-counter relative bpl d:16 5 8 a 0 disp 3 d:8 4 b disp 2 program-counter relative bmi d:16 5 8 b 0 disp 3 d:8 4 c disp 2 program-counter relative bge d:16 5 8 c 0 disp 3 d:8 4 d disp 2 program-counter relative blt d:16 5 8 d 0 disp 3 d:8 4 e disp 2 program-counter relative bgt d:16 5 8 e 0 disp 3 d:8 4 f disp 2 program-counter relative ble d:16 5 8 f 0 disp 3 notes 1. the branch destination address must be even. 2. in machine language bra, brn, bcc, and bcs are identical to bt, bf, bhs, and blo, respectively.
rev. 3.0, 07/00, page 62 of 320 2.2.8 bclr bclr (bit clear) bit clear operation 0 ? ( of ) assembly-language format bclr #xx:3, bclr rn, operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction clears a specified bit in the destination operand to 0. the bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit register rn. the specified bit is not tested. the condition-code flags are not altered. 70 specified by #xx:3 or rn bit no. 0 available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7 rn: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 63 of 320 bclr (bit clear) bit clear operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bclr #xx:3, rd 7 2 0 imm rd 1 direct register bclr #xx:3, @erd 7 d 0 erd 0 7 2 0 imm 04 indirect absolute bclr #xx:3, @aa:8 7 f abs 7 2 0 imm 04 address absolute bclr #xx:3, @aa:16 6 a 1 8 abs 7 2 0 imm 05 address absolute bclr #xx:3, @aa:32 6 a 3 8 abs 7 2 0 imm 06 address register bclr rn, rd 6 2 rn rd 1 direct register bclr rn, @erd 7 d 0 erd 0 6 2 rn 0 4 indirect absolute bclr rn, @aa:8 7 f abs 6 2 rn 0 4 address absolute bclr rn, @aa:16 6 a 1 8 abs 6 2 rn 0 5 address absolute bclr rn, @aa:32 6 a 3 8 abs 6 2 rn 0 6 address
rev. 3.0, 07/00, page 64 of 320 2.2.9 biand biand (bit invert and) bit logical and operation c [ ? ( of )] ? c assembly-language format biand #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: stores the result of the operation. description this instruction ands the inverse of a specified bit in the destination operand with the carry flag and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. c c 70 specified by #xx:3 bit no. invert available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 65 of 320 biand (bit invert and) bit logical and operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register biand #xx:3, rd 7 6 1 imm rd 1 direct register biand #xx:3, @erd 7 c 0 erd 0 7 6 1 imm 03 indirect absolute biand #xx:3, @aa:8 7 e abs 7 6 1 imm 03 address absolute biand #xx:3, @aa:16 6 a 1 0 abs 7 6 1 imm 04 address absolute biand #xx:3, @aa:32 6 a 3 0 abs 7 6 1 imm 05 address
rev. 3.0, 07/00, page 66 of 320 2.2.10 bild bild (bit invert load) bit load operation ? ( of ) ? c assembly-language format bild #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: loaded with the inverse of the specified bit. description this instruction loads the inverse of a specified bit from the destination operand into the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. c 70 specified by #xx:3 bit no. invert available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 67 of 320 bild (bit invert load) bit load operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bild #xx:3, rd 7 7 1 imm rd 1 direct register bild #xx:3, @erd 7 c 0 erd 0 7 7 1 imm 03 indirect absolute bild #xx:3, @aa:8 7 e abs 7 7 1 imm 03 address absolute bild #xx:3, @aa:16 6 a 1 0 abs 7 7 1 imm 04 address absolute bild #xx:3, @aa:32 6 a 3 0 abs 7 7 1 imm 05 address
rev. 3.0, 07/00, page 68 of 320 2.2.11 bior bior (bit invert inclusive or) bit logical or operation c [ ? ( of )] ? c assembly-language format bior #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: stores the result of the operation. description this instruction ors the inverse of a specified bit in the destination operand with the carry flag and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. c c 70 specified by #xx:3 bit no. invert available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 69 of 320 bior (bit invert inclusive or) bit logical or operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bior #xx:3, rd 7 4 1 imm rd 1 direct register bior #xx:3, @erd 7 c 0 erd 0 7 4 1 imm 03 indirect absolute bior #xx:3, @aa:8 7 e abs 7 4 1 imm 03 address absolute bior #xx:3, @aa:16 6 a 1 0 abs 7 4 1 imm 04 address absolute bior #xx:3, @aa:32 6 a 3 0 abs 7 4 1 imm 05 address
rev. 3.0, 07/00, page 70 of 320 2.2.12 bist bist (bit invert store) bit store operation ? c ? ( of ) assembly-language format bist #xx:3, operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction stores the inverse of the carry flag in a specified bit location in the destination operand. the bit number is specified by 3-bit immediate data. other bits in the destination operand remain unchanged. c 70 specified by #xx:3 bit no. invert available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 71 of 320 bist (bit invert store) bit store operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bist #xx:3, rd 6 7 1 imm rd 1 direct register bist #xx:3, @erd 7 d 0 erd 0 6 7 1 imm 04 indirect absolute bist #xx:3, @aa:8 7 f abs 6 7 1 imm 04 address absolute bist #xx:3, @aa:16 6 a 1 8 abs 6 7 1 imm 05 address absolute bist #xx:3, @aa:32 6 a 3 8 abs 6 7 1 imm 06 address
rev. 3.0, 07/00, page 72 of 320 2.2.13 bixor bixor (bit invert exclusive or) bit exclusive logical or operation c ? [ ? ( of )] ? c assembly-language format bixor #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: stores the result of the operation. description this instruction exclusively ors the inverse of a specified bit in the destination operand with the carry flag and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. specified by #xx:3 ? invert c 0 7 c bit no. available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 73 of 320 bixor (bit invert exclusive or) bit exclusive logical or operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bixor #xx:3, rd 7 5 1 imm rd 1 direct register bixor #xx:3, @erd 7 c 0 erd 0 7 5 1 imm 03 indirect absolute bixor #xx:3, @aa:8 7 e abs 7 5 1 imm 03 address absolute bixor #xx:3, @aa:16 6 a 1 0 abs 7 5 1 imm 04 address absolute bixor #xx:3, @aa:32 6 a 3 0 abs 7 5 1 imm 05 address
rev. 3.0, 07/00, page 74 of 320 2.2.14 bld bld (bit load) bit load operation ( of ) ? c assembly-language format bld #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: loaded from the specified bit. description this instruction loads a specified bit from the destination operand into the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. specified by #xx:3 c 0 7 bit no. available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 75 of 320 bld (bit load) bit load operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bld #xx:3, rd 7 7 0 imm rd 1 direct register bld #xx:3, @erd 7 c 0 erd 0 7 7 0 imm 03 indirect absolute bld #xx:3, @aa:8 7 e abs 7 7 0 imm 03 address absolute bld #xx:3, @aa:16 6 a 1 0 abs 7 7 0 imm 04 address absolute bld #xx:3, @aa:32 6 a 3 0 abs 7 7 0 imm 05 address
rev. 3.0, 07/00, page 76 of 320 2.2.15 bnot bnot (bit not) bit not operation ? ( of ) ? (bit no. of ) assembly-language format bnot #xx:3, bnot rn, operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction inverts a specified bit in the destination operand. the bit number is specified by 3- bit immediate data or by the lower 3 bits of an 8-bit register rn. the specified bit is not tested. the condition code remains unchanged. 70 bit no. specified by #xx:3 or rn invert available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7 rn: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 77 of 320 bnot (bit not) bit not operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bnot #xx:3, rd 7 1 0 imm rd 1 direct register bnot #xx:3, @erd 7 d 0 erd 0 7 1 0 imm 04 indirect absolute bnot #xx:3, @aa:8 7 f abs 7 1 0 imm 04 address absolute bnot #xx:3, @aa:16 6 a 1 8 abs 7 1 0 imm 05 address absolute bnot #xx:3, @aa:32 6 a 3 8 abs 7 1 0 imm 06 address register bnot rn, rd 6 1 rn rd 1 direct register bnot rn, @erd 7 d 0 erd 0 6 1 rn 0 4 indirect absolute bnot rn, @aa:8 7 f abs 6 1 rn 0 4 address absolute bnot rn, @aa:16 6 a 1 8 abs 6 1 rn 0 5 address absolute bnot rn, @aa:32 6 a 3 8 abs 6 1 rn 0 6 address
rev. 3.0, 07/00, page 78 of 320 2.2.16 bor bor (bit inclusive or) bit logical or operation c ( of ) ? c assembly-language format bor #xx:3, operand size byte condition code i ? ? ? ? ? ? ?? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: stores the result of the operation. description this instruction ors a specified bit in the destination operand with the carry flag and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. cc 70 specified by #xx:3 bit no. available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 79 of 320 bor (bit inclusive or) bit logical or operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bor #xx:3, rd 7 4 0 imm rd 1 direct register bor #xx:3, @erd 7 c 0 erd 0 7 4 0 imm 03 indirect absolute bor #xx:3, @aa:8 7 e abs 7 4 0 imm 03 address absolute bor #xx:3, @aa:16 6 a 1 0 abs 7 4 0 imm 04 address absolute bor #xx:3, @aa:32 6 a 3 0 abs 7 4 0 imm 05 address
rev. 3.0, 07/00, page 80 of 320 2.2.17 bset bset (bit set) bit set operation 1 ? ( of ) assembly-language format bset #xx:3, bset rn, operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction sets a specified bit in the destination operand to 1. the bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit register rn. the specified bit is not tested. the condition code flags are not altered. 70 bit no. 1 specified by #xx:3 or rn available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7 rn: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 81 of 320 bset (bit set) bit set operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bset #xx:3, rd 7 0 0 imm rd 1 direct register bset #xx:3, @erd 7 d 0 erd 0 7 0 0 imm 04 indirect absolute bset #xx:3, @aa:8 7 f abs 7 0 0 imm 04 address absolute bset #xx:3, @aa:16 6 a 1 8 abs 7 0 0 imm 05 address absolute bset #xx:3, @aa:32 6 a 3 8 abs 7 0 0 imm 06 address register bset rn, rd 6 0 rn rd 1 direct register bset rn, @erd 7 d 0 erd 0 6 0 rn 0 4 indirect absolute bset rn, @aa:8 7 f abs 6 0 rn 0 4 address absolute bset rn, @aa:16 6 a 1 8 abs 6 0 rn 0 5 address absolute bset rn, @aa:32 6 a 3 8 abs 6 0 rn 0 6 address
rev. 3.0, 07/00, page 82 of 320 2.2.18 bsr bsr (branch to subroutine) branch to subroutine operation pc ? @Csp pc + disp ? pc assembly-language format bsr disp operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction branches to a subroutine at a specified address. it pushes the program counter (pc) value onto the stack as a restart address, then adds a specified displacement to the pc value and branches to the resulting address. the pc value pushed onto the stack is the address of the instruction following the bsr instruction. the displacement is a signed 8-bit or 16-bit value, so the possible branching range is C126 to +128 bytes or C32766 to +32768 bytes from the address of the bsr instruction. operand format and number of states required for execution instruction format no. of states addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte normal advanced d:8 5 5 disp 3 4 program-counter relative bsr d:16 5 c 0 0 disp 4 5
rev. 3.0, 07/00, page 83 of 320 bsr (branch to subroutine) branch to subroutine notes the stack structure differs between normal mode and advanced mode. in normal mode only the lower 16 bits of the program counter are pushed onto the stack. ensure that the branch destination address is even. pc 23 16 15 8 7 0 normal mode pc 23 16 15 8 7 0 advanced mode reserved
rev. 3.0, 07/00, page 84 of 320 2.2.19 bst bst (bit store) bit store operation c ? ( of ) assembly-language format bst #xx:3, operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction stores the carry flag in a specified bit location in the destination operand. the bit number is specified by 3-bit immediate data. c 70 specified by #xx:3 bit no. available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 85 of 320 bst (bit store) bit store operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bst #xx:3, rd 6 7 0 imm rd 1 direct register bst #xx:3, @erd 7 d 0 erd 0 6 7 0 imm 04 indirect absolute bst #xx:3, @aa:8 7 f abs 6 7 0 imm 04 address absolute bst #xx:3, @aa:16 6 a 1 8 abs 6 7 0 imm 05 address absolute bst #xx:3, @aa:32 6 a 3 8 abs 6 7 0 imm 06 address
rev. 3.0, 07/00, page 86 of 320 2.2.20 btst btst (bit test) bit test operation ? ( of ) ? z assembly-language format btst #xx:3, btst rn, operand size byte condition code i ? ? ? ? ? ??? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: set to 1 if the specified bit is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction tests a specified bit in the destination operand and sets or clears the zero flag according to the result. the bit number can be specified by 3-bit immediate data, or by the lower three bits of an 8-bit register rn. the destination operand contents remain unchanged. 70 bit no. test specified by #xx:3 or rn available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7 rn: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 87 of 320 btst (bit test) bit test operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register btst #xx:3, rd 7 3 0 imm rd 1 direct register btst #xx:3, @erd 7 c 0 erd 0 7 3 0 imm 03 indirect absolute btst #xx:3, @aa:8 7 e abs 7 3 0 imm 03 address absolute btst #xx:3, @aa:16 6 a 1 0 abs 7 3 0 imm 04 address absolute btst #xx:3, @aa:32 6 a 3 0 abs 7 3 0 imm 05 address register btst rn, rd 6 3 rn rd 1 direct register btst rn, @erd 7 c 0 erd 0 6 3 rn 0 3 indirect absolute btst rn, @aa:8 7 e abs 6 3 rn 0 3 address absolute btst rn, @aa:16 6 a 1 0 abs 6 3 rn 0 4 address absolute btst rn, @aa:32 6 a 3 0 abs 6 3 rn 0 5 address
rev. 3.0, 07/00, page 88 of 320 2.2.21 bxor bxor (bit exclusive or) bit exclusive logical or operation c ? ( of ) ? c assembly-language format bxor #xx:3, operand size byte condition code i ? uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: stores the result of the operation. description this instruction exclusively ors a specified bit in the destination operand with the carry flag and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. the destination operand contents remain unchanged. cc 70 specified by #xx:3 bit no. ? available registers rd: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 89 of 320 bxor (bit exclusive or) bit exclusive logical or operand format and number of states required for execution note: * the addressing mode is the addressing mode of the destination operand . notes for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode * 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states register bxor #xx:3, rd 7 5 0 imm rd 1 direct register bxor #xx:3, @erd 7 c 0 erd 0 7 5 0 imm 03 indirect absolute bxor #xx:3, @aa:8 7 e abs 7 5 0 imm 03 address absolute bxor #xx:3, @aa:16 6 a 1 0 abs 7 5 0 imm 04 address absolute bxor #xx:3, @aa:32 6 a 3 0 abs 7 5 0 imm 05 address
rev. 3.0, 07/00, page 90 of 320 2.2.22 clrmac clrmac (clear mac register) initialize multiply-accumulate register operation 0 ? mach, macl assembly-language format clrmac operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction simultaneously clears registers mach and macl. it is supported only by the h8s/2600 cpu. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states clrmac01a0 2 * note: * a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes execution of this instruction also clears the overflow flag in the multiplier to 0.
rev. 3.0, 07/00, page 91 of 320 2.2.23 (1) cmp (b) cmp (compare) compare operation rd C (eas), set/clear ccr assembly-language format cmp.b < eas>, rd operand size byte condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 3; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 7; otherwise cleared to 0. description this instruction subtracts the source operand from the contents of an 8-bit register rd (destination operand) and sets or clears the condition code bits according to the result. the contents of the 8-bit register rd remain unchanged. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate cmp.b #xx:8, rd a rd imm 1 register direct cmp.b rs, rd 1 c rs rd 1 notes
rev. 3.0, 07/00, page 92 of 320 2.2.23 (2) cmp (w) cmp (compare) compare operation rd C (eas), set/clear ccr assembly-language format cmp.w < eas>, rd operand size word condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 11; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 15; otherwise cleared to 0. description this instruction subtracts the source operand from the contents of a 16-bit register rd (destination operand) and sets or clears the condition code bits according to the result. the contents of the 16- bit register rd remain unchanged. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate cmp.w #xx:16, rd 7 9 2 rd imm 2 register direct cmp.w rs, rd 1 d rs rd 1 notes
rev. 3.0, 07/00, page 93 of 320 2.2.23 (3) cmp (l) cmp (compare) compare operation erd C (eas), set/clear ccr assembly-language format cmp.l < eas>, erd operand size longword condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 27; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 31; otherwise cleared to 0. description this instruction subtracts the source operand from the contents of a 32-bit register erd (destination operand) and sets or clears the condition code bits according to the result. the contents of the 32-bit register erd remain unchanged. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte no. of states immediate cmp.l #xx:32, erd 7 a 2 0 erd imm 3 register direct cmp.l ers, erd 1 f 1 ers 0 erd 1 notes
rev. 3.0, 07/00, page 94 of 320 2.2.24 daa daa (decimal adjust add) decimal adjust operation rd (decimal adjust) ? rd assembly-language format daa rd operand size byte condition code i ? ? ? * * uihunzvc h: undetermined (no guaranteed value). n: set to 1 if the adjusted result is negative; otherwise cleared to 0. z: set to 1 if the adjusted result is zero; otherwise cleared to 0. v: undetermined (no guaranteed value). c: set to 1 if there is a carry at bit 7; otherwise left unchanged. description given that the result of an addition operation performed by an add.b or addx instruction on 4-bit bcd data is contained in an 8-bit register rd and the carry and half-carry flags, the daa instruction adjusts the contents of the 8-bit register rd (destination operand) by adding h'00, h'06, h'60, or h'66 according to the table below. c flag before adjustment upper 4 bits before adjustment h flag before adjustment lower 4 bits before adjustment value added (hexadecimal) c flag after adjustment 0 0 to 9 0 0 to 9 00 0 0 0 to 8 0 a to f 06 0 0 0 to 9 1 0 to 3 06 0 0 a to f 0 0 to 9 60 1 0 9 to f 0 a to f 66 1 0 a to f 1 0 to 3 66 1 1 1 to 2 0 0 to 9 60 1 1 1 to 2 0 a to f 66 1 1 1 to 3 1 0 to 3 66 1
rev. 3.0, 07/00, page 95 of 320 daa (decimal adjust add) decimal adjust available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct daa rd 0 f 0 rd 1 notes valid results (8-bit register rd contents and c, v, z, n, and h flags) are not assured if this instruction is executed under conditions other than those described above.
rev. 3.0, 07/00, page 96 of 320 2.2.25 das das (decimal adjust subtract) decimal adjust operation rd (decimal adjust) ? rd assembly-language format das rd operand size byte condition code i ? ? * *0 uihunzvc h: undetermined (no guaranteed value). n: set to 1 if the adjusted result is negative; otherwise cleared to 0. z: set to 1 if the adjusted result is zero; otherwise cleared to 0. v: undetermined (no guaranteed value). c: previous value remains unchanged. description given that the result of a subtraction operation performed by a sub.b, subx.b, or neg.b instruction on 4-bit bcd data is contained in an 8-bit register rd and the carry and half-carry flags, the das instruction adjusts the contents of the 8-bit register rd (destination operand) by adding h'00, h'fa, h'a0, or h'9a according to the table below. c flag before adjustment upper 4 bits before adjustment h flag before adjustment lower 4 bits before adjustment value added (hexadecimal) c flag after adjustment 0 0 to 9 0 0 to 9 00 0 0 0 to 8 1 6 to f fa 0 1 7 to f 0 0 to 9 a0 1 1 6 to f 1 6 to f 9a 1 available registers rd: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 97 of 320 das (decimal adjust subtract) decimal adjust operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct das rd 1 f 0 rd 1 notes valid results (8-bit register rd contents and c, v, z, n, and h flags) are not assured if this instruction is executed under conditions other than those described above.
rev. 3.0, 07/00, page 98 of 320 2.2.26 (1) dec (b) dec (decrement) decrement operation rd C 1 ? rd assembly-language format dec.b rd operand size byte condition code i ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: previous value remains unchanged. description this instruction decrements an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct dec.b rd 1 a 0 rd 1 notes an overflow is caused by the operation h'80 C 1 ? h'7f.
rev. 3.0, 07/00, page 99 of 320 2.2.26 (2) dec (w) dec (decrement) decrement operation rd C 1 ? rd rd C 2 ? rd assembly-language format dec.w #1, rd dec.w #2, rd operand size word condition code i ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: previous value remains unchanged. description this instruction subtracts the immediate value 1 or 2 from the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct dec.w #1, rd 1 b 5 rd 1 register direct dec.w #2, rd 1 b d rd 1 notes an overflow is caused by the operations h'8000 C 1 ? h'7fff, h'8000 C 2 ? h'7ffe, and h'8001 C 2 ? h'7fff.
rev. 3.0, 07/00, page 100 of 320 2.2.26 (3) dec (l) dec (decrement) decrement operation erd C 1 ? erd erd C 2 ? erd assembly-language format dec.l #1, erd dec.l #2, erd operand size longword condition code i ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: previous value remains unchanged. description this instruction subtracts the immediate value 1 or 2 from the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct dec.l #1, erd 1 b 7 0 erd 1 register direct dec.l #2, erd 1 b f 0 erd 1 notes an overflow is caused by the operations h'80000000 C 1 ? h'7fffffff, h'80000000 C 2 ? h'7ffffffe, and h'80000001 C 2 ? h'7fffffff.
rev. 3.0, 07/00, page 101 of 320 2.2.27 (1) divxs (b) divxs (divide extend as signed) divide signed operation rd ? rs ? rd assembly-language format divxs.b rs, rd operand size byte condition code i ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the quotient is negative; otherwise cleared to 0. z: set to 1 if the divisor is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction divides the contents of a 16-bit register rd (destination operand) by the contents of an 8-bit register rs (source operand) and stores the result in the 16-bit register rd. the division is signed. the operation performed is 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder. the quotient is placed in the lower 8 bits of rd. the remainder is placed in the upper 8 bits of rd. the sign of the remainder matches the sign of the dividend. rd rs rd dividend ? divisor ? remainder quotient 16 bits 8 bits 8 bits 8 bits valid results are not assured if division by zero is attempted or an overflow occurs. available registers rd: r0 to r7, e0 to e7 rs: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 102 of 320 divxs (divide extend as signed) divide signed operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct divxs.b rs, rd 0 1 d 0 5 1 rs rd 13 notes the n flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. the n flag may therefore be set to 1 when the quotient is zero.
rev. 3.0, 07/00, page 103 of 320 2.2.27 (2) divxs (w) divxs (divide extend as signed) divide signed operation erd ? rs ? erd assembly-language format divxs.w rs, erd operand size word condition code i ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the quotient is negative; otherwise cleared to 0. z: set to 1 if the divisor is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction divides the contents of a 32-bit register erd (destination operand) by the contents of a 16-bit register rs (source operand) and stores the result in the 32-bit register erd. the division is signed. the operation performed is 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. the quotient is placed in the lower 16 bits (rd) of the 32-bit register erd. the remainder is placed in the upper 16 bits (ed). the sign of the remainder matches the sign of the dividend. erd rs erd dividend ? divisor ? remainder quotient 32 bits 16 bits 16 bits 16 bits valid results are not assured if division by zero is attempted or an overflow occurs. available registers erd: er0 to er7 rs: r0 to r7, e0 to e7
rev. 3.0, 07/00, page 104 of 320 divxs (divide extend as signed) divide signed operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct divxs.w rs, erd 0 1 d 0 5 3 rs 0 erd 21 notes the n flag is set to 1 if the dividend and divisor have different signs, and cleared to 0 if they have the same sign. the n flag may therefore be set to 1 when the quotient is zero.
rev. 3.0, 07/00, page 105 of 320 2.2.28 (1) divxu (b) divxu (divide extend as unsigned) divide operation rd ? rs ? rd assembly-language format divxu.b rs, rd operand size byte condition code i ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the divisor is negative; otherwise cleared to 0. z: set to 1 if the divisor is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction divides the contents of a 16-bit register rd (destination operand) by the contents of an 8-bit register rs (source operand) and stores the result in the 16-bit register rd. the division is unsigned. the operation performed is 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder. the quotient is placed in the lower 8 bits of rd. the remainder is placed in the upper 8 bits of rd. rd rs rd dividend ? divisor ? remainder quotient 16 bits 8 bits 8 bits 8 bits valid results are not assured if division by zero is attempted or an overflow occurs. available registers rd: r0 to r7, e0 to e7 rs: r0l to r7l, r0h to r7h
rev. 3.0, 07/00, page 106 of 320 divxu (divide extend as unsigned) divide operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct divxu.b rs, rd 5 1 rs rd 12 notes
rev. 3.0, 07/00, page 107 of 320 2.2.28 (2) divxu (w) divxu (divide extend as unsigned) divide operation erd ? rs ? erd assembly-language format divxu.w rs, erd operand size word condition code i ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the divisor is negative; otherwise cleared to 0. z: set to 1 if the divisor is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction divides the contents of a 32-bit register erd (destination operand) by the contents of a 16-bit register rs (source register) and stores the result in the 32-bit register erd. the division is unsigned. the operation performed is 32 bits ? 16 bits ? 16-bit quotient and 16-bit remainder. the quotient is placed in the lower 16 bits (rd) of the 32-bit register erd. the remainder is placed in the upper 16 bits of (ed). erd rs erd dividend ? divisor ? remainder quotient 32 bits 16 bits 16 bits 16 bits valid results are not assured if division by zero is attempted or an overflow occurs. available registers erd: er0 to er7 rs: r0 to r7, e0 to e7
rev. 3.0, 07/00, page 108 of 320 divxu (divide extend as unsigned) divide operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct divxu.w rs, erd 5 3 rs 0 erd 20 notes
rev. 3.0, 07/00, page 109 of 320 2.2.29 (1) eepmov (b) eepmov (move data to eeprom) block data transfer operation if r4l 1 0 then repeat @er5+ ? @er6+ r4l C 1 ? r4l until r4l = 0 else next; assembly-language format eepmov.b operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction performs a block data transfer. it moves data from the memory location specified in er5 to the memory location specified in er6, increments er5 and er6, decrements r4l, and repeats these operations until r4l reaches zero. execution then proceeds to the next instruction. the data transfer is performed a byte at a time, with r4l indicating the number of bytes to be transferred. the byte symbol in the assembly-language format designates the size of r4l (and limits the maximum number of bytes that can be transferred to 255). no interrupts are detected while the block transfer is in progress. when the eepmov.b instruction ends, r4l contains 0 (zero), and er5 and er6 contain the last transfer address + 1. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states eepmov.b 7b5c598f4 + 2n * note: * n is the initial value of r4l. although n bytes of data are transferred, 2(n + 1) data accesses are performed, requiring 2(n + 1) states. (n = 0, 1, 2, , 255). notes this instruction first reads the memory locations indicated by er5 and er6, then carries out the block data transfer.
rev. 3.0, 07/00, page 110 of 320 2.2.29 (2) eepmov (w) eepmov (move data to eeprom) block data transfer operation if r4 1 0 then repeat @er5+ ? @er6+ r4 C 1 ? r4 until r4 = 0 else next; assembly-language format eepmov.w operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction performs a block data transfer. it moves data from the memory location specified in er5 to the memory location specified in er6, increments er5 and er6, decrements r4, and repeats these operations until r4 reaches zero. execution then proceeds to the next instruction. the data transfer is performed a byte at a time, with r4 indicating the number of bytes to be transferred. the word symbol in the assembly-language format designates the size of r4 (allowing a maximum 65535 bytes to be transferred). all interrupts are detected while the block transfer is in progress. if no interrupt occurs while the eepmov.w instruction is executing, when the eepmov.w instruction ends, r4 contains 0 (zero), and er5 and er6 contain the last transfer address + 1. if an interrupt occurs, interrupt exception handling begins after the current byte has been transferred. r4 indicates the number of bytes remaining to be transferred. er5 and er6 indicate the next transfer addresses. the program counter value pushed onto the stack in interrupt exception handling is the address of the next instruction after the eepmov.w instruction. see the note on eepmov.w instruction and interrupt.
rev. 3.0, 07/00, page 111 of 320 eepmov (move data to eeprom) block data transfer operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states eepmov.w 7bd4598f4 + 2n * note: * n is the initial value of r4. although n bytes of data are transferred, 2(n + 1) data accesses are performed, requiring 2(n + 1) states. (n = 0, 1, 2, , 65535). notes this instruction first reads memory at the addresses indicated by er5 and er6, then carries out the block data transfer. eepmov.w instruction and interrupt if an interrupt request occurs while the eepmov.w instruction is being executed, interrupt exception handling is carried out after the current byte has been transferred. register contents are then as follows: er5: address of the next byte to be transferred er6: destination address of the next byte r4: number of bytes remaining to be transferred the program counter value pushed on the stack in interrupt exception handling is the address of the next instruction after the eepmov.w instruction. programs should be coded as follows to allow for interrupts during execution of the eepmov.w instruction. example: l1: eepmov.w mov.w r4,r4 bne l1 interrupt requests other than nmi are not accepted if they are masked in the cpu. during execution of the eepmov.b instruction no interrupts are accepted, including nmi.
rev. 3.0, 07/00, page 112 of 320 2.2.30 (1) exts (w) exts (extend as signed) sign extension operation ( of rd) ? ( of rd) assembly-language format exts.w rd operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction copies the sign of the lower 8 bits in a 16-bit register rd in the upward direction (copies rd bit 7 to bits 15 to 8) to extend the data to signed word data. dont care rd 8 bits sign bit 8 bits sign extension 8 bits 8 bits 70 bit 15 rd 70 bit 15 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct exts.w rd 1 7 d rd 1 notes
rev. 3.0, 07/00, page 113 of 320 2.2.30 (2) exts (l) exts (extend as signed) sign extension operation ( of erd) ? ( of erd) assembly-language format exts.l erd operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction copies the sign of the lower 16 bits in a 32-bit register erd in the upward direction (copies erd bit 15 to bits 31 to 16) to extend the data to signed longword data. dont care 15 16 bits sign bit 16 bits sign extension 16 bits 16 bits 0 bit 31 erd 15 0 bit 31 erd available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct exts.l erd 1 7 f 0 erd 1 notes
rev. 3.0, 07/00, page 114 of 320 2.2.31 (1) extu (w) extu (extend as unsigned) zero extension operation 0 ? ( of rd) assembly-language format extu.w rd operand size word condition code i ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction extends the lower 8 bits in a 16-bit register rd to word data by padding with zeros. that is, it clears the upper 8 bits of rd (bits 15 to 8) to 0. dont care 8 bits 8 bits zero extension 8 bits 8 bits rd 70 bit 15 rd 70 bit 15 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct extu.w rd 1 7 5 rd 1 notes
rev. 3.0, 07/00, page 115 of 320 2.2.31 (2) extu (l) extu (extend as unsigned) zero extension operation 0 ? ( of erd) assembly-language format extu.l erd operand size longword condition code i ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction extends the lower 16 bits (general register rd) in a 32-bit register erd to longword data by padding with zeros. that is, it clears the upper 16 bits of erd (bits 31 to 16) to 0. dont care 16 bits 16 bits zero extension 16 bits 16 bits 15 0 bit 31 erd 15 0 bit 31 erd available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct extu.l erd 1 7 7 0 erd 1 notes
rev. 3.0, 07/00, page 116 of 320 2.2.32 (1) inc (b) inc (increment) increment operation rd + 1 ? rd assembly-language format inc.b rd operand size byte condition code i ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: previous value remains unchanged. description this instruction increments an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct inc.b rd 0 a 0 rd 1 notes an overflow is caused by the operation h'7f + 1 ? h'80.
rev. 3.0, 07/00, page 117 of 320 2.2.32 (2) inc (w) inc (increment) increment operation rd + 1 ? rd rd + 2 ? rd assembly-language format inc.w #1, rd inc.w #2, rd operand size word condition code i ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: previous value remains unchanged. description this instruction adds the immediate value 1 or 2 to the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct inc.w #1, rd 0 b 5 rd 1 register direct inc.w #2, rd 0 b d rd 1 notes an overflow is caused by the operations h'7fff + 1 ? h'8000, h'7fff + 2 ? h'8001, and h'7ffe + 2 ? h'8000.
rev. 3.0, 07/00, page 118 of 320 2.2.32 (3) inc (l) inc (increment) increment operation erd + 1 ? erd erd + 2 ? erd assembly-language format inc.l #1, erd inc.l #2, erd operand size longword condition code i ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: previous value remains unchanged. description this instruction adds the immediate value 1 or 2 to the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct inc.l #1, erd 0 b 7 0 erd 1 register direct inc.l #2, erd 0 b f 0 erd 1 notes an overflow is caused by the operations h'7fffffff + 1 ? h'80000000, h'7fffffff + 2 ? h'80000001, and h'7ffffffe + 2 ? h'80000000.
rev. 3.0, 07/00, page 119 of 320 2.2.33 jmp jmp (jump) unconditional branch operation effective address ? pc assembly-language format jmp operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction branches unconditionally to a specified effective address. available registers ern: er0 to er7 operand format and number of states required for execution instruction format no. of states addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte normal advanced register indirect jmp @ern 5 9 0 ern 0 2 absolute address jmp @aa:24 5 a abs 3 memory indirect jmp @@aa:8 5 b abs 4 5 notes the structure of the branch address and the number of states required for execution differ between normal mode and advanced mode. ensure that the branch destination address is even.
rev. 3.0, 07/00, page 120 of 320 2.2.34 jsr jsr (jump to subroutine) jump to subroutine operation pc ? @Csp effective address ? pc assembly-language format jsr < ea> operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction pushes the program counter onto the stack as a return address, then branches to a specified effective address. the program counter value pushed onto the stack is the address of the instruction following the jsr instruction. available registers ern: er0 to er7 operand format and number of states required for execution instruction format no. of states addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte normal advanced register indirect jsr @ern 5 d 0 ern 0 3 4 absolute address jsr @aa:24 5 e abs 4 5 memory indirect jsr @@aa:8 5 f abs 4 6
rev. 3.0, 07/00, page 121 of 320 jsr (jump to subroutine) jump to subroutine notes the stack structure differs between normal mode and advanced mode. in normal mode only the lower 16 bits of the program counter are pushed onto the stack. ensure that the branch destination address is even. pc 23 16 15 8 7 0 normal mode pc 23 16 15 8 7 0 advanced mode reserved
rev. 3.0, 07/00, page 122 of 320 2.2.35 (1) ldc (b) ldc (load to control register) load ccr operation ? ccr assembly-language format ldc.b , ccr operand size byte condition code i ? ? ? ? ? ? ? ? uihunzvc i: loaded from the corresponding bit in the source operand. h: loaded from the corresponding bit in the source operand. n: loaded from the corresponding bit in the source operand. z: loaded from the corresponding bit in the source operand. v: loaded from the corresponding bit in the source operand. c: loaded from the corresponding bit in the source operand. description this instruction loads the source operand contents into the condition-code register (ccr). no interrupt requests, including nmi, are accepted immediately after execution of this instruction. available registers rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate ldc.b #xx:8, ccr 0 7 imm 1 register direct ldc.b rs, ccr 0 3 0 rs 1 notes
rev. 3.0, 07/00, page 123 of 320 2.2.35 (2) ldc (b) ldc (load to control register) load exr operation ? exr assembly-language format ldc.b < eas>, exr operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction loads the source operand contents into the extended control register (exr). no interrupt requests, including nmi, are accepted for three states after execution of this instruction. available registers rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate ldc.b#xx:8, exr014107 imm 2 register direct ldc.b rs, exr 0 3 1 rs 1 notes
rev. 3.0, 07/00, page 124 of 320 2.2.35 (3) ldc (w) ldc (load to control register) load ccr operation (eas) ? ccr assembly-language format ldc.w < eas>, ccr operand size word condition code i ? ? ? ? ? ? ? ? uihunzvc i: loaded from the corresponding bit in the source operand. h: loaded from the corresponding bit in the source operand. n: loaded from the corresponding bit in the source operand. z: loaded from the corresponding bit in the source operand. v: loaded from the corresponding bit in the source operand. c: loaded from the corresponding bit in the source operand. description this instruction loads the source operand contents into the condition-code register (ccr). although ccr is a byte register, the source operand is word size. the contents of the even address are loaded into ccr. no interrupt requests, including nmi, are accepted immediately after execution of this instruction. available registers ers: er0 to er7
rev. 3.0, 07/00, page 125 of 320 ldc (load to control register) load ccr operand format and number of states required for execution notes addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte states ldc.w @ers, ccr 0140690ers0 3 ldc.w @(d:16, ers), ccr 01406f0ers0 disp 4 ldc.w @(d:32, ers), ccr 0140780ers06b20 disp 6 ldc.w @ers+, ccr 01406d0ers0 4 ldc.w @aa:16, ccr 01406b00 abs 4 ldc.w @aa:32, ccr 01406b20 abs 5 register indirect register indirect with displace- ment register indirect with post- increment absolute address
rev. 3.0, 07/00, page 126 of 320 2.2.35 (4) ldc (w) ldc (load to control register) load exr operation (eas) ? exr assembly-language format ldc.w < eas>, exr operand size word condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction loads the source operand contents into the extended control register (exr). although exr is a byte register, the source operand is word size. the contents of the even address are loaded into exr. no interrupt requests, including nmi, are accepted for three states after execution of this instruction. available registers ers: er0 to er7
rev. 3.0, 07/00, page 127 of 320 ldc (load to control register) load exr operand format and number of states required for execution notes addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte states ldc.w @ers, exr 0141690ers0 3 ldc.w @(d:16, ers), exr 01416f0ers0 disp 4 ldc.w @(d:32, ers), exr 0141780ers06b20 disp 6 ldc.w @ers+, exr 01416d0ers0 4 ldc.w @aa:16, exr 01416b00 abs 4 ldc.w @aa:32, exr 01416b20 abs 5 register indirect register indirect with displace- ment register indirect with post- increment absolute address
rev. 3.0, 07/00, page 128 of 320 2.2.36 ldm ldm (load to multiple registers) restore data from stack operation @sp+ ? ern (register list) assembly-language format ldm.l @sp+, operand size longword condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction restores data saved on the stack to a specified list of registers. registers are restored in descending order of register number. two, three, or four registers can be restored by one ldm instruction. the following ranges can be specified in the register list. two registers: er0-er1, er2-er3, er4-er5, or er6-er7 three registers: er0-er2 or er4-er6 four registers: er0-er3 or er4-er7 available registers ern: er0 to er7
rev. 3.0, 07/00, page 129 of 320 ldm (load to multiple registers) restore data from stack operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states ldm.l @sp+, (ernCern+1) 01106d70ern+17 ldm.l @sp+, (ernCern+2) 01206d70ern+29 ldm.l @sp+, (ernCern+3) 01306d70ern+311 notes
rev. 3.0, 07/00, page 130 of 320 2.2.37 ldmac ldmac (load to mac register) load mac register operation ers ? mach or ers ? macl assembly-language format ldmac ers, mac register operand size longword condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction moves the contents of a general register to a multiply-accumulate register (mach or macl). if the transfer is to mach, only the lowest 10 bits of the general register are transferred. supported only by the h8s/2600 cpu. available registers ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct ldmac ers, mach 0 3 2 0 ers 2 * register direct ldmac ers, macl 0 3 3 0 ers 2 * note: * a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes execution of this instruction clears the overflow flag in the multiplier to 0.
rev. 3.0, 07/00, page 131 of 320 2.2.38 mac mac (multiply and accumulate) multiply and accumulate operation (ean) (eam) + mac register ? mac register ern + 2 ? ern erm + 2 ? erm assembly-language format mac @ern+, @erm+ operand size condition code i * * * uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction performs signed multiplication on two 16-bit operands at addresses given by the contents of general registers ern and erm, adds the 32-bit product to the contents of the mac register, and stores the sum in the mac register. after this operation, ern and erm are both incremented by 2. the operation can be carried out in saturating or non-saturating mode, depending on the macs bit in a system control register. (syscr) see the relevant hardware manual for further information. in non-saturating mode, mach and macl are concatenated to store a 42-bit result. the value of bit 41 is copied into the upper 22 bits of mach as a sign extension. in saturating mode, only macl is valid, and the result is limited to the range from h'80000000 (minimum value) to h'7fffffff (maximum value). if the result overflows in the negative direction, h'80000000 (the minimum value) is stored in macl. if the result overflows in the positive direction, h'7fffffff (the maximum value) is stored in macl. the lsb of the mach register indicates the status of the overflow flag (v-mult) in the multiplier. other bits retain their previous contents. this instruction is supported only by the h8s/2600 cpu.
rev. 3.0, 07/00, page 132 of 320 mac (multiply and accumulate) multiply and accumulate operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register indirect with post-increment mac @ern+, @erm+ 01606d0ern0erm4 notes 1. flags (n, z, v) indicating the result of the mac instruction can be set in the condition-code register (ccr) by the stmac instruction. 2. if ern and erm are the same register, the execution addresses are ern and ern + 2. after execution, the value of ern is ern + 4. 3. if macs is modified during execution of a mac instruction, the result cannot be guaranteed. it is essential to wait for at least three states after a mac instruction before modifying macs. further explanation of instructions using multiplier 1. modification of flags the multiplier has n-mult, z-mult, and v-mult flags that indicate the results of mac instructions. these flags are separated from the condition-code register (ccr). the values of these flags can be set in the n, z, and v flags of the ccr only by the stmac instruction. n-mult and z-mult are modified only by mac instructions. v-mult retains a value indicating whether an overflow has occurred in the past, until it is cleared by execution of the clrmac or ldmac instruction. the setting and clearing conditions for these flags are given below. ? n-mult (negative flag) saturating mode set when bit 31 of register macl is set to 1 by execution of a mac instruction cleared when bit 31 of register macl is cleared to 0 by execution of a mac instruction non-saturating mode set when bit 41 of register mach is set to 1 by execution of a mac instruction cleared when bit 41 of register mach is cleared to 0 by execution of a mac instruction
rev. 3.0, 07/00, page 133 of 320 mac (multiply and accumulate) multiply and accumulate ? z-mult (zero flag) saturating mode set when register macl is cleared to 0 by execution of a mac instruction cleared when register macl is not cleared to 0 by execution of a mac instruction non-saturating mode set when registers mach and macl are both cleared to 0 by execution of a mac instruction cleared when register mach or macl is not cleared to 0 by execution of a mac instruction ? v-mult (overflow flag) saturating mode set when the result of the mac instruction overflows the range from h'80000000 (minimum) to h'7fffffff (maximum) cleared when a clrmac or ldmac instruction is executed note: not cleared when the result of the mac instruction is within the above range non-saturating mode set when the result of the mac instruction overflows the range from h'20000000000 (minimum) to h'1ffffffffff (maximum) cleared when a clrmac or ldmac instruction is executed note: not cleared when the result of the mac instruction is within the above range the n-mult, z-mult, and v-mult flags are not modified by switching between saturating and non-saturating modes, or by execution of a multiply instruction (mulxu or mulxs). 2. example clrmac mac @er1+,@er2+ mac @er1+,@er2+ ??? overflow occurs : mac @er1+,@er2+ ??? result = 0 nop stmac mach,er3 ??? ccr (n = 0, z = 1, v = 1) clrmac stmac mach,er3 ??? ccr (n = 0, z = 1, v = 0)
rev. 3.0, 07/00, page 134 of 320 2.2.39 (1) mov (b) mov (move data) move operation rs ? rd assembly-language format mov.b rs, rd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers one byte of data from an 8-bit register rs to an 8-bit register rd, tests the transferred data, and sets condition-code flags according to the result. available registers rs: r0l to r7l, r0h to r7h rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mov.b rs, rd 0 c rs rd 1 notes
rev. 3.0, 07/00, page 135 of 320 2.2.39 (2) mov (w) mov (move data) move operation rs ? rd assembly-language format mov.w rs, rd operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers one word of data from a 16-bit register rs to a 16-bit register rd, tests the transferred data, and sets condition-code flags according to the result. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mov.w rs, rd 0 d rs rd 1 notes
rev. 3.0, 07/00, page 136 of 320 2.2.39 (3) mov (l) mov (move data) move operation ers ? erd assembly-language format mov.l ers, erd operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers one word of data from a 32-bit register ers to a 32-bit register erd, tests the transferred data, and sets condition-code flags according to the result. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mov.l ers, erd 0 f 1 ers 0 erd 1 notes
rev. 3.0, 07/00, page 137 of 320 2.2.39 (4) mov (b) mov (move data) move operation (eas) ? rd assembly-language format mov.b , rd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the source operand contents to an 8-bit register rd, tests the transferred data, and sets condition-code flags according to the result. available registers rd: r0l to r7l, r0h to r7h ers: er0 to er7
rev. 3.0, 07/00, page 138 of 320 mov (move data) move operand format and number of states required for execution notes the mov.b @er7+, rd instruction should never be used, because it leaves an odd value in the stack pointer (er7). for details refer to section 3.3, exception-handling state, or to the relevant hardware manual. for the @aa:8/@aa:16 access range, refer to the relevant microcontroller hardware manual. addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states immediate mov.b #xx:8, rd f rd imm 1 mov.b @ers, rd 6 8 0 ers rd 2 mov.b 6 e 0 ers rd disp 3 mov.b 7 8 0 ers 0 6 a 2 rd disp 5 mov.b @ers+, rd 6 c 0 ers rd 3 mov.b @aa:8, rd 2 rd abs 2 mov.b @aa:16, rd 6 a 0 rd abs 3 mov.b @aa:32, rd 6 a 2 rd abs 4 absolute address register indirect with displace- ment register indirect with post- increment register indirect @(d:16, ers), rd @(d:32, ers), rd
rev. 3.0, 07/00, page 139 of 320 2.2.39 (5) mov (w) mov (move data) move operation (eas) ? rd assembly-language format mov.w , rd operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the source operand contents to a 16-bit register rd, tests the transferred data, and sets condition-code flags according to the result. available registers rd: r0 to r7, e0 to e7 ers: er0 to er7
rev. 3.0, 07/00, page 140 of 320 mov (move data) move operand format and number of states required for execution notes 1. the source operand must be located at an even address. 2. in machine language, mov.w @er7+, rd is identical to pop.w rd. addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states immediate mov.w #xx:16, rd 7 9 0 rd imm 2 mov.w @ers, rd 6 9 0 ers rd 2 mov.w 6 f 0 ers rd disp 3 mov.w 7 8 0 ers 0 6 b 2 rd disp 5 mov.w @ers+, rd 6 d 0 ers rd 3 mov.w @aa:16, rd 6 b 0 rd abs 3 mov.w @aa:32, rd 6 b 2 rd abs 4 absolute address register indirect with displace- ment register indirect with post- increment register indirect @(d:16, ers), rd @(d:32, ers), rd
rev. 3.0, 07/00, page 141 of 320 2.2.39 (6) mov (l) mov (move data) move operation (eas) ? erd assembly-language format mov.l , erd operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the source operand contents to a specified 32-bit register (erd), tests the transferred data, and sets condition-code flags according to the result. the first memory word located at the effective address is stored in extended register ed. the next word is stored in general register rd. erd ed rdh rdl msb lsb ea available registers ers: er0 to er7 erd: er0 to er7
rev. 3.0, 07/00, page 142 of 320 mov (move data) move operand format and number of states required for execution notes 1. the source operand must be located at an even address. 2. in machine language, mov.l @r7+, erd is identical to pop.l erd. addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte states mov.l #xx:32, rd 7 a 0 0 erd imm 3 mov.l @ers, erd 0100690ers0erd 4 mov.l @(d:16, ers), erd 01006f0ers0erd disp 5 mov.l @(d:32, ers), erd 0100780ers06b20erd disp 7 mov.l @ers+, erd 01006d0ers0erd 5 mov.l @aa:16, erd 01006b00erd abs 5 mov.l @aa:32, erd 01006b20erd abs 6 register indirect immediate register indirect with displace- ment register indirect with post- increment absolute address
rev. 3.0, 07/00, page 143 of 320 2.2.39 (7) mov (b) mov (move data) move operation rs ? (ead) assembly-language format mov.b rs, operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the contents of an 8-bit register rs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. available registers rs: r0l to r7l, r0h to r7h erd: er0 to er7
rev. 3.0, 07/00, page 144 of 320 mov (move data) move operand format and number of states required for execution notes 1. the mov.b rs, @Cer7 instruction should never be used, because it leaves an odd value in the stack pointer (er7). for details refer to section 3.3, exception-handling state, or to the relevant hardware manual. 2. execution of mov.b rnl, @Cern or mov.b rnh, @Cern first decrements ern by one, then transfers the designated part (rnl or rnh) of the resulting ern value. addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states mov.b rs, @erd 6 8 1 erd rs 2 mov.b 6 e 1 erd rs disp 3 mov.b 7 8 0 erd 0 6 a a rs disp 5 mov.b rs, @Cerd 6 c 1 erd rs 3 mov.b rs, @aa:8 3 rs abs 2 mov.b rs, @aa:16 6 a 8 rs abs 3 mov.b rs, @aa:32 6 a a rs abs 4 absolute address register indirect with displace- ment register indirect with pre- decrement register indirect rs, @(d:16, erd) rs, @(d:32, erd)
rev. 3.0, 07/00, page 145 of 320 2.2.39 (8) mov (w) mov (move data) move operation rs ? (ead) assembly-language format mov.w rs, operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the contents of a 16-bit register rs (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. available registers rs: r0 to r7, e0 to e7 erd: er0 to er7
rev. 3.0, 07/00, page 146 of 320 mov (move data) move operand format and number of states required for execution notes 1. the destination operand must be located at an even address. 2. in machine language, mov.w rs, @Cer7 is identical to push.w rs. 3. when mov.w rn, @Cern is executed, the transferred value comes from (value of ern before execution) C 2. addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte states mov.w rs, @erd 6 9 1 erd rs 2 mov.w 6 f 1 erd rs disp 3 mov.w 7 8 0 erd 0 6 b a rs disp 5 mov.w rs, @Cerd 6 d 1 erd rs 3 mov.w rs, @aa:16 6 b 8 rs abs 3 mov.w rs, @aa:32 6 b a rs abs 4 absolute address register indirect with displace- ment register indirect with pre- decrement register indirect rs, @(d:16, erd) rs, @(d:32, erd)
rev. 3.0, 07/00, page 147 of 320 2.2.39 (9) mov (l) mov (move data) move operation ers ? (ead) assembly-language format mov.l ers, operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the contents of a 32-bit register ers (source operand) to a destination location, tests the transferred data, and sets condition-code flags according to the result. the extended register (es) contents are stored at the first word indicated by the effective address. the general register (rs) contents are stored at the next word. ers es rsh rsl msb lsb ea available registers ers: er0 to er7 erd: er0 to er7
rev. 3.0, 07/00, page 148 of 320 mov (move data) move operand format and number of states required for execution notes 1. the destination operand must be located at an even address. 2. in machine language, mov.l ers, @Cer7 is identical to push.l ers. 3. when mov.l ern, @Cern is executed, the transferred value is (value of ern before execution) C 4. addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte states mov.l ers, @erd 0100691erd0ers 4 mov.l ers, @(d:16, erd) 01006f1erd0ers disp 5 mov.l ers, @(d:32, erd) 0100780erd06ba0ers disp 7 mov.l ers, @Cerd 01006d1erd0ers 5 mov.l ers, @aa:16 01006b80ers abs 5 mov.l ers, @aa:32 01006ba0ers abs 6 register indirect register indirect with displace- ment register indirect with pre- decrement absolute address
rev. 3.0, 07/00, page 149 of 320 2.2.40 movfpe movfpe (move from peripheral with e clock) move data with e clock operation (eas) ? rd synchronized with e clock assembly-language format movfpe @aa:16, rd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers memory contents specified by a 16-bit absolute address to a general register rd in synchronization with an e clock, tests the transferred data, and sets condition-code flags according to the result. note: avoid using this instruction in microcontrollers without an e clock output pin, or in single-chip mode. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states absolute address movfpe @aa:16, rd 6 a 4 rd abs * note: * for details, refer to the relevant microcontroller hardware manual. notes 1. this instruction cannot be used with addressing modes other than the above, and cannot transfer word data or longword data. 2. the number of states required for execution is variable. for details, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 150 of 320 2.2.41 movtpe movtpe (move to peripheral with e clock) move data with e clock operation rs ? (ead) synchronized with e clock assembly-language format movtpe rs, @aa:16 operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction transfers the contents of a general register rs (source operand) to a destination location specified by a 16-bit absolute address in synchronization with an e clock, tests the transferred data, and sets condition-code flags according to the result. note: avoid using this instruction in microcontrollers without an e clock output pin, or in single-chip mode. available registers rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states absolute address movtpe rs, @aa:16 6 a c rs abs * note: * for details, refer to the relevant microcontroller hardware manual. notes 1. this instruction cannot be used with addressing modes other than the above, and cannot transfer word data or longword data. 2. the number of states required for execution is variable. for details, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 151 of 320 2.2.42 (1) mulxs (b) mulxs (multiply extend as signed) multiply signed operation rd rs ? rd assembly-language format mulxs.b rs, rd operand size byte condition code i ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction multiplies the lower 8 bits of a 16-bit register rd (destination operand) by the contents of an 8-bit register rs (source operand) as signed data and stores the result in the 16-bit register rd. if rd is one of general registers r0 to r7, rs can be the upper part (rdh) or lower part (rdl) of rd. the operation performed is 8 bits 8 bits ? 16 bits signed multiplication. rd rs rd dont care multiplicand multiplier ? product 8 bits 8 bits 16 bits available registers rd: r0 to r7, e0 to e7 rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mulxs.b rs, rd 0 1 c 0 5 0 rs rd 4 * note: * the number of states in the h8s/2000 cpu is 13. a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes
rev. 3.0, 07/00, page 152 of 320 2.2.42 (2) mulxs (w) mulxs (multiply extend as signed) multiply signed operation erd rs ? erd assembly-language format mulxs.w rs, erd operand size word condition code i ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction multiplies the lower 16 bits of a 32-bit register erd (destination operand) by the contents of a 16-bit register rs (source operand) as signed data and stores the result in the 32-bit register erd. rs can be the upper part (ed) or lower part (rd) of erd. the operation performed is 16 bits 16 bits ? 32 bits signed multiplication. erd rs erd dont care multiplicand multiplier ? product 16 bits 16 bits 32 bits available registers erd: er0 to er7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mulxs.w rs, erd 0 1 c 0 5 2 rs 0 erd 5 * note: * the number of states in the h8s/2000 cpu is 21. a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes
rev. 3.0, 07/00, page 153 of 320 2.2.43 (1) mulxu (b) mulxu (multiply extend as unsigned) multiply operation rd rs ? rd assembly-language format mulxu.b rs, rd operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction multiplies the lower 8 bits of a 16-bit register rd (destination operand) by the contents of an 8-bit register rs (source operand) as unsigned data and stores the result in the 16-bit register rd. if rd is one of general registers r0 to r7, rs can be the upper part (rdh) or lower part (rdl) of rd. the operation performed is 8 bits 8 bits ? 16 bits unsigned multiplication. rd rs rd dont care multiplicand multiplier ? product 8 bits 8 bits 16 bits available registers rd: r0 to r7, e0 to e7 rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mulxu.b rs, rd 5 0 rs rd 3 * note: * the number of states in the h8s/2000 cpu is 12. a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes
rev. 3.0, 07/00, page 154 of 320 2.2.43 (2) mulxu (w) mulxu (multiply extend as unsigned) multiply operation erd rs ? erd assembly-language format mulxu.w rs, erd operand size word condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction multiplies the lower 16 bits of a 32-bit register erd (destination operand) by the contents of a 16-bit register rs (source operand) as unsigned data and stores the result in the 32-bit register erd. rs can be the upper part (ed) or lower part (rd) of erd. the operation performed is 16 bits 16 bits ? 32 bits unsigned multiplication. erd rs erd dont care multiplicand multiplier ? product 16 bits 16 bits 32 bits available registers erd: er0 to er7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct mulxu.w rs, erd 5 2 rs 0 erd 4 * note: * the number of states in the h8s/2000 cpu is 20. a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes
rev. 3.0, 07/00, page 155 of 320 2.2.44 (1) neg (b) neg (negate) negate binary signed operation 0 C rd ? rd assembly-language format neg.b rd operand size byte condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 3; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 7; otherwise cleared to 0. description this instruction takes the twos complement of the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd (subtracting the register contents from h'00). if the original contents of rd were h'80, however, the result remains h'80. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct neg.b rd 1 7 8 rd 1 notes an overflow occurs if the original contents of rd were h'80.
rev. 3.0, 07/00, page 156 of 320 2.2.44 (2) neg (w) neg (negate) negate binary signed operation 0 C rd ? rd assembly-language format neg.w rd operand size word condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 11; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 15; otherwise cleared to 0. description this instruction takes the twos complement of the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd (subtracting the register contents from h'0000). if the original contents of rd were h'8000, however, the result remains h'8000. available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct neg.w rd 1 7 9 rd 1 notes an overflow occurs if the original contents of rd were h'8000.
rev. 3.0, 07/00, page 157 of 320 2.2.44 (3) neg (l) neg (negate) negate binary signed operation 0 C erd ? erd assembly-language format neg.l erd operand size longword condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 27; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 31; otherwise cleared to 0. description this instruction takes the twos complement of the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd (subtracting the register contents from h'00000000). if the original contents of erd were h'80000000, however, the result remains h'80000000. available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct neg.l erd 1 7 b 0 erd 1 notes an overflow occurs if the original contents of erd were h'80000000.
rev. 3.0, 07/00, page 158 of 320 2.2.45 nop nop (no operation) no operation operation pc + 2 ? pc assembly-language format nop operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction only increments the program counter, causing the next instruction to be executed. the internal state of the cpu does not change. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states nop 0000 1 notes
rev. 3.0, 07/00, page 159 of 320 2.2.46 (1) not (b) not (not = logical complement) logical complement operation ? rd ? rd assembly-language format not.b rd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction takes the ones complement of the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct not.b rd 1 7 0 rd 1 notes
rev. 3.0, 07/00, page 160 of 320 2.2.46 (2) not (w) not (not = logical complement) logical complement operation ? rd ? rd assembly-language format not.w rd operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction takes the ones complement of the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct not.w rd 1 7 1 rd 1 notes
rev. 3.0, 07/00, page 161 of 320 2.2.46 (3) not (l) not (not = logical complement) logical complement operation ? erd ? erd assembly-language format not.l erd operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction takes the ones complement of the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct not.l erd 1 7 3 0 erd 1 notes
rev. 3.0, 07/00, page 162 of 320 2.2.47 (1) or (b) or (inclusive or logical) logical or operation rd (eas) ? rd assembly-language format or.b < eas>, rd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction ors the source operand with the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate or.b #xx:8, rd c rd imm 1 register direct or.b rs, rd 1 4 rs rd 1 notes
rev. 3.0, 07/00, page 163 of 320 2.2.47 (2) or (w) or (inclusive or logical) logical or operation rd (eas) ? rd assembly-language format or.w < eas>, rd operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction ors the source operand with the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate or.w #xx:16, rd 7 9 4 rd imm 2 register direct or.w rs, rd 6 4 rs rd 1 notes
rev. 3.0, 07/00, page 164 of 320 2.2.47 (3) or (l) or (inclusive or logical) logical or operation erd (eas) ? erd assembly-language format or.l < eas>, erd operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction ors the source operand with the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte no. of states immediate or.l #xx:32, erd 7 a 4 0 erd imm 3 register direct or.l ers, erd 0 1 f 0 6 4 0 ers 0 erd 2 notes
rev. 3.0, 07/00, page 165 of 320 2.2.48 (1) orc orc (inclusive or control register) logical or with ccr operation ccr #imm ? ccr assembly-language format orc #xx:8, ccr operand size byte condition code i ? ? ? ? ? ? ? ? uihunzvc i: stores the corresponding bit of the result. ui: stores the corresponding bit of the result. h: stores the corresponding bit of the result. u: stores the corresponding bit of the result. n: stores the corresponding bit of the result. z: stores the corresponding bit of the result. v: stores the corresponding bit of the result. c: stores the corresponding bit of the result. description this instruction ors the contents of the condition-code register (ccr) with immediate data and stores the result in the condition-code register. no interrupt requests, including nmi, are accepted immediately after execution of this instruction. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate orc #xx:8, ccr 0 4 imm 1 notes
rev. 3.0, 07/00, page 166 of 320 2.2.48 (2) orc orc (inclusive or control register) logical or with exr operation exr #imm ? exr assembly-language format orc #xx:8, exr operand size byte condition code i uihunzvc h: stores the corresponding bit of the result. n: stores the corresponding bit of the result. z: stores the corresponding bit of the result. v: stores the corresponding bit of the result. c: stores the corresponding bit of the result. description this instruction ors the contents of the extended control register (exr) with immediate data and stores the result in the extended control register. no interrupt requests, including nmi, are accepted for three states after execution of this instruction. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate orc#xx:8, exr014104 imm 2 notes
rev. 3.0, 07/00, page 167 of 320 2.2.49 (1) pop (w) pop (pop data) pop data from stack operation @sp+ ? rn assembly-language format pop.w rn operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction restores data from the stack to a 16-bit general register rn, tests the restored data, and sets condition-code flags according to the result. available registers rn: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states pop.wrn6d7rn 3 notes pop.w rn is identical to mov.w @sp+, rn.
rev. 3.0, 07/00, page 168 of 320 2.2.49 (2) pop (l) pop (pop data) pop data from stack operation @sp+ ? ern assembly-language format pop.l ern operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction restores data from the stack to a 32-bit general register ern, tests the restored data, and sets condition-code flags according to the result. available registers ern: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states pop.l ern 01006d70ern5 notes pop.l ern is identical to mov.l @sp+, ern.
rev. 3.0, 07/00, page 169 of 320 2.2.50 (1) push (w) push (push data) push data on stack operation rn ? @Csp assembly-language format push.w rn operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction saves data from a 16-bit register rn onto the stack, tests the saved data, and sets condition-code flags according to the result. available registers rn: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states push.w rn 6 d f rn 3 notes 1. push.w rn is identical to mov.w rn, @Csp. 2. when push.w r7 or push.w e7 is executed, the value saved on the stack is the r7 or e7 value after effective address calculation (after er7 is decremented by 2).
rev. 3.0, 07/00, page 170 of 320 2.2.50 (2) push (l) push (push data) push data on stack operation ern ? @Csp assembly-language format push.l ern operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the transferred data is negative; otherwise cleared to 0. z: set to 1 if the transferred data is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction pushes data from a 32-bit register ern onto the stack, tests the saved data, and sets condition-code flags according to the result. available registers ern: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states push.l ern 01006df0ern5 notes 1. push.l ern is identical to mov.l ern, @Csp. 2. when push.l er7 is executed, the value saved on the stack is the er7 value after effective address calculation (after er7 is decremented by 4).
rev. 3.0, 07/00, page 171 of 320 2.2.51 (1) rotl (b) rotl (rotate left) rotate operation rd (left rotation) ? rd assembly-language format rotl.b rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 7. description this instruction rotates the bits in an 8-bit register rd (destination operand) one bit to the left. the most significant bit (bit 7) is rotated to the least significant bit (bit 0), and also copied to the carry flag. msb lsb cb7 b0 . . . . . . available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotl.b rd 1 2 8 rd 1 notes
rev. 3.0, 07/00, page 172 of 320 2.2.51 (2) rotl (b) rotl (rotate left) rotate operation rd (left rotation) ? rd assembly-language format rotl.b #2, rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 6. description this instruction rotates the bits in an 8-bit register rd (destination operand) two bits to the left. the most significant two bits (bits 7 and 6) are rotated to the least significant two bits (bits 1 and 0), and bit 6 is also copied to the carry flag. msb lsb cb7 b0 . . . . b6 b1 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotl.b #2, rd 1 2 c rd 1 notes
rev. 3.0, 07/00, page 173 of 320 2.2.51 (3) rotl (w) rotl (rotate left) rotate operation rd (left rotation) ? rd assembly-language format rotl.w rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 15. description this instruction rotates the bits in a 16-bit register rd (destination operand) one bit to the left. the most significant bit (bit 15)is rotated to the least significant bit (bit 0), and also copied to the carry flag. msb lsb c b15 b0 . . . . . . available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotl.w rd 1 2 9 rd 1 notes
rev. 3.0, 07/00, page 174 of 320 2.2.51 (4) rotl (w) rotl (rotate left) rotate operation rd (left rotation) ? rd assembly-language format rotl.w #2, rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 14. description this instruction rotates the bits in a 16-bit register rd (destination operand) two bits to the left. the most significant two bits (bits 15 and 14) are rotated to the least significant two bits (bits 1 and 0), and bit 14 is also copied to the carry flag. msb lsb c b15 b0 . . . . b14 b1 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotl.w #2, rd 1 2 d rd 1 notes
rev. 3.0, 07/00, page 175 of 320 2.2.51 (5) rotl (l) rotl (rotate left) rotate operation erd (left rotation) ? erd assembly-language format rotl.l erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 31. description this instruction rotates the bits in a 32-bit register erd (destination operand) one bit to the left. the most significant bit (bit 31) is rotated to the least significant bit (bit 0), and also copied to the carry flag. msb lsb c b31 b0 . . . . . . available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotl.l erd 1 2 b 0 erd 1 notes
rev. 3.0, 07/00, page 176 of 320 2.2.51 (6) rotl (l) rotl (rotate left) rotate operation erd (left rotation) ? erd assembly-language format rotl.l #2, erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 30. description this instruction rotates the bits in a 32-bit register erd (destination operand) two bits to the left. the most significant two bits (bits 31 and 30) are rotated to the least significant two bits (bits 1 and 0), and bit 30 is also copied to the carry flag. msb lsb c b31 b0 . . . . b30 b1 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotl.l #2, erd 1 2 f 0 erd 1 notes
rev. 3.0, 07/00, page 177 of 320 2.2.52 (1) rotr (b) rotr (rotate right) rotate operation rd (right rotation) ? rd assembly-language format rotr.b rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction rotates the bits in an 8-bit register rd (destination operand) one bit to the right. the least significant bit (bit 0) is rotated to the most significant bit (bit 7), and also copied to the carry flag. msb lsb b7 b0 . . . . . . c available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotr.b rd 1 3 8 rd 1 notes
rev. 3.0, 07/00, page 178 of 320 2.2.52 (2) rotr (b) rotr (rotate right) rotate operation rd (right rotation) ? rd assembly-language format rotr.b #2, rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction rotates the bits in an 8-bit register rd (destination operand) two bits to the right. the least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 7 and 6), and bit 1 is also copied to the carry flag. msb lsb b7 b0 . . . . c b1 b6 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotr.b #2, rd 1 3 c rd 1 notes
rev. 3.0, 07/00, page 179 of 320 2.2.52 (3) rotr (w) rotr (rotate right) rotate operation rd (right rotation) ? rd assembly-language format rotr.w rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction rotates the bits in a 16-bit register rd (destination operand) one bit to the right. the least significant bit (bit 0) is rotated to the most significant bit (bit 15), and also copied to the carry flag. msb lsb b15 b0 . . . . . . c available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotr.w rd 1 3 9 rd 1 notes
rev. 3.0, 07/00, page 180 of 320 2.2.52 (4) rotr (w) rotr (rotate right) rotate operation rd (right rotation) ? rd assembly-language format rotr.w #2, rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction rotates the bits in a 16-bit register rd (destination operand) two bits to the right. the least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 15 and 14), and bit 1 is also copied to the carry flag. msb lsb b15 b0 . . . . c b1 b14 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotr.w #2, rd 1 3 d rd 1 notes
rev. 3.0, 07/00, page 181 of 320 2.2.52 (5) rotr (l) rotr (rotate right) rotate operation erd (right rotation) ? erd assembly-language format rotr.l erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction rotates the bits in a 32-bit register erd (destination operand) one bit to the right. the least significant bit (bit 0) is rotated to the most significant bit (bit 31), and also copied to the carry flag. msb lsb b31 b0 . . . . . . c available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotr.l erd 1 3 b 0 erd 1 notes
rev. 3.0, 07/00, page 182 of 320 2.2.52 (6) rotr (l) rotr (rotate right) rotate operation erd (right rotation) ? erd assembly-language format rotr.l #2, erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction rotates the bits in a 32-bit register erd (destination operand) two bits to the right. the least significant two bits (bits 1 and 0) are rotated to the most significant two bits (bits 31 and 30), and bit 1 is also copied to the carry flag. msb lsb b31 b0 . . . . c b1 b30 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotr.l #2, erd 1 3 f 0 erd 1 notes
rev. 3.0, 07/00, page 183 of 320 2.2.53 (1) rotxl (b) rotxl (rotate with extend carry left) rotate through carry operation rd (left rotation through carry flag) ? rd assembly-language format rotxl.b rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 7. description this instruction rotates the bits in an 8-bit register rd (destination operand) one bit to the left through the carry flag. the carry flag is rotated into the least significant bit (bit 0). the most significant bit (bit 7) rotates into the carry flag. msb lsb cb7 b0 . . . . . . available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxl.b rd 1 2 0 rd 1 notes
rev. 3.0, 07/00, page 184 of 320 2.2.53 (2) rotxl (b) rotxl (rotate with extend carry left) rotate through carry operation rd (left rotation through carry flag) ? rd assembly-language format rotxl.b #2, rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 6. description this instruction rotates the bits in an 8-bit register rd (destination operand) two bits to the left through the carry flag. the carry flag rotates into bit 1, bit 7 rotates into bit 0, and bit 6 rotates into the carry flag. msb lsb cb7 b0 . . . . . . b1 b6 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxl.b #2, rd 1 2 4 rd 1 notes
rev. 3.0, 07/00, page 185 of 320 2.2.53 (3) rotxl (w) rotxl (rotate with extend carry left) rotate through carry operation rd (left rotation through carry flag) ? rd assembly-language format rotxl.w rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 15. description this instruction rotates the bits in a 16-bit register rd (destination operand) one bit to the left through the carry flag. the carry flag is rotated into the least significant bit (bit 0). the most significant bit (bit 15) rotates into the carry flag. msb lsb c b15 b0 . . . . . . available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxl.w rd 1 2 1 rd 1 notes
rev. 3.0, 07/00, page 186 of 320 2.2.53 (4) rotxl (w) rotxl (rotate with extend carry left) rotate through carry operation rd (left rotation through carry flag) ? rd assembly-language format rotxl.w #2, rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 14. description this instruction rotates the bits in a 16-bit register rd (destination operand) two bits to the left through the carry flag. the carry flag rotates into bit 1, bit 15 rotates into bit 0, and bit 14 rotates into the carry flag. msb lsb c b15 b0 . . . . . . b1 b14 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxl.w #2, rd 1 2 5 rd 1 notes
rev. 3.0, 07/00, page 187 of 320 2.2.53 (5) rotxl (l) rotxl (rotate with extend carry left) rotate through carry operation erd (left rotation through carry flag) ? erd assembly-language format rotxl.l erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 31. description this instruction rotates the bits in a 32-bit register erd (destination operand) one bit to the left through the carry flag. the carry flag is rotated into the least significant bit (bit 0). the most significant bit (bit 31) rotates into the carry flag. msb lsb c b31 b0 . . . . . . available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxl.l erd 1 2 3 0 erd 1 notes
rev. 3.0, 07/00, page 188 of 320 2.2.53 (6) rotxl (l) rotxl (rotate with extend carry left) rotate through carry operation erd (left rotation through carry flag) ? erd assembly-language format rotxl.l #2, erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 30. description this instruction rotates the bits in a 32-bit register erd (destination operand) two bits to the left through the carry flag. the carry flag rotates into bit 1, bit 31 rotates into bit 0, and bit 30 rotates into into the carry flag. msb lsb c b31 b0 . . . . . . b1 b30 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxl.l #2, erd 1 2 7 0 erd 1 notes
rev. 3.0, 07/00, page 189 of 320 2.2.54 (1) rotxr (b) rotxr (rotate with extend carry right) rotate through carry operation rd (right rotation through carry flag) ? rd assembly-language format rotxr.b rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction rotates the bits in an 8-bit register rd (destination operand) one bit to the right through the carry flag. the carry flag is rotated into the most significant bit (bit 7). the least significant bit (bit 0) rotates into the carry flag. lsb msb b7 b0 . . . . . . c available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxr.b rd 1 3 0 rd 1 notes
rev. 3.0, 07/00, page 190 of 320 2.2.54 (2) rotxr (b) rotxr (rotate with extend carry right) rotate through carry operation rd (right rotation through carry flag) ? rd assembly-language format rotxr.b #2, rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction rotates the bits in an 8-bit register rd (destination operand) two bits to the right through the carry flag. the carry flag rotates into bit 6, bit 0 rotates into bit 7, and bit 1 rotates into the carry flag. lsb msb b7 b0 . . . . c b1 b6 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxr.b #2, rd 1 3 4 rd 1 notes
rev. 3.0, 07/00, page 191 of 320 2.2.54 (3) rotxr (w) rotxr (rotate with extend carry right) rotate through carry operation rd (right rotation through carry flag) ? rd assembly-language format rotxr.w rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction rotates the bits in a 16-bit register rd (destination operand) one bit to the right through the carry flag. the carry flag is rotated into the most significant bit (bit 15). the least significant bit (bit 0) rotates into the carry flag. lsb msb b15 b0 . . . . . . c available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxr.w rd 1 3 1 rd 1 notes
rev. 3.0, 07/00, page 192 of 320 2.2.54 (4) rotxr (w) rotxr (rotate with extend carry right) rotate through carry operation rd (right rotation through carry flag) ? rd assembly-language format rotxr.w #2, rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction rotates the bits in a 16-bit register rd (destination operand) two bits to the right through the carry flag. the carry flag rotates into bit 14, bit 0 rotates into bit 15, and bit 1 rotates into the carry flag. lsb msb b15 b0 . . . . c b1 b14 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxr.w #2, rd 1 3 5 rd 1 notes
rev. 3.0, 07/00, page 193 of 320 2.2.54 (5) rotxr (l) rotxr (rotate with extend carry right) rotate through carry operation erd (right rotation through carry flag) ? erd assembly-language format rotxr.l erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction rotates the bits in a 32-bit register erd (destination operand) one bit to the right through the carry flag. the carry flag is rotated into the most significant bit (bit 31). the least significant bit (bit 0) rotates into the carry flag. lsb msb b31 b0 . . . . . . c available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxr.l erd 1 3 3 0 erd 1 notes
rev. 3.0, 07/00, page 194 of 320 2.2.54 (6) rotxr (l) rotxr (rotate with extend carry right) rotate through carry operation erd (right rotation through carry flag) ? erd assembly-language format rotxr.l #2, erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction rotates the bits in a 32-bit register erd (destination operand) two bits to the right through the carry flag. the carry flag rotates into bit 30, bit 0 rotates into bit 31, and bit 1 rotates into the carry flag. lsb msb b31 b0 . . . . c b1 b30 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct rotxr.l #2, erd 1 3 7 0 erd 1 notes
rev. 3.0, 07/00, page 195 of 320 2.2.55 rte rte (return from exception) return from exception handling operation when exr is invalid @sp+ ? ccr @sp+ ? pc when exr is valid @sp+ ? exr @sp+ ? ccr @sp+ ? pc assembly-language format rte operand size condition code i ? ? ? ? ? ? ? ? uihunzvc i: restored from the corresponding bit on the stack. ui: restored from the corresponding bit on the stack. h: restored from the corresponding bit on the stack. u: restored from the corresponding bit on the stack. n: restored from the corresponding bit on the stack. z: restored from the corresponding bit on the stack. v: restored from the corresponding bit on the stack. c: restored from the corresponding bit on the stack. description this instruction returns from an exception-handling routine by restoring the exr, condition-code register (ccr) and program counter (pc) from the stack. program execution continues from the address restored to the program counter. the ccr and pc contents at the time of execution of this instruction are lost. if the extended control regiser (exr) is valid, it is also restored (and the existing exr contents are lost). operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states rte 5670 5 * note: * six states when exr is valid.
rev. 3.0, 07/00, page 196 of 320 rte (return from exception) return from exception handling notes the stack structure differs between normal mode and advanced mode. pc 23 16 15 8 7 0 normal mode dont care ccr pc 23 16 15 8 7 0 advanced mode ccr undet.
rev. 3.0, 07/00, page 197 of 320 2.2.56 rts rts (return from subroutine) return from subroutine operation @sp+ ? pc assembly-language format rts operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction returns from a subroutine by restoring the program counter (pc) from the stack. program execution continues from the address restored to the program counter. the pc contents at the time of execution of this instruction are lost. operand format and number of states required for execution instruction format no. of states addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte normal advanced rts 5470 4 5 notes the stack structure and number of states required for execution differ between normal mode and advanced mode. in normal mode, only the lower 16 bits of the program counter are restored. pc 23 16 15 8 7 0 normal mode pc 23 16 15 8 7 0 advanced mode undet. dont care
rev. 3.0, 07/00, page 198 of 320 2.2.57 (1) shal (b) shal (shift arithmetic left) shift arithmetic operation rd (left arithmetic shift) ? rd assembly-language format shal.b rd operand size byte condition code i ? ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: receives the previous value in bit 7. description this instruction shifts the bits in an 8-bit register rd (destination operand) one bit to the left. the most significant bit (bit 7) shifts into the carry flag. the least significant bit (bit 0) is cleared to 0. lsb msb b7 b0 . . . . . . c 0 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shal.b rd 1 0 8 rd 1 notes the shal instruction differs from the shll instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 199 of 320 2.2.57 (2) shal (b) shal (shift arithmetic left) shift arithmetic operation rd (left arithmetic shift) ? rd assembly-language format shal.b #2, rd operand size byte condition code i ? ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: receives the previous value in bit 6. description this instruction shifts the bits in an 8-bit register rd (destination operand) two bits to the left. bit 6 shifts into the carry flag. bits 0 and 1 are cleared to 0. lsb msb b7 b0 . . . . . . c 0 b1 b6 0 0 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shal.b #2, rd 1 0 c rd 1 notes the shal instruction differs from the shll instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 200 of 320 2.2.57 (3) shal (w) shal (shift arithmetic left) shift arithmetic operation rd (left arithmetic shift) ? rd assembly-language format shal.w rd operand size word condition code i ? ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: receives the previous value in bit 15. description this instruction shifts the bits in a 16-bit register rd (destination operand) one bit to the left. the most significant bit (bit 15) shifts into the carry flag. the least significant bit (bit 0) is cleared to 0. lsb msb b15 b0 . . . . . . c 0 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shal.w rd 1 0 9 rd 1 notes the shal instruction differs from the shll instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 201 of 320 2.2.57 (4) shal (w) shal (shift arithmetic left) shift arithmetic operation rd (left arithmetic shift) ? rd assembly-language format shal.w #2, rd operand size word condition code i ? ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: receives the previous value in bit 14. description this instruction shifts the bits in a 16-bit register rd (destination operand) two bits to the left. bit 14 shifts into the carry flag. bits 0 and 1 are cleared to 0. lsb msb b15 b0 . . . . . . c 0 b1 b14 0 0 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shal.w #2, rd 1 0 d rd 1 notes the shal instruction differs from the shll instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 202 of 320 2.2.57 (5) shal (l) shal (shift arithmetic left) shift arithmetic operation erd (left arithmetic shift) ? erd assembly-language format shal.l erd operand size longword condition code i ? ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: receives the previous value in bit 31. description this instruction shifts the bits in a 32-bit register erd (destination operand) one bit to the left. the most significant bit (bit 31) shifts into the carry flag. the least significant bit (bit 0) is cleared to 0. lsb msb b31 b0 . . . . . . c 0 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shal.l erd 1 0 b 0 erd 1 notes the shal instruction differs from the shll instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 203 of 320 2.2.57 (6) shal (l) shal (shift arithmetic left) shift arithmetic operation erd (left arithmetic shift) ? erd assembly-language format shal.l #2, erd operand size longword condition code i ? ? ? ? uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: receives the previous value in bit 30. description this instruction shifts the bits in a 32-bit register erd (destination operand) two bits to the left. bit 30 shifts into the carry flag. bits 0 and 1 are cleared to 0. lsb msb b31 b0 . . . . . . c 0 b1 b30 0 0 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shal.l #2, erd 1 0 f 0 erd 1 notes the shal instruction differs from the shll instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 204 of 320 2.2.58 (1) shar (b) shar (shift arithmetic right) shift arithmetic operation rd (right arithmetic shift) ? rd assembly-language format shar.b rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction shifts the bits in an 8-bit register rd (destination operand) one bit to the right. bit 0 shifts into the carry flag. bit 7 shifts into itself. since bit 7 remains unaltered, the sign does not change. lsb b7 b0 . . . . . . c msb available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shar.b rd 1 1 8 rd 1 notes
rev. 3.0, 07/00, page 205 of 320 2.2.58 (2) shar (b) shar (shift arithmetic right) shift arithmetic operation rd (right arithmetic shift) ? rd assembly-language format shar.b #2, rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction shifts the bits in an 8-bit register rd (destination operand) two bits to the right. bit 1 shifts into the carry flag. bits 7 and 6 receive the previous value of bit 7. since bit 7 remains unaltered, the sign does not change. lsb b7 b0 . . . c msb b1 b5 b6 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shar.b #2, rd 1 1 c rd 1 notes
rev. 3.0, 07/00, page 206 of 320 2.2.58 (3) shar (w) shar (shift arithmetic right) shift arithmetic operation rd (right arithmetic shift) ? rd assembly-language format shar.w rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction shifts the bits in a 16-bit register rd (destination operand) one bit to the right. bit 0 shifts into the carry flag. bit 15 shifts into itself. since bit 15 remains unaltered, the sign does not change. lsb b15 b0 . . . . . . c msb available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shar.w rd 1 1 9 rd 1 notes
rev. 3.0, 07/00, page 207 of 320 2.2.58 (4) shar (w) shar (shift arithmetic right) shift arithmetic operation rd (right arithmetic shift) ? rd assembly-language format shar.w #2, rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction shifts the bits in a 16-bit register rd (destination operand) two bits to the right. bit 1 shifts into the carry flag. bits 15 and 14 receive the previous value of bit 15. since bit 15 remains unaltered, the sign does not change. lsb b15 b0 . . . c msb b1 b13 b14 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shar.w #2, rd 1 1 d rd 1 notes
rev. 3.0, 07/00, page 208 of 320 2.2.58 (5) shar (l) shar (shift arithmetic right) shift arithmetic operation erd (right arithmetic shift) ? erd assembly-language format shar.l erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction shifts the bits in a 32-bit register erd (destination operand) one bit to the right. bit 0 shifts into the carry flag. bit 31 shifts into itself. since bit 31 remains unaltered, the sign does not change. lsb b31 b0 . . . . . . c msb available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shar.l erd 1 1 b 0 erd 1 notes
rev. 3.0, 07/00, page 209 of 320 2.2.58 (6) shar (l) shar (shift arithmetic right) shift arithmetic operation erd (right arithmetic shift) ? erd assembly-language format shar.l #2, erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction shifts the bits in a 32-bit register erd (destination operand) two bits to the right. bit 1 shifts into the carry flag. bits 31 and 30 receive the previous value of bit 31. since bit 31 remains unaltered, the sign does not change. lsb b31 b0 . . . c msb b1 b29 b30 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shar.l #2, erd 1 1 f 0 erd 1 notes
rev. 3.0, 07/00, page 210 of 320 2.2.59 (1) shll (b) shll (shift logical left) shift logical operation rd (left logical shift) ? rd assembly-language format shll.b rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 7. description this instruction shifts the bits in an 8-bit register rd (destination operand) one bit to the left. the most significant bit (bit 7) shifts into the carry flag. the least significant bit (bit 0) is cleared to 0. lsb msb b7 b0 . . . . . . c 0 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shll.b rd 1 0 0 rd 1 notes the shll instruction differs from the shal instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 211 of 320 2.2.59 (2) shll (b) shll (shift logical left) shift logical operation rd (left logical shift) ? rd assembly-language format shll.b #2, rd operand size byte condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 6. description this instruction shifts the bits in an 8-bit register rd (destination operand) two bits to the left. bit 6 shifts into the carry flag. bits 0 and 1 are cleared to 0. lsb msb b7 b0 . . . . c 0 b6 b1 0 0 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shll.b #2, rd 1 0 4 rd 1 notes the shll instruction differs from the shal instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 212 of 320 2.2.59 (3) shll (w) shll (shift logical left) shift logical operation rd (left logical shift) ? rd assembly-language format shll.w rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 15. description this instruction shifts the bits in a 16-bit register rd (destination operand) one bit to the left. the most significant bit (bit 15) shifts into the carry flag. the least significant bit (bit 0) is cleared to 0. lsb msb b15 b0 . . . . . . c 0 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shll.w rd 1 0 1 rd 1 notes the shll instruction differs from the shal instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 213 of 320 2.2.59 (4) shll (w) shll (shift logical left) shift logical operation rd (left logical shift) ? rd assembly-language format shll.w #2, rd operand size word condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 14. description this instruction shifts the bits in a 16-bit register rd (destination operand) two bits to the left. bit 14 shifts into the carry flag. bits 0 and 1 are cleared to 0. lsb msb b15 b0 . . . . c 0 b14 b1 0 0 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shll.w #2, rd 1 0 5 rd 1 notes the shll instruction differs from the shal instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 214 of 320 2.2.59 (5) shll (l) shll (shift logical left) shift logical operation erd (left logical shift) ? erd assembly-language format shll.l erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 31. description this instruction shifts the bits in a 32-bit register erd (destination operand) one bit to the left. the most significant bit (bit 31) shifts into the carry flag. the least significant bit (bit 0) is cleared to 0. lsb msb b31 b0 . . . . . . c 0 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shll.l erd 1 0 3 0 erd 1 notes the shll instruction differs from the shal instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 215 of 320 2.2.59 (6) shll (l) shll (shift logical left) shift logical operation erd (left logical shift) ? erd assembly-language format shll.l #2, erd operand size longword condition code i ? ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 30. description this instruction shifts the bits in a 32-bit register erd (destination operand) two bits to the left. bit 30 shifts into the carry flag. bits 0 and 1 are cleared to 0. lsb msb b31 b0 . . . . c 0 b30 b1 0 0 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shll.l #2, erd 1 0 7 0 erd 1 notes the shll instruction differs from the shal instruction in its effect on the overflow flag.
rev. 3.0, 07/00, page 216 of 320 2.2.60 (1) shlr (b) shlr (shift logical right) shift logical operation rd (right logical shift) ? rd assembly-language format shlr.b rd operand size byte condition code i ? ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction shifts the bits in an 8-bit register rd (destination operand) one bit to the right. the least significant bit (bit 0) shifts into the carry flag. the most significant bit (bit 7) is cleared to 0. . . . . . . lsb msb b7 b0 0 . . . . . . c available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shlr.b rd 1 1 0 rd 1 notes
rev. 3.0, 07/00, page 217 of 320 2.2.60 (2) shlr (b) shlr (shift logical right) shift logical operation rd (right logical shift) ? rd assembly-language format shlr.b #2, rd operand size byte condition code i ? ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction shifts the bits in an 8-bit register rd (destination operand) two bits to the right. bit 1 shifts into the carry flag. bits 7 and 6 are cleared to 0. . . . . . . lsb msb b7 b0 0 . . . . . . c b6 b1 00 available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shlr.b #2, rd 1 1 4 rd 1 notes
rev. 3.0, 07/00, page 218 of 320 2.2.60 (3) shlr (w) shlr (shift logical right) shift logical operation rd (right logical shift) ? rd assembly-language format shlr.w rd operand size word condition code i ? ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction shifts the bits in a 16-bit register rd (destination operand) one bit to the right. the least significant bit (bit 0) shifts into the carry flag. the most significant bit (bit 15) is cleared to 0. . . . . . . lsb msb b15 b0 0 . . . . . . c available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shlr.w rd 1 1 1 rd 1 notes
rev. 3.0, 07/00, page 219 of 320 2.2.60 (4) shlr (w) shlr (shift logical right) shift logical operation rd (right logical shift) ? rd assembly-language format shlr.w #2, rd operand size word condition code i ? ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction shifts the bits in a 16-bit register rd (destination operand) two bits to the right. bit 1 shifts into the carry flag. bits 15 and 14 are cleared to 0. . . . . . . lsb msb b15 b0 0 . . . . . . c b14 b1 00 available registers rd: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shlr.w #2, rd 1 1 5 rd 1 notes
rev. 3.0, 07/00, page 220 of 320 2.2.60 (5) shlr (l) shlr (shift logical right) shift logical operation erd (right logical shift) ? erd assembly-language format shlr.l erd operand size longword condition code i ? ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 0. description this instruction shifts the bits in a 32-bit register erd (destination operand) one bit to the right. the least significant bit (bit 0) shifts into the carry flag. the most significant bit (bit 31) is cleared to 0. . . . . . . lsb msb b31 b0 0 . . . . . . c available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shlr.l erd 1 1 3 0 erd 1 notes
rev. 3.0, 07/00, page 221 of 320 2.2.60 (6) shlr (l) shlr (shift logical right) shift logical operation erd (right logical shift) ? erd assembly-language format shlr.l #2, erd operand size longword condition code i ? ? 0 0 uihunzvc h: previous value remains unchanged. n: always cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: receives the previous value in bit 1. description this instruction shifts the bits in a 32-bit register erd (destination operand) two bits to the right. bit 1 shifts into the carry flag. bits 31 and 30 are cleared to 0. . . . . . . lsb msb b31 b0 0 . . . . . . c b30 b1 00 available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct shlr.l #2, erd 1 1 7 0 erd 1 notes
rev. 3.0, 07/00, page 222 of 320 2.2.61 sleep sleep (sleep) power-down mode operation program execution state ? power-down mode assembly-language format sleep operand size condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description when the sleep instruction is executed, the cpu enters a power-down mode. its internal state remains unchanged, but the cpu stops executing instructions and waits for an exception-handling request. when it receives an exception-handling request, the cpu exits the power-down mode and begins the exception-handling sequence. interrupt requests other than nmi cannot end the power- down mode if they are masked in the cpu. available registers operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states sleep 0180 2 notes for information about power-down modes, see the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 223 of 320 2.2.62 (1) stc (b) stc (store from control register) store ccr operation ccr ? rd assembly-language format stc.b ccr, rd operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction copies the ccr contents to an 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct stc.b ccr, rd 0 2 0 rd 1 notes
rev. 3.0, 07/00, page 224 of 320 2.2.62 (2) stc (b) stc (store from control register) store exr operation exr ? rd assembly-language format stc.b exr, rd operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction copies the exr contents to an 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct stc.b exr, rd 0 2 1 rd 1 notes
rev. 3.0, 07/00, page 225 of 320 2.2.62 (3) stc (w) stc (store from control register) store ccr operation ccr ? (ead) assembly-language format stc.w ccr, operand size word condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction copies the ccr contents to a destination location. although ccr is a byte register, the destination operand is a word operand. the ccr contents are stored at the even address. undetermined data is stored at the odd address. available registers erd: er0 to er7
rev. 3.0, 07/00, page 226 of 320 stc (store from control register) store ccr operand format and number of states required for execution notes addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte states stc.w ccr, @erd 0140691erd0 3 stc.w ccr, @(d:16, erd) 01406f1erd0 disp 4 stc.w ccr, @(d:32, erd) 0140780erd06ba0 disp 6 stc.w ccr, @Cerd 01406d1erd0 4 stc.w ccr, @aa:16 01406b80 abs 4 stc.w ccr, @aa:32 01406ba0 abs 5 register indirect register indirect with displace- ment register indirect with pre- decrement absolute address
rev. 3.0, 07/00, page 227 of 320 2.2.62 (4) stc (w) stc (store from control register) store exr operation exr ? (ead) assembly-language format stc.w exr, operand size word condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction copies the exr contents to a destination location. although exr is a byte register, the destination operand is a word operand. the exr contents are stored at the even address. undetermined data is stored at the odd address. available registers erd: er0 to er7
rev. 3.0, 07/00, page 228 of 320 stc (store from control register) store exr operand format and number of states required for execution notes addressing mnemonic operands instruction format no. of mode 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte states stc.w exr, @erd 0141691erd0 3 stc.w exr, @(d:16, erd) 01416f1erd0 disp 4 stc.w exr, @(d:32, erd) 0141780erd06ba0 disp 6 stc.w exr, @Cerd 01416d1erd0 4 stc.w exr, @aa:16 01416b80 abs 4 stc.w exr, @aa:32 01416ba0 abs 5 register indirect register indirect with displace- ment register indirect with pre- decrement absolute address
rev. 3.0, 07/00, page 229 of 320 2.2.63 stm stm (store from multiple registers) store data on stack operation ern (register list) ? @Csp assembly-language format stm.l , @Csp operand size longword condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction saves a group of registers specified by a register list onto the stack. the registers are saved in ascending order of register number. two, three, or four registers can be saved by one stm instruction. the following ranges can be specified in the register list. two registers: er0-er1, er2-er3, er4-er5, or er6-er7 three registers: er0-er2 or er4-er6 four registers: er0-er3 or er4-er7 available registers ern: er0 to er7
rev. 3.0, 07/00, page 230 of 320 stm (store from multiple registers) store data on stack operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states stm.l (ernCern+1), @Csp 01106df0ern7 stm.l (ernCern+2), @Csp 01206df0ern9 stm.l (ernCern+3), @Csp 01306df0ern11 notes when er7 is saved, the value after effective address calculation (after er7 is decremented by 4) is saved on the stack.
rev. 3.0, 07/00, page 231 of 320 2.2.64 stmac stmac (store from mac register) store data from mac register operation mach ? erd or macl ? erd assembly-language format stmac mac register, erd operand size longword condition code i ? ? ? *** uihunzvc h: previous value remains unchanged. n: set to 1 if a mac instruction resulted in a negative mac register value; otherwise cleared to 0. z: set to 1 if a mac instruction resulted in a zero mac register value; otherwise cleared to 0. v: set to 1 if a mac instruction resulted in an overflow; otherwise cleared to 0. c: previous value remains unchanged. note: * execution of this instruction copies the n, z, and v flag values from the multiplier to the condition-code register (ccr). if the stmac instruction is executed after a clrmac or ldmac instruction with no intervening mac instruction, the v flag will be 0 and the n and z flags will have undetermined values. description this instruction moves the contents of a multiply-accumulate register (mach or macl) to a general register. if the transfer is from mach, the upper 22 bits transferred to the general register are a sign extension. this instruction is supported by the h8s/2600 cpu only. available registers erd: er0 to er7
rev. 3.0, 07/00, page 232 of 320 stmac (store from mac register) store data from mac register operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct stmac mach, erd 0 2 2 0 ers 1 * register direct stmac macl, erd 0 2 3 0 ers 1 * note: * a maximum of three additional states are required for execution of this instruction within three states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between the mac instruction and this instruction, this instruction will be two states longer. notes
rev. 3.0, 07/00, page 233 of 320 2.2.65 (1) sub (b) sub (subtract binary) subtract binary operation rd C rs ? rd assembly-language format sub.b rs, rd operand size byte condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 3; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 7; otherwise cleared to 0. description this instruction subtracts the contents of an 8-bit register rs (source operand) from the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct sub.b rs, rd 1 8 rs rd 1
rev. 3.0, 07/00, page 234 of 320 sub (subtract binary) subtract binary notes the sub.b instruction can operate only on general registers. immediate data can be subtracted from general register contents by using the subx instruction. before executing subx #xx:8, rd, first set the z flag to 1 and clear the c flag to 0. the following coding examples can also be used to subtract nonzero immediate data #imm. (1) orc #h'05,ccr subx #(imm-1),rd (2) add #(0-imm),rd xorc #h'01,ccr
rev. 3.0, 07/00, page 235 of 320 2.2.65 (2) sub (w) sub (subtract binary) subtract binary operation rd C (eas) ? rd assembly-language format sub.w , rd operand size word condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 11; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 15; otherwise cleared to 0. description this instruction subtracts a source operand from the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate sub.w #xx:16, rd 7 9 3 rd imm 2 register direct sub.w rs, rd 1 9 rs rd 1 notes
rev. 3.0, 07/00, page 236 of 320 2.2.65 (3) sub (l) sub (subtract binary) subtract binary operation erd C (eas) ? erd assembly-language format sub.l , erd operand size longword condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 27; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 31; otherwise cleared to 0. description this instruction subtracts a source operand from the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte no. of states immediate sub.l #xx:32, erd 7 a 3 0 erd imm 3 register direct sub.l ers, erd 1 a 1 ers 0 erd 1 notes
rev. 3.0, 07/00, page 237 of 320 2.2.66 subs subs (subtract with sign extension) subtract binary address data operation rd C 1 ? erd rd C 2 ? erd rd C 4 ? erd assembly-language format subs #1, erd subs #2, erd subs #4, erd operand size longword condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction subtracts the immediate value 1, 2, or 4 from the contents of a 32-bit register erd (destination operand). unlike the sub instruction, it does not affect the condition-code flags. available registers erd: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct subs #1, erd 1 b 0 0 erd 1 register direct subs #2, erd 1 b 8 0 erd 1 register direct subs #4, erd 1 b 9 0 erd 1 notes
rev. 3.0, 07/00, page 238 of 320 2.2.67 subx subx (subtract with extend carry) subtract with borrow operation rd C (eas) C c ? rd assembly-language format subx < eas>, rd operand size byte condition code i ? ? ? ? ? uihunzvc h: set to 1 if there is a borrow at bit 3; otherwise cleared to 0. n: set to 1 if the result is negative; otherwise cleared to 0. z: previous value remains unchanged when the result is zero; otherwise cleared to 0. v: set to 1 if an overflow occurs; otherwise cleared to 0. c: set to 1 if there is a borrow at bit 7; otherwise cleared to 0. description this instruction subtracts the source operand and carry flag from the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate subx #xx:8, rd b rd imm 1 register direct subx rs, rd 1 e rs rd 1 notes
rev. 3.0, 07/00, page 239 of 320 2.2.68 tas tas (test and set) test and set operation @erd C 0 ? set/clear ccr 1 ? ( of @erd) assembly-language format tas @erd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction tests a memory operand by comparing it with zero, and sets the condition-code register according to the result. then it sets the most significant bit (bit 7) of the operand to 1. available registers erd: er0, er1, er4, er5 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register indirect tas @erd 0 1 e 0 7 b 0 erd c 4 notes
rev. 3.0, 07/00, page 240 of 320 2.2.69 trapa trapa (trap always) trap unconditionally operation when exr is invalid pc ? @Csp ccr ? @Csp ? pc when exr is valid pc ? @Csp ccr ? @Csp exr ? @Csp ? pc assembly-language format trapa #x:2 operand size condition code i * 1 uihunzvc i: always set to 1. ui: see note. h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. note: * the ui bit is set to 1 when used as an interrupt mask bit, but retains its previous value when used as a user bit. for details, see the relevant microcontroller hardware manual. description this instruction pushes the program counter (pc) and condition-code register (ccr) onto the stack, then sets the i bit to 1. if the extended control register (exr) is valid, exr is also saved onto the stack, but bits i2 to i0 are not modified. next execution branches to a new address given by the contents of the vector address corresponding to the specified vector number. the pc value pushed onto the stack is the starting address of the next instruction after the trapa instruction. vector address #x normal mode advanced mode 0 h'0010 to h'0011 h'000020 to h'000023 1 h'0012 to h'0013 h'000024 to h'000027 2 h'0014 to h'0015 h'000028 to h'00002b 3 h'0016 to h'0017 h'00002c to h'00002f
rev. 3.0, 07/00, page 241 of 320 trapa (trap always) trap unconditionally operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states register direct trapa #x:2 5 7 00 imm 0 7 * note: * eight states when exr is valid. notes the stack and vector structure differ between normal mode and advanced mode, and depending on whether exr is valid or invalid.
rev. 3.0, 07/00, page 242 of 320 2.2.70 (1) xor (b) xor (exclusive or logical) exclusive logical or operation rd ? (eas) ? rd assembly-language format xor.b < eas>, rd operand size byte condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction exclusively ors the source operand with the contents of an 8-bit register rd (destination operand) and stores the result in the 8-bit register rd. available registers rd: r0l to r7l, r0h to r7h rs: r0l to r7l, r0h to r7h operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate xor.b #xx:8, rd d rd imm 1 register direct xor.b rs, rd 1 5 rs rd 1 notes
rev. 3.0, 07/00, page 243 of 320 2.2.70 (2) xor (w) xor (exclusive or logical) exclusive logical or operation rd ? (eas) ? rd assembly-language format xor.w < eas>, rd operand size word condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction exclusively ors the source operand with the contents of a 16-bit register rd (destination operand) and stores the result in the 16-bit register rd. available registers rd: r0 to r7, e0 to e7 rs: r0 to r7, e0 to e7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate xor.w #xx:16, rd 7 9 5 rd imm 2 register direct xor.w rs, rd 6 5 rs rd 1 notes
rev. 3.0, 07/00, page 244 of 320 2.2.70 (3) xor (l) xor (exclusive or logical) exclusive logical or operation erd ? (eas) ? erd assembly-language format xor.l < eas>, erd operand size longword condition code i ? ? 0 uihunzvc h: previous value remains unchanged. n: set to 1 if the result is negative; otherwise cleared to 0. z: set to 1 if the result is zero; otherwise cleared to 0. v: always cleared to 0. c: previous value remains unchanged. description this instruction exclusively ors the source operand with the contents of a 32-bit register erd (destination operand) and stores the result in the 32-bit register erd. available registers erd: er0 to er7 ers: er0 to er7 operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte no. of states immediate xor.l #xx:32, erd 7 a 5 0 erd imm 3 register direct xor.l ers, erd 0 1 f 0 6 5 0 ers 0 erd 2 notes
rev. 3.0, 07/00, page 245 of 320 2.2.71 (1) xorc xorc (exclusive or control register) exclusive logical or with ccr operation ccr ? #imm ? ccr assembly-language format xorc #xx:8, ccr operand size byte condition code i ? ? ? ? ? ? ? ? uihunzvc i: stores the corresponding bit of the result. ui: stores the corresponding bit of the result. h: stores the corresponding bit of the result. u: stores the corresponding bit of the result. n: stores the corresponding bit of the result. z: stores the corresponding bit of the result. v: stores the corresponding bit of the result. c: stores the corresponding bit of the result. description this instruction exclusively ors the contents of the condition-code register (ccr) with immediate data and stores the result in the condition-code register. no interrupt requests, including nmi, are accepted immediately after execution of this instruction. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate xorc #xx:8, ccr 0 5 imm 1 notes
rev. 3.0, 07/00, page 246 of 320 2.2.71 (2) xorc xorc (exclusive or control register) exclusive logical or with exr operation exr ? #imm ? exr assembly-language format xorc #xx:8, exr operand size byte condition code i uihunzvc h: previous value remains unchanged. n: previous value remains unchanged. z: previous value remains unchanged. v: previous value remains unchanged. c: previous value remains unchanged. description this instruction exclusively ors the contents of the extended control register (exr) with immediate data and stores the result in the extended control register. no interrupt requests, including nmi, are accepted for three states after execution of this instruction. operand format and number of states required for execution instruction format addressing mode mnemonic operands 1st byte 2nd byte 3rd byte 4th byte no. of states immediate xorc#xx:8, exr014105 imm 2 notes
rev. 3.0, 07/00, page 247 of 320 2.3 instruction set table 2.1 instruction set (1) data transfer instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mov mov.b #xx:8,rd b 2 #xx:8 ? rd8 0 1 mov.b rs,rd b 2 rs8 ? rd8 0 1 mov.b @ers,rd b 2 @ers ? rd8 0 2 mov.b @(d:16, ers), rd b 4 @(d:16,ers) ? rd8 0 3 mov.b @(d:32,ers),rd b 8 @(d:32,ers) ? rd8 0 5 mov.b @ers+,rd b 2 @ers ? rd8,ers32+1 ? ers32 0 3 mov.b @aa:8,rd b 2 @aa:8 ? rd8 0 2 mov.b @aa:16,rd b 4 @aa:16 ? rd8 0 3 mov.b @aa:32,rd b 6 @aa:32 ? rd8 0 4 mov.b rs,@erd b 2 rs8 ? @erd 0 2 mov.b rs,@(d:16,erd) b 4 rd8 ? @(d:16,erd) 0 3 mov.b rs,@(d:32,erd) b 8 rd8 ? @(d:32,erd) 0 5 mov.b rs,@Cerd b 2 erd32C1 ? erd32,rs8 ? @erd 0 3 mov.b rs,@aa:8 b 2 rs8 ? @aa:8 0 2 mov.b rs,@aa:16 b 4 rs8 ? @aa:16 0 3 mov.b rs,@aa:32 b 6 rs8 ? @aa:32 0 4 mov.w #xx:16,rd w 4 #xx:16 ? rd16 0 2 mov.w rs,rd w 2 rs16 ? rd16 0 1 mov.w @ers,rd w 2 @ers ? rd16 0 2 mov.w @(d:16,ers),rd w 4 @(d:16,ers) ? rd16 0 3 mov.w @(d:32,ers),rd w 8 @(d:32,ers) ? rd16 0 5 mov.w @ers+,rd w 2 @ers ? rd16,ers32+2 ? @ers32 0 3 mov.w @aa:16,rd w 4 @aa:16 ? rd16 0 3 mov.w @aa:32,rd w 6 @aa:32 ? rd16 0 4 mov.w rs,@erd w 2 rs16 ? @erd 0 2 mov.w rs,@(d:16,erd) w 4 rs16 ? @(d:16,erd) 0 3 mov.w rs,@(d:32,erd) w 8 rs16 ? @(d:32,erd) 0 5 mov.w rs,@Cerd w 2 erd32C2 ? erd32,rs16 ? @erd 0 3 mov.w rs,@aa:16 w 4 rs16 ? @aa:16 0 3 mov.w rs,@aa:32 w 6 rs16 ? @aa:32 0 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 248 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mov mov.l #xx:32,erd l 6 #xx:32 ? erd32 0 3 mov.l ers,erd l 2 ers32 ? erd32 0 1 mov.l @ers,erd l 4 @ers ? erd32 0 4 mov.l @(d:16,ers),erd l 6 @(d:16,ers) ? erd32 0 5 mov.l @(d:32,ers),erd l 10 @(d:32,ers) ? erd32 0 7 mov.l @ers+,erd l 4 @ers ? erd32,ers32+4 ? @ers32 0 5 mov.l @aa:16,erd l 6 @aa:16 ? erd32 0 5 mov.l @aa:32,erd l 8 @aa:32 ? erd32 0 6 mov.l ers,@erd l 4 ers32 ? @erd 0 4 mov.l ers,@(d:16,erd) l 6 ers32 ? @(d:16,erd) 0 5 mov.l ers,@(d:32,erd) l 10 ers32 ? @(d:32,erd) 0 7 mov.l ers,@Cerd l 4 erd32C4 ? erd32,ers32 ? @erd 0 5 mov.l ers,@aa:16 l 6 ers32 ? @aa:16 0 5 mov.l ers,@aa:32 l 8 ers32 ? @aa:32 0 6 pop pop.w rn w 2 @sp ? rn16,sp+2 ? sp 0 3 pop.l ern l 4 @sp ? ern32,sp+4 ? sp 0 5 push push.w rn w 2 spC2 ? sp,rn16 ? @sp 0 3 push.l ern l 4 spC4 ? sp,ern32 ? @sp 0 5 ldm ldm.l @sp+,(ermCern) l 4 (@sp ? ern32,sp+4 ? sp) repeated for 7/9/11 * 3 each register restored stm stm.l (ermCern),@Csp l 4 (spC4 ? sp,ern32 ? @sp) repeated for 7/9/11 * 3 each register saved movfpe movfpe@aa:16,rd b 4 @aa:16 ? rd (synchronized with 0 (1) e clock) movtpe movtpe rs,@aa:16 b 4 rs ? @aa:16 (synchronized with 0 (1) e clock) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 249 of 320 (2) arithmetic operation instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa add add.b #xx:8,rd b 2 rd8+#xx:8 ? rd8 1 add.b rs,rd b 2 rd8+rs8 ? rd8 1 add.w #xx:16,rd w 4 rd16+#xx:16 ? rd16 (2) 2 add.w rs,rd w 2 rd16+rs16 ? rd16 (2) 1 add.l #xx:32,erd l 6 erd32+#xx:32 ? erd32 (3) 3 add.l ers,erd l 2 erd32+ers32 ? erd32 (3) 1 addx addx #xx:8,rd b 2 rd8+#xx:8+c ? rd8 (4) 1 addx rs,rd b 2 rd8+rs8+c ? rd8 (4) 1 adds adds #1,erd l 2 erd32+1 ? erd32 1 adds #2,erd l 2 erd32+2 ? erd32 1 adds #4,erd l 2 erd32+4 ? erd32 1 inc inc.b rd b 2 rd8+1 ? rd8 1 inc.w #1,rd w 2 rd16+1 ? rd16 1 inc.w #2,rd w 2 rd16+2 ? rd16 1 inc.l #1,erd l 2 erd32+1 ? erd32 1 inc.l #2,erd l 2 erd32+2 ? erd32 1 daa daa rd b 2 rd8 decimal adjust ? rd8 ** 1 sub sub.b rs,rd b 2 rd8Crs8 ? rd8 1 sub.w #xx:16,rd w 4 rd16C#xx:16 ? rd16 (2) 2 sub.w rs,rd w 2 rd16Crs16 ? rd16 (2) 1 sub.l #xx:32,erd l 6 erd32C#xx:32 ? erd32 (3) 3 sub.l ers,erd l 2 erd32Cers32 ? erd32 (3) 1 subx subx #xx:8,rd b 2 rd8C#xx:8Cc ? rd8 (4) 1 subx rs,rd b 2 rd8Crs8Cc ? rd8 (4) 1 subs subs #1,erd l 2 erd32C1 ? erd32 1 subs #2,erd l 2 erd32C2 ? erd32 1 subs #4,erd l 2 erd32C4 ? erd32 1 dec dec.b rd b 2 rd8C1 ? rd8 1 dec.w #1,rd w 2 rd16C1 ? rd16 1 dec.w #2,rd w 2 rd16C2 ? rd16 1 dec.l #1,erd l 2 erd32C1 ? erd32 1 dec.l #2,erd l 2 erd32C2 ? erd32 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 250 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa das das rd b 2 rd8 decimal adjust ? rd8 ** 1 mulxu mulxu.b rs,rd b 2 rd8 rs8 ? rd16 3 (12 * 7 ) * 4 (unsigned multiplication) mulxu.w rs,erd w 2 rd16 rs16 ? erd32 4 (20 * 7 ) * 4 (unsigned multiplication) mulxs mulxs.b rs,rd b 4 rd8 rs8 ? rd16 4 (13 * 7 ) * 5 (signed multiplication) mulxs.w rs,erd w 4 rd16 rs16 ? erd32 5 (21 * 7 ) * 5 (signed multiplication) divxu divxu.b rs,rd b 2 rd16rs8 ? rd16 (rdh: remainder, (5) (6) 12 rdl: quotient) (unsigned division) divxu.w rs,erd w 2 erd32rs16 ? erd32 (ed: remainder, (5) (6) 20 rd: quotient) (unsigned division) divxs divxs.b rs,rd b 4 rd16rs8 ? rd16 (rdh: remainder, (7) (6) 13 rdl: quotient) (signed division) divxs.w rs,erd w 4 erd32rs16 ? erd32 (ed: remainder, (7) (6) 21 rd: quotient) (signed division) cmp cmp.b #xx:8,rd b 2 rd8C#xx:8 1 cmp.b rs,rd b 2 rd8Crs8 1 cmp.w #xx:16,rd w 4 rd16C#xx:16 (2) 2 cmp.w rs,rd w 2 rd16Crs16 (2) 1 cmp.l #xx:32,erd l 6 erd32C#xx:32 (3) 3 cmp.l ers,erd l 2 erd32Cers32 (3) 1 neg neg.b rd b 2 0Crd8 ? rd8 1 neg.w rd w 2 0Crd16 ? rd16 1 neg.l erd l 2 0Cerd32 ? erd32 1 extu extu.w rd w 2 0 ? ( of rd16) 0 0 1 extu.l erd l 2 0 ? ( of erd32) 0 0 1 exts exts.w rd w 2 ( of rd16) ? ( 0 1 of rd16) exts.l erd l 2 ( of erd32) ? ( 0 1 of erd32) tas tas @erd * 8 b 4 @erdC0 ? set ccr, 1 ? ( of 0 4 @erd) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 251 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mac * 9 mac @ern+,@erm+ 4 @ern @erm+mac ? mac (signed 4 multiplication) (8) (8) (8) ern+2 ? ern,erm+2 ? erm clrmac * 9 clrmac 2 0 ? mach, macl 2 * 6 ldmac * 9 ldmac ers,mach l 2 ers ? mach 2 * 6 ldmac ers,macl l 2 ers ? macl 2 * 6 stmac * 9 stmac mach,erd l 2 mach ? erd 1 * 6 stmac macl,erd l 2 macl ? erd 1 * 6 ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 252 of 320 (3) logic operation instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa and and.b #xx:8,rd b 2 rd8 #xx:8 ? rd8 0 1 and.b rs,rd b 2 rd8 rs8 ? rd8 0 1 and.w #xx:16,rd w 4 rd16 #xx:16 ? rd16 0 2 and.w rs,rd w 2 rd16 rs16 ? rd16 0 1 and.l #xx:32,erd l 6 erd32 #xx:32 ? erd32 0 3 and.l ers,erd l 4 erd32 ers32 ? erd32 0 2 or or.b #xx:8,rd b 2 rd8 #xx:8 ? rd8 0 1 or.b rs,rd b 2 rd8 rs8 ? rd8 0 1 or.w #xx:16,rd w 4 rd16 #xx:16 ? rd16 0 2 or.w rs,rd w 2 rd16 rs16 ? rd16 0 1 or.l #xx:32,erd l 6 erd32 #xx:32 ? erd32 0 3 or.l ers,erd l 4 erd32 ers32 ? erd32 0 2 xor xor.b #xx:8,rd b 2 rd8 ? #xx:8 ? rd8 0 1 xor.b rs,rd b 2 rd8 ? rs8 ? rd8 0 1 xor.w #xx:16,rd w 4 rd16 ? #xx:16 ? rd16 0 2 xor.w rs,rd w 2 rd16 ? rs16 ? rd16 0 1 xor.l #xx:32,erd l 6 erd32 ? #xx:32 ? erd32 0 3 xor.l ers,erd l 4 erd32 ? ers32 ? erd32 0 2 not not.b rd b 2 ? rd8 ? rd8 0 1 not.w rd w 2 ? rd16 ? rd16 0 1 not.l erd l 2 ? rd32 ? rd32 0 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 253 of 320 (4) shift instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa shal shal.b rd b 2 1 shal.b #2,rd b 2 1 shal.w rd w 2 1 shal.w #2,rd w 2 1 shal.l erd l 2 1 shal.l #2,erd l 2 1 shar shar.b rd b 2 0 1 shar.b #2,rd b 2 0 1 shar.w rd w 2 0 1 shar.w #2,rd w 2 0 1 shar.l erd l 2 0 1 shar.l #2,erd l 2 0 1 shll shll.b rd b 2 0 1 shll.b #2,rd b 2 0 1 shll.w rd w 2 0 1 shll.w #2,rd w 2 0 1 shll.l erd l 2 0 1 shll.l #2,erd l 2 0 1 shlr shlr.b rd b 2 0 0 1 shlr.b #2,rd b 2 0 0 1 shlr.w rd w 2 0 0 1 shlr.w #2,rd w 2 0 0 1 shlr.l erd l 2 0 0 1 shlr.l #2,erd l 2 0 0 1 rotxl rotxl.b rd b 2 0 1 rotxl.b #2,rd b 2 0 1 rotxl.w rd w 2 0 1 rotxl.w #2,rd w 2 0 1 rotxl.l erd l 2 0 1 rotxl.l #2,erd l 2 0 1 c msb lsb c msb lsb c msb lsb c 0 0 0 msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 254 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa rotxr rotxr.b rd b 2 0 1 rotxr.b #2,rd b 2 0 1 rotxr.w rd w 2 0 1 rotxr.w #2,rd w 2 0 1 rotxr.l erd l 2 0 1 rotxr.l #2,erd l 2 0 1 rotl rotl.b rd b 2 0 1 rotl.b #2,rd b 2 0 1 rotl.w rd w 2 0 1 rotl.w #2,rd w 2 0 1 rotl.l erd l 2 0 1 rotl.l #2,erd l 2 0 1 rotr rotr.b rd b 2 0 1 rotr.b #2,rd b 2 0 1 rotr.w rd w 2 0 1 rotr.w #2,rd w 2 0 1 rotr.l erd l 2 0 1 rotr.l #2,erd l 2 0 1 c msb lsb c msb lsb c msb lsb ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 255 of 320 (5) bit manipulation instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa bset bset #xx:3,rd b 2 (#xx:3 of rd8) ? 1 1 bset #xx:3,@erd b 4 (#xx:3 of @erd) ? 1 4 bset #xx:3,@aa:8 b 4 (#xx:3 of @aa:8) ? 1 4 bset #xx:3,@aa:16 b 6 (#xx:3 of @aa:16) ? 1 5 bset #xx:3,@aa:32 b 8 (#xx:3 of @aa:32) ? 1 6 bset rn,rd b 2 (rn8 of rd8) ? 1 1 bset rn,@erd b 4 (rn8 of @erd) ? 1 4 bset rn,@aa:8 b 4 (rn8 of @aa:8) ? 1 4 bset rn,@aa:16 b 6 (rn8 of @aa:16) ? 1 5 bset rn,@aa:32 b 8 (rn8 of @aa:32) ? 1 6 bclr bclr #xx:3,rd b 2 (#xx:3 of rd8) ? 0 1 bclr #xx:3,@erd b 4 (#xx:3 of @erd) ? 0 4 bclr #xx:3,@aa:8 b 4 (#xx:3 of @aa:8) ? 0 4 bclr #xx:3,@aa:16 b 6 (#xx:3 of @aa:16) ? 0 5 bclr #xx:3,@aa:32 b 8 (#xx:3 of @aa:32) ? 0 6 bclr rn,rd b 2 (rn8 of rd8) ? 0 1 bclr rn,@erd b 4 (rn8 of @erd) ? 0 4 bclr rn,@aa:8 b 4 (rn8 of @aa:8) ? 0 4 bclr rn,@aa:16 b 6 (rn8 of @aa:16) ? 0 5 bclr rn,@aa:32 b 8 (rn8 of @aa:32) ? 0 6 bnot bnot #xx:3,rd b 2 (#xx:3 of rd8) ? [ ? (#xx:3 of rd8)] 1 bnot #xx:3,@erd b 4 (#xx:3 of @erd) ? [ ? (#xx:3 of @erd)] 4 bnot #xx:3,@aa:8 b 4 (#xx:3 of @aa:8) ? [ ? (#xx:3 of @aa:8)] 4 bnot #xx:3,@aa:16 b 6 (#xx:3 of @aa:16) ? [ ? (#xx:3 of @aa:16)] 5 bnot #xx:3,@aa:32 b 8 (#xx:3 of @aa:32) ? [ ? (#xx:3 of @aa:32)] 6 bnot rn,rd b 2 (rn8 of rd8) ? [ ? (rn8 of rd8)] 1 bnot rn,@erd b 4 (rn8 of @erd) ? [ ? (rn8 of @erd)] 4 bnot rn,@aa:8 b 4 (rn8 of @aa:8) ? [ ? (rn8 of @aa:8)] 4 bnot rn,@aa:16 b 6 (rn8 of @aa:16) ? [ ? (rn8 of @aa:16)] 5 bnot rn,@aa:32 b 8 (rn8 of @aa:32) ? [ ? (rn8 of @aa:32)] 6 no. of states * 1 normal advanced
rev. 3.0, 07/00, page 256 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa btst btst #xx:3,rd b 2 (#xx:3 of rd8) ? z1 btst #xx:3,@erd b 4 (#xx:3 of @erd) ? z3 btst #xx:3,@aa:8 b 4 (#xx:3 of @aa:8) ? z3 btst #xx:3,@aa:16 b 6 (#xx:3 of @aa:16) ? z4 btst #xx:3,@aa:32 b 8 (#xx:3 of @aa:32) ? z5 btst rn,rd b 2 (rn8 of rd8) ? z1 btst rn,@erd b 4 (rn8 of @erd) ? z3 btst rn,@aa:8 b 4 (rn8 of @aa:8) ? z3 btst rn,@aa:16 b 6 (rn8 of @aa:16) ? z4 btst rn,@aa:32 b 8 (rn8 of @aa:32) ? z5 bld bld #xx:3,rd b 2 (#xx:3 of rd8) ? c 1 bld #xx:3,@erd b 4 (#xx:3 of @erd) ? c 3 bld #xx:3,@aa:8 b 4 (#xx:3 of @aa:8) ? c 3 bld #xx:3,@aa:16 b 6 (#xx:3 of @aa:16) ? c 4 bld #xx:3,@aa:32 b 8 (#xx:3 of @aa:32) ? c 5 bild bild #xx:3,rd b 2 ? (#xx:3 of rd8) ? c 1 bild #xx:3,@erd b 4 ? (#xx:3 of @erd) ? c 3 bild #xx:3,@aa:8 b 4 ? (#xx:3 of @aa:8) ? c 3 bild #xx:3,@aa:16 b 6 ? (#xx:3 of @aa:16) ? c 4 bild #xx:3,@aa:32 b 8 ? (#xx:3 of @aa:32) ? c 5 bst bst #xx:3,rd b 2 c ? (#xx:3 of rd8) 1 bst #xx:3,@erd b 4 c ? (#xx:3 of @erd24) 4 bst #xx:3,@aa:8 b 4 c ? (#xx:3 of @aa:8) 4 bst #xx:3,@aa:16 b 6 c ? (#xx:3 of @aa:16) 5 bst #xx:3,@aa:32 b 8 c ? (#xx:3 of @aa:32) 6 bist bist #xx:3,rd b 2 ? c ? (#xx:3 of rd8) 1 bist #xx:3,@erd b 4 ? c ? (#xx:3 of @erd24) 4 bist #xx:3,@aa:8 b 4 ? c ? (#xx:3 of @aa:8) 4 bist #xx:3,@aa:16 b 6 ? c ? (#xx:3 of @aa:16) 5 bist #xx:3,@aa:32 b 8 ? c ? (#xx:3 of @aa:32) 6 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 257 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa band band #xx:3,rd b 2 c (#xx:3 of rd8) ? c 1 band #xx:3,@erd b 4 c (#xx:3 of @erd24) ? c 3 band #xx:3,@aa:8 b 4 c (#xx:3 of @aa:8) ? c 3 band #xx:3,@aa:16 b 6 c (#xx:3 of @aa:16) ? c 4 band #xx:3,@aa:32 b 8 c (#xx:3 of @aa:32) ? c 5 biand biand #xx:3,rd b 2 c [ ? (#xx:3 of rd8)] ? c 1 biand #xx:3,@erd b 4 c [ ? (#xx:3 of @erd24)] ? c 3 biand #xx:3,@aa:8 b 4 c [ ? (#xx:3 of @aa:8)] ? c 3 biand #xx:3,@aa:16 b 6 c [ ? (#xx:3 of @aa:16)] ? c 4 biand #xx:3,@aa:32 b 8 c [ ? (#xx:3 of @aa:32)] ? c 5 bor bor #xx:3,rd b 2 c (#xx:3 of rd8) ? c 1 bor #xx:3,@erd b 4 c (#xx:3 of @erd24) ? c 3 bor #xx:3,@aa:8 b 4 c (#xx3: of @aa:8) ? c 3 bor #xx:3,@aa:16 b 6 c (#xx3: of @aa:16) ? c 4 bor #xx:3,@aa:32 b 8 c (#xx3: of @aa:32) ? c 5 bior bior #xx:3,rd b 2 c [ ? (#xx:3 of rd8)] ? c 1 bior #xx:3,@erd b 4 c [ ? (#xx:3 of @erd24)] ? c 3 bior #xx:3,@aa:8 b 4 c [ ? (#xx:3 of @aa:8)] ? c 3 bior #xx:3,@aa:16 b 6 c [ ? (#xx:3 of @aa:16)] ? c 4 bior #xx:3,@aa:32 b 8 c [ ? (#xx:3 of @aa:32)] ? c 5 bxor bxor #xx:3,rd b 2 c ? (#xx:3 of rd8) ? c 1 bxor #xx:3,@erd b 4 c ? (#xx:3 of @erd24) ? c 3 bxor #xx:3,@aa:8 b 4 c ? (#xx:3 of @aa:8) ? c 3 bxor #xx:3,@aa:16 b 6 c ? (#xx:3 of @aa:16) ? c 4 bxor #xx:3,@aa:32 b 8 c ? (#xx:3 of @aa:32) ? c 5 bixor bixor #xx:3,rd b 2 c ?[ ? (#xx:3 of rd8)] ? c 1 bixor #xx:3,@erd b 4 c ?[ ? (#xx:3 of @erd24)] ? c 3 bixor #xx:3,@aa:8 b 4 c ?[ ? (#xx:3 of @aa:8)] ? c 3 bixor #xx:3,@aa:16 b 6 c ?[ ? (#xx:3 of @aa:16)] ? c 4 bixor #xx:3,@aa:32 b 8 c ?[ ? (#xx:3 of @aa:32)] ? c 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 258 of 320 (6) branch instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa bcc bra d:8(bt d:8) 2 if condition is true then always 2 bra d:16(bt d:16) 4 pc ? pc+d 3 brn d:8(bf d:8) 2 else next; never 2 brn d:16(bf d:16) 4 3 bhi d:8 2 c z=0 2 bhi d:16 4 3 bls d:8 2 c z=1 2 bls d:16 4 3 bcc d:8(bhs d:8) 2 c=0 2 bcc d:16(bhs d:16) 4 3 bcs d:8(blo d:8) 2 c=1 2 bcs d:16(blo d:16) 4 3 bne d:8 2 z=0 2 bne d:16 4 3 beq d:8 2 z=1 2 beq d:16 4 3 bvc d:8 2 v=0 2 bvc d:16 4 3 bvs d:8 2 v=1 2 bvs d:16 4 3 bpl d:8 2 n=0 2 bpl d:16 4 3 bmi d:8 2 n=1 2 bmi d:16 4 3 bge d:8 2 n ? v=0 2 bge d:16 4 3 blt d:8 2 n ? v=1 2 blt d:16 4 3 bgt d:8 2 z (n ? v)=0 2 bgt d:16 4 3 ble d:8 2 z (n ? v)=1 2 ble d:16 4 3 branch condition no. of states * 1 normal advanced
rev. 3.0, 07/00, page 259 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa jmp jmp @ern 2 pc ? ern 2 jmp @aa:24 4 pc ? aa:24 3 jmp @@aa:8 2 pc ? @aa:8 4 5 bsr bsr d:8 2 pc ? @Csp,pc ? pc+d:8 3 4 bsr d:16 4 pc ? @Csp,pc ? pc+d:16 4 5 jsr jsr @ern 2 pc ? @Csp,pc ? ern 3 4 jsr @aa:24 4 pc ? @Csp,pc ? aa:24 4 5 jsr @@aa:8 2 pc ? @Csp,pc ? aa:8 4 6 rts rts 2 pc ? @sp+ 4 5 branch condition no. of states * 1 normal advanced
rev. 3.0, 07/00, page 260 of 320 (7) system control instructions addressing mode and instruction length (bytes) mnemonic size operation condition code no. of states * 1 ihnzvc normal advanced #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa trapa trapa #x:2 2 pc ? @Csp,ccr ? @Csp, 1 7 (9) 8 (9) exr ? @Csp, ? pc rte rte exr ? @sp+,ccr ? @sp+, 5 (9) pc ? @sp+ sleep sleep transition to power-down state 2 ldc ldc #xx:8,ccr b 2 #xx:8 ? ccr 1 ldc #xx:8,exr b 4 #xx:8 ? exr 2 ldc rs,ccr b 2 rs8 ? ccr 1 ldc rs,exr b 2 rs8 ? exr 1 ldc @ers,ccr w 4 @ers ? ccr 3 ldc @ers,exr w 4 @ers ? exr 3 ldc @(d:16,ers),ccr w 6 @(d:16,ers) ? ccr 4 ldc @(d:16,ers),exr w 6 @(d:16,ers) ? exr 4 ldc @(d:32,ers),ccr w 10 @(d:32,ers) ? ccr 6 ldc @(d:32,ers),exr w 10 @(d:32,ers) ? exr 6 ldc @ers+,ccr w 4 @ers ? ccr,ers32+2 ? ers32 4 ldc @ers+,exr w 4 @ers ? exr,ers32+2 ? ers32 4 ldc @aa:16,ccr w 6 @aa:16 ? ccr 4 ldc @aa:16,exr w 6 @aa:16 ? exr 4 ldc @aa:32,ccr w 8 @aa:32 ? ccr 5 ldc @aa:32,exr w 8 @aa:32 ? exr 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
rev. 3.0, 07/00, page 261 of 320 addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa stc stc ccr,rd b 2 ccr ? rd8 1 stc exr,rd b 2 exr ? rd8 1 stc ccr,@erd w 4 ccr ? @erd 3 stc exr,@erd w 4 exr ? @erd 3 stc ccr,@(d:16,erd) w 6 ccr ? @(d:16,erd) 4 stc exr,@(d:16,erd) w 6 exr ? @(d:16,erd) 4 stc ccr,@(d:32,erd) w 10 ccr ? @(d:32,erd) 6 stc exr,@(d:32,erd) w 10 exr ? @(d:32,erd) 6 stc ccr,@Cerd w 4 erd32C2 ? erd32,ccr ? @erd 4 stc exr,@Cerd w 4 erd32C2 ? erd32,exr ? @erd 4 stc ccr,@aa:16 w 6 ccr ? @aa:16 4 stc exr,@aa:16 w 6 exr ? @aa:16 4 stc ccr,@aa:32 w 8 ccr ? @aa:32 5 stc exr,@aa:32 w 8 exr ? @aa:32 5 andc andc #xx:8,ccr b 2 ccr #xx:8 ? ccr 1 andc #xx:8,exr b 4 exr #xx:8 ? exr 2 orc orc #xx:8,ccr b 2 ccr #xx:8 ? ccr 1 orc #xx:8,exr b 4 exr #xx:8 ? exr 2 xorc xorc #xx:8,ccr b 2 ccr ? #xx:8 ? ccr 1 xorc #xx:8,exr b 4 exr ? #xx:8 ? exr 2 nop nop 2 pc ? pc+2 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? no. of states * 1 normal advanced
rev. 3.0, 07/00, page 262 of 320 (8) block transfer instructions addressing mode and instruction length (bytes) mnemonic size operation condition code ihnzvc #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa eepmov eepmov.b 4 if r4l 1 0 4+2n * 2 repeat @er5+ ? @er6+ er5+1 ? er5 er6+1 ? er6 r4lC1 ? r4l until r4l=0 else next; eepmov.w 4 if r4 1 0 4+2n * 2 repeat @er5+ ? @er6+ er5+1 ? er5 er6+1 ? er6 r4C1 ? 4 until r4=0 else next; no. of states * 1 normal advanced notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located i n on-chip memory. 2. n is the initial setting of r4l or r4. 3. seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. 4. one additional state is required for execution immediately after a mulxu, mulxs, or stmac instruction. also, a maximum of t hree additional states are required for execution of a mulxu instruction within three states after execution of a mac instruction. for example, if th ere is a one-state instruction (such as nop) between a mac instruction and a mulxu instruction, the mulxu instruction will be two states longer. 5. a maximum of two additional states are required for execution of a mulxs instruction within two states after execution of a mac instruction. for example, if there is a one-state instruction (such as nop) between a mac instruction and a mulxs instruction, the mulxs ins truction will be one state longer. 6. a maximum of three additional states are required for execution of one of these instructions within three states after execu tion of a mac instruction. for example, if there is a one-state instruction (such as nop) between a mac instruction and one of these instructions, that in struction will be two states longer. 7. for the h8s/2000 cpu. 8. only register er0, er1, er4, or er5 should be used when using the tas instruction. 9. these instructions are supported only by the h8s/2600 cpu. (1) the number of states required for execution of an instruction that transfers data in synchronization with the e clock is va riable. (2) set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. (3) set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. (4) retains its previous value when the result is zero; otherwise cleared to 0. (5) set to 1 when the divisor is negative; otherwise cleared to 0. (6) set to 1 when the divisor is zero; otherwise cleared to 0. (7) set to 1 when the quotient is negative; otherwise cleared to 0. (8) mac instruction results are indicated in the flags when the stmac instruction is executed. (9) one additional state is required for execution when exr is valid.
rev. 3.0, 07/00, page 263 of 320 2.4 instruction code table 2.2 instruction codes instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte add add.b #xx:8,rd b 8 rd imm add.b rs,rd b 0 8 rs rd add.w #xx:16,rd w 7 9 1 rd imm add.w rs,rd w 0 9 rs rd add.l #xx:32,erd l 7 a 1 0 erd imm add.l ers,erd l 0 a 1 ers 0 erd adds adds #1,erd l 0 b 0 0 erd adds #2,erd l 0 b 8 0 erd adds #4,erd l 0 b 9 0 erd addx addx #xx:8,rd b 9 rd imm addx rs,rd b 0 e rs rd and and.b #xx:8,rd b e rd imm and.b rs,rd b 1 6 rs rd and.w #xx:16,rd w 7 9 6 rd imm and.w rs,rd w 6 6 rs rd and.l #xx:32,erd l 7 a 6 0 erd imm and.l ers,erd l 0 1 f 0 6 6 0 ers 0 erd andc andc #xx:8,ccr b 0 6 imm andc #xx:8,exr b 014106 imm band band #xx:3,rd b 7 6 0 imm rd band #xx:3,@erd b 7 c 0 erd 0 7 6 0 imm 0 band #xx:3,@aa:8 b 7 e abs 7 6 0 imm 0 band #xx:3,@aa:16 b 6 a 1 0 abs 7 6 0 imm 0 band #xx:3,@aa:32 b 6 a 3 0 abs 7 6 0 imm 0 bcc bra d:8 (bt d:8) 4 0 disp bra d:16 (bt d:16) 5800 disp brn d:8 (bf d:8) 4 1 disp brn d:16 (bf d:16) 5810 disp bhi d:8 4 2 disp bhi d:16 5820 disp bls d:8 4 3 disp bls d:16 5830 disp bcc d:8 (bhs d:8) 4 4 disp
rev. 3.0, 07/00, page 264 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte bcc bcc d:16 (bhs d:16) 5840 disp bcs d:8 (blo d:8) 4 5 disp bcs d:16 (blo d:16) 5850 disp bne d:8 4 6 disp bne d:16 5860 disp beq d:8 4 7 disp beq d:16 5870 disp bvc d:8 4 8 disp bvc d:16 5880 disp bvs d:8 4 9 disp bvs d:16 5890 disp bpl d:8 4 a disp bpl d:16 5 8 a 0 disp bmi d:8 4 b disp bmi d:16 5 8 b 0 disp bge d:8 4 c disp bge d:16 5 8 c 0 disp blt d:8 4 d disp blt d:16 5 8 d 0 disp bgt d:8 4 e disp bgt d:16 5 8 e 0 disp ble d:8 4 f disp ble d:16 5 8 f 0 disp bclr bclr #xx:3,rd b 7 2 0 imm rd bclr #xx:3,@erd b 7 d 0 erd 0 7 2 0 imm 0 bclr #xx:3,@aa:8 b 7 f abs 7 2 0 imm 0 bclr #xx:3,@aa:16 b 6 a 1 8 abs 7 2 0 imm 0 bclr #xx:3,@aa:32 b 6 a 3 8 abs 7 2 0 imm 0 bclr rn,rd b 6 2 rn rd bclr rn,@erd b 7 d 0 erd 0 6 2 rn 0 bclr rn,@aa:8 b 7 f abs 6 2 rn 0 bclr rn,@aa:16 b 6 a 1 8 abs 6 2 rn 0 bclr rn,@aa:32 b 6 a 3 8 abs 6 2 rn 0
rev. 3.0, 07/00, page 265 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte biand biand #xx:3,rd b 7 6 1 imm rd biand #xx:3,@erd b 7 c 0 erd 0 7 6 1 imm 0 biand #xx:3,@aa:8 b 7 e abs 7 6 1 imm 0 biand #xx:3,@aa:16 b 6 a 1 0 abs 7 6 1 imm 0 biand #xx:3,@aa:32 b 6 a 3 0 abs 7 6 1 imm 0 bild bild #xx:3,rd b 7 7 1 imm rd bild #xx:3,@erd b 7 c 0 erd 0 7 7 1 imm 0 bild #xx:3,@aa:8 b 7 e abs 7 7 1 imm 0 bild #xx:3,@aa:16 b 6 a 1 0 abs 7 7 1 imm 0 bild #xx:3,@aa:32 b 6 a 3 0 abs 7 7 1 imm 0 bior bior #xx:3,rd b 7 4 1 imm rd bior #xx:3,@erd b 7 c 0 erd 0 7 4 1 imm 0 bior #xx:3,@aa:8 b 7 e abs 7 4 1 imm 0 bior #xx:3,@aa:16 b 6 a 1 0 abs 7 4 1 imm 0 bior #xx:3,@aa:32 b 6 a 3 0 abs 7 4 1 imm 0 bist bist #xx:3,rd b 6 7 1 imm rd bist #xx:3,@erd b 7 d 0 erd 0 6 7 1 imm 0 bist #xx:3,@aa:8 b 7 f abs 6 7 1 imm 0 bist #xx:3,@aa:16 b 6 a 1 8 abs 6 7 1 imm 0 bist #xx:3,@aa:32 b 6 a 3 8 abs 6 7 1 imm 0 bixor bixor #xx:3,rd b 7 5 1 imm rd bixor #xx:3,@erd b 7 c 0 erd 0 7 5 1 imm 0 bixor #xx:3,@aa:8 b 7 e abs 7 5 1 imm 0 bixor #xx:3,@aa:16 b 6 a 1 0 abs 7 5 1 imm 0 bixor #xx:3,@aa:32 b 6 a 3 0 abs 7 5 1 imm 0 bld bld #xx:3,rd b 7 7 0 imm rd bld #xx:3,@erd b 7 c 0 erd 0 7 7 0 imm 0 bld #xx:3,@aa:8 b 7 e abs 7 7 0 imm 0 bld #xx:3,@aa:16 b 6 a 1 0 abs 7 7 0 imm 0 bld #xx:3,@aa:32 b 6 a 3 0 abs 7 7 0 imm 0 bnot bnot #xx:3,rd b 7 1 0 imm rd bnot #xx:3,@erd b 7 d 0 erd 0 7 1 0 imm 0 bnot #xx:3,@aa:8 b 7 f abs 7 1 0 imm 0 bnot #xx:3,@aa:16 b 6 a 1 8 abs 7 1 0 imm 0 bnot #xx:3,@aa:32 b 6 a 3 8 abs 7 1 0 imm 0 bnot rn,rd b 6 1 rn rd
rev. 3.0, 07/00, page 266 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte bnot bnot rn,@erd b 7 d 0 erd 0 6 1 rn 0 bnot rn,@aa:8 b 7 f abs 6 1 rn 0 bnot rn,@aa:16 b 6 a 1 8 abs 6 1 rn 0 bnot rn,@aa:32 b 6 a 3 8 abs 6 1 rn 0 bor bor #xx:3,rd b 7 4 0 imm rd bor #xx:3,@erd b 7 c 0 erd 0 7 4 0 imm 0 bor #xx:3,@aa:8 b 7 e abs 7 4 0 imm 0 bor #xx:3,@aa:16 b 6 a 1 0 abs 7 4 0 imm 0 bor #xx:3,@aa:32 b 6 a 3 0 abs 7 4 0 imm 0 bset bset #xx:3,rd b 7 0 0 imm rd bset #xx:3,@erd b 7 d 0 erd 0 7 0 0 imm 0 bset #xx:3,@aa:8 b 7 f abs 7 0 0 imm 0 bset #xx:3,@aa:16 b 6 a 1 8 abs 7 0 0 imm 0 bset #xx:3,@aa:32 b 6 a 3 8 abs 7 0 0 imm 0 bset rn,rd b 6 0 rn rd bset rn,@erd b 7 d 0 erd 0 6 0 rn 0 bset rn,@aa:8 b 7 f abs 6 0 rn 0 bset rn,@aa:16 b 6 a 1 8 abs 6 0 rn 0 bset rn,@aa:32 b 6 a 3 8 abs 6 0 rn 0 bsr bsr d:8 5 5 disp bsr d:16 5 c 0 0 disp bst bst #xx:3,rd b 6 7 0 imm rd bst #xx:3,@erd b 7 d 0 erd 0 6 7 0 imm 0 bst #xx:3,@aa:8 b 7 f abs 6 7 0 imm 0 bst #xx:3,@aa:16 b 6 a 1 8 abs 6 7 0 imm 0 bst #xx:3,@aa:32 b 6 a 3 8 abs 6 7 0 imm 0 btst btst #xx:3,rd b 7 3 0 imm rd btst #xx:3,@erd b 7 c 0 erd 0 7 3 0 imm 0 btst #xx:3,@aa:8 b 7 e abs 7 3 0 imm 0 btst #xx:3,@aa:16 b 6 a 1 0 abs 7 3 0 imm 0 btst #xx:3,@aa:32 b 6 a 3 0 abs 7 3 0 imm 0 btst rn,rd b 6 3 rn rd btst rn,@erd b 7 c 0 erd 0 6 3 rn 0 btst rn,@aa:8 b 7 e abs 6 3 rn 0 btst rn,@aa:16 b 6 a 1 0 abs 6 3 rn 0 btst rn,@aa:32 b 6 a 3 0 abs 6 3 rn 0
rev. 3.0, 07/00, page 267 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte bxor bxor #xx:3,rd b 7 5 0 imm rd bxor #xx:3,@erd b 7 c 0 erd 0 7 5 0 imm 0 bxor #xx:3,@aa:8 b 7 e abs 7 5 0 imm 0 bxor #xx:3,@aa:16 b 6 a 1 0 abs 7 5 0 imm 0 bxor #xx:3,@aa:32 b 6 a 3 0 abs 7 5 0 imm 0 clrmac * 1 clrmac 0 1 a 0 cmp cmp.b #xx:8,rd b a rd imm cmp.b rs,rd b 1 c rs rd cmp.w #xx:16,rd w 7 9 2 rd imm cmp.w rd,rd w 1 d rs rd cmp.l #xx:32,erd l 7 a 2 0 erd imm cmp.l ers,erd l 1 f 1 ers 0 erd daa daa rd b 0 f 0 rd das das rd b 1 f 0 rd dec dec.b rd b 1 a 0 rd dec.w #1,rd w 1 b 5 rd dec.w #2,rd w 1 b d rd dec.l #1,erd l 1 b 7 0 erd dec.l #2,erd l 1 b f 0 erd divxs divxs.b rs,rd b 0 1 d 0 5 1 rs rd divxs.w rs,erd w 0 1 d 0 5 3 rs 0 erd divxu divxu.b rs,rd b 5 1 rs rd divxu.w rs,erd w 5 3 rs 0 erd eepmov eepmov.b 7 b 5 c 5 9 8 f eepmov.w 7 b d 4 5 9 8 f exts exts.w rd w 1 7 d rd exts.l erd l 1 7 f 0 erd extu extu.w rd w 1 7 5 rd extu.l erd l 1 7 7 0 erd inc inc.b rd b 0 a 0 rd inc.w #1,rd w 0 b 5 rd inc.w #2,rd w 0 b d rd inc.l #1,erd l 0 b 7 0 erd inc.l #2,erd l 0 b f 0 erd
rev. 3.0, 07/00, page 268 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte jmp jmp @ern 5 9 0 ern 0 jmp @aa:24 5 a abs jmp @aa:8 5 b abs jsr jsr @ern 5 d 0 ern 0 jsr @aa:24 5 e abs jsr @@aa:8 5 f abs ldc ldc #xx:8,ccr b 0 7 imm ldc #xx:8,exr b 014107 imm ldc rs,ccr b 0 3 0 rs ldc rs,exr b 0 3 1 rs ldc @ers,ccr w 0140690ers0 ldc @ers,exr w 0141690ers0 ldc @(d:16,ers),ccr w 01406f0ers0 disp ldc @(d:16,ers),exr w 01416f0ers0 disp ldc @(d:32,ers),ccr w 0140780ers0 6b20 disp ldc @(d:32,ers),exr w 0141780ers0 6b20 disp ldc @ers+,ccr w 01406d0ers0 ldc @ers+,exr w 01416d0ers0 ldc @aa:16,ccr w 01406b00 abs ldc @aa:16,exr w 01416b00 abs ldc @aa:32,ccr w 01406b20 abs ldc @aa:32,exr w 01416b20 abs ldm ldm.l @sp+,(ernCern+1) l 01106d70 ern+1 ldm.l @sp+,(ernCern+2) l 01206d70 ern+2 ldm.l @sp+,(ernCern+3) l 01306d70 ern+3 ldmac * 1 ldmac ers,mach l 0 3 2 0 ers ldmac ers,macl l 0 3 3 0 ers mac * 1 mac @ern+,@erm+ 01606d0ern0erm mov mov.b #xx:8,rd b f rd imm mov.b rs,rd b 0 c rs rd mov.b @ers,rd b 6 8 0 ers rd mov.b @(d:16,ers),rd b 6 e 0 ers rd disp mov.b @(d:32,ers),rd b 7 8 0 ers 0 6 a 2 rd disp mov.b @ers+,rd b 6 c 0 ers rd mov.b @aa:8,rd b 2 rd abs mov.b @aa:16,rd b 6 a 0 rd abs
rev. 3.0, 07/00, page 269 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte mov mov.b @aa:32,rd b 6 a 2 rd abs mov.b rs,@erd b 6 8 1 erd rs mov.b rs,@(d:16,erd) b 6 e 1 erd rs disp mov.b rs,@(d:32,erd) b 7 8 0 erd 0 6 a a rs disp mov.b rs,@Cerd b 6 c 1 erd rs mov.b rs,@aa:8 b 3 rs abs mov.b rs,@aa:16 b 6 a 8 rs abs mov.b rs,@aa:32 b 6 a a rs abs mov.w #xx:16,rd w 7 9 0 rd imm mov.w rs,rd w 0 d rs rd mov.w @ers,rd w 6 9 0 ers rd mov.w @(d:16,ers),rd w 6 f 0 ers rd disp mov.w @(d:32,ers),rd w 7 8 0 ers 0 6 b 2 rd disp mov.w @ers+,rd w 6 d 0 ers rd mov.w @aa:16,rd w 6 b 0 rd abs mov.w @aa:32,rd w 6 b 2 rd abs mov.w rs,@erd w 6 9 1 erd rs mov.w rs,@(d:16,erd) w 6 f 1 erd rs disp mov.w rs,@(d:32,erd) w 7 8 0 erd 0 6 b a rs disp mov.w rs,@Cerd w 6 d 1 erd rs mov.w rs,@aa:16 w 6 b 8 rs abs mov.w rs,@aa:32 w 6 b a rs abs mov.l #xx:32,rd l 7 a 0 0 erd imm mov.l ers,erd l 0 f 1 ers 0 erd mov.l @ers,erd l 0100690ers0erd mov.l @(d:16,ers),erd l 01006f0ers0erd disp mov.l @(d:32,ers),erd l 0100780ers06 b20erd disp mov.l @ers+,erd l 01006d0ers0erd mov.l @aa:16,erd l 01006b00erd abs mov.l @aa:32,erd l 01006b20erd abs mov.l ers,@erd l 0100691erd0ers mov.l ers,@(d:16,erd) l 01006f1erd0ers disp mov.l ers,@(d:32,erd) * 2 l0100780erd06 ba0ers disp mov.l ers,@Cerd l 01006d1erd0ers mov.l ers,@aa:16 l 01006b80ers abs mov.l ers,@aa:32 l 01006ba0ers abs
rev. 3.0, 07/00, page 270 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte movfpe movfpe @aa:16,rd b 6 a 4 rd abs movtpe movtpe rs,@aa:16 b 6 a c rs abs mulxs mulxs.b rs,rd b 0 1 c 0 5 0 rs rd mulxs.w rs,erd w 0 1 c 0 5 2 rs 0 erd mulxu mulxu.b rs,rd b 5 0 rs rd mulxu.w rs,erd w 5 2 rs 0 erd neg neg.b rd b 1 7 8 rd neg.w rd w 1 7 9 rd neg.l erd l 1 7 b 0 erd nop nop 0000 not not.b rd b 1 7 0 rd not.w rd w 1 7 1 rd not.l erd l 1 7 3 0 erd or or.b #xx:8,rd b c rd imm or.b rs,rd b 1 4 rs rd or.w #xx:16,rd w 7 9 4 rd imm or.w rs,rd w 6 4 rs rd or.l #xx:32,erd l 7 a 4 0 erd imm or.l ers,erd l 0 1 f 0 6 4 0 ers 0 erd orc orc #xx:8,ccr b 0 4 imm orc #xx:8,exr b 014104 imm pop pop.w rn w 6 d 7 rn pop.l ern l 0 1 0 0 6 d 7 0 ern push push.w rn w 6 d f rn push.l ern l 0 1 0 0 6 d f 0 ern rotl rotl.b rd b 1 2 8 rd rotl.b #2,rd b 1 2 c rd rotl.w rd w 1 2 9 rd rotl.w #2,rd w 1 2 d rd rotl.l erd l 1 2 b 0 erd rotl.l #2,erd l 1 2 f 0 erd rotr rotr.b rd b 1 3 8 rd rotr.b #2,rd b 1 3 c rd rotr.w rd w 1 3 9 rd rotr.w #2,rd w 1 3 d rd
rev. 3.0, 07/00, page 271 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte rotr rotr.l erd l 1 3 b 0 erd rotr.l #2,erd l 1 3 f 0 erd rotxl rotxl.b rd b 1 2 0 rd rotxl.b #2,rd b 1 2 4 rd rotxl.w rd w 1 2 1 rd rotxl.w #2,rd w 1 2 5 rd rotxl.l erd l 1 2 3 0 erd rotxl.l #2,erd l 1 2 7 0 erd rotxr rotxr.b rd b 1 3 0 rd rotxr.b #2,rd b 1 3 4 rd rotxr.w rd w 1 3 1 rd rotxr.w #2,rd w 1 3 5 rd rotxr.l erd l 1 3 3 0 erd rotxr.l #2,erd l 1 3 7 0 erd rte rte 5670 rts rts 5470 shal shal.b rd b 1 0 8 rd shal.b #2,rd b 1 0 c rd shal.w rd w 1 0 9 rd shal.w #2,rd w 1 0 d rd shal.l erd l 1 0 b 0 erd shal.l #2,erd l 1 0 f 0 erd shar shar.b rd b 1 1 8 rd shar.b #2,rd b 1 1 c rd shar.w rd w 1 1 9 rd shar.w #2,rd w 1 1 d rd shar.l erd l 1 1 b 0 erd shar.l #2,erd l 1 1 f 0 erd shll shll.b rd b 1 0 0 rd shll.b #2,rd b 1 0 4 rd shll.w rd w 1 0 1 rd shll.w #2,rd w 1 0 5 rd shll.l erd l 1 0 3 0 erd shll.l #2,erd l 1 0 7 0 erd shlr shlr.b rd b 1 1 0 rd shlr.b #2,rd b 1 1 4 rd
rev. 3.0, 07/00, page 272 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte shlr shlr.w rd w 1 1 1 rd shlr.w #2,rd w 1 1 5 rd shlr.l erd l 1 1 3 0 erd shlr.l #2,erd l 1 1 7 0 erd sleep sleep 0 1 8 0 stc stc.b ccr,rd b 0 2 0 rd stc.b exr,rd b 0 2 1 rd stc.w ccr,@erd w 0140691erd0 stc.w exr,@erd w 0141691erd0 stc.w ccr,@(d:16,erd) w 01406f1erd0 disp stc.w exr,@(d:16,erd) w 01416f1erd0 disp stc.w ccr,@(d:32,erd) w 0140780erd0 6ba0 disp stc.w exr,@(d:32,erd) w 0141780erd0 6ba0 disp stc.w ccr,@Cerd w 01406d1erd0 stc.w exr,@Cerd w 01416d1erd0 stc.w ccr,@aa:16 w 01406b80 abs stc.w exr,@aa:16 w 01416b80 abs stc.w ccr,@aa:32 w 01406ba0 abs stc.w exr,@aa:32 w 01416ba0 abs stm stm.l (ernCern+1),@Csp l01106df0ern stm.l (ernCern+2),@Csp l01206df0ern stm.l (ernCern+3),@Csp l01306df0ern stmac * 1 stmac mach,erd l 0 2 2 0 ers stmac macl,erd l 0 2 3 0 ers sub sub.b rs,rd b 1 8 rs rd sub.w #xx:16,rd w 7 9 3 rd imm sub.w rs,rd w 1 9 rs rd sub.l #xx:32,erd l 7 a 3 0 erd imm sub.l ers,erd l 1 a 1 ers 0 erd subs subs #1,erd l 1 b 0 0 erd subs #2,erd l 1 b 8 0 erd subs #4,erd l 1 b 9 0 erd subx subx #xx:8,rd b b rd imm subx rs,rd b 1 e rs rd tas tas @erd * 3 b 0 1 e 0 7 b 0 erd c trapa trapa #x:2 5 7 00 imm 0
rev. 3.0, 07/00, page 273 of 320 instruction format instruction mnemonic size 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte legend imm: immediate data (2, 3, 8, 16, or 32 bits) abs: absolute address (8, 16, 24, or 32 bits) disp: displacement (8, 16, or 32 bits) rs, rd, rn: register field (4 bits specifying an 8-bit or 16-bit register. the symbols rs, rd, and rn correspond to operand symb ols rs, rd, and rn.) ers, erd, ern, erm: register field (3 bits specifying an address register or 32-bit register. the symbols ers, erd, ern, and erm correspond to operand symbols ers, erd, ern, and erm.) the register fields specify general registers as follows. address register 32-bit register 16-bit register 8-bit register register general register general register general field register field register field register 000 er0 0000 r0 0000 r0h 001 er1 0001 r1 0001 r1h 111 er7 0111 r7 0111 r7h 1000 e0 1000 r0l 1001 e1 1001 r1l 1111 e7 1111 r7l xor xor.b #xx:8,rd b d rd imm xor.b rs,rd b 1 5 rs rd xor.w #xx:16,rd w 7 9 5 rd imm xor.w rs,rd w 6 5 rs rd xor.l #xx:32,erd l 7 a 5 0 erd imm xor.l ers,erd l 0 1 f 0 6 5 0 ers 0 erd xorc xorc #xx:8,ccr b 0 5 imm xorc #xx:8,exr b 014105 imm notes: 1. these instructions are supported by the h8s/2600 cpu only. 2. bit 7 of the 4th byte of the mov.l ers, @(d:32,erd) instruction can be either 1 or 0. 3. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 3.0, 07/00, page 274 of 320 2.5 operation code map table 2.3 shows an operation code map. table 2.3 operation code map (1) 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 nop table 2.3 (2) bra mulxu bset note: * these instructions are supported by the h8s/2600 cpu only. 1 table 2.3 (2) table 2.3 (2) brn divxu bnot 2 table 2.3 (2) bhi mulxu bclr 3 table 2.3 (2) bls divxu btst 4 orc or bcc rts or 5 xorc xor bcs bsr xor 6 andc and bne rte and 7 ldc table 2.3 (2) beq trapa 8 bvc table 2.3 (2) mov 9 bvs table 2.3 (2) a table 2.3 (2) table 2.3 (2) bpl jmp table 2.3 (2) table 2.3 (2) b table 2.3 (2) table 2.3 (2) bmi eepmov c mov cmp bge bsr mov d blt e addx subx bgt jsr f table 2.3 (2) table 2.3 (2) ble bor bior stc stmac * ldc ldmac * bxor bixor band biand bst bist bld bild table 2.3 (3) add addx cmp subx or xor and mov operation code: 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. ah al add sub mov.b mov
rev. 3.0, 07/00, page 275 of 320 table 2.3 operation code map (2) 9 adds bvs 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a operation code: 1st byte 2nd byte ah al bh bl ah al bh 0 mov inc adds daa dec subs das bra mov mov mov 1 brn table 2.3 (4) add add 2 bhi mov cmp cmp 3 shll shlr rotxl rotxr not bls table 2.3 (4) sub sub 4 bcc movfpe or or 5 inc extu dec bcs xor xor 6 mac * bne and and 7 inc shll shlr rotxl rotxr extu dec beq 8 sleep bvc mov a clrmac * bpl mov b bmi c table 2.3 (3) bge movtpe d table 2.3 (3) inc exts dec blt e tas bgt f table 2.3 (3) inc shal shar rotl rotr exts dec ble add mov sub cmp neg shll shlr rotxl rotxr not ldc stc shal shar rotl rotr neg subs ldm stm shal shar rotl rotr note: * these instructions are supported by the h8s/2600 cpu only.
rev. 3.0, 07/00, page 276 of 320 table 2.3 operation code map (3) operation code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl 01c05 01d05 01f06 7cr06 * 1 7cr07 7dr06 7dr07 7eaa6 7eaa7 7faa6 7faa7 ahalbhblch cl 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist the letter r indicates a register field. the letters aa indicate an absolute address field. instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: 1. 2. * 1 * 1 * 1 * 2 * 2 * 2 * 2
rev. 3.0, 07/00, page 277 of 320 table 2.3 operation code map (4) operation code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0123456789abcdef bor bior bxor bixor band biand bld bild bst bist instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. btst bset bnot bclr 5th byte 6th byte eh el fh fl operation code: 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh el 0123456789abcdef bor bior bxor bixor band biand bld bild bst bist the letters aa indicate an absolute address field. instruction when most significant bit of hh is 0. instruction when most significant bit of hh is 1. note: * btst bset bnot bclr 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl
rev. 3.0, 07/00, page 278 of 320 2.6 number of states required for instruction execution the tables in this section can be used to calculate the number of states required for instruction execution by the cpu. table 2.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table 2.4 indicates the number of states required for each cycle, depending on its size. the number of states required for each cycle depends on the product. see the hardware manual named for the relevant product for details. the number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. bset #0, @ffffc7:8 from table 2.5: i = l = 2, j = k = m = n= 0 from table 2.4: s i = 4, s l = 2 number of states required for execution = 2 4 + 2 2 = 12 2. jsr @@30 from table 2.5: i = j = k = 2, l = m = n = 0 from table 2.4: s i = s j = s k = 4 number of states required for execution = 2 4 + 2 4 + 2 4 = 24
rev. 3.0, 07/00, page 279 of 320 table 2.4 number of states per cycle access conditions external device on-chip supporting module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i branch address read s j stack operation s k 2n 4 6 + 2m byte data access s l n23 + m word data access s m 1 2n n 46 + 2m 23 + m * internal operation s n 111 1111 note: * for the movfpe and movtpe instructions, refer to the relevant microcontroller hardware manual. legend m: number of wait states inserted into external device access n: number of states required for access to an on-chip supporting module. for the specific number, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 280 of 320 table 2.5 number of cycles in instruction execution instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n add add.b #xx:8,rd 1 add.b rs,rd 1 add.w #xx:16,rd 2 add.w rs,rd 1 add.l #xx:32,erd 3 add.l ers,erd 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd 1 addx rs,rd 1 and and.b #xx:8,rd 1 and.b rs,rd 1 and.w #xx:16,rd 2 and.l #xx:32,erd 3 and.l ers,erd 2 andc andc #xx:8,ccr 1 andc #xx:8,exr 2 band band #xx:3,rd 1 band #xx:3,@erd 2 1 band #xx:3,@aa:8 2 1 band #xx:3,@aa:16 3 1 band #xx:3,@aa:32 4 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bra d:16 (bt d:16) 2 1 brn d:16 (bf d:16) 2 1
rev. 3.0, 07/00, page 281 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bcc bhi d:16 2 1 bls d:16 2 1 bcc d:16 (bhs d:16) 2 1 bcs d:16 (blo d:16) 2 1 bne d:16 2 1 beq d:16 2 1 bvc d:16 2 1 bvs d:16 2 1 bpl d:16 2 1 bmi d:16 2 1 bge d:16 2 1 blt d:16 2 1 bgt d:16 2 1 ble d:16 2 1 bclr bclr #xx:3,rd 1 bclr #xx:3,@erd 2 2 bclr #xx:3,@aa:8 2 2 bclr #xx:3,@aa:16 3 2 bclr #xx:3,@aa:32 4 2 bclr rn,rd 1 bclr rn,@erd 2 2 bclr rn,@aa:8 2 2 bclr rn,@aa:16 3 2 bclr rn,@aa:32 4 2 biand biand #xx:3,rd 1 biand #xx:3,@erd 2 1 biand #xx:3,@aa:8 2 1 biand #xx:3,@aa:16 3 1 biand #xx:3,@aa:32 4 1 bild bild #xx:3,rd 1 bild #xx:3,@erd 2 1 bild #xx:3,@aa:8 2 1 bild #xx:3,@aa:16 3 1 bild #xx:3,@aa:32 4 1 bior bior #xx:8,rd 1 bior #xx:8,@erd 2 1 bior #xx:8,@aa:8 2 1 bior #xx:8,@aa:16 3 1 bior #xx:8,@aa:32 4 1
rev. 3.0, 07/00, page 282 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bist bist #xx:3,rd 1 bist #xx:3,@erd 2 2 bist #xx:3,@aa:8 2 2 bist #xx:3,@aa:16 3 2 bist #xx:3,@aa:32 4 2 bixor bixor #xx:3,rd 1 bixor #xx:3,@erd 2 1 bixor #xx:3,@aa:8 2 1 bixor #xx:3,@aa:16 3 1 bixor #xx:3,@aa:32 4 1 bld bld #xx:3,rd 1 bld #xx:3,@erd 2 1 bld #xx:3,@aa:8 2 1 bld #xx:3,@aa:16 3 1 bld #xx:3,@aa:32 4 1 bnot bnot #xx:3,rd 1 bnot #xx:3,@erd 2 2 bnot #xx:3,@aa:8 2 2 bnot #xx:3,@aa:16 3 2 bnot #xx:3,@aa:32 4 2 bnot rn,rd 1 bnot rn,@erd 2 2 bnot rn,@aa:8 2 2 bnot rn,@aa:16 3 2 bnot rn,@aa:32 4 2 bor bor #xx:3,rd 1 bor #xx:3,@erd 2 1 bor #xx:3,@aa:8 2 1 bor #xx:3,@aa:16 3 1 bor #xx:3,@aa:32 4 1 bset bset #xx:3,rd 1 bset #xx:3,@erd 2 2 bset #xx:3,@aa:8 2 2 bset #xx:3,@aa:16 3 2 bset #xx:3,@aa:32 4 2 bset rn,rd 1 bset rn,@erd 2 2 bset rn,@aa:8 2 2 bset rn,@aa:16 3 2 bset rn,@aa:32 4 2
rev. 3.0, 07/00, page 283 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bsr bsr d:8 normal 2 1 advanced 2 2 bsr d:16 normal 2 1 1 advanced 2 2 1 bst bst #xx:3,rd 1 bst #xx:3,@erd 2 2 bst #xx:3,@aa:8 2 2 bst #xx:3,@aa:16 3 2 bst #xx:3,@aa:32 4 2 btst btst #xx:3,rd 1 btst #xx:3,@erd 2 1 btst #xx:3,@aa:8 2 1 btst #xx:3,@aa:16 3 1 btst #xx:3,@aa:32 4 1 btst rn,rd 1 btst rn,@erd 2 1 btst rn,@aa:8 2 1 btst rn,@aa:16 3 1 btst rn,@aa:32 4 1 bxor bxor #xx:3,rd 1 bxor #xx:3,@erd 2 1 bxor #xx:3,@aa:8 2 1 bxor #xx:3,@aa:16 3 1 bxor #xx:3,@aa:32 4 1 clrmac * clrmac 1 1 * 3 cmp cmp.b #xx:8,rd 1 cmp.b rs,rd 1 cmp.w #xx:16,rd 2 cmp.w rs,rd 1 cmp.l #xx:32,erd 3 cmp.l ers,erd 1 daa daa rd 1 das das rd 1 dec dec.b rd 1 dec.w #1/2,rd 1 dec.l #1/2,erd 1 divxs divxs.b rs,rd 2 11 divxs.w rs,erd 2 19 divxu divxu.b rs,rd 1 11 divxu.w rs,erd 1 19
rev. 3.0, 07/00, page 284 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n eepmov eepmov.b 2 2n + 2 * 1 eepmov.w 2 2n + 2 * 1 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2,rd 1 inc.l #1/2,erd 1 jmp jmp @ern 2 jmp @aa:24 2 1 jmp @@aa:8 normal 2 1 1 advanced 2 2 1 jsr jsr @ern normal 2 1 advanced 2 2 jsr @aa:24 normal 2 1 1 advanced 2 2 1 jsr @@aa:8 normal 2 1 1 advanced 2 2 2 ldc ldc #xx:8,ccr 1 ldc #xx:8,exr 2 ldc rs,ccr 1 ldc rs,exr 1 ldc @ers,ccr 2 1 ldc @ers,exr 2 1 ldc @(d:16,ers),ccr 3 1 ldc @(d:16,ers),exr 3 1 ldc @(d:32,ers),ccr 5 1 ldc @(d:32,ers),exr 5 1 ldc @ers+,ccr 2 1 1 ldc @ers+,exr 2 1 1 ldc @aa:16,ccr 3 1 ldc @aa:16,exr 3 1 ldc @aa:32,ccr 4 1 ldc @aa:32,exr 4 1 ldm ldm.l @sp+,(ernCern+1) 2 4 1 ldm.l @sp+,(ernCern+2) 2 6 1 ldm.l @sp+,(ernCern+3) 2 8 1 ldmac * ldmac ers,mach 1 1 * 3 ldmac ers,macl 1 1 * 3
rev. 3.0, 07/00, page 285 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mac * mac @ern+,@erm+ 2 2 mov mov.b #xx:8,rd 1 mov.b rs,rd 1 mov.b @ers,rd 1 1 mov.b @(d:16,ers),rd 2 1 mov.b @(d:32,ers),rd 4 1 mov.b @ers+,rd 1 1 1 mov.b @aa:8,rd 1 1 mov.b @aa:16,rd 2 1 mov.b @aa:32,rd 3 1 mov.b rs,@erd 1 1 mov.b rs,@(d:16,erd) 2 1 mov.b rs,@(d:32,erd) 4 1 mov.b rs,@Cerd 1 1 1 mov.b rs,@aa:8 1 1 mov.b rs,@aa:16 2 1 mov.b rs,@aa:32 3 1 mov.w #xx:16,rd 2 mov.w rs,rd 1 mov.w @ers,rd 1 1 mov.w @(d:16,ers),rd 2 1 mov.w @(d:32,ers),rd 4 1 mov.w @ers+,rd 1 1 1 mov.w @aa:16,rd 2 1 mov.w @aa:32,rd 3 1 mov.w rs,@erd 1 1 mov.w rs,@(d:16,erd) 2 1 mov.w rs,@(d:32,erd) 4 1 mov.w rs,@Cerd 1 1 1 mov.w rs,@aa:16 2 1 mov.w rs,@aa:32 3 1 mov.l #xx:32,erd 3 mov.l ers,erd 1 mov.l @ers,erd 2 2 mov.l @(d:16,ers),erd 3 2 mov.l @(d:32,ers),erd 5 2 mov.l @ers+,erd 2 2 1 mov.l @aa:16,erd 3 2 mov.l @aa:32,erd 4 2 mov.l ers,@erd 2 2
rev. 3.0, 07/00, page 286 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mov mov.l ers,@(d:16,erd) 3 2 mov.l ers,@(d:32,erd) 5 2 mov.l ers,@Cerd 2 2 1 mov.l ers,@aa:16 3 2 mov.l ers,@aa:32 4 2 movfpe movfpe @:aa:16,rd 2 1 * 2 movtpe movtpe rs,@:aa:16 2 1 * 2 mulxs mulxs.b rs,rd h8s/2600 2 2 * 3 h8s/2000 2 11 mulxs.w rs,erd h8s/2600 2 3 * 3 h8s/2000 2 19 mulxu mulxu.b rs,rd h8s/2600 1 2 * 3 h8s/2000 1 11 mulxu.w rs,erd h8s/2600 1 3 * 3 h8s/2000 1 19 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1 or or.b #xx:8,rd 1 or.b rs,rd 1 or.w #xx:16,rd 2 or.w rs,rd 1 or.l #xx:32,erd 3 or.l ers,erd 2 orc orc #xx:8,ccr 1 orc #xx:8,exr 2 pop pop.w rn 1 1 1 pop.l ern 2 2 1 push push.w rn 1 1 1 push.l ern 2 2 1 rotl rotl.b rd 1 rotl.b #2,rd 1 rotl.w rd 1 rotl.w #2,rd 1 rotl.l erd 1 rotl.l #2,erd 1
rev. 3.0, 07/00, page 287 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n rotr rotr.b rd 1 rotr.b #2,rd 1 rotr.w rd 1 rotr.w #2,rd 1 rotr.l erd 1 rotr.l #2,erd 1 rotxl rotxl.b rd 1 rotxl.b #2,rd 1 rotxl.w rd 1 rotxl.w #2,rd 1 rotxl.l erd 1 rotxl.l #2,erd 1 rotxr rotxr.b rd 1 rotxr.b #2,rd 1 rotxr.w rd 1 rotxr.w #2,rd 1 rotxr.l erd 1 rotxr.l #2,erd 1 rte rte 2 2/3 * 1 1 rts rts normal 2 1 1 advanced 2 2 1 shal shal.b rd 1 shal.b #2,rd 1 shal.w rd 1 shal.w #2,rd 1 shal.l erd 1 shal.l #2,erd 1 shar shar.b rd 1 shar.b #2,rd 1 shar.w rd 1 shar.w #2,rd 1 shar.l erd 1 shar.l #2,erd 1 shll shll.b rd 1 shll.b #2,rd 1 shll.w rd 1 shll.w #2,rd 1 shll.l erd 1 shll.l #2,erd 1
rev. 3.0, 07/00, page 288 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n shlr shlr.b rd 1 shlr.b #2,rd 1 shlr.w rd 1 shlr.w #2,rd 1 shlr.l erd 1 shlr.l #2,erd 1 sleep sleep 1 1 stc stc.b ccr,rd 1 stc.b exr,rd 1 stc.w ccr,@erd 2 1 stc.w exr,@erd 2 1 stc.w ccr,@(d:16,erd) 3 1 stc.w exr,@(d:16,erd) 3 1 stc.w ccr,@(d:32,erd) 5 1 stc.w exr,@(d:32,erd) 5 1 stc.w ccr,@Cerd 2 1 1 stc.w exr,@Cerd 2 1 1 stc.w ccr,@aa:16 3 1 stc.w exr,@aa:16 3 1 stc.w ccr,@aa:32 4 1 stc.w exr,@aa:32 4 1 stm stm.l (ernCern+1),@Csp 2 4 1 stm.l(ernCern+2),@Csp 2 6 1 stm.l(ernCern+3),@Csp 2 8 1 stmac * stmac mach,erd 1 0 * 3 stmac macl,erd 1 0 * 3 sub sub.b rs,rd 1 sub.w #xx:16,rd 2 sub.w rs,rd 1 sub.l #xx:32,erd 3 sub.l ers,erd 1 subs subs #1/2/4,erd 1 subx subx #xx:8,rd 1 subx rs,rd 1 tas tas @erd * 4 22 trapa trapa #x:2 normal 2 1 2/3 * 1 2 advanced 2 2 2/3 * 1 2
rev. 3.0, 07/00, page 289 of 320 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n xor xor.b #xx:8,rd 1 xor.b rs,rd 1 xor.w #xx:16,rd 2 xor.w rs,rd 1 xor.l #xx:32,erd 3 xor.l ers,erd 2 xorc xorc #xx:8,ccr 1 xorc xorc #xx:8,exr 2 notes: * these instructions are supported by the h8s/2600 cpu only. 1. 2 when exr is invalid, 3 when exr is valid. 2. 5 for concatenated execution, 4 otherwise. 3. an internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 4. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 3.0, 07/00, page 290 of 320 2.7 bus states during instruction execution table 2.6 indicates the types of cycles that occur during instruction execution by the cpu. see table 2.4 for the number of states per cycle. how to read the table: internal operation, 1 state order of execution end of instruction read effective address (word-size read) no read or write instruction 12345678 jmp @aa:24 r:w 2nd r:w ea read 2nd word of current instruction (word-size read) 9 legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next address of next instruction ea effective address vec vector address
rev. 3.0, 07/00, page 291 of 320 figure 2.1 shows timing waveforms for the address bus and the 5' and :5 ( +:5 or /:5 ) signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ? address bus ( or ) high level fetching 3rd byte of instruction fetching 4th byte of instruction fetching 1st byte of instruction at jump address fetching 2nd byte of instruction at jump address r:w ea r:w 2nd internal operation figure 2.1 address bus, 5' 5' 5' 5' , and :5 :5 :5 :5 ( +:5 +:5 +:5 +:5 or /:5 /:5 /:5 /:5 ) timing (8-bit bus, three-state access, no wait states)
rev. 3.0, 07/00, page 292 of 320 table 2.6 instruction execution cycles instruction 123456789 add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w next band #xx:3,@aa:8 r:w 2nd r:b ea r:w next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea
rev. 3.0, 07/00, page 293 of 320 instruction 123456789 ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, r:w ea 1 state brn d:16 (bf d:16) r:w 2nd internal operation, r:w ea 1 state bhi d:16 r:w 2nd internal operation, r:w ea 1 state bls d:16 r:w 2nd internal operation, r:w ea 1 state bcc d:16 (bhs d:16) r:w 2nd internal operation, r:w ea 1 state bcs d:16 (blo d:16) r:w 2nd internal operation, r:w ea 1 state bne d:16 r:w 2nd internal operation, r:w ea 1 state beq d:16 r:w 2nd internal operation, r:w ea 1 state bvc d:16 r:w 2nd internal operation, r:w ea 1 state bvs d:16 r:w 2nd internal operation, r:w ea 1 state bpl d:16 r:w 2nd internal operation, r:w ea 1 state bmi d:16 r:w 2nd internal operation, r:w ea 1 state bge d:16 r:w 2nd internal operation, r:w ea 1 state blt d:16 r:w 2nd internal operation, r:w ea 1 state bgt d:16 r:w 2nd internal operation, r:w ea 1 state ble d:16 r:w 2nd internal operation, r:w ea 1 state bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea
rev. 3.0, 07/00, page 294 of 320 instruction 123456789 bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,@erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next
rev. 3.0, 07/00, page 295 of 320 instruction 123456789 bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 normal r:w next r:w ea w:w stack advanced r:w next r:w ea w:w:m stack (h) w:w stack (l) bsr d:16 normal r:w 2nd internal operation, r:w ea w:w stack 1 state advanced r:w 2nd internal operation, r:w ea w:w:m stack (h) w:w stack (l) 1 state bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next
rev. 3.0, 07/00, page 296 of 320 instruction 123456789 btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac * r:w next internal operation, 1 state * 9 cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next ??? repeated n times * 3 ??? exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next
rev. 3.0, 07/00, page 297 of 320 instruction 123456789 inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, r:w ea 1 state jmp @@aa:8 normal r:w next r:w aa:8 internal operation, r:w ea 1 state advanced r:w next r:w:m aa:8 r:w aa:8 internal operation, r:w ea 1 state jsr @ern normal r:w next r:w ea w:w stack advanced r:w next r:w ea w:w:m stack (h) w:w stack (l) jsr @aa:24 normal r:w 2nd internal operation, r:w ea w:w stack 1 state advanced r:w 2nd internal operation, r:w ea w:w:m stack (h) w:w stack (l) 1 state jsr @@aa:8 normal r:w next r:w aa:8 w:w stack r:w ea advanced r:w next r:w:m aa:8 r:w aa:8 w:w:m stack (h) w:w stack (l) r:w ea ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @ers+,exr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+,(ernCern+1) r:w 2nd r:w:m next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state
rev. 3.0, 07/00, page 298 of 320 instruction 123456789 ldm.l @sp+,(ernCern+2) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldm.l @sp+,(ernCern+3) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldmac ers,mach * r:w next internal operation, ??? repeated n times * 3 ??? 1 state * 9 ldmac ers,macl * r:w next internal operation, 1 state * 9 mac @ern+,@erm+ * r:w 2nd r:w next r:w ean r:w eam mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, r:b ea 1 state mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@Cerd r:w next internal operation, w:b ea 1 state mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+, rd r:w next internal operation, r:w ea 1 state mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea
rev. 3.0, 07/00, page 299 of 320 mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:e 4th r:w next w:w ea mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea mov.w rs,@Cerd r:w next internal operation, w:w ea 1 state mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@Cerd r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd r:w 2nd r:w next r:w * 4 ea movtpe rs,@aa:16 r:w 2nd r:w next w:b * 4 ea mulxs.b rs,rd h8s/2600 r:w 2nd r:w next internal operation, 2 states * 9 h8s/2000 r:w 2nd r:w next internal operation, 11 states mulxs.w rs,erd h8s/2600 r:w 2nd r:w next internal operation, 3 states * 9 h8s/2000 r:w 2nd r:w next internal operation, 19 states mulxu.b rs,rd h8s/2600 r:w next internal operation, 2 states * 9 h8s/2000 r:w next internal operation, 11 states mulxu.w rs,erd h8s/2600 r:w next internal operation, 3 states * 9 h8s/2000 r:w next internal operation, 19 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next instruction 123456789
rev. 3.0, 07/00, page 300 of 320 not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next pop.w rn r:w next internal operation, r:w ea 1 state pop.l ern r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state push.w rn r:w next internal operation, w:w ea 1 state push.l ern r:w 2nd r:w:m next internal operation w:w:m ea w:w ea+2 :m rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next instruction 123456789
rev. 3.0, 07/00, page 301 of 320 instruction 123456789 rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, r:w * 5 1 state rts normal r:w next r:w stack internal operation, r:w * 5 1 state advanced r:w next r:w:m stack (h) r:w stack (l) internal operation, r:w * 5 1 state shal.b rd r:w next shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation, 1 state stc ccr,rd r:w next
rev. 3.0, 07/00, page 302 of 320 stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@Cerd r:w 2nd r:w next internal operation, w:w ea 1 state stc exr,@Cerd r:w 2nd r:w next internal operation, w:w ea 1 state stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l(ernCern+1),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ernCern+2),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ernCern+3),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stmac mach,erd * r:w next * 9 ??? repeated n times * 3 ??? stmac macl,erd * r:w next * 9 sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd * 10 r:w 2nd r:w next r:b ea w:b ea trapa #x:2 normal r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w vec internal operation, r:w * 8 1 state 1 state advanced r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 8 1 state 1 state xor.b #xx8,rd r:w next instruction 123456789
rev. 3.0, 07/00, page 303 of 320 instruction 123456789 xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next reset exception normal r:w vec internal operation, r:w * 6 handling 1 state advanced r:w vec r:w vec+2 internal operation, r:w * 6 1 state interrupt exception normal r:w * 7 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w vec internal operation, r:w * 8 handling 1 state 1 state advanced r:w * 7 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 8 1 state 1 state notes: * these instructions are supported by the h8s/2600 cpu only. 1. eas is the contents of er5. ead is the contents of er6. 2. eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instructio n. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. 3. repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. for the number of states required for byte-size read or write, refer to the relevant microcontroller hardware manual. 5. start address after return. 6. start address of the program. 7. prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 8. start address of the interrupt-handling routine. 9. an internal operation may require between 0 and 3 additional states, depending on the preceding instruction. 10. only register er0, er1, er4, or er5 should be used when using the tas instruction.
rev. 3.0, 07/00, page 304 of 320 2.8 condition code modification this section indicates the effect of each cpu instruction on the condition code. the notation used in the table is defined below. 31 for longword operands 15 for word operands m = 7 for byte operands si the i-th bit of the source operand di the i-th bit of the destination operand ri the i-th bit of the result dn the specified bit in the destination operand not affected ? modified according to the result of the instruction (see definition) 0 always cleared to 0 1 always set to 1 * undetermined (no guaranteed value) z' z flag before instruction execution c' c flag before instruction execution
rev. 3.0, 07/00, page 305 of 320 table 2.7 condition code modification instruction h n z v c definition add h = smC4 dmC4 + dmC4 + smC4 n = rm z = ...... v = sm dm + rm c = sm dm + dm + sm adds addx h = smC4 dmC4 + dmC4 + smC4 n = rm z = z' ...... v = sm dm + rm c = sm dm + dm + sm and 0 n = rm z = ...... andc stores the corresponding bits of the result. no flags change when the operand is exr. band c = c' dn bcc bclr biand c = c' bild c = bior c = c' + bist bixor c = c' dn + bld c = dn bnot bor c = c' + dn bset bsr bst btst z = bxor c = c' + dn clrmac * cmp h = smC4 + rmC4 + smC4 rmC4 n = rm z = ... v = dm + sm rm c = sm + rm + sm rm ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ?
rev. 3.0, 07/00, page 306 of 320 instruction h n z v c definition daa ** n = rm z = ...... c: decimal arithmetic carry das ** n = rm z = ...... c: decimal arithmetic borrow dec n = rm z = ...... v = dm divxs n = sm + dm z = ...... divxu n = sm z = ...... eepmov exts 0 n = rm z = ...... extu 0 0 z = ...... inc n = rm z = ...... v = rm jmp jsr ldc stores the corresponding bits of the result. no flags change when the operand is exr. ldm ldmac * mac * mov 0 n = rm z = ...... movfpe 0 n = rm z = ...... movtpe 0 n = rm z = ...... mulxs n = r2m z = ...... ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
rev. 3.0, 07/00, page 307 of 320 instruction h n z v c definition mulxu neg h = dmC4 + rmC4 n = rm z = ...... v = dm rm c = dm + rm nop not 0 n = rm z = ...... or 0 n = rm z = ...... orc stores the corresponding bits of the result. no flags change when the operand is exr. pop 0 n = rm z = ...... push 0 n = rm z = ...... rotl 0 n = rm z = ...... c = dm (1-bit shift) or c = dmC1 (2-bit shift) rotr 0 n = rm z = ...... c = d0 (1-bit shift) or c = d1 (2-bit shift) rotxl 0 n = rm z = ...... c = dm (1-bit shift) or c = dmC1 (2-bit shift) rotxr 0 n = rm z = ...... c = d0 (1-bit shift) or c = d1 (2-bit shift) rte stores the corresponding bits of the result. rts shal n = rm z = ...... v = dm + (1-bit shift) v = dm + (2-bit shift) c = dm (1-bit shift) or c = dmC1 (2-bit shift) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
rev. 3.0, 07/00, page 308 of 320 instruction h n z v c definition shar 0 n = rm z = ...... c = d0 (1-bit shift) or c = d1 (2-bit shift) shll 0 n = rm z = ...... c = dm (1-bit shift) or c = dmC1 (2-bit shift) shlr 0 0 n = rm z = ...... c = d0 (1-bit shift) or c = d1 (2-bit shift) sleep stc stm stmac * n = 1 if mac instruction resulted in negative value in mac register z = 1 if mac instruction resulted in zero value in mac register v = 1 if mac instruction resulted in overflow sub h = smC4 + rmC4 + smC4 rmC4 n = rm z = ...... v = dm + sm rm c = sm + rm + sm rm subs subx h = smC4 + rmC4 + smC4 rmC4 n = rm z = z' ...... v = dm + sm rm c = sm + rm + sm rm tas 0 n = dm z = ...... trapa xor 0 n = rm z = ...... xorc stores the corresponding bits of the result. no flags change when the operand is exr. note: * these instructions are supported by the h8s/2600 cpu only. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
rev. 3.0, 07/00, page 309 of 320 section 3 processing states 3.1 overview the cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 3.1 shows a diagram of the processing states. figure 3.2 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode, module stop mode, etc. figure 3.1 processing states
rev. 3.0, 07/00, page 310 of 320 end of bus request bus request program execution state bus-released state sleep mode exception-handling state external interrupt software standby mode = high reset state = high, = low hardware standby mode * 2 power-down state * 1 notes: 1. 2. from any state except hardware standby mode, a transition to the reset state occurs whenever goes low. from any state, a transition to hardware standby mode occurs when goes low. sleep instruction with ssby = 0 sleep instruction with ssby = 1 interrupt request end of bus request bus request request for exception handling end of exception handling figure 3.2 state transitions 3.2 reset state when the 5(6 input goes low all current processing stops and the cpu enters the reset state. reset exception handling starts when the 5(6 signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 311 of 320 3.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. 3.3.1 types of exception handling and their priority exception handling is performed for traces, resets, interrupts, and trap instructions. table 3.1 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted, in the program execution state. exception handling and the stack structure differ according to the interrupt control mode set in syscr. table 3.1 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately when 5(6 changes from low to high trace end of instruction execution or end of exception-handling sequence * 1 when the trace (t) bit is set to 1, the trace starts at the end of the current instruction or current exception- handling sequence interrupt end of instruction execution or end of exception-handling sequence * 2 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed * 3 notes: 1. traces are enabled only in interrupt control modes 2 and 3. trace exception-handling is not executed at the end of the rte instruction. 2. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 3. trap instruction exception handling is always accepted, in the program execution state. for details on interrupt control modes, exception sources, and exception handling, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 312 of 320 3.3.2 reset exception handling after the 5(6 pin has gone low and the reset state has been entered, reset exception handling starts when 5(6 goes high again. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. 3.3.3 trace traces are enabled only in interrupt control modes 2 and 3. trace mode is entered when the t bit of exr is set to 1. when trace mode is established, trace exception handling starts at the end of each instruction. at the end of a trace exception-handling sequence, the t bit of exr is cleared to 0 and trace mode is cleared. interrupt masks are not affected. the t bit saved on the stack retains its value of 1, and when the rte instruction is executed to return from the trace exception-handling routine, trace mode is entered again. trace exception- handling is not executed at the end of the rte instruction. trace mode is not entered in interrupt control modes 0 and 1, regardless of the state of the t bit. 3.3.4 interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and execution branches to that address. figure 3.3 shows the stack after exception handling ends, for the case of interrupt mode 1 in advanced mode.
rev. 3.0, 07/00, page 313 of 320 (c) interrupt control modes 0 & 1 (d) interrupt control modes 2 & 3 ccr pc (24 bits) sp note: * ignored when returning. ccr pc (24 bits) sp exr reserved * (a) interrupt control modes 0 & 1 (b) interrupt control modes 2 & 3 ccr ccr * pc (16 bits) sp ccr ccr * pc (16 bits) sp exr reserved * normal mode advanced mode figure 3.3 stack structure after exception handling (example) 3.4 program execution state in this state the cpu executes program instructions in sequence.
rev. 3.0, 07/00, page 314 of 320 3.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts except for internal operations. bus masters other than the cpu may include the direct memory access controller (dmac) and data transfer controller (dtc). for further details, refer to the relevant microcontroller hardware manual. 3.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are three modes in which the cpu stops operating: sleep mode, software standby mode, and hardware standby mode. there are also two other power-down modes: medium-speed mode and module stop mode. in medium-speed mode the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual modules, other than the cpu. for details, refer to the relevant microcontroller hardware manual. 3.6.1 sleep mode a transition to sleep mode is made if the sleep instruction is executed while the software standby bit (ssby) in the system control register (syscr) is cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instruction. the contents of cpu registers are retained. 3.6.2 software standby mode a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in syscr is set to 1. in software standby mode, the cpu and clock halt and all on-chip operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. 3.6.3 hardware standby mode a transition to hardware standby mode is made when the 67%< pin goes low. in hardware standby mode, the cpu and clock halt and all on-chip operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained.
rev. 3.0, 07/00, page 315 of 320 section 4 basic timing 4.1 overview the cpu is driven by a system clock, denoted by the symbol ?. the period from one rising edge of ? to the next is referred to as a state. the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. refer to the relevant microcontroller hardware manual for details. 4.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word access. figure 4.1 shows the on-chip memory access cycle. figure 4.2 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus ? bus cycle t1 address read data write data read access write access figure 4.1 on-chip memory access cycle
rev. 3.0, 07/00, page 316 of 320 bus cycle t1 unchanged address bus , data bus ? high high high high-impedance state figure 4.2 pin states during on-chip memory access
rev. 3.0, 07/00, page 317 of 320 4.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular on-chip register being accessed. figure 4.3 shows the access timing for the on-chip supporting modules. figure 4.4 shows the pin states. bus cycle t1 t2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus ? figure 4.3 on-chip supporting module access timing
rev. 3.0, 07/00, page 318 of 320 bus cycle t1 t2 unchanged address bus , data bus ? high high high high-impedance state figure 4.4 pin states during on-chip supporting module access 4.4 external address space access timing the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. figure 4.5 shows the read timing for two-state and three-state access. figure 4.6 shows the write timing for two-state and three-state access. in three-state access, wait states can be inserted. for further details, refer to the relevant microcontroller hardware manual.
rev. 3.0, 07/00, page 319 of 320 read cycle t1 t2 address read data (a) two-state access address bus data bus ? read cycle t1 t2 address read data (b) three-state access t3 address bus data bus ? figure 4.5 external device access timing (read timing)
rev. 3.0, 07/00, page 320 of 320 write cycle t1 t2 address (a) two-state access address bus , data bus ? write data write cycle t1 t2 address write data (b) three-state access t3 address bus data bus ? , figure 4.6 external device access timing (write timing)
h8s/2600 series, h8s/2000 series programming manual publication date: 1st edition, march 1995 3rd edition, july 2000 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. copyright ? hitachi, ltd., 1995. all rights reserved. printed in japan.

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