(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 1 features ? less than 0.4ps rms (12khz-20mhz) phase jitter for all frequencies . ? less than 25ps (typ.) peak to peak jitter for all frequencies. ? low phase noise output (@ 1mhz frequency offset ? -144dbc/hz for 155.52mhz ? -140dbc/hz for 311.04mhz ? 19mhz-40mhz crystal input. ? 38mhz-320mhz output. ? available in pecl, lvds, or cmos outputs. ? no external varicap required. ? output enable selector. ? wide pull range (+/-200ppm). ? 3.3v operation. ? available in 3x3 qfn or 16-pin tssop packages. description the pl580-3x is a monolithic low jitter and low phase noise vcxo, capable of 0.4ps rms phase jitter and cmos, lvds, or pecl outputs, covering a wide frequency output range up to 320mhz. it allows the control of the output frequency with an input voltage (vcon), using a low cost crystal. the frequency selector pads of pl580-3x enable output frequencies of (2, 4, 8, or 16) * f xin . the pl580-3x is designed to address the demanding requirements of high perf ormance applications such as sonet, gps, video, etc. block diagram package pin assignment 16-pin tssop 3x3 qfn note1: qbar is used for single ended cmos output . note2: ^ denotes internal pull up resistor. pl580-3x 1 2 3 4 5 6 7 8 vddana 9 10 11 12 13 14 15 16 xin xout sel2^ oe_ctrl vcon gndana lp sel0^ gndbuf sel1^ gndbuf qbar vddbuf q lm pl580-3x gndbuf vddbuf q qbar xin sel0^ sel1^ vddana sel2^ xout oe_ctrl vcon lp gndana lm gndbuf 4 16 15 14 13 12 11 10 9 8 7 6 5 123 phase detector charge pump loop filter vco (f xin x16) vco divider xtal osc qbar oe xin xout q vcon varicap + performance tuner output divider (1,2,4,8)
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 2 output enable l ogical levels part # oe state 0 (default) output enabled pl580-38 (pecl) 1 tri-state 0 tri-state pl580-35 (pecl) pl580-37 (cmos) pl580-39 (lvds) 1 (default) output enabled pin descriptions name tssop pin number 3x3mm qfn pin number type description vddana 1 11 p vdd for analog circuitry. xin 2 12 i crystal input pin. (see crystal specifications on page 4). xout 3 13 o crystal output pin. (see crystal specifications on page 4). sel2 4 14 i output frequency selector pin. oe_ctrl 5 15 i output enable control pin. (see oe_ctrl logic levels). vcon 6 16 i voltage control input. gndana 7 1 p ground for analog circuitry. lp 8 2 - lm 9 3 - tuning inductor connection. the inductor is recommended to be a high q small size 0402 or 0603 smd component, and must be placed between lp and adjacent lm pin. place inductor as close to the ic as possible to minimize parasitic effects and to maintain inductor q. gndbuf 10 4 p gnd connection for output buffer circuitry. q 11 5 o pecl or lvds output. vddbuf 12 6 p vdd connection for output buffer circuitry. vddbuf should be separately decoupled from other vdds whenever possible. qbar 13 7 o complementary pecl, lvds, or single ended cmos output. gndbuf 14 8 p gnd connection for output buffer circuitry. sel1 15 9 i output frequency selector pin. sel0 16 10 i output frequency selector pin.
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 3 frequency selection table sel2 sel1 sel0 selected multiplier/output frequency 0 0 0 vco max* 0 0 1 vco min* 0 1 0 reserved 0 1 1 reserved 1 0 0 fin x 2 1 0 1 fin x 8 1 1 0 fin x 16 1 1 1 fin x 4 all sel pads have internal pull-ups (default value is ?1?). bond to gnd to set to 0. * special test modes to help selecting the inductor value for the target output frequency. performance tuning & in ductor value selection please refer to phaselink?s ?phasorv tuning assistance? so ftware to automatically calculate the optimum inductor values for your application. in addition, the chart below could be used as a reference for quick inductor value selection. please note that the inductor values ment ioned in the table below, or when using ?phasorv tuning assistance? are derived based on the parasitic values of phaselink?s evaluation board. for performance enhancement of your custom board design, please follow the following instruction: use the special test modes ?vco max? and ?vco min? to determine the optimum inductor value. ?vco max? represents the high end of the vco range and ?vco min? represents the low end of the vco range. the output frequency in the ?vco max? and ?vco min? test modes is vco/16. this means that the output frequencies are around the crystal frequency that will be used. the optimu m inductor value is where the target crystal frequency is closest to the middle between the ?vco max? and ?vco mi n? output frequencies. in th is case the vc o will lock in the middle of its tuning range with maximum margin on either side.
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 4 electrical specifications 1. absolute maximum ratings parameters symbol min. max. units supply voltage v dd 4.6 v input voltage, dc v i -0.5 v dd +0.5 v output voltage, dc v o -0.5 v dd +0.5 v storage temperature t s -65 150 c ambient operating temperature* t a -40 85 c junction temperature t j 125 c lead temperature (soldering, 10s) 260 c esd protection, human body model 2 kv exposure of the device under conditions beyond the limits specif ied by maximum ratings for extended periods may cause permanent damage to the device and affect product reliability. thes e conditions represent a stress rating on ly, and functional operations of the devic e at these or any other conditions above the operational limits noted in this spec ification is not implied. * note : operating temperature is guaranteed by design for all parts (commercial and industrial), but tested for commercial grade only . 2. crystal specifications parameters symbol conditions min. typ. max. units crystal resonator frequency f xin parallel fundamental mode 19 40 mhz at vcon = 0v 17.7 at vcon = 1.65v 9.5 crystal loading rating c l (xtal) at vcon = 3.3v 5.4 pf crystal pullability c 0 /c 1 (xtal) at cut 250 - recommended esr r e at cut 30 note : crystal loading rating: the listed numbers are for the ic only. specify the crystal for the value at vcon = 1.65v and add the pcb & package parasitic. a round number (i.e. 12pf) can be achieved by adding ex ternal capacitors. try to add the same value to xin and xout, and please note, that frequency pulling and oscillator gain may decrease. 3. voltage control crystal oscillator parameters symbol conditions min. typ. max. units vcxo stabilization time * t vcxostb from power valid 10 ms vcxo tuning range f xin = 19 ? 40mhz; xtal c 0 /c 1 < 250 0v vcon 3.3v 500 ppm clk output pullability vcon=1.65v, 1.65v 200 ppm vcxo tuning characteristic 150 ppm/v pull range linearity 10 % vcon pin input impedance 60 80 k vcon modulation bw 0v vcon 3.3v, -3db 25 khz note: parameters denoted with an asterisk (*) represent nominal charac terization data and are not production tested to any specific limits.
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 5 4. general electrical specifications parameters symbol conditions min. typ. max. units 38mhz (preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 6 8. lvds electrical characteristics parameters symbol conditions min. typ. max. units output differential voltage v od 247 355 454 mv v dd magnitude change v od -50 50 mv output high voltage v oh 1.4 1.6 v output low voltage v ol 0.9 1.1 v offset voltage v os 1.125 1.2 1.375 v offset magnitude change v os r l = 100 (see figure) 0 3 25 mv power-off leakage i oxd v out = v dd or gnd v dd = 0v 1 10 ua output short circuit current i osd -5.7 -8 ma 9. lvds switching characteristics parameters symbol conditions min. typ. max. units differential clock rise time t r 0.2 0.7 1.0 ns differential clock fall time t f r l = 100 c l = 10 pf (see figure) 0.2 0.7 1.0 ns out out v od v os 50 50 out v diff r l = 100 c l = 10pf c l = 10pf lvds switching test circuit lvds levels test circuit lvds transistion time waveform out out out 0v (differential) 0v 20% 80% 20% 80% t r t f v diff
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 7 10. pecl electrical characteristics parameters symbol conditions min. max. units output high voltage v oh v dd ? 1.025 v output low voltage v ol r l = 50 to (v dd ? 2v) (see figure) v dd ? 1.620 v 11. pecl switching characteristics parameters symbol freq. condit ions min. typ. max. units clock rise & fall times <150mhz 0.2 0.5 0.7 clock rise & fall times t r & t f >150mhz <320mhz @20/80% - pecl @80/20% - pecl 0.2 0.4 0.55 ns out out 50 50 pecl levels test circuit pecl transistion time waveform out out 50% 20% 80% t r t f vdd duty cycle 45 - 55% 55 - 45% 50% out out t skew pecl output skew 2.0v
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 8 layout recommendations pcb layout considerations fo r performance optimization the following guidelines are to assist you with a performance optimized pcb design: - keep all the pcb traces to pl580 as short as possible, as well as keepi ng all other traces as far away from it as possible. - place the crystal as close as possible to both crystal pins of the device. this will reduce the cross-talk between the crystal and the other signals. - separate crystal pin traces from the other signals on the pcb, but allow ample distance between the two crystal pin traces. - place a 0.01f~0.1f decoupling capacitor between vdd and gnd, on the component side of the pcb, close to the vdd pin. it is not recommended to place this component on the backside of the pcb. going through vias will reduce the signal integrity, causing additional jitter and phase noise. - it is highly recommended to keep the vdd and gnd traces as short as possible. - when connecting long traces (> 1 inch) to a cmos output, it is important to design the traces as a transmission line or ?stripline?, to avoid reflections or ringing. in this case, the cmos output needs to be matched to the trace impedance. usually ?striplines? are designed for 50 ? impedance and cmos outputs usually have lower than 50 ? impedance so matching can be achieved by adding a resistor in series with the cmos output pin to the ?stripline? trace. - please contact phaselink for the application note on how to design outputs driving long traces or the gerber files for the pl580 layout.
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 9 package information 16-pin ssop c l a eh d a1 e b 16 pin tssop ( mm ) symbol min. max. a - 1.20 a1 0.05 0.15 b0.190.30 c0.090.20 d4.905.10 e4.304.50 h 6.40 bsc l0.450.75 e 0.65 bsc 16-pin 3x3 qfn
(preliminary) pl580-35/37/38/39 38mhz-320mhz low phase noise vcxo 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 12/14/06 page 10 ordering information phaselink corporation, reserves the right to make changes in its products or specifications, or bo th at any time without notice . the information furnished by phaselink is believed to be accurate and reliable. however, phaselink makes no guarantee or warranty concerning t he accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselink?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of phaselink corporation. for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination of the following: device number, package type and operating temperature range pl580-3x x c l r order number marking package option pl580-35ocl p580-35ocl tssop - tube (green package) pl580-35ocl-r p580-35ocl tssop - tape & reel (green package) pl580-35qcl p580-35qcl qfn - tube (green package) pl580-35qcl-r p580-35qcl qfn - tape & reel (green package) pl580-37ocl p580-37ocl tssop - tube (green package) pl580-37ocl-r p580-37ocl tssop - tape & reel (green package) pl580-37qcl p580-37qcl qfn - tube (green package) PL580-37QCL-R p580-37qcl qfn - tape & reel (green package) pl580-38ocl p580-38ocl tssop - tube (green package) pl580-38ocl-r p580-38ocl tssop - tape & reel (green package) pl580-38qcl p580-38qcl qfn - tube (green package) pl580-38qcl-r p580-38qcl qfn - tape & reel (green package) pl580-39ocl p580-39ocl tssop - tube (green package) pl580-39ocl-r p580-39ocl tssop - tape & reel (green package) pl580-39qcl p580-39qcl qfn - tube (green package) pl580-39qcl-r p580-39qcl qfn - tape & reel (green package) temperature c=commercial i=industral package type o=tssop-16l q= qfn-16l l= green package none= regular package r= tape & reel none= tube part number
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