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| em78p447s otp rom em78p447s 8-bit micro-controller version 1.2
em78p447s otp rom specification revision history version content 1 . 0 i n i t i a l v e r s i o n 1.1 cha nge po wer on reset co ntent 06/25/2003 1.2 add the de vice cha r a c teri st ic at se ction 6 . 3 5/11/200 4 application note an-0 01: sev e n-s e gmen t and i/o port an-0 02: ke y s tro ke time s displa y e d b y se v e n-segment an-0 03: j u mping out of delay subr outine loop b y external ke y s troke an -0 04: le d w i th con t rol l ed rot a ting direc t ion an-0 05: sin g a song "dr a w " of em78 447 an-0 06: ste pping motor an-0 07: em7 8 p447s v . s. em78p44 7 on the dc cha r acteristic s and progr am timing an-0 08: abo u t em78p4 4 7 s sleep2 mode se tting this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 2 em78p447s otp rom 1. general description em78p44 7s i s a n 8 - bit mi crop ro ce ssor with lo w-po wer a nd high -speed cm os tech nolo g y. it is e quip ped with 4k*13-b i ts electrical one time prog ramm abl e read only memory (o tp-rom). it provides a prote c tio n bit to preve n t user? s cod e in the otp memo ry from being intrud e d . seven option bits a r e also avail able to meet user? s re quireme nts. with its otp-rom featu r e, the em78p 4 47s is abl e to offer a conve n i ent way of developi ng a nd verifying use r ? s pro g ra ms. more ove r , use r can ta ke adva n tage of elan wri ter to easily p r og ram hi s d e velopm ent cod e . this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 3 em78p447s otp rom 2. features ? operatin g voltage rang e: 2.3v~5.5v. ? operatin g temperature ra nge: 0 em78p447s otp rom ? 99.9% singl e instructio n cycle comm a nds ? the transi e nt point of system freq uen cy betwe en hxt and lxt is aroun d 400 khz this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 5 em78p447s otp rom 3. pin assignment tc c vdd nc vss /int p5 0 p5 1 p5 3 p6 0 p6 1 p6 2 p6 3 p6 4 p5 2 /reset os ci os co p7 7 p7 6 p7 5 p7 4 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p7 3 e m 7 8 p447sbp em78p447sbwm 1 2 3 4 5 6 7 8 9 10 11 12 14 13 26 25 24 23 22 21 20 19 18 17 29 30 27 28 p5 5 p5 4 p5 6 p5 7 15 16 31 32 tc c vdd nc vs s /int p5 0 p5 1 p5 3 p6 0 p6 1 p6 2 p6 3 p6 4 p5 2 /reset os ci os co p77 p76 p75 p74 p72 p71 p70 p67 p66 p65 p73 em78p447sap e m 78 p447sam 1 2 3 4 5 6 7 8 9 10 11 12 14 13 26 25 24 23 22 21 20 19 18 17 16 15 27 28 EM78P447SAS tc c vd d vss /in t p5 0 p5 1 p5 3 p6 0 p6 1 p6 2 p6 3 p6 4 p5 2 /reset os ci os co p7 7 p7 6 p7 5 p7 4 p7 2 p7 1 p7 0 p6 7 p6 6 p6 5 p7 3 1 2 3 4 5 6 7 8 9 10 11 12 14 13 26 25 24 23 22 21 20 19 18 17 16 15 27 28 vss fig. 1 pin a ssignmen t t a b l e 1 em78p447s a p an d em78p4 47s a m pin descrip tio n symbol pin no. type fun c tion vdd 2 - * powe r su pp ly . o s c i 2 7 i * xtal type: cry s tal input termin al or ext e rn al clo c k in put pin. * rc type: rc oscillator input pin. o s c o 2 6 i / o * xtal type: output terminal for c r ys tal oscill ator or extern al clock in put pin. * rc type: instru ction clo c k output. * external clo ck sign al inpu t. t c c 1 i * the re al time clo ck/ cou n ter (with sch m itt trigger inp u t pin) mu st be tied to vdd or vss if not in us e. / r e s e t 2 8 i * input pin with schmitt trigger. if this pi n remain s at lo gic low, the controll er will also rem a in in reset condition. p50~p5 3 6~9 i/o * p50~p5 3 are bi-di r e c tion al i/o pins. p60~p6 7 1 0 ~ 1 7 i / o * p60~p6 7 are bi-di r e c tion al i/o pins. these ca n be pulled - hi gh in ternally by softwa r e control. p70~p7 7 1 8 ~ 2 5 i / o * p70~p7 7 are bi-di r e c tion al i/o pins. * p74~p7 5 can be pull e d - high inte rnall y by software control. * p76~p7 7 can have op en -drain outp u t by softwa r e control. * p70 and p7 1 can al so b e defined a s the r-option pi ns. /int 5 i * external interrupt pin trig gered by falling edg e. v s s 4 - * g r o u n d . nc 3 - * no conn ecti on. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 6 em78p447s otp rom t a b l e 2 em78p447s a s pin desc rip t io n symbol pin no. type fun c tion vdd 3 - * powe r su pp ly . o s c i 2 7 i * xtal type: cry s tal input termin al or ext e rn al clo c k in put pin. * rc type: rc oscillator input pin. o s c o 2 6 i / o * xtal type: output terminal for c r ys tal oscill ator or extern al clock in put pin. * rc type: instru ction clo c k output. * external clo ck sign al inpu t. t c c 2 i * the re al time clo ck/ cou n ter (with sch m itt trigger inp u t pin) mu st be tied to vdd or vss if not in us e. / r e s e t 2 8 i * input pin with schmitt trigger. if this pi n remain s at lo gic low, the controll er will also rem a in in reset condition. p50~p5 3 5~8 i/o * p50~p5 3 are bi-di r e c tion al i/o pins. p60~p6 7 9~1 3 , 15~17 i/o * p60~p6 7 are bi-di r e c tion al i/o pins. these ca n be pulled -hig h intern ally by softwa r e control. p70~p7 7 1 8 ~ 2 5 i / o * p70~p7 7 are bi-di r e c tion al i/o pins. * p74~p7 5 can be pull ed -high inte rnall y by software control. * p76~p7 7 can have op en -drain outp u t by softwa r e control. * p70 and p7 1 can al so b e defined a s the r-option pi ns. /int 4 i * external interrupt pin trig gered by falling edg e. v s s 1 , 1 4 - * g r o u n d . t a b l e 3 em78p447s bp an d em78p4 47sb w m pin descr ip tion symbol pin no. type fun c tion vdd 4 - * powe r su pp ly . o s c i 2 9 i * xtal type: cry s tal input termin al or ext e rn al clo c k in put pin. * rc type: rc oscillator input pin. o s c o 2 8 i / o * xtal type: output termin al for cry s tal oscillato r or e x ternal cl ock i nput pin. * rc type: instru ction clo c k output. * external clo ck sign al inpu t. t c c 3 i * the re al time clo ck/ cou n ter (with schm itt trigger inpu t pin), must b e tied to vdd or vs s if not in use. / r e s e t 3 0 i * input pin wit h schmitt trig ger. if this pi n remai n s at logic lo w, the controll er will keep in reset condition. p50~p5 7 8~ 11,2~1, 32~31 i/o * p50~p5 7 are bi-di r e c tion al i/o pins. p60~p6 7 1 2 ~ 1 9 i / o * p60~p6 7 are bi-di r e c tion al i/o pins. t hese can be pulled -hig h i n tern ally by softwa r e control. p70~p7 7 2 0 ~ 2 7 i / o * p70~p7 7 are bi-di r e c tion al i/o pins. * p74~p7 5 can be pull e d - high inte rnall y by software control. * p76~p7 7 can have op en -drain outp u t by softwa r e control. * p70 and p7 1 can al so b e defined a s the r-option pi ns. /int 7 i * external interrupt pin trig gered by falling edg e. v s s 6 - * g r o u n d . nc 5 - * no conn ecti on. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 7 em78p447s otp rom 4. function description io c 5 r5 p 5 0 p 5 1 p 5 2 p 5 3 p 5 4 p 5 5 p 5 6 p 5 7 io c 6 r6 io c 7 r7 acc r3 stac k 1 stac k 2 stac k 3 stac k 4 stac k 5 p c ro m i n st r u ct i o n re g i s t e r i n st r u ct i o n d e c oder al u in te r r u p t c ont r o l r4 ra m wd t t i m e r p r e sca l e r o s c illa t o r / t i m i n g c ont r o l wd t ti m e - out r1 ( t c c ) s l eep & wa k e c ont r o l da t a & co nt ro l b u s /in t tc c os c i os c o / r e set p 6 0 p 6 1 p 6 2 p 6 3 p 6 4 p 6 5 p 6 6 p 6 7 p 7 0 p 7 1 p 7 2 p 7 3 p 7 4 p 7 5 p 7 6 p 7 7 fig. 2 functional block diagram 4.1 operational registers 1. r0 (indirect addressing register) r0 i s n o t a p h ysically impl emente d regi ster. its m a jo r fun c tion i s t o act as an i ndirect a d d r e ssi ng pointe r . any instructio n usi ng r0 a s a p o inter a c tuall y acce sse s d a ta pointed b y the ram select regi ste r (r4). 2. r1 (time clock /counter) ? increa sed b y an external sign al edg e, whi c h is def in ed by te bit ( c o n t-4) thro ugh the tcc pin, or by t he inst r u ct io n cy cle clo ck. ? writable a n d rea dabl e as any other re giste r s. ? defined by resetting pab (cont - 3). ? the pres caler is ass i gned to tcc, if the pab bit (cont-3) is reset. ? the contents of the prescaler counter will be cl ea red only when tcc regi ster is written a value. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 8 em78p447s otp rom 3. r2 (program counter) & sta ck ? depe ndin g on the devi c e type, r2 and hard w a r e st a ck are 10-bit wide. th e structu r e is depi cted i n fig.3. ? generatin g 1024 u 1 3 bits on-chi p otp rom ad dresses to the relati ve prog rammi ng instructio n cod e s. one p r og ram page is 1 024 words lo ng. ? r2 is set a s all "0"s wh en unde r rese t con d ition. ? "jmp" instru ction all o ws d i re ct loadin g of the lo wer 1 0 pro g ram co unter bit s . th us, "jmp" all o ws pc to go to any locatio n within a page. ? "call" in struction l oad s t he lo we r 10 b i ts of the pc, and the n pc+1 i s pu sh ed into the sta ck. thus, the sub r o u tin e entry add re ss can b e located anywhe r e within a pa ge. ? "ret" ("re tl k", "re t i") in stru ction l oad s the pr o g ram counte r with the co n t ents of the t op-l e vel st ac k. ? "add r2,a" allows the co ntents of ?a? to be a dde d to the current pc, and the ninth an d tent h bits of the pc are cl eared. ? "mov r2,a" allows to loa d an ad dress from the "a" registe r to the l o we r 8 bit s of the pc, and t he ninth and tenth bits of the pc are clea re d. ? any instructi on that writes to r2 (e .g. " a dd r2,a", " m ov r2,a", " b c r2,6", ? ? ? ? ? ) will cause the ninth and tenth bit s (a8~a9 ) of the pc to be clea re d. th u s , the comp ute d jump i s limi t ed to the first 256 locatio n s of a page. ? a ll inst ru ct io n ar e si ngle in st ru ct ion cy cl e (f cl k/ 2 o r fcl k /4) exce pt for the in structi on that woul d cha n g e the conte n ts of r2. such i n structio n will need on e mo re in stru ction cycle. a 7 ~ a0 o n -ch i p p r ogr am me m o r y 000 h fffh 001 h 0 02h fig. 3 program coun ter organi zation this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 9 em78p447s otp rom aaddr ess r p a g e register s i o c pa g e r egisters 00 r0 (indir ect addr essing r e gister) r eserv e 01 r1 (t ime clock c o unter ) cont (c ontr ol r egister) 02 r2 (p rogra m co unter) r eserv e 03 r3 (s tatus r e gister) r eserv e 04 r4 (r am s e lect r egister) r eserv e 05 r5 (p ort5) io c 5 (i /o port control r egister) 06 r6 (p ort6) io c 6 (i /o port control r egister) 07 r7 (p ort7) io c 7 (i /o port control r egister) 0 8 g e neral r e gister r e serv e 0 9 g e neral r e gister r e serv e 0a g e neral r e gister r e serv e 0b g e neral r e gister io cb (w ake - up c ontr o l re gis t er for p o rt6 ) 0c g e neral r e gister r e v e rse 0d g e neral r e gister r e v e rse 0e g e neral r e gister io c e (w d t ,s lee p 2 ,o pen d r ain,r - o p tion c ontro l register ) 0f g e neral r e gister io c f (i nterrup t m a sk r egister) 10 U r3f (inter rupt s t atus r egister) fig. 4 dat a m e mor y configuration this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 10 em78p447s otp rom 4. r3 (status register) 7 6 5 4 3 2 1 0 g p p s 1 p s 0 t p z d c c ? bit 7 (gp) gene ral read/ write bit. ? bits 6 (ps1 ) ~ 5 (ps0 ) page selec t bits . ps1~ ps0 are us ed to pre-s e lec t a program memo ry page. whe n exe c uti ng a " j mp", "call", o r oth e r in stru ct ion s which cau s es the progra m co unter to cha nge (e.g. mov r2 , a), ps1~ps0 are load ed into the 11th and 12th bits o f the program cou n ter an d select one of the a v ailable pro g r am m e mo ry pag es. note that ret (retl, reti) i n structio n do es not cha nge th e ps0~ps1 bits. that is, the return w ill always be to the page from wh ere the sub r o u tine wa s call ed, re gardle ss of th e ps1~ps0 b i ts cu rre nt set t ing. ps1 ps0 prog ram me mory pag e [address] 0 0 page 0 [000 -3ff] 0 1 page 1 [400 -7ff] 1 0 page 2 [800 -bff] 1 1 page 3 [c0 0 -fff] ? bit 4 (t ) time-out bit. s e t to 1 with t he "slep" a nd "wdt c" comman d s, or during po we r up, and res e t to 0 with the wdt time-out. ? bit 3 (p) powe r do wn bi t. set to 1 during p o wer o n or by a "wdtc" comma n d and re set to 0 by a "slep" command. ? bit 2 (z) zero flag. set to "1" if the res u lt of an arithmetic or lo gic o peration is ze ro. ? bit 1 (d c) a u xiliary carry flag. ? bit 0 (c ) carry flag 5. r4 (ram select r e gister) ? b i t s 7~6 de termine whi c h ban k is a c tivated amon g the 4 ban ks. ? b i t s 5~0 are use d to sel e ct the re gist ers (ad d re ss: 00~3f) in the indire ct add ressing m ode. ? if no indire ct addressin g is us ed, the rsr can b e used a s an 8-bi t gen eral-purpo se re ad /writer regi ster. ? see the con f iguratio n of the data mem o ry in fig. 4. 6. r5~r7 (port 5 ~ p o rt7) ? r5, r6 and r7 a r e i/o re giste r s 7. r8~r1f and r20~r3e (general purpose register) ? r8~r1f, an d r20 ~ r3e (i nclu ding ba n ks 0 ~ 3 ) are g ene ral-pu rpo s e regi sters. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 11 em78p447s otp rom 8. r3f (interrupt status register) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - e x i f - - t c i f ? bit 3 (exif) external interru pt flag. set by falling edge on /int pi n, flag clea re d by softwa r e ? bit 0 (tcif ) the tcc ove r flow inte rrupt flag. set as tcc overflo w s; flag clea re d by softwa r e . ? bits 1, 2, 4~7 a r e not u s ed and rea d are a s ?0 ?. ? "1" means i n terrupt re qu est, "0" mean s non -inte r ru pt. ? r3f ca n be clea re d by instru ction, but can not be set by instru ctio n. ? iocf is the interrupt mask regis t er. ? note that re ading r3f wil l obtain the re sult of the r3 f "logic and" and iocf. 4.2 special purpose registers 1. a (accumulator) ? internal dat a tran sfer, or instructio n op era nd hol ding . ? it cannot be add re ssed. 2. cont (control register) 7 6 5 4 3 2 1 0 / p h e n / i n t t s t e p a b p s r 2 p s r 1 p s r 0 ? bit 7 (/phen) control bit used to en ab le the pull-hig h of p60~p67 , p74 and p75 pins 0: enable inte rnal p u ll-hi gh. 1: disa ble int e rn al pull-hig h . ? cont regi ster is both rea dable a nd wri t able. ? bit 6 (/int) interru pt ena ble flag 0: masked by disi or hard w a r e interru p t 1: enable d by eni/reti instructio ns ? bit 5 (ts) t cc sign al so urce 0: int e rnal in s t ruct io n cy cl e clo ck 1: transitio n o n tcc pin ? bit 4 (te) t cc sign al ed ge 0: increment i f the transitio n from low to high takes pl ace o n tcc pin 1: increment i f the transitio n from high to low take s pla c e on t c c pi n ? bit 3 (pa b ) prescal e r a ssignme n t bit. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 12 em78p447s otp rom 0: tcc 1: wdt ? bit 2 (psr2 ) ~ bit 0 (psr0 ) tcc/wdt pre s cale r bi ts. psr2 psr1 psr0 tc c rate wd t rate 0 0 0 1 : 2 1 : 1 0 0 1 1 : 4 1 : 2 0 1 0 1 : 8 1 : 4 0 1 1 1 : 1 6 1 : 8 1 0 0 1 : 3 2 1 : 1 6 1 0 1 1 : 6 4 1 : 3 2 1 1 0 1 : 1 2 8 1 : 6 4 1 1 1 1 : 2 5 6 1 : 1 2 8 3. ioc5 ~ ioc7 (i/o p o rt control register) ? "1" put the relative i/o pin into high imp edan ce, while "0" defines the rel a tive i/o pin as o u tp ut. ? ioc5 and ioc7 regi sters are both re adabl e and writable. 4. iocb (wake-up control register for port6) 7 6 5 4 3 2 1 0 / w u e 7 / w u e 6 / w u e 5 / w u e 4 / w u e 3 / w u e 2 / w u e 1 / w u e 0 ? bit 7 (/wue 7 ) control bit is used to en able the wake-u p functio n of p67 pin. ? bit 6 (/wue 6 ) control bit is used to en able the wake-u p functio n of p66 pin. ? bit 5 (/wue 5 ) control bit is used to en able the wake-u p functio n of p65 pin. ? bit 4 (/wue 4 ) control bit is used to en able the wake-u p functio n of p64 pin. ? bit 3 (/wue 3 ) control bit is used to en able the wake-u p functio n of p63 pin. ? bit 2 (/wue 2 ) control bit is used to en able the wake-u p functio n of p62 pin. ? bit 1 (/wue 1 ) control bit is used to en able the wake-u p functio n of p61 pin. ? bit 0 (/wue 0 ) control bit is used to en able the wake-u p functio n of p60 pin. 0: enable inte rnal wa ke-up. 1: disa ble int e rn al wa ke -u p. ? iocb regi ster is both rea dable a nd wri t able. 5. ioce ( w dt control register) 7 6 5 4 3 2 1 0 - o d e wd t e s l p c ro c - - / w u e ? bit 6 (ode ) control bit is use d to enabl e the open -d rain of p76 an d p77 pin s 0: disa ble op en-drai n outp u t. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 13 em78p447s otp rom 1: enable op en-drai n outp u t. the o d e bit can b e re ad a nd written. ? bit 5 (w dt e) cont rol bit use d to enabl e watchdo g timer. the wdte bi t is useful o n l y when enwdt, the co de option bit, is "0". it is only when the e n wdt bit is "0" that wdte bit. is able to disabl ed/ena bled th e wdt. 0: disa ble wdt. 1: enable wdt. the wdte bi t is not u s e d if enwdt, the co de opti o n bit enwdt, i s "1". that i s , if the enwdt bit is "1", wdt i s always di sa b l ed no ma tter what the wdte bit status is. the wdte bi t can be read and written. ? bit 4 (slpc) thi s bit is set by hardware at the low le vel trigger of wake -up si gnal and is cl eared by software. slpc is used to control the oscillator op eration. the oscillator is disabl ed (oscill ator is stopped, and the controlle r enters into sleep2 mode) on the hi gh-to-low transition and i s enabled (controll er is awakened from sleep2 m ode) on low-t o -hi gh transition. in order to ensure the stable output of the oscillato r, once the oscillato r is enable d again, there is a delay for approximately 1 8 ms 1 (o scill ator sta r t-up time r, o s t) befo r e th e next inst ruction of the program is exe c uted. th e o s t is alway s a c tivated by a wa ke-u p event from sle ep mo de re ga rdle ss of the cod e option bit enwdt status i s "0" o r othe rwi s e. a fter wa kin g up , the wdt i s e nable d if the cod e optio n enwdt i s "1" . the block diagram of sleep2 mode and wa ke-up invoked by an input trigger is depicted in fig. 5. the slpc bit can be re ad an d written. ? bit 3 (ro c ) roc is used for the r-option. setting roc to "1" will enabl e the status of r-o p tion pins (p70, p71 ) for the co ntroll e r to rea d . cle a rin g ro c wi ll disabl e the r-opti on fun c tion. otherwise, the r-option function is introduc ed. us ers mus t c o nnec t the p71 pin or/and p70 pin to vss with a 430k ? bit 0 (/wue ) co ntrol bit is used to ena ble the wa ke -up functio n of p74 and p75 . 0: enable the wake-up fun c tion. 1: disa ble the wake-up fun c tion. the /wue bit can be rea d and written. ? bits 1~2, an d 7 not used. 1 em78p447s otp rom 6. iocf (interrupt mask register) 7 6 5 4 3 2 1 0 - - - - e x i e - - t c i e ? bit 3 (exie) exif interru pt enable bit. 0: disabl e exif interru pt 1: enable exif interrupt ? bit 0 (tcie) tcif interru p t enable bit. 0: disabl e tcif interru pt 1: enable t c i f interrupt ? bits 1, 2 and 4~7 not used. ? individual interru pt is ena bled by settin g its asso ciat ed co ntrol bit in the iocf to "1". ? global inte rrupt is en able d by the eni instructio n an d is di sabl ed by the disi instru ction (refe r to fig. 9). ? iocf regi ster is b o th rea dable a nd wri t able. osc i llator en a b le d i s a b l e rese t qd q cl k pr cl cl ea r fr o m s / w se t 2 /w u e 0 /w u e 1 /w u e 7 vcc p6 0 ~ p 6 7 vcc /wue p7 4 ~ p 7 5 /phe n 8 fig. 5 sleep mode and w ake -up circ uit s on i/o port s bloc k di agram this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 15 em78p447s otp rom 4.3 tcc/wdt & prescaler an 8-bit co unte r is avail a b l e as prescal e r for the t cc or w d t . t he prescal e r is ava ila ble f o r either th e t cc or w d t onl y at an y g i v en time, and th e pab bit of the cont regi ster is used to d e termine th e pr escaler ass i g n m ent. t he psr0~ psr2 b i ts determine th e ratio. t he prescaler is cl eare d each time th e instruction is w r itten to t cc u nder t c c mode. t he w d t and presc a le r, w h en ass i gn ed to w d t mo de, are cl eare d b y th e ?w dt c ? or ?slep? ins t ructions . f i g. 6 depicts the circuit di agr am of t cc/w d t . ? r1 (t cc) is a n 8-bit timer/counter . t he clock source of t cc can be inter n al or ext e rna l clock input (ed g e select abl e from t cc pin). if t cc signa l s ource is from i n ternal c l ock, t cc w i ll i n cre a se b y 1 at ev er y i n struction c y c l e ( w ith o u t prescal e r). ref e rring to f i g. 6, clk= f o sc/2 o r clk= f o sc/ 4 selectio n is det ermine d b y t h e code optio n bit cl k st atus. clk= fosc/2 is used if clk bit is "0", and clk= f o sc /4 is used if clk bit is "1". if t cc sign al sour ce comes from exter nal c l ock inp u t, t c c is increas ed b y 1 at ever y fal l i ng e dge or ris i ng ed ge of t cc pin. ? t he w a tc hd o g timer is a free runni ng on-ch i p rc osc ill ator . t he w d t w i l l keep on ru nn in g eve n af ter th e oscil l ator driver h a s b e e n turned of f (i.e. i n sle ep mo de). durin g n o rmal oper ation or sl e ep mo de, a w d t time-out (if en able d ) w i ll c ause th e device to r e set . t he w d t ca n be e n a b le d o r disab l ed an y time duri ng n o r m al mod e b y s o f t w a r e programm i ng. refer to w d t e bit of ioce register . w i thout prescaler , the w d t time-out pe riod is appr o x i m atel y 18 ms 1 (default). wd t te tc c 8 - b i t c o u n ter 2 cy cles t cc( r 1 ) sync pin m x u m x u m x u 8 -to -1 m u x mux ts 0 ps r 0 ~ p s r 2 w d t tim e u o t pa b t c c o v erflo w in terru p t c l k ( = f os c / 2) pa b (in i o c e ) wd t e da t a bu s pa b 1 0 1 0 1 01 fig. 6 tcc a nd wdt blo ck diagr a m 1 em78p447s otp rom 4.4 i/o ports t he i/o registers, port 5, port 6, and po rt 7, are bi-dir ectio n a l tri-state i/o ports . t he functions of pu ll-hi gh, r-optio n, an d open-dr ain ca n be performe d internal l y b y c o nt and ioce respecti vel y . t here is in put status chan ge w a ke-u p function on port 6, p74, and p75. each i/o pin can be defined as "input" or "output" pin by the i/o control register (ioc5 ~ ioc7). t he i/o registers and i/o control r egisters are both readable and w r itable. t he i/o interface circuits for port 5 , port 6, and por t 7 are sho w n in f i gures. 7(a) a nd (b) resp ecti vel y . pdr d q q cl k d pc w r pd w r q q cl k d pr cl po r t 0 1 m u x io d pcr d pr cl fig. 7 (a) t h e i/o p o rt and i / o control register circuit p drd q q cl k d pc w r pd w r q q cl k d 0 1 m u x io d ro c vc c we a k l y pull - u p po rt re x* *t he r e x i s 43 0k oh m e x t e rna l res i st o r p crd pr cl pr cl fig.7(b) the i/o port w i th r-o p tion (p70, p71) cir c uit this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 17 em78p447s otp rom 4.5 reset and wake-up 1. reset a reset is ini t iated by one of the follo w i ng events- (1) po we r on re set, or (2) /reset pin input ?low?, or (3) wdt timeout. (if enable d ) t he device is kept in a rese t c ondition for a perio d of app rox. 18ms 1 (one oscillator start-up timer peri o d ) after the reset is detected. once the reset o ccurs, the follo w ing functions are performed (refer to fig.8). ? the oscillat o r starts or is running ? the program counter (r2) is s e t to all "1". ? when po we r is switched on, bits 5~6 o f r3 and the uppe r 2 bits o f r4 are clea red. ? all i/o port pins a r e confi gured a s inpu t mode (hig h-i m ped an ce st ate). ? the watchd og timer an d pre s cale r are clea re d. ? upon po we r on, the bits 5~6 of r3 a r e clea re d. ? upon po we r on, the uppe r 2 bits of r4 are clea red. ? the bits of co nt re giste r are set to all "1" except bit 6 (int flag). ? iocb regist er is set to ?1? (disable p60 ~ p67 wake-up functio n ). ? bits 3 and 6 of ioce regi ster a r e cl ea red, and bits 0 , 4, and 5 are set to "1". ? bits 0 and 3 of r3f regi st er an d bits 0 and 3 of iocf regi sters are clea re d. t he sleep (po w e r do w n ) mo de is ass e rted b y e x ecuti ng the ?slep? ins t ruction. w h ile enterin g sle e p mode, w d t (i f ena ble d ) is cle a red b u t keeps on runn ing. t he control l er ca n be a w a k en ed b y - (1) external res e t input on /reset pin; (2) wd t time-out (if ena ble d ) t he above t w o cases w ill ca us e the controll er em78p44 7s to reset. t he t and p flags of r3 can be us e d to determine the source of the r e set ( w a k e- up) . in add ition to t he b a sic slee p1 mode, em78p4 47s h a s anoth e r sle ep mode (d esi gna ted as sleep 2 mode an d i s invoked by clearing the ioce register ?slp c? bit). in the sleep2 mode, the contro ller can be a w akened by - 1 note: vdd = 5v, set up time perio d = 16.2m s 30% vdd = 3v, set up time perio d = 19.6m s 30% this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 18 em78p447s otp rom (a) any of the wake-u p pin s is ?0? a s illust rated in fig u re. 5. upon wa king, the cont rolle r will cont inue to execute the su cceedi n g addre s s. unde r th is case, before enterin g sleep2 mode, the wa ke -up fun c tion of the trig ger sou r ces (p60~p6 7 and p74~p75 ) sh ould be sel e cted (e.g., inpu t pin) an d ena bled (e.g., pu ll-hig h , wake-up cont rol). it should be n o ted that afte r wa king up, the wdt is enab led if the code option bit enwdt is ?0?. the wdt operatio n (to be enabled or disa bled ) sho u ld be ap prop riately co ntrol l ed by softwa r e after waki n g up. (b) wdt time-out (if enabled) or external reset input on /reset pi n will trigger a cont roller reset. table 4 us a g e of sleep1 and sleep2 mode usage of sle ep1 an d slee p2 mod e s l e e p 2 s l e e p 1 (a) before sleep (a) before sleep 1. set port6 or p74 or p75 i nput 1. execute slep instru cti on 2. enable pull-hi gh and set wdt pre s cal e r over 1:1 (set co nt.7 and cont.3 ~ co nt. 0 ) 3. enable wa ke -up (s et iocb or ioce.0 ) 4. execute seep2 (set ioce.4) (b) after w a k e -u p (b) after w a k e -u p 1. next ins t ruc t ion 1. res e t 2. disa ble wake -u p 3. disa ble wdt (set ioce.5) if port6 input status cha n g ed wa ke -up i s use d to wake -up the em78p44 7s (ca s e [a] above), the following inst ructions must be ex ecuted before enteri ng sleep2 mode: mov a, @1111 111 1b ; set port6 input i o w r 6 mov a, @0xxx1010b ; set port6 pull-hig h , wdt pre s cale r, pre s cale r must set over 1:1 co nt w mov a, @0000 000 0b ; enable port 6 wa ke -up fu nction i o w r b mov a, @xx00xxx1b ; enable sleep2 iow re after wak e - u p n o p mov a, @1111 111 1b ; disabl e port 6 wa ke -up fu nction i o w r b mov a, @ xx01xxx1b ; disabl e wdt iow re note: after waki ng up from the s l eep2 mode, wdt is au tomatically enabled. the wdt enabl ed/di sabled operation after waking up from sleep2 mode shou ld be appropriat e ly def ined in the software. to avoid rese t from occu rri ng whe n the port6 statu s chang ed interrupt enters into interru pt vector or is used to wa ke -up the m c u, the wdt p r e s caler m u st be set above 1:1 ratio. this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 19 em78p447s otp rom table 5 the summar y of the initializ ed register v a lues address name reset t y pe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 b i t n a m e c57 c56 c55 c54 c53 c52 c51 c50 t y p e a b a b a b a b - - - - n / a i o c 5 po w e r - o n 0 1 0 1 0 1 0 1 1 1 1 1 /reset a n d wdt 0 1 0 1 0 1 0 1 1 1 1 1 w a ke-up from pin ch ang e 0 p 0 p 0 p 0 p p p p p b i t n a m e c67 c66 c65 c64 c63 c62 c61 c60 n / a i o c 6 po w e r - o n 1 1 1 1 1 1 1 1 /reset a n d wdt 1 1 1 1 1 1 1 1 wake-up from pin change p p p p p p p p b i t n a m e c77 c76 c75 c74 c73 c72 c71 c70 n / a i o c 7 po w e r - o n 1 1 1 1 1 1 1 1 /reset a n d wdt 1 1 1 1 1 1 1 1 wake-up from pin change p p p p p p p p b i t n a m e /phen /in t ts te pab psr2 psr1 psr0 n / a cont po w e r - o n 1 0 1 1 1 1 1 1 /reset a n d wdt 1 p 1 1 1 1 1 1 wake-up from pin change p p p p p p p p b i t n a m e - - - - - - - - 0 x 0 0 r 0 ( i a r ) po w e r - o n u u u u u u u u /reset a n d wdt p p p p p p p p wake-up from pin change p p p p p p p p b i t n a m e - - - - - - - - 0 x 0 1 r1(t c c ) po w e r - o n 0 0 0 0 0 0 0 0 /reset a n d wdt 0 0 0 0 0 0 0 0 wake-up from pin change p p p p p p p p b i t n a m e - - - - - - - - 0 x 0 2 r 2 ( p c ) po w e r - o n 1 1 1 1 1 1 1 1 /reset a n d wdt 1 1 1 1 1 1 1 1 w a ke-up from pin ch ang e **0/p **0/p **0/p **0/p **0/p **0/p **0/p **0/p b i t n a m e gp ps1 ps0 t p z dc c 0 x 0 3 r 3 ( s r ) po w e r - o n 0 0 0 1 1 u u u /reset and wdt 0 0 0 t t p p p wake-up from pin change p p p t t p p p b i t n a m e rsr.1 rsr.0 - - - - - - 0 x 0 4 r 4 ( r s r ) po w e r - o n 0 0 u u u u u u /reset a n d wdt 0 0 p p p p p p wake-up from pin change p p p p p p p p bit name p57 p56 p55 p54 p53 p52 p51 p50 0x05 r5(p5) po w e r-on u u u u u u u u /reset and wdt p p p p p p p p w a ke-up from pin ch ang e p p p p p p p p b i t n a m e p67 p66 p65 p64 p63 p62 p61 p60 0 x 0 6 r 6 ( p 6 ) po w e r - o n u u u u u u u u /reset a n d wdt p p p p p p p p wake-up from pin change p p p p p p p p b i t n a m e p77 p76 p75 p74 p73 p72 p71 p70 0 x 0 7 r 7 ( p 7 ) po w e r - o n u u u u u u u u /reset a n d wdt p p p p p p p p wake-up from pin change p p p p p p p p b i t n a m e x x x x ex if x x tc i f 0 x 3 f r 3 f ( i s r ) po w e r - o n u u u u 0 u u 0 /reset and wdt u u u u 0 u u 0 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 20 em78p447s otp rom wake-up from pin ch ang e u u u u p u u p b i t n a m e /wue7 /wue6 /wue5 /wue4 /wue3 /wue2 /wue1 /wue0 0 x 0 b i o c b po w e r - o n 1 1 1 1 1 1 1 1 /reset a n d wdt 1 1 1 1 1 1 1 1 wake-up from pin change p p p p p p p p b i t n a m e x ode wdt e slpc roc x x /wue 0 x 0 e i o c e po w e r - o n u 0 1 1 0 u u 1 /reset and wdt u 0 1 1 0 u u 1 w a ke-up from pin ch ang e u p 1 1 p u u p b i t n a m e x x x x ex ie x x tc i e 0 x 0 f i o c f po w e r - o n u u u u 0 u u 0 /reset and wdt u u u u 0 u u 0 wake-up from pin ch ang e u u u u p u u p b i t n a m e - - - - - - - - 0 x 0 8 r 8 po w e r - o n 0 0 0 0 0 0 0 0 /reset a n d wdt 0 0 0 0 0 0 0 0 wake-up from pin change p p p p p p p p b i t n a m e - - - - - - - - 0x09~ 0x3e r 9 ~ r 3 e po w e r - o n u u u u u u u u /reset a n d wdt p p p p p p p p wake-up from pin change p p p p p p p p ** to execute next instru ction after t he ?slpc? bit sta t us of ioce regist e r bei ng on high -to-l o w tran sition. x: not used. u: un kn own or d on?t care. -: not d e fi ned . p: previous value b e fore re set. t: che ck tabl e 6 2. the status of rst, t, and p of status register a reset condition is in itiate d b y o ne of the follo w i n g eve n ts: 1. a power-o n con d ition, 2. a high-low-high pul se on /reset pin, and 3. watch dog timer time-o ut. t he values of t and p (listed in t able 5 bel o w ) ar e use d to verif y th e event that triggered t he proc essor to w a ke u p . t able 6 sho w s the events that ma y affect the status of t an d p. table 6 the values of rs t, t and p after reset re set type t p powe r on 1 1 /reset during operating mode *p *p /reset wake-up during s l eep1 mode 1 0 /reset wake-up during s l eep2 mode *p *p wdt duri ng ope r ating mo de 0 *p wdt wa ke -u p duri ng sle ep1 mode 0 0 wdt wa ke -u p duri ng sle ep2 mode 0 *p wake-up on pin change during sleep2 mode *p *p *p: previous status b e fore re set this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 21 em78p447s otp rom table 7 the ev ents tha t ma y affe ct the t and p status event t p powe r on 1 1 wdtc in stru ction 1 1 wd t time-o u t 0 *p slep instru ction 1 0 wake-up on pin ch ange during sleep2 mode *p *p *p: previous value befo r e reset vo ltag e det ect o r p o w er- o n res e t wd te set u p tim e vd d dq cl k cl r cl k reset w d t ti m e o u t wd t /r eset os c ill ato r fig. 8 contr o ller rese t block diagr a m this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 22 em78p447s otp rom 4.6 interrupt t he em78p44 7s has t w o int e rrupts liste d b e lo w : (1) t c c overf l ow inte rru pt (2) external interrupt (/int pin). r3f is the inter r upt status regi ster that record s the interru pt requ ests in the relative flags/bits. iocf is the interrupt ma sk re g i ste r . t h e g l o b a l i n terru p t i s e n a b l e d by th e en i i n stru cti o n an d i s d i sa bl ed by the d i si i n stru ctio n . when one of th e inter r upts (ena bl ed) occurs, t he ne xt instructi on w ill b e fetched fr om addr ess 00 1h. once in th e interru p t service routi n e , the source of an inte rrupt c an be d e termin ed b y pol lin g the flag bits in r3f . t he interrupt flag bi t must be cleare d b y instructi o ns befor e le avi ng the interru p t service rout in e and befor e interrupts are e nabl ed to avoid r e cursiv e interrupts. t he flag (exce p t icif bit) in the interrupt st atus reg i ster (r3f ) is set reg a rdless of the status of its mask bit or the executi on of eni. note that the outco m e of r3f are the logic and of r 3 f and iocf (refer to f i g. 9). t he ret i instructio n end s the interrupt r outin e and ena bles the g l ob al inte rrupt (the e x ec utio n of eni). w hen an interr upt is generate d b y the int in struction (ena b l ed), the next i n struction w i l l be fetched from address 002h. in t eni/disi io d rf w r ioc f rd io cf w r ir q n ir q m rf r d io cf / r es et /i rqn vc c rf clk clk q q d p r l c _ p r l c q q _ d fig. 9 interrupt input circuit this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 23 em78p447s otp rom 4.7 oscillator 1. oscillator modes t he em78p447s can operat e in three different oscillat o r modes, i.e., high xt al (hxt ) o scillator mod e , lo w xt al (lxt ) oscill ator mode , and extern al rc oscill ator mode (erc) osci lla tor mod e . user can select o ne of them b y p r ogrammi ng ms, hlf and h l p i n the cod e option re gister. t able 7 dep icts ho w thes e thre e modes ar e d e fine d. t he maximum limit for operati onal fre que nci e s of cr y s tal/ re sonator u nder different v dds is listed in t abl e 8. table 8 osci llator modes define d b y ms and hlp mode ms hlf hlp erc(external rc o scill ator mode) 0 *x *x hxt(high xtal oscillator mode) 1 1 *x lxt(low xt al oscillator mode) 1 0 0 em78p447s otp rom os c i os c o e m 78p 447s e x t. c l o c k fig. 10 cr y s t a l/reso nato r circuit os c i os c o e m 7 8 p 447s c1 c2 xta l rs fig. 1 1 cr y s t a l/re s ona tor circuit table 10 capacitor selection guide for cr y s tal oscillator or ceramic resonator oscillator type freq uen cy m ode freq uen cy c1 (pf ) c2 (pf ) 455 khz 100 ~15 0 100 ~15 0 2.0 mhz 20~40 20~40 ce rami c re sonato r s hxt 4.0 mhz 10~30 10~30 32.768 k h z 2 5 1 5 100k h z 2 5 2 5 lxt 200k h z 2 5 2 5 455k h z 2 0 ~ 4 0 2 0 ~ 1 5 0 1 . 0 m h z 1 5 ~ 3 0 1 5 ~ 3 0 2 . 0 m h z 1 5 1 5 cry s tal oscill ator hxt 4 . 0 m h z 1 5 1 5 f o r some appli c ations that do not nee d a very precis e timin g ca lcul ation, the rc oscil l ato r (f ig. 15) offers a lot of cost savings. n e ver t heless, it sh ou ld be note d tha t the freque nc y of the rc osc i llator is influ e n c ed b y th e sup p l y volta ge, the values of the resistor (re x t), the capac itor (ce x t), and eve n b y th e op erat ion te mp eratur e. moreover, th e freque nc y al s o chan ges sli ghtl y from on e chi p to anoth e r du e to the manuf acturin g proce ss variatio n. in order to mai n tain a stab le s y stem freq uenc y, the val ues of t he ce xt shoul d not be l e ss t han 20 pf , and that the val u e of rext shou ld not be gr eater than 1 m ohm. if the y cann ot be kept in this range, the freque nc y is eas il y affected b y n o is e , this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 25 em78p447s otp rom humid it y , a nd l eaka ge. t he smaller the re xt in the rc oscillator, th e faster its frequenc y w i l l be. on the contrary, for ver y lo w re xt values, fo r instanc e, 1 k : , the oscillator becomes u n stable beca u se the nmos can not disch arge t he curre nt of the cap a citan c e correctly . based on th e abov e reas ons , it must be ke pt in min d that a ll of th e su pp l y v o lta ge, t he oper ation tem p erature, th e compo nents of the rc oscill at or, the packag e t y p e s, the w a y the pcb is l a yo ut, w i ll affect the s y stem fre que nc y . os c i em 78p 4 47s vc c re x t c ext fig. 12 external rc o sci llator mode circuit table 11 rc oscillator frequencies cex t rex t average f o sc 5v,25 q c average f o sc 3v,25 q c 3.3k 4.32 mhz 3.56 mhz 5.1k 2.83 mhz 2.8 mhz 1 0 k 1 . 6 2 m h z 1 . 5 7 m h z 20 pf 100 k 184 khz 187 khz 3.3k 1.39 mhz 1.35 mhz 5.1k 950 khz 930 khz 10k 500 khz 490 khz 100 pf 100 k 5 4 k h z 5 5 k h z 3.3k 580 khz 550 khz 5.1k 390 khz 380 khz 10k 200 khz 200 khz 300 pf 100 k 21 khz 21 khz em78p447s otp rom 4.8 code option register t he em78p44 7s has one co de option w o rd that is not a part of the normal pr ogram mem o r y . t he option bits cannot be access ed d u ring normal pr ogram e x ecuti on. bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ms /enw dt clk cs hlp hlp type - - - - - - ? bit 12 (ms ): oscillator ty pe selection. 0: rc type 1: xtal type(xtal1 and x t al2) ? bit 11 (/en wd t) : wat c h dog timer e n a b le bit. 0: enable 1: disa ble ? bit 10 (c lk ) : instru ction peri od optio n bit. 0: two oscillat o r periods. 1: four oscillator peri o ds. refer to the sec t ion on ins t ruc t ion set. ? bit 9 (cs) : code securit y bit 0: sec u rity on 1: sec u rity off ? bit 8 (hlf ) : xtal freque ncy sel e ctio n 0: xtal2 type (lo w frequ e n cy, 32.768k hz) 1: xtal1 type (hig h frequ ency ) this bit will af fect system o scill ation only when bit1 2 ( ms) is ?1 ?. when ms is?0?, hlf mu st be ?0?. em78p447s otp rom 4.9 power on consideratio n s an y m i croco n troller is not g uar antee d to start and o per ate pr operl y befor e the po w e r su ppl y sta y s at its stead y stat e . em78p4 47s p o r voltage ran ge is 1.2v~ 1 .8 v. under custo m er appl icatio n , w h e n po w e r i s of f, vdd must drop to belo w 1.2v an d remains of f for 10us before po w e r can be s w itch ed on again. t h is w a y, the em78p4 47s w i l l reset and w o rk normall y. t he extra e x ter nal r e set circuit w i ll w o rk w e ll if vd d can rise at ver y fast spee d (50 ms or less). ho w e v e r , under most c a ses w h ere cri t ical ap plic atio ns are inv o lve d , extra d e vic e s are requ ired to assist in solvin g the po w e r-up pr obl e m s. 4.10 external power on reset circu i t t he circuit show n i n f i g.16 im pleme n ts an external rc to produc e the rese t pulse. t he pulse w i dth (time constant ) shoul d be kept long en oug h for vdd to reached min i mum oper ation volt a ge. t h is circuit is used w h en the po w e r suppl y has slo w r i se time. because the cu rrent leaka ge from the /reset pin is about em 78p4 47n /r ese t vdd d r ri n c fig. 13 exter n al po w e r-up res e t cir c uit this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 28 em78p447s otp rom 4.11 residue-voltage protection w hen batter y i s replace d , de vice po w e r (vdd) is taken of f but residue-v o ltag e remains . t he residue- voltag e ma y tri p s belo w vdd mi ni mum, but not to zero. t h is conditio n ma y ca use a po or po wer on reset. f i g . 16 and f i g. 17 sho w h o w to b u ild the resid ue-vo l t age protecti on circuit. em 78p447n /r eset vd d 40k q1 1n4684 10k 33 k vdd fig.14 the residu e v o lt age protecti on circuit 1 em 78p447n / r ese t vd d q1 vdd 40k r2 r1 fig.15 the residu e v o lt age protecti on circuit 2 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 29 em78p447s otp rom 4.12 instruction set each instructio n in the instruc t ion set is a 13-bit w o r d divi de d into an op code an d on e or more opera n ds. normall y , al l instructio ns are exec uted w i t h in on e singl e instructio n c y cl e (one instructi on consis ts of 2 oscillator per iods), unl ess th e program c o u n ter is ch ang ed b y instructi on " m ov r2,a", "add r2,a ", or b y i n structio ns o f ar ithmetic or l ogic oper ation o n r2 (e.g. "sub r2,a", " bs(c) r2,6", "cl r r 2 ", ??? ? em78p447s otp rom inst ruc t i on binary hex mnemonic operation st a t us affe ct ed 0 0000 0 001 rrrr 001r ior r iocr ? em78p447s otp rom inst ruc t i on binary hex mnemonic operation st a t us affe ct ed 1 1111 kkkk kkkk 1fkk add a,k k+a em78p447s otp rom 4.13 timing diagram r e s e t ti m i ng ( c l k = " 0" ) clk / r es et no p in s t r u c t io n 1 e x ecu t e d td r h t c c i n pu t ti m i ng ( c lk s = " 0 " ) cl k tcc tt c c ti n s a c t e s t i ng : i nput i s dr i v e n a t 2 . 4 v f o r l ogi c " 1 " , a nd 0 . 4 v f o r l ogi c " 0 " . t i m i ng m e a s u r e m e nt s a r e m a d e at 2. 0v f o r l o g i c " 1 " , an d 0. 8v f o r l o g i c " 0 " . a c t est i n put / o ut pu t w a v e f o r m 2. 4 0. 4 2. 0 0. 8 t e st po i n ts 2. 0 0. 8 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 33 em78p447s otp rom 5. absolute maximum ratings items rating t e mperature unde r bia s 0 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 34 em78p447s otp rom 6. electrical characteri s tics 6.1 dc electrical characteristic ( ta= 0 c ~ 70 c, vdd= 5.0v 5 % , vss= 0v ) sy m b o l parameter cond itio n min ty p . max unit x t al: vdd to 3v t w o c y cle w i th t w o clocks dc 8.0 mhz fx t x t al: vdd to 5v t w o c y cle w i th t w o clocks dc 20.0 mhz erc erc: vdd to 5 v r: 5.1k ? % % this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 35 em78p447s otp rom 6.2 ac electrical characteristic (ta=0 q c ~ 70 q c, vdd=5v r 5 % , vss=0 v ) sy m b o l parameter cond itio ns min ty p max unit dclk input clk dut y c y cle 45 50 55 % cr y s ta l t y p e 100 dc ns ti n s instruction c y cle time (clks="0") rc t y p e 500 dc ns t t cc t cc input peri od (t ins+ 20)/n* ns t d r h d e v i c e re set hold time ta = 2 5 q c 1 1 . 3 1 6 . 2 2 1 . 6 m s t r s t / r e s e t p u l s e w i d t h ta = 2 5 q c 200 0 n s t w dt w a tchdog time r period ta = 2 5 q c 1 1 . 3 1 6 . 2 2 1 . 6 m s t s et input pin set u p time 0 ns t hold input pin h o l d time 20 ns t dela y output pin d e la y time cloa d = 2 0 p f 50 ns em78p447s otp rom 6.3 device characteristic t he graphic pr ovide d i n the follo w i n g p ages w e re deriv ed base d o n a limi t ed num ber of samples an d a r e sho w n here fo r referenc e o n l y . t he device c h aracteristic ill u s trated h e rei n ar e n o t gu ara n t eed for it accu rac y . in some grap hic, the da ta ma ybe o u t of the spec ified w a rrante d oper a t ing ran ge. vih/vil (input pins with schmitt inverter) 0 0. 5 1 1. 5 2 2 . 533 . 544 . 555 . 5 vdd(volt) vih vil(volt) fig. 16 v i h, v il of tcc, /i nt , /reset pin this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 37 em78p447s otp rom vth (input thershold voltage) of i/o pins 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.5 3 3.5 4 4.5 5 5.5 vdd ( v olt) vth(volt) fig. 17 vth t h res hold v o lt age o f p60~p6 7, p70~p7 7 vs. vdd vo h / i o h ( vdd= 5 v ) -2 5 -2 0 -1 5 -1 0 -5 0 01 23 45 v oh( v o l t ) ioh(ma) vo h / i o h ( vdd= 3 v ) -8 -6 -4 -2 0 00 . 5 11 . 5 22 . 5 3 v oh( v o l t ) ioh(ma ) fig.18 port5, port6, and port7 v oh v s . ioh, vdd= 5v fig.19 port5, port6, and port7 v oh v s . ioh, vdd= 3v em78p447s otp rom vol / i ol ( vdd=5v) 0 10 20 30 40 50 012 345 v o l(v o lt) vo l / i o l ( vdd= 3 v ) 0 5 10 15 20 25 00 . 5 11 . 5 2 2 . 5 3 vo l( vo lt) iol(ma) max 0 ty p 2 5 max 0 min 70 ty p 2 5 min 70 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 39 em78p447s otp rom vol / i o l ( 5 v) 0 10 20 30 40 50 60 01 23 45 vo l ( vo l t ) iol(ma) fig. 22 port7 v o l v s . iol, v d d= 5v v o l / i ol ( 3v ) 0 5 10 15 20 25 0 0 . 5 1 1 .5 2 2 .5 3 vo l ( vo l t ) iol(ma) em78p447s otp rom w d t t i m e _out 0 5 10 15 20 25 30 23 45 6 vd d ( v o l t ) wdt period (ms) max 70 fig. 24 wdt t i me out pe riod v s . vdd, prescaler set to 1 : 1 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 41 em78p447s otp rom ? ? e ??? ? 3 ? ? ? ? 3? ? 3 a? ? 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ?? ??? ?3? ? r = 3 . 3 k r = 5 .1 k r = 1 0 k r = 1 00 k fig. 25 t y p i cal rc os c frequen c y v s . vdd ce xt= 1 00 p f , t e mp e r at u r e at 25 : ? ? ? 3 a ? ? 3 ? ? ? 3 3 ? ? ? ? ? e ??? ? 3 ? ? e ? t ? ?? ?? ? ?? ? ???? ???? ??? ? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ?? : ? fosc/fosc(25 ) 5v 3v fig. 26 t y p i cal rc os c frequen c y v s . t e mpera t ur e r an d c are ideal co mponent this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 42 em78p447s otp rom four conditi ons exis t w i th the oper a ti ng curren t icc1 to icc4. these c ondi tions are a s follo w s ? icc1 ? v d d=3v , fosc = 32 khz, 2clock, wdt disable . icc2 ? v d d=3v , fosc = 32 khz, 2clock, wdt enable. icc3 ? v d d=5v , fosc = 4 mhz, 2clock, wdt en able . icc4 ? v d d=5v , fosc = 10 mhz, 2clock, wdt en able . t y p i cal i c c 1 an d i c c 2 vs . t e m p e r at u r e ?? ? ?? ?? ? ? ?? ? ? ?? ? ? ? ? t e m p er at u r e ( ) current (ua ) t y p icc2 t y p icc1 fig. 27 t y p i cal opera t ing curr ent i c c1 and ic c2 v s . t e mperatur e m axi m u m i c c 1 an d i c c 2 vs . t e m p e r at u r e ? ?? ?? ?? ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? ? ?3 ? : ? ??3??? max icc2 max icc1 fig. 28 maximum operating curren t ic c1 and ic c2 v s . t e mperature this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 43 em78p447s otp rom t y p i c a l i c c 3 an d i c c 4 vs . t e m p e r at u r e 0. 5 1 1. 5 2 2. 5 3 3. 5 4 0 1 02 03 0 4 05 06 07 0 t e mp er at u r e ( ) current (ma) t yp icc4 t yp icc3 fig. 29 t y p i cal opera t ing curr ent m axi m u m i c c 3 an d i c c 4 vs . t e m p e r at u r e 1 1. 5 2 2. 5 3 3. 5 4 4. 5 0 1 02 03 0 4 05 06 07 0 m a x i cc 4 m a x i cc 3 fig. 30 maximum operating curren t this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 44 em78p447s otp rom t w o con d itio ns exist w i th the st an db y curren t isb1 and isb2. th ese con d itio ns are as follo w ? isb1 ? vdd=5v , wdt dis a ble isb2 ? vdd=5v , wdt en able t y pi c a l i s b 1 a nd i s b 2 v s . t e m p e r a t ur e ? ? ?? ? ? ? ? ?? ?? ? ? ? ? t e m p er at u r e ( ) current (ua ) t y p isb2 t y p isb1 fig. 31 t y p i cal s t andb y curren t isb1 and isb2 v s . t e mperature m axi m u m i s b 1 an d i s b 2 vs . t e m p e r at u r e ? ? ?? ? ? ? ? ? ?? ?? ? ? ? ? t e m p er at u r e ( ) current (ua ) max isb 2 max isb 1 fig. 32 maximum s t andby current i s b1 and isb2 v s . t e mperature this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 45 em78p447s otp rom operating voltage (0~70) 0 5 10 15 20 25 22 . 533 . 5 44 . 555 . 5 6 vdd(vol t ) frequency(m hz) fig. 33 oper ating v o lt ag e in t e mpera t ure rang e from 0 to 7 0 this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 46 em78p447s otp rom e m 78p447s h x t i - v 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 6 vo l t ( v ) i (ma ) m a x min fig. 34 em78p447s i-v curv e operating at 4 mhz em78p447s-g hxt i - v 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 6 v o lt (v ) i (ma) max min fig. 35 em78p447s-g i-v curv e opera t ing at 4 m h z this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 47 em78p447s otp rom e m 78p 4 47s l x t i - v 0 10 20 30 40 50 2 2 .5 3 3.5 4 4 .5 5 5.5 6 vo l t ( v ) i (ua) max min fig. 36 em78p447s i-v curv e operating at 32.7 68 khz em78p447s-g l x t i - v 0 10 20 30 40 50 2 2.5 3 3.5 4 4.5 5 5.5 6 v o lt (v ) i (ua) max min fig. 37 em78p447s-g i-v curv e opera t ing at 32.7 6 8 khz this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 48 em78p447s otp rom appendix package ty pes: otp mcu packag e type pin count packag e size e m 7 8 p 4 4 7 s a p d i p 2 8 6 0 0 m i l em78p44 7 s a m s o p 2 8 3 0 0 m i l e m 7 8 p 4 4 7 s a s s s o p 2 8 2 0 9 m i l e m 7 8 p 4 4 7 s b p d i p 3 2 6 0 0 m i l em78p44 7 s b w m s o p 3 2 4 5 0 m i l this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 49 em78p447s otp rom package information 28-l ead plas tic dual inline p ackag e dip 600 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 50 em78p447s otp rom 32-l ead plas tic dual inline p ackag e dip 600 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 51 em78p447s otp rom 28-l ead plas tic small outline p ackag e sop 3 00 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 52 em78p447s otp rom 32-l ead plas tic small outline p ackag e sop 3 00 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 53 em78p447s otp rom 28-l ead shri nk small outline package ssop 209 mil this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 54 em78p447s otp rom elan ( h ea d q uarte r ) m i croelect r o nics c o r p . , ltd. addres s : no. 1 2 , innov a t i on 1 s t. rd. sc ien c e- ba sed in du stri al p a rk , hs i n ch u ci ty , ta i w an. te le phone : 88 6- 3- 5639977 f a cs imi l e : 886- 3- 5639966 elan ( h .k .) microele ct ronics cor p ., ltd. addre s s : r m . 1005b, 10/ f , em pi r e cent re, 68 mody r o ad, ts im shats u i , kowl oon, hong kong. te le phone : 85 2- 27233376 f a cs imi l e : 852- 27237780 e-mail : ela n h k @emc.co m .h k elan mi cro e lectronics shenzhen, ltd. address : ss m e c bldg . 3f , g a oxin s . ave. 1st , so uth are a , sh enzh en high -t ech indu stri al p a rk., sh enzh en te le phone : 86 - 755- 2601056 5 f a cs imi l e : 86-755- 260105 00 elan mi cro e lectronic s s h ang h ai, ltd. addre s s : #23 buil d i ng n o . 1 1 5 lane 572 bibo r o ad. zhang j i a ng , hi- t e c h park, shanghai te le phone : 86 - 21- 50803866 f a cs imi l e : 86-21- 5080460 0 e l a n i n fo r m at i o n t e c h no l o g y g r o u p . addre s s : 1821 sarat o ga avenue, suit e 250, sarat o ga, c a 95070, u sa te le phone : 1 - 408- 366- 8225 f a cs imi l e : 1- 4 08- 366- 8220 elan mi cro e le ctron i cs c o rp . (eur op e) addre s s : d u b e ndorfs t r as se 4, 8051 zuri c h , swi t ze rl and te le phone : 41 - 43- 2994060 f a cs imi l e : 41-43- 2994079 ema il : inf o @e l a n- eur o pe .co m web-s i t e : w w w.elan -europ e.com cop y ri ght ? 20 04 elan micr o e lectro nics cor p . all rights res e rved. elan o w n s th e intel l ectu al p r opert y rig h ts, conce p ts, idea s, inventi ons, kno w -h o w ( w h e t her pate n tab l e or n o t ) relate d to the information an d t e chnolo g y (herei n after r e ferred as " in formation and t e chnolog y") mentio ne d abov e, an d a ll its relate d i ndu strial pr opert y r i ghts throug ho ut the w o rld, a s no w m a y e x i s t or to be cre a ted i n the future. elan repres ents no w a rrant y f o r the use of the spec ificati ons d e scribe d , eithe r express ed or implied , inclu d in g, but n o t limited, to the impli ed w a rr a n ties of mercha ntabil i t y a nd fit ness for particu lar purp o ses. t he entir e risk as to the q ualit y a nd p e rfo rmance of the appl icati on is w i th the user. in no eve n sh all e l an be lia ble f o r an y l o s s or dama ge to r e ven ues, profit s or goo d w il l or other spec ial, i n cide ntal, in dir e ct and co nseq uenti a l dam ag es of an y kind, res u ltin g f r om the perfor m ance or fai l ur e to p e rform, in cludi ng w i tho u t lim itatio n a n y i n terrupti on of b u siness, w h atev er result ing from bre a c h of cont ract or breac h of w a rr ant y , ev en if el an has b een a d vised of the p o ssibi lit y of such dam ages. t he specificati ons of the pro duct and its ap plie d tech nol o g y w i l l be up d a ted or c han g ed time b y tim e . all the informatio n an d e x pl anati ons of the products in this w e bsite is onl y for yo ur refe renc e. t he actual sp ecifica t ions a n d appl ie d techn o l o g y w i l l be b a s ed on e a ch co nfirmed ord e r. elan res e rve s the rig h t to modif y the info rmation w i t h o u t prior n o tificati on. t he most up-to-d a y infor m ation i s avail abl e on th e w e bsit e http:// w w w . emc.com.t w . this specification is subject to cha nge w i thout prio r notice. 06.25.2003 (v1.1 ) 55 |
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