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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max1420, 3.3v, 12-bit analog-to-digital converter (adc) features a fully-differential input, pipelined, 12- stage adc architecture with wideband track-and-hold (t/h) and digital error correction, incorporating a fully- differential signal path. the max1420 is optimized for low-power, high dynamic performance applications in imaging and digital communications. the converter operates from a single 3.3v supply, and consumes only 221mw. the fully-differential input stage has a small signal -3db bandwidth of 400mhz and may be operat- ed with single-ended inputs. an internal 2.048v precision bandgap reference sets the full-scale range of the adc. a flexible reference structure accommodates an internal reference, or externally applied buffered or unbuffered reference for applications that require increased accuracy and a dif- ferent input voltage range. in addition to low operating power, the max1420 fea- tures two power-down modes: reference power-down and shutdown mode. in reference power-down, the internal bandgap reference is deactivated, which results in a typical 2ma supply current reduction. a full shutdown mode is available to maximize power savings during idle periods. the max1420 provides parallel, offset binary, cmos- compatible three-state outputs. the max1420 is available in a 7mm x 7mm x 1.4mm, 48-pin tqfp package, and is specified over the com- mercial (0 c to +70 c) and the extended industrial (-40 c to +85 c) temperature range. pin-compatible lower speed versions of the max1420 are also available. please refer to the max1421 data sheet for 40msps and the max1422 data sheet for 20msps. ________________________applications medical ultrasound imaging ccd pixel processing ir focal plane arrays radar if and baseband digitization features ? 3.3v single power supply ? 67db snr at f in = 5mhz ? 66db snr at f in = 15mhz ? internal 2.048v precision bandgap reference ? differential, wideband input t/h amplifier ? power-down modes 218mw (reference shutdown mode) 10w (shutdown mode) ? space-saving 48-pin tqfp package max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference ________________________________________________________________ maxim integrated products 1 d9 d8 d7 d6 dv dd dv dd dgnd dgnd d5 d4 d3 d2 agnd av dd av dd agnd agnd inp inn agnd agnd av dd av dd agnd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 48-tqfp max1420 agnd av dd av dd agnd clk clk agnd av dd dv dd dgnd d0 d1 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 agnd av dd cml refn refp refin av dd agnd pd oe d11 d10 pin configuration 19-1981; rev 1; 5/04 ordering information part temp range pin-package max1420ccm 0? to +70? 48 tqfp max1420ecm -40 c to +85 c 48 tqfp functional diagram appears at end of data sheet.
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 62.5mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units dc accuracy resolution res 12 bits t a = +25?, no missing codes -1 1 differential nonlinearity dnl t a = t min to t max ?.5 lsb integral nonlinearity inl t a = t min to t max ? lsb mid-scale offset mso -3 .75 3 %fsr mid-scale offset temperature coefficient msotc 3 x 10 -4 %/ c internal reference (note 1) -5 ?.1 5 %fsr e xter nal r efer e nce ap p l i ed to re fin ( n ote 2) -5 ?.2 5 gain error ge e xter nal r efer e nce ap p li ed to re fp , cml, and refn (note 3) -1.5 1.5 gain error temperature coefficient getc external reference applied to refp, cml, and refn (note 3) 100 x 106 %/ c dynamic performance (f clk = 60mhz, 4096-point fft) f in = 5mhz 67 signal-to-noise ratio snr f in = 15mhz, t a =+25? 62 66 db f in = 5mhz 72 spurious-free dynamic range sfdr f in = 15mhz, t a =+25? 64 72 dbc f in = 5mhz -70 total harmonic distortion thd f in = 15mhz, t a =+25? -69 -62 dbc f in = 5mhz 64.5 signal-to-noise and distortion sinad f in = 15mhz, t a =+25? 58.5 63 db f in = 5mhz 10.4 effective number of bits enob f in = 15mhz 10.2 bits two-tone intermodulation distortion imd f in1 = 11.566036mhz, f in2 = 13.4119138mhz (note 4) -74 dbc av dd , dv dd to agnd ..............................................-0.3v to +4v dv dd , av dd to dgnd..............................................-0.3v to +4v dgnd to agnd.....................................................-0.3v to +0.3v inp, inn, refp, refn, refin, cml, clk, clk ....................(agnd - 0.3v) to (av dd + 0.3v) d0?11, oe , pd .....................(dgnd - 0.3v) to (dv dd + 0.3v) continuous power dissipation (t a = +70?) 48-pin tqfp (derate 21.7mw/? above +70?)........1789mw operating temperature ranges max1420ccm ....................................................0? to +70? max1420ecm .................................................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300?
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 62.5mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units differential gain dg 1% differential phase dp 0.25 degrees analog inputs (inp, inn, cml) input resistance r in either input to ground 22 k ? input capacitance c in either input to ground 4 pf common-mode input level (note 5) v cml v avdd x 0.5 v common-mode input voltage range (note 5) v cmvr v cml 5% v differential input range v in v inp - v inn (note 6) v diff v small-signal bandwidth bw -3db (note 7) 400 mhz large-signal bandwidth fpbw -3db (note 7) 150 mhz overvoltage recovery ovr 1.5 x fs input 1 clock cycles internal reference (refin bypassed with 0.22? in parallel with 1nf) common-mode reference voltage v cml at cml v avdd _ 0.5 v positive reference voltage v refp at refp v cml + 0.512 v negative reference voltage v refn at refn v cml - 0.512 v differential reference voltage v diff (note 6) 1.024 ?% v differential reference temperature coefficient reftc 100 ppm/ c external reference (v refin = 2.048v) refin input resistance r in (note 8) 5 k ? refin input capacitance c in 10 pf refin reference input voltage v refin 2.048 10% v differential reference voltage v diff (note 6) 0.92 x v refin /2 v refin /2 1.08 x v refin /2 v external reference (v refin = 0, reference voltage applied to refp, refn, and cml) refp, refn, cml input current i in -200 200 ? refp, refn, cml input capacitance c in 15 pf
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 62.5mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units differential reference voltage range v diff (note 6) 1.024 10% v cml input voltage range v cml 1.65 10% v refp input voltage range v refp v cml + v diff /2 v refn input voltage range v refn v cml - v diff /2 v digital inputs (clk, clk, pd, oe) input logic high v ih 0.7 x v dvdd v input logic low v il 0.3 x v dvdd v clk, clk ?30 pd -20 20 input current oe -20 20 ? input capacitance 10 pf digital outputs (d0?11) output logic high v oh i oh = 200? v dvdd - 0.5 v dvdd v output logic low v ol i ol = -200? 0 0.5 v three-state leakage -10 10 ? three-state capacitance 2pf power requirements analog supply voltage v avdd 3.135 3.3 3.465 v digital supply voltage v dvdd 2.7 3.3 3.63 v analog supply current i avdd 67 78 ma analog supply current with internal reference in shutdown v refin = 0 66 76 ma analog shutdown current pd = d vdd 10 20 ? digital supply current i dvdd 8ma digital shutdown current pd = v dvdd 20 ? power dissipation p diss analog power dissipation 221 258 mw
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 5 note 1: internal reference, refin bypassed to agnd with a combination of 0.22? in parallel with 1nf capacitor. note 2: external 2.048v reference applied to refin. note 3: internal reference disabled. v refin = 0, v refp = 2.162v, v cml = 1.65v, and v refn = 1.138v. note 4: imd is measured with respect to either of the fundamental tones. note 5: specifies the common-mode range of the differential input signal supplied to the max1420. note 6: v diff = v refp - v refn . note 7: input bandwidth is measured at a -3db level. note 8: v refin is internally biased to 2.048v through a 10k ? resistor. note 9: measured as the ratio of the change in mid-scale offset voltage for a ?% change in v avdd , using the internal reference. electrical characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input voltage at -0.5dbfs, internal reference, f clk = 62.5mhz (50% duty cycle); digital output load c l = 10pf, +25? guaranteed by production test, <+25? guaranteed by design and characterization. typical values are at t a = +25?.) parameter symbol conditions min typ max units power dissipation in shutdown p diss pd = v dvdd 10 ? power-supply rejection ratio psrr (note 9) ? mv/v timing characteristics maximum clock frequency f clk 60 mhz clock high t ch figure 6, clock period 16.667ns 8.33 ns clock low t cl figure 6, clock period 16.667ns 8.33 ns pipeline delay (latency) figure 6 7 clock cycles aperture delay t ad figure 10 2 ns aperture jitter t aj figure 10 2 ps data output delay t od figure 6 5 10 14 ns bus enable time t be figure 5 5 ns bus disable time t bd figure 5 5 ns t ypical operating characteristics (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 60.006mhz (50% duty cycle), digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) -120 -80 -100 -40 -60 -20 0 030 fft plot (8192-point data record) max1420 toc01 analog input frequency (mhz) amplitude (db) 10 15 52025 hd2 hd3 f in = 5.5449mhz -120 -80 -100 -40 -60 -20 0 030 fft plot (8192-point data record) max1420 toc02 analog input frequency (mhz) amplitude (db) 10 15 52025 hd2 hd3 f in = 13.4119mhz -120 -80 -100 -40 -60 -20 0 030 fft plot (8192-point data record) max1420 toc03 analog input frequency (mhz) amplitude (db) 10 15 52025 hd2 hd3 f in = 37.7012mhz
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 60.006mhz (50% duty cycle), digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) -120 -80 -100 -40 -60 -20 0 030 two-tone imd plot (8192-point data record) max1420 toc04 analog input frequency (mhz) amplitude (db) 10 15 52025 f in1 f in1 = 11.566mhz f in2 = 13.4119mhz a in1 = a in2 = -6.5db fs f in2 imd3 imd2 imd2 imd3 85 45 110 100 spurious-free dynamic range vs. analog input frequency 53 max1420 toc08 analog input frequency (mhz) sfdr (dbc) 61 69 77 max1420 toc09 -10 0 20 10 50 60 40 30 70 snr (db) -70 -50 -40 -60 -30 -20 -10 0 analog input power (db fs) signal-to-noise ratio vs. input power (f in = 15mhz) -80 -60 -70 -40 -50 -30 -20 max1420 toc11 thd (dbc) total harmonic distortion vs. input power (f in = 15mhz) -70 -50 -40 -60 -30 -20 -10 0 analog input power (db fs) 20 40 30 60 50 70 80 max1420 toc12 sfdr (dbc) spurious-free dynamic range vs. input power (f in = 15mhz) -70 -50 -40 -60 -30 -20 -10 0 analog input power (db fs) -50 -80 110 100 total harmonic distortion vs. analog input frequency -74 max1420 toc07 analog input frequency (mhz) thd (dbc) -68 -62 -56 max1420 toc10 -10 0 80 sinad (db) -70 -50 -40 -60 -30 -20 -10 0 analog input power (db fs) signal-to-noise + distortion vs. input power (f in = 15mhz) 10 40 30 20 70 60 50 70 50 110 100 signal-to-noise ratio vs. analog input frequency 54 max1420 toc05 analog input frequency (mhz) snr (db) 58 62 66 70 50 110 100 signal-to-noise + distortion vs. analog input frequency 54 max1420 toc06 analog input frequency (mhz) sinad (db) 58 62 66
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference t ypical operating characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 60.006mhz (50% duty cycle), digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) 60 62 66 64 68 70 -40 10 -15 35 60 85 max1420 toc13 temperature ( c) snr (db) signal-to-noise ratio vs. temperature f in = 15mhz 0 2048 1024 3072 4096 max1420 toc17 digital output code integral nonlinearity vs. digital output code inl (lsb) 0.50 0.25 0 -0.25 -0.50 0 2048 1024 3072 4096 max1420 toc18 digital output code differential nonlinearity vs. digital output code inl (lsb) -1.25 -1.00 -0.50 -0.75 -0.25 0 -40 10 -15 35 60 85 offset error vs. temperature max1420 toc20 temperature ( c) offset error (%fsr) 55 57 61 59 63 65 3.1 3.5 max1420 toc21 av dd (v) i avdd (ma) analog supply current vs. analog supply voltage 3.3 3.2 3.4 64 68 76 72 80 84 -40 10 -15 35 60 85 max1420 toc16 temperature ( c) sfdr (dbc) spurious-free dynamic range vs. temperature f in = 15mhz -0.500 0.250 -40 10 -15 35 60 85 max1420 toc19 temperature ( c) gain error (%fsr) gain error vs. temperature, external reference v refin = 2.048v -0.250 -0.375 0 -0.125 0.125 60 66 -40 10 -15 35 60 85 max1420 toc14 temperature ( c) sinad (db) signal-to-noise + distortion vs. temperature f in = 15mhz 62 61 64 63 65 -75 -73 -69 -71 -67 -65 -40 10 -15 35 60 85 max1420 toc15 temperature ( c) thd (dbc) total harmonic distortion vs. temperature f in = 15mhz ________________________________________________________________________________________ 7
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference 8 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v avdd = v dvdd = 3.3v, agnd = dgnd = 0, v in = ?.024v, differential input drive, a in = -0.5dbfs, f clk = 60.006mhz (50% duty cycle), digital output load c l = 10pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) 80 70 60 50 40 -40 10 -15 35 60 85 max1420 toc22 temperature ( c) i avdd (ma) analog supply current vs. temperature 0 0.03 0.09 0.06 0.12 0.15 2.7 3.0 2.9 3.2 3.3 3.5 3.6 max1420 toc26 dv dd (v) i dvdd ( a) digital power-down current vs. digital supply voltage 40 45 50 55 60 65 70 75 80 30 40 35 45 50 55 70 max1420 toc27 clock frequency (mhz) snr/sinad, thd/sfdr (db, dbc) snr/sinad, thd/sfdr vs. clock frequency thd sfdr snr sinad f in = 15mhz 60 65 2.00 2.02 2.06 2.04 2.08 2.10 -40 10 -15 35 60 85 max1420 toc29 temperature ( c) v refin (v) internal reference voltage vs. temperature n-6 n-4 n-3 n-5 n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 max1420 toc30 digital output noise counts 0 300,000 200,000 100,000 400,000 500,000 600,000 output noise histogram (dc input) 0 342 14538 2 6113 242 0 115171 153704 53499 339785 387312 502186 0 0.04 0.12 0.08 0.16 0.20 3.10 3.50 max1420 toc25 av dd (v) i avdd ( a) analog power-down current vs. analog supply voltage 3.30 3.20 3.40 2.075 2.063 2.050 2.038 2.025 3.1 3.3 3.2 3.4 3.5 max1420 toc28 av dd (v) v refin (v) internal reference voltage vs. analog supply voltage 14 12 10 8 6 2.7 3.2 2.9 3.0 3.3 3.5 3.6 max1420 toc23 dv dd (v) i dvdd (ma) digital supply current vs. digital supply voltage 8 14 -40 10 -15 35 60 85 max1420 toc24 temperature ( c) i dvdd (ma) digital supply current vs. temperature 10 9 12 11 13
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference _______________________________________________________________________________________ 9 pin name function 1, 4, 5, 8, 9, 12, 13, 16, 19, 41, 48 agnd analog ground. connect all return paths for analog signals to agnd. 2, 3, 10, 11, 14, 15, 20, 42, 47 av dd analog supply voltage. for optimum performance, bypass to the closest agnd with a parallel combination of a 0.1? and a 1nf capacitor. connect a single 10? and 1? capacitor combination between a vdd and a gnd . 6 inp positive analog signal input 7 inn negative analog signal input 17 clk clock frequency input. clock frequency input ranges from 100khz to 60mhz. 18 clk complementary clock frequency input. this input is used for differential clock inputs. if the adc is driven with a single-ended clock, bypass clk with a 0.1? capacitor to agnd. 21, 31, 32 dv dd digital supply voltage. for optimum performance, bypass to the closest dgnd with a parallel combination of a 0.1? and a 1nf capacitor. connect a single 10? and 1? capacitor combination between d vdd and d gnd . 22, 29, 30 dgnd digital ground 23?8 d0?5 digital data outputs. data bits d0 through d5, where d0 represents the lsb. 33?8 d6?11 digital data outputs. d6 through d11, where d11 represents the msb. 39 oe output enable input. a logic ??on oe places the outputs d0?11 into a high-impedance state. a logic ??allows for the data bits to be read from the outputs. 40 pd shutdown input. a logic ??on pd places the adc into shutdown mode. 43 refin external reference input. bypass to agnd with a capacitor combination of 0.22? in parallel with 1nf. refin can be biased externally to adjust reference levels and calibrate full-scale errors. to disable the internal reference, connect refin to agnd. 44 refp p osi ti ve refer ence i/o . byp ass to ag n d w i th a cap aci tor com b i nati on of 0.22? i n p ar al l el w i th 1nf. w i th the i nter nal r efer ence d i sab l ed ( re fin = ag n d ) , re fp shoul d b e b i ased to v c m l + v d if f / 2. 45 refn n eg ati ve refer ence i/o . byp ass to ag n d w i th a cap aci tor com b i nati on of 0.22? i n p ar al l el w i th 1nf. w i th the i nter nal r efer ence d i sab l ed ( re fin = ag n d ) , re fn shoul d b e b i ased to v c m l - v d if f / 2. 46 cml common-mode level input. bypass to agnd with a capacitor combination of 0.22? in parallel with 1nf. pin description
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference 10 ______________________________________________________________________________________ detailed description the max1420 uses a 12-stage, fully-differential, pipelined architecture (figure 1) that allows for high- speed conversion while minimizing power consump- tion. each sample moves through a pipeline stage every half-clock cycle, including the delay through the output latch. the latency is seven clock cycles. a 2-bit (2-comparator) flash adc converts the held- input voltage into a digital code. the following digital- to-analog converter (dac) converts the digitized result back into an analog voltage, which is then subtracted from the original held-input signal. the resulting error signal is then multiplied by two, and the product is passed along to the next pipeline stage. this process is repeated until the signal has been processed by all 12 stages. each stage provides a 1-bit resolution. digital error correction compensates for adc comparator off- sets in each pipeline stage and ensures no missing codes. input track-and-hold circuit figure 2 displays a simplified functional diagram of the input track-and-hold (t/h) circuit in both track-and-hold mode. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully-differential circuit passes the input signal to the two capacitors c2a and c2b through switches s4a and s4b. switches s2a and s2b set the common mode for the operational transcon- ductance amplifier (ota) input, and open simultane- ously with s1, sampling the input waveform. the result- ing differential voltage is held on capacitors c2a and c2b. switches s4a and s4b are then opened before s3a, s3b, s4c are closed. the ota is used to charge capacitors c1a and c1b to the same values originally held on c2a and c2b. this value is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. the wide input bandwidth t/h amplifier allows the max1420 to track and sample/hold analog inputs of high frequencies beyond nyquist. the analog inputs inp to inn can be driven either differen- tially or single-ended. match the impedance of inp and inn and set the common-mode voltage to midsupply (av dd /2) for optimum performance. analog input and reference configuration the full-scale range of the max1420 is determined by the internally generated voltage difference between refp (av dd /2 + v refin /4) and refn (av dd /2 - v refin /4). the max1420? full-scale range is adjustable through refin, which provides high input impedance for this purpose. refp, cml (av dd /2), and refn are internally buffered low impedance outputs. an internal 2.048v precision bandgap reference sets the full-scale range of the adc. a flexible reference structure accommodates an internal reference, or exter- nally applied buffered or unbuffered reference for appli- t/h v out x2 flash adc dac 2 bits mdac 12 v in v in stage 1 stage 2 d11?0 digital correction logic stage 12 to next stage max1420 figure 1. pipelined architecture?tage blocks s3b s3a cml s5b s2b s5a s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias ota internal bias cml s2a max1420 figure 2. internal track-and-hold circuit
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 11 cations that require increased accuracy and a different input voltage range. the max1420 provides three modes of reference oper- ation: ? internal reference mode ? buffered external reference mode ? unbuffered external reference mode in internal reference mode, the on-chip 2.048v bandgap reference is active and refin, refp, cml, and refn are left floating. for stability purposes, bypass refin, refp, refn and cml with a capacitor network of 0.22? in parallel with a 1nf capacitor to agnd. in buffered external reference mode, the reference volt- age levels can be adjusted externally by applying a stable and accurate voltage at refin. in unbuffered external reference mode, refin is con- nected to agnd, thereby deactivating the on-chip buffers of refp, cml, and refn. with their buffers shut down, these nodes become high impedance and can be driven by external reference sources, as shown in figure 3. clock inputs (clk, clk ) the max1420? clk and clk inputs accept both dif- ferential and single-ended input operation and accept cmos-compatible clock signals. if clk is driven with a single-ended clock signal, bypass clk with a 0.1? capacitor to agnd. since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). sampling occurs on the rising edge of the clock signal, requiring this edge to have the lowest possible jitter. any signifi- cant aperture jitter would limit the snr performance of the adc according to the following relationship: where f in represents the analog input frequency and t aj is the aperture jitter. clock jitter is especially critical for high input frequency applications. the clock input should always be considered as an analog signal and routed away from any analog or digital signal lines. the max1420 clock input operates with a voltage threshold set to av dd /2. clock inputs must meet the specifications for high and low periods as stated in the electrical characteristics . snr ft db in aj = 20 1 2 10 log max1420 refin refn r 50 ? r r r r 0.5v r 50 ? 50 ? r r av dd cml 1nf 0.22 f 1nf 0.22 f 1nf 0.22 f agnd av dd 4 max4284 max4284 refp av dd 2 av dd 4 av dd 2 figure 3. unbuffered external reference drive?nternal reference disabled
12 ______________________________________________________________________________________ max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference figure 4 shows a simplified model of the clock input cir- cuit. this circuit consists of two 10k ? resistors to bias the common-mode level of each input. this circuit may be used to ac-couple the system clock signal to the max1420 clock input. output enable ( oe ), power-down (pd) and output data (d0?11) in addition to low operating power, the max1420 fea- tures two power-down modes: reference power-down and shutdown mode. in reference power-down, the in- ternal bandgap reference is deactivated, which results in a typical 2ma supply current reduction. a full shutdown mode is available to maximize power savings during idle periods. the max1420 provides parallel, offset binary, cmos- compatible three-state outputs. with oe high, the digital outputs enter a high-imped- ance state. if oe is held low with pd high, the outputs are latched at the last digital output code prior to the power-down. all data outputs, d0 (lsb) through d11 (msb), are ttl/cmos logic-compatible. there is a seven clock-cycle latency between any particular sam- ple and its valid output data. the output coding is in off- set binary format (table 1). the capacitive load on the digital outputs d0 through d11 should be kept as low as possible ( 10pf), to avoid large digital currents that could feed back into the analog portion of the max1420, thereby degrading its performance. the use of buffers (e.g., 74lvch16244) on the digital outputs of the adc can further isolate the digital outputs from heavy capacitive loads. to further improve the dynamic performance of the max1420, add small-series resistors of 100 ? to the digital output paths, close to the adc. figure 5 displays the timing relationship between out- put enable and data output. system timing requirements figure 6 depicts the relationship between the clock input, analog input, and valid data output. the max1420 samples the analog input signal on the rising edge of clk (falling edge of clk ) and output data is valid seven clock cycles (latency) later. applications information figure 7 depicts a typical application circuit containing a single-ended to differential converter. the internal ref- erence provides an av dd /2 output voltage for level shifting purposes. the input is buffered and then split to a voltage follower and inverter. a lowpass filter at the input suppresses some of the wideband noise associated d11?0 10k ? 10k ? 10k ? 10k ? a vdd adc clk clk inn inp agnd max1420 figure 4. simplified clock input circuit output data d11?0 oe t bd t be high-z high-z valid data figure 5. output enable timing table 1. max1420 output code for differential inputs differential input voltage* differential input offset binary v ref 2047/2048 +full scale - 1lsb 1111 1111 1111 v ref 2046/2048 +full scale - 2lsb 1111 1111 1110 v ref 1/2048 + 1 lsb 1000 0000 0001 0 bipolar zero 1000 0000 0000 -v ref 1/2048 - 1 lsb 0111 1111 1111 -v ref 2046/2048 -full scale + 1 lsb 0000 0000 0001 -v ref 2047/2048 -full scale 0000 0000 0000 * v ref = v refp - v refn
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 13 n - 7 n n - 6 n + 1 n - 5 n + 2 n - 4 n + 3 n - 3 n + 4 n - 2 n + 5 n - 1 n n + 6 7 clock-cycle latency analog input data output t od t ch t cl clk clk figure 6. system and output timing diagram input 300 ? -5v 5v 0.1 f 0.1 f 0.1 f 0.1 f *c in 22pf *c in 22pf 1nf 0.22 f 44pf* r iso 50 ? r iso 50 ? -5v 600 ? 300 ? 300 ? inp inn lowpass filter cml 600 ? 5v -5v 0.1 f 600 ? 300 ? 600 ? 300 ? 0.1 f 0.1 f 0.1 f 5v 0.1 f 300 ? max4108 max1420 max4108 max4108 lowpass filter *two c in (22pf) caps may be replaced by one 44pf cap, to improve performance. figure 7. typical application circuit for single-ended to differential conversion
max1420 with high-speed op amps. select the r iso and c in val- ues to optimize the filter performance, to suit a particu- lar application. for the application in figure 7, an isolation resistor (r iso ) of 50 ? is placed before the capacitive load to prevent ringing and oscillation. the 22pf c in capacitor acts as a small bypassing capacitor. connecting c in from inn to inp may further improve dynamic performance. using transformer coupling an rf transformer (figure 8) provides an excellent solution to convert a single-ended signal to a fully dif- ferential signal, required by the max1420 for optimum performance. connecting the center tap of the trans- former to cml provides an av dd /2 dc level shift to the input. although a 1:1 transformer is shown, a 1:2 or 1:4 step-up transformer may be selected to reduce the drive requirements. in general, the max1420 provides better sfdr and thd with fully differential input signals over single-ended input signals, especially for very high input frequencies. in differential input mode, even-order harmonics are sup- pressed and each input requires only half the signal swing compared to single-ended mode. single-ended ac-coupled input signal figure 9 shows an ac-coupled, single-ended applica- tion, using a max4108 op amp. this configuration pro- vides high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. grounding, bypassing, and board layout the max1420 requires high-speed board layout design techniques. locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the adc, using surface-mount devices for minimum inductance. bypass refp, refn, refin, and cml with a parallel network of 0.22? capacitors and 1nf to agnd. av dd should be bypassed with a similar network of a 10? bipolar capacitor in parallel with two ceramic capacitors of 1nf and 0.1?. follow the same rules to bypass the digital supply dv dd to dgnd. multilayer boards with separate ground and power planes produce the highest level of signal integrity. consider the use of a split ground plane arrangement to match the physical location of the analog ground (agnd) and the digital ground (dgnd) on the adcs package. join the two ground planes at a single point, such that the noisy digital ground currents do not inter- fere with the analog ground plane. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy, dig- ital systems ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensitive analog traces and remove digital ground and power planes from under- neath digital outputs. keep all signal lines short and free of 90 degree turns. 12-bit, 60msps, 3.3v, low-power adc with internal reference max1420 t1 n.c. v in 6 1 5 2 4 3 22pf 22pf 1nf 0.1 f 0.22 f 25 ? 25 ? minicircuits t1?t?k81 inn inp cml 44pf * * * *replace both 22pf caps with 44pf between inp and inn to improve dynamic performance. figure 8. using a transformer for ac-coupling 14 _____________________________________________________________________________________
static parameter definitions integral nonlinearity (inl) i ntegral nonlinearity is the deviation of the values on an actual transfer function from a straight-line. this straight- line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function once off- set and gain errors have been nullified. the static lineari- ty parameters for the max1420 are measured using the best straight-line fit method. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step-width and the ideal value of 1lsb. a dnl error specification of less than 1lsb guarantees no missing codes. dynamic parameter definitions aperture jitter figure 10 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (figure 10). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error). the ideal theoretical minimum analog-to-digital noise is caused by quantiza- tion error only and results directly from the adcs reso- lution (n-bits): snr max = (6.02 x n + 1.76) db in reality, there are other noise sources besides quanti- zation noise, e.g., thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spec- tral components minus the fundamental, the first four harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to all spectral components minus the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob is computed from: enob sinad = ? 176 602 . . max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference ______________________________________________________________________________________ 15 max1420 1nf 1k ? 100 ? 100 ? c in 22pf c in 22pf cml inp inn 0.1 f r iso 50 ? r iso 50 ? 0.22 f v in max4108 figure 9. single-ended ac-coupled input signal hold analog input sampled data (t/h) t/h t ad t aj track track clk clk figure 10. t/h aperture timing
max1420 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first four harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest spurious component, excluding dc offset. intermodulation distortion (imd) the two-tone imd is the ratio expressed in decibels of either input tone to the worst 3rd-order (or higher) inter- modulation products. the individual input tone levels are at -6.5db full scale. thddb vvvv v = +++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 10 2 2 3 2 4 2 5 2 1 log 12-bit, 60msps, 3.3v, low-power adc with internal reference clk inp interface pipeline adc output drivers refin refp cml refn oe av dd agnd dv dd dgnd d11?0 inn pd t/h max1420 bandgap reference clk ref system + bias functional diagram ______________________________________________________________________________________ 16
max1420 12-bit, 60msps, 3.3v, low-power adc with internal reference package information 32l/48l,tqfp.eps maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 17 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products.
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max1420 part number table notes: see the max1420 quickview data sheet for further information on this product family or download the max1420 full data sheet (pdf, 848kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max1420c c m-td 0c to +70c rohs/lead-free: no max1420c c m+td 0c to +70c rohs/lead-free: yes max1420c c m+d 0c to +70c rohs/lead-free: yes max1420c c m-d lqfp;48 pin;7x7x1.4 mm dwg: 21-0054f (pdf) use pkgcode/variation: c 48-2 * 0c to +70c rohs/lead-free: no materials analysis max1420ec m+d lqfp;48 pin;7x7x1.4 mm dwg: 21-0054f (pdf) use pkgcode/variation: c 48+2 * -40c to +85c rohs/lead-free: yes materials analysis max1420ec m-td -40c to +85c rohs/lead-free: no max1420ec m-d lqfp;48 pin;7x7x1.4 mm dwg: 21-0054f (pdf) use pkgcode/variation: c 48-2 * -40c to +85c rohs/lead-free: no materials analysis
max1420ec m+t -40c to +85c rohs/lead-free: yes max1420ec m+ -40c to +85c rohs/lead-free: yes max1420ec m+td -40c to +85c rohs/lead-free: yes didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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