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4 r on , triple/quad spdt 15 v/+12 v/5 v i cmos switches adg1433/adg1434 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, 62-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 all rights reserved. p.o. box 9106, norwood, ma 020 ?2006C2009 analog devices, inc. features 4.7 maximum on resistance @ 25c 0.5 on resistance flatness fully specified at 15 v/+12 v/5 v 3 v logic-compatible inputs up to 115 ma continuous current per channel rail-to-rail operation break-before-make switching action 16-/20-lead tssop and 4 mm 4 mm lfcsp_vq packages applications relay replacement audio and video routing automatic test equipment data acquisition systems temperature measurement systems avionics battery-powered systems communication systems medical equipment general description the adg1433 and adg1434 are monolithic industrial cmos ( i cmos?) analog switches comprising three independently selectable single-pole, double-throw (spdt) switches and four independently selectable spdt switches, respectively. all channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. an en input on the adg1433 (lfcsp and tssop packages) and adg1434 (lfcsp package only) is used to enable or disable the device. when disabled, all channels are switched off. the i cmos modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (cmos), and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no other generation of high voltage parts has been able to achieve. unlike analog ics using a conventional cmos process, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. i cmos construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments. functional block diagrams in1 in2 in3 en s1a d1 s1b s3b d3 s3a s2b d2 s2a logic adg1433 switches shown for a 1 input logic. 06181-001 figure 1. adg1433 tssop and lfcsp_vq s1 a d1 s1b in1 in2 s2b s2 a d2 s4a d4 s4b in4 in3 s3b s3a d3 adg1434 switches shown for a 1 input logic. 06181-002 figure 2. adg1434 tssop s1a d1 s1b s2b s2a d2 s4a d4 s4b s3b s3a d3 adg1434 06181-101 switches shown for a 1 input logic. in1 in2 in3 in4 en logic figure 3. adg1434 lfcsp_vq
adg1433/adg1434 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? 15 v dual supply ....................................................................... 3 ? 12 v single supply ........................................................................ 5 ? 5 v dual supply ......................................................................... 6 ? absolute maximum ratings ............................................................7 ? thermal resistance .......................................................................7 ? esd caution...................................................................................7 ? pin configurations and function descriptions ............................8 ? typical performance characteristics ........................................... 10 ? test circuits ..................................................................................... 13 ? terminology .................................................................................... 15 ? outline dimensions ....................................................................... 16 ? ordering guide .......................................................................... 17 ? revision history 6/09rev. b to rev. c updated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 17 3/09rev. a to rev. b change to i dd parameter, table 1 ................................................... 4 change to i dd parameter, table 2 ................................................... 5 updated outline dimensions, figure 39 ..................................... 17 6/08rev. 0 to rev. a added continuous current per channel parameter, table 1 ..... 4 added continuous current per channel parameter, table 2 ..... 5 added continuous current per channel parameter, table 3 ..... 6 changes to table 4 ............................................................................. 7 changes to figure 30 ...................................................................... 13 updated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 17 10/06revision 0: initial version
adg1433/adg1434 rev. c | page 3 of 20 specifications 15 v dual supply v dd = +15 v 10%, v ss = C15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance, r on 4 typ v s = 10 v, i s = ?10 ma; see figure 25 4.7 5.7 6.7 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between 0.5 typ v s = 10 v, i s = ?10 ma channels, r on 0.78 0.85 1.1 max on resistance flatness, r flat(on) 0.5 typ v s = 10 v, i s = ?10 ma 0.72 0.77 0.92 max leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.04 na typ v d = 10 v, v s = 10 v; see figure 26 0.3 0.6 3 na max drain off leakage, i d (off ) 0.04 na typ v d = 10 v, v s = 10 v; see figure 26 0.3 0.6 3 na max channel on leakage, i d , i s (on) 0.05 na typ v s = v d = 10 v; see figure 27 0.4 0.8 8 na max digital inputs input high voltage, v ih 2.0 v min input low voltage, v il 0.8 v max input current, i il or i ih 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 2 transition time, t trans 140 ns typ r l = 100 , c l = 35 pf 170 200 230 ns max v s = 10 v, see figure 28 break-before-make time delay, t d 40 ns typ r l = 100 , c l = 35 pf 30 ns min v s1 = v s2 = 10 v, see figure 29 t on (en ) 140 ns typ r l = 100 , c l = 35 pf 170 200 230 ns max v s = 10 v, see figure 30 t off (en ) 60 ns typ r l = 100 , c l = 35 pf 75 85 90 ns max v s = 10 v, see figure 30 charge injection ?50 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 31 off isolation ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 32 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 total harmonic distortion, thd + n 0.025 % typ r l = 110 , 15 v p-p, f = 20 hz to 20 khz, see figure 35 ?3 db bandwidth 200 mhz typ r l = 50 , c l = 5 pf, see figure 33 insertion loss 0.24 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 33 c s (off ) 12 pf typ f = 1 mhz c d (off ) 22 pf typ f = 1 mhz c d , c s (on) 72 pf typ f = 1 mhz
adg1433/adg1434 rev. c | page 4 of 20 parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.001 a typ digital inputs = 0 v or v dd 1 a max i dd 260 a typ digital inputs = 5 v 475 a max i ss 0.001 a typ digital inputs = 0 v, 5 v, or v dd 1 a max v dd /v ss 4.5/16.5 v min/max gnd = 0 v continuous current per channel 2 v dd = +13.5 v, v ss = ?13.5 v adg1433 115 75 40 ma max adg1434 100 65 40 ma max 1 temperature range for y version: ?40 c to +125c. 2 guaranteed by design, not subject to production test.
adg1433/adg1434 rev. c | page 5 of 20 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 6 typ v s = 0 v to 10 v, i s = ?10 ma, see figure 25 8 9.5 11.2 max v dd = 10.8 v, v ss = 0 v on resistance match between 0.55 typ v s = 0 v to 10 v, i s = ?10 ma channels, r on 0.82 0.85 1.1 max on resistance flatness, r flat(on) 1.5 typ v s = 0 v to 10 v, i s = ?10 ma 2.5 2.5 2.8 max leakage currents v dd = 13.2 v source off leakage, i s (off) 0.04 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 26 0.3 0.6 3 na max drain off leakage, i d (off) 0.04 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 26 0.3 0.6 3 na max channel on leakage, i d , i s (on) 0.06 na typ v s = v d = 1 v or 10 v, see figure 27 0.4 0.8 8 na max digital inputs input high voltage, v ih 2.0 v min input low voltage, v il 0.8 v max input current, i il or i ih 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 2 transition time, t trans 200 ns typ r l = 100 , c l = 35 pf 255 310 350 ns max v s = 8 v, see figure 28 break-before-make time delay, t d 80 ns typ r l = 100 , c l = 35 pf 55 ns min v s1 = v s2 = 8 v, see figure 29 t on ( en ) 210 ns typ r l = 100 , c l = 35 pf 270 320 360 ns max v s = 8 v, see figure 30 t off ( en ) 70 ns typ r l = 100 , c l = 35 pf 86 95 105 ns max v s = 8 v, see figure 30 charge injection ?10 pc typ v s = 6 v, r s = 0 , c l = 1 nf, see figure 31 off isolation C70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 32 channel-to-channel crosstalk C70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 ?3 db bandwidth 135 mhz typ r l = 50 , c l = 5 pf, see figure 33 insertion loss 0.5 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 33 c s (off) 25 pf typ f = 1 mhz c d (off) 45 pf typ f = 1 mhz c d , c s (on) 80 pf typ f = 1 mhz power requirements v dd = 13.2 v i dd 0.002 a typ digital inputs = 0 v or v dd 1 a max i dd 260 a typ digital inputs = 5 v 475 a max v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v continuous current per channel 2 v dd = +10.8 v, v ss = 0 v adg1433 100 65 40 ma max adg1434 85 60 35 ma max 1 temperature range for y version: ?40 c to +125 c. 2 guaranteed by design, not subject to production test.
adg1433/adg1434 rev. c | page 6 of 20 5 v dual supply v dd = +5 v 10%, v ss = ?5 v 10%, gnd = 0 v, unless otherwise noted. table 3. parameter +25c ?40c to +85c ?40c to +125c 1 unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance (r on ) 7 typ v s = 4.5 v, i s = ?10 ma, see figure 25 9 10.5 12 max v dd = +4.5 v, v ss = ?4.5 v on resistance match between 0.55 typ v s = 4.5 v, i s = ?10 ma channels (r on ) 0.78 0.91 1.1 max on resistance flatness, r flat(on) 1.5 typ v s = 4.5 v, i s = ?10 ma 2.5 2.5 3 max leakage currents v dd = +5.5 v, v ss = ?5.5 v source off leakage, i s (off) 0.02 na typ v d = 4.5 v, v s = 4.5 v, see figure 26 0.3 0.6 3 na max drain off leakage, i d (off) 0.02 na typ v d = 4.5 v, v s = 4.5 v, see figure 26 0.3 0.6 3 na max channel on leakage, i d , i s (on) 0.04 na typ v s = v d = 4.5 v, see figure 27 0.4 0.8 8 na max digital inputs input high voltage, v ih 2.0 v min input low voltage, v il 0.8 v max input current, i il or i ih 0.005 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 4 pf typ dynamic characteristics 2 transition time, t trans 315 ns typ r l = 100 , c l = 35 pf 430 480 550 ns max v s = 5 v, see figure 28 break-before-make time delay, t d 90 ns typ r l = 100 , c l = 35 pf 55 ns min v s1 = v s2 = 5 v, see figure 29 t on ( en ) 325 ns typ r l = 100 , c l = 35 pf 425 490 545 ns max v s = 5 v, see figure 30 t off ( en ) 150 ns typ r l = 100 , c l = 35 pf 200 225 240 ns max v s = 5 v, see figure 30 charge injection ?10 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 31 off isolation ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 32 channel-to-channel crosstalk ?70 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 34 total harmonic distortion, thd + n 0.06 % typ r l = 110 , 5 v p-p, f = 20 hz to 20 khz, see figure 35 ?3 db bandwidth 145 mhz typ r l = 50 , c l = 5 pf, see figure 33 insertion loss 0.5 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 33 c s (off) 18 pf typ f = 1 mhz c d (off) 32 pf typ f = 1 mhz c d , c s (on) 80 pf typ f = 1 mhz power requirements v dd = +5.5 v, v ss = ?5.5 v i dd 0.002 a typ digital inputs = 0 v, 5 v, or v dd 1 a max i ss 0.001 a typ digital inputs = 0 v, 5 v, or v dd 1 a max v dd /v ss 4.5/16.5 v min/max gnd = 0 v continuous current per channel 2 v dd = +4.5 v, v ss = ?4.5 v adg1433 95 60 35 ma max adg1434 85 55 35 ma max 1 temperature range for y version: ?40c to +125c. 2 guaranteed by design, not subject to production test.
adg1433/adg1434 rev. c | page 7 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd ?25 v to +0.3 v analog inputs, digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, s or d (pulsed at 1 ms, 10% duty cycle maximum) 250 ma continuous current, s or d 2 data + 15% operating temperature range industrial (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c reflow soldering peak temperature (pb-free) 260 (+ 0 to ?5)c 1 overvoltages at a, en , s, or d pins are clamped by internal diodes. current should be limited to the maximum ratings given. 2 see data given in the specifications section (see table 1 to table 3 ). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 5. package type ja jc unit tssop 150.4 50 c/w lfcsp_vq 30.4 n/a c/w esd caution
adg1433/adg1434 rev. c | page 8 of 20 pin configurations and function descriptions 06181-003 06181-005 pin 1 indicator 1 d1 2 s1b 3 s2b 4 d2 11 v ss 12 en 10 s3b 9d3 5 s 2 a 6 i n 2 7 i n 3 8 s 3 a 1 5 v d d 1 6 s 1 a 1 4 g n d 1 3 i n 1 top view (not to scale) adg1433 1 2 3 4 5 6 7 8 16 15 14 13 12 s1a d1 s1b s2b v dd in1 en v ss s3b gnd adg1433 top view (not to scale) 11 10 9 s2a d2 s3a in2 in3 d3 notes 1. exposed pad is tied to substrate, v ss . figure 4. adg1433 tssop pin configuration figure 5. adg1433 lfcsp_vq pin configuration table 6. adg1433 pin function descriptions pin no. mnemonic description tssop lfcsp_vq 1 15 v dd most positive power supply potential. 2 16 s1a source terminal 1a. ca n be an input or an output. 3 1 d1 drain terminal 1. can be an input or an output. 4 2 s1b source terminal 1b. ca n be an input or an output. 5 3 s2b source terminal 2b. ca n be an input or an output. 6 4 d2 drain terminal 2. can be an input or an output. 7 5 s2a source terminal 2a. ca n be an input or an output. 8 6 in2 logic control input 2. 9 7 in3 logic control input 3. 10 8 s3a source terminal 3a. ca n be an input or an output. 11 9 d3 drain terminal 3. can be an input or an output. 12 10 s3b source terminal 3b. can be an input or an output. 13 11 v ss most negative power supply potential. in single-supply applications, it can be connected to ground. 14 12 en active low digital input. when high, the device is disabled and all switches are off. when low, inx logic inputs determine the on switches. 15 13 in1 logic control input 1. 16 14 gnd ground (0 v) reference. table 7. adg1433 truth table en inx sxa sxb 1 x off off 0 0 off on 0 1 on off
adg1433/adg1434 rev. c | page 9 of 20 1 2 3 4 5 6 8 20 19 18 17 16 15 13 s1a d1 s1b 7 s2b gnd v ss in1 s4a d4 s4b 14 s3b 9 s2a 12 s3a 10 in2 11 in3 d2 d3 nc v dd in4 adg1434 top view (not to scale) nc = no connect 06181-004 6 pin 1 indicator figure 6. adg1434 tssop pin configuration 06181-00 1 d1 2 s1b 3v ss 4 gnd 5 s2b 13 v dd 14 s4b 15 d4 12 s3b 11 d3 6 d 2 7 s 2 a 8 i n 2 1 0 s 3 a 9 i n 3 1 8 e n 1 9 i n 1 2 0 s 1 a 1 7 i n 4 1 6 s 4 a top view (not to scale) adg1434 notes 1. exposed pad is tied to substrate, v ss . figure 7. adg1434 lfcsp_vq pin configuration table 8. adg1434 pin function descriptions pin no. tssop mnemonic description lfcsp_vq 1 19 in1 logic control input 1. 2 20 s1a source terminal 1a. ca n be an input or an output. 3 1 d1 drain terminal 1. can be an input or an output. 4 2 s1b source terminal 1b. ca n be an input or an output. 5 3 v ss most negative power supply potential. in single-supply applications, it can be connected to ground. 6 4 gnd ground (0 v) reference. 7 5 s2b source terminal 2b. ca n be an input or an output. 8 6 d2 drain terminal 2. can be an input or an output. 9 7 s2a source terminal 2a. ca n be an input or an output. 10 8 in2 logic control input 2. 11 9 in3 logic control input 3. 12 10 s3a source terminal 3a. can be an input or an output. 13 11 d3 drain terminal 3. can be an input or an output. 14 12 s3b source terminal 3b. can be an input or an output. 15 n/a nc no connect. 16 13 v dd most positive power supply potential. 17 14 s4b source terminal 4b. can be an input or an output. 18 15 d4 drain terminal 4. can be an input or an output. 19 16 s4a source terminal 4a. can be an input or an output. 20 17 in4 logic control input 4. n/a 18 en active low digital input. when high, the device is disabled and all switches are off. when low, inx logic inputs determine the on switches. table 9. adg1434 tssop truth table inx sxa sxb 0 off on 1 on off table 10. adg1434 lfcsp_vq truth table en inx sxa sxb 1 x off off 0 0 off on 0 1 on off
adg1433/adg1434 rev. c | page 10 of ?16.5 15.5 source or drain voltage (v) ?12.5 ?8.5 ?4.5 ?0.5 3.5 7.5 11.5 20 typical performance characteristics 5 6 0 on resistance ( ? ) 4 3 2 1 v dd = +15v, v ss = ?15v v dd = +13.5v, v ss = ?13.5v v dd = +12v, v ss = ?12v v dd = +10v, v ss = ?10v v dd = +16.5v, v ss = ?16.5v t a = 25c 7 0 ?15 source or drain voltage (v) on resistance ( ? ) 15 t a = +25c t a = +85c t a = ?40c t a = +125c v dd = +15v v ss = ?15v 6 5 4 3 2 1 ?10 ?5 0 5 10 06181-010 12 0 ?5 source or drain voltage (v) on resistance ( ? ) 5 06181-007 figure 8. on resistance as a function of v d (v s ), dual supply 5 9 6 7 8 0 on resistance ( ? ) 4 3 2 1 ?7 ?4?5?6 7 source or drain voltage (v) ?3 ?2 ?1 0 5 43 12 6 v dd = +7v, v ss = ?7v v dd = +5.5v, v ss = ?5.5v v dd = +5v, v ss = ?5v v dd = +4.5v, v ss = ?4.5v t a = 25c 06181-008 figure 9. on resistance as a function of v d (v s ), dual supply 12 13 0 on resistance ( ? ) 11 10 9 8 7 6 5 4 3 2 1 0 source or drain voltage (v) 1 2 3 4 5 6 7 8 9 10 11 12 13 v dd = 12v v dd = 13.2v v dd = 10.8v v dd = 8v v dd = 5v t a = 25c v ss = 0v 06181-009 figure 10. on resistance as a function of v d (v s ), single supply figure 11. on resistance as a function of v d (v s ) for different temperatures, 15 v dual supply 10 8 6 4 2 ?4?3?2?101234 t a = +25c t a = +85c t a = ?40c t a = +125c v dd = +5v v ss = ?5v 06181-011 10 0 0 on resistance ( ? ) 12 figure 12. on resistance as a function of v d (v s ) for different temperatures, 5 v dual supply source or drain voltage (v) 9 8 7 6 5 4 3 2 1 246810 t a = +25c t a = +85c t a = ?40c t a = +125c v dd = 12v v ss = 0v 181-012 06 figure 13. on resistance as a function of v d (v s ) for different temperatures, 12 v single supply
adg1433/adg1434 rev. c | page 11 of 20 1600 1400 1000 1200 800 600 400 200 0 ?200 120 100 80 60 40 20 0 leakage currents (pa) 013 70 0 01 4 logic, inx (v) i dd (a) temperature (c) 06181- v dd = +15v v ss = ?15v v bias = +10v/?10v 60 50 40 30 20 10 24681012 i s (off) + ? i s (off) ? + i d ,i s (on) ? ? i d ,i s (on) + + v dd = +15v v ss = ?15v v dd = +12v v ss = 0v v dd = +5v v ss = ?5v i dd per channel t a = 25c 06181-015 200 ?200 ?150 ?100 ?50 0 50 100 150 ?15 15 10 5 0 ?5 ?10 v s (v) charge injection (pc) figure 14. leakage currents as a function of temperature, 15 v dual supply 1600 1400 1000 1200 800 600 400 200 0 ?200 120 100 80 60 40 20 0 leakage currents (pa) 1-014 temperature (c) 0618 v dd = +5v v ss = ?5v v bias = +4.5v/?4.5v i s (off) + ? i s (off) ? + i d ,i s (on) ? ? i d ,i s (on) + + figure 15. leakage currents as a function of temperature, 5 v dual supply 2000 1600 1800 1400 1000 1200 800 600 400 200 leakage currents (pa) 0 ?200 120 100 80 60 40 20 0 temperature (c) 06181-020 v dd = 12v v ss = 0v v bias = 1v/10v i s (off) + ? i d ,i s (on) ? ? i d ,i s (on) + + i s (off) ? + figure 16. leakage currents as a function of temperature, 12 v single supply figure 17. i dd vs. logic level t a = 25c v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = +12v v ss = 0v 06181-016 figure 18. charge injection vs. source voltage 350 300 250 200 150 100 50 0 time (ns) v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = +12v v ss = 0v 120 100 80604020 0 ?20 ?40 temperature (c) 06181-01 7 figure 19. transition time vs. temperature
adg1433/adg1434 rev. c | page 12 of 20 0 ?110 1k 1g off isolation (db) frequency (hz) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25c 018 06181- figure 20. off isol ation vs. frequency 0 ?110 1k 1g crosstalk (db) frequency (hz) ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 10k 100k 1m 10m 100m v dd = +15v v ss = ?15v t a = 25c 06181- 0 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 on response (db) 019 ?4.0 ?3.5 100 1g 100m 10m 1m 100k 10k 1k frequency (hz) figure 21. crosstalk vs. frequency v dd = +15v v ss = ?15v t a = 25c 06181-100 figure 22. on response vs. frequency 0 10 100k frequency (hz) thd + n (%) 0.09 0.10 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 100 1k 10k load = 110 ? t a = 25c v dd = +5v, v ss = ?5v, v s = +5v p-p v dd = +15v, v ss = ?15v, v s = +15v p-p 06181-032 figure 23. thd + n vs. frequency 0 100 1k 10m frequency (hz) acpsrr (db) ?20 ?40 ?60 ?80 ?100 ?120 10k 100k 1m v dd = +15v v ss = ?15v t a = 25c v p-p = 0.63v no decoupling capacitors decoupling capacitors on supplies 06181-035 figure 24. acpsrr vs. frequency
adg1433/adg1434 rev. c | page 13 of 20 test circuits i ds sd v s v 06181-021 figure 25. on resistance sd i s (off) i d (off) a a v v d s 06181-022 figure 26. off leakage sd i d (on) a v d nc nc = no connect 06181-023 figure 27. on leakage in v out v v dd ss d sa v dd v ss gnd c l 35pf sb v s v in 0.1 f 0.1f v in 50% 50% 90% 50% 50% 90% t on t off r l 100? v in v out 06181-024 figure 28. switching timing in v out v v dd ss d sa v dd v ss gnd c l 35pf sb v s v in 0.1f 0.1f r l 100? 80% v out v in t bbm t bbm 06181-025 figure 29. break-before-make delay, t d en v inx v dd v ss dd v ss adg1433 gnd inx s1b s1a v in 0.1f 0.1f inx v s 50% 50% v 0v enable drive (v in ) 3v 0.9v out 0.9v out t on (en) out 0v output v out d1 c l 35pf t off (en) r l 100 ? 50 ? 06181-026 figure 30. enable delay, t on ( en ), t off ( en )
adg1433/adg1434 rev. c | page 14 of 20 v in (normally closed switch) v out v in (normally open switch) off v out on q inj = c l v out in v out nc v v dd ss sa v dd v ss gnd c l 1nf d v in v s 0.1f 0.1f sb 06181-027 figure 31. charge injection v v v out 50? network analyzer r l 50? in v in sa d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sb off isolation = 20 log v out v s 0 6181-028 figure 32. off isolation v out 50? network analyzer r l 50? in v in sa d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? nc sb insertion loss = 20 log v out with switch v out without switch 06181-029 figure 33. bandwidth channel-to-channel crosstalk = 20 log v out gnd sa d sb v out network analyzer r l 50 ? r 50? v s v s v dd v ss dd 0.1f ss 0.1f in 06181-030 figure 34. channel-to-channel crosstalk v v dd v out r s audio precision r l 110 ? in v in s d v s v p-p v dd v ss 0.1f ss 0.1f gnd 0618 1-031 figure 35. thd + noise
adg1433/adg1434 rev. c | page 15 of 20 terminology r on ohmic resistance between terminal d and terminal s. r on the difference between the r on of any two channels. r flat(on) the difference between the maximum and minimum value of on resistance as measured. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminal d and terminal s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on ( en ) delay time between the 50% and 90% points of the digital input and switch on condition. t off ( en ) delay time between the 50% and 90% points of the digital input and switch off condition. t trans delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% point of both switches when switching from one address state to another. v il maximum input voltage for logic 0. v ih minimum input voltage for logic 1. i il (i ih ) input current of the digital input. i dd positive supply current. i ss negative supply current. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental. ac power supply rejection ratio (acpsrr) a measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
adg1433/adg1434 rev. c | page 16 of 20 outline dimensions 16 9 8 1 4.50 4.40 4.30 pin 1 seating plane 8 0 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab compliant to jedec standards mo-220-vggc. figure 36. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 1 0.65 bsc 0.60 max p i n 1 i n d i c a t o r 1.95 bcs 0.50 0.40 0.30 0.25 min 3.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 4.00 bsc sq 2.65 2.50 sq 2.35 16 5 13 8 9 12 4 exposed pa d bottom view 031006-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 37. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-13) dimensions shown in millimeters
adg1433/adg1434 rev. c | page 17 of 20 compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarit y 0.10 figure 38. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters 2.65 2.50 sq 2.35 3.75 bsc sq 4.00 bsc sq 1 0.50 bsc p i n 1 i n d i c a t o r 0.50 0.40 0.30 compliant to jedec standards mo-220-vggd-1 090408-b top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 39. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-4) dimensions shown in millimeters ordering guide model temperature range description en pin package option adg1433yruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] yes ru-16 adg1433yruz-reel 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] yes ru-16 adg1433yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] yes ru-16 adg1433ycpz-reel 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] yes cp-16-13 ADG1433YCPZ-REEL7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] yes cp-16-13 adg1434yruz 1 ?40c to +125c 20-lead thin shrink small outline package [tssop] no ru-20 adg1434yruz-reel 1 ?40c to +125c 20-lead thin shrink small outline package [tssop] no ru-20 adg1434yruz-reel7 1 ?40c to +125c 20-lead thin shrink small outline package [tssop] no ru-20 adg1434ycpz-reel 1 ?40c to +125c 20-lead lead frame chip scale package [lfcsp_vq] yes cp-20-4 adg1434ycpz-reel7 1 ?40c to +125c 20-lead lead frame chip scale package [lfcsp_vq] yes cp-20-4 1 z = rohs compliant part.
adg1433/adg1434 rev. c | page 18 of 20 notes
adg1433/adg1434 rev. c | page 19 of 20 notes
adg1433/adg1434 rev. c | page 20 of 20 notes ?2006C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06181-0-6/09(c)

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