general description the max4950a dual pci express (pcie) equalizer/ redriver operates from a single +3.3v supply. this device improves signal integrity at the receiver through programmable input equalization and redrive circuitry with output deemphasis to correct for high-frequency losses. this device permits optimal placement of key pcie components and longer runs of stripline, microstrip, or cable. the max4950a contains two identical channels capa- ble of equalizing pcie gen i (2.5gt/s) and gen ii (5.0gt/s) signals. the max4950a features electrical idle and receiver detection on each channel and a power-saving mode. the max4950a is available in a small 36-pin (6.0mm x 6.0mm) tqfn package with flowthrough traces for opti- mal layout and minimal space requirements. the max4950a is specified over the 0? to +70? commer- cial operating temperature range. applications servers industrial pcs test equipment computers external graphics applications communications switchers storage area networks features ? single +3.3v supply operation ? pcie gen i (2.5gt/s) and gen ii (5.0gt/s) capable excellent differential return loss: 8db (f = 1.25ghz to 2.5ghz) ? very low latency with 280ps (typ) propagation delay ? individual lane detection ? three-level programmable input equalization ? three-level programmable output deemphasis ? standard, -2.5db programmable output levels ? on-chip 50 input/output terminations ? space-saving, 6.0mm x 6.0mm tqfn package max4950a dual pci express equalizer/redriver ________________________________________________________________ maxim integrated products 1 19-4583; rev 0; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pci express is a registered trademark of pci-sig corp. max4950a 27 26 25 24 23 22 21 20 19 1 top view 2 3 4 5 tqfn + 6 7 8 9 28 29 30 31 32 33 34 35 36 n.c. v cc odea0 odea1 o_ampa ineqa0 ineqa1 v cc n.c. gnd inap inam gnd en gnd outbp outbm gnd 18 17 16 15 14 13 12 11 10 n.c. v cc ineqb0 ineqb1 o_ampb odeb0 odeb1 v cc n.c. *connect exposed pad (ep) to gnd. gnd outap outam gnd rx_det gnd inbp inbm gnd *ep ordering information part temp range pin-package max4950actx+t 0c to +70c 36 tqfn-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. t = tape and reel. pin configuration
max4950a dual pci express equalizer/redriver 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +3.0v to +3.6v, c cl = 75nf coupling capacitor on each output, r l = 50 resistor on each output, t a = 0? to +70?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (note 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: all i/o pins are clamped by internal diodes. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . (voltages referenced to gnd.) v cc ........................................................................-0.3v to +4.0v all other pins (note 1)................................-0.3v to (v cc + 0.3v) continuous current in_p, in_m, out_p, out_m ............?0ma peak current in_p, in_m, out_p, out_m (pulsed for 1?, 1% duty cycle)..................................?00ma continuous power dissipation (t a = +70?) 36-pin tqfn (derate 35.7mw/? above +70?) .......2857mw junction-to-case thermal resistance ( jc ) (note 2) 36-pin tqfn...................................................................1?/w junction-to-ambient thermal resistance ( ja ) (note 2) 36-pin tqfn.................................................................28?/w operating temperature range...............................0? to +70? junction temperature range ............................-40? to +150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units dc performance power-supply range v cc 3.0 3.6 v supply current i cc en = v cc , v o_ampa = v gnd , v o_ampb = v gnd (note 4) 130 165 ma differential input impedance z rx-diff-dc dc 80 100 120 differential output impedance z tx-diff-dc dc 80 100 120 common-mode resistance to gnd z rx-high- imp-dc-pos v in_p = v in_m = 0 to +200mv, input terminations not powered 50 k common-mode resistance to gnd z rx-high- imp-dc-neg v in_p = v in_m = -150mv to 0, input terminations not powered 1 k common-mode resistance to gnd, input terminations powered z rx-dc 40 50 60 output short-circuit current i tx-short single-ended 90 ma common-mode delta between active and idle states v tx-cm-dc- active- idle-delta v o_amp_ = v gnd 100 mv dc output offset during active state v tx-cm-dc- line-delta |v out_p - v out_m | 25 mv dc output offset during electrical idle v tx-idle- diff-dc |v out_p - v out_m | 10 mv ac performance f = 0.05ghz to 1.25ghz 10 differential input return loss (note 5) rl rx-diff f = 1.25ghz to 2.5ghz 8 db common-mode input return loss (note 5) rl rx-cm f = 0.05ghz to 2.5ghz 6 db
max4950a dual pci express equalizer/redriver _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units f = 0.05ghz to 1.25ghz 10 differential output return loss (note 5) rl tx-diff f = 1.25ghz to 2.5ghz 8 db common-mode output return loss (note 5) rl tx-cm f = 0.05ghz to 2.5ghz 6 db redriver-operation differential input signal range v rx-diff-pp f = 0.05ghz to 2.5ghz 120 1200 mv p-p full-swing no-deemphasis differential output voltage v tx-diff-pp abs|v out_p - v out_m |; o_amp_ = gnd 800 1000 1200 mv p-p low-swing no-deemphasis differential output voltage v tx-diff- pp-low abs|v out_p - v out_m |; o_amp_ = v cc 600 750 900 mv p-p output deemphasis ratio, 0db v tx-de- ratio-0db f = 2.5ghz, ode_1 = gnd, ode_0 = gnd, figure 1 (see table 3) 0 db output deemphasis ratio, 3.5db v tx-de- ratio-3.5db f = 2.5ghz, ode_1 = gnd, ode_0 = v cc , figure 1 (see table 3) 3.5 db output deemphasis ratio, 6db v tx-de- ratio-6db f = 2.5ghz, ode_1 = v cc , ode_0 = v cc or gnd, figure 1 (see table 3) 6 db input equalization, 0db (note 6) v rx-eq- 0db f = 2.5ghz, ineq_1 = gnd, ineq_0 = gnd (see table 2) 0 db input equalization, 3.5db (note 6) v rx-eq- 3.5db f = 2.5ghz, ineq_1 = gnd, ineq_0 = v cc (see table 2) 3.5 db input equalization, 6db (note 6) v rx-eq- 6db f = 2.5ghz, ineq_1 = v cc , ineq_0 = v cc or gnd (see table 2) 6 db output common-mode voltage v tx-cm-ac- pp max(v out_p + v out_m )/2 - min(v out_p + v out_m )/2 100 mv p-p propagation delay (note 5) t pd f = 2.5ghz 160 280 400 ps rise/fall time t tx-rise- fall (note 7) 30 ps rise/fall time mismatch t tx-rf- miismatch (note 7) 20 ps same-pair output skew (note 5) t sk f = 2.5ghz 10 15 ps lane-to-lane output skew (note 5) t skl f = 2.5ghz -50 +50 ps deterministic jitter (note 5) t tx-dj-dd k28.5 pattern, 5.0gt/s, ac coupled, r l = 50 , effects of deemphasis deembedded 15 ps p-p random jitter t tx-rj-dd dio.2 pattern 1.4 ps rms electrical idle entry delay t tx-idle- set-to-idle from input to output 15 ns electrical idle exit delay t tx-idle-to- diff-data from input to output 12 ns electrical characteristics (continued) (v cc = +3.0v to +3.6v, c cl = 75nf coupling capacitor on each output, r l = 50 resistor on each output, t a = 0? to +70?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (note 3)
max4950a dual pci express equalizer/redriver 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +3.0v to +3.6v, c cl = 75nf coupling capacitor on each output, r l = 50 resistor on each output, t a = 0? to +70?, unless otherwise noted. typical values are at v cc = +3.3v and t a = +25?.) (note 3) parameter symbol conditions min typ max units electrical idle detect threshold v tx-idle- thresh 65 95 120 mv p-p output voltage during electrical idle (ac) v tx-idle- diff-ac-p abs|v out_p - v out_m |, f = 500mhz 25 mv p-p receiver detect pulse amplitude (note 5) v tx-rcv- detect voltage change in positive direction 600 mv receiver detect pulse width 100 ns receiver detect retry period 200 ns control logic (ineq_1, ineq_0, ode_1, ode_0, en, rx_det, o_amp_) input logic-level low v il 0.6 v input logic-level high v ih 1.4 v input logic hysteresis v hyst 130 mv input leakage current i in v control_logic = +0.5v or +1.5v -50 +50 a note 3: all devices are 100% production tested at t a = +70?. specifications for all temperature limits are guaranteed by design. note 4: currents are applicable for both pcie generation i and generation ii speeds. table 5 summarizes the predicted power consumption. note 5: guaranteed by design, unless otherwise noted. note 6: equivalent to the same amount of deemphasis driving the output. note 7: rise and fall times are measured using 20% and 80% levels. timing diagram v low_p-p pe(db) = 20 [ log ( )] v high_p-p v low_p-p v high_p-p figure 1. illustration of output deemphasis
max4950a dual pci express equalizer/redriver _______________________________________________________________________________________ 5 typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) ineq_0 = ineq_1 = 0, o_amp_ = 0, v in = 200mv p-p , ode_0 = 0, ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 200 400 600 -600 -400 -200 eye diagram voltage (mv) max4950a toc01 ineq_0 = ineq_1 = 0, o_amp_ = 0, v in = 200mv p-p , ode_0 = 1, ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 200 400 600 -600 -400 -200 eye diagram voltage (mv) max4950a toc02 ineq_0 = ineq_1 = 0, o_amp_ = 0, v in = 200mv p-p , ode_0 = 0, ode_1 = 1 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 100 300 200 400 500 -500 -300 -400 -200 -100 eye diagram voltage (mv) max4950a toc03 ineq_0 = ineq_1 = 0, o_amp_ = 1, v in = 200mv p-p , ode_0 = 0, ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 100 300 200 400 500 -500 -300 -400 -200 -100 eye diagram voltage (mv) max4950a toc04 ineq_0 = ineq_1 = 0, o_amp_ = 1, v in = 200mv p-p , ode_0 = 1, ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 100 300 200 400 -400 -300 -200 -100 eye diagram voltage (mv) max4950a toc05 ineq_0 = ineq_1 = 0, o_amp_ = 1, v in = 200mv p-p , ode_0 = 0, ode_1 = 1 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 100 300 200 400 -400 -300 -200 -100 eye diagram voltage (mv) max4950a toc06
max4950a dual pci express equalizer/redriver 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.) ineq_0 = 1, ineq_1 = 0, o_amp_ = 0, v in = 500mv p-p , with 6in stripline ode_0 = ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 400 200 600 -600 -400 -200 eye diagram voltage (mv) max4950a toc07 ineq_0 = 0, ineq_1 = 1, o_amp_ = 0, v in = 500mv p-p , with 19in stripline ode_0 = ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 400 200 600 -600 -400 -200 eye diagram voltage (mv) max4950a toc08 ineq_0 = ineq_1 = 0, o_amp_ = 0, v in = 500mv p-p , with 19in stripline ode_0 = ode_1 = 0 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 400 200 600 -600 -400 -200 eye diagram voltage (mv) max4950a toc09 ineq_0 = ineq_1 = 0, o_amp_ = 1, v in = 200mv p-p , ode_0 = 1, ode_1 = 0, output after 6in stripline 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 100 300 200 400 -400 -300 -200 -100 eye diagram voltage (mv) max4950a toc10 ineq_0 = ineq_1 = 0, o_amp_ = 0, v in = 200mv p-p , ode_0 = 0, ode_1 = 1, output after 19in stripline 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 50 150 100 200 250 -250 -150 -200 -100 -50 eye diagram voltage (mv) max4950a toc11 ineq_0 = ineq_1 = 0, o_amp_ = 0, v in = 200mv p-p , ode_0 = 0, ode_1 = 0, output after 19in stripline 0ps 50ps 100ps 150ps -150ps-100ps -50ps 0 100 300 200 400 500 -500 -300 -400 -200 -100 eye diagram voltage (mv) max4950a toc12
max4950a dual pci express equalizer/redriver _______________________________________________________________________________________ 7 pin description pin name function 1, 4, 6, 9, 19, 22, 24, 27 gnd ground 2 inap noninverting input a 3 inam inverting input a 5 en enable input. drive en low for standby mode. drive en high for normal mode. en is internally pulled down by a 50k (typ) resistor. 7 outbp noninverting output b 8 outbm inverting output b 10, 18, 28, 36 n.c. no connection. not internally connected. 11, 17, 29, 35 v cc power-supply input. bypass v cc to gnd with 1f and 0.01f capacitors in parallel as close as possible to the device. 12 odeb1 output b deemphasis control msb. odeb1 is internally pulled down by a 50k (typ) resistor. see table 3. 13 odeb0 output b deemphasis control lsb. odeb0 is internally pulled down by a 50k (typ) resistor. see table 3. 14 o_ampb output b amplitude selection input. o_ampb is internally pulled down by a 50k (typ) resistor. 15 ineqb1 input b equalization control msb. ineqb1 is internally pulled down by a 50k (typ) resistor. see table 2. 16 ineqb0 input b equalization control lsb. ineqb0 is internally pulled down by a 50k (typ) resistor. see table 2. 20 inbm inverting input b 21 inbp noninverting input b 23 rx_det receiver-detection control bit. toggle rx_det to initiate receiver detection. rx_det is internally pulled down by a 50k (typ) resistor. 25 outam inverting output a 26 outap noninverting output a 30 odea0 output a deemphasis control lsb. odea0 is internally pulled down by a 50k (typ) resistor. see table 3. 31 odea1 output a deemphasis control msb. odea1 is internally pulled down by a 50k (typ) resistor. see table 3. 32 o_ampa output a amplitude selection input. o_ampa is internally pulled down by a 50k (typ) resistor. 33 ineqa0 input a equalization control lsb. ineqa0 is internally pulled down by a 50k (typ) resistor. see table 2. 34 ineqa1 input a equalization control msb. ineqa1 is internally pulled down by a 50k (typ) resistor. see table 2. ep exposed pad. internally connected to gnd. connect ep to a large gr ound plane to maximize thermal performance. ep is not intended as an electrical connection point.
max4950a dual pci express equalizer/redriver 8 _______________________________________________________________________________________ max4950a equalizer equalizer ineq_0 ineq_1 in_p in_m r hi electrical idle detector receiver detect manager global power save o_amp_ rx_det en out_p out_m ode_0 ode_1 figure 2. block diagram of each channel
max4950a dual pci express equalizer/redriver _______________________________________________________________________________________ 9 detailed description the max4950a dual equalizer/redriver is designed to support both gen i (2.5gt/s) and gen ii (5.0gt/s) pcie data rates. the device contains two identical drivers with idle/receive detect on each lane and equalization to compensate for circuit-board loss. signal integrity at the receiver is improved by the use of programmable input equalization circuitry. the max4950a features individual channel output amplitude selection inputs, o_ampa and o_ampb (table 1), and programmable output deemphasis, permitting optimal placement of key pcie components and longer runs of stripline, microstrip, or cable. programmable input equalization the max4950a features programmable input equaliz- ers capable of providing 0db, 3.5db, or 6db of high- frequency boost on either channel (see table 2). programmable output deemphasis the max4950a features programmable output deem- phasis on either channel by setting two control bits, ode_1 and ode_0, for deemphasis ratios of 0db, 3.5db, and 6db (see table 3). receiver detection the max4950a features receiver detection on each channel. upon initial power-up, if en is high, receiver detection initializes. receiver detection can also be ini- tiated on a rising or falling edge of the rx_det input when en is high. during this time, the part remains in low-power standby mode and the outputs are squelched, despite the logic-high state of en. once started, receiver detection repeats indefinitely on each channel. once a receiver is detected on one of the channels, up to three more attempts are made on the other channel. upon receiver detection, channel output and electrical idle detection are enabled (see table 4). electrical idle detection the max4950a features electrical idle detection to pre- vent unwanted noise from being redriven at the output. if the max4950a detects that the differential input has fallen below v tx-idle-thresh , the max4950a squelch- es the output. for differential input signals that are above v tx-idle-thresh , the max4950a turns on the output and redrives the signal. power-saving features the max4950a features an enable input (en) to shut down the device and reduce supply current. to place the device in shutdown mode, drive en low. to enable the device, drive en high. during normal operation, supply current can also be reduced by reducing the channel output amplitudes. table 5 shows typical power consumption differences between shutdown mode and normal operation with different output redrive strengths. o_ampa/ o_ampb differential output voltage (mv p-p ) 0 1000 (typ) 1 750 (typ) table 1. output amplitude selection table 2. input equalization x = don? care. x = don? care. ode_1 ode_0 output deemphasis ratio (db) 0 0 0 0 1 3.5 (typ) 1 x 6 (typ) table 3. output deemphasis rx_det en description x 0 receiver detection inactive 01 fol l ow i ng a r i si ng or fal l i ng ed g e, i nd efi ni te r etr y unti l r ecei ver d etected ri si ng or fal li ng e dg e 1 initiate receiver detection 11 fol l ow i ng a r i si ng or fal l i ng ed g e, i nd efi ni te r etr y unti l r ecei ver d etected table 4. receiver-detection input function x = don? care. ineq_1 ineq_0 input equalization (db) 0 0 0 0 1 3.5 (typ) 1 x 6 (typ)
max4950a dual pci express equalizer/redriver maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. applications information layout circuit-board layout and design can significantly affect the performance of the max4950a. use good high-fre- quency design techniques, including minimizing ground inductance and using controlled-impedance transmission lines on data signals. it is recommended to run receive and transmit on different layers to mini- mize crosstalk and to place power-supply decoupling capacitors as close as possible to v cc . always con- nect v cc to a power plane. exposed pad package the exposed-pad, 36-pin, tqfn package incorporates features that provide a very low thermal resistance path for heat removal from the ic. the exposed pad on the max4950a must be soldered to the circuit-board ground plane for proper thermal performance. for more information on exposed-pad packages, refer to maxim application note hfan-08.1: thermal considerations of qfn and other exposed-paddle packages . power-supply sequencing caution: do not exceed the absolute maximum rat- ings because stresses beyond the listed ratings may cause permanent damage to the device. proper power-supply sequencing is recommended for all devices. always apply gnd then v cc before apply- ing signals, especially if the signal is not current limited. chip information process: bicmos en o_ampb o_ampa quiescent power supply current (typ) (ma) quiescent power supply current (max) (ma) quiescent power dissipation (3.3v, typ) (mw) quiescent power dissipation (3.6v, max) (mw) 0 0 0 60 75 198 270 0 0 1 55 68 182 243 0 1 0 55 68 182 243 0 1 1 50 60 165 216 1 0 0 130 165 429 594 1 0 1 125 157 413 565 1 1 0 125 157 413 565 1 1 1 120 150 396 540 table 5. quiescent power dissipation with equalization and deemphasis pcie tx rx northbridge pcie x1 connector 0.5m to 2m cable max4950a figure 3. typical application circuit?ax4950a used as x1 lane cable driver package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 36 tqfn t3666+2 21-0141
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