the SY89429A is a general purpose, synthesized clock source targeting applications that require both serial and parallel interfaces. its internal vco will operate over a range of frequencies from 400mhz to 800mhz. the differential pecl output can be configured to be the vco frequency divided by 2, 4, 8 or 16. with the output configured to divide the vco frequency by 2, and with a 16mhz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1mhz steps. features description rev.: h amendment: /0 issue date: october, 1998 clockworks SY89429A final programmable frequency synthesizer (25mhz to 400mhz) improved jitter performance over sy89429 25mhz to 400mhz differential pecl outputs 25ps peak-to-peak output jitter minimal frequency over-shoot synthesized architecture serial 3 wire interface parallel interface for power-on internal quartz reference oscillator driven by quartz crystal or pecl source pecl output can operate with either +3.3v or +5v vcc_out power supply external loop filter optimizes performance/cost applications note (an-06) for ease of design-ins available in plcc and soic 28-pin packages pin configuration applications workstations advanced communications high end consumer high-performance computing risc cpu clock graphics pixel clock test equipment other high-performance processor-based applications 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 5 67891011 v cc_quie t xtal1 s _clock s _data loop_ ref s _loa d loop _filter v cc1 m[3] m[0] m[1] m[2] xtal2 p _load m[8] m[4] m[7] m[5] n[1] m[6] n[0] fout v cc_out test gnd v cc (ttl) gnd (ttl) fout plcc top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 27 28 26 25 24 23 22 21 20 19 18 17 16 15 m[0] m[1] m[2] m[3] m[4] m[5] m[6] m[7] m[8] n[0] n[1] gnd (ttl) test v cc (ttl) p _load v cc1 xtal 2 xtal 1 loop _ref loop _filter v cc_quiet s _load s _data s _clock v cc_out fout fout gnd top view soic z28-1 1
2 clockworks SY89429A micrel block diagram detailed block diagram note: pin numbers reference plcc pinout. +5.0v phase detector pll vco ?n f ref pecl 400 ?800 mhz test config info 3 wire interface 10-25mhz fundamental crystal or pecl source fout osc interface logic serial parallel 8 m +5.0v phase detector 8 osc fref fout vco 400-800 mhz v cc_quiet 23 1 xtal1 xtal2 25 v cc_out fout 24 23 latch 3-bit sr 01 01 6, 21 8 -> 16 9 m[8:0] 17,18 n[1:0] 19,22 s_ clock s_ data p_ load s_ load 4 5 28 7 27 26 10 25mhz fundamental crystal or pecl source v cc1 n (2,4,8,16) 2 10 9-bit m counter latch latch 2-bit sr 9-bit sr test 20 t110 +5.0v +5.0v l = latch h = transparent loop_ref loop_filter 7 fout 4 s_ clock m low fout m fref high 6 5 4 3 2 1 0
3 clockworks SY89429A micrel inputs xtal1, xtal2 these pins form an oscillator when connected to an external crystal. the crystal is series resonant. alternatively, these pins can be driven with 100k pecl level by an external source. s_ load this ttl pin loads the configuration latches with the contents of the shift registers. the latches will be transparent when this signal is high; thus, the register data must be stable on the high-to-low transition of s_ load for proper operation. s_ data this ttl pin is the input to the serial configuration shift registers. s_ clock this ttl pin clocks the serial configuration shift registers. on the rising edge of this signal, data from s_ data is sampled. p_ load this ttl pin loads the configuration latches with the contents of the parallel inputs. the latches will be transparent when this signal is low; thus, the parallel data must be stable on the low-to-high transition of p_ load for proper operation. m[8:0] these ttl pins are used to configure the pll loop divider. they are sampled on the low-to-high transition of p_ load . m[8] is the msb, m[0] is the lsb. the binary count on the m pins equates to the divide-by value for the pll. n[1:0] these ttl pins are used to configure the output divider modulus. they are sampled on the low-to-high transition of p_ load . outputs fout, fout these differential positive-referenced ecl signals (pecl) are the output of the synthesizer. test the function of this ttl output is determined by the serial configuration bits t[2:0]. power v cc1 this is the positive supply for the chip and is normally connected to +5.0v. v cc_out this is the positive reference for the pecl outputs, fout and fout. it is constrained to be less than or equal to vcc1 . v cc_quiet this is the positive supply for the pll and should be as noise- free as possible for low-jitter operation. gnd these pins are the negative supply for the chip and are normally all connected to ground. other loop_filter this is an analog i/o pin that provides the loop filter for the pll. loop_ref this is an analog i/o pin that provides a reference voltage for the pll. pin descriptions n[1:0] output division 0 0 2 0 1 4 1 0 8 1 1 16
4 clockworks SY89429A micrel in 50 ? . the positive reference for the output driver is provided by a dedicated power pin (v cc_out ) to reduce noise and provide application flexibility. the configuration logic has two sections: serial and parallel. the parallel interface uses the values at the m[8:0] and n[1:0] inputs to configure the internal counters. normally upon system reset, the p_ load input is held low until sometime after power becomes valid. with s_ load held low, on the low- to-high transition of p_ load , the parallel inputs are captured. the parallel interface has priority over the serial interface. internal pull-up resistors are provided on the m[8:0] and n[1:0] inputs to reduce component count. the serial interface logic is implemented with a 14-bit shift register scheme. the register shifts once per rising edge of the s_ clock input. the serial input s_ data must meet set-up and hold timing as specified in the ac parameters section of this data sheet. with p_ load held high, the configuration latches will capture the value in the shift register on the high-to-low edge of the s_ load input. see the programming section for more information. the test output reflects various internal node values and is controlled by the t[2:0] bits in the serial data stream. see the programming section for more information. symbol parameter value unit v cc power supply voltage 0.5 to +7.0 v v i input voltage 0.5 to +7.0 v i out output source continuous 50 ma surge 100 t store storage temperature 65 to +150 c t a operating temperature 0 to +75 c with 16mhz input absolute maximum ratings (1) note: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data sheet. exposure to absolute maximum ratlng condi tions for extended periods may affect device reliability. the internal oscillator uses the external quartz crystal as the basis of its frequency reference. the output of the reference oscillator is divided by eight before being sent to the phase detector. with a 16mhz crystal, this provides a reference frequency of 2mhz. the vco within the pll operates over a range of 400 800mhz. its output is scaled by a divider that is configured by either the serial or parallel interfaces. the output of this loop divider is also applied to the phase detector. the phase detector and loop filter force the vco output frequency to be m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low) the pll will not achieve loop lock. external loop filter components are utilized to allow for optimal phase jitter performance. the output of the vco is also passed through an output divider before being sent to the pecl output driver. the output divider is configured through either the serial or the parallel interfaces and can provide one of four divider ratios (2, 4, 8 or 16). this divider extends the performance of the part while providing a 50% duty cycle. the output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated functional description vco frequency 256 128 64 32 16 8421 (mhz) m count m8 m7 m6 m5 m4 m3 m2 m1 m0 400 200 011001000 402 201 011001001 404 202 011001010 406 203 011001011 794 397 110001101 796 398 110001110 798 399 110001111 800 400 110010000
5 clockworks SY89429A micrel m,n s _clock s _data s _load p _load m[8:0] n[1:0] t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 programming interface programming the device is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. the output frequency can be represented by this formula: where f xtal is the crystal frequency, m is the loop divider modulus, and n is the output divider modulus. note that it is possible to select values of m such that the pll is unable to achieve loop lock. to avoid this, always make sure that m is selected to be 200 m 400 for a 16mhz input reference. m[8:0] and n[1:0] are normally specified once at power-on, through the parallel interface, and then possibly again through the serial interface. this approach allows the designer to bring up the application at one frequency and then change or fine- tune the clock, as the ability to control the serial interface becomes available. to minimize transients in the frequency domain, the output should be varied in the smallest step size possible. the test output provides visibility for one of several internal nodes (as determined by the t[1:0] bits in the serial configuration stream). it is not configurable through the parallel interface. although it is possible to select the node that represents fout, the ttl output may not be able to toggle fast enough for some of the higher output frequencies. the t2, t1, t0 configuration latches are preset to 000 when p_load is low, so that the fout outputs are as jitter-free as possible. the serial configuration port can be used to select one of the alternate functions for this pin. the test register is loaded with the first three bits, the n register with the next two and the m register with the final eight bits of the data stream on the s_ data input. for each register the most significant bit is loaded first (t2, n1 and m8). when t[2:0] is set to 100 the SY89429A is placed in pll bypass mode. in this mode the s_ clock input is fed directly into the m and n dividers. the n divider drives the fout differential pair and the m counter drives the test output pin. in this mode the s_ clock input could be used for low speed board level functional test or debug. bypassing the pll and driving fout directly gives the user more control on the test clocks sent through the clock tree (see detailed block diagram). because the s_ clock is a ttl level the input frequency is limited to 250mhz or less. this means the fastest the fout pin can be toggled via the s_ clock is 125mhz as the minimum divide ratio of the n counter is 2. note that the m counter output on the test output will not be a 50% duty cycle due to the way the divider is implemented. input s_ data to m0 then m1, then m2, etc., as indicated above. first bit last bit t2 t1 t0 test fout / fout 0 0 0 data out last bit sr fvco n 0 0 1 high fvco n 0 1 0 fref fvco n 0 1 1 m counter output fvco n 1 0 0 fout fvco n 1 0 1 low fvco n 110s_ clock ms_ clock n 1 1 1 fout 4 fvco n fout = ( ) x fxtal 8 m n
6 clockworks SY89429A micrel t a = 0 ct a = +25 ct a = +75 c symbol parameter min. max. min. max. min. max. unit condition v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i ih input high current 50 50 50 av in = 2.7v i il input low current 0.6 0.6 0.6 ma v in = 0.5v v ik input clamp voltage 1.2 1.2 1.2 v i in = 12ma v oh output high voltage 2.5 2.5 2.5 v i oh = 2.0ma v ol output low voltage 0.5 0.5 0.5 v i ol = 8ma i os output short circuit current 80 (typ.) 80 (typ.) 80 (typ.) ma v out = 0v i cc1 supply current 225 225 225 ma typical % of i cc1 v cc1 91% 91% 91% v cc_out 4.5% 4.5% 4.5% v cc_quiet 2.25% 2.25% 2.25% v cc_ttl 2.25% 2.25% 2.25% symbol parameter min. max. unit condition v oh output high voltage v cc_out 1.075 v cc_out 0.830 v 50 ? to v cc_out 2v v ol output low voltage v cc_out 1.860 v cc_out 1.570 v 50 ? to v cc_out 2v 100h ecl dc electrical characteristics v cc1 = v cc_quiet = v cc_ttl = +5.0v 5%; v cc_out = +3.3v to +5.0v 5%; t a = 0 c to +75 c ttl dc electrical characteristics v cc1 = v cc_quiet = v cc_ttl = +5.0v 5%; v cc_out = +3.3v to +5.0v 5%; t a = 0 c to +75 c t a = 0 ct a = +25 ct a = +75 c symbol parameter min. max. min. max. min. max. unit condition f maxi maximum input frequency (1) s_ clock 10 10 10 mhz fundamental xtal oscillator 10 25 10 25 10 25 cyrstal f maxo maximum output frequency vco (internal) 400 800 400 800 400 800 mhz fout 25 400 25 400 25 400 t lock maximum pll lock time 10 10 10 ms t jitter cycle-to-cycle jitter (peak-topeak) 25 25 25 ps test output static t s setup time s_ data to s_ clock 20 20 20 ns s_ clock to s_ load 20 20 20 m, n to p_ load 20 20 20 t h hold time s_ data to s_ clock 20 20 20 ns s_ clock to s_ load 20 20 20 m, n to p_ load 20 20 20 t pw(min) minimum pulse width s_ load 50 50 50 ns p_ load 50 50 50 t dc fout duty cycle 45 55 45 55 45 55 % t r output rise/fall fout 300 800 300 800 300 800 ps t f 20% to 80% ac electrical characteristics v cc1 = v cc_quiet = v cc_ttl = +5.0v 5%; v cc_out = +3.3v to +5.0v 5%; t a = 0 c to +75 c note: 1. 10mhz is the maximum frequency to load the feedback divide registers. s_ clock can be switched at high frequencies when used as a test clock in test_mode 6.
7 clockworks SY89429A micrel timing diagram product ordering code ordering package operating code type range SY89429Ajc j28-1 commercial SY89429Ajctr j28-1 commercial SY89429Azc z28-1 commercial SY89429Azctr z28-1 commercial s_ data s_ clock s_ loa d m[8:0] n[1:0] p_ load t hold t set-up t set-up t set-up t hold
8 clockworks SY89429A micrel 28 lead soic .300" wide (z28-1) rev. 02
9 clockworks SY89429A micrel 28 lead plcc (j28-1) rev. 03 micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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