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1 5336a?hirel?08/03 features ? pc603e ? microprocessor (embedded powerpc ? core) at 133 - 300 mhz ? 280 mips at 200 mhz (dhrystone 2.1) ? 520 mips at 300 mhz (dhrystone 2.1) ? high-performance, superscalar microprocessor ? disable cpu mode ? improved low-power core ? 16-kbyte data and 16-kbyte instruct ion cache, four-way set associative ? memory management unit (mmu) ? floating point unit (fpu) ? common on-chip processor (cop) ? two bus architectures: one 64-bit powe rpc and one 32-bit pci or local bus ? system integration unit (siu) ? memory controller, including two dedicat ed sdram machines ? pci up to 66 mhz ? hardware bus monitor and software watchdog timer ? ieee 1149.1 jtag test access port ? high-performance communications processor module (cpm) ? cpm frequency up to 200 mhz ? powerpc and cpm may run at different frequencies ? parallel i/o registers ? on-board 32 kbytes of dual-port ram ? two multi-channel controllers (mccs) each supporting 128 full-duplex, 64-kbps, hdlc lines ? virtual dma functionality ? 3 fccs supporting: up to 155 mbps atm sar, maximu m of two (aal0, aal1, aal2, aal5) 10/100 mbps ethernet, up to three (ieee 802.3 x with flow control) 45 mbps hdlc/transparent (up to three) ? two utopia level-2 master/slave ports, both with multi-ph y support. one can support 8/16 bit data ? three mii interfaces ? eight tdm interfaces (t1/e1), two td m ports can be glueless to t3/e3 ? power consumption: 2.5w at 300 mhz description the PC8265A powerquicc ii ? is a versatile communications processor that inte- grates on one chip, a high-performance powerpc (pc603e) risc microprocessor, a highly flexible system integration unit, an d many communications peripheral control- lers that can be used in a variety of app lications, particularly in communications and networking systems. the core is an embedded variant of the pc 603e microprocessor, specifically referred to later in this document as the ec603e, with 16 kbytes of instruction cache and 16 kbytes of data cache and floating-point un it (fpu). the system interface unit (siu) consists of a flexible memory controller t hat interfaces to almost any user-defined memory system, a 60x-to-pci bus bridge and many other peripherals, making this device a complete system on a chip. the communications processor module (cp m) includes all the peripherals found in the pc860, with the addition of three hi gh-performance communication channels that support new emerging protocols (for exam ple, 155-mbps atm and fast ethernet). equipped with dedicated hardware, the PC8265A can handle up to 256 full-duplex, time-division, multiple xed logical channels. powerpc ? - based communications processor PC8265A powerquicc ii ? preliminary specification alpha site
2 PC8265A powerquicc ii 5336a?hirel?08/03 screening quality packaging this product is manufactur ed in full compliance with: ? upscreening based upon atmel standards ? military temper ature range ( t c = -55 c, t c = +125 c) ? 480-ball tape ball grid array package (tbga 37.5 x 37.5 mm) PC8265A architecture general overview figure 1. PC8265A block diagram features the major features of the PC8265A family are as follows: ? dual-issue integer core a core version of the ec603e microprocessor system core microprocessor supporting frequencies of 150 ? 300 mhz separate 16-kbyte data and instruction caches: ? four-way set associative ? physically addressed ? lru replacement algorithm powerpc architecture-compliant memory management unit (mmu) common on-chip processor (cop) test interface 16 kb ytes g2 core i-cache i-mmu 16 kbytes d-cache d-mmu communication processor module (cpm) timers parallel i/o baud rate generators 32 kbytes 32-bit risc microcontroller and program rom serial dmas 4 virtual idmas 60x-to-pci bridge bridge memory controller clock counter system functions system interface unit (siu) mcc1 mcc2 fcc1 fcc2 fcc3 scc1 scc2 scc3 scc4 smc1 smc2 spi i 2 c serial interf ace 3 mii 2 utopia ports ports 60x bus dual-por t ram interrupt controller time slot assigner 8 tdm ports xed i/o 60x-to-local bus interf ace unit local bus 32 bits, up to 83 mhz pci bus 32 bits, up to 66 mhz or non-multiple
3 PC8265A powerquicc ii 5336a?hirel?08/03 high-performance (6 .6 - 7.65 spec95 benchmark at 300 mhz; 1.68 mips/mhz without inlining and 1.90 dhr ystones mips/mhz with inlining) supports bus snooping for data cache coherency floating-point unit (fpu) ? separate power supply for internal logic and for i/o ? separate plls for g2 core and for the cpm g2 core and cpm can run at different frequencies for power/performance optimization internal core/bus clock multiplier that provi des 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios internal cpm/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios ? 64-bit data and 32-bit address 60x bus bus supports multiple master designs supports single- and four-beat burst transfers 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller supports data parity or ecc and address parity ? 32-bit data and 18-bit address local bus single-master bus, supports external slaves eight-beat burst transfers 32-, 16-, and 8-bit port sizes cont rolled by on-chip memory controller ? 60x-to-pci bridge programmable host bridge and agent 32-bit data bus, 66 mhz, 3.3v synchronous and asynchronous 60x and pci clock modes all internal address space available to external pci host dma for memory block transfers pci-to-60x address remapping ? system interface unit (siu) clock synthesizer reset controller real-time clock (rtc) register periodic interrupt timer hardware bus monitor and software watchdog timer ieee 1149.1 jtag test access port ? twelve-bank memory controller glueless interface to sram, page mode sdram, dram, eprom, flash and other user-definable peripherals byte write enables and sele ctable parity generation 32-bit address decoder with programmable bank size three user programmable machines, gener al-purpose chip-select machine, and page-mode pipeline sdram machine byte selects of 64 bus width (60x) and byte selects for 32 bus width (local) dedicated interface logic for sdram
4 PC8265A powerquicc ii 5336a?hirel?08/03 ? cpu core can be disabled and the device can be used in slave mode to an external core ? communications processor module (cpm) embedded 32-bit communications processor (c p) uses a risc architecture for flex- ible support of communications protocols interfaces to g2 core through an on-chip 32-kbyte dual-port ram and dma controller serial dma channels for receive and transmit on all serial channels parallel i/o registers with open -drain and interrupt capability virtual dma functionality executing memory-to-memory and memory-to-i/o transfers three fast communications controllers supporting the following protocols: ? 10/100-mbit etherne t/ieee 802.3 cdma/cs inte rface through a media independent interface (mii) ? atm ? full-duplex sar protocols at 155 mbps, through utopia interface, aal5, aal1, aal0 protocols, tm 4.0 cbr, vbr, ubr, abr traffic types, up to 16 k external connections ? transparent ? hdlc ? up to t3 rates (clear channel) two multichannel controllers (mccs) ? each mcc handles 128 serial, full-duplex, 64-kbps data channels. each mcc can be split into four subgroups of 32 channels each ? almost any combination of subgroups can be multiplexed to single or multiple tdm interfaces up to four tdm interfaces per mcc four serial communications controllers (sccs) identical to those on the pc860, supporting the digital portions of the following protocols: ? ethernet/ieee 802.3 cdma/cs ? hdlc/sdlc and hdlc bus ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? binary synchronous (bisync) communications ? transparent two serial management controllers (smc s), identical to those of the pc860 ? provides management for bri devices as general circuit interface (gci) controllers in time-divisio n-multiplexed (tdm) channels ? transparent ? uart (low-speed operation) one serial peripheral interface identical to the pc860 spi one inter-integrated circuit (i2c) controlle r (identical to the pc860 i2 c controller) ? microwire compatible ? multiple-master, single-master, and slave modes up to eight tdm interfaces ? supports two groups of four tdm channels for a total of eight tdms ? 2,048 bytes of si ram ? bit or byte resolution
5 PC8265A powerquicc ii 5336a?hirel?08/03 ? independent transmit and receive routing, frame synchronization ? supports t1, cept, t1/e1, t3/e3, pulse code modulation highway, isdn basic rate, isdn primary rate, motorola interchip digital link (idl), general circuit interface (gci), and user-defined tdm serial interfaces eight independent baud rate generators and 20 input clock pins for supplying clocks to fccs, sccs, smcs, and serial channels four independent 16-bit timers that can be interconnected as two 32-bit timers ?cpm 32-kbyte dual-port ram additional mcc host commands ? cpm multiplexing fcc2 can also be connected to the tc layer ? pci bridge pci specification revision 2.2 compliant and supports frequencies up to 66 mhz on-chip arbitration support for pci to 60x memory and 60x memory to pci streaming pci host bridge or peripheral capabilities includes 4 dma channels for the following transfers: ? pci-to-60x to 60x-to-pci ? 60x-to-pci to pci-to-60x ? pci-to-60x to pci-to-60x ? 60x-to-pci to 60x-to-pci includes all of the configuration registers (which are automatically loaded from the eprom and used to configure the PC8265A) required by the pci standard as well as message and doorbell registers supports the i2o standard hot-swap friendly (supports the hot swap s pecification as defin ed by picmg 2.1 r1.0 august 3, 1998) support for 66 mhz, 3.3v specification 60x-pci bus core logic which uses a buff er pool to allocate buffers for each port makes use of the local bus signals, so there is no need for additional pins
6 PC8265A powerquicc ii 5336a?hirel?08/03 pinout this section provides the pin assignments and pinout list for the PC8265A. pin assignments figure 2 shows the pinout of the PC8265A?s 480 tbga package as viewed from the top surface. figure 2. pinout of the 480 tbga package as viewed from the top surface 1 2 3 4 5 6 7 8 91011121314151 617181920212223242526272829 not to scale 1 2 3 4 5 6 7 8 9 10111213 141516171819 202122 2324 2526272829 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj
7 PC8265A powerquicc ii 5336a?hirel?08/03 figure 3 shows the side profile of the tbga package to indicate the direction of the top surface view. figure 3. side view of the tbga package table 1 shows the pinout list of the pc826 5a. table 2 on page 31 defines conventions and acronyms used in table 1. table 1. pinout list pin name ball br w5 bg f4 abb irq2 e2 ts e3 a0 g1 a1 h5 a2 h2 a3 h1 a4 j5 a5 j4 a6 j3 a7 j2 a8 j1 a9 k4 a10 k3 a11 k2 a12 k1 a13 l5 a14 l4 a15 l3 a16 l2 copper traces die copper heat spreader (oxidized for insulation) 1.27 mm pitch glob-top dam etched pressure sensitive die polymide tape ca vity adhesive attach soldermask glob-top filled area view
8 PC8265A powerquicc ii 5336a?hirel?08/03 a17 l1 a18 m5 a19 n5 a20 n4 a21 n3 a22 n2 a23 n1 a24 p4 a25 p3 a26 p2 a27 p1 a28 r1 a29 r3 a30 r5 a31 r4 tt0 f1 tt1 g4 tt2 g3 tt3 g2 tt4 f2 tbst d3 tsiz0 c1 tsiz1 e4 tsiz2 d2 tsiz3 f5 aack f3 artry e1 dbg v1 dbb irq3 v2 d0 b20 d1 a18 d2 a16 d3 a13 d4 e12 d5 d9 table 1. pinout list (continued) pin name ball
9 PC8265A powerquicc ii 5336a?hirel?08/03 d6 a6 d7 b5 d8 a20 d9 e17 d10 b15 d11 b13 d12 a11 d13 e9 d14 b7 d15 b4 d16 d19 d17 d17 d18 d15 d19 c13 d20 b11 d21 a8 d22 a5 d23 c5 d24 c19 d25 c17 d26 c15 d27 d13 d28 c11 d29 b8 d30 a4 d31 e6 d32 e18 d33 b17 d34 a15 d35 a12 d36 d11 d37 c8 d38 e7 d39 a3 d40 d18 d41 a17 table 1. pinout list (continued) pin name ball
10 PC8265A powerquicc ii 5336a?hirel?08/03 d42 a14 d43 b12 d44 a10 d45 d8 d46 b6 d47 c4 d48 c18 d49 e16 d50 b14 d51 c12 d52 b10 d53 a7 d54 c6 d55 d5 d56 b18 d57 b16 d58 e14 d59 d12 d60 c10 d61 e8 d62 d6 d63 c2 dp0 rsrv ext_br2 b22 irq1 dp1 ext_bg2 a22 irq2 dp2 tlbisync ext_dbg2 e21 irq3 dp3 ckstp_out ext_br3 d21 table 1. pinout list (continued) pin name ball
11 PC8265A powerquicc ii 5336a?hirel?08/03 irq4 dp4 core_sreset ext_bg3 c21 irq5 dp5 tben ext_dbg3 b21 irq6 dp6 cse0 a21 irq7 dp7 cse1 e20 psdval v3 ta c22 tea v5 gbl irq1 w1 ci baddr29 irq2 u2 wt baddr30 irq3 u3 l2_hit irq4 y4 cpu_bg baddr31 irq5 u4 cpu_dbg r2 cpu_br y3 cs0 f25 cs1 c29 cs2 e27 cs3 e28 cs4 f26 cs5 f27 cs6 f28 cs7 g25 table 1. pinout list (continued) pin name ball
12 PC8265A powerquicc ii 5336a?hirel?08/03 cs8 d29 cs9 e29 cs10 bctl1 f29 cs11 ap0 g28 baddr27 t5 baddr28 u1 ale t2 bctl0 a27 pwe0 psddqm0 pbs0 c25 pwe1 psddqm1 pbs1 e24 pwe2 psddqm2 pbs2 d24 pwe3 psddqm3 pbs3 c24 pwe4 psddqm4 pbs4 b26 pwe5 psddqm5 pbs5 a26 pwe6 psddqm6 pbs6 b25 pwe7 psddqm7 pbs7 a25 psda10 pgpl0 e23 psdwe pgpl1 b24 poe psdras pgpl2 a24 table 1. pinout list (continued) pin name ball
13 PC8265A powerquicc ii 5336a?hirel?08/03 psdcas pgpl3 b23 pgta pupmwait pgpl4 ppbs a23 psdamux pgpl5 d22 lwe0 lsddqm0 lbs0 pci_cfg0 h28 lwe1 lsddqm1 lbs1 pci_cfg1 h27 lwe2 lsddqm2 lbs2 pci_cfg2 h26 lwe3 lsddqm3 lbs3 pci_cfg3 g29 lsda10 lgpl0 pci_modckh0 d27 lsdwe lgpl1 pci_modckh1 c28 loe lsdras lgpl2 pci_modckh2 e26 lsdcas lgpl3 pci_modckh3 d25 lgta lupmwait lgpl4 lpbs c26 table 1. pinout list (continued) pin name ball
14 PC8265A powerquicc ii 5336a?hirel?08/03 lgpl5 lsdamux pci_modck b27 lwr d28 l_a14 par n27 l_a15 frame smi t29 l_a16 trdy r27 l_a17 irdy ckstp_out r26 l_a18 stop r29 l_a19 devsel r28 l_a20 idsel w29 l_a21 perr p28 l_a22 serr n26 l_a23 req0 aa27 l_a24 req1 hsejsw p29 l_a25 gnt0 aa26 l_a26 gnt1 hsled n25 l_a27 gnt2 hsenum aa25 l_a28 rst core_sreset ab29 l_a29 inta ab28 table 1. pinout list (continued) pin name ball
15 PC8265A powerquicc ii 5336a?hirel?08/03 l_a30 req2 p25 l_a31 dllout ab27 lcl_d0 ad0 h29 lcl_d1 ad1 j29 lcl_d2 ad2 j28 lcl_d3 ad3 j27 lcl_d4 ad4 j26 lcl_d5 ad5 j25 lcl_d6 ad6 k25 lcl_d7 ad7 l29 lcl_d8 ad8 l27 lcl_d9 ad9 l26 lcl_d10 ad10 l25 lcl_d11 ad11 m29 lcl_d12 ad12 m28 lcl_d13 ad13 m27 lcl_d14 ad14 m26 lcl_d15 ad15 n29 lcl_d16 ad16 t25 lcl_d17 ad17 u27 table 1. pinout list (continued) pin name ball
16 PC8265A powerquicc ii 5336a?hirel?08/03 lcl_d18 ad18 u26 lcl_d19 ad19 u25 lcl_d20 ad20 v29 lcl_d21 ad21 v28 lcl_d22 ad22 v27 lcl_d23 ad23 v26 lcl_d24 ad24 w27 lcl_d25 ad25 w26 lcl_d26 ad26 w25 lcl_d27 ad27 y29 lcl_d28 ad28 y28 lcl_d29 ad29 y25 lcl_d30 ad30 aa29 lcl_d31 ad31 aa28 lcl_dp0 c0 be0 l28 lcl_dp1 c1 be1 n28 lcl_dp2 c2 be2 t28 lcl_dp3 c3 be3 w28 table 1. pinout list (continued) pin name ball
17 PC8265A powerquicc ii 5336a?hirel?08/03 irq0 nmi_out t1 irq7 int_out ape d1 trst ah3 tck ag5 tms aj3 tdi ae6 tdo af5 tris ab4 poreset ag6 hreset ah5 sreset af6 qreq aa3 rstconf aj4 modck1 ap1 tc0 bnksel0 w2 modck2 ap2 tc1 bnksel1 w3 modck3 ap3 tc2 bnksel2 w4 xfc ab2 clkin1 ah4 pa0 restart1 dreq3 fcc2_utm_txaddr2 ac29 pa1 reject1 fcc2_utm_txaddr1 done3 ac25 table 1. pinout list (continued) pin name ball
18 PC8265A powerquicc ii 5336a?hirel?08/03 pa2 clk20 fcc2_utm_txaddr0 dack3 ae28 pa3 clk19 fcc2_utm_rxaddr0 dack4 l1rxd1a2 ag29 pa4 reject2 fcc2_utm_rxaddr1 done4 ag28 pa5 restart2 dreq4 fcc2_utm_rxaddr2 ag26 pa6 l1rsynca1 ae24 pa7 smsyn2 l1tsynca1 l1gnta1 ah25 pa8 smrxd2 l1rxd0a1 l1rxda1 af23 pa9 smtxd2 l1txd0a1 ah23 pa10 fcc1_ut8_rxd0 fcc1_ut16_rxd8 msnum5 ae22 pa11 fcc1_ut8_rxd1 fcc1_ut16_rxd9 msnum4 ah22 pa12 fcc1_ut8_rxd2 fcc1_ut16_rxd10 msnum3 aj21 table 1. pinout list (continued) pin name ball
19 PC8265A powerquicc ii 5336a?hirel?08/03 pa13 fcc1_ut8_rxd3 fcc1_ut16_rxd11 msnum2 ah20 pa14 fcc1_ut8_rxd4 fcc1_ut16_rxd12 fcc1_rxd3 ag19 pa15 fcc1_ut8_rxd5 fcc1_ut16_rxd13 fcc1_rxd2 af18 pa16 fcc1_ut8_rxd6 fcc1_ut16_rxd14 fcc1_rxd1 af17 pa17 fcc1_ut8_rxd7 fcc1_ut16_rxd15 fcc1_rxd0 fcc1_rxd ae16 pa18 fcc1_ut8_txd7 fcc1_ut16_txd15 fcc1_txd0 fcc1_txd aj16 pa19 fcc1_ut8_txd6 fcc1_ut16_txd14 fcc1_txd1 ag15 pa20 fcc1_ut8_txd5 fcc1_ut16_txd13 fcc1_txd2 aj13 pa21 fcc1_ut8_txd4 fcc1_ut16_txd12 fcc1_txd3 ae13 pa22 fcc1_ut8_txd3 fcc1_ut16_txd11 af12 pa23 fcc1_ut8_txd2 fcc1_ut16_txd10 ag11 table 1. pinout list (continued) pin name ball
20 PC8265A powerquicc ii 5336a?hirel?08/03 pa24 fcc1_ut8_txd1 fcc1_ut16_txd9 msnum1 ah9 pa25 fcc1_ut8_txd0 fcc1_ut16_txd8 msnum0 aj8 pa26 fcc1_utm_rxclav fcc1_uts_rxclav fcc1_mii_rx_er ah7 pa27 fcc1_ut_rxsoc fcc1_mii_rx_dv af7 pa28 fcc1_utm_rxenb fcc1_uts_rxenb fcc1_mii_tx_en ad5 pa29 fcc1_ut_txsoc fcc1_mii_tx_er af1 pa30 fcc1_utm_txclav fcc1_uts_txclav fcc1_mii_crs fcc1_rts ad3 pa31 fcc1_utm_txenb fcc1_uts_txenb fcc1_mii_col ab5 pb4 fcc3_txd3 fcc2_ut8_rxd0 l1rsynca2 fcc3_rts ad28 pb5 fcc3_txd2 fcc2_ut8_rxd1 l1tsynca2 l1gnta2 ad26 table 1. pinout list (continued) pin name ball
21 PC8265A powerquicc ii 5336a?hirel?08/03 pb6 fcc3_txd1 fcc2_ut8_rxd2 l1rxda2 l1rxd0a2 ad25 pb7 fcc3_txd0 fcc3_txd fcc2_ut8_rxd3 l1txda2 l1txd0a2 ae26 pb8 fcc2_ut8_txd3 fcc3_rxd0 fcc3_rxd txd3 l1rsyncd1 ah27 pb9 fcc2_ut8_txd2 fcc3_rxd1 l1txd2a2 l1tsyncd1 l1gntd1 ag24 pb10 fcc2_ut8_txd1 fcc3_rxd2 l1rxdd1 ah24 pb11 fcc3_rxd3 fcc2_ut8_txd0 l1txdd1 aj24 pb12 fcc3_mii_crs l1clkob1 l1rsyncc1 txd2 ag22 pb13 fcc3_mii_col l1rqb1 l1tsyncc1 l1gntc1 l1txd1a2 ah21 table 1. pinout list (continued) pin name ball
22 PC8265A powerquicc ii 5336a?hirel?08/03 pb14 fcc3_mii_tx_en rxd3 l1rxdc1 ag20 pb15 fcc3_mii_tx_er rxd2 l1txdc1 af19 pb16 fcc3_mii_rx_er l1clkoa1 clk18 aj18 pb17 fcc3_mii_rx_dv l1rqa1 clk17 aj17 pb18 fcc2_ut8_rxd4 fcc2_rxd3 l1clkod2 l1rxd2a2 ae14 pb19 fcc2_ut8_rxd5 fcc2_rxd2 l1rqd2 l1rxd3a2 af13 pb20 fcc2_ut8_rxd6 fcc2_rxd1 l1rsyncd2 l1txd1a1 ag12 pb21 fcc2_ut8_rxd7 fcc2_rxd0 fcc2_rxd l1tsyncd2 l1gntd2 l1txd2a1 ah11 pb22 fcc2_ut8_txd7 fcc2_txd0 fcc2_txd l1rxd1a1 l1rxdd2 ah16 table 1. pinout list (continued) pin name ball
23 PC8265A powerquicc ii 5336a?hirel?08/03 pb23 fcc2_ut8_txd6 fcc2_txd1 l1rxd2a1 l1txdd2 ae15 pb24 fcc2_ut8_txd5 fcc2_txd2 l1rxd3a1 l1rsyncc2 aj9 pb25 fcc2_ut8_txd4 fcc2_txd3 l1tsyncc2 l1gntc2 l1txd3a1 ae9 pb26 fcc2_mii_crs fcc2_ut8_txd1 l1rxdc2 aj7 pb27 fcc2_mii_col fcc2_ut8_txd0 l1txdc2 ah6 pb28 fcc2_mii_rx_er fcc2_rts l1tsyncb2 l1gntb2 txd1 ae3 pb29 fcc2_utm_rxclav fcc2_uts_rxclav l1rsyncb2 fcc2_mii_tx_en ae2 pb30 fcc2_mii_rx_dv fcc2_ut_txsoc l1rxdb2 ac5 pb31 fcc2_mii_tx_er fcc2_ut_rxsoc l1txdb2 ac4 table 1. pinout list (continued) pin name ball
24 PC8265A powerquicc ii 5336a?hirel?08/03 pc0 dreq1 brgo7 smsyn2 l1clkoa2 ab26 pc1 dreq2 brgo6 l1rqa2 ad29 pc2 fcc3_cd fcc2_ut8_txd3 done2 ae29 pc3 fcc3_cts fcc2_ut8_txd2 dack2 cts4 ae27 pc4 fcc2_utm_rxenb fcc2_uts_rxenb si2_l1st4 fcc2_cd af27 pc5 fcc2_utm_txclav fcc2_uts_txclav si2_l1st3 fcc2_cts af24 pc6 fcc1_cd l1clkoc1 fcc1_utm_rxaddr2 fcc1_uts_rxaddr2 fcc1_utm_rxclav1 aj26 pc7 fcc1_cts l1rqc1 fcc1_utm_txaddr2 fcc1_uts_txaddr2 fcc1_utm_txclav1 aj25 table 1. pinout list (continued) pin name ball
25 PC8265A powerquicc ii 5336a?hirel?08/03 pc8 cd4 rena4 fcc1_ut16_txd0 si2_l1st2 cts3 af22 pc9 cts4 clsn4 fcc1_ut16_txd1 si2_l1st1 l1tsynca2 l1gnta2 ae21 pc10 cd3 rena3 fcc1_ut16_txd2 si1_l1st4 fcc2_ut8_rxd3 af20 pc11 cts3 clsn3 l1clkod1 l1txd3a2 fcc2_ut8_rxd2 ae19 pc12 cd2 rena2 si1_l1st3 fcc1_utm_rxaddr1 fcc1_uts_rxaddr1 ae18 pc13 cts2 clsn2 l1rqd1 fcc1_utm_txaddr1 fcc1_uts_txaddr1 ah18 pc14 cd1 rena1 fcc1_utm_rxaddr0 fcc1_uts_rxaddr0 ah17 table 1. pinout list (continued) pin name ball
26 PC8265A powerquicc ii 5336a?hirel?08/03 pc15 cts1 clsn1 smtxd2 fcc1_utm_txaddr0 fcc1_uts_txaddr0 ag16 pc16 clk16 tin4 af15 pc17 clk15 tin3 brgo8 aj15 pc18 clk14 tgate2 ah14 pc19 clk13 brgo7 ag13 pc20 clk12 tgate1 ah12 pc21 clk11 brgo6 aj11 pc22 clk10 done1 ag10 pc23 clk9 brgo5 dack1 ae10 pc24 fcc2_ut8_txd3 clk8 tout4 af9 pc25 fcc2_ut8_txd2 clk7 brgo4 ae8 table 1. pinout list (continued) pin name ball
27 PC8265A powerquicc ii 5336a?hirel?08/03 pc26 clk6 tout3 tmclk aj6 pc27 fcc3_txd fcc3_txd0 clk5 brgo3 ag2 pc28 clk4 tin1 tout2 cts2 clsn2 af3 pc29 clk3 tin2 brgo2 cts1 clsn1 af2 pc30 fcc2_ut8_txd3 clk2 tout1 ae1 pc31 clk1 brgo1 ad1 pd4 brgo8 l1tsyncd1 l1gntd1 fcc3_rts smrxd2 ac28 pd5 fcc1_ut16_txd3 done1 ad27 pd6 fcc1_ut16_txd4 dack1 af29 table 1. pinout list (continued) pin name ball
28 PC8265A powerquicc ii 5336a?hirel?08/03 pd7 smsyn1 fcc1_utm_txaddr3 fcc1_uts_txaddr3 fcc1_txclav2 af28 pd8 smrxd1 fcc2_ut_txprty brgo5 ag25 pd9 smtxd1 fcc2_ut_rxprty brgo3 ah26 pd10 l1clkob2 fcc2_ut8_rxd1 l1rsyncb1 brgo4 aj27 pd11 l1rqb2 fcc2_ut8_rxd0 l1tsyncb1 l1gntb1 aj23 pd12 si1_l1st2 l1rxdb1 ag23 pd13 si1_l1st1 l1txdb1 aj22 pd14 fcc1_ut16_rxd0 l1clkoc2 i2cscl ae20 pd15 fcc1_ut16_rxd1 l1rqc2 i2csda aj20 pd16 fcc1_ut_txprty l1tsyncc1 l1gntc1 spimiso ag18 table 1. pinout list (continued) pin name ball
29 PC8265A powerquicc ii 5336a?hirel?08/03 pd17 fcc1_ut_rxprty brgo2 spimosi ag17 pd18 fcc1_utm_rxaddr4 fcc1_uts_rxaddr4 fcc1_utm_rxclav3 spiclk af16 pd19 fcc1_utm_txaddr4 fcc1_uts_txaddr4 fcc1_utm_txclav3 spisel brgo1 ah15 pd20 rts4 tena4 fcc1_ut16_rxd2 l1rsynca2 aj14 pd21 txd4 fcc1_ut16_rxd3 l1rxd0a2 l1rxda2 ah13 pd22 rxd4 fcc1_ut16_txd5 l1txd0a2 l1txda2 aj12 pd23 rts3 tena3 fcc1_ut16_rxd4 l1rsyncd1 ae12 pd24 txd3 fcc1_ut16_rxd5 l1rxdd1 af10 pd25 rxd3 fcc1_ut16_txd6 l1txdd1 ag9 table 1. pinout list (continued) pin name ball
30 PC8265A powerquicc ii 5336a?hirel?08/03 pd26 rts2 tena2 fcc1_ut16_rxd6 l1rsyncc1 ah8 pd27 txd2 fcc1_ut16_rxd7 l1rxdc1 ag7 pd28 rxd2 fcc1_ut16_txd7 l1txdc1 ae4 pd29 rts1 tena1 fcc1_utm_rxaddr3 fcc1_uts_rxaddr3 fcc1_utm_rxclav2 ag1 pd30 fcc2_utm_txenb fcc2_uts_txenb txd1 ad4 pd31 rxd1 ad2 syn ab3 syn1 b9 gndsyn ab1 clkin2 (1) ae11 spare4 (2) u5 pci_mode (3) af25 spare6 (2) v4 thermal0 (4) aa1 thermal1 (4) ag4 table 1. pinout list (continued) pin name ball
31 PC8265A powerquicc ii 5336a?hirel?08/03 notes: 1. this pin should be used as clkin2 2. must be pulled down or left floating 3. this pin should be asserted if the pci functi on is desired or pulled up or left floating if pci is not desired 4. for information on how to use this pin, refer to mpc8260 powerquicc ii thermal resistor guide available at www.motorola.com/semiconductors symbols used in table 1 are described in table 2. i/o power ag21, ag14, ag8, aj1, aj2, ah1, ah2, ag3, af4, ae5, ac27, y27, t27, p27, k26, g27, ae25, af26, ag27, ah28, ah29, aj28, aj29, c7, c14, c16, c20, c23, e10, a28, a29, b28, b29, c27, d26, e25, h3, m4, t3, aa4, a1, a2, b1, b2, c3, d4, e5 core power u28, u29, k28, k2 9, a9, a19, b19, m1, m2, y1, y2, ac1, ac2, ah19, aj19, ah10, aj10, aj5 ground aa5, af21, af14, af8, ae7, af11, ae17, ae23, ac26, ab25, y26, v25, t26, r25, p26, m25, k27, h25, g26, d7, d10, d14, d16, d20, d23, c9, e11, e13, e15, e19, e22, b3, g5, h4, k5, m3, p5, t4, y5, aa2, ac3 table 2. symbol legend symbol meaning overbar signals with overbars, such as ta , are active low utm indicates that a signal is part of the utopia master interface uts indicates that a signal is part of the utopia slave interface ut8 indicates that a signal is part of the 8-bit utopia interface ut16 indicates that a signal is part of the 16-bit utopia interface mii indicates that a signal is part of the media independent interface table 1. pinout list (continued) pin name ball
32 PC8265A powerquicc ii 5336a?hirel?08/03 electrical and thermal characteristics this section provides ac and dc electrical specifications and thermal characteristics for the PC8265A. dc electrical characteristics this section describes the dc electrical ch aracteristics for the PC8265A. table 3 shows the maximum electrical ratings. notes: 1. absolute maximum ratings are stress ratings only; functional operation (see table 4) at the maximums is not gu aranteed. stress beyond thos e listed may affect device reliability or cause permanent damage. 2. caution: vdd/syn must not exceed v ddh by more than 0.4v at any time, including during power-on reset. 3. caution: v ddh can exceed vdd/syn by 3.3v during power on reset by no more than 100 ms. v ddh should not exceed vdd/syn by more than 2.5v during normal operation. 4. caution: v in must not exceed v ddh by more than 2.5v at any time, including during power-on reset. table 4 lists recommended operational voltage conditions. notes: 1. caution: these are the recommended and tested operating conditions. proper device operation outside of these co nditions is not guaranteed 2. cpu frequency less than or equal to 200 mhz 3. cpu frequency greater than 200 mhz but less than or equal 233 mhz 4. cpu frequency greater than 233 mhz note: v ddh and v dd must track each other and both must vary in the same direction ? in the positive direction (+5% and +0.1 v dc ) or in the negative direction (-5% and -0.1 v dc ). table 3. absolute maximum ratings (1) rating symbol value unit core supply voltage (2) v dd -0.3 ? +2.5 v pll supply voltage (2) syn -0.3 ? + 2.5 v i/o supply voltage (3) v ddh -0.3 ? + 4.0 v input voltage (4) v in gnd(-0.3) ? + 3.6 v storage temperature range t stg -55 ? +150 c table 4. recommended operating conditions (1) rating symbol value unit core supply voltage v dd 1.7 ? 1.9 (2) 1.7 ? 2.1 (3) 1.9 ? 2.2 (4) v pll supply voltage syn 1.7 ? 1.9 (2) 1.7 ? 2.1 (3) 1.9 ? 2.2 (4) v cpu minimum frequency fmin 150 190 190 mhz i/o supply voltage v ddh 3.135 ? 3.465 v input voltage v in gnd (-0.3) ? 3.465 v tcase t c -55 ? +125 c
33 PC8265A powerquicc ii 5336a?hirel?08/03 this device contains circuitr y protection against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid applica- tion of any voltages higher than maximum-rated voltages. reliability of operation is enhanced if unused inputs are tied to an appropr iate logic voltage level (either gnd or v cc ). table 5 shows dc electrical characteristics table 5. dc electrical characteristics characteristic symbol min max unit input high voltage, all inputs except clkin v ih 2.0 3.465 v input low voltage v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = v ddh i in ?10a hi-z (off state) leakage current, v in = v ddh i oz ?10 a signal low input current, v il = 0.8v i l ?1 a signal high input current, v ih = 2.0v i h ?1 a output high voltage, i oh = -2 ma except xfc, utopia mode, and open drain pins in utopia mode: i oh = -8.0 ma pa[0-31] pb[4-31] pc[0-31] pd[4-31] v oh 2.4 ? v in utopia mode: i ol = 8.0 ma pa[0-31] pb[4-31] pc[0-31] pd[4-31] v ol ?0.5v i ol = 7.0 ma br bg abb/irq2 ts a[0-31] tt[0-4] tbst tsize[0?3] aack artry dbg v ol ?0.4v
34 PC8265A powerquicc ii 5336a?hirel?08/03 dbb /irq3 d[0-63] dp(0)/rsrv /ext_br2 dp(1)/irq1 /ext_bg2 dp(2)/tlbisync /irq2 /ext_dbg2 dp(3)/irq3 /ext_br3 /ckstp_out dp(4)/irq4 /ext_bg3 /core_srest dp(5)/tben/irq5 /ext_dbg3 dp(6)/cse(0)/irq6 dp(7)/cse(1)/irq7 psdval ta tea gbl /irq1 ci /baddr29/irq2 wt /baddr30/irq3 l2_hit /irq4 cpu_bg /baddr31/irq5 cpu_dbg cpu_br irq0 /nmi_out irq7 /int_out /ape poreset hreset sreset rstconf qreq i ol = 5.3 ma cs [0-9] cs (10)/bctl1 cs (11)/ap(0) baddr[27?28] ale bctl0 pwe (0:7)/psddqm (0:7)/pbs (0:7) psda10/pgpl0 psdwe /pgpl1 poe /psdras /pgpl2 psdcas/pgpl3 pgta/pupmwait/pgpl4/ppbs psdamux/pgpl5 lwe [0?3]lsddqm [0?3]/lbs [0?3]/pci_cfg[0?3 (1) lsda10/lgpl0/pci_modckh0 (1) lsdwe/lgpl1/pci_modckh1 (1) v ol ?0.4v table 5. dc electrical characteristics (continued) characteristic symbol min max unit
35 PC8265A powerquicc ii 5336a?hirel?08/03 note: 1. the leakage current is measured for nominal v ddh and v dd or both v ddh and v dd must vary in the same direction; that is, v ddh and v dd either both vary in the positive direction (+5% and +0.1 v dc ) or both vary in the negative direction (-5% and -0.1 v dc ) loe /lsdras /lgpl2/pci_modckh2 (1) lsdcas/lgpl3/pci_modckh3 (1) lgta/lupmwait/lgpl4/lpbs lsdamux/lgpl5/pci_modck (1) lwr modck1/ap(1)/tc(0)/bnksel(0) modck2/ap(2)/tc(1)/bnksel(1) modck3/ap(3)/tc(2)/bnksel(2) i ol = 3.2 ma l_a14/par (1) l_a15/frame (1) /smi l_a16/trdy (1) l_a17/irdy (1) /ckstp_out l_a18/stop (1) l_a19/devsel (1) l_a20/idsel (1) l_a21/perr (1) l_a22/serr (1) l_a23/req0 (1) l_a24/req1 (1) /hsejsw (1) l_a25/gnt0 (1) l_a26/gnt1 (1) /hsled (1) l_a27/gnt2 (1) /hsenum (1) l_a28/rst (1) /core_sreset l_a29/inta (1) l_a30/req2 (1) l_a31 lcl_d(0-31)/ad(0-31) (1) lcl_dp(0-3)/c/be (0-3) (1) pa[0?31] pb[4?31] pc[0?31] pd[4?31] tdo table 5. dc electrical characteristics (continued) characteristic symbol min max unit
36 PC8265A powerquicc ii 5336a?hirel?08/03 thermal characteristics table 6 describes thermal characteristics. notes: 1. assumes a single layer board with no thermal vias 2. natural convection 3. assumes a four layer board 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package 5. thermal resistance between the die and th e case top surface as measured by the cold plate method (mil spec-883 method 1012.1) power considerations the average chip-junction temperature, t j , in c can be obtained from the following: t j = t a + (p d x ja ) (1) where t a = ambient temperature c ja = package thermal resistance, junction to ambient, c/w p d = p int + p i/o p int = i dd x v dd watts (chip internal power) p i/o = power dissipation on input and output pins (determined by user) for most applications p i/o < 0.3 x p int . if p i/o is neglected, an appr oximate relationship between p d and t j is as follows: p d = k/(t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d x (t a + 273 c) + ja x p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equa- tion (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equati ons (1) and (2) iteratively for any value of t a . table 6. thermal characteristics for the 480 tbga package characteristics symbol value unit air flow junction to ambient ja 13.07 (1) c/w nc (2) ja 9.55 (1) c/w 1 m/s ja 10.48 (3) c/w nc ja 7.78 (3) c/w 1 m/s junction to board (4) jb 6 c/w ? junction to case (5) jc 2 c/w ?
37 PC8265A powerquicc ii 5336a?hirel?08/03 layout practices each pin should be provided with a low-impedance path to the board?s power supply. each ground pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of lo gic on the chip. the power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to the chip and gro und should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as gnd planes. all output pins on the PC8265A have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize overdamped conditions and reflections caused by these fast output switching times. th is recommendation par- ticularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassi ng becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the gnd circuits. pull up all unused inputs or sig nals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. table 7 provides preliminary, estimated po wer dissipation for various configurations. note that suitable thermal management is required for conditions above p d = 3w (when the ambient temperature is 70 c or greater) to ensure the junction temperature does not exceed the maximum specified value. also note that the i/o powe r should be included when determining whether to use a heat sink. notes: 1. test temperature = room temperature (25 c) 2. p int = i dd x v dd watts (chip internal power) table 7. estimated power dissipation for various configurations (1) bus (mhz) cpm multiplier core cpu multiplier cpm (mhz) cpu (mhz) p int (w) (2) vddl 1.8 volts vddl 2.0 volts nominal maximum nominal maximum 66.66 2 3 133 200 1.2 2 1.8 2.3 66.66 2.5 3 166 200 1.3 2.1 1.9 2.3 66.66 3 4 200 266 ? ? 2.3 2.9 66.66 3 4.5 200 300 ? ? 2.4 3.1 83.33 2 3 166 250 ? ? 2.2 2.8 83.33 2 3 166 250 ? ? 2.2 2.8 83.33 2.5 3.5 208 291 ? ? 2.4 3.1
38 PC8265A powerquicc ii 5336a?hirel?08/03 ac electrical characteristics the following sections include illustrations and tables of clock diagrams, signals, and cpm outputs and inputs for the 66 mhz PC8265A device. note that ac timings are based on a 50-pf load. typical output buffer impedances are shown in table 8. note: 1. these are typical values at 65 c. the impedance may vary by 25% with process and temperature. table 9 lists cpm output characteristics. note: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timing s are measured at the pin. table 10 lists cpm input characteristics. note: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. note that although the specifications gen erally reference the rising edge of the cl ock, the following ac timing diagrams also apply when the falling ed ge is the active edge. table 8. output buffer impedances (1) output buffers typical impedance ( ?) 60x bus 40 local bus 40 memory controller 40 parallel i/o 46 pci 25 table 9. ac characteristics for cpm outputs (1) spec_num max/min characteristic max delay (ns) min delay (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp36a/sp37a fcc outputs ? internal clock (nmsi) 6 5.5 1 1 sp36b/sp37b fcc outputs ? external clock (nmsi) 14 12 2 1 sp38a/sp39a scc/smc/spi/i2c outputs ? internal clock (nmsi) 19 16 1 0.5 sp38b/sp39b ex_scc/smc/spi /i2c outputs ? external clock (nmsi) 19 16 2 1 sp42/sp43 timer/idma outputs 14 11 1 0.5 sp42a/sp43a pio outputs 14 11 0.5 0.5 table 10. ac characteristics for cpm inputs (1) spec_num characteristic setup (ns) hold (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp16a/sp17a fcc inputs ? internal clock (nmsi) 10 8 0 0 sp16b/sp17b fcc inputs ? external clock (nmsi) 3 2.5 3 2 sp20/sp21 tdm inputs/si 15 12 12 10 sp18a/sp19a scc/smc/spi/i 2c inputs ? internal clock (nmsi) 20 16 0 0 sp18b/sp19b scc/smc/spi/i2c inputs ? external clock (nmsi) 5454 sp22/sp23 pio/timer/idma inputs 10 8 3 3
39 PC8265A powerquicc ii 5336a?hirel?08/03 figure 4 shows the fcc external clock. figure 4. fcc external clock diagram figure 5 shows the fcc internal clock. figure 5. fcc internal clock diagram serial clkin fcc input signals fcc output signals when gfmr[tci] = 1 when gfmr[tci] = 0 sp16b sp17b sp36b/sp37b sp36b/sp37b fcc output signals brg_out fcc input signals fcc output signals when gfmr.tci = 1 when gfmr.tci = 0 sp16a sp17a sp36a/sp37a sp36a/sp37a fcc output signals
40 PC8265A powerquicc ii 5336a?hirel?08/03 figure 6 shows the scc/smc/spi/i 2 c external clock. figure 6. scc/smc/spi/i 2 c external clock diagram note: the clock edge is selectable on scc and spi. figure 7 shows the scc/smc/spi/i 2 c internal clock. figure 7. scc/smc/spi/i 2 c internal clock diagram note: the clock edge is selectable on scc and spi figure 8 shows tdm input and output signals. figure 8. tdm signals diagram there are four possible tdm timing conditions: 1. input sampled on the rising edge and output driven on the rising edge (shown) 2. input sampled on the rising edge a nd output driven on the falling edge 3. input sampled on the falling edge an d output driven on the falling edge 4. input sampled on the falling edge and output driven on the rising edge sp19b sp18b sp38b/sp39b serial clkin scc/smc/spi/i2c input signals (see note.) scc/smc/spi/i2c output signals (see note.) sp19a sp18a sp38a/sp39a brg_out scc/smc/spi/i2c output signals (see note.) scc/smc/spi/i2c input signals (see note.) sp20 sp40/sp41 serial clkin tdm input signals tdm output signals sp21
41 PC8265A powerquicc ii 5336a?hirel?08/03 figure 9 shows pio, timer, and dma signals. figure 9. pio, timer, and dma signal diagram table 11 lists siu input characteristics. note: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. table 11. ac characteristics for siu inputs (1) spec_num characteristic setup (ns) hold (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp11/sp10 aack /artry /ta /ts /tea /dbg /bg /br 6511 sp12/sp10 data bus in normal mode 5 4 1 1 sp13/sp10 data bus in ecc and parity modes 8 6 1 1 sp14/sp10 dp pins 7 6 1 1 sp15/sp10 all other pins 5 4 1 1 sp22 sp42/sp43 sp23 sp42a/sp43a pio output signals clkin pio/timer/idma input signals timer/idma output signals
42 PC8265A powerquicc ii 5336a?hirel?08/03 table 12 lists siu output characteristics. note: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timing s are measured at the pin. table 12. ac characteristics for siu outputs (1) spec_num max/min characteristic setup (ns) hold (ns) 66 mhz 83 mhz 66 mhz 83 mhz sp31/sp30 psdval /tea /ta 760.50.5 sp32/sp30 add/add_atr./ba ddr/ci/gbl/wt 8 6.5 0.5 0.5 sp33a/sp30 data bus 6.5 6.5 0.5 0.5 sp33b/sp30 dp 8 7 0.5 0.5 sp34/sp30 memory controller signals/ale 6 5 0.5 0.5 sp35/sp30 all other signals 6 5.5 0.5 0.5
43 PC8265A powerquicc ii 5336a?hirel?08/03 figure 10 shows the interaction of several bus signals. figure 10. bus signals note: activating data pipelining (setting br x [dr] in the memory controller) improves the ac timing. when data pipelining is ac ti- vated, sp12 can be used for data bus setup even when ecc or parity are used. also, sp33a can be used as the ac specification for dp signals. sp11 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp12 sp15 sp31 sp32 sp33a sp35 clkin aack/artry/ta/ts/tea/ dbg/bg/br input signals data bus normal mode input signal all other input signals psdval/tea/ta output signals add/add_atr/baddr/ci/ gbl/wt output signals data bus output signals all other output signals
44 PC8265A powerquicc ii 5336a?hirel?08/03 figure 11 shows signal behavior for all parity modes (including ecc, rmw parity, and standard parity). figure 11. parity mode diagram figure 12 shows signal behavior in memc mode. figure 12. memc mode diagram note: generally, all PC8265A bus and system output signals are driven from the rising edge of the input clock (clkin). memory controller signals, however, trigger on four points within a clkin cycle. each cycle is divided by four in ternal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge, and t3 at the fa lling edge, of clkin. however, the spacing of t2 and t4 depends on the pll clock ratio selected, as shown in table 13. sp13 sp33b/sp10 sp10 sp10 sp14 clkin data bus, ecc, and parity mode input signals dp mode input signal dp mode output signal table 13. tick spacing for memory controller signals pll clock ratio tick spacing (t1 occurs at the rising edge of clkin) t2 t3 t4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 clkin 1/2 clkin 3/4 clkin 1:2.5 3/10 clkin 1/2 clkin 8/10 clkin 1:3.5 4/14 clkin 1/2 clkin 11/14 clkin sp34/sp30 clkin v_clk memory controller signals
45 PC8265A powerquicc ii 5336a?hirel?08/03 figure 13 is a graphical representation of table 13 . figure 13. internal tick spacing for memory controller signals note: the upm machine outputs change on the internal tick determined by the memory con- troller programming; the ac specifications ar e relative to the inte rnal tick. note that sdram and gpcm machine outputs change on clkin?s rising edge. t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4 for 1:2, 1:3, 1:4, 1:5, 1:6 clkin for 1:2.5 clkin for 1:3.5 clkin
46 PC8265A powerquicc ii 5336a?hirel?08/03 clock configuration modes to configure the main pll multiplication factor and the core, the cpm, and 60x bus fre- quencies, the modck[1:3] pins are sampled while hreset is asserted. table 14 shows the eight basic configuration modes. another 49 modes are available by using the configuration pin (rstconf ) and driving four pins on the data bus. local bus mode table 14 describes default clock modes for the PC8265A. table 15 describes all possible clock configurations when using the hard reset configuration sequence. note that the clock configuration changes only after por is asserted. note also that basic modes are shown in boldface type. table 14. clock default modes modck[1?3] input clock frequency (mh)z cpm multiplication factor cpm frequency (mhz) core multiplication factor core frequency (mhz) 000 33 3 100 4 133 001 33 3 100 5 166 010 33 4 133 4 133 011 33 4 133 5 166 100 66 2 133 2.5 166 101 66 2 133 3 200 110 66 2.5 166 2.5 166 111 66 2.5 166 3 200 table 15. clock configuration modes (1) modck_h?modck[1?3] input clock frequency (2)(3) (mhz) cpm multiplication factor (2) cpm frequency (2) (mhz) core multiplication factor (2) core frequency (2) (mhz) 0001_000 33 2 66 4 133 0001_001 33 2 66 5 166 0001_010 33 2 66 6 200 0001_011 33 2 66 7 233 0001_100 33 2 66 8 266 0001_101 33 3 100 4 133 0001_110 33 3 100 5 166 0001_111 33 3 100 6 200 0010_000 33 3 100 7 233 0010_001 33 3 100 8 266 0010_010 33 4 133 4 133 0010_011 33 4 133 5 166
47 PC8265A powerquicc ii 5336a?hirel?08/03 0010_100 33 4 133 6 200 0010_101 33 4 133 7 233 0010_110 33 4 133 8 266 0010_111 33 5 166 4 133 0011_000 33 5 166 5 166 0011_001 33 5 166 6 200 0011_010 33 5 166 7 233 0011_011 33 5 166 8 266 0011_100 33 6 200 4 133 0011_101 33 6 200 5 166 0011_110 33 6 200 6 200 0011_111 33 6 200 7 233 0100_000 33 6 200 8 266 0100_001 reserved 0100_010 0100_011 0100_100 0100_101 0100_110 0100_111 reserved 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 2 133 2 133 0101_110 66 2 133 2.5 166 0101_111 66 2 133 3 200 0110_000 66 2 133 3.5 233 0110_001 66 2 133 4 266 0110_010 66 2 133 4.5 300 table 15. clock configuration modes (1) (continued) modck_h?modck[1?3] input clock frequency (2)(3) (mhz) cpm multiplication factor (2) cpm frequency (2) (mhz) core multiplication factor (2) core frequency (2) (mhz)
48 PC8265A powerquicc ii 5336a?hirel?08/03 notes: 1. because of speed dependencies, not all of the possible configurations in table 15 are applicable. 2. the user should choose the input clock frequency and the mult iplication factors such that th e frequency of the cpu is equal to or greater than150 mhz and the cpm ranges between 66 ? 233 mhz. 3. input clock frequency is given only for the purpose of refe rence. modck_h?modck_l should be set so that the resulting configuration does not exceed the freq uency rating of the user?s part. example. if a part is rated at 266 mhz cpu, 200 mhz cpm, and 66 mhz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 66 mhz input clock and modck_h?modck_l[0111?101] ( with a core multiplication factor of 4 and a cpm multiplication factor of 3). the resulting configuration equals the part?s maximum possible frequencies of 266 mhz cpu, 200 mhz cpm, and 66 mhz bus. 2. 50 mhz input clock and modck_h?modck_l[0111?101] to achieve a configuration of 200 mhz cpu, 150 mhz cpm, and 50 mhz bus. 3. 40 mhz input clock and modck_h?modck_l[0010?011] to achieve a configuration of 200 mhz cpu, 160 mhz cpm, and 40 mhz bus. note that with each example, any one of several values for modck_h?modck_l could possibly be used as long as the resulting configuration does not exceed the part?s rating. 0110_011 66 2.5 166 2 133 0110_100 66 2.5 166 2.5 166 0110_101 66 2.5 166 3 200 0110_110 66 2.5 166 3.5 233 0110_111 66 2.5 166 4 266 0111_000 66 2.5 166 4.5 300 0111_001 66 3 200 2 133 0111_010 66 3 200 2.5 166 0111_011 66 3 200 3 200 0111_100 66 3 200 3.5 233 0111_101 66 3 200 4 266 0111_110 66 3 200 4.5 300 0111_111 66 3.5 233 2 133 1000_000 66 3.5 233 2.5 166 1000_001 66 3.5 233 3 200 1000_010 66 3.5 233 3.5 233 1000_011 66 3.5 233 4 266 1000_100 66 3.5 233 4.5 300 table 15. clock configuration modes (1) (continued) modck_h?modck[1?3] input clock frequency (2)(3) (mhz) cpm multiplication factor (2) cpm frequency (2) (mhz) core multiplication factor (2) core frequency (2) (mhz)
49 PC8265A powerquicc ii 5336a?hirel?08/03 pci mode this section pertains to the PC8265A and the pc8266a only. in pci mode only, modck_hi[0:3] and pci_ modck come from the following external pins: ? pci_modck = lgpl5 ? modck_hi[0:3] = {lgpl0,lgpl1,lgpl2,lgpl3} note: the minimum tval = 2 when pci_modck = 1 and minimum tval = 1 when pci_modck = 0; therefore, board designers should use clock configurations that fit this condition to achieve pci-compliant ac timing. notes: 1. assumes modck_hi = 0000. 2. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) table 17 describes all possible clock confi gurations when using the PC8265A or the pc8266a?s internal pci bridge in host mode. table 16. clock default configurations in pci host mode (modck_hi = 0000) modck[1? 3] (1) input clock frequency cpm multiplication cpm frequency core multiplication core frequency pci division factor (2) pci frequency (2) 000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 001 66 mhz 2 133 mhz 3 200 mhz 2/4 66/33 mhz 010 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 011 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 100 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 101 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 110 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 111 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz table 17. clock configuration modes in pci host mode modck_h ? modck[1?3] input clock frequency (1) (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) pci frequency (2) 0001_000 33 mhz 3 100 mhz 5 166 mhz 3/6 33/16 mhz 0001_001 33 mhz 3 100 mhz 6 200 mhz 3/6 33/16 mhz 0001_010 33 mhz 3 100 mhz 7 233 mhz 3/6 33/16 mhz 0001_011 33 mhz 3 100 mhz 8 266 mhz 3/6 33/16 mhz 0010_000 33 mhz 4 133 mhz 5 166 mhz 4/8 33/16 mhz 0010_001 33 mhz 4 133 mhz 6 200 mhz 4/8 33/16 mhz 0010_010 33 mhz 4 133 mhz 7 233 mhz 4/8 33/16 mhz 0010_011 33 mhz 4 133 mhz 8 266 mhz 4/8 33/16 mhz 0011_000 (3) 33 mhz 5 166 mhz 5 166 mhz 5 33 mhz 0011_001 (3) 33 mhz 5 166 mhz 6 200 mhz 5 33 mhz
50 PC8265A powerquicc ii 5336a?hirel?08/03 modck_h ? modck[1?3] input clock frequency (1) (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) pci frequency (2) 0011_010 (3) 33 mhz 5 166 mhz 7 233 mhz 5 33 mhz 0011_011 (3) 33 mhz 5 166 mhz 8 266 mhz 5 33 mhz 0100_000 3 33 mhz 6 200 mhz 5 166 mhz 6 33 mhz 0100_001 3 33 mhz 6 200 mhz 6 200 mhz 6 33 mhz 0100_010 3 33 mhz 6 200 mhz 7 233 mhz 6 33 mhz 0100_011 3 33 mhz 6 200 mhz 8 266 mhz 6 33 mhz 0101_000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 0101_001 66 mhz 2 133 mhz 3 200 mhz 2/4 66/33 mhz 0101_010 66 mhz 2 133 mhz 3.5 233 mhz 2/4 66/33 mhz 0101_011 66 mhz 2 133 mhz 4 266 mhz 2/4 66/33 mhz 0101_100 66 mhz 2 133 mhz 4.5 300 mhz 2/4 66/33 mhz 0110_000 66 mhz 2.5 166 mhz 2.5 166 mhz 3/6 55/28 mhz 0110_001 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 0110_010 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 0110_011 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 0110_100 66 mhz 2.5 166 mhz 4.5 300 mhz 3/6 55/28 mhz 0111_000 66 mhz 3 200 mhz 2.5 166 mhz 3/6 66/33 mhz 0111_001 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 0111_010 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 0111_011 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz 0111_100 66 mhz 3 200 mhz 4.5 300 mhz 3/6 66/33 mhz 1000_000 66 mhz 3 200 mhz 2.5 166 mhz 4/8 50/25 mhz 1000_001 66 mhz 3 200 mhz 3 200 mhz 4/8 50/25 mhz 1000_010 66 mhz 3 200 mhz 3.5 233 mhz 4/8 50/25 mhz 1000_011 66 mhz 3 200 mhz 4 266 mhz 4/8 50/25 mhz 1000_100 66 mhz 3 200 mhz 4.5 300 mhz 4/8 50/25 mhz 1001_000 66 mhz 3.5 233 mhz 2.5 166 mhz 4/8 58/29 mhz 1001_001 66 mhz 3.5 233 mhz 3 200 mhz 4/8 58/29 mhz 1001_010 66 mhz 3.5 233 mhz 3.5 233 mhz 4/8 58/29 mhz table 17. clock configuration modes in pci host mode (continued)
51 PC8265A powerquicc ii 5336a?hirel?08/03 notes: 1. input clock frequency is given only for the purpose of re ference. user should set modck_h ?modck_l so that the result- ing configuration does not exceed th e frequency rating of the user?s part. example. if a part is rated at 266 mhz cpu, 200 mhz cpm, and 66 mhz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 66 mhz input clock, modck_h?modck_l[0111?011] (with a core multiplication factor of 4 and a cpm multi- plication factor of 3), and pci_modck = 0 (see note 2 below). the resulting configuration equals the part?s maximum possible frequencies of 266 mhz cpu, 200 mh z cpm, 66 mhz 60x bus, and a pci frequency of 66 mhz. 2. 50 mhz input clock, modck_h?modck_l[0111?011], and pci_modck = 0 (see note 2below) to achieve a configuration of 200 mhz cpu, 150 mhz cpm, 50 mhz 60x bus, and a pci frequency of 50 mhz. 3. 40 mhz input clock, modck_h?mo dck_l[0010?000], and pci_modck = 0 (see note 2 below) to achieve a configuration of 200 mhz cpu, 160 mhz cpm, 40 mhz 60x bus, and a pci frequency of 40 mhz. note that with each of the examples, any one of severa l values for modck_h?modck_l could possibly be used as long as the resulting configuration does not exceed the part?s rating. 2. the frequency depends on the value of pci_modck. if pci_mo dck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.). 3. in this mode, pci_modck must be ?0? modck_h ? modck[1?3] input clock frequency (1) (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) pci frequency (2) 1001_011 66 mhz 3.5 233 mhz 4 266 mhz 4/8 58/29 mhz 1001_100 66 mhz 3.5 233 mhz 4.5 300 mhz 4/8 58/29 mhz 1010_000 100 mhz 2 200 mhz 2 200 mhz 3/6 66/33 mhz 1010_001 100 mhz 2 200 mhz 2.5 250 mhz 3/6 66/33 mhz 1010_010 100 mhz 2 200 mhz 3 300 mhz 3/6 66/33 mhz 1010_011 100 mhz 2 200 mhz 3.5 350 mhz 3/6 66/33 mhz 1010_100 100 mhz 2 200 mhz 4 400 mhz 3/6 66/33 mhz 1011_000 100 mhz 2.5 250 mhz 2 200 mhz 4/8 62/31 mhz 1011_001 100 mhz 2.5 250 mhz 2.5 250 mhz 4/8 62/31mhz 1011_010 100 mhz 2.5 250 mhz 3 300 mhz 4/8 62/31 mhz 1011_011 100 mhz 2.5 250 mhz 3.5 350 mhz 4/8 62/31 mhz 1011_100 100 mhz 2.5 250 mhz 4 400 mhz 4/8 62/31 mhz table 17. clock configuration modes in pci host mode (continued)
52 PC8265A powerquicc ii 5336a?hirel?08/03 . notes: 1. the user should verify that all buses and f unctions run frequencies that are within the supported ranges 2. assumes modck_hi = 0000 3. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2 4. core frequency = (60x bus frequency)(core multiplication factor) 5. bus frequency = cpm frequency/bus division factor table 19 describes all possible clock configurations when using the PC8265A or the pc8266a?s internal pci bridge in agent mode. table 18. clock default configurations in pci agent mode (modck_hi = 0000) (1) modck[1?3] (2) input clock frequency (pci) (3) cpm multiplication factor (3) cpm frequency core multiplication factor core (4) frequency bus division factor 60x bus (5) frequency 000 66/33 mhz 2/4 133 mhz 2.5 166 mhz 2 66 mhz 001 66/33 mhz 2/4 133 mhz 3 200 mhz 2 66 mhz 010 66/33 mhz 3/6 200 mhz 3 200 mhz 3 66 mhz 011 66/33 mhz 3/6 200 mhz 4 266 mhz 3 66 mhz 100 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 101 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 110 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 111 66/33 mhz 4/8 266 mhz 3 300 mhz 2.5 100 mhz table 19. clock configuration modes in pci agent mode (1) modck_h ? modck[1?3] input clock frequency (pci) (2)(3) cpm multiplication factor (2) cpm frequency core multiplication factor core (4) frequency bus division factor 60x bus (5) frequency 0001_001 66/33 mhz 2/4 133 mhz 5 166 mhz 4 33 mhz 0001_010 66/33 mhz 2/4 133 mhz 6 200 mhz 4 33 mhz 0001_011 66/33 mhz 2/4 133 mhz 7 233 mhz 4 33 mhz 0001_100 66/33 mhz 2/4 133 mhz 8 266 mhz 4 33 mhz 0010_001 50/25 mhz 3/6 150 mhz 3 180 mhz 2.5 60 mhz 0010_010 50/25 mhz 3/6 150 mhz 3.5 210 mhz 2.5 60 mhz 0010_011 50/25 mhz 3/6 150 mhz 4 240 mhz 2.5 60 mhz 0010_100 50/25 mhz 3/6 150 mhz 4.5 270 mhz 2.5 60 mhz 0011_000 66/33 mhz 2/4 133 mhz 2.5 110mhz 3 44 mhz 0011_001 66/33 mhz 2/4 133 mhz 3 132 mhz 3 44 mhz 0011_010 66/33 mhz 2/4 133 mhz 3.5 154 mhz 3 44 mhz 0011_011 66/33 mhz 2/4 133 mhz 4 176 mhz 3 44 mhz 0011_100 66/33 mhz 2/4 133 mhz 4.5 198 mhz 3 44 mhz
53 PC8265A powerquicc ii 5336a?hirel?08/03 modck_h ? modck[1?3] input clock frequency (pci) (2)(3) cpm multiplication factor (2) cpm frequency core multiplication factor core frequency ( 4) bus division factor 60x bus frequency ( 5) 0100_000 66/33 mhz 3/6 200 mhz 2.5 166 mhz 3 66 mhz 0100_001 66/33 mhz 3/6 200 mhz 3 200 mhz 3 66 mhz 0100_010 66/33 mhz 3/6 200 mhz 3.5 233 mhz 3 66 mhz 0100_011 66/33 mhz 3/6 200 mhz 4 266 mhz 3 66 mhz 0100_100 66/33 mhz 3/6 200 mhz 4.5 300 mhz 3 66 mhz 0101_000 6 33 mhz 5 166 mhz 2.5 166 mhz 2.5 66 mhz 0101_001 6 33 mhz 5 166 mhz 3 200 mhz 2.5 66 mhz 0101_010 6 33 mhz 5 166 mhz 3.5 233 mhz 2.5 66 mhz 0101_011 6 33 mhz 5 166 mhz 4 266 mhz 2.5 66 mhz 0101_100 6 33 mhz 5 166 mhz 4.5 300 mhz 2.5 66 mhz 0110_000 50/25 mhz 4/8 200 mhz 2.5 166 mhz 3 66 mhz 0110_001 50/25 mhz 4/8 200 mhz 3 200 mhz 3 66 mhz 0110_010 50/25 mhz 4/8 200 mhz 3.5 233 mhz 3 66 mhz 0110_011 50/25 mhz 4/8 200 mhz 4 266 mhz 3 66 mhz 0110_100 50/25 mhz 4/8 200 mhz 4.5 300 mhz 3 66 mhz 0111_000 66/33 mhz 3/6 200 mhz 2 200 mhz 2 100 mhz 0111_001 66/33 mhz 3/6 200 mhz 2.5 250 mhz 2 100 mhz 0111_010 66/33 mhz 3/6 200 mhz 3 300 mhz 2 100 mhz 0111_011 66/33 mhz 3/6 200 mhz 3.5 350 mhz 2 100 mhz 1000_000 66/33 mhz 3/6 200 mhz 2 160 mhz 2.5 80 mhz 1000_001 66/33 mhz 3/6 200 mhz 2.5 200 mhz 2.5 80 mhz 1000_010 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 1000_011 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 1000_100 66/33 mhz 3/6 200 mhz 4 320 mhz 2.5 80 mhz 1000_101 66/33 mhz 3/6 200 mhz 4.5 360 mhz 2.5 80 mhz 1001_000 66/33 mhz 4/8 266 mhz 2.5 166 mhz 4 66 mhz 1001_001 66/33 mhz 4/8 266 mhz 3 200 mhz 4 66 mhz 1001_010 66/33 mhz 4/8 266 mhz 3.5 233 mhz 4 66 mhz 1001_011 66/33 mhz 4/8 266 mhz 4 266 mhz 4 66 mhz 1001_100 66/33 mhz 4/8 266 mhz 4.5 300 mhz 4 66 mhz table 19. clock configuration modes in pci agent mode (1) (continued)
54 PC8265A powerquicc ii 5336a?hirel?08/03 notes: 1. the user should verify that all buses and func tions run frequencies that are within the supported ranges. 2. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. 3. input clock frequency is given only for the purpose of refe rence. modck_h?modck_l should be set so that the resulting configuration does not exceed the freq uency rating of the user?s part. example. if a part is rated at 266 mhz cpu, 200 mhz cpm, and 66 mhz bus, any of the following are possible (note that the three input clock frequencies are only three of many possible input clock frequencies): 1. 50 mhz input clock, modck_h?modck_l[0110?011] (with a core multiplicat ion factor of 4, a cpm multiplica- tion factor of 4, and a bus division factor of 3), an d pci_modck = 0 (see note 2 above). the pci frequency is 50 mhz and the resulting configuration equals the part?s maximum possible fr equencies of 266 mhz cpu, 200 mhz cpm, and 66 mhz 60x bus. 2. 66 mhz input clock, modck_h?modck_l[0100?001], a nd pci_modck = 1 (see note 2 above) to achieve a pci frequency of 33 mhz and a configuration of 200mhz cpu, 200 mhz cpm, and 66 mhz 60x bus. 3. 40 mhz input clock, modck_h?modck_l[1001?011], a nd pci_modck = 0 (see note 2 above) to achieve a pci frequency of 40 mhz and a configuration of 160 mhz cpu, 160 mhz cpm, and 40 mhz 60x bus. note that with each of the examples, any one of se veral values for modck_h?modck_l could possibly be used as long as the resulting configuration does not exceed the part?s rating. 4. core frequency = (60x bus frequency) (core multiplication factor) 5. bus frequency = cpm frequency/bus division factor 6. in this mode, pci_modck must be ?1?. modck_h ? modck[1?3] input clock frequency (pci) (2)(3) cpm multiplication factor (2) cpm frequency core multiplication factor core frequency ( 4) bus division factor 60x bus frequency ( 5) 1010_000 66/33 mhz 4/8 266 mhz 2.5 222 mhz 3 88 mhz 1010_001 66/33 mhz 4/8 266 mhz 3 266 mhz 3 88 mhz 1010_010 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 1010_011 66/33 mhz 4/8 266 mhz 4 350 mhz 3 88 mhz 1010_100 66/33 mhz 4/8 266 mhz 4.5 400 mhz 3 88 mhz 1011_000 66/33 mhz 4/8 266 mhz 2 212mhz 2.5 106 mhz 1011_001 66/33 mhz 4/8 266 mhz 2.5 265 mhz 2.5 106 mhz 1011_010 66/33 mhz 4/8 266 mhz 3 318 mhz 2.5 106 mhz 1011_011 66/33 mhz 4/8 266 mhz 3.5 371 mhz 2.5 106 mhz 1011_100 66/33 mhz 4/8 266 mhz 4 424 mhz 2.5 106 mhz table 19. clock configuration modes in pci agent mode (1) (continued)
55 PC8265A powerquicc ii 5336a?hirel?08/03 package description the following sections provide the package parameters and mechanical dimensions for the PC8265A. package parameters package parameters are provided in table 20. the package type is a 37.5 x 37.5 mm, 480-lead tbga. table 20. package parameters parameter value package outline 37.5 x 37.5 mm interconnects 480 (29 x 29 ball array) pitch 1.27 mm nominal unmounted package height 1.55 mm
56 PC8265A powerquicc ii 5336a?hirel?08/03 status limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent dam- age to the device. these are stress ratings on ly and operation of the device at these or at any other conditions above those given in the characteri stics sections of the specifi- cation is not implied. exposure to limiting values for exte nded periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. life support applications these products are not designed for use in lif e support appliances, devices, or systems where malfunction of these pr oducts can reasonably be expect ed to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indem nify atmel for any damages resulting from such improper use or sale. table 21. datasheet status datasheet status validity objective specification this datasheet co ntains target and goal specification for discussion with customer and application validation. valid before design phase target specification this datasheet contai ns target or goal specifications for product development. v alid during the design phase preliminary specification site this datasheet contains pr eliminary data. additional data may be published later. this could include simulation results. valid before the characterization phase preliminary specification site this datasheet also contains characteriza tion results. valid before the industrialization phase. product specification this datasheet contains final product specifications. valid for production purposes
57 PC8265A powerquicc ii 5336a?hirel?08/03 mechanical dimensions figure 14 provides the mechanical dimensi ons and bottom surface nomenclature of the 480 tbga package. figure 14. mechanical dimensions and bottom surface nomenclature dim millimeters min max a 1.45 1.65 a1 0.60 0.70 a2 0.85 0.95 a3 0.25 _ b 0.65 0.85 d 37.50 bsc d1 35.56 ref e 1.27 bsc e 37.50 bsc e1 35.56 ref notes: 1. dimensions and tolerancing per asme y14.5m-1994 2. dimensions in millimeters 3. dimension b is measured at the maximum solder ball diameter, parallel to primary data a 4. primary data a and the seating plane are defined by the spherical crowns of the solder balls d b e c a a top view a1 bottom view aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 12345 67 891011121314151617181920212223242526272829 3 480x b abc a 3 15 m m (e1) 28x e 28x e (d1) seating plane a3 4x 0.2 a1 a a2 0.15 a 480x 0.15 a
58 PC8265A powerquicc ii 5336a?hirel?08/03 ordering information prefix (1) temperature range: tj screening level (2) package pc 8265a m tp mhb m: -55, +125c v: -40, +110c u tp: tbga cpu/cpm/bus speed (mhz) m = 266 mhz h = 166 mhz b = 66 mhz (1) atmel (2) u: upscreening (x) type prototype b revision level for availability of the different versions, contact your sales office.
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