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| 1. general description the PCA9646 is a monolithic cmos integrated circuit for 2-wire bus buffering and switching in applications including i 2 c-bus, smbus, pmbus, and other systems based on similar principles. each of the four outputs may be independently enabled in any combination as determined by the contents of the programmable control regi ster. each i/o is impedance isolated from all others, thus allowing a total of five bran ches of 2-wire bus with the maximum specified load (e.g., 5 ? 400 pf for fm+ i 2 c-bus at 1 mhz, or 5 ? 4 nf at lower frequencies) ( ref. 1 ). more than one PCA9646 may be used in series, providing a substantial fan-out capability. as per the pca9525 and pca9605 simple bus buffers, the PCA9646 includes a unidirectional buffer for the clock signal, and a bidirectional buffer for the data signal. the direction of the clock signal may also be set by the contents of the programmable control register. clock stretching and timing must alwa ys be under control of the master device. the PCA9646 has excellent application to 2-wire bus address expansion and increasing of maximum load capacitance. very large led displays are a perfect example. 2. features and benefits ? drop-in pin compatible with pca9546a, etc. ? each i/o is impedance isolated from all others allowing maximum capacitance on all branches ? 30 ma static sink capability on all ports ? works with i 2 c-bus (standard-mode, fast-mode, and fast-mode plus (fm+)), smbus (standard and high power mode), and pmbus ? fast switching times allow op eration in excess of 1 mhz ? allows driving of large loads (e.g., 5 ? 4nf) ? hysteresis on i/o increases noise immunity ? operating voltages from 2.7 v to 5.5 v ? uncomplicated characteristics suitable for quick implementation in most common 2-wire bus applications 3. applications ? large arrays of i 2 c-bus components, e.g., led displays ? power management systems ? game consoles, computers, raid systems PCA9646 buffered 4-channel 2-wire bus switch rev. 1 ? 1 march 2011 product data sheet
PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 2 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 4. ordering information 5. block diagram table 1. ordering information type number topside mark package name description version PCA9646d PCA9646 so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 PCA9646pw PCA9646 tssop16 plast ic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 fig 1. simplified block diagram of PCA9646 r4 002aaf367 i 2 c-bus control 5 7 10 12 4 6 9 11 sc0 sc1 sc2 sc3 sd0 sd1 sd2 sd3 r3 r5 r6 r7 r8 r9 r10 v dd 16 filter 1 a0 2 a1 13 a2 14 15 3 scl sda reset r2 r1 2.7 v to 5.5 v PCA9646 v ss 8 PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 3 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for so16 fig 3. pin configuration for tssop16 PCA9646d a0 v dd a1 sda reset scl sd0 a2 sc0 sc3 sd1 sd3 sc1 sc2 v ss sd2 002aaf364 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 PCA9646pw 002aaf366 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 a0 v dd a1 sda reset scl sd0 a2 sc0 sc3 sd1 sd3 sc1 sc2 v ss sd2 table 2. pin description symbol pin description a0 1 address input 0 a1 2 address input 1 reset 3 active low reset input sd0 4 serial data 0 sc0 5 serial clock 0 sd1 6 serial data 1 sc1 7 serial clock 1 v ss 8 negative supply (ground) sd2 9 serial data 2 sc2 10 serial clock 2 sd3 11 serial data 3 sc3 12 serial clock 3 a2 13 address input 2 scl 14 serial clock line (normally input) sda 15 serial data line v dd 16 positive supply PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 4 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 7. functional description refer to figure 1 ? simplified block diagram of PCA9646 ? . 7.1 v dd , v ss ? dc supply pins the power supply voltage for the PCA9646 may be any voltage in the range 2.7 v to 5.5 v. the ic supply must be common with the supply for the bus. hysteresis on the ports are a percentage of the ic?s power supply, hence noise margin considerations should be taken into account when selecting an operating voltage. 7.2 scl ? clock signal input the clock signal buffer is unidirectional, with this pin acting as the default input. however, the clock signal direction may be reversed by setting the msb of the control register high. in normal i 2 c-bus operations the master device generates a unidirectional clock signal to the slave. for lowest cost the pc a9646 combines unidirectional buffering of the clock signal with a bidirectional buffer for the data signal. clock stretching is therefore not supported and slave devices that may requir e clock stretching must be accommodated by the master adopting an appropriate clocking when communicating with them. the buffer includes hysteresis to ensure cl ean switching signals are output, especially with slow rise times on high capacitively loaded buses. 7.3 sc0, sc1, sc2, sc 3 ? clock signal outputs the clock signal from scl is buffered through four independent buffers, and the signal is presented at the four sc0 to sc3 ports. port s are open-drain type and require external pull-up resistors. when the msb of the control register is se t high, the port direction is reversed. the anded result of the selected sc0 to sc3 lines is then used to drive the open-drain output of the scl pin. 7.4 sda, sd0, sd1, sd2, sd3 ? data signal inputs/outputs the data signal buffers are bidirectional. the port (sda, or any one of sd0 to sd3) which first falls low, will decide the direction of this buffer and ?lock out? signals coming from the opposite side. as the ?input? signal continues to fall, it will then drive the op en-drain of the ?output? side low. again, hyster esis is applied to the buffer to minimize the effects of noise. ports are open-drain type and require external pull-up resistors. at some points during the communication, the data direction will reverse?for example, when the slave transmits an acknowledge (ack ) or responds with its register contents. during these times, the controlling ?in put? side will have to rise to v unlock before it releases the ?lock?, which then allows the ?output? side to gain control, and pull (what was) the ?input? side low again. this will cause a ?pulse? on the ?input? side, whic h can be quite long duration in high capacitance buses. however, this pulse will not inte rfere with the actual data transmission, as it shou ld not occur during times of clock line transition (during normal i 2 c-bus and smbus protocols), and thus data signal set-up time requirements are still met. PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 5 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 7.5 reset ? reset ic to default state the active low reset input is used to disable the buffer, and reset it to its default state. the ic should only be disabled when the bus is idle to avoid truncation of commands which may confuse other devices on the bus. the reset signal will clear the contents of the co ntrol register, which has the effect of disabling all output lines sc[0:3] and sd[0:3]. it is the nature of the i 2 c-bus protocol that devices may become ?stuck?. to help in the cl earing of this condition, the PCA9646 can be reset, and each port brought on-line successively to find the component holding the bus low. 7.6 power-on reset (por) during power-on, the PCA9646 is internally held in the rese t condition for a maximum of t rst = 500 ns. the default condition after reset is for the control register to be erased (all zeros), resulting in all output channels being disabled. 7.7 a0, a1, a2 ? address lines the slave address of the PCA9646 is shown in figure 4 . the address pins (a2, a1, a0) must be driven to a high or low level?they are not internally pulled to a default state. the read/write bit must be set low to enable a write to the co ntrol register, or high to read from the control register. 7.8 control register the control register of the PCA9646 is shown in figure 5 . each of the four output channels (scn/sdn pairs) can be enabled in dependently, and the di rection of the clock signal can be reversed. fig 4. slave address 002aaf368 1 1 1 0 a2 a1 a0 r/w fixed externally selectable read = 1 write = 0 fig 5. control register 002aaf369 b7 x x x b3 b2 b1 b0 output channel enable bits msb lsb scl direction 0: scl sc0 to sc3 1: sc0 to sc3 scl sc0/sd0 enable sc1/sd1 enable sc2/sd2 enable sc3/sd3 enable PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 6 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch a low or ?zero? bit (b[3:0]) indicates that the respective channel (sc[3:0], sd[3:0]) is disabled. the default reset condition of the re gister is all zeros, all channels disabled, forward direction. a high or ?one? bit indicates the respective channel is enabled. example: b3 = 1, b2 = 0, b1 = 1, b0 = 0 means channel 3 (sc3/sd3) and channel 1 (sc1/sd1) are enabled, and channel 2 (sc2/sd2) and channel 0 (sc0/sd0) are disabled. as each channel is individually buffered, the loads on each are isolated, and therefore there is no special requirement to keep the sum of the collective capacitances below the maximum bus capacitance. instead, each line may have up to the maximum bus capacitance and be enabled or disabled with out affecting the performance of the other channels. the most significant bit (msb) b7 is used to set the direction of the scl (clock) signal. the default state is low (zero). in this state, the scl port will act as the input, and the ic will supply a buffered signal to any of the four out put channels (sc0 to sc3) which are enabled. when b7 is set high (one), the cl ock signal direction is reversed. the ports sc0 to sc3 act as inputs, the anded combinatio n of the selected signals is buffered and output on the scl pin. the PCA9646 is always addressable from the scl/sda side, regardless of the state of b7. any device which can communicate data to th e scl/sda pins, either by being directly attached to those pins or by transmitting through the PCA9646 (when b7 = 1), may address the device and change the control regist er?s contents. the control register is only updated upon receipt of the stop condition. 8. bus transaction a typical i 2 c-bus write transaction to the PCA9646 is shown in figure 6 . a typical read transaction is shown in figure 7 . fig 6. PCA9646 write transaction to control register fig 7. PCA9646 read transaction from control register 002aaf370 s 1 1 1 0 a2 a1 a0 slave address 0 a b7 x x x b3 b2 b1 b0 a p control register start condition r/w acknowledge from slave acknowledge from slave stop condition 002aaf371 s 1 1 1 0 a2 a1 a0 slave address 1 a b7 0 0 0 b3 b2 b1 b0 na p control register start condition r/w acknowledge from slave not acknowledge from master stop condition PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 7 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 9. limiting values [1] voltages are specified with respect to pin 8 (v ss ). 10. characteristics table 3. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage [1] ? 0.3 +7 v v i/o voltage on an input/output pin pins sdx, scx [1] v ss ? 0.5 +7 v v i input voltage reset pin [1] v ss ? 0.5 v dd +0.5 v address pins a2, a1, a0 [1] v ss ? 0.5 v dd +0.5 v i i input current pins other than scx/sdx - 20 ma all scx and sdx - 40 ma i ss ground supply current - 280 ma p tot total power dissipation - 300 mw t stg storage temperature ? 55 +125 ?c t amb ambient temperature operating ? 40 +85 ?c table 4. characteristics t amb = ? 40 ? c to +85 ? c; voltages are specified with respect to ground (v ss ); v dd = 5.5 v unless otherwise specified. symbol parameter conditions min typ max unit power supply v dd supply voltage operating 2.7 - 5.5 v i dd supply current quiescent; v i (reset pin)=0v--1 ? a i 2 c-bus ports (scl, sda, sc[3:0], sd[3:0]) v i2c-bus i 2 c-bus voltage sdx, scx - - 5.5 v v il low-level input voltage v dd =2.7v [1] --0.4v v dd =5.5v [1] --0.5v v ih high-level input voltage v dd =2.7v [1] 1.2 - - v v dd =5.5v [1] 2.0 - - v v i(hys) hysteresis of input voltage v dd =2.7v [1] 80 - - mv v dd =5.5v [1] 200 - - mv i li input leakage current pin at v dd or v ss ? 1- +1 ? a i o(sink) output sink current low-level; v sxx input < v il 30 - - ma v ol low-level output voltage i ol =30ma; v dd = 2.7 v - 260 450 mv i ol =30ma; v dd = 5.5 v - 140 275 mv pins sda, sd0, sd1, sd2, sd3 v lock direction lock voltage v dd =2.7v [1] --1.3v v dd =5.5v [1] --3.0v v unlock direction unlock voltage v dd =2.7v [1] 2.0 - - v v dd =5.5v [1] 4.8 - - v PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 8 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch [1] supply voltage dependent; refer to graphs ( figure 9 through figure 12 ) for typical trend. [2] guaranteed by design, not subject to test. reset v ih high-level input voltage v dd = 2.7 v 2.0 - - v v dd = 5.5 v 4.8 - - v v il low-level input voltage v dd = 2.7 v - - 650 mv v dd = 5.5 v - - 900 mv v hys hysteresis voltage v dd =2.7v 100 - - mv v dd =5.5v 200 - - mv i li input leakage current pin at v dd or v ss ? 1- +1 ? a t w(rst)l low-level reset time v i PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 9 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch t amb =25 ? c fig 9. typical input levels versus supply voltage fig 10. typical v ih ? v il hysteresis versus supply voltage t amb =25 ? ci ol =30ma fig 11. typical low-level output voltage versus pull-up resistance fig 12. typical low-level output voltage versus ambient temperature 2 3 1 4 5 v i (v) 0 v dd (v) 26 5 34 002aaf333 v lock v ih v il 400 600 200 800 1000 v i(hys) (v) 0 v dd (v) 26 5 34 002aaf334 t amb = +85 c +25 c ?40 c 100 150 50 200 250 v ol (mv) 0 r pu () 0 1000 800 400 600 200 002aaf372 v dd = 5.5 v 2.7 v 100 300 400 v ol (mv) 0 t amb (c) ?50 150 100 050 002aaf373 200 v dd = 2.7 v 5.5 v PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 10 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 11. application information figure 13 shows a typical data transfer through the PCA9646. the PCA9646 has excellent application to extending loads and expanding the address space of slave devices. rise times are determined simply by the side of the buffer with the slowest rc time constant. figure 14 shows a typical application for the PCA9646. each channel can support up to the maximum permissible capacitance load, th us the maximum loading of the system can be 5 times that which could be achieved without buffering. the channel enable function can be used to interface buses of different operating frequencies. when certain bus sections are e nabled, the system frequency may be limited by a bus section having a slave device specified only to 100 khz. when that bus section is disabled, the slow slave is isolated and th e remaining bus can be run at 400 khz. the timing performance and current sinking capabilit y will allow the PCA9646 to run in excess of the 1 mhz maximum limit of the i 2 c-bus fast-mode plus (fm+), or to run a huge 4 nf load at 100 khz. figure 15 shows the PCA9646 used as a line driver . four such lines (only one shown) can be run from the same device. the receiving end may then again be used as a 4-way bus switch, radiating out into another four lines. using the address pins, this entire structur e may be repeated. thus a total of eight PCA9646 ?line drivers? may be connected to a single bus master (u1), allowing for 32 (8 ? 4) long distance bus pairs to be driven from the one i 2 c-bus port. remark: input to output delay exaggerated for clarity. fig 13. typical communication sequence through the PCA9646 002aaf374 s start sequence scl (clock) sda (data) a0 (master) a1 (master) a2 (master) master side of PCA9646 slave side of PCA9646 purpose of bit (address bit 5) device asserting data line (master/slave) a3 (master) a4 (master) a5 (master) a6 (master) sda direction 'hand over' pulses upon change of device asserting the data line w (master) ack (slave) p stop sequence PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 11 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch fig 14. PCA9646 typical buffer application 002aaf375 bus master u3 v dd scl sda r8 1.1 k sc0 sd0 scl sda PCA9646 v dd sc0 sd0 u1 reset 3.3 v scl sda v dd master/ slave u4 scl sda v dd slave u5 scl sda v dd slave u6 r7 1.1 k r1 1.1 k r2 1.1 k sc2 sd2 sc2 sd2 r3 1.1 k r4 1.1 k sc3 sd3 sc3 sd3 r5 1.1 k r6 1.1 k 400 pf load at 1 mhz or 4 nf load at 100 khz 400 pf load at 1 mhz or 4 nf load at 100 khz 400 pf load at 1 mhz or 4 nf load at 100 khz a0 a1 a2 v ss r10 1.1 k sc1 sd1 sc1 sd1 scl sda v dd slave u7 scl sda v dd slave u8 r9 1.1 k 400 pf load at 1 mhz or 4 nf load at 100 khz 400 pf load at 1 mhz or 4 nf load at 100 khz fig 15. PCA9646 as a 30 ma line driver 002aaf376 bus master u1 v dd scl sda r4 180 scl sda PCA9646 v dd sc0 sc1 u2 reset 5 v r3 180 r1 r2 a0 a1 e.g., pc/tv receiver or decoder box sd0 sd1 etc. sc2 sc3 a2 sd2 sd3 scl sda PCA9646 v dd sc0 sc1 u3 reset a0 a1 sd0 sd1 sc2 sc3 a2 sd2 sd3 address address backplane or long cable run with 30 ma pull-up current slave u4 v dd scl sda r6 r5 e.g., monitor, flat tv, led array PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 12 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch figure 16 shows how PCA9646 can be used to combine or extend existing long cable systems using p82b715 i 2 c-bus extenders when they have reached their maximum capacitance limit. p82b715 alone provides a ?10 ? impedance transformation? ( ref. 2 ) but no isolation of the loadings on either side. p82b715 systems have a finite capacitance limit and its system calculations can be relatively complex. the buffering action of PCA9646 simplifies calculations and allows the isolated bus rise time to meet the fast-mode requirement even when that is not possible on the long cable section. of course it is possible to create a much larger system by connecting existing long p82b715 cable systems to each of the four channels and driving all of them from one isolated master. PCA9646 provides bus isolation and simp lifies calculation of bus rc components. fig 16. PCA9646 isolating the standard i 2 c-bus from a p82b715 used as a line driver 002aaf377 scl sda scl sda PCA9646 v dd sc0 sc1 u1 reset 5 v r1 1.8 k r2 1.8 k a[2:0] sd0 sd1 sc2 sc3 sd2 sd3 p82b715 u2 v cc sx sy r4 r3 3 lx ly long cable run isolated i 2 c-bus no pull-up required PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 13 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch the PCA9646 may also be driven in series. figure 17 shows this configuration. in this scenario, each of the four outputs of the first device (u2) has six more PCA9646?s connected to it. each of those six devices has four outputs, thus giving 4 ? 7 ? 4 = 112 outputs. if the reset pin on u2 was also driven from the master, it would be possible to reproduce this entire struct ure multiple times, giving a truly massive address space capability. such a configuration may be applied to situations such as display drivers. fig 17. PCA9646 series implementation for large i/o fan-out 002aaf378 scl scl sda PCA9646 v dd sc0 sc1 u2 reset 5 v r1 180 r2 180 a[2:0] sd0 sd1 sc2 sc3 sd2 sd3 3 bus master u1 v dd scl sda 000b up to seven PCA9646s on each output pair (address: 001b to 111b) structure in dashed box repeated etc. r4 180 r3 180 scl sda PCA9646 v dd sc0 sc1 u3 reset sd0 sd1 sc2 sc3 sd2 sd3 a[2:0] 3 001b total output of 4 7 4 = 112 individually enabled fully isolated buses, each with full capacitance load (e.g., 400 pf at 1 mhz) 5 v scl sda PCA9646 v dd sc0 sc1 u4 reset sd0 sd1 sc2 sc3 sd2 sd3 a[2:0] 3 010b connect, for example, 8 led driver ics, each with 8 led outputs = 7168 leds up to seven devices (address: 001b to 111b) PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 14 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 12. package outline fig 18. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1 PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 15 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch fig 19. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 16 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 13. handling information 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering caution this device is sensitive to electrostatic di scharge (esd). observe precautions for handling electrostatic sensitive devices. such precautions are described in the ansi/esd s20.20 , iec/st 61340-5 , jesd625-a or equivalent standards. PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 17 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 20 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 5 and 6 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 20 . table 5. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 6. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 18 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations 16. references [1] um10204, ?i 2 c-bus specification and user manual? ? nxp semiconductors; www.nxp.com/documents/user_manual/um10204.pdf [2] p82b715, i 2 c-bus extender ? nxp semiconductors; product data sheet; www.nxp.com/documents/data_sheet/p82b715.pdf msl: moisture sensitivity level fig 20. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 7. abbreviations acronym description cmos complementary metal-oxide semiconductor i 2 c-bus inter-integrated circuit bus i/o input/output ic integrated circuit led light-emitting diode msb most significant bit pmbus power management bus raid redundant array of independent discs rc resistor-capacitor network smbus system management bus PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 19 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 17. revision history table 8. revision history document id release date data sheet status change notice supersedes PCA9646 v.1 20110301 product data sheet - - PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 20 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. PCA9646 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1 ? 1 march 2011 21 of 22 nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors PCA9646 buffered 4-channel 2-wire bus switch ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 1 march 2011 document identifier: PCA9646 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 v dd , v ss ? dc supply pins . . . . . . . . . . . . . . . 4 7.2 scl ? clock signal input . . . . . . . . . . . . . . . . . 4 7.3 sc0, sc1, sc2, sc3 ? clock signal outputs. . 4 7.4 sda, sd0, sd1, sd2, sd3 ? data signal inputs/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.5 reset ? reset ic to default state . . . . . . . . . . 5 7.6 power-on reset (por) . . . . . . . . . . . . . . . . . . 5 7.7 a0, a1, a2 ? address lines . . . . . . . . . . . . . . . 5 7.8 control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 bus transaction . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 application information. . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 handling information. . . . . . . . . . . . . . . . . . . . 16 14 soldering of smd packages . . . . . . . . . . . . . . 16 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 16 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 16 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 17 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 16 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 19 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 20 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 20 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21 19 contact information. . . . . . . . . . . . . . . . . . . . . 21 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 |
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