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holt integrated circuits www.holtic.com 1 november, 2010 HI-6120 parallel bus interface and hi-6121 serial peripheral interface (spi) mil-std-1553 remote terminal ics ds6120 rev. b 11/10 features ? fully integrated 3.3v remote terminal meets all requirements for mil-std-1553b notice 2 ? four data buffer modes for subaddress transmit and receive commands. data buffer modes are independently selectable for transmit and receive commands on each subaddress ? simplifed mode code command handling ? integral 16-bit time-tag counter has programma - ble options for clock, interrupts and auto-synchro - nization ? message information and time-tag words are stored with message data words for all transacted messages ? in compliance with mil-std-1553b notice 2, re - ceived data from broadcast messages may be optionally separated from non-broadcast received data ? optional interrupt log buffer stores the most recent 16 interrupts to minimize host service duties ? optional illegal command detection uses internal table ? optional automatic self-initialization at reset ? 8kv esd protection (hbm, all pins) ? mil-std-1760 compliant pin configuration (top) general description the HI-6120 and hi-6121 provide a complete, integrated, 3.3v mil-std-1553 remote terminal in a monolithic sili - con gate cmos device. two host interface options are offered: the HI-6120 uses a 16-bit parallel host bus inter - face for access to registers and ram and is offered in a 100-pin plastic quad fat pack (pqfp). the hi-6121 has a 4-wire spi (serial peripheral interface) host connection and comes in a reduced pin count 52-pin pqfp or 9mm x 9mm 64-pin qfn. both devices handle all aspects of the mil-std-1553 protocol, including message encod - ing, decoding, error detection, illegal command detection and data buffering. host data management is simplifed by storing message information and data within the on- chip 32k x 16 static ram. a descriptor table in shared ram provides fully program - mable memory management. multiple descriptor tables can be implemented for fast context switching. trans - mit and receive commands can use any of four differ - ent data buffer modes: indexed (single) buffering, ping- pong (double) buffering or two circular buffer schemes. transmit and receive commands for each subaddress may use different buffer modes. mode code commands employ a simple scheme for storing mode data and mes - sage information with programmable interrupts. the device provides internal illegalization capability, allowing any subset of subaddress, command t/ r bit, broadcast vs non-broadcast and word count (or mode code) to be illegalized, resulting in a total of 4,096 pos - sible combinations. the illegalization table resides in in - ternal ram. the rt can also operate without illegal com - mand detection, providing in form responses to all valid commands. broadcast command recognition is optional. the HI-6120 and hi-6121 provide programmable inter - rupts for automatic message handling, message status and general status. a host interrupt history log maintains information about the last 16 interrupts. the HI-6120 and hi-6121 can be confgured for automat - ic self-initialization. a dedicated spi port reads data from external serial eeprom memory to fully confgure the descriptor table, illegalization table and host interrupts. internal dual-redundant transceivers provide direct connection to bus isolation transformers. the device is offered with industrial temperature range as well as extended temperature range with optional burn-in. a rohs compliant lead-free option is also offered. hi-6121 in pqfp-52 package 52 - txinhb 51 - txinha 50 - aut oe n 49 - vcc 48 - g nd 47 - ssysf 46 - active 45 - ready 44 - ttclk 43 - ackint 42 - 41 - 40 - intmes inthw bendi 39 - test 38 - l ock 37 - m tst of f 36 - busa 35 - vccp 34 - 33 - 32 - vccp 31 - 30 - 29 - 28 - 27 - test3 busa busb busb test0 test1 test2 rt ap - 1 4 miso - 1 5 - 1 6 - 1 7 - 1 8 - 1 9 - 2 0 esck - 2 1 ee1k - 2 2 test7 - 2 3 test6 - 2 4 test5 - 2 5 - 2 6 mos i vcc gnd eecopy test4 ecs comp - 1 - 2 mod e - 3 si - 4 sck - 5 so - 6 mclk - 7 rt a0 - 8 rt a1 - 9 rt a2 - 1 0 - 1 1 rt a3 - 1 2 rt a4 - 1 3 ce mr hi-6121pqx
HI-6120, hi-6121 holt integrated circuits 2 notes:
HI-6120, hi-6121 holt integrated circuits 3 table of contents 1. block diagram ........................................................................................... 10 2. pin descriptions ....................................................................................... 11 3. functional overview .............................................................................. 16 3.1. shared ram utilization .............................................................................................. 16 3.1.1. descriptor table .......................................................................................................... 16 3.1.2. illegalization table ....................................................................................................... 16 3.1.3. message data buffers ................................................................................................. 16 3.1.4. storage for mode code commands ........................................................................... 16 3.1.5. interrupt log ................................................................................................................ 17 3.2. hardware feature summary ...................................................................................... 17 3.2.1. clock interrupts ........................................................................................................... 17 3.2.2. remote terminal address inputs ................................................................................ 17 3.2.3. integral time-tag counter ........................................................................................... 17 3.2.4. dual bus transceivers ................................................................................................ 17 3.2.5. encoder and decoders ............................................................................................... 17 3.2.6. auto-initialization serial eeprom interface ............................................................... 17 4. memory and register addressing ..................................................... 18 5. registers ..................................................................................................... 20 5.1. configuration register 1 (0x0000) ............................................................................ 21 5.2. configuration register 2 (0x0001) ............................................................................ 24 5.3. operational status register (0x0002) ...................................................................... 28 5.4. current command register (0x0003) ...................................................................... 30 5.5. current control word address register (0x0004) .................................................... 30 5.6. descripter table base address register (0x0005) .................................................. 30 5.7. pending interrupt register (0x0006) ........................................................................ 31 5.8. 1553 status word bits register (0x0007) ................................................................ 33 5.9. time-tag register (0x0008) ..................................................................................... 34 5.10. interrupt log address register (0x0009) .................................................................. 35 5.11. current message information word address register (0x000a) ............................. 35 5.12. memory address pointer register (hi-6121 only) (0x000f) ................................... 36 5.13. interrupt enable register (0x0010) .......................................................................... 36
HI-6120, hi-6121 holt integrated circuits 4 5.14. time-tag utility register (0x0011) ............................................................................ 38 5.15. bus a select register (0x0012) ................................................................................ 39 5.16. bus b select register (0x0013) ............................................................................... 39 5.17. built-in test word register (0x0014) ........................................................................ 40 5.18. alternate built-in test word register (0x0015) ........................................................ 41 5.19. reserved register (0x0016) ..................................................................................... 41 5.20. test control register (0x0017) ................................................................................ 41 5.21. loopback test transmit data register (0x0018) ..................................................... 45 5.22. loopback test receive data register (0x0019) ...................................................... 45 6. command responses ............................................................................... 46 6.1. rt to rt commands. ................................................................................................ 47 7. command illegalization table ............................................................. 48 8. temporary receive data buffer ......................................................... 52 9. interrupt log buffer ............................................................................. 52 10. descriptor table ...................................................................................... 55 10.1. receive subaddress control word ............................................................................ 57 10.2. transmit subaddress control word ........................................................................... 60 10.3. data buffer options for mode code commands ........................................................ 62 10.4. receive mode control word ...................................................................................... 63 10.5. transmit mode control word ...................................................................................... 65 11. message data buffers ............................................................................ 69 11.1. subaddress message information words ................................................................. 70 11.1.1. receive subaddress command ................................................................................ 70 11.1.2. transmit subaddress command ............................................................................... 72 11.2. mode command message information words ........................................................... 73 11.2.1. receive mode command ........................................................................................... 73 11.2.2. transmit mode command .......................................................................................... 75 11.3. ping-pong data buffering ........................................................................................... 78 11.3.1. double buffered (ping-pong) mode ............................................................................ 78 11.3.2. ping-pong enable / disable handshake ..................................................................... 78 11.3.3. broadcast message handling in ping-pong mode ..................................................... 80 11.4. indexed data buffer mode .......................................................................................... 82 11.4.1. single message mode ................................................................................................. 82
HI-6120, hi-6121 holt integrated circuits 5 11.4.2. broadcast message handling in index mode ............................................................. 82 11.5. circular buffer mode 1 ................................................................................................ 86 11.6. circular buffer mode 2 ................................................................................................ 90 12. mode command processing .................................................................. 95 12.1. general considerations .............................................................................................. 95 12.2. mode command interrupts ......................................................................................... 95 12.3. mode command data words ..................................................................................... 95 12.4. standard mode command processing ....................................................................... 98 12.5. simplified mode command processing ...................................................................... 98 13. interrupt management .......................................................................... 99 13.1. host message detection options ............................................................................... 99 13.2. host interrupt generation ........................................................................................... 99 13.2.1. interrupt log address register ................................................................................. 100 13.2.2. interrupt address word (iaw) ................................................................................... 100 13.2.3. interrupt identification word (iiw) ............................................................................ 100 14. reset and initialization ........................................................................ 101 14.1. master reset using the mr pin and optional auto-initialization ............................... 101 14.2. software reset ......................................................................................................... 105 14.3. reset remote terminal mode code ........................................................................ 105 14.4. serial eeprom programming utility ...................................................................... 105 15. host interface ........................................................................................ 107 15.1. HI-6120 host bus interface ...................................................................................... 107 15.1.1. bus wait states and data prefetch ........................................................................... 107 15.2. hi-6121 serial peripheral interface .......................................................................... 108 15.2.1. serial peripheral interface (spi) basics ................................................................... 108 15.2.2. hi-6121 spi commands ........................................................................................... 109 15.2.3. fast-access commands for registers 0-15 ............................................................ 109 15.2.4. indirect addressing of ram and registers .............................................................. 109 15.2.5. data prefetch for spi read cycles ............................................................................ 111 15.2.6. special purpose commands ...................................................................................... 111 15.2.7. descriptor table prefetch exceptions ....................................................................... 113 16. appendix: rt messages responses, options & exceptions ... 117 17. electrical characteristics .............................................................. 144
HI-6120, hi-6121 holt integrated circuits 6 17.1. absolute maximum ratings ...................................................................................... 144 17.2. recommended operating conditions ...................................................................... 144 17.3. dc electrical characteristics .................................................................................... 144 17.4. ac electrical characteristics D hi-6121 host bus interface timing ........................ 145 17.5. ac electrical characteristics D HI-6120 host bus interface timing ........................ 146 18. mil-std-1553 bus interface .................................................................. 151 19. thermal characteristics ................................................................... 152 20. additional pin / package configurations ..................................... 152 20.1. hi-6121pcx (64-pin qfn) ........................................................................................ 152 20.2. HI-6120pqx (100-pin qfn) ...................................................................................... 153 21. ordering information .......................................................................... 154 22. revision history ..................................................................................... 155 23. package dimensions .............................................................................. 156
HI-6120, hi-6121 holt integrated circuits 7 list of figures figure 1. HI-6120 / hi-6121 block diagram ................................................................................. 10 figure 2. address mapping for registers and ram .................................................................... 19 figure 3. mil-std-1553 command word structure ................................................................... 46 figure 4. deriving the illegalization table address from the received command word ........... 49 figure 5. fixed address mapping for illegalization table ........................................................... 50 figure 6. summary of illegalization table addresses for mode code commands ...................... 51 figure 7. fixed address mapping for interrupt log buffer .......................................................... 54 figure 8. address mapping for descriptor table ......................................................................... 56 figure 9. deriving a descriptor table control word address from command word ................. 57 figure 10. illustration of ping-pong buffer mode ........................................................................ 79 figure 11. ping-pong buffer mode example for a receive subaddress .................................... 81 figure 12. illustration of indexed buffer mode ............................................................................ 84 figure 13. indexed buffer mode example for a receive subaddress (broadcast not enabled) . 85 figure 14. illustration of circular buffer mode 1 .......................................................................... 88 figure 15. circular buffer mode 1 example for a receive subaddress ..................................... 89 figure 16. illustration of circular buffer mode 2 .......................................................................... 93 figure 17. circular buffer mode 2 example for a receive subaddress ..................................... 94 figure 18. generalized single-byte transfer using spi protocol. sck is shown for spi modes 0 and 3 ........................................................................................................................... 108 figure 19. single-word (2-byte) read from ram or a register ............................................... 110 figure 20. single-word (2-byte) write to ram or a register .................................................... 110 figure 21. hi-6121 host bus interface timing diagram ............................................................ 146 figure 22. register and ram write operations for btype = 1 ................................................ 147 figure 23. register and ram write operations for btype = 0 ................................................ 148 figure 24. register and ram read operations for btype = 1 ................................................ 149 figure 25. register and ram read operations for btype = 0 ................................................ 150
HI-6120, hi-6121 holt integrated circuits 8 figure 26. mil-std-1553 direct coupled test circuits ............................................................. 151 figure 27. mil-std-1553 transformer coupled test circuits ................................................... 151
HI-6120, hi-6121 holt integrated circuits 9 list of tables table 1. pin descriptions (both HI-6120 and hi-6121) ................................................................. 11 table 2. pin descriptions (HI-6120 only) ..................................................................................... 14 table 3. pin descriptions (hi-6121 only) ..................................................................................... 15 table 4. register summary ......................................................................................................... 20 table 5. settings and responses to interrupt-causing messages .............................................. 38 table 6. interrupt information word bits summary ...................................................................... 52 table 7. summary of data buffer modes. ................................................................................... 70 table 8. circular buffer mode 2 (initialization factors based on message block size) ................. 91 table 9. mode code command summary ................................................................................... 96 table 10. summary of interrupt outputs. .................................................................................... 99 table 11. interrupt identifcation word ....................................................................................... 100 table 12. summary of changes due to mr master reset or srst software reset ............... 103 table 13. fast-access spi commands for registers 0-15 ........................................................ 115 table 14. spi commands using address pointer register ......................................................... 116
HI-6120, hi-6121 holt integrated circuits 10 1. block diagram discrete signal interf ace to hos t inthw ssysf ackhw ackmes intmes ready active vccp memor y access manager shared st a tic ram and registers 32 k x 16 address sp ace mclk ttclk (opt) internal clocks vcc gnd logic power transceiver power mr test7:0 control address da ta control address da ta rt a 4 - 0 aut oen rt ap ee1k mtst off eecopy btype bwid bendi wpol config . option logi c HI-6120 onl y ce r / or w w e str oe or a0 / l b w ait or w ait d15:0 a15:1 sck si so host bus interf ace host spi interf ace HI-6120 onl y hi-6121 onl y message sequencer and dual encoder- decoders spi master mode interf ace to optional serial eeprom (aut o-config) bus busa bus busa busb busb txinha txinhb ecs esck mosi miso control address da ta remote terminal st at e machine bus transceivers lock test mode test logic comp } * * combined into ackint pin on hi-6121pqx variant figure 1. HI-6120 / hi-6121 block diagram
HI-6120, hi-6121 holt integrated circuits 11 2. pin descriptions table 1. pin descriptions (both HI-6120 and hi-6121) pin function description inthw output hardware interrupt output, active low.this signal is programmed as a brief low- going pulse output, or as a level output by the intsel bit in confguration regis - ter 1. intmes output message interrupt output, active low. this signal is programmed as a brief low-go - ing pulse output, or as a level output by the intsel bit in confguration register 1. mr input master reset, active low. internal 50k pull-up resistor. the host can also assert software reset by setting the srst bit in confguration register 1. mtstoff input memory test disable, active high. internal 50k pull-down resistor . when this pin is low, the device performs a memory test on the entire ram after rising edge on the mr reset pin. when this pin is high, the ram test is skipped, resulting in a faster reset process. for further information, refer to section 14 on page 101. eecopy input eeprom copy, active high. internal 50k pull-down resistor. this input is used to start the process that copies registers and confguration tables to serial eeprom. refer to section 14 on page 101. autoen input auto-initialize enable, active high. internal 50k pull-down resistor . if this pin is high at rising edge on mr reset input, automatic initialization proceeds, copying confguration data to registers and ram from an external serial eeprom via the dedicated auto-initialization spl port. refer to section 14 on page 101 . ee1k input when the autoen pin is high, the ee1k input sets the range of the auto-initial - ization process. when ee1k is low, registers and ram occupying the 32k ad - dress range from 0x0 to 0x7fff are initialized. for applications needing faster initialization, when ee1k is high, only registers and ram occupying the 1k address range from 0x0 to 0x03ff are initialized. this pin has an internal 50k pull-down resistor. if the autoen pin is low, this pin is not used. refer to section 14 on page 101 . rta4:0 rtap inputs remote terminal address bits 4 - 0, and parity bit. internal 50k pull-up resistors. the rtap pin should provide odd parity for the address present on pins rta4:0. terminal address and parity pin levels are latched into the operational status register when rising edge occurs on the mr pin. the operational status register value (not these pins) refects the active terminal address. the register value can be overwritten by the host under some circumstances. see section 5.3 on page 28. lock input internal 50k pull-down resistor. pin state is latched into the operational status register lock bit when rising edge occurs on the mr pin. if operational status register lock bit is high, terminal address in the register cannot be overwritten by a host register write. if operational status register lock bit is low , the host can overwrite the fve terminal address bits and address parity bit in the operational status register. txinha txinhb inputs transmit inhibits for bus a and bus b, active high. internal 50k pull-down resistors. these inputs are logically ored with the corresponding txinha and txinhb bits in confguration register 1. if the input pin or register bit is high, bus transmit is disabled.
HI-6120, hi-6121 holt integrated circuits 12 pin function description ready output pin is low when auto-initialization or built-in test is in-process. the host must not access shared ram or device registers when pin state is low. when output is high, the shared ram and registers may be confgured, and device will begin terminal execution when the stex (start execution) bit in confguration register 1 is set. active output pin is high when the HI-6120 / hi-6121 is actively processing a valid mil- std-1553 command, otherwise low. the falling edge signifes message comple - tion. mclk input master clock input, 50.0 mhz 0.01% (100ppm). internal 50k pull-down resistor . ttclk input time-tag clock input. internal 50k pull-down resistor. when confguration reg - ister 1 bits ttck2:0 = 001, this pin is the clock input for the time tag counter. for other values of ttck2:0, the time-tag counter is internally clocked so the ttclk pin is not used. ssysf input subsystem fail input, active high. internal 50k pull-down resistor . when this input is high, the HI-6120 / hi-6121 terminal sets the subsys fag in its status word. ecs output chip select output for the dedicated serial peripheral interface (spi) that con - nects to the optional external serial eeprom used for automatic self-initialization. for this auto-initialization spi, the device operates in spi master mode while the external memory operates in slave mode. this spi is separate from the host spi found in the hi-6121. esck output serial clock output signal for the dedicated auto-initialization spi connected to external auto-initialization eeprom. miso input serial input signal (master-in slave-out) for the dedicated auto-initialization spi connected to external auto-initialization eeprom. internal 50k pull-down resis - tor. mosi output serial output signal (master-out slave-in) for the dedicated auto-initialization spi connected to external auto-initialization eeprom. busa, busa analog bi-directional analog interface to mil-std-1553 bus a isolation transformer, posi - tive and negative signals respectively. busb, busb analog bi-directional analog interface to mil-std-1553 bus b isolation transformer , posi - tive and negative signals respectively. vcc, vccp power 3.3v supply voltage inputs for logic and transceiver circuits. gnd power ground pin for logic and transceiver circuits. test input test enable. internal 50k pull-down resistor. the host asserts this pin to per - form ram self-test or loopback tests. test7:0 bi-dir test pins used for factory testing. internal 50k pull-down resistor. do not con - nect these pins. mode input test pin used for factory testing. internal 50k pull-up resistor. do not connect this pin. comp input test pin used for factory testing. internal 50k pull-down resistor. do not con - nect this pin.
HI-6120, hi-6121 holt integrated circuits 13 pin function description ce input chip enable, active low. internal 50k pull-up resistor. when asserted, this pin enables host read or write accesses to device ram or registers. on hi-6121, it is normally connected to a host spi slave select output signal. bendi input confguration pin for selecting endianness of the host interface when byte trans - fers are used. internal 50k pull-up resistor. endianness is the system attribute that indicates whether integers are represented with the most signifcant byte stored at the lowest address (big endian) or at the highest address (little endian). internal storage is big endian. when using the HI-6120, this pin only applies when the host bus is confgured for 8-bit width, that is, when bwid equals 0. when the HI-6120 is confgured for 16-bit bus width, the bendi input pin is dont care. when using the hi-6121, this pin controls the byte order of the 16-bit data following the spi command. when bendi is low, little endian is chosen; the low order byte (bits 7:0) is trans - acted before the high order byte (bits 15:8). when bendi is high, big endian is chosen and the high order byte is transacted on the host bus before the low order byte. ackhw* input hardware interrupt acknowledge, active high. internal 50kw pull-down resistor. this input is only used when the intsel bit in confguration register 1 is assert - ed to enable level interrupts. after interrupt assertion causes the inthw output to go low, a high state (60ns minimum duration) on ackhw will clear the inthw output to logic 1. the interrupt is also cleared automatically by reading the pend - ing interrupt register. ackmes* input message interrupt acknowledge, active high. internal 50kw pull-down resistor. this input is only used when the intsel bit in confguration register 1 is as - serted to enable level interrupts. after interrupt assertion causes the intmes output to go low, a high state (60ns minimum duration) on ackmes will clear the intmes output to logic 1. the interrupt is also cleared automatically by reading the pending interrupt register. * note: these pins are combined into the ackint pin on hi-6121pqx variant.
HI-6120, hi-6121 holt integrated circuits 14 table 2. pin descriptions (HI-6120 only) pin function description d15:0 i/o tri-state data bus for host read/write operations upon registers and shared ram. internal 50k pull-down resistors. all read/write operations transact 16 bit words, but bus width can be confgured for 8 or 16 bits. for 8 bit bus width, pins d15:8 are not connected; each 16-bit word is transacted as a pair of upper and lower byte operations, with data presented sequentially on pins d7:0. for compatibility with different host processors, when byte transfers are enabled the bendi input pin sets whether the low order byte is transferred before the high order byte, or vice versa. a15:1 and a0 ( lb ) inputs address bus for host read/write operations upon registers and shared ram. for 16-bit bus width, address bit a0 ( lb ) from the host is not used. for 8-bit bus width, bit a0 equals 0 during the frst byte read/write access; while a0 equals 1 during the second byte access. bwid input confguration pin for host bus width. internal 50k pull-up resistor . high selects 16-bit bus width, low selects 8-bit bus width. btype input confguration pin for host bus read/write control signal style. internal 50k pull-up resistor. high selects intel style using separate read strobe oe (output enable) and write strobe we . low selects motorola style using combined read/write strobe str and read/write select signal, r/ w . r/ w or we input r/ w (read/write) signal when btype pin is low, or we (write enable) when btype pin is high. internal 50k pull-up resistor. used for host read or write ac - cesses to device ram or registers. important: this pin or the ce pin should be high during all address transitions. str or oe input when btype pin is low, common str (read/write strobe). when btype pin is high, oe (output enable). internal 50k pull-up resistor. used for host read or write accesses to device ram or registers. wait or wait output host bus read cycle wait output. for compatibility with different host processors, this output can be made active high or active low, set by the state of the wpol input pin. the wait output may be ignored when the host processors read cycle time is suffciently slow to meet worst case (slowest) read cycle timing for this device, or when wait cycles have been enabled from the processor . the wait output is useful when the host processor runs at high clock rates and/or when processor read wait states do not provide adequate timing margin for worst case (slowest) read cycle timing for this device. see section 15.1 on page 107 for further information. wpol input confguration pin for wait output polarity. internal 50k pull-up resistor. when wpol is low, the wait output is active low ( wait ). when wpol is high, the wait output is active high (wait). the HI-6120 uses pre-fetching to speed up any series of reads from successive addresses. as long as successive reads are sequential, only the frst words read cycle generates a wait ( wait ) output. no wait is generated for following words read.
HI-6120, hi-6121 holt integrated circuits 15 table 3. pin descriptions (hi-6121 only) pin function description so output serial peripheral interface (spi) serial output pin. so is normally connected to miso (master in - slave out) pin on host spi port. the so pin is tri-stated when not transmitting serial data to host. si input serial peripheral interface (spi) serial input pin. internal 50k pull-down resistor . si is normally connected to mosi (master out - slave in) pin on host spi port. sck input serial peripheral interface (spi) serial clock pin. internal 50k pull-down resis - tor. sck is normally connected to sck output pin on host spi port. ackint (hi-6121pqx variant only) input interrupt acknowledge, active high. internal 50k pull-down resistor. this input is only used when the intsel bit in confguration register 1 is asserted to enable level interrupts. after interrupt assertion causes the inthw or intmes output to go low, a high state (60ns minimum duration) on ackint will clear the inthw or intmes output to logic 1. interrupt outputs on inthw and intmes are also cleared by reading the pending interrupt register.
HI-6120, hi-6121 holt integrated circuits 16 3. functional overview the holt HI-6120 or hi-6121 provides a complete re - mote terminal (rt) interface between a host and a mil-std-1553b dual redundant data bus. it automati - cally handles all aspects of the mil-std-1553 protocol, namely, encoding/decoding, message formatting, error checking, message data buffering, protocol checking, illegalization and default terminal responses. internal static ram is shared by the host and device logic, pro - viding effcient storage for message data and informa - tion about messages, updated after each message transaction. the shared ram also contains host-initial - ized tables that defne terminal operation. two options are offered for host interface. the HI-6120 uses a 16-bit tri-state data bus, ideally suited for memo - ry-mapped host processor operation. the hi-6121 uses a 3-wire serial peripheral interface (spi) with powerful spi command set. figure 2 shows address mapping for registers and ram. registers occupy the lowest 32 addresses of the 32k memory address space. internal registers (or contained bit felds) are partitioned as read-only or read-write so the host can exercise confguration control without risk of misconfguration caused by accidental writes to de - vice-maintained registers or bit felds. dedicated output pins convey status to the host, and generate host interrupts for preselected events. before processing messages, internal registers and transmit data buffers in shared ram must be initialized by the host to defne the desired message responses. host ini - tialization can be replaced by optional auto-initialization using parameters in external eeprom. 3.1. shared ram utilization 3.1.1. descriptor table the host-initialized descriptor table, residing in shared ram, defnes terminal response to valid commands. the table is comprised of 4-word descriptor blocks. each of 32 subaddresses and 32 mode code values has two descriptor blocks, one for transmit and one for receive, for a total of 128 descriptor blocks. the frst word in each descriptor block defnes message options (interrupt selections, data buffer mode, etc.). except for indexed buffer mode (where one word counts messag - es) the remaining three words point to allocated data storage in shared ram. after master reset is negated and before message processing, the host must initialize descriptor blocks for each utilized subaddress and mode code. unused subaddresses and unimplemented mode codes may be illegalized (see below). the descriptor table base address register is initialized with the start - ing address of the descriptor table. multiple descriptor tables can be used for fast context switching, with the active table designated by the base address register. 3.1.2. illegalization table optional illegal command detection utilizes an illegal - ization table in the shared ram. the table can illegal - ize any logical combination of 11 command word bits for subaddress, t/ r bit and word count (or mode code), plus broadcast vs non-broadcast status, resulting in a total of 4,096 possible combinations. the illegalization table base address register is initialized with the ta - bles start address. terminal response to an illegal com - mand sets message error status and transmits status word only. if illegal command detection is not used (that is, no illegal entries in illegalization table), the terminal responds in form to all valid commands. 3.1.3. message data buffers after master reset, all locations in shared memory are re - set to 0000 hex. ordinary transmit or receive commands transfer 1 to 32 data words. these are called subad - dress commands, distinguishing them from mode code commands, described in the next paragraph. by ini - tializing the descriptor table, the host allocates space in shared ram for storing message data words and message information words. data pointers in the table assign separate data buffer addresses in memory for each command. data storage arrangement differs by choice of data buffer method. two examples are shown for each of the four buffer modes in figures 11-18. after successfully transacting a message with one or more re - ceived data words, the rt writes into the assigned data buffer. while transacting a message with one or more transmitted data words, the rt reads data for trans - mission from the assigned data buffer. before transmit commands occur, the host should write desired data into assigned transmit data buffers in shared ram. trans - mit subaddress data buffers can be optionally loaded by auto-initialization. 3.1.4. storage for mode code commands mil-std-1553 defnes mode code commands that are used for command and control, instead of data transfer. the various mode commands transfer a single data word, or no data word at all. the user has two choices for storing mode command data: (1) similar to subaddress command data, mode command data can be stored in ram data buffers assigned by the host-initialized de - scriptor table, or (2) when simplifed mode command processing is chosen, mode command data is stored
HI-6120, hi-6121 holt integrated circuits 17 within the descriptor table itself. just six defned mode commands transfer a data word; thus, option 2 is often preferred since initialization is easier. consistent, pre - dictable terminal responses can be set up for all mode commands, including the reserved and undefned mode codes. an option bit in confguration register 1 glob - ally sets whether the 22 undefned mode commands are treated as illegal (rt response dependent on com - mands illegalization table setting) or invalid (no rt re - sponse whatsoever, and no rt status change). 3.1.5. interrupt log the device maintains information from the last 16 inter - rupts in a 32-word circular buffer in shared ram known as the interrupt log. two 16-bit words characterize each interrupt; one word identifes the interrupt type (interrupt identifcation word) and one word identifes the com - mand that generated the interrupt (interrupt address word). after reset, the interrupt log address register is reset to the fxed starting address of the 32 word inter - rupt log. after each occurring interrupt, the device up - dates the register to point to the log address used for the next occurring interrupt. 3.2. hardware feature summary 3.2.1. clock interrupts a 50 mhz master clock input is required. the time-tag counter clock is selected from six internally generated frequencies, or may use an external clock input signal. 3.2.2. remote terminal address inputs the 5-bit remote terminal address is set using pins rta0 to rta4. the rtap input pin should be set or re - set to present matching odd parity. the state of the rt address and parity pins is latched into the operational status register upon rising edge on the mr master reset input. the state of the lock input is latched into the op - erational status register at the same time, and controls whether or not the active terminal address and parity in the operational status register can be overwritten by host writes into the register. between master reset as - sertions, the state of the rta and rtap inputs is dont care. if the value of rt address and parity in the opera - tional status register has parity error, terminal operation is disallowed. 3.2.3. integral time-tag counter a free-running 16-bit counter provides time-tag values that are recorded for each message transacted. the time-tag counter can be clocked from one of six inter - nally generated frequencies, or from an external source. the user can enable automatic counter synchronization in response to synchronize mode commands, and op - tional host interrupts are provided for time-tag counter roll-over, and counter match to a stored value in the time-tag utility register. 3.2.4. dual bus transceivers built-in bus transceivers provide direct interface between the device and mil-std-1553 bus isolation transform - ers. the transceivers convert digital data to and from differential manchester ii encoded bus signals. a pair of transmit inhibit input pins exercises direct control over transmission for both buses. 3.2.5. encoder and decoders the rt contains separate manchester ii encoders and decoders for each bus. encoder-decoder logic inter - faces directly with the dual-bus mil-std-1553 trans - ceivers. the decoder checks for proper sync pulse and manchester waveform, edge skew, correct number of bits and parity. during transmission, each encoded word is looped back through the decoder to check for errors. bus sampling is clocked at 25 mhz, providing superior tolerance to zero-crossing distortion. 3.2.6. auto-initialization serial eeprom interface the device has an automatic self-initialization feature. if self-initialization is enabled after mr master reset, the device reads confguration settings from external serial eeprom to load the descriptor table, illegaliza - tion table, transmit mode command data and registers for terminal operation. self-initialization can optionally initialize transmit data buffers with fxed data from ee - prom. a mechanism is provided to initially program or later modify the external serial eeprom memory, by copying host-loaded tables and register values to the serial eeprom.
HI-6120, hi-6121 holt integrated circuits 18 4. memory and register addressing the HI-6120 and hi-6121 have an internal address space of 32k 16-bit words. all memory addresses in this data sheet are expressed as hexadecimal numbers, using the c programming convention where the prefx 0x denotes a hexadecimal value; e.g., 0x00ff repre - sents 00ff hex. all device ram and register address mapping is word oriented, rather than byte oriented. register and mem - ory addresses throughout this document refect word addressing. for all hi-6121 and most HI-6120 applica - tions, word oriented addressing applies. word oriented addressing with the HI-6120 uses address inputs a15 to a1; address input a0 is not used as ffteen bits are suf - fcient for a 32k address range. HI-6120 only: when required by the application, the host bus interface HI-6120 is able to use byte transfers. all 8-bit microprocessors (and some 16-bit and 32-bit mi - croprocessors) use (or can use) byte-oriented memory accesses. to provide byte capability, the HI-6120 has a sixteenth bus address input, a0. byte oriented address - ing with the HI-6120 uses all 16 address pins, a15:a0 to address 64k bytes. the a0 input denotes whether the frst or second byte in the word is being addressed, while a15:a1 indicate the word address. this difference must be considered when assigning HI-6120 pointer values or accessing ram or registers. from the microproces - sors standpoint, any host-assigned ram buffer address will be double the value of the buffers pointer stored in ram. this paragraph only applies to HI-6120 us - ing 8-bit bus width. from this point on, all register and memory addresses presented in this data sheet are 15- bit word addresses. from the host standpoint, register operations and ram operations are performed identically. registers occupy the lowest 32 addresses, 0x0 to 0x001f. depending on function, individual registers may be read-only, read- write, or a combination of read-only and read-write bit felds. read-only registers, and read-only bit felds con - tained in registers, are protected against accidental host overwrite by device logic. addresses in the range 0x0020 to 0x7fff apply to static ram memory. all ram is read-write and can be written or read by either the host or the internal device logic. some memory locations (specifcally descriptor table control words) contain bits updated by both host and device. these locations are protected against accidental data collision by device arbitration logic which acts when concurrent writes by both host and device occur.
HI-6120, hi-6121 holt integrated circuits 19 0x0200 0x0100 0x0000 0x01ff 0x00ff 0x7fff 0x0040 0x003f 0x005f 0x0060 0x00ff 0x0400 0x03ff 0x0000 0x001f 0x0020 host-allocated subaddress data buffers. comprising 97% of the memory address space, this ram is allocated into subaddress data buffers by the descriptor table. descriptor table. defines terminal behavior for valid commands: how data is stored, host interrupts, etc. 512 words multiple descriptor tables can be used for fast context switching. the active descriptor table is defined by the descriptor table base address register. illegalization table. initialized by the host, this table identifies illegal commands. 256 words expanded at right unallocated memory. this space in shared ram can be assigned by the host. 160 words interrupt log data buffer. 32 words temporary receive data buffer. 32 words registers (listed on next page) 32 locations figure 2. address mapping for registers and ram
HI-6120, hi-6121 holt integrated circuits 20 5. registers residing at the start of the memory address space, 32 addresses are reserved for HI-6120 and hi-6121 registers. register addresses overlay the shared ram address space, but are separate from the shared dual-port ram. all register bits are active high. unless otherwise indicated, all registers are reset in software to the logic zero condition after master reset (except any bits refecting the state of input pins). for all registers, bit 15 is the most signifcant. table 4. register summary register number hex address register name 0 0x0000 confguration register 1 1 0x0001 confguration register 2 2 0x0002 operational status register 3 0x0003 current command register 4 0x0004 current control word address register 5 0x0005 descriptor table base address register 6 0x0006 pending interrupt register 7 0x0007 1553 status word bits register 8 0x0008 time-tag register 9 0x0009 interrupt log address register 10 0x000a current message information word address register 11-14 0x000b-0x000e reserved 15 0x000f memory address pointer (hi-6121 only) 16 0x0010 interrupt enable register 17 0x0011 time-tag utility register 18 0x0012 bus a select register 19 0x0013 bus b select register 20 0x0014 built-in test (bit) word register 21 0x0015 alternate built-in test (bit) word register 22 0x0016 reserved 23 0x0017 test control register 24 0x0018 loopback test transmit data register 25 0x0019 loopback test receive data register 26-31 0x001a-0x001f reserved
HI-6120, hi-6121 holt integrated circuits 21 5.1. confguration register 1 (0x0000) this 16-bit register is read-write and is fully maintained by the host. all bits are active high. inhbusb ttck2 inhbusa ttck1 ttck0 srst stex bcstinv umcinv notice2 smcp intsel msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x ssrd8 sdsel note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 inhbusa r/w 0 bus a inhibit. when set, this bit disables transmit and receive for bus a. this bit is logically ored with the txinha input signal to control bus a transmitter enablement. bus a transmission is disabled if the inhbusa register bit or txinha input pin is asserted. the txinha pin does not affect the bus a receiver. 14 inhbusb r/w 0 bus b inhibit. when set, this bit disables transmit and receive for bus b. this bit is logically ored with the txinhb input signal to control bus b transmitter enablement. bus b transmission is disabled if the inhbusb register bit or txinhb input pin is asserted. the txinhb pin does not affect the bus b receiver. 13 intsel r/w 0 interrupt mode select. when this bit is low, pulse interrupt outputs are selected for intmes and inthw output pins. when this bit is high, level interrupts are enabled which require host acknowledgment for interrupt pin reset.
HI-6120, hi-6121 holt integrated circuits 22 bit no. mnemonic r/w reset function 12 sdsel r/w 0 shutdown select. this bit affects terminal response to transmitter shutdown mode code commands and only applies when the mcopt4 bit in confguration register 2 equals logic 0 for automatic shutdown after transmitter shut - down and selected transmitter shutdown mode code commands. when mcopt4 and sdsel are both logic 0, a valid transmitter shutdown mode command automatically disables the inactive bus transmitter and receiver (complete bus shutdown). this is the recommended mode of operation and is the default state of these two bits after mr reset. when mcopt4 is logic 0 and sdsel is logic 1, transmitter shutdown or selected transmitter shutdown mode commands automatically disable just the inactive bus transmitter, but the bus receiver remains enabled. the terminal fully complies with valid commands received on the inactive bus (storing received data, etc.), except it does not transmit status or data onto that bus (mute terminal). this mode of operation is not recommend - ed but may be required in some applications. see mcopt4 bit in confgu - ration register 2 for further information concerning transmitter shutdown and selected transmitter shutdown mode commands. the built-in test (bit) word register contains status fags that refect automatic shutdown status when the mcopt4 bit in confguration register 2 is logic 0. see page xx. 11, 10, 9 ttck2:0 r/w 0 time-tag counter clock select. these three bits select the time-tag coun - ter clock source from the following options: ttck2 0 0 0 0 1 1 1 1 ttck1 0 0 1 1 0 0 1 1 ttck0 0 1 0 1 0 1 0 1 clock source time-tag counter disabled external clock provided at ttck input pin internally generated 2s clock internally generated 4s clock internally generated 8s clock internally generated 16s clock internally generated 32s clock internally generated 64s clock 8 stex r/w 0 start execution. assertion of this bit initiates rt operation; negation of this bit inhibits or stops rt operation. upon stex assertion, rt parity-address error pre - vents terminal operation, regardless of the logical state of the stex bit. if rt address parity error occurs, the status register and pending inter - rupt register rtapf bits will be asserted. this bit is cleared after mr pin master reset. 7 srst r/w 0 (sr = 0) software reset. assertion of this bit immediately initiates the software reset process. this bit should not be set to logic 1 during auto-initialization. this bit is cleared after mr master reset and automatically self-resets after being set by the host. 6,5 ----- r/w 0 (sr = 0) not used.
HI-6120, hi-6121 holt integrated circuits 23 bit no. mnemonic r/w reset function 4 bcstinv r/w 0 broadcast commands invalid. if this bit is high, commands addressed to rt address 31 are treated as invalid: there is no terminal recognition of commands to rt address 31; there is no rt command response, and no status updating for the beneft of following transmit status or transmit last command mode commands. if this bit is low, commands addressed to rt address 31 are treated as valid broadcast commands. 3 umcinv r/w 0 undefned mode codes invalid. this bit globally defnes whether undefned mode code commands are treated as valid (default) or invalid commands. this bit applies only to the following undefned mode code commands: mode codes 0 through 15 with t/ r bit = 0 mode codes16, 18 and19 witht/ r bit = 0 mode codes 17, 20 and 21 with t/ r bit = 1 if this bit is low (default state after mr pin reset) undefned mode code commands are considered valid, and rt response is based on individual mode command settings in the illegalization table: if a mode command is legal, the rt responds in form and updates status. if a mode command is illegal, the rt asserts message error status and (if non-broadcast) transmits only its status word without associated data word. later in this data sheet, the section rt message responses, options & exceptions fully describes terminal response for each mode code value, command word t/ r bit state, and option settings. if this bit is high, undefned mode code commands are treated as invalid: there is no rt recognition of an invalid command, no rt command response, and no status updating for the beneft of following transmit status or transmit last command mode commands. 2 notice2 r/w 0 if this bit is high, the terminal stores data associated with broadcast com - mands separately from data associated with non-broadcast commands to meet the requirements of mil-std-1553b notice 2. if this bit is low , broadcast command data is stored in the same buffer as non-broadcast command data. 1 smcp r/w 0 simplifed mode command processing. when asserted, the device applies simplifed processing for all valid mode code commands. the later section entitled mode command processing describes this option. 0 ssrd8 r/w 0 single-strobe read for 8-bit parallel bus mode. this bit only applies to HI-6120 (not hi-6121) and only applies when the parallel host bus is confgured for 8-bit bus width. when performing 2-byte read accesses of external memory, some microprocessors with 8-bit bus assert individual read enable (or strobe ) pulses for high and low bytes. other microprocessors assert a single, wider read enable (or strobe ) pulse, while simply changing the low address bit (a0 / lb ) to access the two bytes. for this last case, the ssrd8 bit should be set when writing device confguration, before register or ram readback is performed.
HI-6120, hi-6121 holt integrated circuits 24 5.2. confguration register 2 (0x0001) this 16-bit register is read-write and is fully maintained by the host. all bits are active high. ttload rt ta g trxdb t osel0 mcopt4 mcopt3 mcopt2 mcopt1 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t osel1 x x mcopt0 al tbitw x x x note: reset refers to bit value following master reset ( mr ). this register is unaffected by software reset. bit no. mnemonic r/w reset function 15,14 tosel1:0 r/w 0 time-out select for rt-rt receive commands. these bits select the no response time-out for rt-rt receive commands. message error occurs when the transmitting remote terminal fails to begin transmission before time-out occurs. time interval boundaries are defned in rt validation test plan figure 8 rt-rt timeout measurement. mil-std- 1553b stipulates that 54 to 60s is the acceptable range for time-out. how - ever, longer time-out options are provided for systems using long buses and/ or utilizing bus repeaters that add delay to bus traffc. rt-rt time-out can be selected from the following options: tosel1 1 1 0 0 tosel0 1 0 1 0 rt-rt time-out 150s 125s 100s 57s (default after mr pin master reset) 13 trxdb r/w 0 temporary receive data buffer. setting this bit enables a temporary data buffer for all receive commands. when enabled, the rt stores received data words in a 32-word data buffer during message processing. upon error-free message completion, all saved words are written to data buffer memory in a burst. when the temporary receive data buffer is disabled, the rt writes each received data word to the subaddress data buffer memory as it is received. should message error oc - cur during data word reception, this mode results in loss of data integrity , as vaild data from the prior command is partially overwritten by data from a mes - sage with error. mil-std-1553 states that data should be disregarded for messages ending in error. this bit should only be modifed while confgura - tion register 1 stex bit is low. changes occurring while stex = 1 cause un - predictable results. in a typical application, the buffer is not directly accessed by the host, although there is no restriction preventing host data access. 12 ttload r/w 0 load time-tag counter. when this bit is written from logic 0 to logic 1, data contained in the time- tag utility register is written to the time-tag counter. the ttload register bit self-resets after use. see mcopt3 bit which affects automatic time-tag counter loading upon synchronize mode command with data word.
HI-6120, hi-6121 holt integrated circuits 25 bit no. mnemonic r/w reset function 11 rttag r/w 0 reset time-tag counter. assertion of this bit clears the time-tag counter and counting is disabled until the bit is negated. also the synchronize mode command (mc1) causes automatic time-tag counter reset. 10 altbitw r/w 0 alternate bit word enable. if this bit is logic 0, the device responds to a transmit bit word mode com - mand (mc19) by sending the word stored in the built-in test word register, at address 0x0014. if this bit is logic 1, the terminal transmits the word stored in the alternate built-in test word register, at address 0x0015. the alternate register allows the user to fully defne the bit word, while the default register location contains several predefned, device-controlled status bits. 9 mcopt4 r/w 0 mode code option 4. note: mode commands mc4 and mc5 are not affected by the mcopt4 bit, but are included in this description to present a complete picture of device response to bus shutdown mode commands. the bus controller exercises shutdown control over the terminal s con - nection to the inactive mil-std-1553 bus using the transmitter shutdown (mc4) or selected transmitter shutdown (mc20 decimal) mode code commands. when the inactive transmitter is shutdown, the hi-612x device inhibits further transmission on that bus. once shutdown, the transmitter can be reactivated by (a) an override transmitter shutdown (mc5) mode com - mand, (b) an override selected transmitter shutdown (mc21 decimal) mode command, (c) a reset remote terminal (mc8) mode command, (d) hardware mr master reset or (e) software reset by setting the srst bit in confgura - tion register 1. when the mcopt4 bit is reset, the device automatically performs bus shut - down and shutdown override in response to mode commands. when the mcopt4 bit is set, the device only transmits status; the host must perform bus shutdown and override duties by asserting control of the txinha and txinhb bits in confguration register 1, or by controlling the input pins with the same function. mode commands mc4 (transmitter shutdown) and mc5 (override trans - mitter shutdown) have unconditional shutdown or override response. when mc4 is received, the terminal fulflls shutdown for the inactive bus, disabling the transmitter and receiver, or transmitter only, depending on the state of the sdsel bit in confguration register 1. the device affrms shutdown status by updating bits 15-12 in the bit word register. when mode command mc5 is received, inactive bus transmit and receive is automatically reenabled by the device; shutdown override status is affrmed by resetting the inactive bus shutdown bit(s) in the bit word register.
HI-6120, hi-6121 holt integrated circuits 26 bit no. mnemonic r/w reset function 9 mcopt4 (continued) r/w 0 the selected transmitter shutdown (mc20 decimal) and override selected transmitter shutdown (mc21 decimal) mode commands act similarly to mc4 and mc5 respectively, except bus shutdown (or shutdown override) is condi - tional, based on the value of a mode data word received with the command. to act on a given bus, the received mode data word must match a predeter - mined bus select value. bus shutdown (or shutdown override) can only act on the inactive bus, and only when the received mode data word matches the bus select value for that bus. when a mc20 mode data word matches the bus select value for the inactive bus, the terminal fulflls shutdown for the inactive bus, disabling the transmitter and receiver, or transmitter only, depending on the state of the sdsel bit in confguration register 1. the de - vice affrms shutdown status by updating bits 15-12 in the bit word register. when a mc21 mode data word matches the bus select value for the inac - tive bus, the terminal fulflls shutdown override for the inactive bus, enabling the transmitter (and receiver, if the sdsel bit in confguration register 1 is logic 0). the device affrms override status by resetting bits 15-12 in the bit word register. when the mcopt4 bit equals zero, unique bus select values should be ini - tialized by the host in the bus a select register (0x0012) and bus b select register (0x0013) for fulfllment of selected transmitter shutdown and over - ride mode commands. when mcopt4 equals zero, transmitter shutdown (or shutdown override) automatically occurs when the received mode data value matches the inactive bus bus select register. below shows device response for transmitter shutdown and override trans - mitter shutdown mode code commands for different option confgurations: the mcopt4 bit in confguration register 2 is logic 0 or 1 mc4 (or mc5) unconditional fulfllment inactive bus tx & rx disabled (enabled). (only tx is disabled, if the sdsel confg. bit = 1) status word transmitted, unless broadcast in bit word register, txsd & rxsd bits updated. (only txsd bit updated, if the sdsel confg. bit = 1) the mcopt4 bit in confguration register 2 is logic 0 mc20 (or mc21) if mode data value matches bus select value inactive bus tx & rx disabled (enabled). (only tx is disabled, if the sdsel confg. bit = 1) status word transmitted, unless broadcast in bit word register, txsd & rxsd bits updated. (only txsd bit updated, if the sdsel confg. bit = 1) mc20 (or mc21) if mode data does not match bus select value inactive bus tx & rx status not changed status word transmitted, unless broadcast in bit word register, txsd & rxsd bits are static
HI-6120, hi-6121 holt integrated circuits 27 bit no. mnemonic r/w reset function 9 mcopt4 (continued) r/w 0 the mcopt4 bit in confguration register 2 is logic 1 mc20 (or mc21) if mode data value matches bus select value inactive bus tx & rx status not changed (host can modify businh bit in con - fguration reg 1) status word transmitted, unless broadcast in bit word register, txsd & rxsd bits are static mc20 (or mc21) if mode data does not match bus select value inactive bus tx & rx status not changed status word transmitted, unless broadcast in bit word register, txsd & rxsd bits are static 8,7 mcopt3:2 r/w 0 mode code options 3 and 2. if both of these bits equal one, the data word received with a valid synchro - nize mode command (mc17) is unconditionally loaded into the time-tag counter. for non-broadcast mc17 commands, the counter load occurs be - fore status word transmission. if both of these bits equal 0, the external host assumes responsibility for actions needed to perform synchronize duties upon reception of the valid mc17 synchronizemode code command, but status transmission automatically occurs. the binary 01 and 10 combinations of the mcopt3 and mcopt2 bits sup - port certain extended subaddressing schemes. if the mcopt3-mcopt2 bits equal 01, the received data word is automatically loaded into the time- tag counter if bit 0 of the received data word equals 0. if the mcopt3- mcopt2 bits equal 10, the received data word is automatically loaded into the time-tag counter if bit 0 of the received data word equals 1. for non-broadcast mc17 commands, the counter load occurs before status word transmission. 6 mcopt1 r/w 0 mode code option 1. if this bit is logic 0, reception of a transmit vector word mode command (mc16) causes automatic reset of the service request status bit. the ser - vice request bit is reset in the status word bits register before status word transmission begins. if the mcopt1 bit is logic 1, the external host assumes responsibility for resetting the service request bit in the status w ord bits register. 5 mcopt0 r/w 0 mode code option 0. if this bit is logic 0, reception of a reset remote terminal mode command (mc8) causes automatic assertion of srst software reset. if non-broadcast mode command, reset occurs after status word transmission is complete. if this bit is logic 1, the external host assumes responsibility for actions needed to perform terminal reset. 4-0 ----- r/w 0 not used
HI-6120, hi-6121 holt integrated circuits 28 5.3. operational status register (0x0002) all sixteen register bits are active high. after rising edge on the mr master reset input pin, bits 15 - 8 refect the state of input pins rta4 through rta0, rtap, lock and autoen; register bits 7 - 3 are reset to logic 0 state. register bits 8 - 0 are always read-only. if the registers lock bit is logic 0, bits 15 - 9 are read-write but cannot be written unless stex in confguration register 1 is low. if the register lock bit is logic 1, bits 15 - 9 are is read-only. once the lock bit is set, unlock requires a new mr master reset assertion with the lock input pin at logic 0 state. rt a1 rt a0 rt a2 rt a3 rt ap lock aut oen rt apf ready active msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rt a4 eeckf mcnd mcrd mctd ramif note: reset refers to bit value following master reset ( mr ). the value pin denotes the bit is set to the value of the corresponding pin following master reset. this register is unaffected by software reset. bit no. mnemonic r/w reset function 15-11 rta4 - 0 r/w pin remote terminal address bits 4 - 0. 10 rtap r/w pin remote terminal address parity. these bits contain the active remote terminal address. after a rising edge on the mr master reset input signal, these bits refect the state of the rta4 - 0 and rtap input pins. when the register lock bit is high, these bits are read-only. when the register lock bit is low (and stex in con - fguration register 1 equals 0) auto-initialization (see bit 8) or the host can overwrite these bits to change the terminal address and parity. 9 lock r/w pin terminal address lock. after a rising edge on the mr master reset input signal, this bit refects the state of the lock input pin. when the lock bit is high, this bit is read-only . when lock is low (and stex in confguration register 1 equals 0) auto- initialization (see bit 8) or the host can write this bit to logic 1 to lock the active terminal address. 8 autoen r pin auto-initialize enable. this read-only bit refects the state of the autoen input pin that applied at the rising edge on the mr master reset input signal. if the register autoen bit is high, device auto-initialization was performed following mr reset. when auto-initialization is complete, the device waits for the host to as - sert the stex bit in confguration register 1 to enable terminal operation. auto-initialization of the control register can optionally set stex to begin terminal operation without host assistance. see section entitled reset and initialization for details. 7 ready r 0 ready status. this read-only bit refects the state of the output pin ready and is cleared on reset. the bit is asserted after post-reset internal terminal initialization is complete, indicating that shared ram is ready to accept confguration data from the host.
HI-6120, hi-6121 holt integrated circuits 29 bit no. mnemonic r/w reset function 6 active r 0 active status. when set, this read-only bit indicates the terminal is presently processing a message. this bit refects the state of output pin active and is cleared on reset. note: ths bit and the corresponding output pin are asserted upon valid command detection and negated when command processing is com - pleted. 5,4,3 mcnd mcrd mctd r 0 mode code command type flags (no-data, receive-data and transmit- data). these three bits refect the state of the command stored in the current command register, 0x0003: current command type mcnd mcrd mctd current com - mand word subaddress (not mode code) 0 0 0 subaddress, transmit or receive mode code (no data word) 1 0 0 mc0 to mc15, t/ r bit equals 1 mode code (receive data) 0 1 0 mc16 to mc31, t/ r bit equals 0 mode code (transmit data) 0 0 1 mc16 to mc31, t/ r bit equals 1 mode code (undefned, no data) 1 1 1 mc0 to mc15, t/ r bit equals 0 2 rtapf r 0 rt address parity fail. this bit is set when remote terminal address parity error is present. the bit is low when correct odd parity applies to the terminal address latched in bits 15-10. this bit is high when parity error is present. 1 eeckf r 0 eeprom checksum fail. this bit only applies when auto-initialization is enabled. while performing auto-initialization, this bit is set if the checksum tallied from read eeprom data doesnt match the checksum value stored in eeprom. this failure also sets bit 1 in the built-in test word register (0x0014). 0 ramif r 0 ram initialization fail. this bit only applies when auto-initialization is enabled. while performing initialization, this bit is set if a write-then-read ram value doesnt match its counterpart location in the serial eeprom. this failure also sets bit 1 in the built-in test word register (0x0014).
HI-6120, hi-6121 holt integrated circuits 30 5.4. current command register (0x0003) this 16-bit register is read-only and is fully maintained by the device. 15 14 13 12 11 10 msb lsb current command 15:0 c c c c c c c c c c c c c c c c 9 8 7 6 5 4 3 2 1 0 note: reset refers to bit value following master reset ( mr ). this register is unaffected by software reset. bit no. mnemonic r/w reset function 15-0 cc15:0 r 0 current command word. this register contains the last valid command received over either mil- std-1553 bus. this register is updated 5us after the active output is as - serted. bit 15 is msb. 5.5. current control word address register (0x0004) this 16-bit register is read-only and is fully maintained by the device. 15 14 13 12 11 10 msb lsb current control word address 15:0 a a a a a a a a a a a a a a a a 9 8 7 6 5 4 3 2 1 0 note: reset refers to bit value following master reset ( mr ). this register is unaffected by software reset. bit no. mnemonic r/w reset function 15-0 ccw15:0 r 0 current control word address register this register contains the address for the descriptor table control w ord cor - responding to the current command stored in the current command register (0x0003). this register is updated 5us after the active output is asserted. bit 15 is msb. also see current message information word address regis - ter, 0x000a. 5.6. descripter table base address register (0x0005) 15 14 13 12 11 10 msb lsb descriptor table base address 15:0 0 a a a a a a 0 0 0 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 this 16-bit register is read-write and is fully maintained by the host. this register is loaded with 0x0200 after mr pin master reset or srst software reset. the host maintains this register to specify the starting address for the descriptor table. for fast context switching, the host may initialize multiple descriptor tables, then update this register to load the new base address when the active descriptor table changes. the base address must be chosen with bits 7:0 = 00000000. these bits (and the highest address bit) cannot be set in the register. the primary descriptor table
HI-6120, hi-6121 holt integrated circuits 31 (enabled at reset) should reside at address space 0x0200 to 0x03ff. other tables (if used) could begin at address multiples of 0x0200, like 0x0400 and 0x0600. bit 15 and bits 8:0 cannot be set and will always read logic 0. thus a value written by the host must equal or exceed 0x200. 5.7. pending interrupt register (0x0006) this 16-bit register is read-only. if the corresponding bit is set in the interrupt enable register when a predetermined interrupt-causing event occurs, these actions occur: (1) a pending interrupt bit is set in this register, (2) the intmes or inthw output is asserted, depending on interrupt type, (3) the interrupt is registered in the interrupt log. if the cor - responding bit is reset in the interrupt enable register when a predetermined interrupt-causing event occurs, there is no reaction. to simplify host interrupt management, when the host reads this register, the pending interrupt register automatically resets to 0x0000 and (if level interrupts are enabled by the intsel confguration bit) the intmes and/or inthw output pins are automatically negated. for further information on interrupt behavior, also see descriptions for interrupt enable register and interrupt log address register, and refer to the later section entitled interrupt manage - ment. ilcmd ibr iwa merr eeckf msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ixeqz rtapf x x ramif x lbfa spifail lbfb ttint1 ttint0 note: reset refers to bit value following master reset ( mr ). this register is unaffected by software reset. bit no. mnemonic r/w reset function 15 ixeqz r 0 index equal zero interrupt. if the ixeqz bit is set in the interrupt enable register and the subaddress descriptor control word allows the ixeqz interrupt, this bit is asserted for (a) subaddresses using indexed buffer mode when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes when the pre-determined number of messages has been transacted. the intmes output is asserted and the interrupt log is updated. 14 iwa r 0 interrupt when accessed. if the iwa bit is set in the interrupt enable register and the subaddress de - scriptor control word allows the iwa interrupt, this bit is asserted each time a valid legal message is transacted for the subaddress. the intmes output is asserted and the interrupt log is updated. 13 ibr r 0 broadcast command received interrupt. if the ibr bit is set in the interrupt enable register and the subaddress de - scriptor control word allows the ibr interrupt, this bit is asserted each time a valid legal broadcast message is transacted for the subaddress. the intmes output is asserted and the interrupt log is updated. 12,11 ----- r 0 not used.
HI-6120, hi-6121 holt integrated circuits 32 bit no. mnemonic r/w reset function 10 merr r 0 message error interrupt. if the merr bit is set in the interrupt enable register, this bit is asserted when a message error is detected. errors can be caused by manchester encoding problems or protocol errors. the intmes output is asserted and the interrupt log is updated. 9 ----- r 0 not used. 8 ilcmd r 0 illegal command interrupt. if the ilcmd bit is set in the interrupt enable register, this bit is asserted each time an illegal message (determined by the illegalization table) occurs for a new command. the intmes output is asserted and the interrupt log is up - dated. see section illegalization table for additional information. 7 spifail r 0 spi fail interrupt (hi-6121 only). the hi-6121 uses a spi interface for host access. the device operates in spi slave mode. if the spifail bit is set in the interrupt enable register, this bit is asserted each time an incorrect number of sck clocks occurs during spi chip select assertion, the inthw output is asserted and the interrupt log is updated. 6,5 lbfa, lbfb r 0 loopback fail bus a and loopback fail bus b interrupts. during all transmitted command responses, the device compares words trans - mitted to the received and decoded words detected on the bus. if the lbf a or lbfb bit is set in the interrupt enable register, this bit is asserted each time this loopback detects mismatch. the intmes output is asserted and the inter - rupt log is updated. 4 ttint1 r 0 time-tag interrupt 1. if the ttint1 bit is set in the interrupt enable register, this bit is asserted each time the free-running time-tag counter value matches the value stored in the time-tag utility register. the inthw output is asserted and the interrupt log is updated. 3 ttint0 r 0 time-tag interrupt 0. if the ttint0 bit is set in the interrupt enable register, this bit is asserted each time the free-running time-tag counter value rolls over from full count 0xffff to 0x0000. the inthw output is asserted and the interrupt log is updated. 2 rtapf r 0 rt address parity fail interrupt. this bit is asserted when rt address and parity bits latched in the operational status register do not exhibit odd parity (odd number of bits having logic 1 state). because the rtapf bit is always set in the interrupt enable register, the inthw output is asserted and the interrupt log is updated. when par - ity error occurs, the rt will not begin operation, regardless of the state of the control register stex bit. 1 eeckf r 0 initialization eeprom checksum fail interrupt. this bit is asserted if serial eeprom checksum failure occurs during auto- initialization. because the eeckf bit is always set in the interrupt enable register, the inthw output is asserted and the interrupt log is updated.
HI-6120, hi-6121 holt integrated circuits 33 bit no. mnemonic r/w reset function 0 ramif r 0 ram initialization fail interrupt. this bit is asserted after auto-initialization if an initialized ram location does not match its 2 corresponding serial eeprom locations. because the ramif bit is always set in the interrupt enable register, the inthw output is asserted and the interrupt log is updated. 5.8. 1553 status word bits register (0x0007) this 16-bit register is read-write and is fully maintained by the host. all bits are active high. bits set in this register are refected in the outgoing mil-std-1553 status word. inst svcreq busy ssysf tf msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 txandclr 0 0 0 0 0 0 0 (me) * 0 (bcr) * 0 * status bit automatically controlled by device thedynamic bus control acceptance bit is not implemented; this device cannot function as bus controller. the host controls the instrumentation, busy, terminal flag, service request and subsystem flag status word bits by writing to bits 9:0 in this register. remote terminal status word responses refects the assertion of these register bits until negated by the host, unless the immediate clear function (bit 15) is enabled. the position of register bits 4 and 10 correspond to the broadcast command received (bcr) and message error (me) bits in the terminal status word. transmit state for the bcr and me bits in the terminals status word is controlled by the device, based on prior command transac - tions. this pair of register bits cannot be set by a host write operation and always read back logic 0, so do not refect the true status of these status fags. note: reset refers to bit value following either master reset ( mr ) or software reset. bit no. mnemonic r/w reset function 15 txandclr r/w 0 transmit (once) and clear. when this bit is set, the register is cleared after any set bits 0-9 are used once in a transmitted status word. this bit does not affect operation of the transmit status word and transmit last command mode codes. example: transaction of a valid legal command with the inst and txandclr bits asserted results in status word transmission with the instrumentation bit set. if the following command is transmit status or transmit last com - mand mode code, the instrumentation bit remains set. 14-10 ----- r 0 not used, these bits cannot be set. 9 inst r/w 0 instrumentation. when this bit is asserted, the instrumentation status bit is set. 8 svcreq r/w 0 service request. when this bit is asserted, the service request status bit is set. 7-4 ----- r 0 not used, these bits cannot be set.
HI-6120, hi-6121 holt integrated circuits 34 bit no. mnemonic r/w reset function 3 busy r/w 0 busy (global). when this bit is asserted, the device asserts busy bit in status response for all valid commands. instead of globally enabling busy status for all com - mands here, the host can assert busy status for selected commands by asserting the busy bit in descriptor table control words for the individual commands. when response to a command conveys busy status, the device suppresses transmission of data words that would normally accom - pany status transmission. for any message transacted with busy status, the wasbusy fag is asserted in the stored message information word. 2 ssysf r/w 0 subsystem flag. this register bit is logically ored with the ssysf input pin. if either ssysf register bit or ssysf pin is asserted, the ssysf subsystem flag status bit is set. if the confguration register 2 mcopt1 bit equals 0, reception of a transmit vector word mode command (mc16) causes automatic reset of the ssysf status bit in this register; when this occurs, the register bit is reset before status word transmission begins. 1 ----- r 0 not used, this bit cannot be set. 0 tf r/w 0 terminal flag. when this bit is asserted, the terminal flag status bit is set. 5.9. time-tag register (0x0008) this register is read only and is cleared after mr pin master reset or srst software reset. reads to this register address return the current value of the free running 16-bit time tag counter. counter resolution is programmed by ttck2:0 bits in confguration register 1. options are: 2, 4, 8, 16, 32 and 64us, or externally provided clock. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb time-tag count 15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 the device automatically resets the time-tag count when a synchronize mode command without data (mc1) is received. in addition, the host can reset the time-tag count at any time by asserting the rttag bit in confguration register 2. the mcopt2 and mcopt3 bits in confguration register 2 allow automatic loading of time-tag count using the data word received with a synchronize with data mode command, mc17. if both of these bits equal one, the data word received with a valid synchronize mode command (mc17) is unconditionally loaded into the time-tag counter. for non-broadcast mc17 commands, the counter load occurs before status word transmission. if both mcopt2 and mcopt3 bits equal 0, the external host assumes responsibility for actions needed to perform synchronize duties upon reception of the valid mc17 synchronize command, but status transmission automatically occurs. the binary 01 and 10 combinations of the mcopt2 and mcopt3 bits support certain extended subaddressing schemes. if the mcopt3-mcopt2 bits equal 01, the received data word is automatically loaded into the time-tag counter if the low order bit of the received data word (bit 0) equals 0. if the mcopt3-mcopt2 bits equal 10, the re - ceived data word is automatically loaded into the time-tag counter if the low order bit of the received data word (bit 0) equals 1. for non-broadcast mc17 commands, the counter load occurs before status word transmission.
HI-6120, hi-6121 holt integrated circuits 35 5.10. interrupt log address register (0x0009) this 16-bit register is read-only and is fully maintained by HI-6120/21 logic. the register contains 0x0040 after mr pin master reset but is not affected by srst software reset. bits 7:0 contain an address pointer for the 32-word interrupt log buffer located in shared ram. the value in interrupt log address register bits 7:0 indicates the storage address where interrupt information words will be stored for the next occurring interrupt, 0x40 - 0x5e. the value is always even since two words are stored for each interrupt. bits 15:8 contain a count value for the number of interrupts logged (0 - 255) since the interrupt log address register was last read. the count increment stops at 255. bits 15:8 are reset automatically after this register is read by the host. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb interrupt log address 7:0 c c c c c c c c 0 1 0 a a a a 0 interrupt count 7:0 to help the host process interrupts, the device maintains information from the 16 most recent interrupts in a 32-word ring buffer in shared ram, found at address range 0x0040 to 0x005f. each interrupt stores two information words: the interrupt identifcation word (iiw) identifes the interrupt type(s) that occurred; the interrupt address word (iaw) identifes the interrupt source. for interrupts that result from message processing, the iaw contains the 16-bit address of the commands control word in the descriptor table. for hardware interrupts, the iaw value is 0x0000. after mr master reset, the device automatically resets this register to 0x0040, an interrupt count of zero and log ad - dress of 0x40. during terminal operation, the host can read bits 15:8 to see the number of interrupts logged in the buffer since the last read operation upon the register. information words for the sixteenth interrupt are stored in buffer addresses 0x005e and 0x005f, and the interrupt log address rolls over to read 0x40, where interrupt information for the seventeenth interrupt will be stored. for further information on interrupts, see descriptions for the interrupt enable register, the pending interrupt register, and see the later section entitled interrupt management. 5.11. current message information word address register (0x000a) this 16-bit register is read-only and is fully maintained by the device. this register is cleared after mr pin master reset, but is not affected by srst software reset. also see current control word address register, 0x0004. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb current msg info word address 15:0 a a a a a a a a a a a a a a a a note: reset refers to bit value following master reset ( mr ). this register is unaffected by software reset. bit no. mnemonic r/w reset function 15-0 miwa15:0 r/w 0 current message information word address register this register contains the data buffer address for the last commands mes - sage information word, or miw, corresponding to the current command stored in the current command register (0x0003). this register is updated 5us after the active output is asserted. bit 15 is msb.
HI-6120, hi-6121 holt integrated circuits 36 5.12. memory address pointer register (hi-6121 only) (0x000f) this register is read-write and is cleared after mr pin master reset, but is not affected by srst software reset. this register is maintained by the host. the contained value is a memory address used when fulflling ram or register read or write operations via the hi-6121 serial peripheral interface (spi). see data sheet section, host serial peripheral interface (spi) for further details. for HI-6120 devices, writes to this address have no effect; the address reads back 0x0000 if a host read cycle occurs. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb memory address 15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5.13. interrupt enable register (0x0010) this 16-bit register is read-write (except bits 2-0 are read only) and is fully maintained by the host. all bits are active high. for further information on interrupts, see descriptions for the pending interrupt and interrupt log address regis - ters, and refer to the later section entitled interrupt management. ilcmd ibr iwa merr eeckf msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ixeqz rtapf x x rami f x lbfa spifail lbfb ttint1 ttint0 1 1 1 an interrupt type is globally disabled when the corresponding bit in this register is reset. this allows the external host or subsystem to temporarily disable interrupt servicing for some or all interrupts. while an interrupt enable bit is ne - gated, the terminal does not generate an interrupt output signal for the corresponding interrupt event. note: asserting an interrupt bit in this register after an event occurs does not generate an interrupt for that event. for some interrupts that result from message processing, interrupt enable bits in a each commands descriptor control word act in combi - nation with settings in this register to respond appropriately to interrupt-causing events. note: reset refers to bit value following master reset ( mr ). this register is unaffected by software reset. bit no. mnemonic r/w reset function 15 ixeqz r/w 0 index equal zero interrupt. when this bit is asserted, interrupts are globally enabled for (a) subad - dresses using indexed buffer mode when the index decrements from 1 to 0, and (b) subaddresses using a circular buffer mode when the pre-deter - mined number of messages has been transacted. when this bit is assert - ed, occurrence of an ixeqz event (a) or (b) causes intmes output asser - tion (if the ixeqz bit is set in the commands descriptor control word). 14 iwa r/w 0 interrupt when accessed interrupt. when this bit is asserted, interrupts are globally enabled for each message occurrence to subaddresses in which the descriptor control word allows the iwa interrupt. when this bit is asserted, occurrence of an iwa event causes intmes output assertion (if the iwa bit is set in the commands descriptor control word).
HI-6120, hi-6121 holt integrated circuits 37 bit no. mnemonic r/w reset function 13 ibr r/w 0 broadcast command received interrupt. when this bit is asserted, interrupts are globally enabled for each broad - cast message to subaddresses in which the descriptor control word allows the ibr interrupt. when this bit is asserted, occurrence of an ibr event causes intmes output assertion (if the ibr bit is set in the com - mands descriptor control word). 12,11 ----- r/w 0 not used. 10 merr r/w 0 message error interrupt. when this bit is high, the intmes interrupt output is asserted when a mes - sage error is detected. errors are caused by manchester encoding prob - lems or protocol errors. interrupt assertion occurs whenever the terminal sets the me message error bit in the terminals status word. the detected error type can be found in message information word stored as a result of message processing. 9 ----- r/w 0 not used. 8 ilcmd r.w 0 illegal command interrupt. illegal commands are defned in the illegalization table. when enabled, the ilcmd interrupt is asserted when the illegalization table bit corresponding to the received command is logic 1. the illegalization table should only contain nonzero values when illegal command detection is being applied. when illegal commands are received, the terminal responds by transmitting status word with me message error fag set; no data words are transmitted. if this ilcmd bit is high, all illegal commands cause intmes interrupt output assertion. see next section entitled pending interrupt register (below) and the section entitled illegalization table for further information. 7 spifail r.w 0 spi fail interrupt (hi-6121 only). the hi-6121 uses a spi interface for host access. the device operates in spi slave mode. when this bit is high, the inthw output is asserted and the interrupt log is updated each time an incorrect number of sck clocks occurs during spi chip select assertion. 6,5 lbfa, lbfb r/w 0 loopback fail bus a and loopback fail bus b interrupts. during all transmitted command responses, the device compares words transmitted to the received and decoded words detected on the bus. when this bit is high, the intmes output is asserted and the interrupt log is updated each time loopback detects word mismatch. 4 ttint1 r/w 0 time-tag interrupt 1. if this bit is logic 1, the inthw interrupt output is asserted and the ttint1 bit is set in the pending interrupt register each time the free-running time- tag counter value matches the value stored in the time-tag utility regis - ter.
HI-6120, hi-6121 holt integrated circuits 38 bit no. mnemonic r/w reset function 3 ttint0 r/w 0 time-tag interrupt 0. if this bit is logic 1, the inthw interrupt output is asserted and the ttint0 bit is set in the pending interrupt register each time the free-running time- tag counter value rolls over from 0xffff full count to 0x0000. 2 rtapf r 1 rt address parity fail interrupt. when this bit is high, the inthw interrupt is asserted when rt address parity error is detected. this bit is 1 after mr master reset and cannot be reset by host register write. 1 eeckf r 1 initialization eeprom checksum fail interrupt. when this bit is high, the inthw interrupt is asserted if serial eeprom checksum failure occurs during auto-initialization. this bit is 1 after mr master reset and cannot be reset by host register write. 0 ramif r 1 ram initialization fail interrupt. when this bit is high, the inthw interrupt is asserted after auto-initializa - tion if an initialized ram location does not match its 2 corresponding serial eeprom locations. this bit is 1 after mr master reset and cannot be reset by host register write. the interrupt enable register lets the host temporarily or permanently disable interrupt servicing for some or all in - terrupt types. when bits are reset in this register, interrupt output signals are globally disabled for the corresponding interrupt types. asserting a bit in the interrupt enable register after an event occurs does not generate an interrupt for that event. the ixeqz, iwa and ibr interrupts result from message processing. the host can enable or disable these three interrupt types for individual subaddresses and mode code commands by setting or resetting the ixeqz, iwa and ibr bits in descriptor table control words corresponding to each subaddress or mode command. while the ilcmd and merr interrupts also result from message processing, these interrupts (along with all hardware interrupts) are globally enabled or disabled, and are unaffected by descriptor table settings. table gives a summary of settings and responses to interrupt-causing messages. table 5. settings and responses to interrupt-causing messages setting response descriptor control word ixeqz, iwa & ibr bits interrupt enable register bit for interrupt type effect on corresponding bit in pending interrupt register is interrupt output signal generated reset set set dont care reset set no change no change pending int. register bit is set no no yes all interrupts except ixeqz, iwa & ibr (no control word bits) reset set no change pending int. register bit is set no yes 5.14. time-tag utility register (0x0011) this 16-bit register is read-write and is fully maintained by the host. this register is cleared after mr pin master reset, but is not affected by srst software reset. this register has two functions associated with the free-running time-tag counter:
HI-6120, hi-6121 holt integrated circuits 39 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb time-tag utility15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 function 1: when confguration register 2 is written causing a 0 to 1 transition of the ttload bit, the value contained in the time-tag utility register is loaded into the time-tag counter. function 2: if the ttint1 bit in the interrupt enable register is set, the interrupt pending register ttint1 bit is set and the inthw interrupt output is asserted each time the free-running time-tag counter value matches the value stored in the time-tag utility register. 5.15. bus a select register (0x0012) this 16-bit register is read-write and is fully maintained by the host. this register is cleared after mr pin master reset, but is not affected by srst software reset. the bus a select register is only used when the mcopt4 bit in confguration register 2 equals 0. this mcopt4 setting means the device automatically fulflls mode commands mc20 (decimal) selected transmitter shutdown or mc21 override selected transmitter shutdown. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb bus a select register15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmitter shutdown or shutdown override can only occur for the inactive bus. if either mode command is received on bus b, the inactive bus is bus a. the device compares the received mode data word to the contents of the bus a select register to determine whether inactive bus a is selected for transmitter shutdown or transmitter shutdown override. (bus shutdown or shutdown override can only occur for the inactive bus.) if the data word matches the value stored in the bus a select register and mcopt4 equals 0, the device automatically fulflls mc20 transmitter shutdown or mc21 shutdown override without host assistance: if the mode command received was mc20, the transmit shutdown a bit in the built-in test (bit) word is asserted. if mode command mc21 was received, the transmit shutdown a bit in the bit word is negated. refer to confguration register 2 description of mcopt4 bit for additional details. 5.16. bus b select register (0x0013) this 16-bit register is read-write and is fully maintained by the host. this register is cleared after mr pin master reset, but is not affected by srst software reset. the bus b select register is only used when the mcopt4 bit in confguration register 2 equals 0. this mcopt4 setting means the device automatically fulflls mode commands mc20 (decimal) selected transmitter shutdown or mc21 override selected transmitter shutdown. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb bus b select register15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit shutdown or shutdown override can only occur for the inactive bus. if either mode command is received on bus a, the inactive bus is bus b. the device compares the received mode data word to the contents of the bus b select register to determine whether inactive bus b is selected for transmitter shutdown or transmitter shutdown override. if the data word matches the value stored in the bus b select register and mcopt4 equals 0, the device automatically fulflls mc20 transmit shutdown or mc21 shutdown override without host assistance: if the mode
HI-6120, hi-6121 holt integrated circuits 40 command received was mc20, the transmit shutdown b bit in the built-in test (bit) word is asserted. if mode com - mand mc21 was received, the transmit shutdown b bit in the bit word is negated. refer to confguration register 2 description of mcopt4 bit for additional details. 5.17. built-in test word register (0x0014) bits 4-11 in this 16-bit register are read-write, the remaining bits are read-only. the ten assigned bits are written by the device when predetermined events occur. the host may overwrite the device-written bits 5 and 4. after mr pin master reset, bits 13-12, 5-4 and 0 are reset. bits 15-14 will be set if the corresponding txinha or txinhb input pins are high. bits 3-1 will be set if rt address parity error, or post- mr memory test or auto-initialization failure occurred. bmtf rxbsd msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rxasd rtapf tfbinh unassigned bits are user defined eelf blbfb blbfa txbsd txasd if the altbitw option bit in confguration register 2 is zero when a valid transmit bit word mode command (mc19) is received, the current value in this register is transmitted as the mode data word in the terminal response. the value is also copied to the assigned data buffer for mc19, after mode command fulfllment. note: reset refers to bit value following master reset ( mr ). the value pin denotes the bit is set to the value of the corresponding pin following master reset. the bit value following software reset is unchanged unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 14 txasd txbsd r pin sr = pin transmitter a shutdown. transmitter b shutdown. these read-only bits are set when the corresponding bus transmitter was disabled by assertion of the bus txinha or txinhb input pin, or by fulfll - ment of a transmitter shutdown mode command mc4 or mc20. refer to the description for the sdsel bit in confguration register 1 and the de - scription for the mcopt4 bit in confguration register 2 for further informa - tion. 13 12 rxasd rxbsd r 0 sr = 0 receiver a shutdown. receiver b shutdown. these read-only bits are set when the corresponding bus receiver was disabled concurrently with the bus transmitter by a transmitter shutdown mode command mc4 or mc20. refer to the description for the sdsel bit in confguration register 1 and the description for the mcopt4 bit in confgu - ration register 2 for further information. 11-6 ----- r/w 0 user defned. host can write any value. 5 blbfa r 0 sr = 0 built-in-self-test (bist) loopback fail bus a (see section 5.20). this bit is set if bus a loopback failure error occurs during built-in self-test. 4 blbfb r 0 sr = 0 bist loopback fail bus b (see section 5.20). this bit is set if bus b loopback failure error occurs during built-in self-test
HI-6120, hi-6121 holt integrated circuits 41 bit no. mnemonic r/w reset function 3 bmtf r test result bist memory test fail (see section 5.20). this bit is set if error occurs during built-in self-test for device ram memory . 2 rtapf r test result rt address parity failure. this bit is asserted when operational status register bits 15:10 refect parity error. after mr master reset, bits 15:10 in the operational status register refect input pin states, but will be overwritten if subsequent auto-initialization is performed (if autoen pin is high) and the initialization eeprom contains different data for operational status register bits 15:10. 1 eelf r test result auto-initialization eeprom load fail. this bit only applies when auto-initialization is enabled (autoen input pin state equals 1). this bit is set if, after mr master reset, failure occurs when copying serial eeprom to registers and ram. when this occurs, bit 0 or bit 1 will be set in the operational status register (0x0002) to indicate type of failure. 0 tfbinh r 0 sr = 0 terminal flag bit inhibited. this bit is set when the terminal flag status bit is disabled while fulflling an inhibit terminal fag bit mode code command (mc6). this bit is reset if terminal fag status bit disablement is later cancelled by an override inhibit terminal fag bit mode code command (mc7). 5.18. alternate built-in test word register (0x0015) this 16-bit register is read-write and is fully maintained by the external host. this register is cleared after mr pin master reset but is unaffected by srst software reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb alternate built-in test word register15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 if the altbitw option bit in confguration register 2 equals one when a valid transmit bit word mode command (mc19) is received, the current value in this register is transmitted as the mode data word in the terminal response. the value is also copied to the assigned data buffer for mc19, after mode command fulfllment. 5.19. reserved register (0x0016) register 0x0016 is used for factory testing. it is cleared after mr pin master reset and cannot be written by the host while the test input pin is low. 5.20. test control register (0x0017) this register controls ram built-in self-test, and transceiver loopback testing. bits 0, 1, 8, 9 are read only. the re - maining bits in this register are read-write but can be written only when the test input pin is high. if test = 0, these bits will read back 0x0000.
HI-6120, hi-6121 holt integrated circuits 42 this register supports two types of test: register bits 15 - 8 are used for ram built-in self test (ram bist). register bits 7 - 2 are used for transceiver loopback testing (either digital loopback or analog loopback). rbfail rbsel2 rbffail rbstrt msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 frama rbsel1 rbsel0 rbpass lbstart lbpass lbfail lbbusel lbalog lbsync 0 0 under internal logic control, this device uses one ram self test (inc / dec test described below) to check internal ram memory after mr pin master reset. test control register bits 15 - 8 provide a means for the host to perform ram self-test at other times. register bits 13:11 select ram test type. then bit 10 starts the selected ram test, and bits 9-8 report a pass/fail result after test completion. all tests are destructive, overwriting data present before test com - mencement. note: reset refers to bit value following either master reset ( mr ) or software reset. bit no. mnemonic r/w reset function 15 frama r/w 0 full ram access enable. during normal operation, some bits in certain ram locations (e.g., descrip - tor table control words) cannot be written by the host. when the frama bit is asserted, host writes to ram are unrestricted to permit full testing. during normal completion, this bit must be reset to logic 0. 14 rbffail r/w 0 ram bist force failure. when this bit is asserted, ram test failure is forced to verify that ram bist logic is functional. 13,12,11 rbsel2:0 r/w 0 ram bist select bits 2-0. this 3-bit feld selects the ram bist test mode applied when the rb - start bit is set: rbsel2:0 selected ram test test time 000 idle - 001 pattern test, described below 14.42ms 010 write 0x0000 to ram address range 0x0000 - 0x7fff 170s 011 read and verify 0x0000 over ram address range 0x0000 - 0x7fff 500s 100 write 0xffff to ram address range 0x0000 - 0x7fff 170s 101 read and verify 0xffff over ram address range 0x0000 - 0x7fff 500s 110 inc / dec test performs only steps 5 - 8 of the pat - tern test below 1.32ms 111 idle -
HI-6120, hi-6121 holt integrated circuits 43 bit no. mnemonic r/w reset function 13,12,11 rbsel2:0 (continued) r/w 0 description of the ram bist pattern test selected when register bits rbsel2:0 = 001: note: test read /write accesses to addresses 0x0000 - 0x001f involve 32 ram locations not accessible to the host. these accesses do not affect the host-accessible registers, overlaying the same address range. 1. write 0x0000 to all ram locations, 0x0000 through 0x7fff. 2. repeat the following sequence for each ram location from 0x00000 through 0x7fff: a. read and verify 0x0000 b. write then read and verify 0x5555 c. write then read and verify 0xaaaa d. write then read and verify 0x3333 e. write then read and verify 0xcccc f. write then read and verify 0x0f0f g. write then read and verify 0xf0f0 h. write then read and verify 0x00ff i. write then read and verify 0xff00 j. write 0x0000 then increment ram address and go to step (a) 3. write 0xffff to all ram locations, 0x0000 through 0x7fff 4. repeat the following sequence for each ram location from 0x00000 through 0x7fff: a. read and verify 0xffff b. write then read and verify 0x5555 c. write then read and verify 0xaaaa d. write then read and verify 0x3333 e. write then read and verify 0xcccc f. write then read and verify 0x0f0f g. write then read and verify 0xf0f0 h. write then read and verify 0x00ff i. write then read and verify 0xff00 j. write 0xffffthen increment ram address and go to step (a) 5. write each cells memory address into each ram location from 0x00020 to 0x7fff. 6. read each memory location from 0x00000 to 0x7fff and verify it con - tains its address. 7. write 1s complement of each cells memory address, into each ram location (same addr range). 8. read each memory location and verify it contains the 1s complement of its address. 10 rbstrt r/w 0 ram bist start. writing logic 1 to this bit initiates the ram bist test selected by register bits rbsel2:0. the rbstrt bit can only be set if the test input pin is high and if register bit 15 is already asserted. this bit is automatically cleared upon test completion. register bits 9-8 indicate pass / fail test result.
HI-6120, hi-6121 holt integrated circuits 44 bit no. mnemonic r/w reset function 9 rbpass r 0 ram bist pass. device logic asserts this bit when the selected ram test completes without error. this bit is automatically cleared when rbstrt bit 10 is set. 8 rbfail r 0 ram bist fail. device logic asserts this bit when failure occurs while performing the selected ram test. this bit is automatically cleared when rbstrt bit 10 is set. when bist failure occurs, a clue to the failing ram address can be read at register address 0x001e. for speed, the ram bist concur - rently tests 4 quadrants of the ram address range, in parallel. if test failure occurs, register address 0x001e contains the ram address be - ing tested in the lowest ram quadrant. actual failure will occur in any of these four locations: at ram address addr stored in register 0x001e, or addr+0x2000, or addr+0x4000 or addr+0x6000. 7,6 ----- r 0 not used. these bits cannot be set. a read will return 0x0000. 5 lbalog r/w 0 loopback test analog. the device supports either digital or analog loopback testing for either bus transceiver. when the lbalog bit is low, digital loopback is selected and no data is transmitted onto the selected external mil-std-1553 bus. when the lbalog bit is high, analog loopback is selected and a test word is transmitted onto and received from the selected external mil-std-1553 bus. 4 lbsync r/w 0 loopback test word sync select. when the lbsync bit is high, the loopback test word is transmitted with command sync. when the lbsync bit is low, the loopback test word is transmitted with data sync. 3 lbbusel r/w 0 loopback test bus select. when this bit is low, loopback testing occurs on bus a. when this bit is high, loopback testing occurs on bus b. 2 lbstart r/w 0 loopback test start. writing logic 1 to this bit initiates the loopback test selected by register bits 3, 4 and 5. the lbstrt bit can only be set if the external test pin is al - ready asserted, and is automatically cleared upon test completion. register bits 1,0 indicate pass / fail test result. 1 lbpass r 0 loopback test pass. device logic asserts this bit when the selected ram test completes without error. this bit is automatically cleared when lbstart bit 2 is set. 0 lbfail r 0 loopback test fail. device logic asserts this bit when failure occurs while performing the selected loopback test. failure is comprised of manchester encoding error , parity error, wrong sync type or data mismatch. this bit is automatically cleared when lbstart bit 2 is set.
HI-6120, hi-6121 holt integrated circuits 45 5.21. loopback test transmit data register (0x0018) this 16-bit register is read-write and is fully maintained by the host. this register is cleared after mr pin master reset, but is not affected by srst software reset. the value contained in this register is used when performing digital loopback testing. see test control register, 0x0016, for additional information. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb loopback test transmit data register15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5.22. loopback test receive data register (0x0019) this 16-bit register is read-only. this register is cleared after mr pin master reset, but is not affected by srst software reset. data is written to this register when performing digital loopback testing. see test control register, 0x0016, for additional information. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb lsb loopback test receive data register15:0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HI-6120, hi-6121 holt integrated circuits 46 to mode code commands by the mode code number. for example, a mode command with 5-bit mode code feld of 0x10 is called mc16, and the full range of mode code values is mc0 through mc31 (decimal). mode codes mc16 through mc31 (0x10 through 0x1f) have a single associated data word. when the command t/ r bit equals 0, the data word is contiguous with the command word and received by the rt. when the com - mands t/ r bit equals 1, the data word is transmitted by the rt, following the terminals transmitted status word. mode codes mc0 through mc15 (0x0f) do not have as - sociated data words. for these 16 commands, the com - mand t/ r bit does not specify direction. these com - mands must be transmitted with t/ r bit equal to 1. if the t/ r bit is 0, the mode command is undefned. twenty-two mode commands are undefned mode com - mands in mil-std-1553b: mode codes 0 through 15 with t/r bit = 0 mode codes16, 18 and19 with t/r bit = 0 mode codes 17, 20 and 21 with t/r bit = 1 the umcinv bit in confguration register 1 determines how these undefned mode commands are handled by the HI-6120/21. if the umcinv confguration bit equals 1, the undefned mode commands are treated as invalid. they are not recognized by the device. there is no terminal response and status is not updated. if the umcinv confguration bit equals 0, the 22 undefned mode commands are considered valid; this is the default condition following reset. for this case, terminal response depends on whether or not the application uses illegal command detection. if illegal command detection is not used , all illegaliza - tion table entries should be logic 0, including the 22 en - tries for these undefned commands. (the illegalization table is fully described in section 7 on page 48. after mr reset, all entries equal logic 0.) the terminal responds in form, transmitting clear status (and a single mode data word if the command is mc17, mc20 or mc21 with t/ r bit = 1). terminal status is updated. if illegal command detection applies, the illegalization table entries for these 22 undefned commands should be initialized to logic 1. in this case, the terminal will re - spond with status word only, with message error bit set. no mode data word is transmitted. terminal status is up - dated. twenty-seven mode codes are considered reserved in mil-std-1553b: 6. command responses a brief review of mil-std-1553 commands and re - sponses is appropriate here to establish terminology used in the rest of this data sheet. shown in figure 3, each command word is comprised of a sync feld, three 5-bit data felds, a single bit denoting transmit / receive direction and ends with a parity bit. the hardware de - coder uses the sync feld to determine word type (com - mand vs. data). word validity is based on proper sync encoding, manchester ii encoding, correct bit count and correct odd parity for the 16 data bits. once a valid word with command sync is found, the sync and parity are stripped before the commands 16 data bits are stored for further processing. command sync terminal address field subaddress (sa) field word count field * t/ r bi t parity bit * word count field is replaced by mode code field when the sa field equals 0x00 or 0x1f figure 3. mil-std-1553 command word structure a valid command can be specifcally addressed to the individual HI-6120 terminal (the command words em - bedded terminal address feld matches the terminal address latched in the operational status register) or can be a broadcast command addressed to all termi - nals. broadcast commands are always addressed to rt address 31 (0x1f). in systems where broadcast com - mands are disallowed, rt31 is not used as a conven - tional terminal address. when set, the bcstinv bit in confguration register 1 renders rt31 commands as invalid: broadcast commands are indistinguishable from commands addressed to other terminals. invalid commands are simply disregarded. when the command words 5-bit sa (subaddress) feld is in the range of 1 to 30 (0x01 to 0x1e) the command is considered a subaddress command. the terminal will either receive or transmit data words, and direction is specifed by the commands t/ r bit. the number of data words transacted is specifed in the 5-bit word count feld, ranging from 1 to 32 words. thirty-two data words is represented when the word count feld equals 0x00. when the commands 5-bit subaddress feld equals 0 or 31 (0x1f) a mode code command is indicated; the low order fve bits no longer specify a word count, instead they convey a mode code value. this data sheet refers
HI-6120, hi-6121 holt integrated circuits 47 mode codes 9 through 15 with t/r bit = 1 mode codes 22 through 31 with t/r bit = 1 mode codes 22 through 31 with t/r bit = 0 treatment of these reserved mode commands depends on their respective illegalization table entries. as de - scribed above for undefned mode commands, response depends on whether or not illegal command detection applies. any mode commands not implemented in the HI-6120/21 terminal should be treated the same as reserved mode commands. for example, command mc0 (with t/ r = 1) is probably unimplemented because the HI-6120 does not have provisions for accepting dynamic bus control. the important point is that illegal command detection should be universally applied (or not applied) when set - ting up a HI-6120/21 remote terminal application. here are the two options: not using illegal command detection. the HI-6120/21 illegalization table is left in its default state (all locations equal to mr post-reset 0x0000). the terminal responds in form to all valid commands, whether legal or illegal. using illegal command detection. the HI-6120/21 il - legalization table is initialized by the host to implement illegal command detection. the host sets bits for all illegal commands. this generally includes the reserved and unimplemented mode commands, unimplemented subaddresses (or specifc word counts, t/ r bit states, and/or broadcast vs. non-broadcast status within subad - dresses). treatment for the undefned mode commands depends on umcinv bit. the host defnes terminal response for all individual commands by initializing the descriptor table, fully de - scribed later. at this point, a few comments about the descriptor table are appropriate. the command sa (subaddress) feld has a range of 0 to 31 (0x1f). when sa is in the range 1 to 30 (0x1e), the command is a transmit or receive subaddress com - mand. the number of data words transmitted or re - ceived is expressed in the low order 5 bits. when sa equals 0 or 31 (0x1f) the command is a mode com - mand and the mode code value is expressed in the low order 5 bits. for each subaddress, separate table descriptor blocks for transmit and receive commands permit different data buffering to be applied. the host initializes the table so each transmit-subaddress and each receive-subad - dress uses one of four methods for storing message data. during table initialization, memory is allocated in shared ram for storing message data according to the application requirements. each transmit-subaddress and receive-subaddress has one or more data pointers (depending on buffer method) addressing its reserved data buffer(s). each mode command also has its own table descrip - tor block. mode commands have either one data word or no associated data words. descriptor words used as data pointers by subaddress commands are in - stead used for direct storage of transacted mode data words. mode commands that transmit or receive mode data words have a dedicated storage address range in shared ram, eliminating the need for descriptor table data pointers. each mode command with mode data word has its own fxed address for data storage. this includes reserved mode codes with data word. thus the HI-6120/21 can respond consistently for all mode commands; transmit - ted data values for in form responses (when illegal command detection is not used) can be predetermined, even for the reserved mode commands. 6.1. rt to rt commands. the mil-std-1553 standard allows for data word trans - mission from a specifed transmitting terminal to a dif - ferent receiving terminal. when broadcast commands are allowed, data transmission can be addressed to the broadcast terminal address, rt31. if broadcast is allowed, the host should initialize the bcstinv (broad - cast invalid) bit in confguration register 1 to logic 0. all rt to rt commands are characterized by a pair of contiguous command words: command word 1 is a receive command addressed to the intended receiving terminal, then command word 2 is a transmit command addressed to a single transmitting terminal. command word 2 cannot be broadcast address rt31. the HI-6120 automatically detects and handles rt to rt commands, except when either command word contains a subad - dress feld equal to 0x0 or 0x1f. either subaddress val - ue indicates a mode code command; the device treats rt to rt commands with mode code as invalid. if either rt-rt command word is addressed to the HI-6120/21 terminal but contains subaddress 0x0 or 0x1f, the com - mand is not recognized; there is no rt command re - sponse, and no status updating for the beneft of follow - ing transmit status or transmit last command mode commands. when either rt-rt command word (with subaddress feld not equal to 0x0 or 0x1f) is addressed to the hi- 6120/21 terminal, but the other command word contains subaddress 0x0 or 0x1f, the rt-rt command is not rec - ognized as valid. there is no rt command response,
HI-6120, hi-6121 holt integrated circuits 48 and no status updating for the beneft of following trans - mit status or transmit last command mode commands. an rt-rt command pair where command word 1 is addressed to the HI-6120/21 terminal and command word 2 is addressed to a different terminal is considered an rt-rt receive command. when the message is transacted, the device sets the rtrt bit in the receive subaddress message information word in the subad - dress data buffer. an rt-rt command pair where command word 2 is solely addressed to the HI-6120/21 terminal (not rt31) is considered an rt-rt transmit command. the mes - sage information word does not distinguish the rt to rt transmit message from an ordinary rt to bc trans - mit command. 7. command illegalization table the following pages describe various structures resid - ing in the ram shared between the host and HI-6120 or hi-6121 command processing logic. the host initializes these structures to control the terminals response to re - ceived commands. the frst structure described is the command illegalization table used for illegal command detection. illegal command detection is an optional process. when illegal command detection is not used, the terminal re - sponds in form to all valid commands: it sends clear status and transacts the number of data words defned in the received command. when illegal command detec - tion is not used, the bus controller cannot tell whether the command is legal or illegal, from the terminals trans - mitted response. if illegal command detection is used, the terminal re - sponds differently when an illegal command is detected. the terminal responds to illegal commands with mes - sage error status, transmitting only status word. data word transmission is suppressed if the command type inherently includes transmitted data words. the terminal responds to each legal command with clear status and transacts the number of data words defned in the type of command received. for consistency, apply illegal command detection to all illegal and unimplemented commands, and to all re - served or undefned mode code commands, or respond in form to all of these commands (illegal command de - tection disabled) by leaving the illegalization table in the all-cleared default state after mr master reset the device uses a 256-word illegalization table in shared ram to distinguish between legal and illegal commands. after the ( mr ) master reset input is negated, HI-6120/21 performs internal self test including a shared ram test which leaves all memory locations fully reset. once self test is complete, the HI-6120/21 ready out - put goes high to indicate HI-6120/21 readiness for host initialization. at this point, all entries in the illegalization table read logic 0, so by default, illegal command detec - tion is not applied. to apply illegal command detection, the host (or auto- initialization) writes the illegalization table to set bits for all illegal command combinations. this typically includes any unimplemented subaddresses and/or word counts, undefned mode commands, reserved mode commands and any mode commands not implemented in the ter - minal design. host initialization of the table can be re - placed by auto-initialization. once stex is set in confguration register 1, terminal execution begins. each time a valid command is re - ceived, a 1-bit entry (indexed using command word data bits) is fetched from the illegalization table: if fetched illegalization table bit equals logic 0, the command is legal; the terminal responds in form, transmitting clear status and transacting the number of data words defned for the message type. terminal sta - tus is updated. if fetched illegalization table bit equals logic 1, the command is illegal; the terminal responds with status word only, with message error bit set. no data words are transmitted. terminal status is updated. when illegal command detection is not applied, all table entries should read logic 0; the terminal responds in form to all valid commands. the illegalization scheme allows any subset of command t/ r bit, broadcast vs. non-broadcast status, subaddress and word count (or mode code number), for a total of 4,096 legal/illegal command combinations. commands may be illegalized down to the word count level. for ex - ample, 10-word receive commands to a given subad - dress may be legal, while 9-word receive commands to the same subaddress are illegal. broadcast receive commands are illegalized separately from non-broadcast receive commands. transmit and receive commands for the same subaddress are illegal - ized separately. for mode commands, any combination of mode code number, t/ r bit and broadcast/non-broad - cast status can be legal or illegal. the illegalization table is located in shared ram within
HI-6120, hi-6121 holt integrated circuits 49 the fxed address range of 0x0100 to 0x01ff. see fig - ure 4. the table is comprised of 256 16-bit words. to cover the full range of 1 to 32 data words, each subad - dress uses a pair of illegalization registers. the lower register (even memory address) covers word counts 0 to 15, using one bit per word count. as in command encod - ing, 0 denotes 32 data words. bit 0 corresponds to 32 data words, bit 1 corresponds to 1 data word and bit 15 corresponds to 15 data words. the upper register (odd memory address) similarly covers word counts 16 to 31, using one bit per word count. bit 0 corresponds to 16 data words, while bit 15 corresponds to 31 data words. when a commands subaddress feld equals 0 or 31 (0x1f), the command is a mode command. table en - tries for mode commands use bits to represent mode code numbers, not word counts. the lower register (even memory address) covers mode codes 0 to 15, us - ing one bit per mode code. bit 0 corresponds to mode code 0, bit 15 corresponds to mode code 15. the upper register (odd memory address) similarly covers mode codes 16 to 31, using one bit per mode code. bit 0 cor - responds to mode code 16, bit 15 corresponds to mode code 31. there is no functional difference between sa0 mode commands and sa31 mode commands. since either subaddress indicates a mode command, the sub - address 0 table words should match the subaddress 31 table words in each quadrant. table entries from 0x0142 to 0x017d do not have to be programmed. these correspond to broadcast transmit subaddress commands (undefned by mil-std-1553b) and are always invalid. there is no terminal response. addressing for the illegalization table is derived from the command word t/ r bit, subaddress feld, msb of the word count (mode code) feld and the commands broadcast vs. non-broadcast status as shown below in figure 4. terminal address ta4:0 subaddress sa4:0 word count (mode code) wc4:0 t/ bi t r 0 0 0 0 0 0 0 1 0 if ta4:0 = 11111 else 1 wc4 t/r sa4 sa3 sa2 sa1 sa0 table address bit fields comprise each received command word p command sync figure 4. deriving the illegalization table address from the received command word figure 6 shows individual bit locations in the illegaliza - tion table for broadcast and non-broadcast variants of all mode commands defned by mil-std-1553b. loca - tions are also identifed for reserved mode codes and undefned mode code commands. the following examples illustrate how the illegalization table is initialized to distinguish between legal and il - legal commands when illegal command detection is being used. remember: if the terminal does not use il - legal command detection, the table is left in its post- mr reset state, with all table locations reset to 0x0000. in this case, all command responses are in form. for subaddress commands (ordinary receive com - mands or transmit commands) individual table bits cor - respond to word counts specifed in the received com - mand word. if a bit is 0, the corresponding word count is legal. if a bit is 1, the corresponding word count is illegal. for example, transmit commands to subaddress 1 are controlled by the words at 0x01c2 and 0x01c3. in fig - ure 5, these words are located in the rt address trans - mit block. the word stored at 0x01c3 controls subad - dress 1 transmit commands having word counts 16 to 31. the word stored at 0x01c2 controls subaddress 1 transmit commands having word counts 1 to 15 or 32. (reminder: in mil-std-1553b, zero corresponds to 32 words.) word at 0x01c3 (tx subaddr 1) 31 to 16 words bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 word at 0x01c2 (tx subaddr 1) 15 to 1 & 32 words bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32 if the word stored at 0x01c3 = 0xffff and the word stored at 0x01c2 = 0xff0f, then commands with 4, 5, 6, or 7 data words are the only legal transmit commands for subaddress 1 and all other word counts are illegal. receive commands and broadcast receive commands for subaddresses1 through 30 are encoded similarly. for mode code commands (characterized by com - mand word subaddress feld equal to 00000 or 11111 bi - nary) individual table bits correspond to individual mode code values. here transmit and receive simply indi - cate the state of the command word t/ r bit. (for mode codes 0-15, the t/ r bit does not indicate data direction since data is not transacted when fulflling these com - mands).
HI-6120, hi-6121 holt integrated circuits 50 rt address tx mode codes 15 - 0 rt address tx mode codes 31 - 1 6 0x01c1 0x01c0 rt address rx mode codes 15 - 0 rt address rx mode codes 31 - 1 6 0x0181 0x0180 broadcast tx mode codes 15 - 0 broadcast tx mode codes 31 - 1 6 0x0141 0x0140 broadcast rx mode codes 15 - 0 broadcast rx mode codes 31 - 1 6 0x0101 0x0100 0x01ff 0x01c0 0x01bf 0x0180 0x017f 0x0140 0x013f 0x0100 broadcast transmit quadrant 32 subaddress blocks of 2 words each sa1 to sa30 are illegal broadcast transmit! rt addr tx sa30 w ord counts 15 - 0 * rt address tx mode codes 15 - 0 rt addr tx sa30 w ord counts 31 - 1 6 rt address tx mode codes 31 - 1 6 0x01ff 0x01fe 0x01fd 0x01fc example subaddress blocks from each table quadrant illegalization table comprised of 32 2-word blocks per quadrant rt address transmit quadrant 32 subaddress blocks of 2 words each 0x01bf 0x01be 0x01bd 0x01bc 0x017f 0x017e 0x017d 0x017c 0x013f 0x013e 0x013d 0x013c rt addr rx sa30 w ord counts 15 - 0 * rt address rx mode codes 15 - 0 rt addr rx sa30 w ord counts 31 - 1 6 rt address rx mode codes 31 - 1 6 broadcast tx sa30 w ord counts 15 - 0 * broadcast tx mode codes 15 - 0 broadcast tx sa30 w ord counts 31 - 1 6 broadcast tx mode codes 31 - 1 6 broadcast rx sa30 w ord counts 15 - 0 * broadcast rx mode codes 15 - 0 broadcast rx sa30 w ord counts 31 - 1 6 broadcast rx mode codes 31 - 1 6 tx subaddress 31 block (mode codes) tx subaddress 30 block tx subaddress 1 block tx subaddress 0 block (mode codes) rt address receive quadrant 32 subaddress blocks of 2 words each rx subaddress 31 block (mode codes) rx subaddress 30 block rx subaddress 1 block rx subaddress 0 block (mode codes) command sync tx subaddress 31 block (mode codes) tx subaddress 30 block tx subaddress 1 block tx subaddress 0 block (mode codes) rx subaddress 31 block (mode codes) rx subaddress 30 block rx subaddress 1 block rx subaddress 0 block (mode codes) broadcast receive quadrant 32 subaddress blocks of 2 words each * word count = 0 denotes 32 words * word count = 0 denotes 32 words * word count = 0 denotes 32 words * word count = 0 denotes 32 words figure 5. fixed address mapping for illegalization table figure 6 summarizes the 16 illegalization table locations for mode commands. these locations are scattered through -
HI-6120, hi-6121 holt integrated circuits 51 out the overall illegalization table shown in figure 5. remember: the host must initialize all table locations corresponding to both subaddress 0 and subaddress 31 (11111 binary). consider an example in which all reserved and all unde - fned mode commands are illegal. if all defned transmit mode commands are legal except mc0 (dynamic bus control) the eight table entries for transmit mode com - mands would be: 0x01ff and 0x01c1 = 1111 1111 1111 0010 = 0xfff2 0x01fe and 0x01c0 = 1111 1110 0000 0001 = 0xfe01 0x017f and 0x0141 = 1111 1111 1111 1111 = 0xffff 0x017e and 0x0140 = 1111 1110 0000 0101 = 0xfe05 the receive mode command words are encoded simi - larly. continuing the same example where all reserved and all undefned mode commands are illegal: if all de - fned receive mode commands are legal, the eight table entries for receive mode commands would be: 0x01bf and 0x0181 = 1111 1111 1100 1101 = 0xffcd 0x01be and 0x0180 = 1111 1111 1111 1111 = 0xffff 0x013f and 0x0101 = 1111 1111 1100 1101 = 0xffcd 0x013e and 0x0100 = 1111 1111 1111 1111 = 0xffff tx mc3 1 - mc1 6 tx mc1 5 - mc0 rx mc3 1 - mc1 6 rx mc1 5 - mc0 br .tx mc3 1 - mc1 6 br .tx mc1 5 - mc0 br .rx mc3 1 - mc1 6 t ransmit mode commands with data receive mode commands with data t ransmit mode commands without data receive mode commands without data broadcast t ransmit mode commands with data broadcast receive mode commands with data broadcast t ransmit mode commands without data br .rx mc1 5 - mc0 broadcast receive mode commands without data 0x01ff and 0x01c 1 0x01fe and 0x01c 0 0x01bf and 0x0181 0x01be and 0x0180 0x017f and 0x0141 0x017e and 0x0140 0x013f and 0x0101 0x013e and 0x0100 bit no. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r u u d d u d 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r d d d d d d d d d 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 s r r r r r r r r r r d d u u d u 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u u u u u u u u u u u u u u u u d = defined mode command r = reserved mode code u = undefined mode command nb = defined code, but broadcast not allowed mc # status mc # status mc # stat u mc # status legend 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r u u nb nb u n b 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r d d d d d d nb d n b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r r r r r r r r r r d d u u d u 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 u u u u u u u u u u u u u u u u mc # status mc # status mc # status mc # status ram address figure 6. summary of illegalization table addresses for mode code commands
HI-6120, hi-6121 holt integrated circuits 52 8. temporary receive data buffer the 32-word temporary receive data buffer resides in shared ram in address space 0x0020 to 0x003f. the device optionally uses this buffer for temporary storage of receive data words until successful message comple - tion. to enable the buffer, the host asserts the trxdc bit in confguration register 2. when enabled, the terminal stores received data words in the 32-word buffer during message processing. upon error-free message completion, all buffered words are written in a burst to the data buffer memory assigned to the specifc subaddress in the descriptor table. when the trxdb bit in confguration register 2 is ne - gated, the temporary receive data buffer is disabled. at 20us intervals, the terminal writes received data words to assigned subaddress data buffer memory as each word is received. if message error occurs during data reception, data integrity is lost; valid data from the prior receive message may be partially overwritten by data from a message ending in error. mil-std-1553 states that all received data from messages ending in error should be disregarded. in a typical application, the temporary buffer is not di - rectly accessed by the host, although there is no restric - tion preventing host data access. the host should never write data into the temporary buffer space. 9. interrupt log buffer two interrupt output pins notify the host upon occur - rence of pre-determined interrupt-causing events. the interrupt types are listed below. each interrupt type only occurs when the corresponding interrupt type bit is as - serted in the interrupt enable register. to manage host interrupts, the device architecture uses an interrupt log buffer, three control registers, two interrupt output pins and two interrupt acknowledge input pins. the data sheet section entitled interrupt management provides additional details. shown in figure 7, the interrupt log buffer is a 32-word ring buffer located in shared ram, at address range 0x0040 to 0x005f. to help the host process interrupts, the device interrupt manager maintains information from the 16 most recent interrupts in this buffer. the buffer contains two information words for each occurring inter - rupt: the interrupt identifcation word and interrupt ad - dress word. the interrupt identifcation word (iiw) identifes the oc - curring interrupt type using a word format identical to the pending interrupt register. upon update, all bits except the occurring interrupt type bit(s) are reset. table 6. interrupt information word bits summary iiw - interrupt information word iaw - interrupt address word bit interrupt origin 15 ixeqz message iaw contains the command word descriptor table address 14 iwa message 13 ibr message 12 ----- 11 ----- 10 merr message 9 ----- 8 ilcmd message 7 spifail hardware iaw contains 0x0000 6 lbfa hardware 5 lbfb hardware 4 ttint1 hardware 3 ttint0 hardware 2 rtapf hardware 1 eeckf hardware 0 ramif hardware more than one bit may be asserted in an interrupt identi - fcation word. for example, ibr (interrupt broadcast re - ceived) and merr (interrupt message error) can occur for the same message. one assertion of the intmes output pin alerts the host when concurrent message in - terrupts occur. the interrupt address word (iaw) identifes the origi - nating command for message-based interrupts. when interrupts originate from message processing, the inter - rupt address word (iaw) identifes the interrupt source using the 16-bit address of the commands control word in the descriptor table. hardware interrupts are not linked with command processing. these interrupts write an interrupt address word value of 0x0000.
HI-6120, hi-6121 holt integrated circuits 53 after mr reset or srst software reset, the device auto - matically initializes bits 7:0 in the interrupt log address register to the buffers base address, 0x0040. the bit 7:0 value read will always be even, ranging from 0x0040 to 0x005e. once terminal operation begins, the current value of the interrupt log address indicates where the interrupt information word (iiw) for the next occurring interrupt will be stored. on the frst interrupt occurring after reset, the device writes the iiw and iaw to offset locations 00000 and 00001 respectively. the device increments the ring buffer pointer after each word is stored, storing interrupt information sequentially in the ring buffer. information words for the sixteenth interrupt are stored in offset locations 0x1e and 0x1f (buffer addresses 0x005e and 0x005f) and the interrupt log address rolls over to again point to offset location 0 (buffer address 0x0040) where the interrupt information word for the seventeenth interrupt will be stored. bits 15:8 in the interrupt log address register maintain a count of interrupt events since the register was last read. the interrupt count stops at 255 decimal. counts greater than 16 indicate buffer overrun, but the extended count capacity is provided as a diagnostic aid.
HI-6120, hi-6121 holt integrated circuits 54 interrupt log address register is initialized by device logi c t o point to this address after hardwar e r eset (mr) or softwar e r eset 0x0047 0x0046 0x0045 0x0044 0x0043 0x0042 0x0041 0x0040 0x004f 0x004e 0x004d 0x004c 0x004b 0x004a 0x0049 0x0048 0x0057 0x0056 0x0055 0x0054 0x0053 0x0052 0x0051 0x0050 0x005f 0x005e 0x005d 0x005c 0x005b 0x005a 0x0059 0x0058 interrup t 1 interrup t 1 interrupt address w ord interrupt information w ord interrup t 2 interrup t 2 interrupt address w ord interrupt information w ord interrup t 3 interrup t 3 interrupt address w ord interrupt information w ord interrup t 4 interrup t 4 interrupt address w ord interrupt information w ord interrup t 5 interrup t 5 interrupt address w ord interrupt information w ord interrup t 6 interrup t 6 interrupt address w ord interrupt information w ord interrup t 7 interrup t 7 interrupt address w ord interrupt information w ord interrup t 8 interrup t 8 interrupt address w ord interrupt information w ord interrup t 9 interrup t 9 interrupt address w ord interrupt information w ord interrup t 1 0 interrup t 1 0 interrupt address w ord interrupt information w ord interrup t 1 1 interrup t 1 1 interrupt address w ord interrupt information w ord interrup t 1 2 interrup t 1 2 interrupt address w ord interrupt information w ord interrup t 1 3 interrup t 1 3 interrupt address w ord interrupt information w ord interrup t 1 4 interrup t 1 4 interrupt address w ord interrupt information w ord interrup t 1 5 interrup t 1 5 interrupt address w ord interrupt information w ord interrup t 1 6 interrup t 1 6 interrupt address w ord interrupt information w ord the interrupt log address register point s t o t his address afte r i nterrupt 15 event occurs. upon interrupt 16 completion, device logi c r einitializes th e l og address pointer to 0x0040 befor e i nterrupt 17 is processed. address w or d = 0x02f8 descriptor address for tx subaddress 30. * information w or d = 0x4000 iw a (interrupt when accessed) bit = 1 . example 2: iw a t ransmit subaddress 30 control word to generate an interrupt upon each message occurrence. a transmit command is received for subaddress 30: bi t is set in interrupt enabl e register . the iw a b it is set in address w or d = 0x0278 descriptor address for rx subaddress 30. * information w or d = 0x0400 merr (interrupt message error) bit = 1 . example 1: merr bi t is set in interrupt enabl e register . an error occurs while transactin g a receive command for subaddress 30: address w or d = 0x0300 descriptor address for rx mode code 0. * information w or d = 0x0100 ilcmd (interrupt illegal command) bit = 1 . example 3: ilcmd bi t is set in interrupt enabl e r egister . illegal command detection i s being applied and al l illegalization t abl e bits for undefined mode codes are set. an undefined mode cod e 0 w ith t/ bit = 0 i s received: r address w or d = 0x0000 (all hardware interrupts reset the ia w) information w or d = 0x0010 ttint0 (t ime-t ag interrupt 0) bi t = 1 example 4: ttint0 bi t i s set in interrupt enabl e r egister . the time-t ag counter rolls over from full count 0xffff to 0x0000: example: 2-word log buffer entries for v arious interrupt types... * figur e 8 show s w here these addresses occur in the descriptor t able. figure 7. fixed address mapping for interrupt log buffer
HI-6120, hi-6121 holt integrated circuits 55 10. descriptor table the descriptor table, resides in shared ram, in ad - dress range 0x0200 to 0x03ff. this table is initialized by the host (or auto-initialization) to defne how the ter - minal processes valid commands. descriptor table set - tings for each command specify where message data is stored, how data is stored, whether host interrupts are generated, and other aspects essential to command processing. shown in figure 8, the table consists of 128 consecutive descriptor blocks, each comprised of four 16-bit words. the table is organized into four quadrants. the receive subaddress and transmit subaddress quadrants defne response for commands having a sub - address feld ranging from 1 to 30 (0x1e). these are simple n-data word receive or transmit commands, where n can range from 1 to 32 words. when the com - mand t/ r bit equals 0, the receive command quadrant applies. when the t/ r bit equals 1, the transmit com - mand quadrant applies. both subaddress quadrants are padded at top and bot - tom with unused descriptor blocks for subaddresses 0 and 31 (0x1f). the word space reserved for sa0 and sa31 aligns the table addressing, but values stored in these eight locations is not used. command subaddress - es 0 and 31 indicate mode commands. the response for commands containing either sa value is defned in the two mode command table quadrants. the receive mode command quadrant applies when the command word t/ r bit equals 0, while the transmit mode com - mand quadrants applies when t/ r equals 1. the term transmit mode command is a misnomer. all defned mode commands with mode code less than 0x0f havet/ r bit equal to 1, yet none of these mode commands transmits a data word. they transmit only the terminal status word, just like receive commands. within the receive and transmit mode command quadrants, block addressing is based on the low order 5 bits in the command word, containing the mode code value. this is fundamentally different from the subad - dress quadrants in which block addressing is based on the 5-bit subaddress feld. figure 9 shows how to de - rive control word address from the received command word. the control word address for the last valid com - mand can also be found in the current control word address register. all 128 4-word descriptor blocks start with a control word. there are four control word variants (described later), based on command type: receive vs. transmit and mode vs. non-mode commands. all descriptor control words are initialized by the host (or auto-initialization) to defne basic command response. each control word specifes the data buffer method and host interrupt for a specifc subaddress or mode command. each subaddress has both a receive subaddress block and a transmit subaddress block. receive and transmit commands to the same subaddress can be programmed to respond differently. the function of the three remaining descriptor words (in each 4-word block) depends on the data buffer method specifed in the control word. there are 4 data buffer options available: indexed (or single buffer) method where a predeter - mined number of messages is transacted using a single data buffer in shared ram. several host interrupt op - tions are offered, including an interrupt generated when all n messages are successfully completed. double (or ping-pong) buffer method where succes - sive messages alternate between two data buffers in shared ram. several host interrupt options are offered. circular buffer mode 1 where buffer boundaries deter - mine when the bulk transfer is complete and message information and time-tag words are stored with message data in a common buffer. several host interrupt options are offered, including an interrupt generated when the allocated data buffer is full. circular buffer mode 2 where the number of messages transacted defnes bulk transfer progress, and message data words are stored contiguously in one buffer while message information and time-tag words are stored in a separate buffer. several host interrupt options are of - fered, including an interrupt generated when all n mes - sages are successfully completed. the 4-word descriptor table entry for each command (its descriptor block) begins with a control word. there are four types of descriptor control word: ? receive subaddress control word ? transmit subaddress control word ? receive mode command control word ? transmit mode command control word the descriptor control word is initialized by the host to select data buffer method and interrupt options. after a command is processed by the HI-6120/21 terminal, the device updates the commands descriptor control word. update will differ based on the chosen data buf - fer method. reading the descriptor table can differ from other ram accesses. for HI-6120, see section 15.1.1. for hi-6121, see sections 15.2.5 and 15.2.7.
HI-6120, hi-6121 holt integrated circuits 56 0x03ff 0x0380 0x037f 0x0300 0x02ff 0x0280 0x027f 0x0200 subaddress 0 block 32 descriptor blocks of 4 words each transmit mode code quadrant (mode codes with t/r bit = 1) mode code 30 block control w ord for tx mc3 0 descriptor w or d 3 for tx mc3 0 descriptor w or d 2 for tx mc3 0 descriptor w or d 4 for tx mc3 0 control w ord for rx mc3 0 descriptor w or d 3 for rx mc3 0 descriptor w or d 2 for rx mc3 0 descriptor w or d 4 for rx mc3 0 control w ord for tx sa30 descriptor w or d 3 for tx sa30 descriptor w or d 2 for tx sa30 descriptor w or d 4 for tx sa30 control w ord for rx sa30 descriptor w or d 3 for rx sa30 descriptor w or d 2 for rx sa30 descriptor w or d 4 for rx sa30 0x03fb 0x03f a 0x03f9 0x03f8 0x037b 0x037a 0x0379 0x0378 0x02fb 0x02f a 0x02f9 0x02f8 0x027b 0x027a 0x0279 0x0278 example 4-word descriptor blocks from each table quadrant 32 4-word blocks per quadrant note: sa0 and sa31 indicate mode codes, so are not valid receive or transmit subaddresses. see note. see note. see note. see note. subaddress 1 block subaddress 30 block subaddress 31 block subaddress 0 block subaddress 1 block subaddress 30 block subaddress 31 block mode code 31 block mode code 0 block mode code 1 block mode code 30 block mode code 31 block mode code 0 block mode code 1 block 32 descriptor blocks of 4 words each receive mode code quadrant (mode codes with t/r bit = 0) 32 descriptor blocks of 4 words each transmit subaddress quadrant 32 descriptor blocks of 4 words each receive subaddress quadrant figure 8. address mapping for descriptor table (assumes table base address = 0x0200)
HI-6120, hi-6121 holt integrated circuits 57 descriptor address format depends on command words subaddress 0 0 0 0 0 0 1 t/r sa4 sa3 sa2 sa1 sa0 p 0 0 descriptor table address for subaddress commands sa4:0 equals 00001 to 11110 0 0x0 0x2 0 0 0 0 0 0 1 t/r mc 4 mc 3 mc2 mc1 mc 0 p 0 0 1 0x0 0x3 rt addr ta4:0 subaddress sa4:0 word count wc4:0 t/ bi t r command sync rt addr ta4:0 subaddress sa4:0 mode code mc4:0 t/ bi t r command sync descriptor table address for mode code commands sa4:0 equals 00000 or 11111 figure 9. deriving a descriptor table control word address from command word (assumes table base address = 0x0200) 10.1. receive subaddress control word receive subaddress control words apply when a valid command word t/ r bit equals zero (receive) and the subad - dress feld has a value in the range of 1 to 30 (0x1e). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when confguration register 1 stex bit equals 1. the host can write bits 0-2 and 4-7 only when stex equals zero; bits 3 and 12-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any read cycle to the control word address, the dbac bit is reset. msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbac iwa bcast cir2zn3 cir2zn2 cir2zn0 stopp ppen cir2en cir1en ixeqz cir2zn1 ppon mkbusy dpb d1 d d d h h h h h h h h h ibr h bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device h h note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for (a) subaddresses using indexed buf fer mode when the indx value decrements from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. if enabled, upon completion of command processing that results in index = 0, an ixeqz interrupt is entered in the pending interrupt register , out - put pin intmes is asserted, and the interrupt is registered in the interrupt log.
HI-6120, hi-6121 holt integrated circuits 58 bit no. mnemonic r/w reset function 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid receive com - mand. if enabled, upon completion of command processing, an iwa interrupt is entered in the pending interrupt register, output pin intmes is asserted, and the interrupt is registered in the interrupt log. 13 ibr 0 interrupt broadcast received. if the interrupt enable register ibr bit is high, assertion of this bit enables interrupt generation when the subaddress receives a valid broadcast com - mand. if enabled, upon completion of message processing an ibr interrupt is entered in the pending interrupt register, output pin intmes is asserted, and the interrupt is registered in the interrupt log. this bit has no function if the bcstinv bit is high in confguration register 1. in this case, commands to r t address 31 are not recognized as valid by the device. 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this receive subaddress. this bit is an alternative to globally applying busy status for all valid commands, enabled from the 1553 status bits register . see that register description for additional information. when busy is asserted, received data words are not stored and the dpb bit does not toggle after mes - sage completion. 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message processing. the host may poll this bit to detect subaddress activity, instead of using host interrupts. this bit is reset to logic 0 by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies in ping-pong buf fer mode. this bit indicates the buffer to be used for the next occurring receive command to this subaddress. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in er - ror, after illegal commands or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buf fer a. this bit is dont care for indexed single-buffer mode or either circular buffer mode. 9 bcast 0 sr = 0 broadcast command. device logic sets this bit when a valid broadcast receive command is received at this subaddress. if ibr bit 13 and interrupt enable register ibr bit are both set, the output pin intmes is asserted. this bit has no function if the bcst - inv bit is asserted in the confguration register 1; in this case commands to rt address 31 are not recognized as valid by the device. this bit is reset to logic 0 by mr master reset or srst software reset.
HI-6120, hi-6121 holt integrated circuits 59 bit no. mnemonic r/w reset function 8 ppon 0 ping-pong enable acknowledge. this bit is controlled by the device and cannot be written by the host. it only applies if ppen bit 2 was initialized to logic one by the host after reset, en - abling ping-pong buffer mode for this subaddress. device logic asserts this bit when it recognizes ping-pong is active for this subaddress. before of f-loading the receive data buffer for this subaddress, the host can ask the device to temporarily disable ping-pong by asserting stopp bit 3. the device acknowl - edges ping-pong is disabled by negating ppon. the host can safely off-load the buffer without data collision while ppon is negated. after buffer servicing, the host asks the device to re-enable ping-pong by negating stopp bit 3. the device acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is high and ppon bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. each new message overwrites exist - ing data in the buffer specifed by dpb bit 10, and the dpb bit does not toggle after command completion. 7-4 cir2zn 0 circular mode 2 zero number. used only in circular buffer mode 2, this 4-bit feld is initialized with the number of trailing zeros in the initialized miba address. this is explained in section 11.6, which fully describes circular buffer mode 2. 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this subaddress. the host resets this bit to ask the device to re-enable ping-pong. the device confrms recognition of ping-pong enable or disable status by writing ppon bit 8. refer to later section fully describing ping-pong mode. 2 1 0 ppen cir2en cir1en 0 0 0 ping-pong, circular buffer mode 2 or circular buffer mode 1 enable. the ppen, cir2en and cir1en bits are initialized by the host to select buf fer mode. the table below summarizes how buffer mode selection is encoded. in the case of ping-pong, the host initializes the ppen bit to logic one after reset to enable ping-pong buffering for this subaddress. the host asserts stopp bit 3 to ask the device to temporarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping- pong enable or disable state changes by writing the ppon bit. ppen cir2en cir1en buffer mode 1 dont care dont care ping-pong 0 1 dont care circular mode 2 0 0 1 circular mode 1 0 0 0 indexed single buffer
HI-6120, hi-6121 holt integrated circuits 60 10.2. transmit subaddress control word transmit subaddress control words apply when a valid command word t/ r bit equals one (transmit) and the subad - dress feld has a value in the range of 1 to 30 (0x1e). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when confguration register 1 stex bit equals 1. the host can write bits 0-2 and 4-7 only when stex equals zero; bits 3,12 and 14-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any host read cycle to the control word address, the dbac bit is reset. msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x dbac iwa bcast cir2zn3 cir2zn2 cir2zn0 stopp ppen cir2en cir1en ixeqz cir2zn1 ppon mkbusy dpb d1 d d d h h h h h h h h h h h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for (a) subaddresses using indexed buf fer mode when the indx value decrements from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. if enabled, upon completion of command processing that results in index = 0, an ixeqz interrupt is entered in the pending interrupt register , output pin intmes is asserted, and the interrupt is registered in the interrupt log. 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid transmit com - mand. if enabled, upon completion of command processing, an iwa interrupt is entered in the pending interrupt register, output pin intmes is asserted, and the interrupt is registered in the interrupt log. 13 ----- 0 not used 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this transmit subaddress. this bit is an alternative to globally applying busy status for all valid commands, enabled from the 1553 status bits register . see that register description for additional information. when busy is as - serted, data words are not transmitted and the dpb bit does not toggle after message completion.
HI-6120, hi-6121 holt integrated circuits 61 bit no. mnemonic r/w reset function 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message processing. the host may poll this bit to detect subaddress activity, instead of using host interrupts. this bit is reset to logic zero by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies in ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring transmit command to this subaddress. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in error, after illegal commands or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buffer a. this bit is dont care for indexed single-buffer mode or either circular buffer mode. 9 bcast 0 sr = 0 broadcast received. the device sets this bit when a broadcast-transmit command is received for this subaddress. because non-mode broadcast-transmit commands are always illegal, the assertion of this bit in the control word by the de - vice indicates an illegal command was received. terminal response varies, depending on whether or not illegal command detection applies (any bits set in illegalization table). this bit has no function if the bcstinv bit is asserted in confguration register 1; in this case commands to rt address 31 are not recognized as valid by the device. this bit is reset to logic 0 by mr master reset or srst software reset. 8 ppon 0 ping-pong enable acknowledge. this bit is controlled by the device and should not be written by the host. it only applies if ppen bit 2 was initialized to logic one by the host after reset, enabling ping-pong buffer mode for this subaddress. the rt asserts this bit when it recognizes ping-pong is active for this subaddress. before load - ing the transmit data buffer for this subaddress, the host can ask the rt to temporarily disable ping-pong by asserting stopp bit 3. the rt acknowl - edges ping-pong is disabled by negating ppon. the host can safely load the buffer without data collision while ppon is negated. after buffer servicing, the host asks the rt to re-enable ping-pong by negating stopp bit 3. the rt acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is high and ppon bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. each new message transmits data from the same buffer, specifed by dpb bit 10, and the dpb bit does not toggle after command completion. 7-4 cir2zn 0 circular mode 2 zero number. used only in circular buffer mode 2, this 4-bit feld is initialized with the number of trailing zeros in the initialized miba address. this is explained in section 11.6, which fully describes circular buffer mode 2.
HI-6120, hi-6121 holt integrated circuits 62 bit no. mnemonic r/w reset function 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this subaddress. the host resets this bit to ask the rt to re-enable ping-pong. the rt con - frms recognition of ping-pong enable or disable status by writing ppon bit 8. refer to later section describing ping-pong mode for more information. 2 1 0 ppen cir2en cir1en 0 0 0 ping-pong, circular buffer mode 2 or circular buffer mode 1 enable. the ppen, cir2en and cir1en bits are initialized by the host to select buffer mode. the table below summarizes how buffer mode selection is encoded. in the case of ping-pong, the host initializes the ppen bit to logic one after reset to enable ping-pong buffering for this subaddress. the host asserts stopp bit 3 to ask the device to temporarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping- pong enable or disable state changes by writing the ppon bit. ppen cir2en cir1en buffer mode 1 dont care dont care ping-pong 0 1 dont care circular mode 2 0 0 1 circular mode 1 0 0 0 indexed single buffer 10.3. data buffer options for mode code commands data buffer options for mode code commands differ from options offered for subaddress commands. mode commands cannot use either circular data buffer method, but may use double (ping-pong) buffering or single (indexed) buffering. single message index mode (indx = 0) is suitable in many applications (see section 11.4.1). an alternative called simplifed mode command processing (smcp) may be globally applied for all mode code commands (see section 12.5). to use single (indexed) buffer or double (ping-pong) buffer for mode commands, the smcp bit in confguration reg - ister 1 is logic 0. the control word ppen bit for each mode command determines whether ping-pong or indexed buffering is used. to use simplifed mode command processing, the smcp bit in confguration register 1 is set to logic 1. the control word ppen bit for mode commands is dont care (no longer specifes index or ping-pong buffer mode) because sim - plifed mode command processing stores mode command data and message information words directly within each mode commands redefned descriptor table block. when smcp is enabled, mode code command descriptor blocks (in the descriptor table) do not contain data pointers to reserved buffers elsewhere in the shared ram. instead, each 4-word descriptor block itself contains the message information word, the time-tag word and the data word transacted for each mode command (for mode codes 16-31 decimal). when simplifed mode command processing is used, the range of active bits is reduced in each receive or transmit mode command control word. interrupt control and response is not affected by the smcp option. simplifed mode command processing is fully presented in the later data sheet section entitled mode code commands.
HI-6120, hi-6121 holt integrated circuits 63 10.4. receive mode control word receive mode control words apply when the command word t/ r bit equals zero (receive) and the subaddress feld has a value of 0 or 31 (0x1f). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when confguration register 1 stex bit equals 1. the host can write bit 2 only when stex equals zero; bits 3 and 12-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any read cycle to the control word address, the dbac bit is reset. when single-message indexed buffering or ping-pong buffering is used instead of smcp (simplifed mode code pro - cessing), the receive mode control word looks like this: msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h dbac iwa bcast stopp ppen ixeqz ppon mkbusy dpb d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x h h x d d d when smcp applies, the number of active mode control word bits is reduced: msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h dbac iwa bcast ixeqz ppon mkbusy d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x x x x d d x note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic r/w reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buf fer mode when the indx value decrements from 1 to 0. upon completion of command processing that results in indx = 0, when ixeqz interrupts are enabled, an ixeqz interrupt is entered in the pending interrupt register , the intmes output pin is asserted, and the interrupt is registered in the interrupt log. 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. upon completion of command processing, when iwa interrupts are enabled, an iwa interrupt is entered in the pending interrupt register, the intmes output pin is asserted, and the interrupt is registered in the interrupt log.
HI-6120, hi-6121 holt integrated circuits 64 bit no. mnemonic r/w reset function 13 ibr 0 interrupt broadcast received. if the interrupt enable register ibr bit is high, assertion of this bit enables interrupt generation at each instance of a valid broadcast receive mode code command. upon completion of command processing, when ibr interrupts are enabled, an ibr interrupt is entered in the pending interrupt register , the intmes output pin is asserted, and the interrupt is registered in the inter - rupt log. this bit has no function if the bcstinv bit is high in confguration register 1. in this case, commands to rt address 31 are not recognized as valid by the device. 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this mode code. this bit is an alternative to globally applying busy status for all valid commands, enabled from the 1553 status bits register . see that register description for additional information. when busy is asserted, mode data words received with mc16-mc31 are not stored and the dpb bit does not toggle after message completion. 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message pro - cessing. the host may poll this bit to detect mode command activity, instead of using host interrupts. this bit is reset to logic 0 by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies for mode com - mands using ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring mode command. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in error, after illegal commands, or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buffer a. this bit is dont care for indexed single-buffer mode. 9 bcast 0 sr = 0 broadcast received. device logic sets this bit when a valid broadcast mode command is received having t/ r bit = 0. this bit has no function if the bcstinv bit is asserted in confguration register 1. in this case, rt address 31 commands are not rec - ognized as valid by the HI-6120/21. this bit is reset to logic 0 by mr master reset or srst software reset.
HI-6120, hi-6121 holt integrated circuits 65 bit no. mnemonic r/w reset function 8 ppon 0 ping-pong enable acknowledge. this bit is read only and only applies for mode commands using ping-pong mode (ppen bit 2 was initialized to logic 1 by the host after reset). the device asserts this bit when it recognizes ping-pong is active for this mode code. before off-loading the receive data buffer for this mode code, the host can ask the device to temporarily disable ping-pong by asserting st opp bit 3. the device acknowledges ping-pong is disabled by negating ppon. the host can safely load or off-load the buffer without data collision while ppon is negated. after buffer servicing, the host asks the device to re-enable ping-pong by negating stopp bit 3. the device acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is high and ppon bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. each new message overwrites existing data in the buffer specifed by dpb bit 10, and the dpb bit does not toggle after command completion. 7-4 ----- 0 not used 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this mode code. the host resets this bit to ask the device to re-enable ping-pong. the device confrms recognition of ping-pong enable or disable status by writing ppon bit 3. 2 ppen 0 ping-pong buffer enable. the ppen bit is initialized by the host to select buffer mode. if this bit is high, ping-pong buffering is selected. if this bit is low, indexed single buffering is selected. after reset, the host initializes this bit to logic 1 to enable ping-pong buf fering for this mode code. the host asserts stopp bit 3 to ask the device to tempo - rarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping-pong enable or disable state changes by writing the ppon bit. 1,0 ----- 0 not used. 10.5. transmit mode control word transmit mode control words apply when the command word t/ r bit equals one (transmit) and the subaddress feld has a value of 0 or 31 (0x1f). the descriptor control word defnes terminal command response and interrupt behavior, and conveys activity status to the host. it is initialized by the host before terminal execution begins. bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when confguration register 1 stex bit equals 1. the host can write bit 2 only when stex equals zero; bits 3 and 12-15 can be written anytime. this register is cleared to 0x0000 by mr master reset. software reset (srst) clears just the dbac, dpb and bcast bits. following any read cycle to the control word address, the dbac bit is reset. when single-message indexed buffering or ping-pong buffering is used instead of smcp (simplifed mode code pro - cessing), the transmit mode control word looks like this:
HI-6120, hi-6121 holt integrated circuits 66 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h dbac iwa bcast stopp ppen ixeqz ppon mkbusy dpb d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x h h x d d d when smcp applies, the number of active mode control word bits is reduced: msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 h dbac iwa bcast ixeqz ppon mkbusy d1 h bit is not used, may be logic 0 or 1 x bit set by device, reset by host read cycle d d1 bit maintained by host h bit maintained by device ibr h h x x x x x x x x d d x note: reset refers to bit value following master reset ( mr ). the bit value following software reset is un - changed unless specifcally indicated by an sr value. bit no. mnemonic rw reset function 15 ixeqz 0 interrupt when index equals zero. if the interrupt enable register ixeqz bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buf fer mode when the indx value decrements from 1 to 0. upon completion of command processing that results in indx = 0, when ixeqz interrupts are enabled, an ixeqz interrupt is entered in the pending interrupt register , the intmes output pin is asserted, and the interrupt is registered in the interrupt log. 14 iwa 0 interrupt when accessed. if the interrupt enable register iwa bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. upon completion of command processing, when iwa interrupts are enabled, an iwa interrupt is entered in the pending interrupt register, the intmes output pin is asserted, and the interrupt is registered in the interrupt log. 13 ibr 0 interrupt broadcast received. if the interrupt enable register ibr bit is high, assertion of this bit enables interrupt generation at each instance of a valid broadcast transmit mode code command. upon completion of command processing, when ibr interrupts are enabled, an ibr interrupt is entered in the pending interrupt register , the intmes output pin is asserted, and the interrupt is registered in the inter - rupt log. this bit has no function if the bcstinv bit is high in confguration register 1. in this case, commands to rt address 31 are not recognized as valid by the device.
HI-6120, hi-6121 holt integrated circuits 67 bit no. mnemonic rw reset function 12 mkbusy 0 make busy. the host asserts the mkbusy bit to respond with busy status for commands to this mode code. this bit is an alternative to globally applying busy status for all valid commands, enabled from the 1553 status bits register . see that register description for additional information. when busy is asserted, mode data words are not transmitted with mc16-mc31, and the dpb bit does not toggle after message completion. the mkbusy bit is not heeded if set in the control word for mode code command mc8 reset remote terminal. for this command only, busy is inhibited for the status response transmitted before the reset process begins. 11 dbac 0 sr = 0 descriptor block accessed. internal device logic asserts the dbac bit upon completion of message pro - cessing. the host may poll this bit to detect mode command activity, instead of using host interrupts. this bit is reset to logic 0 by mr master reset, srst software reset or a read cycle to this memory address. 10 dpb 0 sr = 0 data pointer b. this status bit is maintained by the device and only applies for mode com - mands using ping-pong buffer mode. this bit indicates the buffer to be used for the next occurring mode command. when the dpb bit is logic 0, the next message will use data pointer a; when dpb is logic 1, the next message uses data pointer b. in ping-pong buffer mode, the bit is inverted after each error-free message completion. the dpb bit is not altered after messages ending in error, after illegal commands, or after messages when the terminal responds with busy status. this bit is reset to logic 0 by mr master reset or srst software reset; therefore the frst message received after either reset will use buffer a. this bit is dont care for indexed single-buffer mode. 9 bcast 0 sr = 0 broadcast received. device logic sets this bit when a valid broadcast mode command is received having t/ r bit = 1. this bit has no function if the bcstinv bit is asserted in confguration register 1. in this case, rt address 31 commands are not rec - ognized as valid by the HI-6120/21. this bit is reset to logic 0 by mr master reset or srst software reset. 8 ppon 0 ping-pong enable acknowledge. this bit is read only and only applies for mode commands using ping-pong mode (ppen bit 2 was initialized to logic 1 by the host after reset). the device asserts this bit when it recognizes ping-pong is active for this mode code. before loading the transmit data buffer for this mode code, the host can ask the device to temporarily disable ping-pong by asserting stopp bit 3. the device acknowledges ping-pong is disabled by negating ppon. the host can safely load or off-load the buffer without data collision while ppon is ne - gated. after buffer servicing, the host asks the device to re-enable ping-pong by negating stopp bit 3. the device acknowledges ping-pong is re-enabled by asserting ppon. if ppen bit 2 is asserted and ppon bit 8 is negated when a new command arrives for this mode code, ping-pong disable handshake is in ef fect: the device applies single-buffer index mode using data pointer a or data pointer b, per dpb bit 10. the dpb bit does not toggle after command completion.
HI-6120, hi-6121 holt integrated circuits 68 bit no. mnemonic rw reset function 7-4 ----- 0 not used 3 stopp 0 stop ping-pong request. the host asserts this bit to suspend ping-pong buffering for this mode code. the host resets this bit to ask the device to re-enable ping-pong. the device confrms recognition of ping-pong enable or disable status by writing ppon bit 3. 2 ppen 0 ping-pong buffer enable. the ppen bit is initialized by the host to select buffer mode. if this bit is high, ping-pong buffering is selected. if this bit is low, indexed single buffering is selected. after reset, the host initializes this bit to logic 1 to enable ping-pong buf fering for this mode code. the host asserts stopp bit 3 to ask the device to tempo - rarily disable ping-pong. negating the stopp bit asks the device to re-enable ping-pong. the device confrms ping-pong enable or disable state changes by writing the ppon bit. 1,0 ----- 0 not used.
HI-6120, hi-6121 holt integrated circuits 69 11. message data buffers the memory structures described up to this point com - prise not more than 1k words of the lower memory ad - dress space. the remaining memory is allocated by the host for message data storage, to fulfll application re - quirements. this section describes the remaining data structures in shared ram that control (and result from) command processing. by initializing the descriptor table, the host allocates memory space for storing data for each subaddress used in the remote terminal application. each legal receive subaddress and each legal transmit subaddress are usually assigned unique buffer memory spaces. (excep - tion: to comply with the requirements for mil-std-1553 data wrap-around, it is convenient to assign the data wrap-around subaddress to use the same buffer space for both receive and transmit commands.) as an option, data from broadcast receive commands can be stored separately from data resulting from non- broadcast receive commands. each subaddress buffer can use any of four data storage methods offered. subaddress (non-mode) commands are transacted with one to 32 data words. these are stored in a data buffer in shared ram. for receive commands, the device stores data received during message processing in the shared ram buffer. later, the host retrieves these data words from the buffer. in the case of transmit commands, the host has previously stored transmit data words in the transmit subaddress buffer. the device retrieves these data words for transmission while processing the trans - mit command. for each complete message processed, the message data stored in the buffer is comprised of these elements: 1. message information word. 2. time-tag word. 3. one to 32 data words transmitted or received dur - ing message transaction ( except no data word for mode code commands 0 - 15 decimal). the message information word and time-tag word are generated by the device and stored in assigned buffer space to aid the host in further message processing. the message information word contains message type, word count and message error information. the 16-bit time-tag word contains the value in the device internal time-tag counter when the command is validated. the host initializes the descriptor table entry for each subaddress or mode command to select one of four data buffering methods. 1. indexed (single buffer) method (see 11.4). a predetermined number of messages (n) is trans - acted using a single data buffer in shared ram. several host interrupt options are offered, including host interrupt when all n messages are successfully completed. this method also supports single-mes - sage mode when n is purposely initialized to zero. 2. double (or ping-pong) buffer method (see 11.3). successive messages alternate between two 34- word data buffers in shared ram. several host in - terrupt options are offered. 3. circular buffer mode 1 (see 11.5). buffer boundaries determine when the bulk trans - fer is complete. message information and time-tag words are stored in the same buffer with data words. several host interrupt options are offered, including host interrupt when the allocated data buffer is full. 4. circular buffer mode 2 (see 11.6). the number of messages transacted defnes bulk transfer progress. message data words are stored contiguously in one buffer while message informa - tion and time-tag words are stored in a separate buffer. several host interrupt options are offered, including host interrupt when all n messages are completed. the data buffer options are summarized in table 7. simplifed mode command processing. this is a global option that applies for all mode code commands, when enabled. mode commands have ei - ther one data word, or no data word. instead of using data buffers for storing this limited mode command data, the message data is stored directly within the descriptor table. this option for mode commands is described in the section called mode command processing. broadcast data separation when the notice2 option is enabled, data words re - sulting from broadcast receive commands will be stored separately from data resulting from non-broadcast re - ceive commands when using indexed or ping-pong buf - fer modes. when notice2 applies, all subaddresses using indexed or ping-pong modes must have an as - signed 34-word broadcast data buffer in addition to the primary buffers listed above. broadcast data segrega - tion cannot be done using either circular buffer mode.
HI-6120, hi-6121 holt integrated circuits 70 table 7. summary of data buffer modes. buffer mode data buffer(s) number and size message info word suitable for mode codes? primary application indexed one. host defnes size for n messages stored in same buffer as data yes, only single message mode for transacting n (multiple) messages with optional host interrupt when done ping-pong two 34-word buffers, one message each stored in same buffer as data yes for transacting single messages, alternating between a and b buffers circular 1 one. host defnes size for n words stored in same buffer as data no for transacting messages until buffer is full / empty, optional interrupt when done circular 2 one. host defnes size for n messages, plus msg info block stored in separate buffer (msg info block) no for transacting n (multiple) messages with optional host interrupt when done. data buffer holds contiguous pure data. 11.1. subaddress message information words 11.1.1. receive subaddress command for receive subaddress commands, the device stores the received data words plus two additional words. the device adds a receive subaddress message information word and a time-tag word to the received data words. the device stores the message information and time-tag words ahead of the data words associated with the receive command, as shown below. if message error occurs, the rt stores only the receive subaddress message information word and time-tag word. once a message error is detected, the device sets the merr bit in the receive subaddress message information word. when this occurs, all data words are considered invalid. whenever the receive subaddress message information word merr bit is set, the host should disregard the records data word(s). here is an example data structure for a 3-word receive command. notice that the receive subaddress data pointer points to the data structure starting address, not the frst data word. the data pointer is located in the receive subad - dress commands descriptor block, fully described later: data buffer hex address word description device writes word ... data pointer equals 0x0500 0x0500 0x0501 0x0502 0x0503 0x0504 message information word time-tag word data word 1 data word 2 data word 3 after message completion after message completion (see note ) note: the data words are written after message completion when confguration register 2 trxdb is 1, otherwise written when received.
HI-6120, hi-6121 holt integrated circuits 71 synerr gaperr iwderr merr wcterr busid rtrt wc3 wc2 wc1 wc0 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wc4 ilcmd txrterr wasbsy tmoerr the following bits comprise the receive subaddress message information w ord: bit no. mnemonic function 15 tmoerr time-out error. this bit is asserted for rt-rt receive messages when the transmitting terminal fails to start its status word and data transmission before time-out occurs, per tosel0-1 bits in confguration register 2. 14 iwderr invalid word error. assertion of this bit indicates manchester error or parity error was observed in a received data word. 13 gaperr gap error. assertion of this bit indicates bus activity was detected immediately after the last expected receive data word or that a gap occurred before all expected data words were received. 12 wcterr word count error. this bit is asserted if command is received with less data words than the command word specifes. for example, a receive command for three data words is received with two contiguous data words. 11 synerr sync error. this bit is asserted when an incorrect (command/status) sync type occurs in received data words. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 7 and 11-15 for details. 9 wasbsy was busy. this bit is asserted when the terminal responds to the receive command with busy status, due to global busy bit set in 1553 status bits register, or command-specifc mkbusy bit set in the descriptor table control word. received data words were buffered normally. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand is logic 1. the illegalization table should only contain nonzero values when illegal command detection is being applied. see section entitled illegalization table for further information.
HI-6120, hi-6121 holt integrated circuits 72 bit no. mnemonic function 7 txrterr rt-rt transmit remote terminal error. this bit is set when the terminal decodes a valid rt-rt receive command, but one of four potential errors is detected in the second command word, cw2: (1) cw2 is addressed to broadcast address rt31. (2) the cw2 t/ r bit equals 0, (3) the cw2 subaddress is a mode command indicator, 00000 or 11111, or (4) cw2 has same non-broadcast terminal address as receive command word cw1. the txrterr bit is also set when status word received from the transmitting terminal is invalid (e.g., parity error) or bits 15:11 in the status word refect the wrong rt address (does not match cw2). 6 rtrt remote terminal to remote terminal transfer. assertion of this bit indicates the receive command was an error-free r t-to-rt transfer. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 wc4:0 word count. this 5-bit feld contains the word count extracted from the command word. zero indicates 32 words. 11.1.2. transmit subaddress command the external host is responsible for organizing the data packet (i.e., storing n data words) in shared ram and initializ - ing the applicable data pointer. the host must allocate two memory locations at the starting address of the data record for device storage of the transmit subaddress message information w ord and time-tag word. here is an example data structure for a 3-word transmit command. notice that the data pointer points to the data structure starting address, not the frst data word. the data pointer is located in the transmit subaddress commands descriptor block. data buffer hex address word description word is written by ... data pointer equals 0x0500 0x0500 0x0501 0x0502 0x0503 0x0504 message information word time-tag word data word 1 data word 2 data word 3 device, after message completion host, prior to terminals data transmit gaperr merr w3 w2 w1 w0 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w4 ilcmd x x x x wcterr busid rtrt wasbsy the following bits comprise the transmit subaddress message information w ord.
HI-6120, hi-6121 holt integrated circuits 73 bit no. mnemonic function 15,14 ----- not used. 13 gaperr gap error. assertion of this bit indicates bus activity was detected immediately after the transmit com - mand word, when a gap was expected. 12 wcterr word count error. this bit is asserted if command is received with unexpected data word(s). 11 ----- not used. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 12 and 13 for details. 9 wasbsy was busy status. this bit is asserted when the terminal responds to the transmit command with busy status, due to global busy bit set in 1553 status bits register, or command-specifc mk - busy bit set in the descriptor table control word. no data words were transmitted. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand equals one. the illegalization table should only contain nonzero values when illegal command detection is being applied. see section entitled illegalization table for further information. 7 ----- not used. 6 rtrt remote terminal to remote terminal transfer. assertion of this bit indicates the transmit command was an error-free r t-to-rt transfer. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 wc4:0 word count. this 5-bit feld contains the word count extracted from the command word. zero indicates 32 words. 11.2. mode command message information words mode command data structures in shared ram are similar to those for subaddresses. mode codes 0 through 15 (0x0f) do not have an associated data word, so data structures for these mode code values have just a message information word and time-tag word. the message information word is stored at the memory address specifed by the descriptor table data pointer. mode codes 16 through 31 (0x10 through 0x1f) have one associated data word. the message information word is stored at the memory address specifed by the descriptor table data pointer, and the time-tag word is stored in the following location. the data word is stored at the memory address specifed by the data pointer plus two locations. 11.2.1. receive mode command the receive mode command data structure contains a message information word, a time-tag word and may con - tain one data word. if a receive mode command has a data word, the device may apply the data as defned by mil-
HI-6120, hi-6121 holt integrated circuits 74 std-1553, plus store the received single mode data word at the address specifed by the data pointer, plus two locations. refer to data sheet section entitled mode command action summary. here is an example data structure for a receive mode command with data (mode code values 0x10 through 0x1f). notice that the data pointer points to the data structure starting address, not the mode data word. the data pointer is located in the receive mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x0500 0x0500 0x0501 0x0502 message information word time-tag word mode data word device, after message completion three receive mode commands with data are not defned under mil-std-1553b. these are mc16, mc18 and mc19 (mode codes 0x10, 0x12 and 0x13 respectively). however the device responds in form if illegal command detection is not used (corresponding bits in illegalization table are logic 0) and the umcinv bit in confguration register 1 is logic 0. for mode code commands without data, the data structure contains only the message information word and time-tag word. here is an example data structure for a receive mode command without data (mode code values 0x00 through 0x0f). note: none of these receive mode commands are defned under mil-std-1553b but the device responds in form if illegal command detection is not used (corresponding bits in illegalization table are logic 0) and the umcinv bit in confguration register 1 is logic 0. notice that the data pointer points to the data structure starting address, the mes - sage information word. the data pointer is located in the receive mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x0500 0x0500 0x0501 message information word time-tag word device, after message completion synerr gaperr iwderr merr busid mc3 mc2 mc1 mc0 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mc4 ilcmd wasbsy x x wcterr x the following bits comprise the receive mode message information w ord: bit no. mnemonic function 15 ----- not used. 14 iwderr invalid word error. assertion of this bit indicates manchester error or parity error was observed in a received data word. 13 gaperr gap error. assertion of this bit indicates bus activity was detected immediately after a received mode data word or that a gap occurred before the data word was received.
HI-6120, hi-6121 holt integrated circuits 75 bit no. mnemonic function 12 wcterr word count error this bit is asserted if the command is received without expected mode data word, or with extra word. 11 synerr sync error. this bit is asserted when incorrect (command/status) sync type occurs in received mode data word. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 11- 14 for details. 9 wasbsy was busy status. this bit is asserted when the terminal responds to the mode command with busy status, due to global busy bit set in 1553 status bits register, or command-specifc mkbusy bit set in the descriptor table control word. 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand equals one. the illegalization table should only contain nonzero values when illegal command detection is being applied. see section entitled illegalization table for further information. 7,6 ----- not used. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 mc4:0 mode code. this 5-bit feld contains the mode code extracted from the command word. 11.2.2. transmit mode command the transmit mode command data structure contains a message information word, a time-tag word and may contain one data word. for mode commands with associated data word (mode codes 16-31 decimal) the host is responsible for loading the mode command data table before transmit mode commands are received (e.g., transmit vector word mode code). two mode codes have internally generated data words: mc18 transmit last command and mc19 transmit bit word. for these, the device automatically transmits the data word then copies the transmitted data value to the stored data structure. here is an example data structure for a transmit mode command with data (mode code values 0x10 through 0x1f). this applies to mc16 transmit vector word. notice that the data pointer points to the data structure starting address, not the mode data word. the data pointer is located in the transmit mode commands descriptor block, fully described later:
HI-6120, hi-6121 holt integrated circuits 76 data buffer hex address word description word is written by ... data pointer equals 0x0500 0x0500 0x0501 0x0502 message information word time-tag word mode data word device, after message completion host, prior to terminals data transmit (except mc18, mc19 are written by the device after completion) three transmit mode commands with data are not defned under mil-std-1553b. these are mc17, mc20 and mc21 (mode codes 0x11, 0x14 and 0x15 respectively). however the device responds in form if illegal command detection is not used (corresponding bits in illegalization table are logic 0) and the umcinv bit in confguration register 1 is logic 0. for mode code commands without data, the data structure contains only the message information word and time-tag word. here is an example data structure for a transmit mode command without data (mode code values 0x00 through 0x0f). again, the data pointer points to the data structure starting address. the data pointer is located in the transmit mode commands descriptor block, fully described later: data buffer hex address word description word is written by ... data pointer equals 0x0500 0x0500 0x0501 message information word time-tag word device, after message completion gaperr merr busid mc3 mc2 mc1 mc0 msb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mc4 ilcmd x x x x wasbsy wcterr x the following bits comprise the mode transmit message information w ord: bit no. mnemonic function 15,14 ----- not used. 13 gaperr gap error. this bit is high when bus activity was detected immediately after the mode command word, when a gap was expected. 12 wcterr word count error this bit is asserted if command is received with unexpected data word(s). 11 ----- not used. 10 merr message error. this bit is asserted when message error status change occurs during command process - ing. see bits 12-13 for details. 9 wasbsy was busy status. this bit is asserted when the terminal responds to the mode command with busy status, due to global busy bit set in 1553 status bits register, or command-specifc mkbusy bit set in the descriptor table control word. no mode data word was transmitted.
HI-6120, hi-6121 holt integrated circuits 77 bit no. mnemonic function 8 ilcmd illegal command received. this bit is asserted when the illegalization table bit corresponding to the received com - mand is logic 1. the illegalization table should only contain nonzero values when illegal command detection is being applied. see section entitled illegalization table for further information. 7,6 ----- not used. 5 busid bus identifcation. if this bit equals zero, message was transacted on bus a. if bit equals one, it was trans - acted on bus b. 4-0 mc4:0 mode code. this 5-bit feld contains the mode code extracted from the command word.
HI-6120, hi-6121 holt integrated circuits 78 11.3. ping-pong data buffering 11.3.1. double buffered (ping-pong) mode ping-pong buffer mode is a method for storing message and time-tag information and data associated with mes - sages. each unique mil-std-1553 subaddress and mode code is assigned a pair of data buffers for transmit commands and a pair of data buffers for receive com - mands. the device retrieves buffer data for transmit commands, or stores buffer data for receive commands. during ping-pong operation, the device alternates mes - sage storage between data buffer a and data buffer b, on a message-by-message basis. when a subaddress or mode command uses ping-pong data buffer mode, its 4-word descriptor block in the de - scriptor table is defned as follows: descriptor word 1 control word descriptor word 2 data pointer a descriptor word 3 data pointer b descriptor word 4 broadcast data pointer if descriptor word 1 is stored at memory address n, de - scriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. prior to starting terminal operation, enable ping-pong buffering for any subaddress (or mode code) by assert - ing the ppen bit and negating the stopp bit in the de - scriptor control word. when the device detects ping- pong is selected (ppen = 1) and enabled (stopp = 0), it asserts the control word ppon bit to confrm ping- pong is active. during ping-pong operation, the rt determines the ac - tive data buffer at the beginning of message process - ing. the control word dpb bit indicates the data pointer to be used by the next command. dpb equals logic 0 means data pointer a is used next; dpb equals logic 1 means data pointer b is used next. for ping-pong, data pointers a and b are static values pointing to the frst ad - dress in each buffer. at the conclusion of error-free mes - sage processing, the control word dpb bit is inverted so the next command ping-pongs to the other data buf - fer. each new message to the subaddress or mode code overwrites message data and information words written two messages back. the dpb bit does not toggle when a message ends in error, or if the command was illegal, or if busy status applied for the received command. in these cases, the next command will overwrite the same buffer. figure 10 is a general illustration of ping-pong buffer mode. figure 11 shows a specifc example. 11.3.2. ping-pong enable / disable handshake because ping-pong messages and host buffer servicing are asynchronous, there is potential for data collision. here is a data collision example: the host reads data from an earlier message while the device simultaneous - ly writes new message data to the same buffer. the host reads a mix of new and old message data. collisions can occur for both transmit and receive messages. a handshake scheme lets the external host asynchro - nously service ping-pong data buffers without data col - lision. to off-load or load a subaddress (or mode code) buffer, the application software performs the following sequence: a. host asserts the control word stopp bit to sus - pend ping-pong operation for the subaddress. when the device recognizes stopp bit asser - tion, it negates the ppon bit to acknowledge ping-pong is disabled. while ppon remains low, the last written (or read) data buffer is pro - tected against device updates. during this time, new messages use the active buffer indicated by the control word dpa bit. recurring messages repeatedly use the same buffer until ping-pong resumes. b. host services the last-used data buffer. if the control word dpb bit equals logic 1, the last command used buffer a. the host application software off-loads or loads inactive buffer a while the remote terminal uses active buffer b for new message(s). if the dpb bit equals logic 0, the last command used buffer b. the host applica - tion software off-loads or loads inactive buffer b while the remote terminal uses active buffer a for any new messages. each new receive message overwrites buffer contents from the last receive message. to avoid possible data loss, host buffer servicing should be timed for completion before a second message can occur. c. host negates the control word stopp bit to re - sume ping-pong operation for the subaddress. when the rt recognizes the stopp bit is reset, it sets the ppon bit to acknowledge ping-pong is again active. as long as ppon remains set, the device alternates between data buffers a and b for new messages.
HI-6120, hi-6121 holt integrated circuits 79 message processing alternates between data buffers a and b. upon sucessful message completion, the dpb bit in descriptor control word is updated so next message uses other buffer. buffers are overwritten every other message. separate buffer for broadcast messages is optional. there is no alternate buffer for successive broadcast messages. bcast data pointer data pointer a data pointer b control word descriptor block for subaddress memory address for the applicable subaddress block is derived from the decoded command word subaddress buffer space for broadcast (optional) broadcast message (if notice2 is asserted) increasing memory address assigned subaddress data buffer b data word 1 message info word time-tag word data words 2-31 data word 32 message #2 message #4 message #6 etc. data word 1 message info word time-tag word data words 2-31 data word 32 message #1 message #3 message #5 etc. assigned subaddress data buffer b data word 1 message info word time-tag word data words 2-31 data word 32 figure 10. illustration of ping-pong buffer mode
HI-6120, hi-6121 holt integrated circuits 80 11.3.3. broadcast message handling in ping- pong mode for mil-std-1553b notice ii compliance, a remote ter - minal should be capable of storing data from broadcast messages separately from non-broadcast message data. some applications may not include this require - ment. the standard does not stipulate where data sep - aration should occur (e.g., within the rt or within the external host) so the device provides alternative strate - gies. when the notice2 bit in confguration register 1 is 1 and the bcstinv bit is 0, ping-pong mode subaddresses (or mode codes) will buffer data words from broadcast and non-broadcast messages separately. broadcast message information and data are stored in the broadcast data buffer; non-broadcast message information and data are stored in ping-pong buffers a and b. since there is just one broadcast data buffer, the notice2 option treats broadcast messages as exceptions to normal ping-pong mode. when using the notice2 option, broadcast data buffer servicing should have high priority, because a closely following broadcast message will overwrite the broadcast buffer. every mode command and subaddress (including transmit subaddresses) must have an assigned val - id broadcast data pointer when notice2 is assert - ed. when the notice2 bit in confguration register 1 is 1 and the bcstinv bit is 0, reception of a broadcast- transmit message updates the message information and time-tag words for the assigned broadcast buffer, but no data is transmitted on the bus. since broadcast- transmit is not allowed, multiple transmit subaddresses may share a common bit bucket broadcast buffer. a two word buffer is suffcient for storing the miw and time-tag word. when using ping-pong mode, there are two ways to han - dle broadcast messages, when broadcast is enabled: option 1 for ping-pong mode broadcast messages: this option isolates broadcast message information in the broadcast data buffer. if the descriptor control word ibr bit and interrupt enable register ibr bit are both set, reception of broadcast messages generates an intmes host interrupt. to prevent data loss, the broadcast data buffer must be serviced before the next broadcast message occurs. broadcast messages do not affect non-broadcast message ping-pong; the control word dpb bit does not toggle after broadcast message completion. option 1 setup: at initialization, host asserts the notice2 bit in confguration register 1 and sets the ibr (interrupt broadcast received) bit in descriptor control word(s). the ibr bit is asserted in the interrupt enable register. when a broadcast command is received, message in - formation and data is stored in the broadcast data buffer and an intmes interrupt is generated. the host must read the interrupt log to determine the originating sub - address (or mode code), then service the broadcast data buffer for that subaddress (or mode code) before another broadcast message to the same subaddress (or mode code) arrives. option 2 for ping-pong mode broadcast messages: the second alternative stores both broadcast and non- broadcast message information in the ping-pong data buffers a and b. iwa interrupts can signal arrival of any new message. the rt handles broadcast messages just like non-broadcast messages, except the mes - sage information word bcast bit is asserted to iden - tify broadcast messages during host buffer servicing. all messages toggle the control word dpb bit in message post-processing. for notice ii compliance, separation of broadcast and non-broadcast data occurs within the host. option 2 setup: at initialization, host negates the no - tice2 bit in confguration register 1. if iwa interrupts are used, the host asserts the descriptor control word iwa (interrupt when accessed) bit 14 and the corre - sponding bit is asserted in the interrupt enable register. using this option, the ibr interrupt is probably not used. the host typically services the ping-pong data buffers a and b whenever a message is transacted. using the setup above, this occurs whenever the subaddress iwa interrupt generates an intmes interrupt output for the host. the host must read the interrupt log to determine the originating subaddress or mode code. the applica - ble data buffer is indicated by the dpb bit in the receive control word. the message information word bcast bit is asserted if the message was broadcast.
HI-6120, hi-6121 holt integrated circuits 81 bcast data pointer data pointer b data pointer a control word increasing memory address control word = 0x2010 ping-pong mode, ibr interrupt initialized descriptor values 0x0500 0x0501 0x0502 0x0503 - 0x0520 0x0521 0x0522 0x0523 0x0524 0x0525 - 0x0542 0x0543 0x0544 0x0545 0x0546 0x0547 - 0x0564 0x0565 ram address device sets control word bcast bit (dpb bit remains static) ibr interrupt is generated device resets control word dpb and bcast bits data word 1 msg info word bc time-tag word bc data words 2-31 data word 32 data word 1 msg info word b time-tag word b data words 2-31 data word 32 data word 1 msg info word a time-tag word a data words 2-31 data word 32 receive message #2 broadcast, 32 data words receive message #3 non-broadcast, 32 data words device resets control word dpb bit receive message #1 non-broadcast, 32 data words message #4 also uses this buffer, if not broadcast broadcast data pointer = 0x0544 start address in ram data pointer b = 0x0522 buffer b start address in ram data pointer a = 0x0500 buffer a start address in ram descriptor block for a receive subaddress assigned subaddress broadcast data buffer assigned subaddress data buffer b assigned subaddress data buffer a following reset (which resets control word dpb bit), the subadd ress transacts 4 commands of 32 data words each. the notice 2 option is enabled so the device segregates data fr om broadcast and non-broadcast messages. message #2 is a broadcast command, while the other three messag es are non-broadcast. notice that the broadcast message does not affect dpb bit, but the following message rese ts bcast bit. the interspersed broadcast command does not affect alternation between buffer a and buffer b. figure 11. ping-pong buffer mode example for a receive subaddress
HI-6120, hi-6121 holt integrated circuits 82 11.4. indexed data buffer mode also called single buffer mode, indexed buffering is one method for storing message and time-tag informa - tion and data associated with messages. buffer mode is selected for each subaddress or mode code in the de - scriptor table control words. indexed mode is enabled when control word ppen, cir1en and cir2en bits are all zero. when a subaddress or mode command uses the in - dexed data buffer mode, its 4-word descriptor block in the descriptor table is defned as follows: descriptor word 1 control word descriptor word 2 data pointer a descriptor word 3 indx index word descriptor word 4 broadcast data pointer if descriptor word 1 is stored at memory address n, de - scriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. as the name implies, all message information and data is stored in a single buffer, indexed by descriptor word data pointer a. the descriptor control word dpb bit is dont care. the host initializes the desired message count in descriptor indx word. during message pro - cessing, the device retrieves or stores data words from the address specifed by descriptor data pointer a, auto - matically incrementing the pointer address as words are read or stored. data pointer a is updated during com - mand post-processing with the current buffer address unless the message index count in descriptor indx (word 3 of descriptor block) decrements to zero upon completion of the message. figure 12 is a general illus - tration of indexed single buffer mode. figure 13 shows a specifc example. to set up a terminal subaddress to buffer multiple mes - sages, the host writes the desired index count (indx) to subaddress descriptor word 3. the initial indx value ranges from zero to 3ff hex (1023) messages. the de - vice decrements the indx count each time an error-free message is transacted, and the data pointer is updated to the frst memory address to be used for the next mes - sage. if indx decrements from one to zero and control word ixeqz bit 15 is asserted, the ixeqz bit is set in the interrupt pending register. if the corresponding bit in the interrupt enable register is asserted, an intmes interrupt is generated when indx decrements from one to zero. indx counter decrement does not occur if the command was illegalized or if indx already equals zero. once indx equals zero, further commands will overwrite the last-written data buffer block and the data pointer value is not updated after successful message completion. when using index mode with a non-zero indx value, the host must remember the initial data pointer a ad - dress. the data pointer a word is not automatically re - initialized to the buffer start address when indx decre - ments from 1 to 0. 11.4.1. single message mode when index mode is initialized with an indx value of zero, the subaddress or mode code is operating in sin - gle message mode. here, the same data block is re - peatedly over-read (for transmit data) or overwritten (for receive or broadcast data). the dpa pointer is not up - dated at the end of each message. the chief advantage of single message mode is simplicity. in comparison to other data buffering options, the single message buffer uses an absolute minimum amount of memory space. the ixeqz interrupt cannot be used for this scheme (indx is always zero) but iwa interrupts may be used. single message mode is best suited to synchronous data transfer where the host processor can reliably read or write new message data prior to the start of the next message to the same subaddress or mode code. 11.4.2. broadcast message handling in index mode for mil-std-1553b notice ii compliance, a remote ter - minal should be capable of storing data from broadcast messages separately from non-broadcast message data. some applications may not include this require - ment. the standard does not stipulate where data sep - aration should occur (e.g., within the rt or within the external host) so the device supports alternative strate - gies. when the notice2 bit is logic 1 in confguration regis - ter 1, broadcast message data is stored in a broadcast data buffer assigned for the subaddress or mode com - mand. each subaddress or mode command must have an assigned, valid non-zero broadcast buffer address. non-broadcast message data is stored in data buffer a. there are two ways to deal with broadcast messages in indexed buffer mode: option 1 for index mode broadcast messages: the frst alternative isolates broadcast message informa - tion in the broadcast data buffer. if the descriptor control word ibr bit and interrupt enable register ibr bit are both set, reception of broadcast messages generates an intmes interrupt to the host. the broadcast data buffer
HI-6120, hi-6121 holt integrated circuits 83 must be processed before another broadcast message arrives to prevent loss of data. broadcast messages do not decrement the indx register, and data pointer a is not updated in message post-processing. this scheme may be well suited for single message mode (indx = 0) when the host can reliably service either the broadcast data buffer or data buffer a before the next receive mes - sage arrives for the same subaddress (or mode code). option 1 setup: at initialization, host asserts notice2 bit in confguration register 1 and sets the control word ibr (interrupt broadcast received) bit for each index mode descriptor block. the ibr bit is also asserted in the interrupt enable register. when a broadcast command is received, message in - formation and data are stored in the broadcast data buf - fer. if descriptor control word ibr bit is set, an intmes interrupt is generated. the host must read the interrupt log to determine the originating subaddress (or mode code) then service the broadcast data buffer for that subaddress (or mode code) before the next broadcast message to the same subaddress (or mode code) ar - rives. option 2 for index mode broadcast messages: the second alternative stores both broadcast and non- broadcast message information in data buffer a. op - tional ibr interrupts can signal arrival of broadcast mes - sages. the rt handles broadcast messages just like non-broadcast messages, except the message informa - tion word bcast bit is asserted to identify broadcast messages during host buffer servicing. all messages decrement the indx register and data pointer a is up - dated in message post-processing. this scheme is com - patible with single message mode or conventional n- message indexing. for notice ii compliance, separation of broadcast and non-broadcast data occurs within the host. option 2 setup: at initialization, host negates the notice2 bit in confguration register 1. if broadcast interrupts are used, the control word ibr (interrupt broadcast received) bit is asserted at each desired index mode descriptor block. the ibr bit is also asserted in the interrupt enable register. using option 2, the host has several options for servicing data buffer a: (a) when indx decrements from one to zero (using the ixeqz interrupt), (b) when a broadcast message occurs (using the ibr interrupt) or (c) when any message arrives (using the iwa interrupt).
HI-6120, hi-6121 holt integrated circuits 84 bcast data pointer data pointer a indx index count control word next message data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n descriptor block for subaddress assigned subaddress buffer space increasing memory address memory address for the applicable subaddress block is derived from the decoded command word subaddress buffer space for broadcast (optional) broadcast message (if notice2 is asserted) current message preceding message upon successful message completion, if non-zero the indx count in descriptor word 3 is decremented. if decremented result is non-zero, data pointer a is adjusted so next message is stored above just-completed message. if decremented indx is zero, data point er a remains static and ixeqz interrupt occurs if enabled in control word. figure 12. illustration of indexed buffer mode
HI-6120, hi-6121 holt integrated circuits 85 0x0500 0x0501 0x0502 0x0503 0x0504 0x0505 0x0506 0x0507 0x0508 0x0509 0x050a ram address messages #2, #3, etc receive 4 words broadcast data pointer = 0xxxxx dont care index = 0x0002 initialize index for 2 messages data pointer a = 0x0500 buffer start address in ram control word = 0x8000 index mode, ixeqz interrupt initialized descriptor values index equals two index decrements to one data pointer a = 0x0505 for message #2, index decrements to zero. data pointer a = 0x0505 (static) ixeqz interrupt is generated for message #3 and beyond, the data buffer is overwritten. index remains zero (static) data pointer a = 0x0505 (static) and no ixeqz interrupt occurs. data word 1 msg info word 1 time-tag word 1 data word 2 data word 3 data word 1 msg info word 1 time-tag word 1 data word 2 data word 3 data word 4 assigned receive subaddress buffer increasing memory address messages #1 receive 3 words bcast data pointer data pointer a indx index count control word descriptor block for a receive subaddress figure 13. indexed buffer mode example for a receive subaddress (broadcast not enabled)
HI-6120, hi-6121 holt integrated circuits 86 11.5. circular buffer mode 1 the device offers two circular data buffer modes as alter - natives to ping-pong and indexed buffering. these circu - lar buffer options only apply for subaddress commands, not mode code commands. circular buffering simplifes software servicing of the remote terminal when imple - menting bulk data transfers. a circular buffer mode can be selected for any subaddress by properly initializing its descriptor control word. circular buffer mode 1 is selected when descriptor control word ppen and ci - r2en bits are both 0, and the cir1en bit is logic 1. when a subaddress uses circular buffer mode 1, its four word block in the descriptor table is defned as follows: descriptor word 1 control word descriptor word 2 sa (buffer start address) descriptor word 3 ca (buffer current address) descriptor word 4 ea (buffer end address) if descriptor word 1 is stored at memory address n, de - scriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. figure 14 provides a generalized illustration of circular buffer mode 1, while figure 15 shows a specifc exam - ple. circular buffer mode 1 uses a single user-defned buffer that merges all transmit or receive data, along with message information. two words (message infor - mation and time-tag) are stored at the beginning of the block for each message, followed by the message data word(s). the mode 1 buffer pointers roll over (are reset to their base addresses) when the allocated data buffer memory is full. for each valid receive message, the device enters a message information word, time-tag word and data word(s) into the circular receive buffer. for each valid transmit message, the device enters a message infor - mation word and a time-tag word into reserved memory locations within the circular transmit buffer. the device automatically controls the wrap around of circular buf - fers. two pointers defne circular buffer length: start of buffer (lowest address) and end of buffer (highest address). user specifes the start of buffer (sa) by writing the low - est address value into the second word of a unique sub - address descriptor block. the user defnes the bottom of the buffer (ea) by writing the highest address value to the fourth word of that unique descriptor block. both sa and ea remain static during message processing. the third word in the descriptor block identifes the current address ca (i.e., last accessed address plus one). the circular buffer wraps to the start address after complet - ing a message that results in ca being greater than or equal to ea. if ca increments past ea during message processing, the device will access memory addresses greater than the ea value. reserve 33 address locations past the ea address to accommodate a worst-case 32 data word message with a record starting at address = ea minus 1. each receive subaddress and transmit subaddress may have a unique circular buffer assignment. the rt de - codes the command word t/ r bit, subaddress feld and word count / mode code feld to select the unique com - mand descriptor block containing the control word, sa pointer, ca pointer and ea pointer. for receive messages, the device stores the message information word to the address specifed by ca, the time-tag word into ca+1 and the data into the next n locations starting with ca+2. for transmit messages, the device stores the message information word to the ad - dress specifed by ca and the time-tag word into ca+1. retrieval of data for transmission starts at address ca+2. when entering multiple transmit command data packets into the circular buffer, delimit each data packet with two reserved memory locations. the device stores the message information word and time-tag word into the reserved locations when processing the command. message processing for all commands begins with the device reading the unique descriptor block for the sub - address or mode code specifed by the t/ r bit, subad - dress and word count felds in the received command word. for receive messages, the device stores n received data words in the circular data buffer. the frst data word received is stored at the location specifed by the ca pointer +2. after message completion, the device stores the message information word and time-tag words to addresses ca and ca+1 respectively. if no errors were detected, the device updates descriptor ca register. if the next address location (last stored data word +1) is less than or equal to ea, ca is updated to (last stored address +1). if the next address location (last stored data word +1) is greater than ea, the data buffer is full (or empty); ca is updated to the sa value. if descriptor control word ixeqz bit is asserted (and if interrupt en - able register ixeqz bit is asserted) the device gener - ates an interrupt to indicate full receive buffer by assert - ing the intmes interrupt output. although all messages store message information and time-tag words, no data is stored if the message end - ed with error, or if the busy status bit was set or if the commend was illegal (example: illegalized word count).
HI-6120, hi-6121 holt integrated circuits 87 such messages do not update ca, so the next message overwrites the same buffer space. for transmit commands, the device begins transmis - sion of data retrieving the frst data word stored at ad - dress ca+2. (reminder: addresses ca and ca+1 are reserved for the message information and time-tag words.) when message processing is complete, the device writes the message information and time-tag words into the buffer. if no errors were detected, the device updates descriptor ca register. if the next ad - dress location (last retrieved data word +1) is less than or equal to ea, ca is updated to (last retrieved address +1). if the next address location (last retrieved data word +1) is greater than ea, the transmit data buffer is empty; ca is updated to the sa value. if the descriptor control word ixeqz bit is asserted (and if the interrupt enable register ixeqz bit is asserted) the device indicates transmit buffer empty by asserting the intmes inter - rupt output. circular buffer mode 1 does not support notice2 seg - regation of broadcast data, even when the notice2 bit equals 1 in confguration register 1. data from broad - cast and non-broadcast receive commands is stored in the same buffer. the bcast bit in the message infor - mation word refects broadcast or non-broadcast status for each stored message. if broadcast messages are not expected during data block transmission, the host can illegalize broadcast commands for the subaddress. broadcast illegalization can be done either permanently, or only when data block transmission is scheduled. for transmit subaddresses using circular buffer mode 1, occurrences of broadcast-transmit commands to rt31 do not result in bus transmission. however these messages update the message information word ad - dressed by the current address (ca) pointer (and fol - lowing time-tag word) but afterwards, the ca pointer remains unchanged. the next transmit command to the same subaddress, whether broadcast or not, overwrites the message information and time-tag word locations written by the previous broadcast transmit command.
HI-6120, hi-6121 holt integrated circuits 88 end address start address current address control word current message last message in data block end address current address start address data word 1 message info word time-tag word data word(s) data word n data word 1 message info word time-tag word data word(s) data word n more messages in data block more messages in data block data word 1 message info word time-tag word data word(s) data word n firstmessage in data block descriptor block for subaddress memory address for the applicable subaddress block is derived from the decoded command word assigned subaddress circular buffer increasing memory address descriptor block is initialized so current address equals buffer start address. after each successful message transaction, current address is adjusted to point past last data word accessed. if adjusted current address points past end address, the current address is reinitialized to match start address and an optional interrupt is generated to notify host that the pre-determined data block was fully transacted. figure 14. illustration of circular buffer mode 1
HI-6120, hi-6121 holt integrated circuits 89 contro l w ord increasing memory address 0x0500 0x0501 0x0502 0x0503 - 0x0520 0x0521 0x0522 0x0523 0x0524 0x0525 - 0x0542 0x0543 0x0544 0x0545 0x0546 0x0547 - 0x0564 0x0565 ram address unless serviced by host after message #3 interrupt, message #4 will overwrite buffer, starting at 0x0500 buffer end address (1 + data word 32 address) end address. device updates current address to equal the start address, 0x0500. ixeqz interrupt is generated. receive message #3 32 data words end address start address current address (1 + data word 32 address) < end address. device updates current address to 0x0544. data word 1 msg info word 3 time-tag word 3 data words 2-31 data word 32 data word 1 msg info word 2 time-tag word 2 data words 2-31 data word 32 data word 1 msg info word 1 time-tag word 1 data words 2-31 data word 32 buffer start address receive message #3 32 data words receive message #3 32 data words (1 + data word 32 address) < end address. device updates current address to 0x0522. descriptor block for a receive subaddress control word = 0x8001 circular mode 1, ixeqz interrupt initialized descriptor values start address = 0x0500 buffer start address in ram current address = 0x0500 buffer current address in ram end address = 0x0545 buffer end address in ram unlike indexed mode, data block completion is based on buffer f ull / buffer empty, not number of messages. buffer size was purposely sized to yield remaining capacity aft er 2 full-count messages, to illustrate device behavior. the circular buffer should have a 33-word pad beyond its end address to deal with buffer overrun without data loss. figure 15. circular buffer mode 1 example for a receive subaddress
HI-6120, hi-6121 holt integrated circuits 90 11.6. circular buffer mode 2 circular buffer mode 2 segregates message data and message information in separate host-defned buffers. separating data from message information simplifes the host software that loads or unloads the data to or from the buffer. after a predetermined number of mes - sages has been transacted, buffer address pointers for data and message information are automatically reset to their base addresses. figure 16 is a generalized illustra - tion of circular buffer mode 2, while figure 17 shows a specifc example. circular buffer mode 2 is selected when the control word ppen bit is zero and the cir2en bit is logic 1. when the cir2en bit is high, the cir1en bit is dont care. the descriptor control word dpb bit is not used. any receive subaddress using circular buffer mode 2 has two circular buffers: a data storage buffer and a message information buffer. a separate buffer pair may be used for transmit commands to the same subad - dress, if it also uses circular buffer mode 2. each trans - mit and receive subaddress using circular buffer mode 2 may have unique data buffer and message info buffer assignments. careful management (involving the bus controller) may allow buffer sharing, as long as multiple message sequences to a given subaddress are not in - terrupted by messages to other subaddresses that use the same buffer space. when a subaddress uses circular buffer mode 2, its de - scriptor table 4-word block is defned as follows: descriptor word 1 control word descriptor word 2 sa (buffer start address) descriptor word 3 ca (buffer current address) descriptor word 4 miba (message info buffer addr) if descriptor word 1 is stored at memory address n, de - scriptor word 2 is stored at address n+1, and the other two words are stored at addresses n+2 and n+3. the frst word in the descriptor block is the control word. the second and third words in the descriptor are the start address (sa) and current address (ca) pointers. the message information buffer address (miba) points to the storage location for the message information word from the next occurring message. each time a message is completed, the device writes a new message information word and time-tag word in the mib (message information buffer) at the miba address and following location, respectively. the miba pointer is not updated if message error occurred, if the busy status bit was set, or if the command was illegal - ized (for example an illegal word count expressed in the command word.) for these situations, the message in - formation and time-tag words are still written, but mib updates for the following message will overwrite the just-written message information and time-tag word addresses. for error-free receive messages, received data words are stored in the data buffer after message completion, starting at the ca address value. the ca value is then updated for next-message readiness. after writing the two mib words, the device updates the miba value to show the buffer address to be used by the next message. until the predetermined number of error-free messages is transacted, the miba value is double-incremented at each update. before updating the miba in descriptor word 4, the pre-existing miba value is incremented once then checked for full count, occurring when all n low-order address bits initialized to zero (explained below) become n one bits. full count means the predetermined number of successful mes - sages was completed. when this occurs, the ca and mib pointers are automatically written to their initialized values by the device. to preserve data integrity, the trxdb bit should be set in control register 2 to avoid storing incomplete data from messages resulting in error. with trxdb asserted, the host is not bothered by message retries caused by errors. the buffer empty/full interrupt (if enabled) is generated only upon successful transaction of the entire n-message data block. to initialize circular buffer mode 2, the host must know the number of messages to be transacted, always a power of two: 1, 2, 4, 8, 16, 32, 64, 128, 256 or 512 messages. the host writes descriptor control word bits 7:4 with an encoded 4-bit value to set the fxed number of messages to be transacted. this is illustrated in table 8. the host initializes the descriptor block miba pointer with a message information buffer starting address. because the mib stores two words for each message, the allocated mib space should equal 2x the number of messages. the initially-loaded mib base address value is restricted. some lower bits of the starting address must be zero so the device can restore the miba pointer to the initial mib base address after the predetermined message count is transacted. as illustrated in table 8, the required number of logic-0 bits depends on the message count. initializ - ing the miba base address with more trailing zeros than indicated is acceptable; initializing less trailing zeros will cause malfunction.
HI-6120, hi-6121 holt integrated circuits 91 allocated space in the data buffer (see column 3, table 8) assumes each message has the maximum 32 data words. if messages contain less than 32 words, the data buffer size can be reduced. since circular buffer mode 2 counts messages, values in all remaining table 8 columns remain valid when message word count is reduced. the host may read the miba value to determine the number of messages that have occurred since initializa - tion. by reading the initially-zeroed lower bits of the mib address, the host may determine the number of the next occurring message. from table 8, a block of 128 messages requires 8 trailing zeros in the initial miba address, for example, 0x0f00. after each message is completed, the miba value is updated (0x0f02, 0x0f04, etc.) the device detects message block completion when all required initially-zero trailing address bits equal 1 after miba is in - cremented once. in our example, miba would increment from 0x0ffe to 0x0fff. when full count occurs, the device updates miba to the original value (e.g., 0x0f00) and copies the sa starting address value to ca current address register, ready for buffer service by the host. the device optionally generates a buffer empty-full in - terrupt for the host when block transfer is completed. during block transfer, the host can read the miba value to determine the number of additional messages need - ed before the n-message data block is complete. message processing for all commands begins with the rt reading the unique descriptor block for the subad - dress specifed by the t/ r bit, subaddress and word count felds in the received command word. table 8. circular buffer mode 2 (initialization factors based on message block size) number of messages control word bits 7:4 cir2zn field required data space if 32 words / msg required mib space, 2 words / msg initial miba value, showing the required leading and trailing zeros 2 0010 (2) 64 4 0xxxxxxxxxxxx00 4 0011 (3) 128 8 0xxxxxxxxxxx000 8 0100 (4) 256 16 0xxxxxxxxxx0000 16 0101 (5) 512 32 0xxxxxxxxx00000 32 0110 (6) 1,024 64 0xxxxxxxx000000 64 0111 (7) 2,048 128 0xxxxxxx0000000 128 1000 (8) 4,096 256 0xxxxxx00000000 256 1001 (9) 8,192 512 0xxxxx000000000 512 1010 (a) 16,384 1,024 0xxxx0000000000
HI-6120, hi-6121 holt integrated circuits 92 for receive subaddresses using circular buffer mode 2, the device stores received data words in the circular data buffer. the frst data word received for each message is stored at the location indicated by the ca pointer. after the correct number of words is received (as specifed in the command word) the device writes message information and time-tag words in the message information buffer then updates the descriptor ca current address and miba message information pointers for next-message readiness. if the predetermined total number of messages has not yet been transacted, miba points to the next location in the message information buffer and ca points to the next location in the data buffer. if the completed message is the last message in the block, the ca current (data) address and miba message information pointers are reinitialized to their base address values. (control word bits 7:4 tell the device how many miba lower bits to reset.) if the descriptor control word ixeqz bit is asserted (and if the interrupt enable register ixeqz bit is asserted) the device generates a buffer full / empty interrupt, asserting the intmes interrupt output. for transmit subaddresses using circular buffer mode 2, the device transmits data from the assigned ram buf - fer, starting at the location specifed by the ca pointer. the frst data word transmitted is stored at the loca - tion specifed by the ca pointer. after all data words are transmitted (as specifed in the command word) the device writes message information and time-tag words in the message information buffer then updates the descriptor ca current address and miba message information pointers for next-message readiness. if the predetermined total number of messages has not yet been transacted, miba points to the next location in the message information buffer and ca points to the next lo - cation in the data buffer. if the completed message is the last message in the block, the ca current (data) address and miba message information pointers are reinitialized to their base address values. (control word bits 7:4 tell the device how many miba lower bits to reset.) if the descriptor control word ixeqz bit is asserted (and if the interrupt enable register ixeqz bit is asserted) the device generates a buffer full / empty interrupt, assert - ing the intmes interrupt output. circular buffer mode 2 does not support notice2 seg - regation of broadcast data, even when the notice2 bit equals 1 in confguration register 1. data words from broadcast receive commands are stored in the same buffer with data from non-broadcast receive commands. the bcast bit in the message information word refects broadcast or non-broadcast status for each stored mes - sage. if broadcast messages to the subaddresss are not expected during data block transmission or will result in data block error, the host can illegalize broadcast com - mands for the subaddress, either permanently or only when block transmission is scheduled. for transmit subaddresses using circular buffer mode 2, occurrences of broadcast-transmit commands to rt31 do not result in bus transmission. however these mes - sages update the message information word addressed by the message information block (mib) pointer (and the following time-tag word) but afterwards, the mib and ca pointers remain unchanged. the next transmit com - mand to the same subaddress, whether broadcast or not, overwrites the message information and time-tag word locations written by the previous broadcast trans - mit command.
HI-6120, hi-6121 holt integrated circuits 93 mib address start address current address control word data word 1 message info word time-tag word data word(s) data word n message info word time-tag word message info word time-tag word data word 1 data word(s) data word n data word 1 data word(s) data word n current address start address assigned subaddress circular data buffer current message last message in data block firstmessage in data block descriptor block for subaddress increasing memory address current message last message in data block firstmessage in data block memory address for the applicable subaddress block is derived from the decoded command word assigned subaddress message info buffer (mib) segregated storage for data and message information simplifies host loading / offloading of buffered data. descriptor mib address tracks number of messages. full count occurs when n initialized 0-bits become n 1-bits. when full number of messages in block is transacted, an optional interrupt is generated to notify host. figure 16. illustration of circular buffer mode 2
HI-6120, hi-6121 holt integrated circuits 94 control word 0x0500 0x0501 - 0x051e 0x051f 0x0520 0x0521 - 0x053e 0x053f 0x0540 0x0541 - 0x055e 0x055f msg count increments to 1. device updates ca to 0x0520 and updates miba to 0x0602. mib address start address current address data word buffer msg count increments to 2. device updates ca to 0x0540 and updates miba to 0x0604. 0x0560 0x0561 - 0x057e 0x057f msg count increments to 3. device updates ca to 0x0560 and updates miba to 0x0606. msg count increments to 4, full count, data block complete. device updates ca to equal buffer start address 0x0500. device updates miba to equal mib start address 0x0600. ixeqz interrupt is generated. message information buffer (mib) ram address 0x0600 0x0601 0x0602 0x0603 0x0604 0x0605 0x0606 0x0607 data word 1 data words 2-31 data word 32 data word 1 data words 2-31 data word 32 data word 1 data words 2-31 data word 32 data word 1 data words 2-31 data word 32 msg info word 3 time-tag word 3 msg info word 2 time-tag word 2 msg info word 1 time-tag word 1 msg info word 4 time-tag word 4 ram address increasing memory address descriptor block for a receive subaddress control word = 0x8042 circular mode 2, 4 messages, ixeqz interrupt initialized descriptor values start address = 0x0500 buffer start address in ram current address = 0x0500 buffer current address in ram mib address = 0x0600 mib start address in ram receive message #3 32 data words receive message #4 32 data words receive message #2 32 data words receive message #1 32 data words data block completion is based on number of messages, not buffe r full or buffer empty. example is set to successfully transact four 32 data word receive messages, then generate ixeqz interrupt for host. the data buffer requires minimal processing by host because message information words are stored separately in mib. figure 17. circular buffer mode 2 example for a receive subaddress
HI-6120, hi-6121 holt integrated circuits 95 12. mode command processing 12.1. general considerations the device provides decoding for all mode code combi - nations, consistent with mil-std-1553b requirements. several mode command options are provided to suit any application requirement: in confguration register 1, the option bit umcinv (un - defned mode codes invalid) globally defnes whether undefned mode code commands are treated as valid (default) or invalid commands. this bit applies only to the following 22 mode code commands that are unde - fned in mil-std-1553b: mode codes 0 through 15 with t/ r bit = 0 mode codes16, 18 and19 witht/ r bit = 0 mode codes 17, 20 and 21 with t/ r bit = 1 if the umcinv bit is low (default after mr reset) unde - fned mode code commands are considered valid and rt response is based on individual mode command set - tings in the illegalization table: if the commands table bit equals 0, the mode command is legal; the rt responds in form and updates status. if the commands table bit equals 1 the mode command is illegal, the rt asserts message error status and (if non-broadcast) transmits only its status word without associated data word. table 9 describes explicit terminal response for each mode code value and command t/ r bit state, based on vari - ous option settings. if umcinv is asserted, the 22 undefned mode code commands are treated as invalid: there is no terminal recognition of the command. no command response oc - curs and status remains unchanged for the beneft of following transmit status or transmit last command mode commands. if umcinv is low, the device determines legal vs. illegal status of commands from the illegalization table. if the terminal does not use illegal command detection, the il - legalization table should be left in its post-reset default state, all values equal logic 0. in this case, the terminal provides in form response to all valid commands. the terminal responds with clear status and a transmitted mode data word for mode commands 16-31 with t/ r bit equals 1. assigned data buffer locations can be initial - ized to provide predictable in form responses for all transmit mode codes 16-31. (if umcinv is asserted, the terminal will not respond or update status for re - ceived mode codes 17, 20 and 21 with t/ r = 1.) to use illegal command detection, the host modifes the illegalization table to make illegal any combination sub - address and mode code commands. this may include undefned mode codes, reserved mode codes, and/or mode codes not implemented in the application. note: mode command mc0 dynamic bus control can - not be implemented in the device since the HI-6120/21 cannot act as a bus controller. therefore, the dynamic bus control acceptance status bit cannot be set in the outgoing status word from this device. 12.2. mode command interrupts for mode commands, interrupt generation is pro - grammed by the top three bits in the descriptor table control word. notice that broadcast-transmit interrupts can be enabled for mode code values in the range of 0 - 15, but broadcast-transmit mode codes 16 - 31 are not allowed. when a mode command is received and the iwa interrupt bit is asserted in its descriptor control word, that command will generate a host interrupt if the iwa bit is high in the interrupt enable register. the iwa bit is asserted in the pending interrupt register and the intmes interrupt output is asserted. before intmes interrupt assertion, the device updates the interrupt log buffer, writing a new iiw interrupt in - formation word and a new iaw interrupt address word. the iwa (interrupt when accessed) bit is asserted in the new iiw to indicate interrupt type. the iaw contains the descriptor table address for the mode commands con - trol word, based on mode code value and command word t/ r bit state. the host reads the iaw to determine the command that caused the interrupt. 12.3. mode command data words mode commands having mode code values from 0 through 15 (decimal) do not have an associated data word. these are received as command word only, never having a contiguous data word. the terminal response to valid mode commands 0-15 always consists of status word only, assuming command was not broadcast. mode commands having mode code values from 16 through 31 (decimal) always have an associated data word. when the command word t/ r bit equals 0, the ter - minal receives a data word, contiguously following the command word. when valid legal mode commands 16- 31 arrive with t/ r bit equal to 1, the terminal responds by transmitting its status word with a single data word. when the smcp option bit in confguration register 1 is zero, individual data words for mode codes 16-31 decimal are stored in an indexed or ping-pong buffer as - signed by the mode commands descriptor table entry.
HI-6120, hi-6121 holt integrated circuits 96 circular buffer methods are not available for mode code commands. when the smcp option bit in confguration register 1 is asserted, individual data words for mode codes 16-31 decimal are stored within the descriptor table itself. this is explained next. table 9. mode code command summary command t/ r bit mode code mil-std-1553 defned function associated data word broadcast allowed see note binary dec. 0 00000 to 01111 0 to 15 undefned mode commands 0 - 15 when t/ r bit = 0 no no (1) 1 00000 0 dynamic bus control no no (3) 1 00001 1 synchronize (without data) no yes 1 00010 2 transmit status word no no 1 00011 3 initiate self-test no yes 1 00100 4 transmitter shutdown no yes 1 00101 5 override transmitter shutdown no yes 1 00110 6 inhibit terminal flag no yes 1 00111 7 override inhibit terminal flag no yes 1 01000 8 reset remote terminal no yes 1 01001 to 01111 9 to 15 reserved mode commands 9 - 15 with t/ r bit = 1 no yes (2) 0 10000 16 undefned mode command yes no (1) 1 10000 16 transmit vector word yes no 0 10001 17 synchronize with data yes yes 1 10001 17 undefned mode command yes no (1) 0 10010 18 undefned mode command yes no (1) 1 10010 18 transmit last command yes no 0 10011 19 undefned mode command yes no (1) 1 10011 19 transmit built-in test word yes no 0 10100 20 selected transmitter shutdown yes yes 1 10100 20 undefned mode command yes no (1) 0 10101 21 override selected transmitter shutdown yes yes
HI-6120, hi-6121 holt integrated circuits 97 command t/ r bit mode code mil-std-1553 defned function associated data word broadcast allowed see note binary dec. 1 10101 21 undefned mode command yes no (1) 0 01001 to 01111 22 to 31 reserved mode commands 22 - 31 with t/ r bit = 0 yes yes (2) 1 01001 to 01111 22 to 31 reserved mode commands 22 - 31 with t/ r bit = 1 yes no (2) notes: 1. the 22 undefned mode commands can be rendered invalid by setting the umcinv (undefned mode codes invalid) option bit in confguration register1. if umcinv is asserted, there is no recognition of the undefned com - mand by the terminal. if umcinv is zero, the commands are considered valid. terminal response when umcinv equals 0 is wholly determined by the illegalization table: a. if a commands bit in the illegalization table equals zero, the terminal responds in form with clear status. mode commands 17, 20 and 21 are undefned when t/ r bit equals one, but will transmit a contiguous data word. mode commands 16, 18 or 19 are undefned when t/ r bit equals 0, but will receive a contiguous data word. b. if a commands bit in the illegalization table equals one, the command is considered illegal. the message error (me) status bit is asserted and the terminal transmits status without data word. illegal mode commands 16-31 will not transmit or receive a mode data word. 2. response to the reserved mode commands is fully defned by illegalization table settings. as described in (a) and (b) above, the terminal illegalizes any reserved mode command having illegalization table bit equal to 1, and re - sponds in form when the table bit equals zero. the in form response for reserved mode commands 16 through 31 transacts a received or transmitted data word. 3. HI-6120/21 cannot fulfll bus control duties.
HI-6120, hi-6121 holt integrated circuits 98 12.4. standard mode command processing data buffer options for mode commands differ from buffer options for subaddress commands. mode com - mands can use ping-pong buffering or indexed buffer - ing. when mode commands use indexed buffers, single message mode (indx = 0) is recommended. when us - ing indexed or ping-pong buffers for mode commands: ? for mode commands without associated data word (mode codes 0-15 decimal), only the message in - formation and time-tag words are updated in the mode commands assigned data buffer in ram. ? for mode commands 16-31 (decimal) that receive a data word, indexed and ping-pong buffer meth - ods copy the received mode data word to the mode commands assigned data buffer in shared ram, after the message is transacted. the message in - formation and time-tag words are also updated. ? for most mode commands 16-31 (decimal) that transmit a data word, the device reads the data word for transmit from the buffer location assigned in the descriptor table. exceptions occur for mc18 transmit last command and for mc19 transmit bit word. the mc18 data word is automatically provided by the device, based on recent command transactions. the mc19 data word comes from register 0x14 or 0x15, depending on the state of the altbitw option in confguration register 2. for both mc18 and mc19, the transmitted data word is automatically recorded in the mode com - mands assigned data buffer in ram, after mes - sage completion. the message information and time-tag words are also updated. 12.5. simplifed mode command processing mode commands have a buffer alternative that is un - available for subaddress commands. the smcp bit in confguration register 1 selects simplifed mode com - mand processing, a global option applying to all mode commands. when the smcp bit is high, mode com - mand descriptor blocks (in the descriptor table) do not contain data pointers to reserved buffers elsewhere in the shared ram. instead, each 4-word descriptor block itself contains the message information word, the time- tag word and the data from the most recent occurrence of each mode command: descriptor word 1 mode command control word descriptor word 2 message information word descriptor word 3 time-tag word descriptor word 4 mode data word descriptor word 1 contains the receive or transmit mode command control word. when smcp is used, just two control word bits are used: dbac (descriptor block ac - cessed) and bcast (broadcast). when smcp is enabled, the host need not initialize the mode code command segments in the descriptor table. when simplifed mode command processing is selected, the host does not write descriptor words 2-3 in the descriptor table entries for mode commands. for mode code values 0 to 15 decimal, the descriptor word 4 serves no function because these mode codes do not have an associated data word. for transmit mode code values 16 to 31, the host may initialize descriptor word 4. the default transmit value is 0x0000. mode com - mand mc16 transmit vector word is one of the three defned mode commands that transmit a data word: mc16, mc18 and mc19. its descriptor word 4 should be initialized if a value other than 0x0000 is needed. mc18 and mc19 are discussed below. ? for mode commands without associated data word (mode codes 0-15 decimal), simplifed mode command processing updates the message infor - mation and time-tag words in descriptor words 2 and 3, and descriptor word 1 (bits 9,11). for these commands, smcp does not update descriptor word 4, which may be non-zero if written earlier by the host. ? for receive mode commands 16-31 (decimal) that receive a data word, simplifed mode command processing copies the received mode data word to descriptor word 4. the message information and time-tag words in descriptor words 2 and 3, and descriptor word 1 (bits 9, 11) are also updated. ? for most transmit mode codes 16-31 (decimal), the device reads the data word for transmission from each commands descriptor word 4. exceptions occur for mc18 transmit last command and for mc19 transmit built-in test word. the mc18 data word is automatically provided, based on the last command transacted. the mc19 data word comes from register 0x14 or 0x15, depending on the state of the altbitw option in confguration register 2. for mc18 and mc19, the transmitted data value is automatically copied to the mode commands descriptor word 4 after message completion. the message information and time-tag words in
HI-6120, hi-6121 holt integrated circuits 99 descriptor words 2 and 3, and descriptor word 1 (bits 9, 11) are also updated. section 16 appendix shows terminal response to all possible subaddress and mode code command com - binations. the table summarizes terminal response for the full range of message conditions, including errors, incomplete messages, etc. the table explicitly describes terminal response and impact on terminal status word, descriptor control words and data buffer message in - formation words. the table includes effects for all per - tinent setup options and identifes all interrupt options available. bold text blocks indicate error-free messages or in form clear status responses when the terminal is not using illegal command detection. 13. interrupt management 13.1. host message detection options upon receiving messages, the host has several options. the individual descriptor table control words have en - able fags for generating interrupts. interrupts can be enabled on a subaddress or mode code basis. for any subaddress, interrupts can be enabled for (a) every command occurrence, (b) upon occurrence of broadcast commands, (c) at end of multiple message block trans - fers (index mode or circular buffer modes only), or (d) no interrupts at all. some subaddress commands may not require immedi - ate host servicing. if the number of legal subaddresses is small, the host can poll descriptor table control words for the legal subaddresses to detect message activ - ity. the control words dbac bit (descriptor block ac - cessed) is set whenever a message is processed. this bit is automatically reset by any host read cycle to the descriptor control word. whenever the dbac bit reads high, the subaddress transacted a message since the last control word read cycle. another interrupt alternative that works for any number of legal subaddresses (or when illegal command detec - tion is not used) is to poll the device active pin. this pin is high whenever a command is being processed. after the active pin goes low, the host can read the current command register to determine the processed command word, or may fetch the commands descriptor table address from the current control word address register. both registers maintain their loaded values until the next valid command to the terminal is decoded. 13.2. host interrupt generation interrupts are output signals notifying the host when predetermined events have occurred during terminal op - eration; the interrupt-causing events are fully program - mable. the host defnes message-specifc interrupt- causing events when initializing the descriptor table. other hardware-based interrupts are confgured when internal device registers are initialized. to manage host interrupts, the device architecture in - volves an interrupt log buffer, three control registers, two interrupt output pins and two interrupt acknowledge input pins. the three internal registers are the pending interrupt register, the interrupt enable register and the interrupt log address register. the pending interrupt register contains information identifying events pro - grammed by the host to generate interrupts. the inter - rupt enable register lets the host enable or disable in - terrupt generation for different interrupt-causing events. the interrupt log buffer is a 32-word ring buffer located in shared ram address range 0x0040 to 0x005f. separate interrupt outputs are provided for hardware interrupts ( inthw ) and message interrupts ( intmes ). the host programs both pins as either pulsed interrupt outputs or level-sensitive outputs, by writing the intsel bit in confguration register 1. the states are summa - rized in table 10. table 10. summary of interrupt outputs. confg. register 1 bit interrupt output pins interrupt acknowledge input pins intsel inthw intmes ackhw ackmes 0 pulsed output active low the ack pins are not used 1 level output active low active high (internal pull-downs) pulsed outputs have brief (~250ns) duration, suffcient to drive edge-triggered host inputs. in the level mode of operation, asserted interrupts remain low until ac - knowledged by the host. there are two ways the host can acknowledge level interrupts: (1) assert the ackhw or ackmes input pin to clear the respective interrupt inthw or intmes output, or (2) read the pending inter - rupt register to clear both inthw and intmes output pins to the high state. assertion of the inthw interrupt indicates an interrupt- causing hardware event that is enabled in the interrupt
HI-6120, hi-6121 holt integrated circuits 100 enable register. defned interrupt-causing events are listed in table 11. when the inthw output is asserted, one or more bits are set in the pending interrupt regis - ter, to identify the interrrupt event(s). assertion of the intmes interrupt after a message is completed indicates a predetermined message event occurred that is (1) globally enabled in the interrupt en - able register and (2) specifcally enabled for the last command transacted. the descriptor table control word for each command is programmed by the host to enable events that generate message interrupts. the type of intmes event is refected in the ixeqz, iwa, ibr, ilcmd and merr bits within the pending interrupt register. the interrupt architecture maintains information for the last 16 interrupts in a 32-word ring buffer. the device automatically handles interrupt-logging overhead. each interrupt generates two words of information to help the host perform interrupt processing. the interrupt identif - cation word (iiw) identifes the type(s) of interrupt that occurred. the interrupt address word (iaw) identifes the interrupt source (e.g., subaddress descriptor block) using a 16-bit address. 13.2.1. interrupt log address register bits 7:0 in this register indicate the iiw storage address within the buffer for the next occurring interrupt, 0x0040 to 0x005e. bits 15:8 indicate the number of interrupts since the register was last read. for further details, see the full description of the interrupt log address register. 13.2.2. interrupt address word (iaw) stored in the interrupt log buffer, interrupt address words (iaw) identify interrupt-causing messages by storing the descriptor block address for the subaddress or mode code command that generated each message interrupt. 13.2.3. interrupt identifcation word (iiw) stored in the interrupt log buffer, interrupt identifcation words identify type of interrupt event. bit assignments match those used in the pending interrupt register. the host or subsystem reads the iiw to determine which type of interrupt occurred. the interrupt identifcation word is defned in table 11. table 11. interrupt identifcation word iiw - interrupt identifcation word iaw - interrupt address word bit interrupt origin 15 ixeqz message iaw contains the command word descriptor table address 14 iwa message 13 ibr message 12 -------- -------- 11 -------- -------- 10 merr message 9 -------- -------- 8 ilcmd message 7 spifail hardware iaw contains 0x0000 6 lbfa hardware 5 lbfb hardware 4 ttint1 hardware 3 ttint0 hardware 2 rtapf hardware 1 eeckf hardware 0 ramif hardware
HI-6120, hi-6121 holt integrated circuits 101 14. reset and initialization this section describes the hardware and software re - set mechanisms. hardware master reset returns the device to the uninitialized state, requiring register/ram initialization before terminal execution can begin. initial - ization can be performed by the host after mr reset, or automatically, at the users option, by reading confgu - ration data from an external serial eeprom. software reset is asserted by setting the srst bit in confgura - tion register 1. software reset has minimal effect on previously initialized registers and ram structures that defne terminal behavior. however some reinitialization may be needed for some applications, after srst reset is complete. 14.1. master reset using the mr pin and optional auto-initialization hardware master reset is initiated by a low to high tran - sition on the mr pin; it should be applied after power-up, but may be used anytime afterward. when asserted, the mr input pin causes immediate, unconditional hardware reset. command processing is terminated, the bus de - coders and encoder are cleared, the time-tag count is reset. the message error, busy and broadcast com - mand received status bits are reset and terminal flag bit is enabled for assertion. all internal logic is cleared. registers and ram structures are restored to the states shown in table 12. the ready, active, intmes and inthw output pins are negated if previously asserted. after mr pin low to high transition, these steps occur: 1. after 200ns, the states of the following input pins are latched into the operational status register: rta4- rta0, rtap, autoen, lock and intsel. before ready assertion, a host read cycle to any address returns the value in the operational status register. 2. if the mtstoff pin is logic zero, the device per - forms a memory test (< 985us). if memory error oc - curs, the bmtf bit is set in the bit word register 0x0014. if the mtstoff pin is logic one, the mem - ory test is bypassed. this option might be chosen if a faster reset process is needed. regardless of mtstoff state, all ram locations above address 0x001f are cleared to 0x0000. 3. after internal processes are initialized, the device checks the latched state of the autoen bit in the operational status register: if the operational status register autoen bit reads low , auto-initialization is bypassed. the host must ini - tialize the terminal as follows: a. the device asserts the ready output pin. this state change indicates the host can begin post- mr reset initialization of registers and ram struc - tures. b. upon ready assertion, the host should initialize confguration and option registers, the descriptor table(s) and the illegalization table. initialization may include data written into the various trans - mit subaddress buffers assigned by the initialized descriptor table. c. after the host completes initialization, it must as - sert the stex (start execution) bit in confgura - tion register 1 to begin remote terminal opera - tion. if the operational status register autoen bit reads high , the device initializes itself from an external serial eeprom via the dedicated eeprom spi port: the ready output pin remains low while auto - matic self-initialization proceeds. the device reads initialization data from the external serial eeprom memory, using the dedicated eeprom spi port. initialization includes all registers, all tables (includ - ing secondary descriptor tables, if used) and can include initial data written to transmit subaddress data buffers allocated by the descriptor table. if the ee1k pin is low , initialization covers the full 32k address range 0x0 to 0x7fff, including the entire ram. therefore it can initialize second - ary descriptor tables and transmit subaddress buffers in the upper ram space. (note: typical auto-initialization time is 63ms). if the ee1k pin is high , initialization covers just the 1k address range 0x0 to 0x003f. this cov - ers all registers and the minimum set of required tables, including the default descriptor table from 0x00200 to 0x003ff. for many applications, this is the only descriptor table. (note: typical auto- initialization time is 1.97ms). during auto-initialization, the written value for each register or ram location is read back for confrma - tion. if the read-back value does not match the cor - responding value from eeprom, an initialization error is saved. this error results in action (described below) that occurs when the initialization process is fnished. while performing initialization, a running checksum is tallied as follows, using eeprom data read from the 1k or 32k address range. a properly confgured serial eeprom contains a 16-bit checksum value stored at the pair of eeprom locations correspond -
HI-6120, hi-6121 holt integrated circuits 102 ing to ram address 0x0020. the stored checksum is tallied as if ram address 0x0020 equals 0x0000 and fve registers are excluded from checksum com - putation: operational status register 0x0002, pend - ing interrupt register 0x0006, time-tag register 0x0008 and bit word register 0x0014. the stored value is actually the twos-complement of the 16-bit memory checksum, ( checksum + 1). during initialization, byte pairs are sequentially read from eeprom, then merged to a 16-bit value that is both written to device ram (or register) and added (running tally) to the twos-complemented checksum value. when the full 1k or 32k eeprom range is tallied, the running checksum tally should equal zero, indicating error-free checksum tally. after ini - tialization (at ready assertion), the 16-bit twos- complement checksum value is copied from ee - prom to device ram address 0x0020. this is part of the temporary receive data buffer, which does not interfere with terminal initialization. when the device completes auto-initialization, the ready output pin is asserted to the high state. if an initialization error occurred, the following events take place immediately after ready assertion: 1. the inthw interrupt output pin is asserted. 2. the operational status register 0x0002 is writ - ten to indicate the type of error. the eeckf or ramif bit is set to show checksum failure or read-back data mismatch between ram and eeprom. 3. the eelf bit is set in the built-in test word register 0x0014. 4. if ramif read-back error occurred, the address of the frst occurring instance is written to regis - ter address 0x001f. additional locations beyond the saved address may have mismatch, but only the frst instance is logged. the stex bit in confguration register 1 is still zero. if the stex bit in the initialization eeprom is high , and if the eeckf, ramif and rtapf bits are reset in the operational status register 0x0002, the device now sets the stex bit to start remote ter - minal operation. this means: (1) auto-initialization was error-free and (2) the rt address in opera - tional status register bits 15-10 has correct parity. the registers terminal address bits refect input pin states if the lock pin is high, or were overwritten by values from the initialization eeprom, if the lock pin is low. if automatic stex assertion was blocked because eeckf or ramif bits were written high after ready assertion, the host can write stex high, overriding the error condition. if stex assertion was blocked because of rt address parity error, the stex bit cannot be asserted until the parity error is corrected. the host may overwrite the operational status reg - ister rtap4-0 and rtap bits to correct the error, then assert the stex bit in confguration register 1. if the stex bit in the initialization eeprom is low , the stex bit in confguration register 1 is not asserted at this time. the device awaits stex as - sertion by a host write to confguration register 1 before starting remote terminal operation. the stex bit may be written any time after the ready output pin goes high. after any mr master reset, the state of certain input pins (autoen, lock and terminal address pins rta4 to rta0 and rtap) are latched into opera - tional status register 0x0002. because auto-initial - ization follows master reset, the mirrored pin states may be overwritten by the values stored in the ini - tialization eeprom bytes corresponding to register address 0x0002, only if the lock input pin is low. a method for programming the eeprom itself from a fully confgured terminal is explained in a following sec - tion entitled serial eeprom programming utility. if a different method is used for writing the serial eeprom, the twos-complemented checksum (described earlier) must be saved in eeprom locations corresponding to device ram address 0x0020. a compatible serial eeprom uses a spi interface for byte-access read and write operations. sixteen-bit reg - ister and ram values in the hi-612x are stored as upper and lower bytes in the eeprom, in big endian fashion. for example, the upper byte for register address 0x0000 is stored at eeprom address 0x0000 while the lower byte is stored at eeprom address 0x0001. a 64k x 8 eeprom is required to store the entire 32k x 16 ad - dress range. serial eeprom data mapping follows the device mem - ory map shown in figure 2. the single exception: two eeprom locations corresponding to device ram ad - dress 0x0020 must contain the expected checksum value. the serial eeprom used for auto-initialization should be fully written to cover the HI-6120/21 upper address limit of 0x7fff (or 0x03ff, depending on the state of the ee1k input pin). ideally the eeprom image will refect a post- mr reset followed by fresh initialization with nothing written to reset-cleared registers or ram as a result of command processing.
HI-6120, hi-6121 holt integrated circuits 103 table 12. summary of changes due to mr master reset or srst software reset hex address device register contents after mr reset contents after srst reset 0x0000 confguration register 1 0x0000 no change 0x0001 confguration register 2 0x0000 no change 0x0002 operational status register bits 7:0 reset to 0x00 bits 15:8 match pins no change 0x0003 current command register 0x0000 no change 0x0004 current control word address register 0x0000 no change 0x0005 descriptor table base address register 0x0200 0x0200 0x0006 pending interrupt register 0x0000 no change 0x0007 1553 status word bits register 0x0000 0x0000 0x0008 time-tag register 0x0000 0x0000 0x0009 interrupt log address register 0x0040 no change 0x000a current message information word register 0x0000 no change 0x000b-0x000e reserved 0x0000 no change 0x000f memory address pointer (hi-6121 only) 0x0000 no change 0x0010 interrupt enable register 0x0007 no change 0x0011 time-tag utility register 0x0000 no change 0x0012 bus a select register 0x0000 no change 0x0013 bus b select register 0x0000 no change 0x0014 built-in test (bit) word register see note 1 0x0000 0x0015 alternate bit word register 0x0000 no change 0x0016 test control register 0x0000 0x0000 0x0017 bist control register 0x0000 0x0000 0x0018 loopback test transmit data register 0x0000 0x0000 0x0019 loopback test receive data register 0x0000 0x0000 0x0020-0x001f reserved 0x0000 no change
HI-6120, hi-6121 holt integrated circuits 104 hex address ram structure contents after mr reset contents after srst reset 0x0020-0x003f temporary receive data buffer, 32 words all 0x0000 no change 0x0040-0x005f interrupt log buffer, 32 words all 0x0000 no change 0x0060-0x00ff unallocated ram, 160 words all 0x0000 no change 0x0100-0x01ff illegalization table, 256 words all 0x0000 no change 0x0200-0x03ff descriptor table (primary), 512 words all 0x0000 see note 2 0x0400-0x7fff host-assigned data buffers all 0x0000 no change secondary descriptor tables, if used all 0x0000 no change terminal function contents after mr reset contents after srst reset hardware bus decoders reset reset hardware encoders and transmitters reset reset command processing & active output reset reset terminal status (incl me & bcr bits) reset reset prior bus shutdown by mode cmd mc4 or mc20 overridden overridden prior terminal flag inhibit by mode cmd mc6 overridden overridden ready output reset set intmes & inthw interrupt outputs negated (high) negated (high) notes: 1. after master reset, bits 15, 14 and 2 in the bit word register depend on input pin settings. see register descrip - tion. if the mtstoff input pin is low, register bit 3 (bmtf) depends on memory test outcome. the remaining bits are unconditionally reset. however if auto-initialization is enabled and eeprom load failure occurs during the subsequent initialization process, register bit 1 (eelf) will be set. 2. upon srst reset, the dbac, dpb, mkbusy and bcast bits are reset for each of the 128 control words in the primary descriptor table which starts at address 0x0200. if secondary descriptor tables are used (above address 0x0400), the host must perform any necessary table reconfguration after srst reset.
HI-6120, hi-6121 holt integrated circuits 105 14.2. software reset software reset is initiated by a host write that sets the srst bit in confguration register 1. this bit is set au - tomatically when a reset remote terminal mode com - mand is received while the mcopt0 bit is set in con - fguration register 2 (0x0002). software reset causes immediate reset without overwriting registers or tables that were initialized by the host to defne terminal behav - ior. changes to registers and ram are summarized in table 12. software reset cannot initiate automatic self- initialization from serial eeprom. once the srst bit in confguration register 1 is asserted, the following steps are performed: 1. the ready, active, intmes and inthw output pins are negated. terminal execution stops while srst reset is underway. command processing is terminated. the hardware bus decoders and hard - ware encoder are cleared. the message error and broadcast command received fags in the internal status register used for mc2 or mc18 mode com - mand responses are not affected by srst. 2. the descriptor base address register (0x0005) is reinitialized to the base address 0x0200. the follow - ing registers are cleared: the 1553 status word bits register (0x0007), the time-tag register (0x0008) and test registers 0x0016 to 0x0019. 3. the bit word register (0x0014) is cleared, except the contained rtapf bit is not changed. this rein - states any bus previously shutdown by mode code commands mc4 or mc20 (decimal). if the terminal flag status bit was previously inhibited by mode command mc6, inhibit is cleared: the terminal flag status bit will be transmitted whenever bit 0 is set in the 1553 status word bits register. 4. all 128 descriptor table control words are modifed to reset the dbac, dpb, mkbusy and bcast bits. subaddresses or mode codes using ping-pong or single message index mode (indx = 0) are ready for immediate operation after srst reset is complete. however the device cannot reinitialize the descrip - tor table to restore multi-message block transfers, for indexed buffer mode when initial indx value was non-zero, or for either circular buffer mode. 5. the device asserts the ready output pin. terminal operation automatically resumes if the stex bit in confguration register 1 was set before srst oc - curred. 6. after ready assertion, the host may reset stex, then reinitialize all or part of the descriptor table. the host can reinitialize the descriptor table for subaddresses using multi-message block transfers (circular buffer mode 1, circular buffer mode 2 or indexed buffer mode with initial non-zero indx.) the host can also reinitialize transmit data in the assigned transmit subaddress data buffers. data buffers in ram contain data values loaded before srst occurred. the host can clear or overwrite this old data. the host can then assert the stex bit in confguration register 1 to restart terminal opera - tion. 14.3. reset remote terminal mode code mode code mc8 with t/ r bit = 1 should reset the re - mote terminal. after status word transmission, the device automatically resets the status message error (me) and broadcast command received (bcr) bits in its internal status register. bits 0, 14 and 15 are reset in the bit word register at address 0x0014. if either trans - mitter was shutdown by a previous mode code mc4 or mc20, the shutdown condition is overridden. if the terminal flag (tf) status bit was inhibited, the inhibit is reset. this command does not reset any of the host- programmed registers that confgure the terminal for op - eration. to complete the reset process, the host must assert ei - ther mr master reset (with or without auto-initialization) or assert the srst bit in confguration register 1 to ex - ecute software reset. since mc8 requires host interac - tion, most applications will probably utilize the iwa inter - rupt to alert the host when valid mc8 is received. per mil-std-1553b appendix 30.4.3, any reset initiated by the reset remote terminal mode command should be completed within 5 ms following transmission of the status word. overall reset time includes internal device initialization, either host initialization or auto-initializa - tion. overall time to complete reset initiated by the re - set remote terminal mode command mc8 is affected by host response speed and application complexity. 14.4. serial eeprom programming utility the HI-6120 or hi-6121 can program a serial eeprom via the dedicated eeprom spi port for subsequent auto-initialization events. the device copies host-confg - ured registers and ram (confguration tables and pos - sibly data buffers) to serial eeprom. compatible spi serial eeproms are 3.3v, operate in spi modes 1 or 3 and and have 128-byte pages. the serial spi data is clocked at 8.3 mhz sck frequency. a 2k x 8 eeprom can restore the lower 1k x 16 device address space. a 64k x 8 eeprom can restore the entire 32k x 16 device address space.
HI-6120, hi-6121 holt integrated circuits 106 a deliberate series of events initiates copy of data from HI-6120 or hi-6121 to serial eeprom. this reduces the likelihood of accidental eeprom overwrites. this series of events must occur to initiate programming: 1. if using a fresh host initialization immediately following mr master reset as the basis for ee - prom copy: with the autoen, txinha and tx - inhb pins in logic zero state, apply mr master reset and wait for ready output assertion. verify that the inthw output does not pulse low at ready asser - tion, indicating likely rt address parity error at the rta4:0 and rtap pins. using known good param - eters, the host initializes device registers, the ram descriptor table and transmit data buffers (if neces - sary). do not assert stex. go to step 3. or 2. if using the existing eeprom confguration as the baseline for a new eeprom confguration: with the autoen pin in logic 1 state and the tx - inha and txinhb pins in logic zero state, apply mr master reset and wait for ready output assertion. verify that the inthw output does not pulse low (or go and remain low) at ready assertion. con - frm that the rtapf, eeckf and ramif bits are all logic 0 in the operational status register 0x0002. if the stex bit in confguration register 1 was set by auto-initialization, reset it now. modify register and ram values to refect the new changes. go to step 3. 3. important: any processing of valid bus com - mands between mr master reset and this point will cause auto-initialization checksum failure later, due to non-zero values written to read-only registers as a result of command processing. the device will not enter eeprom copy mode at step 4 if valid com - mand reception caused active output assertion after mr reset occurred. if set, the stex bit in con - fguration register 1 also locks-out eeprom copy mode at programming step 4. 4. the host writes one of two 2-part unlock codes to ram address 0x0020. the two unlock codes per - form identical eeprom programming with the ex - ception of the programmed state for the stex bit in confguration register 1. if auto-initialize should program confgu - ration register 1 stex bit to logic 0, ram address 0x0020 is frst written 0xa5f0, then a second load to 0x0020 overwrites the value just written with 0x5f0a. if auto-initialize should program confgu - ration register 1 stex bit to logic 1, ram address 0x0020 is frst written 0x5a0f, then a second load to 0x0020 overwrites the value just written with 0xa0f5. in either case, the two unlock writes must occur without intervening access to other device address - es, except memory address pointer 0x000f for hi- 6121. 5. the eecopy input pin is driven high for at least 1 ms, then driven low. in response, the ready output goes low while eeprom memory is written. pro - gramming commences. the unlock code at address 0x0020 is cleared, then device register and ram contents are written to the serial eeprom. during programming, the twos-complemented checksum is tallied for the entire address range being pro - grammed (1k or 32k words), excluding addresses 0x0002, 0x0006, 0x0008, 0x0014 and 0x0020. at eeprom programming completion, the fnal check - sum is stored in the pair of eeprom locations cor - responding to device ram address 0x0020. the value written to eeprom is actually the twos-com - plement of the memory checksum, (checksum + 1). the value in eeprom is used for error detection when performing auto-initialization. (the host can only access the stored value immediately after an auto-initialization sequence is performed. the twos- complement eeprom checksum value will be cop - ied into ram address 0x0020.) 6. when the ready output goes high, eeprom copy is complete. the stex bit is reset in device con - fguration register 1. 7. the address range copied during eeprom pro - gramming depends on the state of the ee1k input pin when rising edge occurs on the eecopy input: if ee1k is high when eecopy is asserted, the lower 1k x 16 address range from 0x0 to 0x03ff is copied from device registers and ram to eeprom. this includes all registers, all confguration tables in ram and the primary descriptor table in ram at address 0x0200 to 0x03ff. the 1k x 16 write to ee - prom requires up to 83 ms. if ee1k is low when eecopy is asserted, the en - tire 32k x 16 address range from 0x0 to 0x7fff is copied from device registers and ram to eeprom. this range covers all registers, all confguration ta - bles in ram, the primary descriptor table in ram at address 0x0200 to 0x03ff. as long as ee1k re - mains low when auto-initialization occurs, the 32k x 16 programming option can initialize secondary descriptor tables above address 0x0400, if used. the 32k x 16 write to eeprom requires up to 2.64 seconds.
HI-6120, hi-6121 holt integrated circuits 107 the 32k x 16 programming option (ee1k equals zero) can also initialize fxed data for any subset of the 32 possible transmit subaddress buffers, us - ing any of the defned data buffer schemes. to en - able eeprom copy for transmit subaddress data buffers, the buffer space must be pre-loaded with the desired data. be sure to reserve space for mes - sage information and time-tag word locations, as required for the transmit subaddress buffer method. 15. host interface 15.1. HI-6120 host bus interface the HI-6120 uses a parallel bus interface for communications with the host. host interface to registers and ram is enabled through the chip enable ( ce ) pin, and accessed via 16-bit data bus and several host-originated control signals described below. timing is identical for register operations and ram operations via the host bus interface, but read and write operations have different signal timing. the HI-6120 parallel host bus interface is capable of faster communication than the hi-6121 serial peripheral interface. depending on the chosen microprocessor family, the processors hardware bus interface may be described as an external bus interface, memory interface or may have a different name. the user can also imple - ment a software controlled bit-banged interface to the HI-6120, at the cost of substantially slower ram and register read/write times. the bus interface is compatible with the two prevalent bus control signal methods: intel style interface, char - acterized by separate strobes for read and write opera - tions ( oe and we ), and motorola style interface, char - acterized by a single read/write strobe ( str ) and a data direction signal (r/ w ). bus control style is selected us - ing the btype confguration pin, which sets the function of two other input pins to serve as either oe and we , or str and r/ w . the bwid confguration pin selects either 8- or 16-bit bus widths. when the bwid pin is connected to ground, 8-bit mode is selected; two bytes are sequentially trans - ferred for each 16-bit word operation. in 8-bit mode only, the bendi confguration pin selects bus endianness. this is the system attribute that indicates whether in - tegers are represented with the most signifcant byte stored at the lowest address (big endian) or at the high - est address (little endian). internal device storage is big endian. for processor compatibility, the bendi pin sets the order for byte accesses when the host bus is confg - ured for 8-bit width, that is, when bwid equals 0. when bendi is low, little endian is chosen; the low order byte (bits 7:0) is transacted before the high order byte (bits 15:8). when bendi is high, big endian is chosen and the high order byte is transacted on the host bus before the low order byte. in 8-bit mode, all transacted data uses bus data bits 7:0 and bus data bits 15:8 are not used. further, bus address bit a0 ( lb ) always equals 0 during the frst byte read/write access, and equals 1 dur - ing the second byte access when the bwid pin is connected high or left unconnect - ed, 16-bit bus width is used. for 16-bit bus operation, the a0 ( lb ) address pin is not used and the bendi input pin is dont care. 15.1.1. bus wait states and data prefetch the HI-6120 has a wait output pin that tells the host to add wait states when additional access time is needed during bus read cycles. for compatibility with different host processors, the state of the wpol input pin sets the wait output as active high or active low. the wait output can be ignored when the host processor read cycle time is always slow enough to work with the hi- 6120 bus. when using fast host processors, cycle time is sometimes slowed down by confguring the processor to add one or more wait states during every read or write cycle, but slow-down affects all cycles, even when unnecessary. data prefetch is a technique used by the HI-6120 to speed up host multi-word read access to registers or ram by eliminating wait states. prefetching occurs when HI-6120 logic requests data before it is actually needed. because register or ram locations are often read sequentially, performance improves when data is prefetched in address sequence order. for every host read cycle, the device frst reads the addressed loca - tion, then prefetches the following address, to speed up access in the likely event that the following word will be read next. for the HI-6120, wait is always asserted for the frst word fetched in any read sequence. the frst read cycle has a long access time because there is no prefetch. this may be the frst byte read in 8-bit mode, or the frst word read in 16-bit mode. after each word (or byte) is fetched for a read operation, the next word (or byte) is prefetched to speed-up the read cycle time when sequential address read sequences occur. after the frst word read, the following words read in sequence are accessed without wait, resulting in faster overall multi- word read timing. as long as bytes or words are read in address order, additional wait states are unnecessary.
HI-6120, hi-6121 holt integrated circuits 108 data prefetch during read cycles is blocked when the next ram address is a control word in the descrip - tor table. the table base address (set by the value in register 0x0005) and every fourth word thereafter is a control word. this consists of table addresses having these address offsets from the table start address of 0, 4, 8, 0xc 0x1f8 and 0x1fc. if allowed, prefetch (like any other read) would reset the control word dbac sta - tus bit, so prefetch is disallowed in this range. thus for HI-6120, multi-word sequential read sequences will assert wait every fourth word when reading ram within the 512-word descriptor table address range. for fastest read access under all conditions, the user can set host processor bus timing (by adjusting proces - sor wait states for the chip select assigned to the hi- 6120) to match the faster read cycle time for prefetched data, while the HI-6120 wait output adds one or more additional wait states for the slower initial read cycle. timing diagrams for bus read and write operations are shown in section 17.5. separate diagrams show intel style and motorola style control interfaces. 15.2. hi-6121 serial peripheral interface in the hi-6121, internal ram and registers occupy a 32k x 16 address space. the lowest 32 addresses access registers and the remaining addresses access ram lo - cations. timing is identical for register operations and ram operations via the serial interface, and read and write operations have likewise identical timing. 15.2.1. serial peripheral interface (spi) basics the hi-6121 uses an spi synchronous serial interface for host access to registers and ram. host serial com - munication is enabled through the chip enable ( ce ) pin, and is accessed via a three-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host and serial clock (sck). all program - ming cycles are completely self-timed, and no erase cycle is required before write. the spi (serial peripheral interface) protocol specifes master and slave operation; the hi-6121 operates as an spi slave. the spi protocol defnes two parameters, cpol (clock polarity) and cpha (clock phase). the possible cpol- cpha combinations defne four possible spi modes. without describing details of the spi modes, the hi- 6121 operates in the two modes where input data for each device (master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge. these are known as spi mode 0 (cpha = 0, cpol = 0) and spi mode 3 (cpha = 1, cpol = 1). be sure to set the host spi logic for one of these modes. msb lsb msb lsb high z high z 0 1 2 3 4 5 6 7 ce so si sck (spi mode 3) 0 1 2 3 4 5 6 7 sck (spi mode 0) figure 18. generalized single-byte transfer using spi protocol. sck is shown for spi modes 0 and 3
HI-6120, hi-6121 holt integrated circuits 109 the difference between spi modes 0 and 3 is the idle state for the sck signal, which is logic 0 for mode 0 state and logic 1 for mode 3 state (see figure 18). there is no confguration setting in the hi-6121 to select spi mode 0 or mode 3 because compatibility is automatic. beyond this point, the hi-6121 data sheet only shows the spi mode 0 sck signal in timing diagrams. the spi protocol transfers serial data as 8-bit bytes. once ce chip enable is asserted, the next 8 rising edg - es on sck latch input data into the master and slave de - vices, starting with each bytes most-signifcant bit. the hi-6121 spi can be clocked at 16 mhz. multiple bytes may be transferred when the host holds ce low after the frst byte transferred, and continues to clock sck in multiples of 8 clocks. a rising edge on ce chip enable terminates the serial transfer and reinitial - izes the hi-6121 spi for the next transfer. if ce goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. two byte transfers are needed for spi exchange of 16- bit register values or ram data. big endian byte order is used for spi data transfers. the high order byte (bits 15:8) is transferred before the low order byte (bits 7:0). in the general case, both master and slave simulta - neously send and receive serial data (full duplex) per figure 18 below. however the hi-6121 operates half duplex, maintaining high impedance on the so output, except when actually transmitting serial data. when the hi-6121 is sending data on so during read operations, activity on its si input is ignored. figure 19 and figure 20 show actual behavior for the hi-6121 so output. 15.2.2. hi-6121 spi commands for the hi-6121, each spi read or write operation be - gins with an 8-bit command byte transferred from the host to the device after assertion of ce . since hi-6121 command byte reception is half-duplex, the host dis - cards the dummy byte it receives while serially transmit - ting the command byte. the hi-6121 spi command set uses the most signifcant command bit to specify whether the command is read or write. the command byte msb is zero for read com - mands, and one for write commands. 15.2.3. fast-access commands for registers 0-15 the spi command set includes directly-addressed read and write commands for registers 0 through 15. the 8-bit pattern for these commands has the general form w-0-r-r-r-r-0-0 where rrrr is the 4-bit register address, and the most signifcant bit, w signifes write when 1, or read when 0. these fast-access commands appear in table 13. figure 19 and figure 20 show read and write timing as it appears for fast-access register operations. the com - mand byte is immediately followed by two data bytes comprising the 16-bit data word read or written. for a register read or write, ce is negated after the 2-byte data word is transferred. 15.2.4. indirect addressing of ram and registers refer to the hi-6121 spi command set shown in table 14. spi commands other than fast-access use an ad - dress pointer to indicate the address for read or write transactions. this memory address pointer resides at register address 15, and must be initialized before any read or write operation, other than fast-access. to set the address pointer, use a fast-access write to register 15, consisting of command byte 0xbc followed by the desired 16-bit memory or register address. the pointer uses a 15-bit value to access any location in the 32k address range. the current address pointer value can be read using a fast-access read command byte 0x3c. after a 2-byte read/write completion, the internal address pointer automatically increments to the following register address. the host can extend the read or write operation to the next register address by continuing to hold ce low while clocking sck 16 additional times. this auto-increment feature can be used to access one or more sequential register addresses above the command address. auto-increment applies (ranging to the top of the address space) as long as sck continues to be clocked under continuous ce assertion. caution: when the primary address pointer is used for auto- incrementing multi-word read/write and reaches the top of the address range (0x7fff) the next increment will roll over the pointer value to 0x0000. the host should avoid this situation.
HI-6120, hi-6121 holt integrated circuits 110 ce so si sck spi mode 0 msb lsb 0 1 2 3 4 5 6 7 high z high z 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 msb lsb msb lsb data byte 0 command byte host may continue to assert ce here to read sequential word(s). each word needs 16 sck clocks. data byte 1 figure 19. single-word (2-byte) read from ram or a register lsb 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 msb lsb ms b lsb host may continue to assert ce here to write sequential word(s). each word needs 16 sck clocks. ce so si sck spi mode 0 msb high z command byte data byte 0 data byte 1 figure 20. single-word (2-byte) write to ram or a register
HI-6120, hi-6121 holt integrated circuits 111 three single-byte spi commands modify the current ad - dress pointer value in register 15: command address pointer operation 0xd0 add 1 to the current pointer value 0xd8 add 2 to the current pointer value 0xe0 add 4 to the current pointer value the add 4 command may be useful when sequential - ly accessing the same word (for example, the control word) in a series of 4-word descriptor table entries. the add 2 command might be useful for reading the inter - rupt log buffer, comprised of 2-word log entries. in both cases, the add command would be probably followed by read command 0x40 to read the location addressed by the current pointer value. similarly, write command 0xc0 writes the location addressed by the current point - er value. two command bytes cannot be chained; ce must be negated after the add command, then reassert - ed for the following read or write command. the memory address pointer is not affected by fast- access read/writes to registers 0-14 because fast- access spi commands use a separate, internal pointer not directly accessible to the host. just two single-byte spi commands use the current address pointer value in register 15 without frst loading or otherwise modifying it: command read operation 0x40 read location addressed by pointer value command write operation 0xc0 write location addressed by pointer value either of these commands can be used to read or write a single location, or may be used when starting a multi- word read or write by using the pointers auto-increment feature. two single-byte spi commands increment the current address pointer value in register 15, then perform a read or write: command read operation 0x48 add 1 to pointer then read addressed location command write operation 0xc8 add 1 to pointer then write addressed location 15.2.5. data prefetch for spi read cycles data prefetch is a technique used by the hi-6121 to speed up host multi-word read access to registers or ram. prefetching occurs when hi-6121 logic accesses data before it is actually needed. because register or ram locations are often read sequentially, performance improves when data is prefetched in address sequence order. for any spi read cycle, the hi-6121 frst fetches the addressed location, then increments the memory address pointer and prefetches the following address, to speed up access in the likely event that the following word will be read next. for the hi-6121, read cycle prefetch allows the spi host to read sequential locations back-to-back, continuing as long as the host asserts chip select and provides spi clock. this is described as the memory address pointer auto-increment feature. there is an exception: read cycle prefetch is blocked when the next ram address is a control word in the descriptor table. if allowed, pre-fetch (like any other read) would reset the control word dbac status bit. to preserve dbac status bit function, prefetch is disabled when reading control words within descriptor table address range. the table base address (set by the value in register 0x0005) and every fourth word thereafter is a control word. this consists of table addresses having these offsets from the table start address: 0, 4, 8, 0xc through and including 0x1f8 and 0x1fc. see further information in section 15.2.7. these two commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointers auto-increment feature. 15.2.6. special purpose commands several other hi-6121 spi commands load or otherwise modify the primary address pointer before initiating a read or write process. these commands were tailored to the specifc needs of hi-6121 remote terminal host software. using a single-byte spi command, the address pointer can be directly loaded with the memory address for the descriptor table control word corresponding to the last completed mil-std-1553 command. the control word is then read. command read operation 0x50 copy current control word address register 13 to address pointer register 15. read the location addressed by the new pointer value. this command can be used to read just the current
HI-6120, hi-6121 holt integrated circuits 112 control word, or may be used to start a multi-word read because memory pointer auto-increment occurs after the control word is read. six single-byte spi commands add an offset to the cur - rent address pointer value, then read the addressed memory location; the read value is then written to the address pointer register 15. the new pointer value is used to start a read or write operation: command read operation 0x68 read the location addressed by the memory address pointer. write the val - ue just read into the memory address pointer. then read. 0x70 add 1 to the memory address pointer. read value at newly addressed loca - tion and write it into the memory ad - dress pointer. then read. 0x78 add 2 to the memory address pointer. read value at newly addressed loca - tion and write it into the memory ad - dress pointer. then read. command write operation 0xe8 read the location addressed by the memory address pointer. write the val - ue just read into the memory address pointer. then write. 0xf0 add 1 to the memory address pointer. read value at newly addressed loca - tion and write it into the memory ad - dress pointer. then write. 0xf8 add 2 to the memory address pointer. read value at newly addressed loca - tion and write it into the memory ad - dress pointer. then write. primary use occurs when a descriptor table control word was just read. for example, the last op code per - formed was 0x50, reading the control word for the last command. after reading the control word, the memory pointer has automatically incremented. the host can ex - amine fag bits contained in the just-read control word to determine the applicable data buffer (e.g., data buffer a, data buffer b or the broadcast data buffer) then di - rectly service that buffer using these op codes; the three data buffer pointers occur in the three words following the initially read control word. these six commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointers auto-increment feature. when some or all subaddress or mode commands are not programmed to trigger host interrupts, a different single-byte spi command may be useful if polling the descriptor table for message activity. in this situation, the host may poll a series of descriptor table control words looking for instances where the dbac activity bit is set. the dbac (descriptor block accessed) fag is set in the control word each time the corresponding com - mand is completed. the process of reading the control word automatically resets the registers dbac bit so the host can detect activity the next time the dbac fag is set by the device. since descriptor table control words are spaced four words apart, this command is useful when polling a se - ries of descriptor table control words: command read operation 0x60 read addressed location then add 4 to pointer primary use occurs when the address pointer initially points to the frst descriptor table control word in a se - ries of control words to be polled (every fourth word). after 8 sck clocks for the spi command, each instance of this command reads a single location using 16 sck clocks. if cs remains low after 24 clocks and sck con - tinues, a multi-word read begins, using the address pointers auto-increment feature. the second word read is at (control word address + 4), the next control word in the table. another single-byte spi command is useful when ser - vicing interrupts. when enabled interrupts occur, two words are written to the circular 32-word interrupt log buffer, and the interrupt log address register 9 is updat - ed to show the storage address where interrupt informa - tion words will be stored for the next occurring interrupt. buffer starting address is 0x0040 and ending address is 0x005f. because two words are written to the buf - fer for each interrupt, the interrupt log address register always contains an even value in the range of 0x0040 to 0x005e. when servicing an interrupt that just occurred, the host wants timely information on that interrupt. an spi com - mand is provided to simplify interrupt handling:
HI-6120, hi-6121 holt integrated circuits 113 command read operation 0x58 write memory address pointer 0x000f with current value in interrupt log ad - dress register minus 1. if the log ad - dress register contains 0x0040 then 0x005f is written to memory pointer register. then read the addressed ram location, containing the last-written in - terrupt address word. then decrement the memory address pointer, addressing the corresponding interrupt information word. this command can be used to read a single location, or may be used to start a multi-word read in which the memory address pointer automatically decrements after each word read. this is the only spi op code that dec - rements the memory pointer for multi-word operations. repeated memory pointer decrements will wrap around the 0x0040 to 0x005f log buffer boundary. 15.2.7. descriptor table prefetch exceptions for the spi-interface hi-6121, the memory address pointer (register 0x000f) contains the address for each new word read by the host. when starting a read access, the host usually writes the memory address pointer with the address for the frst word to read. the host then uses an spi op code to initiate the read process. after the addressed word is transferred by spi to the host, the hi- 6121 continues to read and transmit words from sequen - tial ram memory addresses, as long as the host con - tinuously asserts chip select while providing sck serial clock pulses. after fetching each new word, the device increments the memory address pointer and prefetch - es the data contained in the newly addressed location. the next word is prefetched even when the host does not ultimately read the following address. for hi-6121, sequential reads from descriptor table that rely on map auto-increment will stop advancing when the next address contains a table control word. properly designed spi transfers overcome this behavior. using spi command op codes, the hi-6121 host must consider prefetch and pointer behavior when reading data from the descriptor table. applied outside the de - scriptor table, the following spi sequence would read data from six successive memory addresses. but below, applied within the table, the sequence gets stuck at the fourth word read. here we assume the descriptor table starts at default base address, 0x0200. the host frst uses spi op code 0xbc to store the table start address 0x0200 in the memory address pointer, then uses op code 0x40 (and map auto-increment) to read the map-addressed loca - tion and successive locations. notice: there is no map auto-increment or data prefetch when map equals 0x0203, so the fnal two read cycles repeat the previous read value and address. from from host hi-6121 comment ===== ======= ========================================== 0xbc ---- spi op code writes memory address pointer (map). 0x0200 ---- the table start address written to map. 0x40 ---- spi op code to read location addressed by map ---- data from 0x0200 (sck continues afterward) ---- data from 0x0201 (sck continues afterward) ---- data from 0x0202 (sck continues afterward) ---- data from 0x0203 (sck continues afterward, control word next) ---- data from 0x0203 (sck continues afterward, control word next) ---- data from 0x0203 (sck stops and /cs is then negated)
HI-6120, hi-6121 holt integrated circuits 114 using a different spi op code, the host can sequentially read the entire descriptor table. from from host hi-6121 comment ===== ======= ========================================== 0xbc ---- op code writes memory address pointer (map) 0x01ff ---- decremented table start addr 0x0200 - 1 written to map 0x48 ---- op code pre-increment map then read addressed location ---- data from 0x0200 (sck continues afterward) ---- data from 0x0201 (sck continues afterward) ---- data from 0x0202 (sck continues afterward) ---- data from 0x0203 (sck stops and /cs is negated) 0x48 ---- op code pre-increment map then read addressed location ---- data from 0x0204 (sck continues afterward) ---- data from 0x0205 (sck continues afterward) ---- data from 0x0206 (sck continues afterward) ---- data from 0x0207 (sck stops and /cs is negated) 0x48 ---- op code pre-increment map then read addressed location ---- data from 0x0208 (sck continues afterward) ---- data from 0x0209 (sck continues afterward) ---- data from 0x020a (sck continues afterward) ---- data from 0x020b (sck stops and /cs is negated) the host may repeat this sequence until the entire descriptor table is read. the repeating read process is not shown, but the sequence could end like this, continuing beyond the table boundary 0x48 ---- op code pre-increment map then read addressed location ---- data from 0x03fc (sck continues afterward) ---- data from 0x03fd (sck continues afterward) ---- data from 0x03fe (sck continues afterward) ---- data from 0x03ff (sck continues afterward) table ends
HI-6120, hi-6121 holt integrated circuits 115 table 13. fast-access spi commands for registers 0-15 command bits 5:2 convey the 4-bit register address. command bits 7 6 5 4 3 2 1 0 hex byte fast-access read command bits 7 6 5 4 3 2 1 0 hex byte fast-access write 0 0 0 0 0 0 0 0 0x00 read register 0 1 0 0 0 0 0 0 0 0x80 write register 0 0 0 0 0 0 1 0 0 0x04 read register 1 1 0 0 0 0 1 0 0 0x84 write register 1 0 0 0 0 1 0 0 0 0x08 read register 2 1 0 0 0 1 0 0 0 0x88 write register 2 0 0 0 0 1 1 0 0 0x0c read register 3 1 0 0 0 1 1 0 0 0x8c write register 3 0 0 0 1 0 0 0 0 0x10 read register 4 1 0 0 1 0 0 0 0 0x90 write register 4 0 0 0 1 0 1 0 0 0x14 read register 5 1 0 0 1 0 1 0 0 0x94 write register 5 0 0 0 1 1 0 0 0 0x18 read register 6 1 0 0 1 1 0 0 0 0x98 write register 6 0 0 0 1 1 1 0 0 0x1c read register 7 1 0 0 1 1 1 0 0 0x9c write register 7 0 0 1 0 0 0 0 0 0x20 read register 8 1 0 1 0 0 0 0 0 0xa0 write register 8 0 0 1 0 0 1 0 0 0x24 read register 9 1 0 1 0 0 1 0 0 0xa4 write register 9 0 0 1 0 1 0 0 0 0x28 read register 10 1 0 1 0 1 0 0 0 0xa8 write register 10 0 0 1 0 1 1 0 0 0x2c read register 11 1 0 1 0 1 1 0 0 0xac write register 11 0 0 1 1 0 0 0 0 0x30 read register 12 1 0 1 1 0 0 0 0 0xb0 write register 12 0 0 1 1 0 1 0 0 0x34 read register 13 1 0 1 1 0 1 0 0 0xb4 write register 13 0 0 1 1 1 0 0 0 0x38 read register 14 1 0 1 1 1 0 0 0 0xb8 write register 14 0 0 1 1 1 1 0 0 0x3c read register 15 1 0 1 1 1 1 0 0 0xbc write register 15
HI-6120, hi-6121 holt integrated circuits 116 table 14. spi commands using address pointer register hex byte read or write read address pointer operations (no data is written or read, no pointer auto-increment) 0xd0 ------- add 1 to the current address pointer value in register 15 0xd8 ------- add 2 to the current address pointer value in register 15 0xe0 ------- add 4 to the current address pointer value in register 15 read / write ram or register location using current address pointer value 0x40 r read location addressed by current address pointer value in register 15 0xc0 w write location addressed by current address pointer value in register 15 increment address pointer then read / write addressed ram or register location 0x48 r read addressed location after incrementing pointer in register 15 0xc8 w write addressed location after incrementing pointer in register 15 special purpose commands 0x50 r copy register 13 (current control word address) to address pointer in register 15, then read the location addressed by the new pointer value (read the current control w ord) 0x68 r add 0 to the current address pointer value in register 15. then . . . 0x70 r add 1 to the current address pointer value in register 15. then . . . 0x78 r add 2 to the current address pointer value in register 15. then copy value from newly addressed location to address pointer in register 15 then read newly addressed location. 0xe8 w add 0 to the current address pointer value in register 15. then . . . 0xf0 w add 1 to the current address pointer value in register 15. then . . . 0xf8 w add 2 to the current address pointer value in register 15. then copy value from newly addressed location to address pointer in register 15 then write newly addressed location. 0x60 r read then add 4 to the current address pointer value in register 15. 0x58 r write storage address of last-written interrupt address word to the address pointer in register 15, then read the interrupt address word from the interrupt log buffer. decrement memory address pointer after read operation.
HI-6120, hi-6121 holt integrated circuits 117 16. appendix: rt messages responses, options & exceptions circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options invalid command word (manchester, parity or bit count error) no terminal response, the message is ignored. no status word change. no change no message info word is written none any valid command to rt31 (broadcast). when the bcstinv bit in confguration register 1 equals 1. no terminal response, the message is ignored. no status word change. (broadcast commands are rendered invalid.) no change no message info word is written none rt address parity error based on rta and rtap bits in the operational status register for commands to the rts own address or to broadcast address rt31: no terminal response, message is ignored. no status word change. no change no message info word is written rtapf (not optional) any valid non-mode (subaddress 1-30) transmit command to rt31 (undefned broadcast transmit). no terminal response, set message error (me) and bcr status bits. dbac bit set. dpb bit toggles. bcast bit set. merr bit set. busid bit updated. iwa ibr (ixeqz) any valid non-mode (subaddress 1-30) transmit command except for rt31. the corresponding bit in the illegalization table equals 0.* normal status word response (clear status). data words for transmit are read from the ram data buffer assigned by the descriptor table entry for the transmit subaddress. dbac bit set. dpb bit toggles. bcast bit reset. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (other error bits reset). iwa ibr (ixeqz) any valid non-mode (subaddress 1-30) transmit command except for rt31. the corresponding bit in the illegalization table equals 1. ** assert message error (me) status, then transmit me status word without following data words. dbac bit set. dpb bit toggles. bcast bit reset. ilcmd bit set. busid bit updated. merr bit set. rtrt bit updated. (other error bits reset). ilcmd iwa any valid non-mode (subaddress 1-30) receive command. the corresponding bit in the illegalization table equals 0. * normal status word response (clear status). after message completion, the data words received are stored in the data buffer ram location assigned by the descriptor table entry for the receive subaddress. dbac bit set. dpb bit toggles. bcast bit reset. normal update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (other error bits reset). iwa ibr (ixeqz) * terminal is using illegal command detection and command is legal or terminal is not using illegal command detection and command may be legal or illegal (in form response). ** terminal is using illegal command detection and command is illegal.
HI-6120, hi-6121 holt integrated circuits 118 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options any valid non-mode (subaddress 1-30) receive command. the corresponding bit in the illegalization table equals 1. ** assert message error (me) status and set bcr if broadcast. any received data words are ignored and are not saved. when data reception stops, transmit status word. dbac bit set. dpb bit toggles. bcast bit updated. ilcmd bit set. busid bit updated. merr bit set. rtrt bit updated. (other error bits reset) ilcmd iwa ibr (ixeqz) valid receive command followed by invalid data word (manchester, parity or bit count error). no terminal response. set message error (me) status. if broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. iwderr bit set. ilcmd bit reset. rtrt bit updated (other error bits reset). merr iwa ibr valid receive command followed by one or more good data words, then a data word having command sync. no terminal response. set message error (me) status. if broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. synerr bit set. ilcmd bit reset. (other error bits reset). merr iwa ibr any valid command followed by wrong number of data words (too few or too many words) no terminal response. set message error (me) status. if broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. set wcterr (too few) or gaperr (too many). ilcmd bit reset. rtrt bit updated. (other error bits reset). merr iwa ibr rt-rt where cw1 is a valid non-mode receive command. cw2 is a non-mode transmit command valid for different rt. (normal rt-rt receive message) normal status word response (clear status). if rt-rt command word 1 is broadcast (rt31) set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. rtrt bit set. rtcwerr bit reset. ilcmd bit reset. (all error bits reset). iwa ibr (ixeqz) rt-rt where cw1 is a valid non-mode receive command. transmit command cw2 has an error: t/ r bit = 0, or cw2 subaddress equals 0 or 31 (mode code), or cw2 has same rt address as cw1. no terminal response. set message error (me) status. if rt-rt command word 1 is broadcast (rt31) also set the bcr status bit, dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. rtrt bit set. rtrtcwerr bit set. ilcmd bit reset. (other error bits reset). merr iwa ibr
HI-6120, hi-6121 holt integrated circuits 119 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options rt-rt where cw1 is a valid non-mode receive command. cw2 is valid for different rt but transmitting rt does not respond in time. no terminal response. set message error (me) status. if rt-rt command word 1 is broadcast (rt31), also set the bcr status bit. dbac bit set. bcast bit updated dpb bit toggles. merr bit set. busid bit updated. rtrt bit set. tmoerr bit set. ilcmd bit reset. (other error bits reset). merr iwa ibr rt-rt receive command (cw1 is valid). the transmitting rt response has one of these errors: invalid word (manchester, (sync, bit count, parity or word count error). also includes transmitting rt response with message error or busy status followed by no data words. no terminal response. set message error (me) status. if rt-rt command word 1 is broadcast (rt31) also set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. buisid bit reset. rtrt bit set. iwderr bit set, or wcterr bit set for tx rt busy case. ilcmd bit reset. (other error bits reset). merr iwa ibr rt-rt command where cw2 is a valid non-mode (subaddress 1-30) transmit command. cw1 is a non-mode receive command for rt31. (normal broadcast rt-rt transmit) normal status word response. clear status is transmitted with the commanded number of data words. data words for transmit are read from the ram data buffer assigned in the descriptor table entry for the transmit subaddress. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit set. (all error bits reset). iwa (ixeqz) valid mode code command to rt31 (broadcast). the bcstinv bit in confguration register 1 equals 1. no terminal response, the message is ignored. no status word change. no change no message info word is written none valid undefned mode code command. the umcinv bit in confguration register 1 equals 1. no terminal response, the message is ignored. no status word change. note: this only applies for the undefned mode codes: mc0 to mc15 with t/ r = 0 mc16,18 & 19 with t/ r = 0 mc17,20 & 21 with t/ r = 1 no change no message info word is written none
HI-6120, hi-6121 holt integrated circuits 120 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options valid defned mode code command (including reserved mode code) not illegalized by illegalization table (table bit equals 0 *) if mc2 (transmit status) or mc18 (transmit last command) status word from last command is transmitted. if mc18, data word transmitted is read from an internal register. or if not mc2 or mc18, normal status word response. if broadcast, assert status word bcr bit. for mode codes 16-31 with t/ r bit = 1 which transmit a data word, the word for transmit is read from the mode command data table. and for all mode commands with mode data word (mode codes 16-31), the transmitted or received data word is written to commands descriptor word 4. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr (ixeqz) valid defned mode code command that is illegalized by the illegalizationtable (table bit equals 1 **) set message error (me) status. if not broadcast (rt31), transmit. status word without a following mode data word. if broadcast (rt31), also assert the bcr status bit. and for mode commands with a mode data word (mode codes 16-31), no updates are made to the mode command data table or to the commands word 4 in descriptor table. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. busid bit updated. merr bit reset. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr * terminal is using illegal command detection and command is legal or terminal is not using illegal command detection and command may be legal or illegal (in form response). ** terminal is using illegal command detection and command is illegal.
HI-6120, hi-6121 holt integrated circuits 121 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options valid undefned mode code command. the umcinv bit in confguration register 1 equals 0. if bit in illegalization table that corresponds to the undefned mode code command equals 1 ** set message error (me) status, if not broadcast (rt31), transmit status word without a following mode data word. if broadcast (rt31), also assert the bcr status bit. or if bit in illegalization table that corresponds to the undefned mode code command equals 0 * normal status word (clear status) response. if command was broadcast (rt31), assert the bcr status bit. and for mode codes 16-31 with t/ r bit = 1 which transmit a data word, the word for transmit is read from the mode command data table. and for all mode commands with mode data word (mode codes 16-31), the transmitted or received data word is written to commands descriptor word 4. dbac bit set. bcast bit updated. dpb bit toggles. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. busid bit updated. merr bit reset. rtrt bit reset. (other error bits reset.) normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) ilcmd iwa ibr iwa ibr (ixeqz) * terminal is using illegal command detection and command is legal or terminal is not using illegal command detection and command may be legal or illegal (in form response). ** terminal is using illegal command detection and command is illegal.
HI-6120, hi-6121 holt integrated circuits 122 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options valid receive command followed by invalid data word (manchester, parity or bit count error). no terminal response. set status word me bit, if broadcast, also set status word bcr bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. busid bit updated. iwderr bit set. ilcmd bit reset. rtrt bit updated. (other error bits reset.) merr iwa ibr superseded message: terminal receives an incomplete message interrupted by a gap of at least 3.5 us, followed by a new valid command on the same bus or on the other bus or terminal is transacting a transmit message on one bus and receives the start of a valid command on the other bus. terminal aborts processing for frst message and responds in full to the second (superseding) message. the status word bcr bit refects broadcast status for: the second command, unless second command is mc2 (transmit status) or mc18 (transmit last command). no change to superseded commands control word. for superseding commands control word: dbac bit set. bcast bit updated dpb bit toggles. no msg info word written for the superseded command. for superseding commands data buffer, a normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (all error bits reset.) none for super - seded command iwa ibr (ixeqz) terminal is busy for a valid receive command either globally (busy bit set in status word bits register) or in response to a particular valid receive command (mkbusy bit set in the commands descriptor table control word.) busy bit is set in the 1553 status bits register. status word is transmitted, unless broadcast. if broadcast, the bcr bit in status word is also set. after message completion, data words received are stored in the data buffer assigned by the receive subaddress descriptor table entry. dbac bit set. bcast bit updated. dpb bit toggles. wasbsy bit set. busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (all error bits reset.) iwa ibr terminal is busy for a valid transmit command either globally (busy bit set in status word bits register) or in response to a particular valid receive command (mkbusy bit set in the commands descriptor table control word.) busy bit is set in the 1553 status bits register. if not broadcast, status word is transmitted without data. if broadcast, the bcr bit in status word is also set. dbac bit set. bcast bit updated, (mode commands with t/ r = 1) dpb bit toggles wasbsy bit set. busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit updated. (all error bits reset.) iwa ibr
HI-6120, hi-6121 holt integrated circuits 123 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options dynamic bus control (mc0): mode code command with mode code 00000 and t/ r bit equals 1 hi-6110 is not equipped to accept bus control duties. the host must initialize device to respond using either of the two following methods: the mode codes bit in illegalization table equals 0 * or the mode codes bit in illegalization table equals 1 ** rt is not using illegal command detection. respond in form: reset message error (me) status and transmit status word. or rt is using illegal command detectionand mode code is illegalized. set message error (me) status and transmit status word. dbac bit set. bcast bit reset. dpb bit toggles. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) ilcmd bit set. busid bit updated. merr bit reset. rtrt bit reset. (other error bits reset.) iwa ilcmd iwa mc0 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mc0 is not ndefned when t/ r bit equals 0) no change no message info word is written none * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 124 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. illegalization table bit equals 0 * respond in form: reset message error (me) status and transmit status word. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. illegalization table bit equals 1 ** set message error (me) status and transmit status word. dbac bit set. bcast bit reset. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection
HI-6120, hi-6121 holt integrated circuits 125 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options synchronize without data (mc1): mode code command with mode code 00001 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status word transmit. reset the time tag counter to 0x0000. dbac bit set. bcast bit updated. dpb bit toggles. normal update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr mc1 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. the time tag counter is not reset. dbac bit set. bcast bit updated. dpb bit toggles. normal update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. the time tag counter is not reset. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 126 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit status (mc2): mode code command with mode code 00010 and t/ r bit equals 1 no status word updates, transmit status from last valid command (assuming last command was not a transmit status or a transmit last command mode command. dbac bit set. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa mc2 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb bit toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0 the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. time tag counter is not reset. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0 the illegalization table. bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 127 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options initiate self test (mc3): mode code command with mode code 00011 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. host should initiate self- test then update built-in test word at shared ram address 0x0093. resume terminal execution. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr mc3 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 128 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmitter shutdown (mc4): mode code command with mode code 00100 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set status word bcr bit and suppress status. transmit. after status trans- mission, inhibit the inactive bus: dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on the state of the sdsel bit in confguration register 2. (see description of sdsel and mcopt4 bits in confguration register 2 for further information. when a bus transmitter (or transmitter and receiver) is shut down by mode command, bus status is refected by assertion of a txasd or txbsd bit in the built-in test register at register address 0x0014. if sdsel equals logic 0, an rxasd or rxbsd bit will also be asserted. see built-in test register description for further information. once shutdown, the inactive bus transmitter (or transmitter and receiver can only be reactivated by an override transmitter shutdown mc5 or mc21 or reset remote terminal mc8 mode code command, or by software reset (by setting the srst bit in confguration register 1) or by hardware reset initiated by asserting the mr master reset input pin. mc4 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 129 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options override transmitter shutdown (mc5): mode code command with mode code 00101 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. this command is only used with dual redundant buses. after status transmission, reactivate inactive bus: dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically re-enables transmit and receive for the inactive bus, regardless of the state of the sdsel bit in confguration register 2. the device affrms reenabled bus status by resetting all four txasd, txbsd, rxasd and/or rxbsd bits in the built-in test register at register address 0x0014. note: if the txinha or txinhb input pins are asserted, the device cannot override the resulting hardware transmit inhibit for the affected bus. in this case, the corresponding txasd and/or txbsd bits remain high. see built-in test register description for further information. mc5 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 130 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options inhibit terminal flag bit (mc6): mode code command with mode code 00110 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically sets the tf inhibit bit in the bit word register at address 0x0013. while the tf inhibit bit is set, the device disregards assertion of the terminal flag (tf) bit in the 1553 status bits register (0x0006) and only transmits status with the terminal flag status bit reset. once the terminal flag has been inhibited, it can be reactivated by an override inhibit terminal flag mc7 or reset remote terminal mc8 mode command, by software reset (asserting the srst bit in confguration register 1) or by asserting the mr master reset input pin. mc6 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 131 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options override inhibit terminal flag bit (mc7): mode code command with mode code 00111 and t/ r bit equals 1 default response: reset message error (me) status then transmit status word. if broadcast, set the status word bcr bit and suppress status transmit. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr the device automatically resets the tf inhibit bit in the bit word register at address 0x0013. while the tf inhibit bit is reset, the device transmits status with the terminal flag status bit set if the terminal flag (tf) bit is asserted in the 1553 status bits register (0x0006). mc7 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 132 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options reset remote terminal (mc8): mode code command with mode code 01000 and t/ r bit equals 1 default response: reset message error (me) status. if not broadcast, transmit status word. dbac bit reset. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa ibr after status transmission, the device automatically resets the status message error (me) busy and broadcast command received (bcr) bits in its internal status register. the bit word at shared ram address is reset to 0x0000. if either transmitter was shutdown, the shutdown condition is overridden. if the terminal flag (tf) status bit was inhibited, the inhibit is reset. this command does not reset any of the host-programmed registers that confgure the terminal for operation. to complete the terminal reset process, the host must assert either mr hardware master reset (with or without auto- initialization) or assert the srst bit in confguration register 1 to execute software reset. see following section entitled reset and initialization for additional details. because mc8 requires host interaction, most applications will probably utilize the iwa interrupt to alert the host when received. mc8 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. gaperr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 133 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options reserved mode codes mc9 - mc15: mode code command with mode codes 01001 through 01111 and t/ r bit equals 1 the reserved mode code commands do not have defned terminal actions. host must initialize device to respond using either of the two following methods: the mode codes bit in illegalization table equals 0 * or the mode codes bit in illegalization table equals 1 ** rt is not using illegal command detection. respond in form: reset message error (me) status and transmit status word. or rt is using illegal command detectionand mode code is illegalized. set message error (me) status and transmit status word. dbac bit set. bcast bit updated. dpb bit toggles. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit reset. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) ilcmd bit set. busid bit updated. merr bit set. rtrt bit reset. (other error bits reset.) iwa ilcmd iwa mc9 - mc15 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 134 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit vector word (mc16): mode code command with mode code 10000 and t/ r bit equals 1 default cs response: reset message error (me) and bcr status bits. then transmit status word followed by the data word stored in the assigned index or ping-pong data buffer (or in descriptor word 4 for smcp simplifed mode command processing). dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa mc16 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 135 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options synchronize with data word (mc17): mode code command with mode code 10001 and t/ r bit equals 1 default response: reset message error (me) status. and transmit status word. if broadcast, set bcr status bit and suppress status response. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa device stores received data word in the assigned ping-pong or index data buf fer (or in descriptor word 4 for smcp simplifed mode command processing). confguration register 2 mcopt2 and mcopt3 bits allow automatic time-tag count loading using the data word received. if mcopt2 equals 1, the received data word is automatically loaded to the time-tag counter if the low order bit of the received data word (bit 0 equals 0. if mcopt3 equals 1, the received data word is automatically loaded to the time-tag counter if the low order bit of the received data word (bit 0) equals 1. if both bits are set, the received data word is unconditionally loaded into the time-tag counter. for non-broadcast commands, counter load occurs before status word transmission. mc17 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word followed by data word with manchester encoding or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 136 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit last command (mc18): mode code command with mode code 10010 and t/ r bit equals 1 default response: status is not updated. transmit status word from the previous command, with data word containing the last valid command word (assuming it was not a transmit status or a transmit last command mode command. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa transmitted data word is automatically provided from an internal register, and is copied to assigned index or ping- pong buffer (or to descriptor word 4 for smcp simplifed mode command processing) mc18 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 137 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options transmit bit word (mc19): mode code command with mode code 10011 and t/ r bit equals 1 default response: reset message error (me) and bcr status bits. then transmit status word followed by data word from either bit word register or alternate bit word register, depending on confguration reg. 2 option bit altbitw. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit reset. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa transmitted data word is automatically copied to the assigned index or ping-pong buffer (or to descriptor word 4 for smcp simplifed mode command processing) mc19 exceptions: broadcast address rt31 (broadcast not allowed) no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb toggles. merr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 138 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options selected transmitter shutdown (mc20): mode code command with mode code 10100 and t/ r bit equals 1 default response: reset message error (me) status. and transmit status word. if broadcast, set bcr status bit and suppress status response. this command is intended for use in 1553 systems with more than one dual redundant bus. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa after status word transmission, the device stores received data word in the assigned index or ping-pong buffer (or in descriptor word 4 if smcp simplifed mode command processing applies). if the mcopt4 bit in confguration register 2 equals 0, the received data word is compared to the value in the bus select register corresponding to the inactive bus. for example, if the command is received on bus a, the comparison uses the bus b select register value. if the compared values match, the device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on the state of the sdsel bit in confguration register 2. (see description of sdsel and mcopt4 bits in confguration register 2 for further information. when a bus transmitter (or transmitter and receiver) is shut down by this mode command, bus status is refected by assertion of a txasd or txbsd bit in the built-in test register at register address 0x0014. if sdsel equals logic 0, an rxasd or rxbsd bit will also be asserted. see built-in test register description for further information. if mcopt4 bit in confguration register 2 equals 1, the iwa interrupt is typically used to alert the host when an mc20 command is received. the host must evaluate whether the received mode data word matches the bus selection criteria. if bus selection criteria is met, the host fulflls bus shutdown command using one of two options: 1. set the bus shutdown bit inhbusa or inhbusb for the inactive bus in confguration register 1 to inhibit both transmit and receive, or 2. assert the transmit shutdown input pin txinha or txinhb for the inactive bus to inhibit only transmit. the inactive bus receiver is still active and all valid commands are heeded without transmit. this option is rarely applied. once shutdown, the inactive bus transmitter (or transmitter and receiver) can only be reactivated by an override transmitter shutdown mc5 or mc21 or reset remote terminal mc8 mode code command, or by software reset (by setting the srst bit in confguration register 1) or by hardware reset initiated by asserting the mr master reset input pin. mc20 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none
HI-6120, hi-6121 holt integrated circuits 139 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit updated. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word followed by data word with manchester encoding or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 140 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options override selected transmitter shutdown (mc21): mode code command with mode code 10101 and t/ r bit equals 1 default response: reset message error (me) status. and transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit reset. bcast bit reset. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) iwa after status word transmission, the device stores received data word in the assigned index or ping-pong buffer (or in descriptor word 4 if smcp simplifed mode command processing applies). if the mcopt4 bit in confguration register 2 equals 0, the received data word is compared to the value in the bus select register corresponding to the inactive bus. for example, if the command is received on bus a, the comparison uses the bus b select register value. if the compared values match, the device automatically re-enables transmit and receive for the inactive bus, regardless of the state of the sdsel bit in confguration register 2. the device affrms fully reenabled bus status by resetting all four txasd, txbsd, rxasd and/ or rxbsd bits in the built-in test register at register address 0x0014. note: if the txinha or txinhb input pins are asserted, the device cannot override the resulting hardware transmit inhibit for the af fected bus. in this case, the corresponding txasd and/or txbsd bits remain high. see built-in test register description for further information. if mcopt4 bit in confguration register 2 equals 1, the iwa interrupt is typically used to alert the host when an mc21 command is received. the host must evaluate whether the received mode data word matches the bus selection criteria. if bus selection criteria is met, the host fulflls the override shutdown command using one of two options: 1. reset the bus shutdown bit inhbusa or inhbusb for the inactive bus in confguration register 1 to reenable both transmit and receive, if the host used this bit to shut down transmit and receive for an earlier mc4 or mc20 command. (resetting this shutdown bit does not restore bus transmit capability if a txinha or txinhb input pin is asserted.) or 2. reset the transmit shutdown input pin txinha or txinhb for the inactive bus to re-enable transmit if the host used this pin to shut down transmit only for an earlier mc4 or mc20 command. mc21 exceptions: invalid command word. or t/ r bit equals 0 and umcinv bit in confg. register 1 equals 1 *** no terminal response, the message is ignored. no status word change. (mode code is undefned when t/ r bit equals 0) no change no message info word is written none t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 0 * respond in form: reset message error (me) status. if not broadcast, transmit status word. if broadcast, set the bcr status bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (other error bits reset.) iwa ibr
HI-6120, hi-6121 holt integrated circuits 141 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and umcinv bit in confg. register 1 equals 0. the illegalization table bit equals 1 ** set message error (me) status. if not broadcast, transmit status word. if broadcast, also set status word bcr bit and suppress status response. dbac bit set. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) ilcmd iwa ibr mode code command word not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr mode code command word followed by data word with manchester encoding or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd bit reset. rtrt bit reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection *** undefned mode command rendered invalid by umcinv option bit. command s bit in illegalization table is dont care.
HI-6120, hi-6121 holt integrated circuits 142 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options reserved mode codes mc22 - mc31: mode code commands having mode codes 10110 through 11111 the reserved mode code commands do not have defned actions. host must initialize device to respond using either of the two following methods: the mode codes bit in illegalization table equals 1 ** (rt is using illegal command detection) or the mode codes bit in illegalization table equals 0 * (rt not using illegal command detection, respond in form) mode code is illegalized. set message error (me) status and transmit status word. if t/ r bit equals 1, suppress data word transmission. or if t/ r bit equals 1, reset message error (me) status. transmit status word with contiguous data word read from assigned index or ping- pong buffer (or from descriptor word 4 if the smcp option applies.) if t/ r bit equals 0, reset message error (me) status and transmit status. if broadcast, also set bcr status and suppress status transmit. device stores received data word in assigned index or ping- pong buffer (or in descriptor word 4 if smcp simplifed mode command processing applies). dbac bit set. bcast bit reset. dpb bit toggles. dbac bit set. bcast bit reset. dpb bit toggles. dbac bit reset. bcast bit updated. dpb bit toggles. ilcmd bit set. merr bit set. busid bit updated. rtrt bit reset. (other error bits reset.) normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset. (all error bits reset.) normal cs update: busid bit updated. merr bit reset. ilcmd bit reset. rtrt bit reset (all error bits reset.) ilcmd iwa iwa iwa ibr mc22 - mc31 exceptions: invalid command word. no terminal response, the message is ignored. no status word change. no change no message info word is written none t/ r bit equals 0 and mode code command word is not followed by a contiguous data word (missing data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. wcterr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa ibr
HI-6120, hi-6121 holt integrated circuits 143 circumstances for received message terminal response to received command bits updated in descriptor control word bits updated in data buffer msg info word interrupt options t/ r bit equals 0 and command word is followed by data word with manchester or parity error (bad data word) no status word transmit. set the message error (me) status bit. if broadcast, set the bcr status bit. dbac bit set. bcast bit updated. dpb bit toggles. merr bit set. iwderr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa ibr t/ r bit equals 1 and mode code command word is followed by a contiguous data word no status word transmit. set the message error (me) status bit. dbac bit set. bcast bit reset. dpb bit toggles. merr, wcterr bits set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa t/ r bit equals 1 and mode code command is addressed to rt31 no status word transmit. set the message error (me) and bcr status bits. dbac bit set. bcast bit set. dpb bit toggles. merr bit set. busid bit updated. ilcmd, rtrt bits reset. (other error bits reset.) merr iwa ibr * command is illegal but terminal is not using illegal command detection (in form response). ** command is illegal and terminal is using illegal command detection
HI-6120, hi-6121 holt integrated circuits 144 17.3. dc electrical characteristics v dd = 3.3v, gnd = 0v, t a = operating temperature range (unless otherwise stated) parameters symbol test conditions limits unit min typ max operating voltage v dd 3.15 3.3 3.45 v power supply current see note 1 on next page i cc1 not transmitting - 4 10 ma i cc2 continuous supply current while one bus transmits @ 100% duty cycle, 70 resistive load - 720 760 ma power dissipation see note 2 on next page pd 1 not transmitting - - 60 mw pd 2 transmit one bus @ 100% duty cycle, 70 resistive load - 420 550 mw min. input voltage (hi) v ih digital inputs 70% - - v dd max. input voltage (lo) v il digital inputs - - 30% v dd min. input current (hi) i ih digital inputs - - 20 i dd max. input current (lo) i il digital inputs -20 - - i dd pull up / pull down current i pud digital inputs and data bus - 275 - i dd min. output voltage (hi) v oh i out = -1.0ma, digital outputs 90% - - v dd max. output voltage (lo) v ih i out = 1.0ma, digital outputs - - 10% v dd receiver (measured at point ad in figure 26 unless otherwise specifed) input resistance r in differential 20 - - k input capacitance c in differential - - 5 pf common mode rejection ratio cmrr 40 - - db input level v in differential - - 9 vp-p 17. electrical characteristics 17.1. absolute maximum ratings supply voltage (v dd ) -0.3 v to +5.0 v logic input voltage range -0.3 v to +3.6 v receiver differential voltage 10 vp-p driver peak output current +1.0 a power dissipation at 25c 1.0 w solder temperature 275 o c for 10 sec. junction temperature 175 o c storage temperature -65 o c to +150 o c 17.2. recommended operating conditions operating supply voltage (v dd ) 3.3 vdc 5% operating temperature range industrial extended -40 o c to +85 o c -55 o c to +125 o c note: stresses above absolute maximum ratings or outside recom - mended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended.
HI-6120, hi-6121 holt integrated circuits 145 parameters symbol test conditions limits unit min typ max input common mode voltage v icm -5 - +5 v-pk threshold voltage (direct-coupled) detect v thd 1 mhz sine wave (measured at point ad in figure 26) 1.15 - 20.0 vp-p no detect v thnd - - 0.28 vp-p threshold voltage (transformer-coupled) detect v thd 1 mhz sine wave (measured at point at in figure 27) 0.86 - 14.0 vp-p no detect v thnd - - 0.2 vp-p transmitter (measured at point ad in figure 26 unless otherwise specifed) output voltage direct coupled v out 35 load 6.0 - 9.0 vp-p transformer coupled v out 70 load (measured at point at in figure 27) 18.0 - 27.0 vp-p output noise v on differential, inhibited - - 10.0 mvp-p output dynamic offset voltage direct coupled v dyn 35 load -90 - 90 mv transformer coupled v dyn 70 load (measured at point at in figure 27) -250 - 250 mv output resistance r out differential, not transmitting 10 - - k output capacitance c out 1 mhz sine wave - - 15 pf note 1: in actual use, the highest practical transmit duty cycle is 96%, occurring when a remote terminal responds to a series of 32 data word transmit commands (rt to bc) repeating with minimum intermessage gap of 4s (2s dead time) and typical hi- 6110 rt response delay of 5s. note 2: while one bus continuously transmits, the power delivered by the 3.3v power supply is 3.3v 720ma typical = 2.4w. of this, 420mw is dissipated in the device, the remainder in the load. 17.4. ac electrical characteristics D hi-6121 host bus interface timing v dd = 3.3v, gnd = 0v, t a = operating temperature range (unless otherwise stated) parameters symbol limits units min typ max hi-6121 interface timing (spi host bus interface) sck clock period t cyc 50 - - ns ce set-up time to frst sck rising edge t ces 25 - - ns ce hold time after last sck falling edge t ceh 25 - - ns ce inactive between spi instructions t cph 100 - - ns spi si data set-up time to sck rising edge t ds 10 - - ns spi si data hold time after sck rising edge t dh 10 - - ns sck high time t sckh 25 - - ns sck low time t sckl 100 - - ns so valid after sck falling edge t dv - - 20 ns so high-impedance after ce inactive t chz - - 75 ns
HI-6120, hi-6121 holt integrated circuits 146 ce sclk so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance serial output timing diagram serial input timing diagram ce sclk si msb ces t ds t t dh lsb cph t ceh t figure 21. hi-6121 host bus interface timing diagram 17.5. ac electrical characteristics D HI-6120 host bus interface timing parameters symbol limits units min typ max HI-6120 interface timing (parallel host bus interface) write cycle t wr 55 - - ns read/write inactive time t inact 25 - - ns non-sequential read time t nsr 110 - - ns 8-bit sequential read time t sr8 55 - - ns 16-bit sequential read time t sr16 65 - - ns wait assertion time t was 20 - - ns wait time t w - - 130 ns
HI-6120, hi-6121 holt integrated circuits 147 host write in dual-byte mode (8-bit bus width) showing 2 bytes written for a single 16-bit word using btyp e = 1 ( inte l style - output enable and w rite enable) oe we t wr t inact we cs a0 lb a15:1 address oe we or assertion for the next read or wr it e oe d7:0 wa it byte 0 byte 1 t wr t inact host write in word mode (16-bit bus width) showing a one-word write cycle. successive writes to sequential addresses have same timing. using btyp e = 1 ( inte l style - output enable and w rite enable) oe we all timing intervals equal 0 ns min unless otherwise indicated. all timing intervals equal 0 ns min unless otherwise indicated. we oe cs a15:1 address oe we or assertion for the next read or wr ite d15:0 word wa it t wr t inact figure 22. register and ram write operations for btype = 1
HI-6120, hi-6121 holt integrated circuits 148 d7:0 str r / w wa it a0 lb a15: 1 byte 0 byte 1 address host write in dual-byte mode (8-bit bus width) using btyp e = 0 ( motorol a style - single and r/ direction select ) str w read/w rite strobe str assertion for the next read or wr ite cs t wr t inact t wr t inact host write in word mode (16-bit bus width) d15:0 str cs a15: 1 word address str assertion for the next read or wr ite r / w using btyp e = 0 ( motorol a style - single read/w rite strobe and r/ direction select ) str w wa it t wr t inact showing 2 bytes written for a single 16-bit word all timing intervals equal 0 ns min unless otherwise indicated. showing a one-word write cycle. successive writes to sequential addresses have same timing. all timing intervals equal 0 ns min unless otherwise indicated. figure 23. register and ram write operations for btype = 0
HI-6120, hi-6121 holt integrated circuits 149 t nsr t sr8 after first byte is read, prefetch allows faster access times for successive reads, as long as addresses are sequential . w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thi s a llows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl e i s handled o n a w ait -controlled exception basis. w ait can be optionally inverted. host read in dual-byte mode (8-bit bus width) oe we cs a0 lb a15:1 address t w t wa s wa it d7:0 byte 0 byte 1 high-z high-z high- z using btyp e = 1 (inte l style - output enable and w rite enable) oe we we oe or assertion for the next w rite or read t inact t inact after first word is read, prefetch allows faster access times for successive reads, as long as addresses are sequential. w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thi s a llows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl e i s handled o n a w ait -controlled exception basis. w ait can be optionally inverted. host read in word mode (16-bit bus width) oe cs a15:1 address addres s + 1 we showing two successive words read from sequential addresses using btyp e = 1 (inte l style - output enable and w rite enable) oe we we oe or assertion for the next w rite or read wa it d15:0 word word high-z high-z high- z t nsr t w t wa s t sr16 t inact t inact showing 2 bytes read for a single 16-bit word all timing intervals equal 0 ns min unless otherwise indicated. all timing intervals equal 0 ns min unless otherwise indicated. figure 24. register and ram read operations for btype = 1
HI-6120, hi-6121 holt integrated circuits 150 after first byte is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential. w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thi s allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl e i s handled o n a w ait -controlled exception basis. w ait can be optionally inverted. using btyp e = 0 ( motorol a style - single and r/ direction select ) str w read/w rite strobe str r / w cs a0 lb a15:1 address host read in dual-byte mode (8-bit bus width) str assertion for the next read or wr ite wa it d7:0 byte 0 byte 1 high- z high- z high-z t nsr t sr8 t w t wa s t inact t inact after first word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential. w ait is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. thi s allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycl e i s handled o n a w ait -controlled exception basis. w ait can be optionally inverted. using btyp e = 0 ( motorol a style - single read/w rite strobe and r/ direction select ) str w str cs a15:1 address addres s + 1 r / w host read in word mode (16-bit bus width) str assertion for the next read or wr ite wa it d15: 0 word word high- z high- z high-z t nsr t w t wa s t sr16 t inact t inact showing 2 bytes read for a single 16-bit word all timing intervals equal 0 ns min unless otherwise indicated. all timing intervals equal 0 ns min unless otherwise indicated. showing two successive words read from sequential addresses figure 25. register and ram read operations for btype = 0
HI-6120, hi-6121 holt integrated circuits 151 18. mil-std-1553 bus interface isolatio n t ransformer point ad txinha/b transmitter receiver 1:2.5 55? 55? 35? 2.5:1 55? 55? 35? busa/b busa/b rx data to manchester decoder tx data from manchester encoder isolation t ransformer point ad figure 26. mil-std-1553 direct coupled test circuits rx data to manchester decoder txinha/b transmitter busa/b busa/b 52.5? (.75 zo) 52.5? (.75 zo) 2.5:1 1:2.5 1:1.4 1.4:1 35? (.5 zo) coupling t ransformer coupling t ransformer isolation t ransformer isolation t ransformer receiver 52.5? (.75 zo) 52.5? (.75 zo) 35? (.5 zo) tx data from manchester encoder point at point at figure 27. mil-std-1553 transformer coupled test circuits
HI-6120, hi-6121 holt integrated circuits 152 19. thermal characteristics part number package style condition ja ( o c/w) junction temp, t j ( o c) t a = 25 o c t a = 85 o c t a = 125 o c HI-6120pqx 100-pin pqfp mounted on circuit board 52.7 56 116 156 hi-6121pqx 52-pin pqfp mounted on circuit board 60.9 56 116 156 hi-6121pcx 64-pin qfn heat sink pad unsoldered 31.1 41 101 141 heat sink pad soldered 22.8 37 97 137 20. additional pin / package configurations notes: 1. all vcc, vccp and gnd pins must be connected. 2. see page 1 for hi-6121, 52-pin pqfp package confguration. 20.1. hi-6121pcx (64-pin qfn) top view 64 vcc 61 aut oe n 60 vcc 59 gn d 58 ssysf 57 active 56 ready 55 ttclk 54 ackmes 53 ackhw 52 i 51 50 vcc 49 gn d 63 txinhb 62 txinha nthmes inthw 48 bendi 46 lock 45 mtst off 44 busa 43 vccp 42 vccp 41 40 39 vccp 38 vccp 37 busb 36 35 34 33 test3 47 test test0 test1 test2 busa busb - 1 7 rt ap 18 miso 19 mos i 2 0 vcc 21 vcc 22 gn d 2 3 gn d 2 4 25 eecopy 26 esck 27 ee1k 28 test7 29 test6 30 test5 31 ecs test4 32 gn d 1 com p 2 3 mod e 4 si 5 sck 6 so 7 vcc 8 mclk 9 gn d 10 rt a0 11 rt a1 12 rt a2 13 14 rt a3 15 ce mr rt a4 16 hi-6121pcx
HI-6120, hi-6121 holt integrated circuits 153 20.2. HI-6120pqx (100-pin qfn) top view a3 - 2 6 a4 - 2 7 a5 - 2 8 test5 - 4 7 test4 - 4 8 a13 - 4 9 a14 - 5 0 a6 - 2 9 rt ap - 3 0 miso - 3 1 mos i - 3 2 a7 - 3 3 a8 - 3 4 a9 - 3 5 vcc - 3 6 gnd - 3 7 - 3 8 eecop y - 3 9 esc k - 40 a10 - 4 1 a1 1 - 42 a12 - 4 3 ee1k - 4 4 test7 - 4 5 test6 - 4 6 ecs 100 - d 1 1 99 - d 10 78 - vcc 77 - gnd 76 - d 2 intmes inthw 98 - d 9 97 - txinhb 96 - txinha 95 - a ut oe n 94 - d 8 93 - d 7 92 - d 6 91 - v cc 90 - gnd 89 - d 5 88 - d 4 87 - d 3 86 - ssysf 85 - a ctive 84 - r ead y 83 - ttclk 82 - ackmes 81 - ackh w 80 - 79 - vc c - 1 gnd - 2 d1 2 - 3 - 4 d1 4 - 5 d1 5 - 6 comp - 7 - 8 mode - 9 - 1 0 - 1 1 btype - 1 2 mcl k - 13 gnd - 1 4 w ait - 1 5 r / - 1 6 rt a0 - 1 7 rt a1 - 1 8 rt a2 - 1 9 - 2 0 rt a3 - 2 1 rt a4 - 2 2 a0 - 2 3 a1 - 2 4 a2 - 2 5 ce d1 3 vcc str w mr 75 - d 1 74 - d 0 73 - bend i 72 - test 71 - l ock 70 - m tst of f 69 - b us a 68 - b us a 67 - v ccp 66 - v ccp 65 - 64 - 63 - 62 - 61 - v ccp 60 - 59 - 58 - b us b 57 - test0 56 - test1 55 - 54 - test3 53 - b wid 52 - w pol 51 - a15 busa busa busb busb vccp busb test2
HI-6120, hi-6121 holt integrated circuits 154 21. ordering information part number lead finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no m -55 o c to +125 o c m yes part number package description pq 100 pin plastic quad flat pack, pqfp (100pqs) hi - 6120 pq x x part number lead finish blank tin / lead (sn / pb) solder f 100% matte tin (pb-free, rohs compliant) part number temperature range flow burn in i -40 o c to +85 o c i no t -55 o c to +125 o c t no m -55 o c to +125 o c m yes part number package description pc 64 pin plastic chip-scale package, 9 x 9mm qfn (64pcs) pq 52 pin plastic quad flat pack, pqfp (52ptqs) hi - 6121 px x x
HI-6120, hi-6121 holt integrated circuits 155 22. revision history revision date description of change ds6120, rev. new 11/24/09 initial release rev. a 6/15/10 datasheet format change (table of contents, list of figures, list of tables and cross- references added). inserted new sections to clarify data prefetch operations. minor typos corrected. rev. b 11/18/10 corrected power supply current and device power dissipation values and added explanatory notes.
HI-6120, hi-6121 holt integrated circuits 156 23. package dimensions .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .004 (0.40 ) .10 .281 .006 (7.15 ) .15 .281 .006 (7.15 ) .15 bottom view top view .354 (9.00) bsc 64-pin plastic chip-scale package (qfn) heat sink pad on bottom of package. heat sink must be left floating or connected to v dd . do not connect to gnd. inches (millimeters) package type: 64pcs bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95) d etail a see detail a 0 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6 ) typ .008 (.20) min .005 (.13) r m in r m in .005 (.13) .0256 (.65) bsc .015 .003 (.375 .075 ) .035 .006 (.88 .15) .055 .002 (1.4 .05) .063 (1.6) max. 52-pin plastic quad flat pack (pqfp) inches (millimeters) package type: 52ptqs bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95)
HI-6120, hi-6121 holt integrated circuits 157 detai l a see detail a 0 7 .0197 (0.50) bsc .551 (14.0 ) bsc sq .630 (16.0 ) bsc sq .039 (1.0) typ .008 (0.20) r m ax .003 (0.08) r m in .008 (0.20) mi n .009 .002 (.22 .05) .024 .006 (.60 .15) .059 .004 (1.50 .10) .055 .002 (1.40 .05) 100-pin plastic quad flat pack (pqfp) inches (millimeters) package type: 100pqs bsc = basic spacing between centers is theoretical true position dimension and has no tolerance. (jedec standard 95)

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