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RT9607/a 1 ds9607/a-07 april 2011 www.richtek.com dual channel synchronous-rectified buck mosfet driver ordering information general description the RT9607/a is a dual power channel mosfet driver specifically designed to drive four power n-mosfets in a synchronous-rectified buck converter topology. these drivers combined with richtek ? s series of multi-phase buck pwm controllers provide a complete core voltage regulator solution for advanced microprocessors. the RT9607/a can provide flexible gate driving for both high side and low side drivers. this gives more flexibility of mosfet selection. the output drivers of the part are capble to driver a 3nf load in 30/40ns rising/falling time with fast propagation delay from input transition to the gate of the power mosfet. this device implements bootstrapping on the upper gates with only a single external capacitor required for each power channel. this reduces implementation complexity and allows the use of higher performance, cost effective, n-mosfets. adaptive shoot-through protect-ion is integrated to prevent both mosfets from conducting simultaneously. t he RT9607/a can detect high side mosfet drain-to- source electrical short at power on and pull the 12v power by low side mos and cause power supply to go into over current shutdown to prevent damage of cpu. RT9607 has longer ugate/lgate dead time which can drive the mosfets with large gate rc value, avoiding the shoot-through phenomenon. RT9607a is targeted to drive small gate rc value mosfets and performs better efficiency. features z z z z z drives four n-mosfets z z z z z adaptive shoot-through protection z z z z z propagation delay 40ns z z z z z support high switching frequency z z z z z fast output rise time z z z z z 5v to 12v gate-drive voltages for optimal efficiency z z z z z tri-state input for bridge shutdown z z z z z supply under-voltage protection z z z z z rohs compliant and 100% lead (pb)-free applications z core voltage supplies for motherboard/desktop pc microprocessor core power z high frequency low profile dc-dc converters z high current low voltage dc-dc converters note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information for marking information, contact our sales representative directly or through a richtek distributor located in your area. RT9607/a lead plating system p : pb free g : green (halogen free and pb free) package type qv : vqfn-16l 3x3 (v-type) s : sop-14 short dead time long dead time
RT9607/a 2 ds9607/a-07 april 2011 www.richtek.com typical application circuit pin configurations (top view) pwm1 pwm2 gnd lgate1 pvcc pgnd lgate2 phase2 ugate2 boot2 boot1 ugate1 phase1 vcc 2 3 4 11 12 13 14 5 6 7 8 9 10 sop-14 vqfn-16l 3x3 boot1 ugate1 phase1 lgate1 vcc pvcc pwm1 pwm2 RT9607/a 11 14 5 1 2 4 13 12 ugate2 phase2 lgate2 boot2 gnd pgnd optional 12v 12v 7 8 9 optional v core 3 6 10 from controller pwm1 from controller pwm2 gnd ugate1 ugate2 boot2 boot1 pgnd nc lgate1 nc pvcc lgate2 phase2 phase1 pwm2 pwm1 vcc 12 11 10 9 13 14 15 16 1 2 3 4 8 7 6 5 gnd 17
RT9607/a 3 ds9607/a-07 april 2011 www.richtek.com functional pin description pin no. RT9607/a s RT9607/a qv pin name pin function 1 15 pwm1 channel 1 pwm input. 2 16 pwm2 channel 2 pwm input. 3 1 gnd ground pin. 4 2 lgate1 lower gate drive of channel 1. 5 5 pvcc upper and lower gate driver power rail. 6 4 pgnd lower gate driver ground pin. 7 6 lgate2 lower gate drive of channel 2. 8 7 phase2 connect this pin to phase point of channel 2. phase point is the connection point of high side mosfet source 9 9 ugate2 upper gate drive of channel 2. 10 10 boot2 floating bootstrap supply pin of channel 2. 11 11 boot1 floating bootstrap supply pin of channel 1. 12 12 ugate1 upper gate drive of channel 1. 13 13 phase1 connect this pin to phase point of channel 1. phase point is the connection point of high side mosfet source 14 14 vcc control logic power supply. -- 3, 8 nc no connection. -- exposed pad (17) gnd the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. timing diagram pwm ugate lgate t pdhugate t pdllgate t pdlugate t pdhlgate 90% 90% 2v 2v 2v 2v
RT9607/a 4 ds9607/a-07 april 2011 www.richtek.com function block diagram shoot-through protection power-on ovp shoot-through protection pvcc pgnd control logic shoot-through protection power-on ovp shoot-through protection pvcc pgnd pvcc vcc pwm1 internal 5v r r pwm2 internal 5v r r gnd boot1 ugate1 phase1 lgate1 pgnd boot2 ugate2 phase2 lgate2 pvcc
RT9607/a 5 ds9607/a-07 april 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max units vcc supply current bias supply current i vcc f pwm = 250khz, v pvcc = 12v, c boot = 0.1 f, r phase = 20 -- 5.5 8.0 ma power supply current i pvcc f pwm = 250khz, v pvcc = 12v, c boot = 0.1 f, r phase = 20 -- 5.5 10.0 ma power-on reset v cc rising threshold -- 8.0 -- v hysteresis -- 1.0 -- v recommended operating conditions (note 4) z supply voltage, v cc ------------------------------------------------------------------------------------- 12v 10% z junction temperature range --------------------------------------------------------------------------- 0 c to 125 c z ambient temperature ran ge --------------------------------------------------------------------------- 0 c to 70 c (recommended operating conditions, t a = 25 c unless otherwise specified) to be continued absolute maximum ratings (note 1) z supply voltage, v cc ------------------------------------------------------------------------------------- 15v z supply voltage, pv cc ----------------------------------------------------------------------------------- v cc + 0.3v z boot voltage, v boot -v phase ------------------------------------------------------------------------- 15v z input voltage, v pwm -------------------------------------------------------------------------------------- gnd - 0.3v to 7v z phase to gnd dc ------------------------------------------------------------------------------------------------------------ ? 5v to 15v < 200ns ----------------------------------------------------------------------------------------------------- ? 10v to 30v z boot to gnd dc ------------------------------------------------------------------------------------------------------------ ? 0.3v to v cc + 15v < 200ns ----------------------------------------------------------------------------------------------------- ? 0.3v to 42v z ugate ------------------------------------------------------------------------------------------------------ v phase - 0.3v to v boot + 0.3v z lgate ------------------------------------------------------------------------------------------------------ gnd - 0.3v to v pvcc + 0.3v < 200ns ----------------------------------------------------------------------------------------------------- ? 2v to v cc + 0.3v z power dissipation, p d @ t a = 25 c vqfn ? 16l 3x3 -------------------------------------------------------------------------------------------- 1.471w sop-14 ----------------------------------------------------------------------------------------------------- 0.909w z package thermal resistance (note 2) vqfn ? 16l 3x3, ja -------------------------------------------------------------------------------------- 68 c/w sop-14, ja ----------------------------------------------------------------------------------------------- 110 c /w z storage temperature range --------------------------------------------------------------------------- ? 40 c to 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------------- 260 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------- 200v
RT9607/a 6 ds9607/a-07 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity test board (2s2p,4-layers) of jedec 51-7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max units pwm input maximum input current v pwm = 0 or 5v -- 500 -- a pwm floating voltage v cc = 12v -- 2.5 -- v pwm rising threshold 3.3 3.7 4.3 v pwm falling threshold 1.0 1.26 1.5 v output ugate rise time t rugate v pvcc = v vcc = 12v, 3nf load -- 30 -- ns ugate fall time t fugate v pvcc = v vcc = 12v, 3nf load -- 40 -- ns lgate rise time t rlgate v pvcc = v vcc = 12v, 3nf load -- 30 -- ns lgate fall time t flgate v pvcc = v vcc = 12v, 3nf load -- 30 -- ns RT9607 -- 75 -- RT9607a t pdhugate -- 25 -- t pdlugate v boot = v phase = 12v see timing diagram -- 40 -- t pdhlgate -- 20 -- propagation delay RT9607/a t pdllgate see timing diagram -- 35 -- ns shutdown window 1.0 -- 4.3 v ugate drive source r ugatesr v boot ? v phase = 12v -- 1.8 -- ugate drive sink r ugatesk v boot ? v phase = 12v -- 1.7 -- lgate drive source r lgatesr v cc = 12v -- 1.5 -- lgate drive sink r lgatesk v cc = 12v -- 1.4 --
RT9607/a 7 ds9607/a-07 april 2011 www.richtek.com typical operating characteristics dead time at lgate falling time (50ns/div) no load, phase2 phase lgate ugate (5v/div) dead time at lgate rising time (25ns/div) phase lgate ugate (5v/div) full load (60a), phase1 dead time at lgate rising time (25ns/div) phase lgate ugate (5v/div) full load (60a), phase2 for RT9607 dead time at lgate falling time (50ns/div) no load, phase1 phase lgate ugate (5v/div) dead time at lgate falling time (25ns/div) full load (60a), phase1 phase lgate ugate (5v/div) dead time at lgate falling time (25ns/div) phase lgate ugate (5v/div) full load (60a), phase2
RT9607/a 8 ds9607/a-07 april 2011 www.richtek.com dead time at lgate rising time (50ns/div) no load, phase1 phase lgate ugate (5v/div) dead time at lgate rising time (50ns/div) no load, phase2 phase lgate ugate (5v/div)
RT9607/a 9 ds9607/a-07 april 2011 www.richtek.com for RT9607a dead time at lgate rising time (25ns/div) full load (60a), phase2 phase lgate ugate (5v/div) lgate - phase dead time at lgate rising time (25ns/div) full load (60a), phase1 phase lgate ugate (5v/div) lgate - phase dead time at lgate falling time (25ns/div) full load (60a), phase2 phase lgate ugate (5v/div) lgate - phase dead time at lgate falling time (25ns/div) full load (60a), phase1 phase lgate ugate (5v/div) lgate - phase dead time at lgate falling time (25ns/div) no load , phase2 phase lgate ugate (5v/div) lgate - phase dead time at lgate falling time (25ns/div) no load , phase1 phase lgate ugate (5v/div) lgate - phase
RT9607/a 10 ds9607/a-07 april 2011 www.richtek.com dead time at lgate rising time (25ns/div) no load, phase2 phase lgate ugate (5v/div) lgate - phase dead time at lgate rising time (25ns/div) no load, phase1 phase lgate ugate (5v/div) lgate - phase
RT9607/a 11 ds9607/a-07 april 2011 www.richtek.com application information the RT9607/a ha s power on protection function which held ugate and lgate low before vcc up cross the rising threshold voltage. after the initialization, the pwm signal takes the control. the rising pwm signal first forces the lgate signal turns low then ugate signal is allowed to go high just after a non-overlapping time to avoid shoot- through current. the falling of pwm signal first forces ugate to go low. when ugate and phase signal reach a predetermined low level, lgate signal is allowed to turn high. the non-overlapping function is also presented between ugate and lgate signal transient. the pwm signal is recognized as high if above rising threshold and as low if below falling threshold. any signal level in this window is considered as tri-state, which causes turn-off of both high side and low-side mosfet. when pwm input is floating (not connected), internal divider will pull the pwm to 1.9v to give the controller a recognizable level. the maximum sink/source capability of internal pwm reference is 60 a. the pvcc pin provides flexibility of both high side and low side mosfet gate drive voltages. if 8v, for example, is applied to pvcc, then high side mosfet gate drive is 8v to 1.5v (approximately, internal diode plus series resistance voltage drop). the low side gate drive voltage is exactly 8v. the RT9607/a imple ments a power on over-voltage protection function. if the phase voltage exceeds 1.5v at power on, the lgate would be turn on to pull the phase low until the phase voltage goes below 1.5v. such function can protect the cpu from damage by some short condition happened before power on, which is sometimes encountered in the m/b manufacturing line. non-overlap control to prevent the overlap of the gate drives during the ugate turn low and the lgate turn high, the non-overlap circuit monitors the voltages at the phase node and high side gate drive (ugate-phase). when the pwm input signal goes low, ugate begins to turn low (after propagation delay). before lgate can turn high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.2v. once the monitored voltages fall below 1.2v, lgate begins to turn high. for short pulse condtion, if the phase pin had not gone high after lgate turns low, the lgate has to wait for 200ns before turn high only under short pulse (t on <60ns) condition. by waiting for the voltages of the phase pin and high side gate drive to fall below 1.2v, the non-overlap protection circuit ensures that ugate is low before lgate turns high. also to prevent the overlap of the gate drives during lgate turn low and ugate turn high, the non-overlap circuit monitors the lgate voltage. when lgate go below 1.2v, ugate is allowed to go high. driving power mosfets the dc input impedance of the power mosfet is extremely high. when v gs at 12v (or 5v), the gate draws the current only few nanoamperes. thus once the gate has been driven up to ? on ? on level, the current could be negligible. however, the capacitance at the gate to source terminal should be considered. it requires relatively large currents to drive the gate up and down 12v (or 5v) rapidly. it also required to switch drain current on and off with the required speed. the required gate drive currents are calculated as follows. figure1. the gate driver must supply i gs to c gs and i gd to c gd v o gnd l d2 s2 c gs2 g2 i g2 i gd2 i gs2 c gd2 c gs1 c gd1 i gd1 i gs1 i g1 d1 s1 d1 d1 g1 vi +12v +12v t t vg2 vg1 vphase
RT9607/a 12 ds9607/a-07 april 2011 www.richtek.com according to the desi gn of RT9607/a, be fore driving the gate of the high side mosfet up to 12v (or 5v), the low side mosfet has to be off; and the high side mosfet is turned off before the low side is turned on. from figure 1, the body diode " d 2 " had been turned on before high side mosfets turned on before the low side mosfet is turned on, the c gd2 have been charged to vi. thus, as c gd2 reverses its polarity and g 2 is charged up to 12v, the required current is it is helpful to calculate these currents in a typical case. assume a synchronous rectified buck converter, input voltage v i = 12v, v g1 = v g2 = 12v. the high side mosfet is phb83n03lt whose c iss = 1660pf, c rss = 380pf,and t r = 14ns. the low side mosfet is phb95n03lt whose c iss = 2200pf, c rss = 500pf, and t r = 30ns, from the equation (1) and (2) we can obtain the total current required from the gate driving source is ig1 = igs + igd1 = (1.428 + 0.326) = 1.745a (9) ig2 = igs2 + igd2 = (0.88 + 0.4) = 1.28a (10) by a similar calculation, we can also get the sink current required from the turned off mosfet. layout consider figure 2. shows the schematic circuit of a two-phase synchronous-buck converter to implement the RT9607/a. th e converter operates for the input rang from 5v to 12v. when layout the pc board, it should be very careful. the power-circuit section is the most critical one. if not configured properly, it will generate a large amount of emi. the junction of q1, q2, l2 and q3, q4, l4 should be very close. the connection from q1, and q3 drain to positive sides of c1, c2, c3, and c4; the connection from q2, and q4 source to the negative sides of c1, c2, c3, and c4 should be as short as possible. next, the trace from ugate1, ugate2, lgate1, and lgate2 should also be short to decrease the noise of the driver output signals. phase1 and phase2 signals from the junction of the power mosfet, carrying the large gate drive current pulses, should be as heavy as the gate drive trace. the bypass capacitor c7 should be connected to pgnd directly. furthermore, the bootstrap capacitors (c b1 , c b2 ) should always be placed as close to the pins of the ic as possible. select the bootstrap capacitor figure 3. shows part of the bootstrap circuit o f RT9607/a. the v cb (the voltage difference between boot1 and phase1 on RT9607/a) provides a voltage to the gate of the high side power mosfet. this supply needs to be ensured that the mosfet can be driven. for this, the capacitance c b has to be selected properly. it is in figure 1, the current i g1 and i g2 are required to move the gate up to 12v.the operation consists of charging c gd and c gs . c gs1 and c gs2 are the capacitances from gate to source of the high side and the low side power mosfets, respectively. in general data sheets, the c gs is referred as ? c iss ? which is the input capacitance. c gd1 and c gd2 are the capacitances from gate to drain of the high side and the low side power mosfets, respectively and referred to the data sheets as "c rss ," the reverse transfer capacitance. for example, t r1 and t r2 are the rising time of the high side and the low side power mosfets respectively, the required current i gs1 and i gs2 , are showed below r2 gs2 g2 gs2 gs2 r1 gs1 g1 gs1 gs1 t 12 x c dt dv c i t 12 x c dt dv c i = = = = (1) (2) 0.88a 12 x 10 x 2200 i 1.428a 12 x 10 x 1660 i 9 - 10 x 30 12 - gs2 9 - 10 x 14 -12 gs1 = = = = (6) (5) r2 i gd2 gd2 gd2 t 12v v c dt dv c i + = = (4) r1 gd1 g1 gd1 t 12v c dt dv c i = = (3) 0.4a 10 x 30 12) (12 x 10 x 500 i 0.326a 10 x 14 12 x 10 x 380 i 9 - 12 - gs2 9 - -12 gs1 = + = = = (8) (7) from equation. (3) and (4)
RT9607/a 13 ds9607/a-07 april 2011 www.richtek.com figure 2. two- phase synchronous-buck converter circuit determined by following constraints. in practice, a low value capacitor c b will lead the overcharging that could damage the ic. therefore to minimize the risk of overcharging and reducing the ripple on v cb , the bootstrap capacitor should not be smaller than 0.1 f, and the larger the better. in general design, using 1 f can provide better performance. at least one low-esr capacitor should be used to provide good local de-coupling. here, to adopt either a ceramic or tantalum capacitor is suitable. vin c b v cb + - boot1 pvcc pvcc ugate1 phase1 lgate1 pgnd figure 3. part of bootstrap circuit of RT9607/a boot1 ugate1 phase1 lgate1 vcc pvcc pwm1 pwm2 RT9607/a 11 14 5 1 2 4 13 12 ugate2 phase2 lgate2 boot2 gnd pgnd 10 1uf 12v 1uf phb83n03lt phb95n03lt 2uh 1uf 1000uf 1.2uh 12v 7 8 9 phb83n03lt phb95n03lt 2uh 1uf 1000uf 1uf v core 1500uf 1500uf 3 6 l1 c1 l2 c5 c6 q3 q4 l3 c3 c4 q2 q1 c2 cb1 d1 d2 cb2 r1 c7 pwm1 pwm2 10 v in
RT9607/a 14 ds9607/a-07 april 2011 www.richtek.com outline dimension a a1 a3 d e 1 d2 e2 l b e see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.800 1.000 0.031 0.039 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 1.300 1.750 0.051 0.069 e 2.950 3.050 0.116 0.120 e2 1.300 1.750 0.051 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 v-type 16l qfn 3x3 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2
RT9607/a 15 ds9607/a-07 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. a b f j d c i h m dimensions in millimeter s dimensions in inches symbol min max min max a 8.534 8.738 0.336 0.344 b 3.810 3.988 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.508 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.178 0.254 0.007 0.010 i 0.102 0.254 0.004 0.010 j 5.791 6.198 0.228 0.244 m 0.406 1.270 0.016 0.050 14 ? lead sop plastic package

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