optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 1 of 10 optrex america, inc. 46723 five mile road plymouth, mi 48170 usa 734.416.8500 www.optrex.com table of contents 1.0 references ----------------------------------------------------------------------------------------------2 2.0 descript ion ----------------------------------------------------------------------------------------------2 3.0 principles of operation--------------------------------------------------------------------------2 4.0 mechanical -----------------------------------------------------------------------------------------------3 5.0 electrical ------------------------------------------------------------------------------------------------3 6.0 software--------------------------------------------------------------------------------------------------8 7.0 handling reco mmendations ----------------------------------------------------------------- 10 8.0 specification errata ----------------------------------------------------------------------------- 10 revision history rev date page comment first edition written by engineering div 5/21/2008 reviewed by engineering div revision a document number approved by engineering div application note oai-80018aa-7603 approved by customer type no T-55264GD057J-FW- & t-55265gd057j-lw-series 320rgb x 240tft graphic displays http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 2 of 10 1.0 references (a) T-55264GD057J-FW-abn lcd module tech nical specification rev 1 dated 4/25/2008 http://www.optrex.com/siteim ages/partlist/spec/55264ab.pdf (b) t-55265gd057j-lw-abn lcd module tech nical specification rev 1 dated 4/15/2008 http://www.optrex.com/siteim ages/partlist/spec/55265ab.pdf 2.0 description 2.1. this application note provides guidance fo r interfacing, programming, and using the t-55264 and t-55265-series displays. this document, along with the lcd module specification, references (a) and (b), provides the application information needed design the display into electronic products. this document is not intended to be the sole source of guidance for using the display. 2.2. the lcd module drawing provides size and inform ation for the connector(s) built in the product. the drawing does not provide the source for flexible printed circuits (fpc) that mate to the zero- insertion force (zif) connectors since there are many potential sources available. the drawings are provided within references (a) and (b). 2.3. the lcd module technical specification pr ovides electrical and optical performance specifications, cosmetic specificat ions, and qualification information. 2.4. the t-55264- & t-55265-series displa ys include the following components: ? 262k color thin film transistor (tft) liquid crystal display panel. ? either a white cold cathode fluorescent lamp (ccfl) backlight [t-55264] or white light emitting diode (led) backlight [t-55265]. ? tft timing controller, source drivers and gate driver. ? dc-to-dc boost circuits to generate gate and sour ce driver voltages. the displays require a single 3.3 vdc source. 2.5. the displays require additional components to integrate into the end unit: ? ccfl backlight inverter (t-55264) or le d power supply / led driver (t-55265). ? interconnect flat flex cable or flexible printed circuit. ? mounting screws ? lcd controller. 3.0 principles of operation 3.1. a microprocessor writes to an lcd controller to configure it for operation. the configuration data tells the device the polarity and sequencing of control signals and their timing. the microprocessor then writes or ports image data to the lcd controller for storage in ram. the controller reads the ram and automatically gener ates the control signals to write data to the display. there are 18 data bits in ram for each pixel location (6 red, 6 green, and 6 blue). 18 data bits are latched into the display with each pixel clock. the controller generates control signals to tell t he display when to begin writing a new line (hsyc) and when to start writing a new page (vsyc). the de na signal controls the horizontal position of the data on the page. the source driver in the display takes the dat a and performs a digital to analog voltage conversion on the groups of six bits. the corresponding driv e voltage controls the twist of the liquid crystal and thus the light passage through it. with 6 bits of data, 64 gray shades are generated for each red, green, and blue sub-pixel, within a pixel. there are 262 k combinations or red, green, and blue shades possible. http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 3 of 10 3.2. tft displays use tn-mode liquid crystals. temperature compensation is not required as for passive lcds. 3.3. lcd controllers are often built-in microprocess ors. .this design is often found on arm-based devices, high end microprocessors, and sy stem on a chip (soc) designs. sources for external lc d controller include: seiko epson lcd controllers fujitsu graphics controllers toshiba automotive graphics controllers 4.0 mechanical 4.1. the display is attached via 4 screws on the rear side. the screws self-tap into the polycarbonate internal frame. the recommended screw sizes are: display thread diameter & type max depth max torque t-55264 m3, self-tapping 4.0 mm 0.5 to 0.56 n-m (4.4 to 5.0 pound-inch) t-55265 m3, self-tapping 9.3 mm 0.5 to 0.56 n-m (4.4 to 5.0 pound-inch) 4.2. the connection between the disp lay and the customers pcb is via a flexible printed circuit (fpc) or flat flexible cable (ffc). the thickness of of the fpc / ffc is set by the connector mounted to the display. the fpc / ffc must be 0. 3 mm thick at the contact point stiffener. caution the fpc / ffc must not tightly bend and permanently deform the copper traces (form a crease). during bending, the inner side of the copper traces are compressed while the outer side is placed in tension; fracturing the trace and electrically opening the circuit. the minimum bend radius should be 10 times the thickness of the fpc / ffc to prevent permanent deformation. typical fpc are rated 0.3 mm thick at the contact point stiffener. this is not the bending point. most fpc are thinner away from that point. for an fpc that is 0.120 mm thick in the bend area, the minimum bend radius is 1.2 mm for a 90 degree bend. a 180 bend requires a larger radius to prevent creasing. small radius bends greater than 90 should be formed once and not unbent. 5.0 electrical 5.1. interface connection & voltages 5.1.1. the displays interface via a 33-conducto r fpc / ffc to zif connector mounted to the display. kyocera elco 08-6210-033-340-800 ? 33 pin, zero insertion force (zif), right angle, bottom contact, surface mount, 0.5 mm pitch fp c, 0.30 mm thick, with front slide lock. 5.1.2. a major design consideration for the custom er?s pcb is the contact location in the mating connector. the display zif has contacts on the bottom (pcb) side. the designer must take fpc bending and connector location into account and choose the correct contact location when selecting connectors. if the fpc exits straight from the display with no bends, then a top contact connector is required. if a single 180-degree bend is made, then a bottom http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 4 of 10 contact connector is re quired. sources for compatible connectors, in addition to the avx elco, are: molex 54132-3397 ? 33 pin, zero insertion force (zif), right angle, bottom contact, surface mount, 0.5 mm pitch fpc, 0.30 mm thick, with front slide lock. omron xf2m-3315-1a ? 33 pin, zero insertion force (zif), right angle, top & bottom contact, surface mount, 0.5 mm pitch fpc, 0.30 mm thick, with rear rotary lock. these part numbers are presented for inform ation only. optrex has not tested the performance and reliability of these connectors and makes no warranty to their fitness for use. please note that any connector matc hing the fpc pitch characteristics and mating tolerances may be used. 5.1.3. sources for t he ffc / fpc include: http://www.parlex.com/products/ffc.php http://www.circoflex.com/ http://www.innovative-circuits.com/index.htm these manufacturers are presented for inform ation only. optrex has not tested the performance and reliability of their products and makes no warranty to their fitness for use. please note that any fpc must matc h the connector pitch characteristics and mating tolerances. 5.2. signal timing 5.2.1. the timing values needed to operate the display are programmed into the lcd controller registers. please consult references (a) and (b) for the values. please note timing characteristics are dependent upon the tft timing controller (tcon) used. this means the timing for a 320rgb x 240 tft can vary between manufacturers . 5.2.2. t-55264 and t-55265 latch dat a on the rising edge of the clock . this may differ from the timing output of the lcd controller design. optrex highly recommends careful study of the lcd controller specification to determine the timing it expects the display to use. figure 1 shows a timing diagram from an lcd controller. th is definition shows the lcd controller expects the display to latch data on t he negative clock edge. with this definition, the clock signal requires inversion to meet the display data setup and hold time requirements. the seiko epson s1d13706 controller has this definition. figure 1 -- clock / data reference 1 2 3 320 t data setup t data hold reference to negative transition indicates controller expects display to latch on negative edge. if controller has this definition, invert display clock . invalid invalid clk data http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 5 of 10 inverter sn74aupg06 (low-power single inverter buffer/driver with open drain outputs) has been successfully used with the t-55264 & t-55265. figure 2 shows the timing for a seiko eps on s1d13706 lcd controller. this controller expects the display to latch t he data on the negative clock edge ( red line ). note the clock negative edge occurs in the middle of the data ( green line ). the vertical dashed lines show the data setup time for the display is about 6 ns which violates the timing and the display cannot sync up to the image data. the inverted clock (purple line) has about 75 us of setup between the positive edge of the clock and data and does operate correctly. figure 2 -- s1d13706 clk to data with clock & inverted clock http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 6 of 10 5.3. electrical connections to lcd controller figure 3 -- t-55264 / t-55265 interface connections 5.4. the display bezel is internally connected to ground. there is no need for a chassis ground. 5.5. t-55264 ccfl backlight 5.5.1. the t-55265 backlight uses a jst bhr-03vs-1 connector. this is a wire to board, disconnectable, crimp pin connector using the bh housing with three pins at 4.0 mm pitch. the mating connector is: jst sm03(4.0)b-bhs-1-tb ? a 3-pin surface-mount, right-angle, shrouded pin header with 4.0 mm pitch. the housing is polarized to prevent improper insertion. the ?03? indicates three circuits are populated and the ?(4.0)? indicates pin pitch. 5.5.2. the customer must supply an inverter of correct rating to drive the backlight. the following are inverter sources: tdk cxa-0490 ? dc to ac inverter, 12 v input, dimming, with open lamp protection and matching ccfl output connector. lcd controller s1d13706 fpdat[17:0] fpframe fpline fpshift drdy gpo display t-55264 / t-55265 data vsyc hsyc clk (note 1) enab vdd u/d (note 2) l/r (note 2) u/d = 1 r/l = 0 u/d = 1 r/l = 1 u/d = 0 r/l = 0 u/d = 0 r/l = 1 notes: 1. inverter may not be required for other lcd controllers. see section 5.2.2. 2. set the u/d & r/l pins to select dat a scanning direction. by using this feature and rotating the display, it is possible to orient the display for best viewing as needed for the application. rotate display http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 7 of 10 tdk cxa-l10l ? dc to ac inverter, board-mount, 5 /12 v input, non-dimming, with pin connections. microsemi lxmg1617a-05-41 ? dc to ac inverter, 5 v input, dimming, with open lamp & short circuit protection, programmable current limiting and matching ccfl output connector. microsemi lxmg1612-12-01 ? dc to ac inverter, 12 v input, dimming, with open lamp & short circuit protection, programmable current limiting and matching ccfl output connector. erg 8m class -- dc to ac inverter, 5 or 12 v input, dimming, and matching ccfl output connector. erg utilizes standard inverter designs and customizes the magnetics to the desired output characteristics. 5.5.3. the backlight drive voltage should be ener gized after the lcd is configured and placed in operation to hide optical effects caused by startup with undefined data in the ram. likewise, the backlight should be powered off before the the display during shutdown. 5.6. t-55265 led backlight 5.6.1. the t-55265 backlight uses a jst shl connector. this is a wire to board, 1 mm pitch, crimp pin connector using the shlp-6 housing. the mating connector is a 6-pin header. jst sm06b-shsl-tf ? 6-pin, 1.0 mm pitch top entry, shrouded header. the mechanical drawing schematic shows resi stors; these are populated with zero ohm values. the designer must limit drive current. 5.6.2. the backlight power supply can be designed to implement fixed luminance or dimming via pulse width modulation techniques. since there ar e three individual series led circuits, it is best to drive each individually with a current controlled source. do not use a constant current drive source with the led strings tied in parallel. if one led fails, the c urrent source will drive the remaining operational strings with excessive current and fail the backlight. if the designer wishes to tie all three led strings in parallel, use a constant voltage source. with a voltage source, the designer must limit drive current to protec t the leds, the current- limiting resistor must meet the criteria of equation 1 and have adequate power rating. equation 1 ? current limiting resistor calculation the values of v f and i f are found in section 7 of the lcd module technical specification. pwm techniques may be used to control luminance. the high temperature current derating curve must be followed. 5.6.3. led driver ics are a good option for driving the backlight. these ics provide dc to dc boost, dimming, and current limiting capability while minimizing external component size and count. there are numerous sources found by searching ?white led driver? on the internet. 5.6.4. the backlight drive voltage should be ener gized after the lcd is configured and placed in operation to hide optical effects caused by startup with undefined data in the ram. likewise, the backlight should be powered off before the the display during shutdown. f f i r v v supply ? http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 8 of 10 6.0 software 6.1. the t-55264 and t-55265 displays are not prog rammable. there is no software programming for the display itself. 6.2. an lcd controller is required to drive the di splay. the following timing definition and register values apply for a seiko epson s1d13706 lcd controller. figure 4 -- seiko epson s1d 13706 timing definitions register name id value comment memory clock configuration 0x04 0x00 set bclk to mclk ratio = 1:1 (20 mhz). pixel clock configuration 0x05 0x22 set pclk source to clk1 divided by 3 to obtain (20 mhz / 3 = 6.7 mhz). this gives a 58.8 hz scan rate. panel type 0x10 0x69 tft panel, 18- bit data width, color lcd. horizontal total 0x12 50 ht = {[(320 + 68+ 20) / 8] ? 1} = 50 (th from optrex spec.) horizontal display period 0x14 39 hdp = [(320 / 8) ? 1] = 39 (th d from optrex spec.) horizontal display 0x16 68 hdps = 68 hdps hps hpw hdp ht vdps vdp vps vpw vt kyocera tcg057qv1 optrex t-55264 & t-55265 h s y c vsyc http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 9 of 10 register name id value comment period start position register 0 (the from optrex spec). bits d0 ? d7 are used. bits d8 and d9 are entered in register 0x17. horizontal display period start position register 1 0x17 0x00 see above. vertical total register 0 0x18 0x05 vt = [(240 + 18+ 4) ? 1] = 261 (0x0105). bits d0 ? d7 are used. bits d8 and d9 are entered in register 0x19. vertical total register 1 0x19 0x01 see above. vertical display period register 0 0x1c 239 vdp = (240 ? 1) = 239. (tv d from optrex spec). bits d0 ? d7 are used. bits d8 and d9 are entered in register 0x1d. vertical display period register 1 0x1d 0 see above. vertical display period start position register 0 0x1e 18 vdps = 18 (tv ds from optrex spec.). bits d0 ? d7 are used. bits d8 and d9 are entered in register 0x1f. vertical display period start position register 1 0x1f 0x00 see above. fpline pulse width 0x20 0x1d hpw = (30 ? 1) = 29. (th s from optrex spec). hsyc polarity set active low. fpline pulse start position register 0 0x22 0x00 hps = 0. bits d0 ? d7 are used. bits d8 and d9 are entered in register 0x23. fpline pulse start position register 1 0x23 0x00 see above. fpframe pulse width 0x24 0x02 vpw = (3 -1)= 2. (tv s from optrex spec). vsyc polarity active low. fpframe pulse start position register 0 0x26 0x01 vps = 1. bits d0 ? d7 are used. bits d8 and d9 are entered in register 0x27. fpframe pulse start position register 1 0x27 0x00 see above. display mode 0x70 0xc3 64 shades per color operation (256 k colors total), normal image display, dithering on, display image blanked. change to 0x83 to display image. 6.3. replacing kyocera tcg057qv1 display 6.3.1. the clock must be inverted. http://www..net/ datasheet pdf - http://www..net/
optrex america oai-80018aa-7603-a application note t-5526 4gd057j-fw- & t-55265gd057j-lw-series page 10 of 10 6.3.2. the following software values must be cha nged to move the image starting position. see figure 4 . 6.3.2.1. the typical ht periods differ. increase ht from 400 to 408. 6.3.2.2. increase hdps from 7 pixels to 68 pixels. 6.3.2.3. increase the vdps from 7 lines to 18 lines. 7.0 handling recommendations 7.1. fpc & wire handling precautions ? do not pick the display up by the fpc tail. this action can break the electrical connection to the zif connector or peel the connector from the pcb. ? do not pull the fpc. ? do not bend the fpc tight and form creases. this will fracture the copper traces and cause an open circuit. ? do not pick the dispay up by the ccfl wires or led cable. 7.2. lcd protective liner ? the display is manufactured with an optical-grade, clear protective liner attached to the front polarizer. the liner is optical grade to allo w inspection through the liner while it is still attached. ? leave the liner installed until the last possible moment in production to protect the polarizer from impact scratches, fingerprints, and airborne debris. ? remove the protective liner by placing a small piece of adhesive tape at a corner and press it in place. slowly use the tape to pull the protective liner up and roll off the glass. the protective liner should bend 180 back upon itself as it is slowly pulled. a slow pulling speed reduces electrostatic voltage activating the pixels. 7.3. do not insert anything into the holes in the front or rear bezel. these holes are for factory use only. 8.0 specification errata the following sections provide corrections to the specifications. end_of_file http://www..net/ datasheet pdf - http://www..net/
|
