View ACE24C512DPTH_5423681.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ace24c 512 two - wire serial eeprom ver 1. 4 1 description the ace24c 512 provides wide voltage of 524 , 288 bits of serial electrically erasable and progr ammable read - only memory (eeprom) organized as 65 , 536 words of 8 bits each. the device s cascadable feature allows up to 8 devices to share a common t wo - wire bus. the device is optimized for use in many industrial and c om mercial applications where low - power and low - voltage operations are essential. features ? low operation voltage: vcc = 1. 7 v to 5.5v ? internally organized: 65 , 536 x 8 ? two - wire serial inter face ? schmitt trigger, filtered inputs for noise suppression ? bi - directional data transfer protocol ? 1mhz (2.5v~5.5v) and 400 khz (1. 7 v) compatibility ? write protect pin for hardware data protection ? 128 - byte page write modes ? partial page writes are allowed ? se lf - timed write cycle (5 ms max) ? high - reliability - endurance: 1,000,000 write cycles - data retention: 4 0 years absolute maximum ratings operating temperature - 55 to +125 storage temperature - 65 to +150 voltage on any pin with respect to ground - 1.0v to +7.0v maximum operating voltage 6.25v dc output current 5.0 ma *n otice : stresses beyond those listed under absolute maximum ratings may cause permanent d am age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditio ns for extended periods may affect device reliability .
ace24c 512 two - wire serial eeprom ver 1.4 2 packaging type pin configurations block diagram figure 1 pin name function a0~a2 device address inputs sda serial data input / output scl serial clock input wp write prot ect vcc power supply gnd ground
ace24c 512 two - wire serial eeprom ver 1.4 3 ordering information ace24c 512 xx + x h s erial c lock (scl) : the scl input is used to positive edge clock data into each eeprom de vice and negative edge clock data out of each device. s erial d ata (sda) : the sda pin is bi - directional for serial data transfer. this pin is open - drain driven and may be wire - ored with any number of other open - drain or open - collector devices. d evice /p age a ddresses (a2 , a1 , a 0 ) : the a2, a1 and a0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other ace 24c xx x devices . when the pins are hardwired, a s many as eight 512 k devices may be addressed on a sin gle bus system (device addressing is discussed in detail under the device addressing section).if the pins are left floating, the a2, a1 and a0 pins w ill be internally pulled down to gnd if the capacitive coupling to the circuit board vcc plane is < 3pf, if coupling is > 3pf recommends connecting the address pins to gnd. w rite p rotect (wp): the ace24 c 512 has a write provides hardware data protection. the wp pin allows normal write operations when connected to ground (gnd) . when the write protect pin is conn ected to vcc. a ll write operations to the memory are inhibited. write protect description wp pin status part of the array protected wp= v cc full ( 512 k) memory wp= gnd normal read/write operations memory organization ace 24c 512 , 512 k s erial eeprom: inte rnally organized with 512 pages of 128 bytes each, the 512k requires a 16 - bit data word address for random word addressing. pb - free u : tube t : tape and reel dp : dip - 8 fm : sop - 8 tm : tssop - 8 halogen - free
ace24c 512 two - wire serial eeprom ver 1.4 4 pin capacitance applicable over reco mmended operating range from: t a = 25 , f = 1.0 mhz, v cc = +1. 7 v. symbol test condition max u nits conditions c i/o 1 input / output capacitance 8 pf v i/o = 0v c in 1 input capacitance 6 pf v in = 0v note : 1 . this parameter is characterized and is not 100% tested . dc characteristics applicable over recommended operating range fr om : t a = - 40 to +8 5 , v cc = + 1. 7 v to +5.5v, (unless otherwise noted). symbol parameter test condition min typ max units v cc supply voltage 1. 7 5.5 v i cc1 supply current v cc = 5 .5 v, read at 400k 0.4 1.0 ma i cc2 supply current v cc = 5 .5 v, write at 400k 2.0 3.0 ma i sb standby current v in = v cc / v ss 1.0 20 .0 a i li input leakage current v in = v cc /v ss 0.10 3.0 a i lo output leakage current v out = v cc / v ss 0.05 3.0 a v il 1 input low level - 0.6 v cc x0.3 v v ih 1 input high level v cc x0.7 v cc +0.5 v v ol 1 outpu t low level v cc = 1.7 v, i ol = 0.15 ma 0. 2 v v ol 2 output low level v cc = 3.0 v, i ol = 2.1 ma 0. 4 v note: 1. v il min and v ih max are reference only and are not tested.
ace24c 512 two - wire serial eeprom ver 1.4 5 ac characteristics applicable over recommended operating range f rom: ta = - 40 to +85 , vcc = + 1. 7 v to +5.5v, cl = 100 pf (unless otherwise noted). test conditions are listed in note2. symbol parameter 1. 7 - volt 2.5 - volt 5.5 - volt units min max min max min max f scl clock frequency, scl 400 1000 1000 khz t low clo ck pulse width low 1 300 400 400 n s t high clock pulse width high 600 400 400 n s ti 1 noise suppression time 100 50 50 t aa clock low to data out valid 20 900 20 550 20 550 n s t buf 1 time the bus must be free before a new transmission can start 13 00 500 500 n s t hd.sta start hold time 600 250 250 n s t su.sta start setup time 600 250 250 n s t hd.dat data in hold time 0 0 0 n s t su.dat data in setup time 100 100 100 ns t r inputs rise time 300 300 300 n s t f inputs fall time 300 1 00 100 ns t su.sto stop setup time 600 250 250 n s t dh data out hold time 2 0 2 0 2 0 ns t wr write cycle time 5 5 5 ms endurance 1 3.3 v, 25 , page mode 1,000,000 write cycles notes:1. this parameter is characterized and not 100% tested. 2.ac measurement conditions: rl (connects to vcc): 1.3k input pulse voltages: 0.3 vcc to 0.7 vcc input rise and fall times: Q 50 ns input and output timing reference voltages: 0.5vcc
ace24c 512 two - wire serial eeprom ver 1.4 6 device operation c lock and d ata t ra nsitions : the sda pin is nor mally pulled high with an external device. data on the sda pin may change only during scl low time periods (refer to figure 4 ). data changes during scl high periods will indicate a start or stop condition as defined below. s tar t c ondition : a high - to - low transition of sda with scl high is a start condition which must precede any other command (refer to figure 5 ). s top c ondition : a low - to - high transition of sda with scl high is a stop condition. after a read sequence, the stop c ommand will place the eeprom in a standby power mode (refer to figure 5 ). a cknowledge : all addresses and data words are serially transmitted to and from the eeprom in 8 - bit words. the eeprom sends a zero during the ninth clock cycle to acknowledge that it has received each word. s tandby m ode : the ace 24c 512 features a low - power standby mode which is enabled: (a) upon power - up and (b) after the receipt of the stop bit and the completion of any internal operations. m emory r eset : after an interruption in protocol power loss or system reset, any two - wire part can be protocol reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high and then. 3. create a start condition as sda is high. bus timing figu re 2 scl: serial clock , sda: serial data i/o
ace24c 512 two - wire serial eeprom ver 1.4 7 write cycle timing figure 3 scl: serial clock, sda: serial data i/o note: the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. figure 4 data validity figure 5 start and stop definition
ace24c 512 two - wire serial eeprom ver 1.4 8 figure 6 output acknowledge device addressing the 512 k eeprom device require an 8 - bit device address word following a start con dition to enable th e chip for a read or write operation (refer to figure 7 ). the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. this is common to all the eeprom devices. the 512 k eeprom use the three device a ddress bits a2, a1 , a0 to allow as many as eight devices on the same bus. these bits must compare to their corresponding hard - wired input pins. the a2,a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the module package device address word also consists of a mandatory one, zero sequence for the first four most significant bits. the next 3 bits are all zero. the eight h bit of the device address is the read/write operation select bit . a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a zero. if a compare is not made, the device will return to a standby state. noise prote ction: special internal circuitry place on the sda and scl pins prevent small noise spikes from activating the device. date security: the ace24c 512 has a hardware data protect scheme that slows the user to write protect t he entire memory when the wp pin is at vcc. write operations b yte w rite : a write operation requires two 8 - bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time the eeprom enters an internally timed write cycl e, t wr, to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (refer to figure 8 ).
ace24c 512 two - wire serial eeprom ver 1.4 9 p age w rite : the 512 k eeprom is capable of an 128 - byte page write . a page write is initiate d the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcon troller can transmit up to 127 more data words. t he eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condi tion (refer to figure 9 ). the data word address lower 7 bits are internally incremented following the receipt of e ach data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more th an 128 data words are transmitted to the eeprom, the data word address will roll over and previ ous data will be overwritten. a cknowledge p olling : once the internally timed write cycle has start ed and the eeprom inputs are dis abled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero allowing the re ad or write sequence to continue. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address r ead, random address read and sequential read. c urrent a ddress r ead : the internal data word address counter maintains the last address accessed dur ing the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address roll over during read is from the last byte of the last memory page to the first byte of the first page. the address roll over during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input zero but does generate a f ollowing stop condition (refer to figure 10 ). r andom r ead : a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microco ntroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 11 ).
ace24c 512 two - wire serial eeprom ver 1.4 10 s equential r ead : sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to figure 12 ) . msb lsb 1 0 1 0 a 2 a 1 a 0 r/w figure 7 device address figure 8 byte write figure 9 page write
ace24c 512 two - wire serial eeprom ver 1.4 11 figure 10 current address read figure 11 random read figure 12 sequential read
ace24c 512 two - wire serial eeprom ver 1.4 12 packaging information dip - 8
ace24c 512 two - wire serial eeprom ver 1.4 13 packaging information sop - 8
ace24c 512 two - wire serial eeprom ver 1.4 14 packaging information t ssop - 8
ace24c 512 two - wire serial eeprom ver 1.4 15 notes ace does not assume any responsibility for use as critical components in life support devices or systems without th e express written approval of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or sy stem whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http://www.ace - ele.com/

▲Up To Search▲

Price & Availability of ACE24C512DPTH

	To Download ACE24C512DPTH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .