View VL-MM9-4SBN_5406907.PDF datasheet online --- IC-ON-LINE

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product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 1 general information 4gb 512mx64 ddr3 sdram low voltage non-ecc unbuffered sodimm 204-pin description the vl47d5263a is a 512mx64 ddr3 sdram high density so dimm. this dual rank memory module consists of sixteen cmos 256mx8 bits with 8 ban ks ddr3 synchronous dr ams in bga packages and a 2k eeprom in an 8- pin mlf package. this module is a 204-pin small-outline dual in-line memory module and is intended for mounting into an edge connector socket. decoupling capacitors are mounted on the printed circuit board for each ddr3 sdram. features pin description ? 204-pin, small-outline dual in-line memory module (sodimm) ? fast data transfer rates: pc3- 12800, pc3-10600, pc3-8500, pc3-6400 ? vdd = vddq = 1.35v (1.28v~1 .45v) & 1.5v (1.425v~1.575v) ? jedec standard 1.35v (1.28v~1 .45v) & 1.5v (1.425v~1.575v) ? vddspd = 3.0v to 3.6v ? eight internal component banks for concurrent operation ? 8-bit pre-fetch architecture ? bi-directional differential data-strobe ? nominal and dynamic on -die termination (odt) ? zq calibration support ? programmable cas# latency: 11 (ddr3-1600), 9 (ddr3-1333), 7 (ddr3-1066), 6 (ddr3-800) ? programmable burst; length (8) ? average refresh period 7.8 us ? asynchronous reset ? fly-by topology ? on board terminated command, address, and control bus ? serial presence detect (spd) eeprom with thermal sensor ? thermal sensor range: -40 o c to +125 o c (max +/-3 o c accuracy) ? lead-free, rohs compliant ? gold edge contacts ? pcb: height 30.00mm (1.181?), double sided component ? operating temperature (toper): - commercial (0 o c <= tc <= 95 o c) - industrial (-40 o c <= tc <= 95 o c) notes: double refresh rate is required when 85 o c < t oper <= 95 o c. t oper is dram case temperature (tc). pin name function a0~a14 address inputs a10/ap address input/ autoprecharge a12/bc# address input/ burst chop ba0~ba2 bank address inputs dq0~dq63 data input/output dqs0~dqs7 data strobes dqs0#~dqs7# data strobes complement dm0~dm7 data masks ck0,ck0#, ck1,ck1# clock input odt0, odt1 on-die termination control cke0, cke1 clock enables cs0#, cs1# chip selects ras# row address strobes cas# column address strobes we# write enable vdd voltage supply vss ground sa0~sa1 spd address sda spd data input/output scl spd clock input event# temperature event output vrefca reference voltage for ca vrefdq reference voltage for dq vddspd spd voltage supply vtt termination voltage reset# register and sdram control nc no connect order information: vl 47d5263a - k0 s d - x operating temperature none: commercial s1: industrial screening dram die d-die dram manufacturer s - samsung module speed k0: pc3-12800 @ cl11 k9: pc3-10600 @ cl9 f8: pc3-8500 @ cl7 e7: pc3-6400 @ cl6 vl: lead-free/rohs dram component: samsung k4b2g0846d-hyk0
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 2 pin configuration 204-pin ddr3 sodimm front 204-pin ddr3 sodimm back pin name pin name pin name pin name pin name pin name pin name pin name 1 vrefdq 53 dq19 105 vdd 157 dq42 2 vss 54 vss 106 vdd 158 dq46 3 vss 55 vss 107 a10 159 dq43 4 dq4 56 dq28 108 ba1 160 dq47 5 dq0 57 dq24 109 ba0 161 vss 6 dq5 58 dq29 110 ras# 162 vss 7 dq1 59 dq25 111 vdd 163 dq48 8 vss 60 vss 112 vdd 164 dq52 9 vss 61 vss 113 we# 165 dq49 10 dqs0# 62 dqs3# 114 cs0# 166 dq53 11 dm0 63 dm3 115 cas# 167 vss 12 dqs0 64 dqs3 116 odt0 168 vss 13 vss 65 vss 117 vdd 169 dqs6# 14 vss 66 vss 118 vdd 170 dm6 15 dq2 67 dq26 119 a13 171 dqs6 16 dq6 68 dq30 120 odt1 172 vss 17 dq3 69 dq27 121 cs1# 173 vss 18 dq7 70 dq31 122 nc 174 dq54 19 vss 71 vss 123 vdd 175 dq50 20 vss 72 vss 124 vdd 176 dq55 21 dq8 73 cke0 125 nc 177 dq51 22 dq12 74 cke1 126 vrefca 178 vss 23 dq9 75 vdd 127 vss 179 vss 24 dq13 76 vdd 128 vss 180 dq60 25 vss 77 nc 129 dq32 181 dq56 26 vss 78 a15 * 130 dq36 182 dq61 27 dqs1# 79 ba2 131 dq33 183 dq57 28 dm1 80 a14 132 dq37 184 vss 29 dqs1 81 vdd 133 vss 185 vss 30 reset# 82 vdd 134 vss 186 dqs7# 31 vss 83 a12 135 dqs4# 187 dm7 32 vss 84 a11 136 dm4 188 dqs7 33 dq10 85 a9 137 dqs4 189 vss 34 dq14 86 a7 138 vss 190 vss 35 dq11 87 vdd 139 vss 191 dq58 36 dq15 88 vdd 140 dq38 192 dq62 37 vss 89 a8 141 dq34 193 dq59 38 vss 90 a6 142 dq39 194 dq63 39 dq16 91 a5 143 dq35 195 vss 40 dq20 92 a4 144 vss 196 vss 41 dq17 93 vdd 145 vss 197 sa0 42 dq21 94 vdd 146 dq44 198 event# 43 vss 95 a3 147 dq40 199 vddspd 44 vss 96 a2 148 dq45 200 sda 45 dqs2# 97 a1 149 dq41 201 sa1 46 dm2 98 a0 150 vss 202 scl 47 dqs2 99 vdd 151 vss 203 vtt 48 vss 100 vdd 152 dqs5# 204 vtt 49 vss 101 ck0 153 dm5 50 dq22 102 ck1 154 dqs5 51 dq18 103 ck0# 155 vss 52 dq23 104 ck1# 156 vss *: these pins are not used in this module.
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 3 function block diagram d1 dq3 dq13 dq7 cs# dq7 dqs6# cas# command, address, control, and clock line terminations dq6 dm dq0 dq1 dqs7 dq6 dq5 cs# d0-d15 dqs# dqs dq30 dq35 dq0 dq2 vss d0-d7 dq1 dq3 dq16 cs# zq dm dq0 dm a0-a14 dq6 vss dq7 dq0 dq0 dq59 dqs5# dq1 dq2 dm d0-d15 dq5 dq4 dq1 dq8 zq dq3 dq3 d4 dqs# d0-d15 dqs# dq7 vss dq0 odt0: sdrams d0-d7 ddr3 sdram cs# zq 0.1uf dq2 zq dq41 dm dq7 d0-d15 dq2 dq7 dq54 dq0 dq4 zq d13 dq7 dq18 dq3 dq3 dq3 dq3 cs# dq2 odt1: sdrams d8-d15 ck0, ck1 dq0 dqs# dq43 dqs3# vss zq d0-d15 d3 dq2 dq38 d15 cs0# dq19 dq4 dq4 dqs7# dq4 odt1 dq2 dqs6 dq3 dqs dqs dq57 ras#: sdrams d0-d15 w ith integrated thermal sensor dq6 dm1 dq0 zq dq5 dqs dq25 dq52 dqs# dq5 dm5 dq2 d14 dq3 dq23 dq2 dq2 dqs cke1: sdrams d8-d15 vtt d6 dqs3 dq7 dq4 dq0 zq dq40 vss dq7 a0-a14: sdrams d0-d15 sa1 dq3 dq0 dq29 dq60 dq5 dm d12 dq22 dq1 dqs# zq dm7 dqs dq3 cke1 dq3 dq0 dq10 dqs5 dm dq2 cs# dq5 we# event# dq4 dq4 d0 dq1 dq28 dq6 dqs2 d11 dm0 dq17 dq0 dq5 dm cs# dq0 2. zq resistors are 240 ohms +/-1% dqs4 dq9 dqs# dqs0 dq6 dq33 ras# a2 dm dq2 dq4 dq7 dq1 vss dq6 dqs d9 dq5 dq21 dq47 vss dq6 dq5 dqs# dq3 1. unless otherw ise noted, resistor values are 15 ohms +/-5% vdd dq15 zq dq5 vrefca dq5 dq39 dq3 ba0-ba2 event# dqs# dq2 dq4 vss dq58 vss dq4 d10 dq5 dq20 dq56 dqs dq7 dq6 notes : dq2 dq6 dqs0# dq2 dq55 dm2 dqs ba0-ba2: sdrams d0-d15 a0 dq5 36 ohm +/- 5% dq4 vss dq51 dq4 dq1 dqs1 d8 vss dq42 dq2 vss zq cs# cs1#, cke1, odt1 vtt dq5 dq14 dq5 dqs dq0 dq45 dq6 odt0 sa0 dm6 dq6 vss dq4 dq1 dq63 dq48 dqs# cs# cs# vss a0-a14, ba0-ba2 ras#, cas#, we#, cs0#, cke0, odt0 cs# dq24 dq50 dqs# dq1 dq7 reset#: sdrams d0-d15 30 ohm +/- 5% dq4 dq12 vss dqs4# dq4 cke0: sdrams d0-d7 a1 vss dqs d7 dq49 cs# dm dq0 dq6 3.3pf dq6 dq3 dq6 dq26 dq34 cs# dm reset# ck0#, ck1# dq1 dq1 dq46 dm cke0 scl vdd dm vss dq6 dq5 dq62 dqs dq7 dqs ck1 vddspd dq1 dqs# dq27 dq44 dm zq dqs1# 3.3pf dq2 dq11 cs# ddr3 sdram d2 d5 dq5 we#: sdrams d0-d15 sda dm3 dq1 dq7 dq37 dq0 zq dqs# dq36 vss ck1# vrefdq dq7 dq7 dqs dqs dq32 ck0 dq1 zq dm dm4 dqs# dq7 cas#: sdrams d0-d15 serial pd cs# dqs dq3 dq53 dqs# zq cs1# dq6 dqs2# dq1 d8-d15 serial pd/ thermal sensor dm dqs# dq31 dq61 zq cs# dq4 dq1 ck0#
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 4 absolute maximum ratings symbol parameter min max unit vdd voltage on vdd pin relative to vss -0.4 1.975 v vddq voltage on vddq pin relative to vss -0.4 1.975 v vin, vout voltage on any pin relative to vss -0.4 1.975 v tstg storage temperature -55 100 0 c il input leakage current; any input 0v product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 5 input dc logic level all voltages referenced to vss symbol parameter min max unit 1.35v command and address vihca(dc) input high (logic 1) voltage (ddr3-800/1066/1333/1600) vref + 0.090 vdd v vilca(dc) input low (logic 0) voltage (ddr3-800/1066/1333/1600) vss vref - 0.090 v dq and dm vihdq(dc) input high (logic 1) voltage (ddr3-800/1066/1333/1600) vref + 0.090 vdd v vildq(dc) input low (logic 0) voltage (ddr3-800/1066/1333/1600) vss vref - 0.090 v 1.5v command and address vihca(dc) input high (logic 1) voltage (ddr3-800/1066/1333/1600) vref + 0.100 vdd v vilca(dc) input low (logic 0) voltage (ddr3-800/1066/1333/1600) vss vref - 0.100 v dq and dm vihdq(dc) input high (logic 1) voltage (ddr3-800/1066/1333/1600) vref + 0.100 vdd v vildq(dc) input low (logic 0) voltage (ddr3-800/1066/1333/1600) vss vref ? 0.100 v input ac logic level all voltages referenced to vss symbol parameter min max unit 1.35v command and address vihca(ac) input high (logic 1) voltage (ddr3-800/1066/1333/1600) vref + 0.160 - v vilca(ac) input low (logic 0) voltage (ddr3-800/1066/1333/1600) - vref - 0.160 v dq and dm vihdq(ac) input high (logic 1) voltage (ddr3-800/1066) vref + 0.160 - v vildq(ac) input low (logic 0) voltage (ddr3-800/1066) - vref - 0.160 v vihdq(ac) input high (logic 1) voltage (ddr3-1333/1600) vref + 0.135 - v vildq(ac) input low (logic 0) voltage (ddr3-1333/1600) - vref - 0.135 v 1.5v command and address vihca(ac) input high (logic 1) voltage (ddr3-800/1066/1333/1600) vref + 0.175 - v vilca(ac) input low (logic 0) voltage (ddr3-800/1066/1333/1600) - vref - 0.175 v dq and dm vihdq(ac) input high (logic 1) voltage (ddr3-800/1066) vref + 0.175 - v vildq(ac) input low (logic 0) voltage (ddr3-800/1066) - vref - 0.175 v vihdq(ac) input high (logic 1) voltage (ddr3-1333/1600) vref + 0.150 - v vildq(ac) input low (logic 0) voltage (ddr3-1333/1600) - vref - 0.150 v
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 6 input/output capacitance ta=25 0 c, f=100mhz parameter symbol k0 (ddr3-1600) k9 (ddr3-1333) f8 (ddr3-1066) e7 (ddr3-800) unit min max min max min max min max 1.35v input capacitance (a0~a14, ba0~ba2, ras#, cas#, we#) cin1 16 24.8 16 24.8 16 24.8 16 24.8 pf input capacitance (cke0, cke1), (odt0, odt1), (cs0#, cs1#) cin2 10 14.4 10 14.4 10 14.4 10 14.4 pf input capacitance (ck0, ck0#), (ck1, ck1#) cin3 10.4 15.2 10.4 15.2 10.4 16.8 10.4 16.8 pf input/output capacitance (dq, dqs, dqs#, dm) cio 6.4 8.6 7 8.6 7 9 7 9 pf 1.5v input capacitance (a0~a14, ba0~ba2, ras#, cas#, we#) cin1 16 24.8 16 24.8 16 28 16 28 pf input capacitance (cke0, cke1), (odt0, odt1), (cs0#, cs1#) cin2 10 14.4 10 14.4 10 16 10 16 pf input capacitance (ck0, ck0#), (ck1, ck1#) cin3 10.4 15.2 10.4 15.2 10.4 16.8 10.4 16.8 pf input/output capacitance (dq, dqs, dqs#, dm) cio 6.8 8.6 7 9 7 9.4 7 10 pf
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 7 basic idd and iddq measurement conditions symbol condition idd0* operating one bank active-precharge current; tck= tck(idd); trc= trc(idd); tras= tras min(idd); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching. idd1* operating one bank active-read-precharge current; iout = 0ma; bl = 8; cl = cl(idd); al = 0; tck= tck(idd) ; trc= trc(idd); tras= tras min(idd); trcd= trcd(idd); cke is high, cs# is high between valid commands; address bus i nputs are switching; data pattern is same as idd4w. idd2p-f** precharge power-down current fast exit; all device banks idle; tck= tck(idd); cke is low; other c ontrol and address bus inputs are stable; data bus inputs are floating. idd2p-s** precharge power-down current low exit; all device banks idle; tck= tck(idd); cke is low; other c ontrol and address bus inputs are stable; data bus inputs are floating. idd2n** precharge standby current; all device banks idle; tck= tck(idd); cke is high; cs# is hi gh; other control and address bus inputs are switching; data bus inputs are switching. idd2q** precharge quiet standby current; all device banks idle; tck= tck(idd); cke is high; cs# is hi gh; other control and address bus inputs are stable; data bus inputs are floating. idd3p** active power-down current; all device banks open; tck= tck(idd); cke is low; other cont rol and address bus inputs are stable; data bus inputs are floating. idd3n** active standby current; all device banks open; tck= tck(idd); trp= trp(idd); tras= tr as max(idd)); cke is high, cs# is high between valid commands; other control and address bus inputs ar e switching; data bus inputs are switching. idd4r* operating burst read current; all device banks open; continuous burst reads; iout = 0ma; bl = 8; cl = cl(idd); al = 0; tck= tck(idd); tras= tras max(idd); trp= trp(idd); cke is high, cs# is high betw een valid commands; address bus inputs are switching; data pattern is same as idd4w. idd4w* operating burst write current; all device banks open; continuous burst writes; bl = 8; cl = cl (idd); al = 0; tck= tck(idd); tras= tras max(idd); trp= trp(idd); cke is high, cs# is high between valid commands ; address bus inputs are switching; data bus inputs are switching. idd5** burst refresh current; tck=tck(idd); refresh command at every trfc(idd) interval ; cke is high; cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd6** self refresh current; ck and ck# at 0v; cke < 0.2v; other control and address bus inputs are floating; data bus inputs are floating. idd7* operating bank interleave read current; all bank interleaving reads; iout = 0ma; bl = 8; cl = cl(i dd); al = trcd(idd) - 1*tck(idd); tck= tck(idd); trc= trc(idd); trrd = trrd(idd); trcd = 1*tck(idd) ; cke is high; cs# is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r. notes: *: value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. **: value calculated reflects all m odule ranks in this operating condition.
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 8 idd specification symbol k0 (ddr3-1600) k9 (ddr3-1333) f8 (ddr3-1066) e7 (ddr3-800) unit 1.35v 1.5v 1.35v 1.5v 1.35v 1.5v 1.35v 1.5v idd0 400 456 360 416 320 376 320 376 ma idd1 480 536 440 496 400 456 400 456 ma idd2p-f 240 240 208 240 208 240 208 240 ma idd2p-s 160 192 160 192 160 192 160 192 ma idd2n 272 320 240 320 240 272 240 272 ma idd2q 272 320 240 320 240 272 240 272 ma idd3p 272 320 240 272 240 272 240 272 ma idd3n 480 560 400 560 400 480 400 480 ma idd4r 600 816 560 696 480 616 480 616 ma idd4w 680 856 600 736 520 656 520 656 ma idd5 1840 1920 1840 1840 1760 1760 1760 1760 ma idd6 160 192 160 192 160 192 160 192 ma idd7 1080 1216 1040 1176 840 936 840 936 ma note: idd specification is based on samsung d-die components.
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 9 ac timing parameters & specifications parameter symbol k0 (ddr3-1600) k9 (ddr3-1333) f8 (ddr3-1066) e7 (ddr3-800) unit min max min max min max min max clock timing minimum clock cycle time (dll off mode) tck(dll_off) 8 - 8 - 8 - 8 - ns average clock period tck(avg) 1.25 <1.50 1.5 <1.875 1.875 <2.5 2.5 3.3 ns clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ns average high pulse width tch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) clock period jitter tjit(per) -70 70 -80 80 -90 90 -100 100 ps clock period jitter during dll locking period tjit(per, lck) -60 60 -70 70 -80 80 -90 90 ps cycle to cycle period jitter tjit(cc) 140 160 180 200 ps cycle to cycle period jitter during dll locking period tjit(cc, lck) 120 140 160 180 ps cumulative error across 2 cycles terr(2per) -103 103 -118 118 -132 132 -147 147 ps cumulative error across 3 cycles terr(3per) -122 122 -140 140 -157 157 -175 175 ps cumulative error across 4 cycles terr(4per) -136 136 -155 155 -175 175 -194 194 ps cumulative error across 5 cycles terr(5per) -147 147 -168 168 -188 188 -209 209 ps cumulative error across 6 cycles terr(6per) -155 155 -177 177 -200 200 -222 222 ps cumulative error across 7 cycles terr(7per) -163 163 -186 186 -209 209 -232 232 ps cumulative error across 8 cycles terr(8per) -169 169 -193 193 -217 217 -241 241 ps cumulative error across 9 cycles terr(9per) -175 175 -200 200 -224 224 -249 249 ps cumulative error across 10 cycles terr(10per) -180 180 -205 205 -231 231 -257 257 ps cumulative error across 11 cycles terr(11per) -184 184 -210 210 -237 237 -263 263 ps cumulative error across 12 cycles terr(12per) -188 188 -215 215 -242 242 -269 269 ps cumulative error across n = 13, 14 ... 49, 50 cycles terr( n per) terr( n per)min =(1+ 0.68ln( n ))*tjit(per)min terr( n per)max=(1+ 0.68ln( n ))*tjit(per)max ps absolute clock high pulse width tch(abs) 0.43 - 0.43 - 0.43 - 0.43 - tck(avg) absolute clock low pulse width tcl(abs) 0.43 - 0.43 - 0.43 - 0.43 - tck(avg) data timing dqs,dqs# to dq skew, per group, per access tdqsq - 100 - 125 - 150 - 200 ps dq output hold time from dqs, dqs# tqh 0.38 - 0.38 - 0.38 - 0.38 - tck(avg) dq low-impedance time from ck, ck# tlz(dq) -450 225 -500 250 -600 300 -800 400 ps dq high-impedance time from ck, ck# thz(dq) - 225 - 250 - 300 - 400 ps data setup time to dqs, dqs# referenced to vih(ac)vil(ac) levels 1.35v tds(base) (ac160) - - - - 40 - 90 - ps tds(base) (ac135) 25 - 45 - - - - - ps data setup time to dqs, dqs# referenced to vih(ac)vil(ac) levels 1.5v tds(base) (ac175) - - - - 25 - 75 - ps tds(base) (ac150) 10 - 30 - - - - - ps
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 10 ac timing parameters & specifications parameter symbol k0 (ddr3-1600) k9 (ddr3-1333) f8 (ddr3-1066) e7 (ddr3-800) unit min max min max min max min max data hold time to dqs, dqs# referenced to vih(ac)vil(ac) levels tdh(base) 55 - 75 - 110 - 160 - ps dq and dm input pulse width for each input tdipw 360 - 400 - 490 - 600 - ps data strobe timing dqs, dqs# read preamble trpre 0.9 - 0.9 - 0.9 - 0.9 - tck dqs, dqs# differential read postamble trpst 0.3 - 0.3 - 0.3 - 0.3 - tck dqs, dqs# output high time tqsh 0.4 - 0.4 - 0.38 - 0.38 - tck(avg) dqs, dqs# output low time tqsl 0.4 - 0.4 - 0.38 - 0.38 - tck(avg) dqs, dqs# write preamble twpre 0.9 - 0.9 - 0.9 - 0.9 - tck dqs, dqs# write postamble twpst 0.3 - 0.3 - 0.3 - 0.3 - tck dqs, dqs# rising edge output access time from rising ck, ck# tdqsck -225 225 -255 255 -300 300 -400 400 ps dqs, dqs# low-impedance time (referenced from rl-1) tlz(dqs) -450 225 -500 250 -600 300 -800 400 ps dqs, dqs# high-impedance time (referenced from rl+bl/ 2) thz(dqs) - 225 - 250 - 300 - 400 ps dqs, dqs# differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs, dqs# differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs, dqs# rising edge to ck, ck# rising edge tdqss -0.27 0.27 -0.25 0.25 -0.25 0.25 -0.25 0.25 tck(avg) dqs,dqs# failing edge setup time to ck, ck# rising edge tdss 0.18 - 0.2 - 0.2 - 0.2 - tck(avg) dqs,dqs# failing edge hold time to ck, ck# rising edge tdsh 0.18 - 0.2 - 0.2 - 0.2 - tck(avg) command and address timing dll locking time tdllk 512 - 512 - 512 - 512 - nck internal read command to precharge command delay trtp max (4tck,7.5ns) - max (4tck,7.5ns) - max (4tck,7.5ns) - max (4tck,7.5ns) - delay from start of internal write transaction to internal read command twtr max (4tck,7.5ns) - max (4tck,7.5ns) - max (4tck,7.5ns) - max (4tck,7.5ns) - write recovery time twr 15 - 15 - 15 - 15 - ns mode register set command cycle time tmrd 4 - 4 - 4 - 4 - nck mode register set command update delay tmod max (12tck,15ns) - max (12tck,15ns) - max (12tck,15ns) - max (12tck,15ns) - cas# to cas# command delay tccd 4 - 4 - 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup (trp / tck(avg)) nck multi-purpose register recovery time tmprr 1 - 1 - 1 - 1 - nck active to precharge command period tras 35 9*tr efi 36 9*trefi 37.5 9* trefi 37.5 9*trefi ns active to internal read or write delay time trcd 13.75 - 13.5 - 13.13 - 15 - ns precharge command period trp 13.75 - 13.5 - 13.13 - 15 - ns active to active or ref command period trc 48.75 - 49.5 - 50.63 - 52.5 - ns active to active command period for 1kb page size trrd max (4tck,6ns) - max (4tck,6ns) - max (4tck,7.5ns) - max (4tck,10ns) - active to active command period for 2kb page size trrd max (4tck,7.5ns) - max (4tck,7.5ns) - max (4tck,10ns) - max (4tck,10ns) - four activate window for 1kb page size tfaw 30 - 30 - 37.5 - 40 - ns four activate window for 2kb page size tfaw 40 - 45 - 50 - 50 - ns command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels 1.35v tis(base) (ac160) - - - - 140 - 215 - ps tis(base) (ac135) 185 - 205 - - - - - ps
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 11 ac timing parameters & specifications parameter symbol k0 (ddr3-1600) k9 (ddr3-1333) f8 (ddr3-1066) e7 (ddr3-800) unit min max min max min max min max command and address setup time to ck, ck# referenced to vih(ac) / vil(ac) levels 1.5v tis(base) (ac175) 45 - 65 - 125 - 200 - ps tis(base) (ac150) 45 + 125 - 65 + 125 - 125 + 150 - 200 + 150 - ps command and address hold time from ck, ck# referenced to vih(ac) / vil(ac) levels tih(base) 130 - 150 - 210 - 285 - ps control & address input pulse width for each input tipw 560 - 620 - 780 - 900 - ps refresh timing 2gb refresh to refresh or refresh to active command interval trfc 160 - 160 - 160 - 160 - ns average periodic refresh interval (0c<= tcase <= 85 c) trefi 7.8 - 7.8 - 7.8 - 7.8 - us average periodic refresh interval (85c<= tcase <= 95 c) trefi 3.9 - 3.9 - 3.9 - 3.9 - us calibration timing power-up and reset calibration time tzqiniti 512 - 512 - 512 - 512 - tck normal operation full calibration time tzqoper 256 - 256 - 256 - 256 - tck normal operation short calibration time tzqcs 64 - 64 - 64 - 64 - tck reset timing exit reset from cke high to a valid command txpr max (5tck, trfc + 10ns) - max (5tck, trfc + 10ns) - max (5tck, trfc + 10ns) - max (5tck, trfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll txs max(5tc, trfc+10ns) - max(5tc, trfc+10ns) - max(5tc, trfc +10ns) - max(5tc, trfc +10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min) - tdllk(min) - tdllk(min) - tdllk(min) - nck minimum cke low width for self refresh entry to exit timing tckesr tcke(min) + 1tck - tcke(min) + 1tck - tcke(min) + 1tck - tcke(min) + 1tck - valid clock requirement after self refresh entry (sre) tcksre max(5tc, 10ns) - max(5tck, 10ns) - max(5tck, 10ns) - max(5tck, 10ns) - valid clock requirement before self refresh exit (srx) tcksrx max(5tc, 10ns) - max(5tck, 10ns) - max(5tck, 10ns) - max(5tck, 10ns) - power down timing exit power down with dll to any valid command; exit precharge power down with dll frozen to commands not requiring a locked dll txp max (3tck,6ns) - max (3tck,6ns) - max (3tck,7.5ns) - max (3tck,7.5ns) - exit precharge power down with dll frozen to commands requiring a locked dll txpdll max (10tck,24ns) - max (10tck,24ns) - max (10tck,24ns) - max (10tck,24ns) - cke minimum pulse width tcke max (3tck, 5ns) - max (3tck, 5.625ns) - max (3tck, 5.625ns) - max (3tck, 7.5ns) - command pass disable delay tcpded 1 - 1 - 1 - 1 - nck power down entry to exit timing tpd tc ke(min) 9*trefi tcke(min) 9*trefi tcke( min) 9*trefi tcke(mi n) 9*trefi tck timing of act command to power down entry tactpden 1 - 1 - 1 - 1 - nck timing of pre command to power down entry tprpden 1 - 1 - 1 - 1 - nck timing of rd/rda command to power down entry trdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry bl8 (otf, mrs), bl4otf twrpden wl + 4 + (twr/ tck(avg)) - wl + 4 + (twr/ tck(avg)) - wl + 4 + (twr/ tck(avg)) - wl + 4 + (twr/ tck(avg)) - nck timing of wra command to power down entry bl8 (otf, mrs), bl4otf twrapden wl+4 +wr+1 - wl+4 +wr+1 - wl+4 +wr+1 - wl+4 +wr+1 - nck
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 12 ac timing parameters & specifications parameter symbol k0 (ddr3-1600) k9 (ddr3-1333) f8 (ddr3-1066) e7 (ddr3-800) unit min max min max min max min max timing of wr command to power down entry (bl4mrs) twrpden wl + 2 + (twr/ tck(avg)) - wl + 2 + (twr/ tck(avg)) - wl + 2 + (twr/ tck(avg)) - wl + 2 + (twr/ tck(avg)) - nck timing of wra command to power down entry (bl4mrs) twrapden wl+2 +wr+1 - wl+2 +wr+1 - wl+2 +wr+1 - wl+2 +wr+1 - nck timing of ref command to power down entry trefpden 1 - 1 - 1 - 1 - timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - tmod(min) - tmod(min) - odt timing odt high time without write command or with write command and bc4 odth4 4 - 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - 6 - nck asynchronous rtt turn-on delay (power- down with dll frozen) taonpd 2 8.5 2 8.5 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power- down with dll frozen) taofpd 2 8.5 2 8.5 2 8.5 2 8.5 ns odt turn-on taon -225 225 -250 250 -300 300 -400 400 ps rtt_nom and rtt_wr turn-off time from odtl off reference taof 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg) write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed twlmrd 40 - 40 - 40 - 40 - tck dqs/dqs delay after tdqs margining mode is programmed twldqsen 25 - 25 - 25 - 25 - tck setup time for tdqss latch twls 165 - 195 - 245 - 325 - ps hold time for tdqss latch twlh 165 - 195 - 245 - 325 - ps write leveling output delay twlo 0 7.5 0 9 0 9 0 9 ns write leveling output error twloe 0 2 0 2 0 2 0 2 ns
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 13 package dimensions note: 1. all dimensions are in millimeters with tolerance +/- 0.15mm unles s otherwise specified. 2. the dimensional diagram is for reference only. 21.00 typ 24.80 typ front view 3.00 typ 4.0 +/- 0.10 (2x) 4.00 typ 67.60 pin 2 pin 203 20.00 pin 1 2.55 typ 2.15 typ 30.00 1.80 (2x) back view 0.60 typ 3.40 max 0.45 typ 1.0 +/- 0.10 1.0 +/- 0.10 typ 63.60 typ typ 0.5 r 6.00 typ pin 204 39.00 typ
product specifications part no.: vl47d5263a-k0/k9/f8/e7sd rev: 1.2 tel 949.888.2444 ? 30052 tomas, rancho santa margarita, ca 92688 usa ? www.virtium.com 14 revision history: date rev. page changes 04/17/2012 1.0 all spec released 05/04/2012 1.1 5 update input ac logic level table 05/07/2012 1.2 5 typo correction

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