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description designed to provide the power supply requirements of next generation car audio and infotainment systems, the a8600 provides all the control and protection circuitry to produce four high current regulators, each with 1.5% accuracy. the a8600 includes control circuitry to implement three adjustable, asynchronous buck regulators with integrated mosfets. also, the a8600 provides the control circuitry, gate drivers, and current sensing to implement a synchronous buck controller with external mosfets. in standby mode, the a8600 draws less than 50 a from v in of 12 v while employing pulse frequency modulation (pfm) to deliver 3.3 v/40 a via the always-on regulator, sw1. the always-on regulator operates down to at least v in of 3.6 v (v in falling). features of the a8600 include: an en/sync input to either turn the a8600 on/off or increase/decrease the base pulse width modulation (pwm) frequency, four adjustable soft-start times, and four external compensation pins. output voltage monitoring of switchers sw2, sw3, and sw4 is provided by a single, open-drain pok output. in addition, the a8600 provides two high voltage, high-side switches with foldback overcurrent protection. these two high-side switches actively block reverse current. the a8600 also provides direct battery (bu) and switched (accessory) battery (acc) detectors and a mute pulse output with an adjustable delay. a8600-ds, rev. 3 features and benefits ? four independent, high current switching regulators ? adjustable 1.0 a/1.5% always-on asynchronous buck regulator with an integrated 150 m mosfet (sw1) ? employs pfm to deliver 3.3 v/40 a while drawing less than 50 a from v in of 12 v ? operates down to at least 3.6 v in ? adjustable 1.5 a/1.5% asynchronous buck regulator with an integrated 120 m high-side mosfet (sw2) ? adjustable 2.0 a/1.5% asynchronous buck regulator with an integrated 110 m mosfet (sw3) ? adjustable 1.5% synchronous buck controller with integrated gate drivers and current sensing (sw4) ? fixed 425 khz, interleaved pwm switching frequency ? en/sync input for pwm frequency scaling ? adjustable soft-start time for each switching regulator ? all switching regulators provide prebias startup with zero reverse current ? all switching regulators have overvoltage protection ? external compensation for all switching regulators quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay package: 48-pin lqfp (suffix jp) not to scale a8600 1.0 a avg / 2.5 a peak 1.5 a avg / 2.5 a peak 2.0 a avg / 2.5 a peak switcher 1 (sw1) always-on adjustable output voltage adjustable output voltage adjustable output voltage adjustable output voltage adjustable i lim pwm / pfm asynchronous buck switcher 2 (sw2) pwm switcher 3 (sw3) pwm switcher 4 (sw4) pwm regulator asynchronous buck regulator asynchronous buck regulator synchronous buck controller bu and acc detectors mute pulse with delay 425 khz 180 shift (en/sync) charge enable and synchronization pump high-side switch 2 (s2) high-side switch 1 (s1) 1.0 total with foldback limiting 1.0 total with foldback limiting continued on the next page? continued on the next page? figure 1. a8600 major features
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com protection features of the a8600 include pulse-by-pulse current limit, hiccup mode short circuit protection, asynchronous diode protection, boot voltage protection, undervoltage lockout, over- voltage protection and thermal shutdown. the a8600 is supplied in a low profile 48-pin lqfp package (suffix jp ) with exposed power pad. it is lead (pb) free, with 100% matte- tin leadframe plating. ? power ok (pok) open-drain output with de-glitch ? bu and acc voltage detectors and comparators ? mute control with programmable delay ? two internal high-voltage, high-side nmos switches (s1 and s2) with foldback short circuit protection ? high-side switches simultaneously controlled on/off ? high-side switches block reverse current ? internal charge pump for high-side switch biasing ? withstands surge voltages up to 40 v ? ? 40c to 85c ambient operating temperature range ? 150c maximum junction temperature ? thermally enhanced, surface mount package features and benefits (continued) description (continued) selection guide part number operating ambient temperature range t a , (c) package packing* leadframe plating A8600EJPTR-T ?40 to 85 48-pin lqfp with exposed thermal pad 1500 pieces per 13-in. reel 100% matte-tin *contact allegro ? for additional packing options.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table of contents specifications 4 absolute maximum ratings 4 thermal characteristics 4 pin-out diagram and list 5 top level block diagram 6 typical application circuit 6 sw1/2/3 detailed block diagram 7 sw4 detailed block diagram 8 electrical characteristics table 9 general specifications 9 sw1 regulator 10 sw2 regulator 12 sw3 regulator 14 sw4 controller 16 s1, s2 switches 18 bu and acc comparators 18 ctmr and mute 19 timing diagrams 20 sw1 normal pwm operation 20 sw1 low iq and low ip operation 21 sw2/3/4 pwm operation 22 s1/2 operation 23 bu, acc, and mute operation 24 functional description 25 overview 25 reference voltage 25 pwm switching frequency 25 enable/synchronization input (en/sync) 25 bias input pin, ratings, and connections 26 transconductance error amplifier 26 slope compensation 26 current sense amplifiers 26 power mosfets 26 boot regulators 27 sw1/2/3/4 pulse width modulation (pwm) mode 27 sw1 low ip pwm mode 27 sw1 pulse frequency modulation (pfm) and low iq mode 27 soft start (startup) and inrush current control 28 prebiased startup 29 high-side switches (s1 and s2) 29 bu and acc detectors and mute output 31 power ok (pok) output 31 protection features 32 undervoltage lockout (uvlo) 32 thermal shutdown (tsdl and tsdh) 32 pulse-by-pulse overcurrent protection (ocp) 32 output short circuit (hiccup mode) protection 33 boot capacitor protection 33 asynchronous diode protection 34 overvoltage protection (ovp) 34 application information 36 design and component selection 36 setting the output voltage (v swx , r fbax , r fbbx ) 36 output inductor (lswx) 37 output capacitors (cswx) 37 sw1 low iq pfm ripple calculation 38 input capacitors (cinx) 38 asynchronous diode (dswx) 39 bootstrap capacitor (cbootx) 40 soft start and hiccup mode timing (cssx) 40 sw4 external mosfet selections 41 sw4 current sense resistor 41 compensation components (rzx, czx, cpx) 41 a generalized tuning procedure 43 power dissipation and thermal calculations 44 pcb component placement and routing 45 pin descriptions table 47 pin esd structures 49 package outline drawing 50
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings 1 characteristic symbol notes rating unit outx pins continuous ?0.3 to 40 v bui, vin1/2/3, vins, ssx, mute, pok pins ?0.3 to 40 v bias, csp, csn pins ?0.3 to 7 v hg4 pin ?0.3 to v in3 + 7 v lg4 pin ?0.3 to 8.5 v bootx pins v inx = v in1 , v in2 , v in3 ?0.3 to v inx +7 v lx1/2/3 pin to gnd v lx1 , v lx2 , v lx3 continuous, v inx = v in1 , v in2 , v in3 ; minimum voltage is a function of temperature ?0.3 to v inx +1 v t < 50 ns, v inx = v in1 , v in2 , v in3 ?1.0 to v inx +3 v lx4 pin to gnd v lx4 continuous, lower limit is a function of temperature ?1.0 to 37 v t < 50 ns ?1.5 to 40 v vreg pin to gnd v vreg ?0.3 to 5.5 v acci pin 2 i acci 1ma t < 100 ms ?50 ma all other pins ?0.3 to 5.5 v operating ambient temperature t a e temperature range ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc 1 stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the elec trical characteristics table is not implied. exposure to absolute maximum-rated conditions for extended periods may affect device reli ability. 2 negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. thermal characteristics characteristic symbol test conditions* value unit package thermal resistance, junction to ambient r ja on 4-layer pcb based on jedec standard 23 oc/w on 2-layer pcb with 3 in. 2 of copper area on 2 sides 44 oc/w package thermal resistance, junction to pad r jp 2 oc/w *additional thermal information available on the allegro website.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 24 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 vin2 vin2 nc pgnd lg4 boot4 lx4 hg4 ss4 csp csn fb4 vin1 mute gnd vreg ctmr en/sync acco acci buo bui vin3 vin3 comp4 pok out2 vins out1 ens comp3 fb3 ss3 boot3 lx3 lx3 lx2 lx2 boot2 ss2 fb2 comp2 comp1 fb1 bias ss1 boot1 lx1 pad pin-out diagram name number function acci 8 input to the acc comparator acco 7 output of the acc comparator bias 45 bias input, supplies internal circuitry when v sw1 is high enough boot1 47 floating gate drive for buck regulator sw1 boot2 39 floating gate drive for buck regulator sw2 boot3 15 floating gate drive for buck regulator sw3 boot4 31 floating gate drive for buck regulator sw4 bui 10 input to the bu comparator buo 9 output of the bu comparator comp1 43 error amplifier compensation network for regulator sw1 comp2 42 error amplifier compensation network for regulator sw2 comp3 18 error amplifier compensation network for regulator sw3 comp4 24 error amplifier compensation network for regulator sw4 csn 26 current sense pin for buck regulator sw4 csp 27 current sense pin for buck regulator sw4 ctmr 5 delay programming for the mute pulse circuit en/sync 6 swx enable and pfm control, and pwm synchronization ens 19 s1/s2 enable input fb1 44 feedback pin for buck regulator sw1 fb2 41 feedback pin for buck regulator sw2 fb3 17 feedback pin for buck regulator sw3 name number function fb4 25 feedback pin for buck regulator sw4 gnd 3 ground hg4 29 high side gate drive for buck regulator sw4 lg4 32 low side gate drive for buck regulator sw4 lx1 48 switching node for buck regulator sw1 lx2 37, 38 switching node for buck regulator sw2 lx3 13, 14 switching node for buck regulator sw3 lx4 30 switching node for buck regulator sw4 mute 2 open-drain, active low output of the mute pulse circuit nc 34 unused out1 20 high-side switch s1 output out2 22 high-side switch s2 output pad ? exposed pad for enhanced thermal dissipation pgnd 33 power ground pok 23 power ok open drain output ss1 46 soft start programming for regulator sw1 ss2 40 soft start programming for regulator sw2 ss3 16 soft start programming for regulator sw3 ss4 28 soft start programming for regulator sw4 vin1 1 input supply for buck regulator sw1 vin2 35, 36 input supply for buck regulator sw2 vin3 11, 12 input supply for buck regulator sw3 (and sw4) vins 21 s1/s2 high-side switch input vreg 4 internal voltage regulator bypass capacitor pin
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com fb2 lx 2 lx 2 vin2 vin2 boot2 10 comp2 ss 2 comp2 delay ss2 clk180 tsdh adj (8 v) 1.0 a avg 2.5 a peak fb3 lx3 lx3 boot 3 10 comp3 ss 3 comp3 ss3 clk0 tsdh adj (3. 3 v) 3. 3 v 2. 0 a avg 2. 5 a peak fb4 lg 4 hg4 comp4 ss 4 comp4 ss4 clk 180 tsdh csp csn fb1 switcher 1 (sw1) adjustable always-on pwm/pfm asynchronous buck regulator switcher 3 (sw3) adjustable pwm asynchronous buck regulator switcher 4 (sw4) adjustable pwm synchronous buck controller high-side switch 1 (s1) with foldback limiting high-side switch 2 (s2) with foldback limiting switcher 2 (sw2) adjustable pwm asynchronous buck regulator lx1 lsw1 csw1 cin1 cboot1 cin2 csw2 csw3 csw4 lsw2 lsw3 vin1 boot 1 10 comp1 comp1 ss1 clk0 1.0 a adj avg 2.5 a peak 15 m rs shoot- through protec- tion 10 h 10 h 10 lsw4 h adj (5.7 v) 2.5 a avg 4.0 a peak 50 f vin3 vin3 bias ss 1 css1 rz1 cz1 rz2 cz2 rz4 cz4 cp4 cp3 cp2 cp1 rz3 cz3 css2 css3 0.68 f 22 nf 150 m 120 m 112 m 15 h 3 dsw1 a 40 v lx 4 boot 4 0.1 f v sw1 3a 40 v 3a 40 v vreg 1. 0 f en ens vins 1.0 to t a l 1.0 to t a l out2 load 2 1 f 50 v load 1 out1 825 k 1% 1m 1% mute logic ctmr 8to32 s de-glitch acci acco vbat buo bui acc switch 1% 22 .1 k 1% 78 .7 k 1% 475 k 1% 6.2 v 6.2 v bu 3 .3v tc7s h14f bu 3.3 v tc 7sh14f 35 v 4.7k 9.1 k 10 k 15 k 1 f 1 f 2200 a8600 f pgnd 200 k 200 k pok 3 current will not flow from acci to bui or any vinx pin tsdl 0 cctmr .1 f tsdl bu clean 50 k done charge set rst 2 a 2 a pok pok 2 pok 3 pok 4 200 k en/ pfm en en 2048 n 1.205 v 215 mv 3.3 to 5. 5 v 18.7 k 4.7 nf 27 pf 47 47 nf 47 nf k r fba1 r fbb1 147 k 10 pf audio amplifier mute bi as bi as 60 .4 k 60 .4 k 1% 5.0v en/sync 200 k vreg to microcontroller to microcontroller to microcontroller from microcontroller 3a 40 v 50 k 50 k v reg bias bias switch >3 .2 v and off on bias >ldo out ldo vin1 oscillator 180 shift with synchronization sq r sq r vin s uvlo pok 2 pok 4 tsd en s gnd vreg por tsdl tsdh tsdl 5.0 v charge pump 50 f 50 f 50 f 39.2 k 2.2 nf 27 pf 22 nf css4 22 nf 18.7 k 2.2 nf 27 pf 24.9 k 2.2 nf 27 pf vins uvlo + ? 3.70 v s1a 1 f 50 v s1a 1. 8 k 16 .2 k 4.7 k 14 .7 k 1.8 k 11 k vreg por 1.205v ref band gap v regporh v regporl vreg por vreg por vreg por vin3 vbat _filt vbat _ filt vbat _ filt vbat _filt 3a 40 v block active in low iq mode a b b a b current will not flow from acco, buo, mute, bias, vreg, fb1, pok, or outx to any vinx pin sw4 lower fet must not cause v sw4 to decay during prebias startup c optional: pok to out2 short protection for microcontroller optional: ens to out1 for short protection for microcontroller optional: to protect vins for field decay test pad c c d c c c a c c c c d optional: mute to vin1 short protection for amplifier schottky for sw4 may be omitted for very low current system only optional: to maintain v boot1 during very low v bat v sw2 v sw3 v sw4 delay 15 n r fba2 r fbb2 r fba3 r fbb3 r fba4 r fbb4 47 nf dsw2 cin3 dsw3 dsw4 cboot2 cboot3 cboot4 top level functional block diagram and typical application circuit
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com up p e r fe t on: q = 1 & t off,min = 0 upper fet off: fb x ov or 1x ocx = 1 or 1x bootx uv or ssinitx =1 or hiccupx = 1 lowe r fe t on : bootx uv & t off,min = 1 lowe r fe t off : s s in itx = 1 o r hiccupx = 1 sq rq lx 1,2 ,3 vin1/2/3 compx fbx ssx hiccupx ssi ni tx pwm com parator reset dominant clk 0 (sw 1/3 ) clk 180 (sw2) 400mv + ? + error a8600 am p lx 2, 3 vin2/3 i sensex 800mv ref sl ope comp 400mv pwm x rst on ilim g csa 5k 1k iss hicx iss su x 2. 3 v 0.3v fbx > 0.3v ssx > 2 .3 v ocx comparator & counter 0 = 30 counts 1 = 118 counts enable counter i sensex compx max boot monitor & counters 7x b ootx ov or 30x bootx uv ssx < 0. 2 v 0.2v fbx ov fbx uv 860mv 740mv reset dominant lx1 fa ult lx1 q bootx ? lxx bootx + ? lxx oscillator if fbx<0.4v then f /2 if hiccupx=1 then f /4 else f t off,min i fbx sw2 & sw3 only bootx tgx bgx sw1 only low ip pwm (sw1 only) uvlo on uvlo of f q rq s sq rq pokx de- glitch sw2 and sw3 only sw 1 fixed off-time pfm control i sense1 fb1 uvlo1 enable tg1 boot 1 on i peak wake /sleep sw1 only 1x boot 1 fau l t 1x lx1 fault low ip pwm: all pwm functions on & 50% i lim uvlox lx2, lx3 lx2,3 or lg2 fa ults sw2 and sw3 only tsdh (s w 2, s w3 only) en (s w 2, s w 3 only) vreg por en/ pfm (s w 1 onl y) sq rq clamp compx max en/ pfm figure 2. detailed functional block diagram for sw1, sw2, and sw3
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sq rq lx4 comp4 fb4 ss 4 pwm com parator reset dominant clk180 400mv + ? + error am p i sense4 800mv ref sl ope comp 400mv pwm 4 rst on ilim g csa q oscillator if fb 4 <0 .4 v th e n f / 2 if hiccup 4= 1 then f /4 else f t off,min i fb4 boot 4 vin3 csp csn hg4 lg 4 pgnd vin 3 q up p e r fe t on: q = 1 & t off,min = 0 up p e r fe t off: fb4 ov or 1x oc4 = 1 or 1x boot4 uv or ssinit4 =1 or hiccup4 = 1 lowe r fe t on: q = 1 & t off, min = 1 or boot4 uv & t off, min = 1 lowe r fe t off : ssinit4 = 1 or hiccup4 = 1 ga te driver non- ov e rla p hiccup4 ssi ni t 4 5k 1k iss hic4 iss su 4 2. 3 v 0.3v fb4 > 0.3v ss4 > 2.3v oc4 comparator & counter 0 = 30 counts 1 = 118 counts enable counter i sense4 comp4 max boot monitor & counters 7x b ootx ov or 30x bootx uv ss4 < 0.2v 0.2v fb4 ov fb4 uv 860mv 740mv reset dominant boot4 ? lx4 boot 4 + ? lx4 uvlo on uvlo of f q rq s sq rq pok 4 de- glitch uvlo4 lx4 lx4 or lg2 fa ults tsdh en vreg por sq rq clamp comp4 max a8600 figure 3. detailed functional block diagram for sw4
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit general specifications input supply current input supply current 1 i in1 v bias > 3.2 v, i sw1 = 0 ma ? 7.5 10 ma input supply current, pfm 1,3 (using components shown in typical application circuit diagram and table 3.) i lo_iq0 v in1 = 12 v, v sw1 = 3.3 v, v en/sync 0.4 v, buo and acco open, i sw1 = 40 a, t a = 25oc ?? 50 a i lo_iq1 v in1 = 12 v, v sw1 = 5.0 v, v en/sync 0.4 v, buo and acco open, i sw1 = 200 a, t a = 25oc ?? 250 a i lo_iq2 v in1 = 12 v, v sw1 = 6.5 v, v en/sync 0.4 v, buo and acco open, i sw1 = 1 ma, t a = 25oc ?? 750 a internal oscillator frequency lx1/2/3/4 switching frequency f osc 360 425 490 khz en/sync synchronization timing synchronization input frequency f sync 325 ? 525 khz synchronization input duty cycle d sync 45 50 55 % en/sync input en/sync pin high threshold v enih 3.0 v < v bias < 3.6 v, v en/sync rising ?? 2.0 v 4.5 v < v bias < 5.5 v, v en/sync rising ?? 2.6 v en/sync pin low threshold v enil 3.0 v < v bias < 3.6 v, v en/sync falling 0.8 ?? v 4.5 v < v bias < 5.5 v, v en/sync falling 1.2 ?? v en/sync hysteresis v enhys 3.0 v < v bias < 3.6 v, v enih ? v enil ? 200 ? mv 4.5 v < v bias < 5.5 v, v enih ? v enil ? 400 ? mv en/sync input resistance r enin 120 200 280 k en/sync turn-off delay t doff measured from en/sync pulled low to sw2/3/4, s1/2, and tsd turned off ? 15 ? pwm cycles t dlo_iq measured from en/sync pulled low or tsdh going high to sw1 entering low iq mode ? 2048 ? pwm cycles vreg output and bias input vreg output voltage v vreg v bias = 0 v 2.95 3.05 3.175 v vreg (regok rising) v regporhi v vreg rising 2.86 2.93 2.98 v vreg (bias switch off and por) v regporlo v vreg falling 2.85 2.90 2.96 v bias switch turn-on threshold v bias(th) v bias ? v vreg ? 31020mv bias switch voltage drop v biassw v bias ? v vreg ? 45 70 mv bias input voltage range v bias 3.2 ? 5.5 v power ok (pok) pok low condition output voltage v poko(l) i pok = 3 ma ?? 300 mv pok leakage 1 i pok(lkg) v poko = 5.0 v ? 1 ? 1 a continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com general specifications (continued) thermal protection sw1/2/3/4 tsd threshold 3 t tsdh sw1 to low iq mode after 2048 cycles, reset by cycling en/sync, or by a vreg por 150 165 180 oc s1/2 latched tsd threshold 3 t tsdl reset by cycling any of ens, en/sync, vins, or by a vreg por 140 155 170 oc sw1 (always-on, low iq, pwm/pfm regulator) input voltage input voltage range 2 v in1 4.0 ? 35 v uvlo start v uvloon1 v in1 rising 3.6 3.8 4.0 v uvlo stop v uvlooff1 v in1 falling 3.2 3.4 3.6 v uvlo hysteresis v uvlohys1 ? 400 ? mv voltage regulation feedback voltage accuracy v fb1 v in1 4.1 v, v fb1 = v comp1 788 800 812 mv output voltage setting range v sw1 v sw1 (min) value is design target, see footnote 2 for typ and max voltages 3.3 5.0 6.5 v output dropout voltage v sw(pwm)1 v in1 = 3.7 v, i sw1 = 50 ma 3.3 ?? v v in1 = 6.0 v, i sw1 = 1 a 5.0 ?? v low iq peak current limit i peak(lo_iq) 600 800 1000 ma low iq dc current capability i dc(lo_iq) 500 ?? ma dc low iq constant off time t off(lo_iq) 220 300 380 ns low iq maximum on time t on(lo_iq) 3.3 4 4.9 s low iq mode voltage ripple 3 v pp1(lo_iq) 8 v < v in1 < 12 v, configured as shown in the typical application circuit ?? 50 mv pp internal mosfet 2 high-side mosfet on-resistance r ds(on)hs1 t j = 25oc, i ds1 = 1.0 a ? 150 170 m high-side mosfet leakage 1 i hs(lkg)1 t j < 85c,v en/sync 0.8 v, v lx1 = 0 v, v in1 = 16 v ? 5 ? 5 a low-side mosfet on-resistance r ds(on)ls1 t j = 25oc ?? 10 boot regulator boot voltage enable threshold v boot(th)1 v boot1 rising 1.85 2.10 2.30 v boot voltage enable hysteresis v boot(hys)1 ? 375 ? mv error amplifier feedback input bias current 1 i fb1 ?30 ? ?8 na open loop voltage gain a vol1 v comp1 = 1.2 v 52 58 65 db transconductance g m1 400 mv < v fb1 550 750 950 a/v 0 v < v fb1 < 400 mv 275 375 475 a/v electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw1 (always-on, low iq, pwm/pfm regulator) (continued) error amplifier (continued) output current i ea1 v comp1 = 1.2 v ? 75 ? a maximum output voltage v eao(max)1 1.3 1.7 2.1 v minimum output voltage v eao(min)1 ?? 200 mv comp1 pull down resistance r comp1 fault condition ? 1 ? k pulse width modulation (pwm) pwm ramp offset v pwmoffset1 v comp1 set for 0% duty cycle ? 400 ? mv minimum controllable on-time t on(min)1 80 140 180 ns minimum switch off-time t off(min)1 40 95 135 ns comp1 to sw1 current gain g mpower1 ? 3.6 ? a/v slope compensation s e1 300 450 600 ma/ s overcurrent protection (ocp) pulse-by-pulse current limit i lim1 t on1 = t on(min)1 , f sw = f osc 3.9 4.4 4.9 a t on1 = (1 / f osc ) ? t off(min)1 , f sw = f osc 3.0 3.5 4.0 a overvoltage protection (ovp) output overvoltage threshold (sw1 disable) v ovo1 v fb1 rising, pwm mode 840 860 880 mv overvoltage hysteresis v ovohys1 v fb1 falling, relative to v ovo1 ?? 10 ? mv soft start ss1 hiccup reset voltage v ssrst1 v ss1 falling due to r ssflt1 140 200 275 mv ss1 switching frequency f ss1 0 v < v fb1 < 300 mv, v comp1 at maximum ? f sw1 /4 ? khz 0 v < v fb1 < 300 mv ? f sw1 /2 ? khz 300 mv < v fb1 ? f sw1 ? khz ss1 startup (source) current 1 i sssu1 hiccup mode disabled (no fault condition) ? 2.50 ? 2.00 ? 1.50 a ss1 hiccup (sink) current 1 i sshic1 hiccup mode enabled 0.75 1.00 1.25 a ss1 delay time t dss1 css1 = 0.68 f ? 136 ? ms ss1 ramp time t ssramp1 css1 = 0.68 f ? 272 ? ms ss1 pull down resistance r ssflt1 fault condition ? 5 ? k hiccup mode (pwm only, not in pfm) hiccup ocp enable threshold v hicen1 v ss1 rising ? 2.3 ? v hiccup operation ocp count t ocplim1 v ss1 > 2.3 v, v fb1 < 0.3 v ? 30 ? pwm cycles v ss1 > 2.3 v, v fb1 > 0.3 v ? 118 ? pwm cycles hiccup operation boot shorted count t bootuv1 ? 30 ? pwm cycles hiccup operation boot open count t bootopen1 ? 7 ? pwm cycles electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw2 (asynchronous buck regulator) input voltage input voltage range 2 v in2 4.4 ? 35 v uvlo start v uvloon2 v in2 rising 4.1 4.25 4.4 v uvlo stop v uvlooff2 v in2 falling 3.6 3.75 3.9 v uvlo hysteresis v uvlohys2 ? 500 ? mv voltage regulation feedback voltage accuracy v fb2 v in2 4.4 v, v fb2 = v comp2 788 800 812 mv output voltage setting range v sw2 v sw2 (typ) value is design target, see footnote 2 for min and max voltages 1.2 8.0 9.2 v output dropout voltage 3 v sw(pwm)2 v in2 = 6.0 v, i sw2 = 1 a 5.0 ?? v internal mosfet 2 high-side mosfet on-resistance r ds(on)hs2 t j = 25oc, i ds2 = 1.5 a ? 120 140 m high-side mosfet leakage 1 i hs(lkg)2 t j < 85c,v en/sync 0.8 v, v lx2 = 0 v, v in2 = 16 v ? 5 ? 5 a low-side mosfet on-resistance r ds(on)ls2 t j = 25oc ?? 10 boot regulator boot voltage enable threshold v boot(th)2 v boot2 rising 1.85 2.10 2.30 v boot voltage enable hysteresis v boot(hys)2 ? 375 ? mv error amplifier feedback input bias current 1 i fb2 ?100 ? ?8 na open loop voltage gain a vol2 v comp2 = 1.2 v 52 60 65 db transconductance g m2 400 mv < v fb2 550 750 950 a/v 0 v < v fb2 < 400 mv 275 375 475 a/v output current i ea2 v comp2 = 1.2 v ? 75 ? a maximum output voltage v eao(max)2 1.3 1.7 2.1 v minimum output voltage v eao(min)2 ?? 200 mv comp2 pull down resistance r comp2 fault condition ? 1 ? k pulse width modulation (pwm) pwm ramp offset v pwmoffset2 v comp2 set for 0% duty cycle ? 400 ? mv minimum controllable on-time t on(min)2 80 140 180 ns minimum switch off-time t off(min)2 40 95 135 ns comp2 to sw2 current gain g mpower2 ? 3.6 ? a/v slope compensation s e2 300 450 600 ma/ s electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw2 (asynchronous buck regulator) (continued) overcurrent protection (ocp) pulse-by-pulse current limit i lim2 t on2 = t on(min)2 , f sw = f osc 3.9 4.4 4.9 a t on2 = (1 / f osc ) ? t off(min)2 , f sw = f osc 3.0 3.5 4.0 a power ok (pok) thresholds for overvoltage (ov) and undervoltage (uv) pok threshold for overvoltage v pokov2 v fb2 rising 840 860 880 mv pok hysteresis for overvoltage v pokovhys2 v fb2 falling, relative to v pokov2 ?? 10 ? mv pok threshold for undervoltage v pokuv2 v fb2 falling 720 740 760 mv pok hysteresis for undervoltage v pokuvhys2 v fb2 rising, relative to v pokuv2 ? 10 ? mv power ok (pok) filtering pok delay time v pokdelay2 response to a step input ? 6 ? s soft start ss2 hiccup reset voltage v ssrst2 v ss2 falling due to r ssflt2 140 200 275 mv ss2 switching frequency f ss2 0 v < v fb2 < 300 mv, v comp2 at maximum ? f sw2 /4 ? khz 0 v < v fb2 < 300 mv ? f sw2 /2 ? khz 300 mv < v fb2 ? f sw2 ? khz ss2 startup (source) current 1 i sssu2 hiccup mode disabled (no fault condition) ? 30 ?20 ? 10 a ss2 hiccup (sink) current 1 i sshic2 hiccup mode enabled 5 10 20 a ss2 delay time t dss2 css2 = 22 nf ? 440 ? s ss2 ramp time t ssramp2 css2 = 22 nf ? 880 ? s ss2 pull down resistance r ssflt2 fault condition ? 5 ? k ss2 startup current ratio i sssutrk2 relative to i sssu3 or i sssu4 ? 15 ? +15 % hiccup mode hiccup ocp enable threshold v hicen2 v ss2 rising ? 2.3 ? v hiccup operation ocp count t ocplim2 v ss2 > 2.3 v, v fb2 < 0.3 v ? 30 ? pwm cycles v ss2 > 2.3 v, v fb2 > 0.3 v ? 118 ? pwm cycles hiccup operation boot shorted count t bootuv2 ? 30 ? pwm cycles hiccup operation boot open count t bootopen2 ? 7 ? pwm cycles electrical characteristics (continued) valid at 5.5 v v in 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw3 (asynchronous buck regulator) input voltage specifications input voltage range 2 v in3 4.4 ? 35 v uvlo start v uvloon3 v in3 rising 4.1 4.25 4.4 v uvlo stop v uvlooff3 v in3 falling 3.6 3.75 3.9 v uvlo hysteresis v uvlohys3 ? 500 ? mv voltage regulation feedback voltage accuracy v fb3 v in3 4.4 v, v fb3 = v comp3 788 800 812 mv output voltage setting range v sw3 v sw3 (typ) value is design target, see footnote 2 for min and max voltages 1.2 3.3 9.2 v output dropout voltage 3 v sw(pwm)3 configured as in ty, v in3 = 6.0 v, i sw3 = 1 a 5.0 ?? v internal mosfet parameters 2 high-side mosfet on-resistance r ds(on)hs3 t j = 25oc, i ds3 = 2.0 a ? 112 130 m high-side mosfet leakage 1 i hs(lkg)3 t j < 85c,v en/sync 0.8 v, v lx3 = 0 v, v in3 = 16 v ? 5 ? 5 a low-side mosfet on-resistance r ds(on)ls3 t j = 25oc ?? 10 boot regulator boot voltage enable threshold v boot(th)3 v boot3 rising 1.85 2.10 2.30 v boot voltage enable hysteresis v boot(hys)3 ? 375 ? mv error amplifier feedback input bias current 1 i fb3 ?100 ? ?8 na open loop voltage gain a vol3 v comp3 = 1.2 v 52 60 65 db transconductance g m3 400 mv < v fb3 550 750 950 a/v 0 v < v fb3 < 400 mv 275 375 475 a/v output current i ea3 v comp3 = 1.2 v ? 75 ? a maximum output voltage v eao(max)3 1.3 1.7 2.1 v minimum output voltage v eao(min)3 ?? 200 mv comp3 pull down resistance r comp3 fault condition ? 1 ? k pulse width modulation (pwm) pwm ramp offset v pwmoffset3 v comp3 set for 0% duty cycle ? 400 ? mv minimum controllable on-time t on(min)3 80 140 180 ns minimum switch off-time t off(min)3 40 95 135 ns comp3 to sw3 current gain g mpower3 ? 3.6 ? a/v slope compensation s e3 300 450 600 ma/ s electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw3 (asynchronous buck regulator) (continued) overcurrent protection (ocp) pulse-by-pulse current limit i lim3 t on3 = t on(min)3 , f sw = f osc 3.9 4.4 4.9 a t on3 = (1 / f osc ) ? t off(min)3 , f sw = f osc 3.0 3.5 4.0 a power ok (pok) thresholds for overvoltage (ov) and undervoltage (uv) pok threshold for overvoltage v pokov3 v fb3 rising 840 860 880 mv pok hysteresis for overvoltage v pokovhys3 v fb3 falling, relative to v pokov3 ?? 10 ? mv pok threshold for undervoltage v pokuv3 v fb3 falling 720 740 760 mv pok hysteresis for undervoltage v pokuvhys3 v fb3 rising, relative to v pokuv3 ? 10 ? mv power ok (pok) filtering pok delay time v pokdelay3 response to a step input ? 6 ? s soft start ss3 hiccup reset voltage v ssrst3 v ss3 falling due to r ssflt3 140 200 275 mv ss3 switching frequency f ss3 0 v < v fb3 < 300 mv, v comp3 at maximum ? f sw3 /4 ? khz 0 v < v fb3 < 300 mv ? f sw3 /2 ? khz 300 mv < v fb3 ? f sw3 ? khz ss3 startup (source) current 1 i sssu3 hiccup mode disabled (no fault condition) ? 30 ?20 ? 10 a ss3 hiccup (sink) current 1 i sshic3 hiccup mode enabled 5 10 20 a ss3 delay time t dss3 css3 = 22 nf ? 440 ? s ss3 ramp time t ssramp3 css3 = 22 nf ? 880 ? s ss3 pull down resistance r ssflt3 fault condition ? 5 ? k ss3 startup current ratio i sssutrk3 relative to i sssu2 or i sssu4 ? 15 ? +15 % hiccup mode hiccup ocp enable threshold v hicen3 v ss3 rising ? 2.3 ? v hiccup operation ocp count t ocplim3 v ss3 > 2.3 v, v fb3 < 0.3 v ? 30 ? pwm cycles v ss3 > 2.3 v, v fb3 > 0.3 v ? 118 ? pwm cycles hiccup operation boot shorted count t bootuv3 ? 30 ? pwm cycles hiccup operation boot open count t bootopen3 ? 7 ? pwm cycles electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw4 (synchronous buck controller with gate drivers) input voltage specifications input voltage range 2 v in3 4.4 ? 35 v uvlo start v uvloon4 v in3 rising 4.1 4.25 4.4 v uvlo stop v uvlooff4 v in3 falling 3.6 3.75 3.9 v uvlo hysteresis v uvlohys4 ? 500 ? mv voltage regulation feedback voltage accuracy v fb4 v in3 4.4 v, v fb4 = v comp4 788 800 812 mv output voltage setting range v sw4 v sw4 (typ) value is design target, see footnote 2 for min and max voltages 1.2 5.7 6.5 v output dropout voltage 3 v sw(pwm)4 configured as in typical application circuit, v in4 = 6.0 v, i sw4 = 1 a 5.0 ?? v external mosfet gate drivers hg4 high output voltage v hg4on measured as v hg4 ? v in3 4.0 6.0 6.7 v hg4 low output voltage v hg4off measured as v hg4 ? v lx4 , i hg4 = 100 ma ? 0.20 0.40 v hg4 sink current 1 i hg4on v hg4 = v in3 ? 2 v ? 1000 ? ma hg4 source current 1 i hg4off v hg4 = v in3 ? 2 v ?? 150 ? ma lg4 high output voltage v lg4on v in3 5.5 v 4.0 6.0 7.2 v lg4 low output voltage v lg4off i lg4 = 100 ma ? 0.25 0.50 v lg4 source current 1 i lg4on ?? 500 ? ma lg4 sink current 1 i lg4off ? 600 ? ma boot regulator boot voltage enable threshold v boot(th)4 v boot4 rising 2.25 2.60 2.90 v boot voltage enable hysteresis v boot(hys)4 ? 375 ? mv error amplifier feedback input bias current 1 i fb4 ?100 ? ?8 na open loop voltage gain a vol4 v comp4 = 1.2 v 52 60 65 db transconductance g m4 400 mv < v fb4 550 750 950 a/v 0 v < v fb4 < 400 mv 275 375 475 a/v output current i ea4 v comp4 = 1.2 v ? 75 ? a maximum output voltage v eao(max)4 1.3 1.7 2.1 v minimum output voltage v eao(min)4 ?? 200 mv comp4 pull down resistance r comp4 fault condition ? 1 ? k electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com sw4 (synchronous buck controller with gate drivers) (continued) pulse width modulation (pwm) pwm ramp offset v pwmoffset4 v comp4 set for 0% duty cycle ? 400 ? mv comp4 cycle skip level v compskip4 v ss4 < 2.3 v ? 200 ? mv minimum controllable on-time t on(min)4 40 100 150 ns minimum switch off-time t off(min)4 80 120 160 ns comp4 to sw4 current gain g mpower4 ? 63 ? (a?m )/v slope compensation s e4 4.5 6.8 9.0 mv/ s overcurrent protection (ocp) pulse-by-pulse current limit i lim4 t on4 = t on(min)4 62 75 88 mv t on4 = (1 / f osc ) ? t off(min)4 , f sw = f osc 48 60 72 mv power ok (pok) thresholds for overvoltage (ov) and undervoltage (uv) pok threshold for overvoltage v pokov4 v fb4 rising 840 860 880 mv pok hysteresis for overvoltage v pokovhys4 v fb4 falling, relative to v pokov4 ?? 10 ? mv pok threshold for undervoltage v pokuv4 v fb4 falling 720 740 760 mv pok hysteresis for undervoltage v pokuvhys4 v fb4 rising, relative to v pokuv4 ? 10 ? mv power ok (pok) filtering pok delay / de-glitch v pokdelay4 response to a step input ? 6 ? s soft start ss4 hiccup reset voltage v ssrst4 v ss4 falling due to r ssflt4 140 200 275 mv ss4 switching frequency f ss4 0 v < v fb4 < 300 mv, v comp4 at maximum ? f sw4 /4 ? khz 0 v < v fb4 < 300 mv ? f sw4 /2 ? khz 300 mv < v fb4 ? f sw4 ? khz ss4 startup (source) current 1 i sssu4 hiccup mode disabled (no fault condition) ? 30 ?20 ? 10 a ss4 hiccup (sink) current 1 i sshic4 hiccup mode enabled 5 10 20 a ss4 delay time t dss4 css4 = 22 nf ? 440 ? s ss4 ramp time t ssramp4 css4 = 22 nf ? 880 ? s ss4 pull down resistance r ssflt4 fault condition ? 5 ? k ss4 startup current ratio i sssutrk4 relative to i sssu2 or i sssu3 ? 15 ? +15 % electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit continued on the next page? hiccup mode hiccup ocp enable threshold v hicen4 v ss4 rising ? 2.3 ? v hiccup operation ocp count t ocplim4 v ss4 > 2.3 v, v fb4 < 0.3 v ? 30 ? pwm cycles v ss4 > 2.3 v, v fb4 > 0.3 v ? 118 ? pwm cycles hiccup operation boot shorted count t bootuv4 ? 30 ? pwm cycles hiccup operation boot open count t bootopen4 ? 7 ? pwm cycles high-side switches (s1, s2) input voltage range 2 v ins 4.5 ? 35 v uvlo start v uvloons v ins rising 4.0 4.2 4.4 v uvlo stop v uvlooffs v ins falling 3.5 3.7 3.9 v uvlo hysteresis v uvlohyss ? 500 ? mv overvoltage threshold (rising) v ovrises v ins rising 17.2 18.3 19.4 v overvoltage threshold (falling) v ovfalls v ins falling 16.9 18.0 19.0 v mosfet on-resistance r ds(on)s i s = 250 ma, t j = 25oc ? 1.00 1.15 voltage drop v s v ins 5.5 v, i s = ? 250 ma, t j = 25oc ? 250 290 mv v ins 4.5 v, i s = ? 100 ma, t j = 25oc ? 100 115 mv current limit 1,2 i peaks not continuous ? 570 ? 450 ? 270 ma foldback current 1 i fldbks v outx = 0 v, v ins = 15 v ? 150 ? 100 ? 55 ma leakage current 1 i lkgs ? 1 ? 1 a pull down resistance r flts ? 200 ? k turn-on delay t ds v ens rise to 10% of v outx 10 60 200 s output rise time t rs 237 / 1 f load, 10% to 90% of v outx 10 60 200 s ens high threshold v ensh ?? 2.0 v ens low threshold v ensl 0.8 ?? v ens hysteresis v enshys ? 100 ? mv ens input resistance r inens 120 200 280 k
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics (continued) valid at 5.5 v v inx 26 v, ?40c t a 125oc, ?40c t j 125oc; unless otherwise specified characteristic symbol test conditions min. typ. max. unit bu and acc comparators bui and acci detect threshold v det 1.181 1.205 1.229 v bui and acci input bias 1 i bui, i acci v bui or v acci 5.0 v 30 65 100 na buo delay t dbuo 20 mv input overdrive ? 1.5 5 s acco delay t dacco 20 mv input overdrive ? 1.5 5 s buo and acco output voltage v buoh , v accoh i buo = i acco = ? 3 ma v bias ? 300 mv ? v bias v v buol , v accol i buo = i acco = 3 ma ?? 300 mv buo and acco forced low v buolf , v accolf i buo = i acco = 3 ma , 2 v < v bias < 3 v, v in1 < 5.5 v ?? 300 mv ctmr and mute ctmr charge current 1 i ctmr(chrg) mute = low, v ctmr rising ? 2.50 ? 2.00 ? 1.50 a ctmr discharge current 1 i ctmr(dis) mute = low, v ctmr falling 1.50 2.00 2.50 a ctmr upper threshold v ctmrvh v ctmr rising 1.181 1.205 1.229 v ctmr lower threshold v ctmrvl v ctmr falling 185 215 245 mv ctmr pull down resistance r ctmr mute = high ? 50 ? k mute low output voltage v muteol i mute = 3 ma ?? 300 mv mute leakage current 1 i mutelkg v mute = 5.0 v ? 1 ? 1 a mute rising delay t drmute c ctmr = 0.10 f 725 1000 1275 ms mute falling delay (de-glitch) t dfmute from buo set low to mute low 8 16 32 s mute self-protect shutoff v mute(off) ? 8.5 ? v 1 negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin. 2 thermally limited depending on input voltage, duty cycle, regulator load currents, pcb layout, and airflow. 3 determined by design and characterization, not production tested.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 4. sw1 pwm timing diagram with en/sync pin high 15 vout1 shorted to gnd boot faults en/sync for 15 cycles or vreg por clears the tsdh latch 2048 2048 diode fault boot faults mode acco en/sync tsdh oc hic_en hiccup oc fault boot fault vin1 vout1 ss1 comp1 diode fault lx1 tsdl f f / 4 f / 2 f / 2 f / 2 f / 2 ss pwm oc hiccup hiccup oc ss pwm hiccup pwm hiccup pwm tsdl / tsdh low iq due to tsdh (internal osc is operational) pwm f f f f f/4 s s ss f / 2 ss low iq vfb<0 .3v : x30 vfb>0.3v: x120 s s hicc up f / 2 ss hi c diode fault x1 x1 x7 open x30 uv x7 open x30 uv to 2.3v from 2.3v to 2.3v from 2.3 v off vfb<0.3v: x30 vfb>0.3v : x120
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boot faults boot faults boot faults en/sync or acco low-ip pwm low-ip pwm low-ip pwm ss>2.3v ? fb>0.74v ss>2.3v ? fb>0.74v diode fault mode acco en/sync tsdh oc hic_en hiccup oc fault boot fault vin1 vout1 ss1 comp1 diode fault lx1 tsdl f / 2 ss lo_iq hiccup oc f f / 4 f / 2 f/4 f / 2 f / 2 f f / 2 ss ss lo_iq hiccup s s lo_iq x1 pwm o c hiccup f / 2 f / 2 x1 f / 2 f lo_iq hicc up hiccup ss ss diode fault x1 f / 2 f / 2 x1 s s hicc up ss hi c ss hi c f s s diode fault f ss>2.3v ? fb>0.74v ss>2.3v ? fb>0.74v x7 open x30 uv x7 open x30 uv x7 open x30 uv to 2.3v from 2.3v to 2.3v from 2.3v to 2.3v from 2.3v to 2.3v from 2.3v low-ip pwm 2048 2048 2048 2048 off vout1 shorted to gnd vfb<0.3v: x30 vfb>0.3 v: x120 vfb<0.3v: x30 vfb>0.3 v: x120 figure 5. sw1 low iq pwm and low ip pfm timing, with en/sync low and acci low
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com en/sync for 15 cycles or vreg por clears the tsdh latch boot faults en reset diode fault boot faults mode acco en/sync tsdh oc hic_en hiccup oc fault boot fault vin2 vout2 ss2 comp2 diode fault lx2 tsdl f f / 4 f / 2 f / 2 f / 2 f / 2 f / 2 ss pwm oc hiccup hiccup oc ss pwm hiccup pwm ss pwm tsdl tsdh tsdh pwm f f f f f/4 off off s s ss ss 15 15 f / 2 s s 15 reset s s hicc up x1 off x7 open x30 uv x7 open x30 uv to 2.3 v from 2.3v 15 off vfb<0.3 v: x30 vfb >0.3v: x120 vfb <0.3v: x30 vfb>0 .3v : x120 figure 6. sw2, sw3, and sw4 pwm timing
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ens i out,sx v out, sx sx_ foldback t j tsdh 165 c 155 c > 450 ma typ ~vin s s1/2 latch_off en/sync lx 2, 3, 4 reset sx reset sx reset tsdh a tsdl bc pwm2 /3/ 4_latch _off figure 7. s1 and s2 timing a. the load on one of the high-side switches increases until it enters foldback. the a8600 junction temperature increases. when the junction temperature exceeds 155oc (tsdl) both high- side switches (s1, s2) are latched off. this state is maintained until the high-side switches are reset via the ens. b. the loads on the a8600 increase and the junction temperature begins to increase. when the junction temperature exceeds 155oc (tsdl) both high-side switches (s1, s2) are latched off. in this case, even though the switches are shut off, the junction temperature continues to increase. when the junction temperature exceeds 165oc (tsdh) switching regulators sw2, sw3, and sw4 are also latched off, and sw1 enters low iq pfm mode. after tsdh, both high side switches (s1, s2) and the switching regulators sw2, sw3, and sw4 remain latched off until they are reset via en/sync. c. the load on one of the high-side switches increases until it enters foldback. the junction temperature increases but does not exceed 155oc (tsdl). when the load on the high-side switch decreases, the switch exits foldback and the output voltage recovers.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com bui vreg buo t d1 t d1 t d1 t d1 1.205v bu o , acc o , mute valid 3v 2v bu o , acc o, mute latched low bu o , acc o , mute undefined ctmr mute 1.205 v t d,mute t mu te t mu te t d,mute acci acco t d2 t d2 t d2 1. 205 v t d2 tsdl 215 mv retrigger retrigger 16 s typ vbias 750 mv v bias > 3.2 and v bias > ldo out ldo out vin1 removed reg_ok (internal signal ) 16 s typ figure 8. bux, accx and mute/ctmr timing
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description overview the a8600 is a highly sophisticated, multi-function ic that incorporates all the control and protection circuitry necessary to provide the power supply requirements of next generation car audio and infotainment systems. the a8600 features three adjustable asynchronous peak cur- rent mode buck regulators with internal mosfets. these three regulators, sw1, sw2, and sw3, can continuously supply 1.0 a, 2.0 a and 2.5 a respectively. a synchronous controller, sw4, was designed to deliver up to 4 a but can be configured for as much as 8 a by setting the sense resistor accordingly. sw1 is an always-on buck regulator that provides low quiescent input current (low iq) mode. when the en/sync and acci pins are held low, sw1 employs pulse frequency modulation (pfm) to draw only 10s of microamperes from the input supply while delivering 3.3v, 5.0v, or 6.5v at no load. sw4 is an adjustable, synchronous, peak current mode buck controller with internal mosfet gate drivers and externally adjustable current limit. in addition, the a8600 incorporates two 1 high-side switches, s1 and s2) which typically provide 250 ma (dc) and 450 ma (peak), with foldback type overcurrent protection. for thermal reasons, s1 and s2 are allowed to be on only for input voltages up to approximately 18.3 v. the a8600 also offers two detectors (that is, comparators) for sensing both battery voltage (bu circuit) and battery voltage remotely applied through a key type ignition switch (acc cir- cuit). there is also a mute output with a programmable delay set by a capacitor at the ctmr pin. reference voltage the a8600 incorporates an internal reference that allows output voltages as low as 0.8 v. the accuracy of the internal reference is 1.5% across the operating temperature range. the output volt- age of each regulator is adjusted by connecting a resistor divider between the respective v swx nodes and fbx pins of the a8600, as shown in the typical application diagram. pwm switching frequency the pwm switching frequency of the a8600 is fixed at 425 khz and has an accuracy of 15% across the operating temperature range. the four buck switchers are interleaved at 180 intervals: sw1 and sw3 turn on at 0, and sw2 and sw4 turn on at 180. during startup, the pwm switching frequency is reduced to 50% of the nominal frequency until fbx exceeds 300 mv. this is done to improve output regulation when v swx is starting to ramp upward and the pwm control loop is operating at the minimum controllable on-time and requires very low duty cycles. if the voltage at the fbx pin is less than 300 mv, and the compx voltage reaches its maximum level, the pwm switching fre- quency is reduced to 25% of the nominal frequency. this is done because a very low fbx voltage combined with a maximum compx voltage indicates the regulator output is shorted to ground. the extra-low switching frequency allows additional off (decay) time between lxx pulses so the inductor current does not climb to a value that may damage the a8600 or the output inductor. enable/synchronization input (en/sync) the enable/synchronization input (en/sync pin) provides two major functions. first, the en/sync pin is a control input that sets the operating mode of the a8600. when en/sync is a logic high, all 4 switchers operate in pwm mode and the high-side switches turn on or off via the ens input. when en/sync is a logic low, sw1 operates in low current keep-alive (low iq) mode, and sw2, sw3, sw4, s1, and s2 are turned off. second, when an external clock is applied to the en/sync pin, the a8600 wakes-up, completes soft start at the nominal pwm frequency, and then synchronizes its pwm to the external clock. the external clock may be used to either increase or decrease the a8600 nominal pwm frequency. synchronization operates when pwm is in the range from 325 to 550 khz. when using synchro- nization, the external clock pulses must satisfy the pulse width, duty cycle, and rise/fall time requirements shown in the electrical characteristics table in this data sheet. when en/sync transitions to logic high, the a8600 turns on and then, provided there are no fault conditions, sw2, sw3, and sw4 initiate soft start and the output voltages will ramp to their final voltage in the time set by the soft start capacitors (cssx). when en/sync transitions to low, then the a8600 will wait 2048 pwm cycles before transitioning sw1 from pwm to pfm mode. however after en/sync transitions to low, the a8600 will wait only 15 pwm cycles before shutting off sw2, sw3, sw4, s1, and s2.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com bias input pin, ratings, and connections when the a8600 is powering up, it operates an internal ldo regulator directly from vin1. however, vin1 is a relatively high voltage and an ldo regulator is very inefficient and generates heat. to improve efficiency, especially in pfm mode, a bias input is utilized. for most applications, the bias pin should be connected directly to the output of sw1. when v sw1 rises to an adequate level (approximately 2.93 v), the a8600 stops using the inefficient ldo and begins running its control circuitry directly from the output of sw1. this makes the a8600 more efficient and cooler. the bias pin is designed to operate in the range from 3.2 to 5.5 v. if the output of sw1 is in this range, then the bias pin simply should be routed directly to the v sw1 node. however, if the output of sw1 is in the range from 5.6 to 6.5 v, then a very small ldo regulator, capable of at least 10 ma, must be used to reduce the output at v sw1 to either 3.3 v or 5.0 v before routing it to the bias pin. transconductance error amplifier the transconductance error amplifier primary function is to control the output voltage of the switchers. the error amplifier circuit is shown in figure 9. here, it is shown as a three-terminal input device with two positive and one negative input. the nega- tive input is simply connected to the fbx pin and is used to sense the feedback voltage for regulation. the two positive inputs are used for soft start and steady-state regulation. the error amplifier performs an analog or selection between its two positive inputs. the error amplifier regulates either to the soft start pin voltage (minus an offset of 400 mv) or to the a8600 internal reference, whichever is lower. to stabilize the regulator, a series rc compensation network (rzx and czx) must be connected from the error amplifier out- put (the compx pin) to gnd as shown in the typical applica- tion diagram. in some instances, an additional, relatively low value capacitor (cpx) may be connected in parallel with the rzx/ czx components to roll-off the loop gain at higher frequencies. however, if the cpx capacitor is too large the phase margin of the converter may be reduced. if the switcher is disabled or a fault occurs, the compx pin is immediately pulled to gnd via approximately 1 k and pwm switching is inhibited. slope compensation the a8600 incorporates internal slope compensation to allow pwm duty cycles above 50% for a wide range of input/output voltages and inductor values. as shown in the functional block diagram the slope compensation signal is added to the sum of the current sense amplifier output and the pwm ramp offset. the slope compensation is based on the internal oscillator at 425 khz and does not scale when the regulators are synchronized to an external clock. current sense amplifiers the a8600 incorporates high-bandwidth current sense ampli- fiers to monitor the current in the upper mosfets of the three asynchronous regulators; sw1, sw2, and sw3. for the synchro- nous controller, sw4, a high-bandwidth differential amplifier is provided. the positive and negative inputs to this amplifier are csp and csn, respectively. as shown in the typical application diagram, the csp and csn pins must be routed to a discrete, cur- rent sense resistor, rs, in series with the sw4 output inductor. power mosfets the a8600 includes high-side n-channel mosfets with low r ds(on) , for sw1 (150 m ), sw2 (120 m ), and sw3 (112 m ) capable of continuously supplying 1.0 a, 1.5 a, and 2 a, respec- tively. the a8600 also includes a 10 low-side mosfet for each regulator to insure the boot capacitor is always charged. the typical r ds(on) increase versus temperature is shown in figure 10. + - + error amplifier compx ssx v fbx v ref 800 mv 400 mv figure 9. an a8600 error amplifier
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boot regulators each of the four switchers has a regulator to charge its boot capacitor. the boot regulators detect undervoltage and overvolt- age of the boot capacitor. also, the boot regulators have a current limit circuit to protect the boot regulator during a short circuit condition. sw1, sw2, and sw3 derive their boot voltage from vin1, vin2, and vin3, respectively. however, sw4 does not have a vin pin because it drives external mosfets. there- fore, sw4 derives its boot voltage from the vin3 pin. this sets a requirement that v in3 should be approximately equal to the supply voltage at the drain of the external, high-side mosfet (which could be considered to be v in4 ). sw1/2/3/4 pulse width modulation (pwm) mode the a8600s four buck switchers utilize fixed-frequency, peak current mode control to provide excellent load and line regula- tion, fast transient response, and ease of compensation. a high-speed comparator and control logic, capable of pulse widths less than 180 ns, is included for each of the four buck switchers. the inverting input of the comparator is connected to the output of the error amplifier. the non-inverting input is connected to the sum of the current sense signal, the slope compensation, and a dc offset voltage (v pwmoffsetx , nomi- nally 400 mv). at the beginning of each pwm cycle, the clk signal sets the pwm flip-flop and the upper mosfet is turned on. when the summation of the dc offset, slope compensation, and current sense signal, rises above the error amplifier voltage the pwm flip-flop is reset and the upper mosfet is turned off. the pwm flip-flop is reset dominant so the error amplifier may override the clk signal in certain situations. for example, at very light loads or extremely high input voltage the error amplifier temporarily reduces its output voltage below the 400 mv dc offset and the pwm flip-flop ignores one or more of the incoming clk pulses. the upper mosfet does not turn on and the regulator skips pulses to maintain output voltage regulation. in pwm mode all of the a8600 fault detection circuits are active. see the timing diagrams section for diagrams showing how faults are handled when in pwm mode. also, the protection features section of this datasheet provides a detailed description of each fault and table 1 presents a summary. sw1 low ip pwm mode sw1 supports two different levels of pwm current limit: 100% current limit mode, which is normal pwm operation, and low ip pwm mode, in which the current is limited to about 50% of the typical current limit. low ip pwm mode is invoked when sw1 is commanded to be in low iq pfm mode (see next section) but is either soft starting (v fb1 < 700 mv) or a fault has occurred. the purpose of low ip pwm mode is to give priority to main- taining reliable regulation of v sw1 while enabling all the pro- tection circuits inside the a8600 (high precision comparators, timers, and counters) that are normally off during low iq pfm mode. there are several faults that cause a transition from low iq pfm mode to low ip pwm mode: a missing asynchro- nous diode, an open or shorted boot capacitor, v sw1 shorted to ground, or lx1 shorted to ground. see the timing diagrams sec- tion for operation of sw1 in normal pwm mode, and operation of sw1 when it transitions from low iq pfm mode to low ip pwm mode. sw1 pulse frequency modulation (pfm) and low iq mode sw1 is an always-on buck regulator, with both pwm and pfm modes of operation (pwm mode is described in the previous sec- tion). sw1 operates in low iq pfm mode if both the en/sync and acci pins are held low continuously for 2048 clock cycles. 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 60 80 100 120 160 140 40 temperature (c) normalized on-resistance, r ds(on) figure 10. typical mosfet r ds(on) versus temperature
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com in pfm mode, sw1 operates with a switching frequency that depends on the load condition. the average current drawn from the input supply depends primarily on the load and how often the a8600 must wake up to maintain regulation. in pfm mode, a comparator monitors the voltage at fb1. if the voltage at fb1 is above approximately 800 mv, the a8600 will remain in keep-alive mode and draw extremely low current from the input supply. if the voltage at the fb1 pin drops below approximately 800 mv, the a8600 will wake up, and after a delay of approximately 2 s for the ic to fully power-up, turn on the upper mosfet. v sw1 rises at a rate dependent on the input voltage, inductor value, and output capacitance. the upper mosfet is turned off when either: (1) the upper mosfet (that is, the output inductor) current reaches approxi- mately 800 ma, or (2) the upper mosfet has been on for approximately 4 s. after the upper mosfet is turned off, the a8600 will delay approximately 300 ns and either: (1) turn the mosfet on again if the voltage at fb1 is still below 800 mv or (2) return to the extremely low current keep-alive mode. figures 11 and 12 demonstrate pfm mode operation for a light load and an increased load, respectively. in pfm mode the following faults are detected: a missing asynchronous diode, an open or shorted boot capacitor, v sw1 shorted to ground, or lx1 shorted to ground. as described in the previous section for pwm mode, if any of these faults occur the a8600 will transition from low iq pfm mode to low ip pwm mode, and operate at 50% of the normal pwm current limit. see the timing diagrams section for operation of sw1 in low iq pfm mode. in pfm mode the a8600 dissipates very little power, so the ther- mal monitoring circuit (tsd) is not required and is disabled to minimize the quiescent current. soft start (startup) and inrush current control inrush currents to the 4 switchers are controlled by the soft start function. when the a8600 is enabled and all faults are cleared, the soft start pin, ssx, will source i sssux and the voltage on the soft start capacitor, cssx, will ramp upward from 0 v. when the voltage at the soft start pin exceeds approximately 400 mv, the error amplifier slews its output voltage above the pwm ramp offset (v pwmoffsetx ). at that instant, the upper and lower mosfets will begin switching. as shown in figure 13, there is a delay (t dssx ) between when the enable pin transitions high and the combination of the soft start voltage exceeding 400 mv and the error amplifier slewing its output enough to initiate pwm switching. once the a8600 begins switching, the error amplifier will regulate the voltage at the fbx pin to the ssx pin voltage, minus approximately 400 mv. during the active portion of soft start, the figure 11. sw1 pfm operation at v in1 = 12 v, v sw1 = 3.3 v, v sw1 = 50 ma load, lx1 turns on once every 26 s to regulate v sw1 ; shows v sw1 (ch1, 100 mv/div.), v lx1 (ch2, 5 v/div.), i lx1 (ch3, 500 ma/div.), t = 5 s/div. figure 12. sw1 pfm operation at v in1 = 12 v, v sw1 = 3.3 v, v sw1 = 120 ma load, lx1 turns on twice every 18 s to regulate v sw1 ; shows v sw1 (ch1, 100 mv/div.), v lx1 (ch2, 5 v/div.), i lx1 (ch3, 500 ma/div.), t = 5 s/div. t v sw1 i lx1 v lx1 3.3 v 800 ma c1 c3 c2 t v sw1 i lx1 v lx1 t off 300 ns 3.3 v 800 ma c1 c3 c2
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 29 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com voltage at the ssx pin rises from 400 mv to 1.2 v (a difference of 800 mv), the voltage at the fbx pin rises from 0 v to 800 mv, and the switcher output voltage (v swx ) will rise from 0 v to the setpoint determined by the feedback (fbx pin) resistor divider. when the voltage at the soft start pin reaches approximately 1.2 v, the error amplifier will change mode and begin regulat- ing the voltage at the fbx pin to the a8600 internal reference, 800 mv. the voltage at the soft start pin will continue to rise to about 3.3 v. complete soft start operation from 0 v swx is shown in figure 13. if the a8600 is disabled or a fault occurs, the internal fault latch is set and the soft start pin is discharged via approximately 5 k . the a8600 will clear the internal fault latch when the voltage at the ssx pin decays to approximately 200 mv (v ssrstx ). if the a8600 enters hiccup mode, the capacitor on the soft start pin is discharged by a current sink, i sshicx . therefore, the soft start capacitor (cssx) not only controls the startup time but also the time between soft start attempts. hiccup mode operation is discussed in more detail in the hiccup mode protection section of this datasheet. for initial startup, when the voltage at the fbx pin is between 0 and 300 mv, the pwm switching frequency, f sw , is reduced to f sw /2. this is done to achieve the extremely low duty cycles required for precise regulation when v inx is relatively high and v swx is near 0 v. after v fbx rises above 300 mv, the pwm switching frequency is increased to f sw . if the output of the switcher is shorted to ground, the voltage at the fbx pin will remain less than 300 mv and the voltage at the compx pin will reach its maximum value. if these two conditions occur, the pwm switching frequency is reduced to f sw /4 to allow additional off (decay) time between lxx pulses. this prevents the inductor current from rising to an unusually high value that may damage the a8600 or the output inductor. prebiased startup if the output of any of the regulators is prebiased to some volt- age, the a8600 will modify the normal startup routine to prevent discharging the output capacitors. as described previously, the error amplifier usually becomes active when the voltage at the soft start pin exceeds 400 mv. if the output is prebiased the fbx pin will be at some non-zero voltage. the a8600 will not start switching until the voltage at the soft start pin increases to approximately v fbx + 400 mv. when the soft start voltage exceeds this value, the error amplifier becomes active, the voltage at the compx pin rises, pwm switching starts, and v swx will ramp upward starting from the prebias level. figure 14 shows startup when the output voltage is prebiased to 2.0 v. high-side switches (s1 and s2) the a8600 contains two 1 high-side switches, s1 and s2, capable of delivering at least 250 ma each. the vins pin pro- vides input voltage and current to both s1 and s2. the outputs of s1 and s2 are at out1 and out2, respectively. both high- side switches are constructed from two back-to-back, series mosfets so current will not flow in the reverse direction (back figure 13. normal startup to v swx = 3.3 v at i swx = 1.6 a load; shows v en/sync (ch1, 10 v/div.), v swx (ch2, 1 v/div.), v comp (ch3, 500 mv/div.), v ssx (ch4, 1 v/div.), v swx (ch5, 1 a/div.), t = 500 s/div. figure 14. pre-biased startup from v swx = 2 v rising to 3.3 v at i swx = 1.6 a load; shows v en/sync (ch1, 10 v/div.), v swx (ch2, 1 v/div.), v comp (ch3, 500 mv/div.), v ssx (ch4, 1 v/div.), v swx (ch5, 1 a/div.), t = 500 s/div. t v en/sync v compx v swx v ssx i swx v swx rises from 2 v, does not drop to 0 v switching delayed until v ssx = v fbx + 400 mv 2 v 400 mv 3.3 v c1 c5 c4 c3 c2 t v swx v ssx i swx 1.2 v 400 mv 3.3 v c1 c5 c4 c3 c2 v compx v en/sync t dssx t ssx
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 30 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com to vins) through the switches. s1 and s2 are simultaneously controlled on or off by the ens pin. the a8600 contains an inter- nal charge pump to provide gate drive to s1 and s2. if out1 or out2 is pulled down relatively slowly by a heavy load, the switch will protect itself by limiting its current to about 350 ma dc . if the output of s1 or s2 drops below 8 v, the switch will begin to foldback the current. at 0 v output, each switch typically delivers only 100 ma. however if out1 or out2 is very quickly shorted to ground, the switch will allow a relatively high peak current, approximately 800 ma(peak) at v ins = 18 v, for a short time. this scheme allows for minimal power dissipa- tion while allowing out1/out2 startup with capacitive loads up to 1 f. for thermal reasons, if vins exceeds approximately 18.3 v, both s1 and s2 are turned off. figure 15 shows the typical dc fold back characteristics of the high-side switches. figure 16 shows a high-side switch turn- ing on with v ins = 12 v and a 40 /22 f load. in figure 16, notice the switch is starting with foldback limiting, allowing only 100 ma when v outx = 0 v, increasing the current to about 400 ma when v outx exceeds 5 v, and providing full output voltage with a 300 ma load. without foldback control, the switch would have allowed an extremely high peak current due to the capacitive load (> 20 a) and the a8600 may have been damaged or caused some other system level malfunction, such as uvlo of the entire ic. in some applications, s1 and s2 are connected to a wiring har- ness to supply a remote load at a relatively long distance from the a8600. the wiring harness will introduce significant series inductance (4 to 6 h) between the outx pin and the actual load. this forms an lc tank circuit with very low resistance. if the load is short circuited to ground, the outx pin will transi- tion or ring below ground for a short time. to protect the a8600, allegro strongly recommends the use of a 1 a, 30 v (min) diode, as shown in the typical application diagram, to help clamp the negative voltage at the out1/out2 pins. preferably, this clamp diode would be a schottky type. for most applications, the vins pin will share a common input node with the buck switcher vin1/2/3/4 pins, as shown in figure 17. in this configuration, the vins pin is protected from negative transients (such as during a field decay test) by two series diodes, the mosfet body diodes and the external, asyn- chronous schottky diodes, dsw1 through dsw4 . depending on the application, it may be necessary to isolate the vins pin from the switching noise on the vin1/2/3/4 pins. figure 15. typical dc current fold back versus v outx of s1 and s2 figure 16. s1/s2 outx turning on with a load of 40 and 22 f; shows v ens (ch1, 5 v/div.), v outx (ch2, 5 v/div.), i outx (ch3, 200 ma/div.), t = 500 s/div. t v ens v outx 100 ma 300 ma 400 ma i outx c1 c3 c2 0 5 10 15 20 0 50 100 150 200 250 300 350 400 output voltage (v) current limit (ma)
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 31 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com one method to accomplish this is to add an additional lc filter, as shown in figure 18. in this configuration the body diode and external schottky diode from the buck swtichers no longer protect the vins pin from negative voltage transients. if the vins pin is isolated in any way, allegro recommends adding a schottky diode, dvins, at the vins pin as shown in figure 18. there are two levels of thermal protection in the a8600. a detailed description of these two levels, how they affect the operation of s1 and s2, and how they must be reset is provided in the protections features section of this data sheet. see the timing diagrams section for operation of the high-side switches during current limit and high temperature. bu and acc detectors and mute output the a8600 includes two relatively simple comparators to monitor both v bat /v in and v bat /v in applied through a key-type ignition switch. the bu comparator monitors v bat /v in at the bui pin. the acc comparator monitors the ignition switch at the acci pin. both comparators have an internal reference of 1.205 v at their negative pins. therefore, a resistor divider must be used to set the bu and acc thresholds to something higher than 1.205 v, as shown in the typical application diagram. also, if hysteresis is necessary, this must be done with an external resistor from buo to bui and acco to acci, as shown in the typical application diagram. it should be noted that the acc comparator also controls the mode of sw1. if the en/sync and acci inputs are low, sw1 will enter low iq pfm mode after 2048 pwm cycles. if acci is high, it will immediately force sw1 into normal, high-current pwm mode. see the timing diagrams section for operation of the bu and acc detectors. the a8600 has an open drain, active low mute output with a programmable on-time. the mute output is an open drain out- put, therefore an external pull-up resistor must be used as shown in the typical application circuit diagram. the mute on-time is set by a counter and a capacitor from the ctmr pin to ground. basically, any time the bu comparator changes state the mute output is pulled low while the ctmr pin transitions 10 times between v ctmrh and v ctmrl . if the bu comparator changes state before the counter reaches 10, the counter will be reset to 0 and the mute time extended. the bu comparator has a de- glitch filter, so any fast transient on bui lasting less than 16 s (typ) will be ignored and a false mute will not occur. t tsdl and t tsdh do not affect the mute output. see timing diagrams section for operation of the mute and ctmr pins in conjunction with the bu detector. power ok (pok) output the a8600 has a power ok (pok) output. the pok output is an open drain output, so an external pull-up resistor must be used as shown in the typical application circuit diagram. the pok output is pulled low if either an under- or overvoltage condition occurs at fb2, fb3, or fb4. sw1 is an always-on regulator, so it does not help control pok. the typical pok thresholds are set at 60 mv (7.5% of 800 mv). figure 17. vins pin connected directly to vin1/2/3/4 pins figure 18. vins isolated from vin1/2/3/4, so the addition of d vins is required vins vin1 - vin4 vbat body diode schottky vins vin1 - vin4 vbat schottky body diode d_vins
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 32 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the pok comparators incorporate a small amount of hysteresis, 10 mv (typ), to help reduce chattering due to voltage ripple at any of the fbx pins. protection features the a8600 is designed to satisfy the most demanding automotive and non-automotive applications. in this section, a description of each protection feature is provided, and table 1 summarizes the protection features and their operation. undervoltage lockout (uvlo) for each of the three buck regulators, sw1/2/3, an undervolt- age lock out (uvlo) comparator monitors the voltage at the corresponding vinx pin and keeps the regulator disabled if the voltage is below the lockout threshold ( v uvloonx ). each uvlo comparator incorporates some hysteresis ( v uvlohysx ) to prevent on/off cycling of the regulator due to resistive or inductive drops in the v inx path during heavy loading or during startup. thermal shutdown (tsdl and tsdh) the a8600 has two levels of thermal protection: low (tsdl) and high (tsdh). tsdl typically occurs at approximately 155c and tsdh typically occurs at approximately 165c. if the junction temperature of the a8600 exceeds t tsdl , but remains below t tsdh , s1 and s2 are latched off, in order to reduce power and give priority to maintaining regulation of the buck outputs even though the regulator is getting hot. in this case, the tsdl latch may be reset by setting ens to logic low after the a8600 cools. however, if the junction temperature of the a8600 exceeds t tsdh , s1/2, and sw2/3/4 will all be latched off and sw1 will begin operating in low iq mode. for the extremely high temperature case, the tsdh latch may only be reset by set- ting en/sync to a logic low for at least 15 pwm counts or by cycling vin1. pulse-by-pulse overcurrent protection (ocp) the a8600 monitors the current in the upper mosfet and if the current exceeds the pulse-by-pulse over current threshold (i limx ) then the upper mosfet is turned off. normal pwm operation resumes on the next clock pulse from the internal oscillator. the a8600 includes leading edge blanking to prevent falsely trigger- ing the pulse-by-pulse current limit when the upper mosfet is turned on. pulse-by-pulse current limiting is always active. because of the addition of the slope compensation ramp to the inductor current, the a8600 delivers slightly less current at higher duty cycles than at lower duty cycles. if the synchronization input is used to reduce the switching frequency, the a8600 will, in effect, reduce the current limit with frequency too. figure 19 shows the minimum, typical and maximum pulse-by-pulse cur- rent limit at the typical pwm frequency, 425 khz. also, figure 19 shows the minimum expected pulse-by-pulse current limit if the synchronization input is used to reduce the switching fre- quency to 325 khz. the exact current each of the buck regulators can support is heavily dependent on duty cycle, ambient tempera- ture, thermal resistance of the pcb, airflow, component selection, and nearby heat sources. figure 19. pulse-by-pulse current limit versus duty cycle and pwm (sync) frequency 5.00 4.50 4.00 3.50 3.00 2.50 2,00 1.50 5.0 15.0 25.0 35.0 65.0 75.0 85.0 95.0 45.0 55.0 duty cycle (%) peak current limit (a) maximum at 425 khz minimum at 425 khz minimum at 325 khz typical at 425 khz
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 33 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com output short circuit (hiccup mode) protection hiccup mode protects the buck switchers when their load is either too high or when the output of the switcher is shorted to ground. hiccup mode operation is shown in figure 20. when the voltage at the ssx pin is below the hiccup ocp enable threshold (v hicenx , 2.3 v (typ)) hiccup mode protection is disabled. after the voltage at the ssx pin exceeds the hiccup ocp enable threshold, an ocp counter is enabled. the quantity of ocp pulses allowed then depends on the fbx voltage. if v fbx is below 300 mv, only 30 ocp counts are allowed. if the fbx voltage is above 300 mv, the quantity of ocp pulses allowed increases to 118. this dual count technique provides maximum thermal protection for the a8600 and allowing robust attempts for starting with highly capacitive or heavy loads. if the ocp counter reaches its limit, a latch is set and the compx pin is pulled low by a relatively low resistance (1 k ). the same latch enables a small current sink connected to the ssx pin (i sshicx ). the result is the voltage at the soft start pin will begin to ramp downward. when the voltage at the soft start pin decays to a much lower level, v ssrstx (200 mv (typ)) the hiccup latch will be cleared and the small current sink turned off. at this instant, the ssx pin will begin to source current (i sssux ) and the voltage at the ssx pin will ramp upward. this marks the begin- ning of a new, normal soft start cycle as described earlier. when the voltage at the soft start pin exceeds the pwm ramp offset (v pwmoffset , 400 mv (typ)) the error amplifier will force the voltage at the compx pin to slew up quickly and pwm switching will resume. if the short circuit at the switcher output remains, another hiccup cycle will occur. hiccups will repeat until the short circuit is removed or the switcher is disabled. if the short circuit is removed, the a8600 will soft start normally and the output voltage will automatically recover to the required level, as shown in figure 20. boot capacitor protection for each buck switcher, the a8600 monitors the voltage across the boot capacitor to detect if the capacitor is missing or short circuited. if the boot capacitor is missing, the regulator will enter hiccup mode after 7 pwm cycles. if the boot capacitor is short circuited, the regulator will enter hiccup mode after 30 pwm cycles. for a boot fault, hiccup mode operates similarly to the hiccup mode described for an output short circuit, with ssx ramping up and down as a timer to initiate repeated soft start attempts. a boot fault is a non-latched condition, so the a8600 will automatically recover when the fault is corrected. figure 20. hiccup mode and recovery to v swx = 3.3 v at i swx = 1.6 a; shows v swx (ch1, 2 v/div), v compx (ch2, 2 v/div), v ssx (ch3, 1 v/div), i sssux (ch4, 2 a/div); t = 2 ms/div t v swx v compx v ssx i swx 30 ocp counts ocp counter enabled short removed hiccup mode ocp latched soft start to normal operation 2.3 v 5 a 200 mv c1 c2 c3 c4
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 34 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com asynchronous diode protection in most high voltage asynchronous buck regulators, if the asyn- chronous diode is missing or damaged, the lx pin will transition to a very high negative voltage when the upper mosfet turns off, resulting in damage to the regulator. the a8600 includes protection circuitry to detect when the asynchronous diode is missing or damaged. if the lxx pin becomes more negative than 1.25 v (typ) for more than 50 ns (typ), the a8600 will protect itself to prevent damage. sw1 will enter hiccup mode after 1 missing diode fault. sw2/3/4 will latch off after 1 missing diode fault. after a latched missing diode fault, the latch must be reset by either setting en/sync to a logic low or cycling v inx . overvoltage protection (ovp) the a8600 provides a basic level of overvoltage protection by monitoring the voltage level at the fbx pin of all four buck switchers. two overvoltage conditions can be detected. first, if the fbx pin is disconnected from its feedback resistor divider, a tiny internal current source will force the voltage at the fbx pin to rise. when the voltage at the fbx pin exceeds the overvoltage threshold (v pokovx , 860 mv (typ)), pwm switching will stop. for sw1, the pok pin level is unaffected by overvoltage, but for sw2/3/4 the pok pin will be pulled low. second, if a higher external voltage supply is accidently shorted to a switcher output, v fbx will rise above the overvoltage thresh- old and be detected as an overvoltage condition. pwm switch- ing will stop and the pok pin pulled low (for sw2/3/4). if the condition causing the overvoltage is removed the regulators will automatically recover.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 35 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 1: summary of fault mode operation fault condition latched v ssx v compx v pok pwm switching s1, s2 reset sw1/2/3/4 output shorted to gnd no hiccup after 30 or 118 faults discharged, then respond to v ssx rise depends on v swx active, responds to vcompx not affected auto, remove short s1/2 output shorted to gnd no not affected not affected not affected not affected foldback limiting auto, remove short sw1/2/3/4 boot capacitor missing no hiccup, after 7 faults discharged, then respond to v ssx rise depends on v swx off during hiccup not affected auto, replace capacitor sw1/2/3/4 boot capacitor shorted no hiccup, after 30 faults discharged, then respond to v ssx rise depends on v swx off via uvlo boot not affected auto, unshort capacitor sw1 asynchronous diode missing no hiccup, after 1 fault discharged, then respond to v ssx rise n/a active, responds to vcompx not affected auto, install diode sw1/2/3/4 asynchronous diode missing yes discharged after 1 fault discharged depends on v swx forced off not affected en/sync low* or vreg por via vin1 uvlo sw1 asynchronous diode (or lx1) hard short no hiccup after 1 fault discharged, then respond to v ssx rise n/a active, responds to vcompx not affected auto, remove short sw1 asynchronous diode (or lx1) soft short no hiccup after 30 faults discharged, then respond to v ssx rise n/a active, responds to vcompx not affected auto, remove short sw1/2/3/4 asynchronous diode (or lxx) hard short yes pulled low after 1 fault discharged depends on v swx forced off not affected en/sync low* or vreg por via vin1 uvlo sw1/2/3/4 asynchronous diode (or lxx) soft short no hiccup after 30 faults discharged, then respond to v ssx rise depends on v swx active, responds to vcompx not affected auto, remove short sw1/2/3/4 fbx pin open (v fbx floats high) no ramps high for soft start low via loop response sw2/3/4 low via v fbx high (ov) off via v compx low not affected auto, connect fbx pin sw1/2/3/4 overvoltage (v fbx > 107.5%) no ramps high for soft start low via loop response pulled low forced off not affected auto, v fbx to normal range lg4 more than 8.1 v for >400 ns yes pulled low after 1 fault discharged depends on v sw4 latched off not affected en/sync low* or vreg por via vin1 uvlo lg4 in high state but < 1 v for >400 ns yes pulled low after 1 fault discharged depends on v sw4 latched off not affected en/sync low* or vreg por via vin1 uvlo lg4 in low state but > 1 v for >400 ns yes pulled low after 1 fault discharged depends on v sw4 latched off not affected en/sync low* or vreg por via vin1 uvlo thermal (tsdl) yes not affected not affected depends on v swx not affected off en/sync low* or ens low or vreg por via vin1 uvlo sw1 thermal (tsdh) yes after 2048 pwm cycles, latches in low iq mode off en/sync low* or vreg por via vin1 uvlo sw2/3/4 thermal (tsdh) yes pulled low pulled low depends on v swx latched off off en/sync low* or vreg por via vin1 uvlo 1 en/sync low requires a logic low for 15 clock cycles.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 36 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information design and component selection setting the output voltage (v swx , r fbax , r fbbx ) the output voltage of any switcher, sw1 through sw4, is deter- mined by connecting a resistor divider from the switcher output node (v swx ) to the switcher fbx pin as shown in figure 21. there are trade-offs when choosing the value of the feedback resis- tors. if the series combination (r fbax + r fbbx ) is relatively low, then the light load efficiency of the regulator will be reduced. so to maximize the efficiency, it is best to choose resistors with higher values. conversely, if the value of the parallel combination (r fbax //r fbbx ) is too high, then the switcher may be susceptible to noise coupling into the fbx pin. in general, the feedback resistors must satisfy the ratio shown in equation 1 to produce a required output voltage: = ? 1 0.8 (v) v swx r fbbx r fbax (1) table 2 shows the most common output voltages and recom- mended feedback resistors assuming less than 0.2% efficiency loss at light load of 100 ma and a parallel combination of 4 k presented to the fbx pin. for optimal system accuracy, it is rec- ommended that the feedback resistors have tolerances of 1% . sw1 presents some unique challenges when determining its feed- back resistor divider. this resistor divider must draw minimum current from v sw1 or it will raise the input current during low iq operation. with this in mind, allegro recommends the standard 1% resistor values shown in table 3. for low iq mode operation, a small feed-forward capacitor (cfb1) should be connected in parallel with rfba1, as shown in figure 22. the purpose of this capacitor is to offset any stray capacitance (c stray ) from fb1 to ground. without cfb1, the stray capacitance and the relatively high resistor values used for the sw1 feedback network form a low pass filter and introduce lag to the low iq pfm feedback path. the feed-forward capaci- rfba1 rfbb1 v sw1 fb1 pin c stray cfb1 figure 22. addition of cfb1 to cancel stray capacitance table 2. recommended feedback resistors for switchers sw2 through sw4 v sw2/3/4 (v) r fba2/3/4 (k ) r fbb2/3/4 (k ) 1.2 6.04 12.1 1.5 7.50 8.45 1.8 9.09 7.15 2.5 12.4 5.76 3.3 16.5 5.23 5.0 24.9 4.75 7.0 34.8 4.53 8.0 40.2 4.42 9.6 47.5 4.32 table 3. recommended feedback components for switcher sw1 v sw1 (v) r fba1 (k ) r fbb1 (k ) c fb1 (pf) 3.3 163 52.3 7.2 to 12 5.0 249 47.5 4.7 to 8 6.5 365 51.1 3.3 to 6 figure 21. connecting the feedback divider rfbax rfbbx v swx fbx pin
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 37 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com tor helps to maintain sensitivity during pfm mode and assure the output voltage ripple is minimized. in general, cfb1 should be calculated as: c fb1 > (1.5 c stray ) ( r fbb1 / r fba1 ) (2) where c stray is typically 15 to 25 pf. output inductor (lswx) for a peak current mode buck regulator, it is common knowl- edge that, without adequate slope compensation, the system will become unstable when the duty cycle exceeds approximately 50%. however, the slope compensation in the a8600 is a fixed value (s e(x) ) . therefore, it is important to calculate an inductor value such that the downward slope of the current (s fx ) approxi- mately matches the a8600 slope compensation. equations 3 and 4 can be used to calculate a range of values for the output inductor based on the well known approach of providing slope compensation that matches 50% to 100% of downward slope of the inductor current. in these equations, we assume the minimum value of slope compensation (s e(x) = 300 ma/ s). v fx is the forward voltage of the asynchronous diode: l swx v swx +v fx l swx 0.6 10 ?6 v swx +v fx 0.3 10 ?6 (3) (4) more recently, dr. raymond ridley presented a formula to calculate the amount of slope compensation required to critically damp the double poles at half the pwm switching frequency. this formula includes the duty cycle (d), which should be calcu- lated at the minimum input voltage to insure maximum stability: l swx 1 ? ( v inx (min) +v fx ) v swx +v fx v swx +v fx 0.45 10 ?6 0.18 (5) also, note that v inx (min) must be approximately 1 to 1.5 v above v swx when calculating the inductor value with equation 5. recall that sw4 is a synchronous regulator so v fx = 0 v should be used in equations 3 to 5. if equations 3 to 5 yield an inductor value that is not a standard value, then the next highest available value should be used. the final inductor value should allow for 5% to 10% of initial toler- ance and 10% to 20% of inductor saturation. the saturation current of the inductor should be higher than the peak current capability of the a8600. ideally, for output short circuit conditions, the inductor should not saturate given the high- est pulse-by-pulse current limit at minimum duty cycle (i limx ), 4.9 a (max). this may be too costly. at the very least, the induc- tor should not saturate given the peak operating current according to equation 6. in equation 6, v inx (max) is the maximum continu- ous input voltage, such as 18 v (not a surge voltage). = i limx 4.4 ? 0.45 10 ?6 ( v swx +v fx ) f swx (max) ( v inx (max) +v fx ) (6) starting with equation 6 and subtracting half of the inductor ripple current provides us with an interesting equation to predict the typical dc load capability for any of the buck regulators: = i swx(dc) 4.4 ? 0.45 10 ?6 d f swx 2 f swx l swx v swx 1 ? d (7) after an inductor is chosen, it should be tested during output short circuit conditions. the inductor current should be monitored using a current probe. a good design would ensure the induc- tor or the switcher are not damaged when the output is shorted to gnd at maximum input voltage and at the highest expected ambient temperature. output capacitors (cswx) the output capacitors filter the output voltage to provide an acceptable level of ripple voltage and they store energy to help maintain voltage regulation during a load transient. the voltage rating of the output capacitors must support the output voltage with sufficient design margin.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 38 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the output voltage ripple ( v swx ) is a function of the output capacitor parameters: esr swx , esl swx , and c swx : = ? v swx ? i lswx esr swx ? i lswx esl swx v inx ?v swx l swx 8 f swx c swx + + (8) the type of output capacitors will determine which terms of equation 8 are dominant. for ceramic output capacitors the esr and esl are virtually zero so the output voltage ripple will be dominated by the third term of equation 8: = ? v swx f swx c swx ? i lswx 8 (9) to reduce the voltage ripple of a design using ceramic output capacitors simply increase the total capacitance, reduce the induc- tor current ripple (that is, increase the inductor value), or increase the switching frequency. for electrolytic output capacitors the value of capacitance will be relatively high so the third term in equation 8 will be minimized and the output voltage ripple will be determined primarily by the first two terms of equation 8: = + ? v swx ? i lswx esr swx v inx l swx esl swx (10) to reduce the voltage ripple of a design using electrolytic output capacitors, simply decrease the equivalent esr and esl by using a high quality capacitor, and/or add more capacitors in parallel, or reduce the inductor current ripple (that is, increase the inductor value). the esr of some electrolytic capacitors can be quite high so allegro recommends choosing a high quality capacitor with a datasheet that that clearly documents the esr or the total imped- ance. also, the esr of electrolytic capacitors usually increases significantly at cold ambient, which increases the output voltage ripple and, in many cases, reduces the stability of the system. the transient response of the a8600 depends on the number and type of output capacitors. in general, minimizing the esr of the output capacitance will result in a better transient response. the esr can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. at the instant of a fast load transient (di/dt), the output voltage will change by the amount: =+ ? v swx ? i loadswx di dt esl swx esr swx (11) after the load transient occurs, the output voltage will deviate for a short time. the time will depend on the system bandwidth, the output inductor value, and output capacitance. after a short delay, the error amplifier will bring the output voltage back to its nominal value. the speed at which the error amplifier brings the output volt- age back to its setpoint will depend mainly on the closed-loop bandwidth of the system. a higher bandwidth usually results in a shorter time to return to the nominal voltage. however, with a higher bandwidth system it may be more difficult to obtain acceptable gain and phase margins. selection of the compensa- tion components (rz, cz, cp) are discussed in more detail in the compensation components section of this datasheet. sw1 low iq pfm ripple calculation after choosing an output inductor and output capacitor(s) for sw1, its important to calculate the output voltage ripple during low iq pfm mode. with ceramic output capacitors the output voltage ripple in pwm mode is usually negligible, but that is not the case during low iq pfm mode. first, we need to calculate the mosfet on and off times. the on-time is defined as the time it takes for the inductor current to reach 800 ma (typ): = t on 800 (ma) l sw1 v in1 ? v sw1 ? 800 (ma) ( r ds(on)hs1 + r dclsw1 ) (12) where r ds(on)hs1 is the on-resistance of the sw1 high-side mosfet (150 m (typ)) and r dclsw1 is the dc resistance of the output inductor, l sw1 . the on-time during pfm mode is internally limited to approximately 4 s. the off-time is defined as the time it takes for the inductor cur- rent to decay from 800 ma (typ) to 0 a: = t off 800 (ma) l sw1 v sw1 +v f1 (13)
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 39 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com lastly, the pfm output voltage ripple can be calculated: = ? v sw1(pfm) 800 (ma) ( t on + t off ) 2 c sw1 (14) if the pfm output voltage ripple appears to be too high, then the output capacitance of sw1 should be increased. the pfm output voltage ripple will increase as the input voltage decreases. notice that t on will increase as the output to input voltage ratio ( v sw1 / v in1 ) increases. if the v sw1 / v in1 ratio is too high, the system will not be able to achieve 800 ma within only 1 pfm pulse. in this case the on-time will be limited to approximately 4 s and a second pfm pulse will be required, about 300 ns later, as shown in figure 12 . input capacitors (cinx) three factors should be considered when choosing the input capacitors. first, they must be chosen to support the maximum expected input voltage, with adequate design margin. second, their rms current rating must be higher than the expected rms input current to the switcher. third, they must have enough capacitance, and a low enough esr, to limit the input voltage dv/dt to something much less than the hysteresis of the uvlo circuitry (nominally 400 mv for the a8600) at maximum loading and minimum input voltage. the input capacitors must deliver the rms current according to: = i rms i swx d (1 ? d ) (15) where the duty cycle is: d ( v swx + v fx ) / ( v in + v fx ) (16) and v fx is the forward voltage of the asynchronous diode, d swx . figure 23 shows the normalized input capacitor rms current versus duty cycle. to use this graph, simply find the operational duty cycle (d) on the x-axis and determine the input/output cur- rent multiplier on the y-axis. for example, at a 20% duty cycle, the input/output current multiplier is 0.400. therefore, if the regulator is delivering 2.0 a of steady-state load current, the input capacitor(s) must support 0.400 2.0 a or 0.8 a rms . the input capacitors must limit the voltage deviations at the vinx pin to something significantly less than the a8600 uvlo hysteresis during maximum load and minimum input voltage. equation 17 allows us to calculate the minimum input capaci- tance: c inx i swx ( ? v inx (min) f swx (min) d (1 ? d ) (17) where v inx (min) is chosen to be much less than the hysteresis of the v inx uvlo comparator ( v inx (min) 150 mv is recom- mended), and f sw(min) is the lowest expected pwm frequency. the d (1?d) term in equation 17 has an absolute maximum value of 0.25 at 50% duty cycle. so for example, a very conserva- tive design, based on i swx = 2 a, f sw (min) = 325 khz, d (1?d) = 0.25, and v inx = 150 mv: = c inx 2 (a) 10.2 f 325 (khz) 150 (mv) 0.25 a good design accommodates the dc-bias effect on a ceramic capacitor: as the applied voltage approaches the rated value, the capacitance value decreases. this effect is very pronounced with the y5v and z5u temperature characteristic devices (as much as 90% reduction) so these types should be avoided. the x5r and x7r type capacitors should be the primary choices due to their stability versus both dc bias and temperature. for all ceramic capacitors, the dc-bias effect is even more pro- nounced on smaller case sizes, so a good design uses the largest affordable case size (such as 1206 or 1210). also, its advisable to select input capacitors with plenty of design margin in the voltage rating, in order to accommodate the worst case transient input voltage (that is, load dump as high as 40 v for automotive applications). 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 102030 50607080 100 90 40 duty cycle (%) i rms / i swx figure 23. input capacitor ripple versus duty cycle
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 40 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com equation 17 should be used for each of the four buck switchers to calculate the required amount of ceramic input capacitance for each switcher. in the pcb layout, the input capacitor(s) for each buck switcher should be placed close to the switcher they support. asynchronous diode (dswx) there are three requirements for the asynchronous diodes. first, the asynchronous diode must be able to withstand the regu- lators input voltage when the high-side mosfet is on. there- fore, the design should have a diode with a reverse voltage rating (v rx ) higher than the maximum expected input voltage (that is, the surge voltage). second, the forward voltage of the diode (v fx ) should be mini- mized or the regulator efficiency will suffer. also, if v fx is too high the missing diode protection in the a8600 could be falsely activated. a schottky-type diode that can maintain a very low v f when the regulator output is shorted to ground at the coldest ambient temperature is highly recommended. third, the asynchronous diode must conduct the output current when the high-side mosfet is off. therefore, the average for- ward current rating of this diode (i favgx ) must be high enough to deliver the load current according to equation 17, such that: i favgx i swx (max) (1 ? d ) (18) where i swx (max) is the maximum continuous putput current of the regulator, and the minimum duty cycle is: d (min) = ( v swx + v fx ) / ( v inx (max) + v fx ) (19) even though sw4 is a synchronous controller, it requires an external schottky diode from lx4 to ground (dsw4), as shown in the typical application circuit diagram. this diode will conduct during the non-overlap time and must clamp the lx4 pin to a relatively low (negative) voltage. without this schottky diode the lx4 pin will become more and more negative. eventu- ally, the negative voltage will forward-bias the substrate parasitic base-emitter junction and/or the lx4 esd structure, which could lead to malfunction or even destruction of the a8600. bootstrap capacitor (cbootx) a bootstrap capacitor must be connected between the bootx and lxx pins to provide floating gate drive to the high-side mosfet. usually, sw1/2/3 require only 47 nf. however, for sw4 with its relatively large external mosfet, 100 nf is recom- mended. this capacitor should be a high-quality ceramic, such as an x5r or x7r, with a voltage rating of at least 16 v. for sw1/2/3, the a8600 incorporates a 10 low-side mosfet to insure that the bootstrap capacitor is always charged, even when the regulator is lightly loaded or prebiased. soft start and hiccup mode timing (cssx) the soft start time of the a8600 is determined by the value of the capacitance on the ssx pin (cssx). when the a8600 is enabled, the voltage at the ssx pin will start from 0 v and be charged by the soft start current, i sssux . how- ever, pwm switching will not begin instantly because the voltage at the ssx pin must rise above 400 mv. the soft start delay ( t dssx ) can be calculated using: = t dssx c ssx i sssux 400 (mv) (20) if the a8600 is starting into a very heavy load, a very fast soft start time may cause the switcher to exceed the pulse-by-pulse overcurrent threshold. this can occur because the total of the full load current, the inductor ripple current, and the additional cur- rent required to charge the output capacitors i co = c swx v swx / t ss (21) figure 24. output current (i co ) during startup output capacitor current, i co } i lim i load t ss
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 41 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com is higher than the pulse-by-pulse current threshold, as shown in figure 24. this phenomenon is more pronounced when using high value, electrolytic-type output capacitors. to avoid prematurely triggering hiccup mode, the soft start capacitor, cssx, should be calculated using the following for- mula: c ssx c swx v swx i ssssux 0.8 (v) i cox (22) where v swx is the output voltage, c swx is the output capacitance, i cox is the amount of current allowed to charge the output capaci- tance during soft start (allegro recommends an i cox between 0.1 and 0.3 a). higher values of i co result in faster soft start times. howewer, lower values of i co ensure that hiccup mode is not falsely trig- gered. allegro recommends starting the design with an i co of 0.1 a and increasing it only if the soft start time is too slow. if a non-standard capacitor value for cssx is calculated, the next larger value should be used. the output voltage ramp time, t ssrampx , can be calculated by using either of the following methods: = = t ssx t ssx c swx c ssx i sssux v swx 0.8 (v) or i cox (24) (25) when the a8600 is in hiccup mode, the cssx capacitor is used as a timing capacitor and sets the hiccup period. the ssx pin charges the cssx capacitor with i sssux during a startup attempt, and discharges the cssx capacitor with i sshicx between startup attempts. because the ratio of the ssx pin currents is 2:1, the time between hiccups will be at least twice as long as the startup time. therefore, the effective duty-cycle of the a8600 will be very low when the output is shorted to ground, and the junction tempera- ture will be kept low. sw4 external mosfet selections the external mosfets for sw4 must withstand the maximum expected input voltage. in an automotive environment this is usu- ally the 40 v load dump situation. the boot4 regulator shown in the typical application circuit diagram, internal gate drivers, and protection circuits were optimized for mosfets with less than12 nc of gate charge at v gs = 5 v. the upper and lower mosfets must support the sw4 peak output current according to the following equations: upper mosfet: i dhs4 i sw4 (peak) v in4 (min) v sw4 (26) lower mosfet: i dhs4 i sw4 (peak) 1 ? v in4 (max) v sw4 (27) examples of several 40 v mosfets with less than 12 nc of gate charge are shown in table 4. sw4 current sense resistor the current limit of sw4 at its minimum on-time (t on (min)) is determined by the value of the external sense resistor according to the following equation: = i sw4 (peak) at t on (min) r sense4 i lim4 = r sense4 75 (mv) (typ) (28) notice that this sets the current limit at t on (min) only. the actual current limit will depend on the duty cycle and switching frequency as shown in equations 5 and 6. therefore, the sense resistor should be chosen to support the required load current (plus some margin) at a relatively high duty cycle and minimum switching frequency. compensation components (rzx, czx, cpx) to compensate the system, it is important to understand where the buck power stage, load resistance, and output capacitance form their poles and zeros in frequency. also, its important to understand that the compensated error amplifier introduces a zero table 4: possible 40 v mosfets for sw4 part number manufacturer typical at v gs = 4.5 v (a) (m )nc fds8449 fairchild 6.8 26 8 si4446dy vishay 4.9 37 8 dmn4034sss diodes, inc. 5.5 39 5 ntms5838nl on semi 7 25 9
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 42 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com and two more poles, and where these should be placed to maxi- mize system stability, provide a high bandwidth, and optimize the transient response. first, we will take a look at the power stage of the a8600, the output capacitors, and the load resistance. this circuitry is com- monly referred as the control-to-output transfer function. the low frequency gain of this section depends on the compx to v swx node current gain (g mpowerx ), and the value of the load resistor (r loadx ). the dc gain (0 hz) of the control-to-output (cto) is: g cto(0hz)x = g mpowerx r loadx (29) the control-to-output transfer function has a pole (f p1 ), formed by the output capacitance (c swx ) and load resistance (r loadx ), at: = f p1x c swx r load 2 1 (30) the control-to-output transfer function also has a zero (f z1 ) formed by the output capacitance (c swx ) and its associated esr: = f z1x c swx esrx 2 1 (31) for a design with very low-esr type output capacitors (such as ceramic or oscon output capacitors), the esr zero (f z1 ) is usu- ally at a high frequency, so it can be ignored. on the other hand, if the esr zero falls below or near the 0 db crossover frequency of the system (such as for electrolytic output capacitors), then it should be cancelled by the pole formed by the cpx capacitor and the rzx resistor (discussed and identified later as f p3 ). a bode plot of the control-to-output transfer function for sw3 as shown in the typical application circuit diagram, with v sw3 = 3.3 v, i sw3 = 2 a, and r load3 = 1.65 ) is shown in figure 25. the pole at f p1 can be seen at 1.9 khz while the esr zero (f z1) occurs at a very high frequency, 636 khz (this is typical for a design using ceramic output capacitors). note, there is more than 90 of total phase shift because of the double-pole at half the switching frequency. next, we will take a look at the feedback resistor divider, (rfbax and rfbbx), the error amplifier (g m ), and its compensa- tion network rz-cz-cp. it greatly simplifies the transfer function derivation if r ox (error amplifier output impedance) >> r zx , and c zx >> c p x . in most cases, r ox > 2 m , 1 k < r zx < 50 k , 220 pf < c zx < 47 nf, and c px < 100 pf, so the following analy- sis should be very accurate. the low frequency gain of the control section (g c0hz ) is formed by the feedback resistor divider and the error amplifier. it can be calculated using: = g c0hz r fbbx r ox r fbax +r fbbx g mx = v fbx r ox v swx g mx = v fbx v swx a volx (32) where v swx is the output voltage, v fbx is the reference voltage (0.8 v), g mx is the error amplifier transconductance (750 a/v), and r ox is the error amplifier output impedance (a volx /g mx ). the transfer function of the type-ii compensated error amplifier has a (very) low frequency pole (f p2 ) dominated by the output error amplifier output impedance r ox and the czx compensation capacitor: = f p2x c zx r ox 2 1 (33) figure 25 . control-to-output bode plot for sw3 60 40 20 0 -20 -40 -60 180 90 0 -90 -180 10 1 10 6 10 5 10 4 10 3 10 2 frequency (hz) phase () gain (db) double pole at 212.5 khz f p1 = 1.9 khz gco 0hz = 13.6 db
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 43 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 3.32 3.30 3.28 3.26 3.24 3.22 3.20 440 480 520 560 640 680 720 760 800 600 recovery time (s) output voltage, v swx (v) 9 khz / 57 3.8 khz / 66 60 40 20 0 -20 -40 -60 180 90 0 -90 -180 10 1 10 6 10 5 10 4 10 3 10 2 frequency (hz) phase () gain (db) pm = 66 f c = 36 khz the transfer function of the type-ii compensated error amplifier also has frequency zero (f z2 ) dominated by the rzx resistor and the czx capacitor: = f p2x c zx r zx 2 1 (34) lastly, the transfer function of the type-ii compensated error amplifier has a higher frequency pole (f p3 ) dominated by the rzx resistor and the cpx capacitor: = f p3x c px r zx 2 1 (35) a bode plot of the error amplifier and its compensation network is shown in figure 26, in which f p2 , f p3 , and f z2 are indicated on the magnitude plot. notice that the zero (f z2 at 3.8 khz) has been placed so that it is in the vicinity of the pole at f p1 previously shown at 1.9 khz in the control-to-output bode plot, figure 25. placing f z2 just above f p1 will result in excellent phase margin, but relatively slow transient recovery time, as we will see later. finally, we take a look at the combined bode plot of both the control-to-output and the compensated error amplifier; see the red curve shown in figure 27. careful examination of this plot shows that the magnitude and phase of the entire system (red trace) are simply the sum of the error amplifier response (blue trace) and the control-to-output response (green trace). as shown in fig- ure 27, the bandwidth (f c ) of this system is 36 khz and the phase margin is 66 degrees. a generalized tuning procedure 1) choose the system bandwidth, f c , which is the frequency at which the magnitude of the gain will cross 0 db. recommended values for f c , based on the pwm switching frequency, are in the range: f sw / 20 < f c < f sw / 10. a higher value of f c will generally provide a better transient response, and a lower value of f c will make it easier to obtain higher gain and phase margins. figure 28. transient recovery comparison for f z2 at 3.8 khz / 66 and 9 khz / 57 figure 27. bode plot of the complete sw3 system (red curve) figure 26. compensated error amplifier bode plot (sw3) 60 40 20 0 -20 -40 -60 180 90 0 -90 -180 10 1 10 6 10 5 10 4 10 3 10 2 frequency (hz) phase () gain (db) g co 0hz = 45.6 db f p2 = 54 hz f p3 = 315 khz f z1 = 3.8 khz
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 44 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 2) calculate the rzx resistor value to set the required system bandwidth (f c ): = r zx f c g mpowerx g mx c swx v swx v fbx 2 (36) 3) determine the frequency of the pole (f p1 ) formed by c swx and r load by using equation 30 (repeated here): = f p1x c swx r load 2 1 4) calculate a range of values for the czx capacitor: << c zx f cx r zx 2 4 f p1x r zx 2 1.5 1 (34) to maximize system stability (that is, to have the most gain margin), use a higher value of cz x . to optimize transient recovery time, at the expense of some phase margin, use a lower value of cz x . figure 28 shows the output voltage recovery time due to a 1a load transient for the system shown in figure 27 (f z2 = 3.8 khz, 66 phase margin) and a system with f z2 at 1 / 4 the crossover frequency, or 9 khz. the system with f z2 at 9 khz has 57 of phase margin but recovers about twice as fast as the other system. 5) calculate the frequency of the esr zero (f z1 ) formed by the output capacitor(s) by using equation 31 (repeated here): = f z1x c swx esrx 2 1 5a) if f z1 is at least 1 decade higher than the target crossover frequency (f c ) then f z1 can be ignored. this is usually the case for a design using ceramic output capacitors. use equation 35 to calculate the value of cpx by setting f p3 to either 5 f c or f sw / 2, whichever is higher. 5b) conversely, if f z1 is near or below the target crossover fre- quency (f c ) then use equation 35 to calculate the value of cpx by setting f p3 equal to f z1 . this is usually the case for a design using high esr electrolytic output capacitors. power dissipation and thermal calculations the power dissipated in the a8600 is the sum of the power dissi- pated from the v in supply current (p in ), the power dissipated due to the switching of the internal power mosfets (p sw1/2/3 ), the power dissipated due to the rms current being conducted by the internal mosfet (p cond1/2/3 ), the power dissipated by the four internal gate drivers (p driver1/2/3/4 ), and the power dissipated due to the rms current being conducted by the two high-side switches (p s1/s2 ). the power dissipated from the v in supply current can be calcu- lated using the following equation: p intotal = v inx i q + ( v inx ? v gsx ) (3 q g + q g4 ) f sw (35) where v inx is the input voltage, i q is the input quiescent current drawn by the a8600 (nominally 7.5 ma), v gs is the mosfet gate drive voltage (typically 5 v), q g is the internal mosfet gate charge (approximately 2.5 nc), q g4 is the external mosfet gate charge for sw4, and f sw is the pwm switching frequency. the power dissipated by the internal high-side mosfet while it is switching can be calculated using the following equation: p sw1/2/3 v in1/2/3 i sw1/2/3x f sw ( t r + t f ) 2 (36) where v inx is the input voltage, i swx is the regulator output cur- rent, f swx is the pwm switching frequency, and t r and t f are the rise and fall times measured at the v lxx node. the exact rise and fall times at the v swx node will depend on the external compo- nents and pcb layout so each design should be measured at full load. approximate values for both t r and t f range from 5 to 10 ns. the power dissipated by the internal high-side mosfets while they are conducting can be calculated using the following equa- tion: = p cond1/2/3 i rms(fet)1/2/3 r ds(on)hs1/2/3 v sw1/2/3 + v f1/2/3 v in1/2/3 + v f1/2/3 + 12 2 ? i l1/2/3 2 i l sw1/2/3 2 = r ds(on)hs1/2/3 (37)
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 45 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com where i swx is the regulator output current, i lx is the peak-to- peak inductor ripple current, r ds(on)hsx is the on-resistance of the high-side mosfet, and v fx is the forward voltage of the asynchronous diode. the r ds(on) of the high-side mosfet will have some initial tolerance plus an increase from self-heating and elevated ambi- ent temperatures. a conservative design should accommodate an r ds(on) with at least a 15% initial tolerance plus 0.39%/c increase due to temperature. the sum of the power dissipated by the internal gate driver can be calculated using the following equation: p driver = (3 q g + q g4 ) v gs f sw (38) where v gs is the gate drive voltage (typically 5 v for all four buck switchers), q g is the gate charge to drive internal mosfet1/2/3 to v gs = 5 v (about 2.5 nc each), q g4 is the gate charge to drive the external mosfet to v gs = 5 v (this must come from the mosfet datasheet), and f sw is the pwm switch- ing frequency. the power dissipated by the high-side switches (s1, s2) can be calculated using th following equation: p s1/s2 = i 2 s1/s2 r ds(on)s1/s2 (39) where i x is the dc current through high-side switches s1 and s2, and r ds(on)sx is the on-resistance of the switch (typically 1 ), finally, the total power dissipated (p total ) is the sum of the pre- vious equations for all four switchers and the high-side switches: p total = p intotal + p sw1/2/3 + p driver + p s1/s2 (40) the average junction temperature can be calculated with the fol- lowing equation: t j = p total + r ja + t a (41) where p total is the total power dissipated as described in equation 40, r ja is the junction-to-ambient thermal resistance (23c/w on a 4-layer pcb), and t a is the ambient temperature. the maximum junction temperature will be dependent on how efficiently heat can be transferred from the pcb to ambient air. the thermal pad on the bottom of the ic should be connected to a at least one ground plane using multiple vias for optimum performance. a small amount of airflow can improve the thermal performance considerably. as with any regulator, there are limits to the amount of power that can be delivered and heat that can be dissipated before risking thermal shutdown. there are tradeoffs between ambient operating temperature, input voltage, output voltage, output cur- rent, switching frequency, pcb thermal resistance, airflow, and other nearby heat sources. even a small amount of airflow will will reduce junction temperature considerably. pcb component placement and routing a good pcb layout is critical if the a8600 is to provide clean, stable output voltages. follow these guidelines to insure good pcb layout. figure 28 shows a typical buck converter schematic with the critical power paths/loops. figure 29 shows an example pcb component placement and routing (for sw3) with the same critical power paths/loops from the schematic. 1) by far, the highest di/dt in the asynchronous buck regulator occurs at the instant the upper fet turns on and the capacitance of the asynchronous schottky diode (200 to 1000 pf) is quickly charged to v inx . the ceramic input capacitors must deliver this fast, short pulse of current. therefore, the loop from the ceramic input capacitors through the upper fet and into the asynchro- nous diode to ground should be minimized. ideally these compo- nents are all connected using only the top layer traces (that is, do not use vias to other power or signal layers). 2) when the upper fet is on, current flows from the input supply and capacitors, through the upper fet, into the load via the out- put inductor, and back to ground. this loop should be minimized and have relatively wide traces. 3) when the upper fet is off, free-wheeling current flows from ground, through the asynchronous diode, into the load via the
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 46 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com output inductor, and back to ground. this loop should be mini- mized and have relatively wide traces. 4) the voltage on the lxx nodes transition from 0 v to v inx very quickly and are the root cause of many noise issues. it is best to place the asynchronous diode and output inductor close to the a8600 to minimize the size of the lxx polygon. also, keep low- level analog signals (such as fbx and compx) away from the lxx polygon. 5) place the feedback resistor dividers (rfbax and rfbbx) very close to the fbx pin. ground this resistor divider as close as pos- sible to the a8600. 6) the two traces to the sw4 sense resistor should be run in parallel back to csp and csn. 7) to have the highest output voltage accuracy, the output voltage sense trace (from v swx to rfbax) should be connected as close as possible to the load. 8) place the compensation components (rzx, czx, and cpx) as close as possible to the compx pin. place vias to the gnd plane as close as possible to these components. 9) place the soft start capacitor (cssx) as close as possible to the ssx pin. place a via to the gnd plane as close as possible to this component. 10) place the boot strap capacitor (cbootx) near the bootx pin and keep the routing to this capacitor as short as possible. 11) when routing the input and output ceramic capacitors, use multiple vias to gnd and place the vias as close as possible to the pads of the component. 12) to minimize pcb losses and improve system efficiency, the input and output traces should be as wide as possible and be duplicated on multiple layers, if possible. 13) to improve thermal performance, place multiple vias to the gnd plane around the anode of the asynchronous diode. 14) the thermal pad under the a8600 must connect to the gnd plane using multiple vias. more vias will ensure the lowest junc- tion temperature and highest efficiency.
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 47 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com q3 vin gnd loop 2 loop 1 loop 3 load figure 29. example pcb component placement and routing, example shows sw3 figure 28. typical buck converter pcb layout, with critical paths and loops shown loop 1 (red): at the instant q3 turns on, the schottky diode d3 (which is very capacitive), must be very quickly charged and sh ut off. the spike of charging current must come from the input capacitors, cin1/2/3. this spike of current is quite large and will be an e mi/emc issue if loop 1 is not minimized. therefore, the input capacitors and schottky diode d3 must be placed be on the same (top) layer, be located near each other, and be grounded at virtually the same point on the pcb. loop 2 (brown): when q3 is off, free-wheeling inductor current must flow from ground through diode d3, into the output inductor , out to the load and return via ground. while q3 is off, the voltage on the output capacitors will decrease. the output capacitors and sch ottky diode d3 must be placed on the same (top) layer, be located near each other, and be grounded at virtually the same point on the pcb. loop 3 (blue): when q3 is on, current flows from the input supply and input capacitors through the output inductor and into the load. at this time the voltage on the output capacitors will increase. vin3 (cswx) (v sw3 ) co1 co5 d3 lsw3 lx3 vout3 q3 cin1 cin2 csnub3 rsnub3 cin3 ... ... loop 2 loop 3 loop 1 load
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 48 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 5. pin descriptions table name number description pin connection if pin function not used general en/sync 6 en/pfm control and pwm synchronization input ((always used)) bias 45 bias input, supplies internal circuitry when v sw1 is high enough ground vreg 4 internal voltage regulator bypass capacitor pin (always used) pok 23 power ok open drain output open gnd 3 ground (always used) pad ? exposed pad for enhanced thermal dissipation (always used, connect to ground) internal asynchronous always-on buck regulator (sw1) vin1 1 input supply for buck regulator sw1 (always used) lx1 48 switching node for buck regulator sw1 (always used) boot1 47 floating gate drive for buck regulator sw1 (always used) fb1 44 feedback pin for buck regulator sw1 (always used) comp1 43 error amplifier compensation network for regulator sw1 (always used) ss1 46 soft start programming for regulator sw1 (always used) internal asynchronous buck regulator (sw2) vin2 35 input supply for buck regulator sw2 ground vin2 36 input supply for buck regulator sw2 ground lx2 37 switching node for buck regulator sw2 ground lx2 38 switching node for buck regulator sw2 ground nc 34 unused, this pin should be left unconnected n/a boot2 39 floating gate drive for buck regulator sw2 ground fb2 41 feedback pin for buck regulator sw2 fb3 or fb4 comp2 42 error amplifier compensation network for regulator sw2 ground ss2 40 soft start programming for regulator sw2 ground internal asynchronous buck regulator (sw3) vin3 11 input supply for buck regulator sw3 v in supply (or ground 1 ) vin3 12 input supply for buck regulator sw3 v in supply (or ground 1 ) lx3 13 switching node for buck regulator sw3 boot3 (or ground 1 ) lx3 14 switching node for buck regulator sw3 boot3 (or ground 1 ) boot3 15 floating gate drive for buck regulator sw3 lx3 (or ground 1 ) fb3 17 feedback pin for buck regulator sw3 fb2 or fb4 comp3 18 error amplifier compensation network for regulator sw3 ground ss3 16 soft start programming for regulator sw3 ground continued on the next page?
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 49 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com external synchronous buck regulator (sw4) lx4 30 switching node for buck regulator sw4 boot4 (or ground 1 ) boot4 31 floating gate drive for buck regulator sw4 lx4 (or ground 1 ) hg4 29 high side gate drive for buck regulator sw4 open (or ground 1 ) lg4 32 low side gate drive for buck regulator sw4 open (or ground 1 ) pgnd 33 power ground (always used) csp 27 current sense pin for buck regulator sw4 ground csn 26 current sense pin for buck regulator sw4 ground fb4 25 feedback pin for buck regulator sw4 fb2 or fb3 comp4 24 error amplifier compensation network for regulator sw4 ground ss4 28 soft start programming for regulator sw4 ground bu, acc, and mute functions bui 10 input to the bu comparator ground buo 9 output of the bu comparator open acci 8 input to the acc comparator ground acco 7 output of the acc comparator open ctmr 5 delay programming for the mute pulse circuit ground mute 2 open-drain, active low output of the mute pulse circuit open high-side switches (s1, s2) vins 21 input to the high-side switches v in supply (or ground 2 ) ens 19 input to enable/disable both high-side switches ground out1 20 high-side switch s1 output out2 or open (or ground 2 ) out2 22 high-side switch s2 output out1 or open (or ground 2 ) 1 connect to ground instead, if also sw3 and sw4 both are not used. 2 connect to ground instead, if also s1 and s2 both are not used. table 5. pin descriptions table (continued) name number description pin connection if pin function not used
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 50 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin esd structures: (note: the hv clamp is shown where needed, but there is only 1 common hv clamp in the ic) low voltage pins; fb x , en/sync, vreg, bias, csp, csn, lg4, buo , acco , ctmr, acci high voltage pins with clamp: bui, ss x , ens high voltage pins; out1, out2, vins, mute, pok gnd to pgnd sw1, sw2, and sw3 power pins; vin1, vin2, vin3, lx1, lx2, lx3, boot1, boot2, boot3 sw4 output pins; boot4, hg4, lx4 pin lv gnd gnd circuit pin pgnd hv pgnd pin pgnd hv pgnd pgnd gnd hv pgnd pgnd lxx boot x vinx hv pgnd pgnd lx4 hg4 boot 4
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 51 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package jp, 48-pin lqfp package outline drawing 2 1 48 a exposed thermal pad (bottom surface) terminal #1 mark area b b a 7o 0o c seating plane c 0.08 48x gage plane seating plane 5.00 5.00 1.60 max 0.50 5.00 8.60 0.30 1.70 8.60 5.00 for reference only (reference jedec ms-026 bbchd) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown 1.40 0.05 0.10 0.05 0.22 0.05 9.00 0.20 9.00 0.20 7.00 0.20 7.00 0.20 0.50 pcb layout reference view c 0.25 (1.00) 0.60 0.15 4 4 0.15 +0.05 ?0.06 c reference land pattern layout (reference ipc7351 qfp50p900x900x160-48m); adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 48 2 1 c
quadruple output regulator with two high-side switches, bu/acc voltage detectors, and mute delay a8600 52 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com revision history revision revision date description of revision rev. 3 december 5, 2012 editorial changes copyright ?2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.

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