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? semiconductor components industries, llc, 2002 april, 2002 rev. 1 1 publication order number: ncp1651/d ncp1651 product preview single stage power factor controller the ncp1651 is an active, power factor correction controller that can operate over a wide range of input voltages, and output power levels. it is a fixed frequency control chip that can operate in continuous or discontinuous conduction modes. it is designed to operate on 50/60 hz power systems. this controller is ideal for driving a single stage, flyback converter. it provides a low cost solution for acdc converters operating below 200 watts and requiring power factor correction. the error amplifier and reference are located on the secondary side for excellent line and load regulation. the ncp1651 uses a proprietary multiplier design that allows for much more accurate operation than with conventional analog multipliers. features ? fixed frequency operation ? average current mode pwm ? internal high voltage startup circuit ? continuous or discontinuous mode operation ? high accuracy multiplier ? overtemperature shutdown ? external shutdown ? undervoltage lockout ? low cost/parts count solution ? ramp compensation does not affect oscillator accuracy typical applications ? high current battery chargers ? front ends for distributed power systems this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. device package shipping ordering information ncp1651d so16 48 units/rail ncp1651dr2 so16 2500 tape & reel 1 2 3 4 5 6 7 8 16 12 11 10 9 (top view ) i s+ out gnd c t ramp comp i avgfltr i avg fb/sd startup v ref ac comp ac input ac ref 13 v cc 15 14 nc nc so16 d suffix case 751b 1 tbd 16 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week marking diagram pin connections http://onsemi.com
ncp1651 http://onsemi.com 2 pin function description pin no. function description 1 output drive output for power fet or igbt. capable of driving small devices, or can be connected to an external driver for larger transistors. 2 ground ground reference for the circuit. 3 c t timing capacitor for the internal oscillator. this capacitor adjusts the oscillator frequency. 4 ramp compensation this pin biases the ramp compensation circuit, to adjust the amount of compensation that is added to the current signal for stability purposes. 5 i s+ positive current sense input. designed to connect to the positive side of the current shunt. 6 i avgfltr a capacitor connected to this pin filters the high frequency current signal to resemble the line frequency waveform. 7 i avg an external resistor with a low temperature coefficient is connected from this terminal to ground, to set and stabilize the gain of the current sense amplifier output that drives the ac error amplifier. 8 feedback/ shutdown the error signal from the error amplifier circuit is fed via an optocoupleer or other isolation circuit, to this pin. 9 ac input the rectified input ac haversine wave is connected to this pin. this information is used for the reference comparator and the average current compensation circuit. 10 ac reference a capacitor is connected to this pin to filter the modulated output of the reference multiplier. 11 ac compensation provides pole for the ac reference amplifier. this amplifier compares the sum of the ac input voltage and the low frequency component of the input current to the reference signal. the response must be slow enough to filter out most of the high frequency content of the current signal that is injected from the current sense amplifier, but fast enough to cause minimal distortion to the line frequency information. 12 vref 6.5 volt regulated reference output. 13 v cc provides power to the device. this pin is monitored for undervoltage and the unit will not operate if the v cc voltage is not within the uvlo range. initial power is supplied to this pin via the high voltage startup network. 14 no connection this pin is not available due to spacing considerations of the startup pin. 15 no connection this pin is not available due to spacing considerations of the startup pin. 16 startup this pin connects to the rectified input signal and provides current to the internal bias circuitry for the startup period of operation. note: pins 14 and 15 have not been used for clearance considerations due to the potential voltages present on pin 16. in order t o maintain proper spacing between the high voltage and low voltage pins, traces should not be placed on the circuit board between pins 16 and 13.
ncp1651 http://onsemi.com 3 maximum ratings (t a = 25 c unless otherwise noted.) rating symbol value unit power supply voltage (operating) v cc 18 v current sense amplifier input v(i s +) 1.0 v multiplier inputs (pin 5) vac 0.3 to 6.5 v thermal resistance, junctiontoair q ja thermal resistance, junctiontolead q jl maximum power dissipation @ t a = 25 c operating temperature range t j 40 to 125 c nonoperating temperature range t j 55 to 150 c lead temperature, soldering (tbd sec) t l c electrical characteristics (v cc = 14 volts, t j = 25 c for typical values. for min/max values t j is the applicable junction temperature.) characteristic symbol min typ max unit oscillator frequency (c t = 470 pf) t j = 40 c to 85 c f osc 95 90 100 100 105 110 khz frequency range 25 250 khz max duty cycle (c t = 470 pf) dmax 0.95 ramp peak (c t = 470 pf) v rpeak 4.0 v ramp valley (c t = 470 pf) v rvalley 0.100 v ramp compensation peak voltage (pin 13) 4.0 v ramp compensation current (pin 13) 150 a ac error amplifier (v comp = 2.0 v) input offset voltage v io 20 mv transconductance g m 60 100 150 umho output source i osource 30 a output sink i osink 30 a ac reference buffer transconductance g m 250 umho current amplifier input bias current (pin 5) 40 50 60 a input offset voltage (v comp = tbd) 3.0 8.0 mv differential input voltage range 0.75 v output gain (150 a/.150 v) (voltage loop outputs) 1000 umho output gain (150 a/.150 v) (ac e/a output) (r 10 = tbd w) 1000 umho bandwidth (note 1) khz pwm output voltage gain (k = v pwm + / ( v sense+ v sense ) ) (v pin 3 = v pin 13 = 0) av 15 v/v current limit voltage gain (k = vac e/a / ( v sense+ v sense ) ) (v pin5 = 0) av 15 v/v average current compensation amplifier voltage gain av .75 v/v 1. verified by design.
ncp1651 http://onsemi.com 4 electrical characteristics (continued) (v cc = 14 volts, t j = 25 c for typical values. for min/max values t j is the applicable junction temperature.) characteristic symbol min typ max unit reference multiplier dynamic input voltage range ac input (pinput) (note 2) compensation input (ainput) (note 2) offset voltage (ainput) v max 0.90 3.50 1.0 1.10 v v v multiplier gain t j = 40 c to 85 c k v mult out (v ac v ramp pk ) (v loopcomp v offset ) k 0.50 ac input (pin 5) input bias current (total bias current for both multipliers and line transient amplifier) i inbias a drive output source resistance (1.0 volt drop) r source 4.0 8.0 20 w sink resistance (1.0 volt drop) r sink 4.0 8.0 20 w rise time (c l = 1.0 nf) t r 50 ns fall time (c l = 1.0 nf) t f 50 ns output voltage in uvlo condition v o(uv) v voltage reference buffered output (i load = 0 ma, v cc = 12 vdc, temperature) vref out 6.24 6.50 6.76 v load regulation (buffered output, io = 0 to 10 ma, v cc > 10 v) dvref out 0 100 mv fb/sd pin opto current source (unit operational, v fb = 0.5 v) vref out 1.1 1.5 1.9 ma opto current source (shutdown, v fb = 0.1 v 16 20 a input voltage for 0 duty cycle 1.5 input voltage for 95% duty cycle dvref out 4.0 mv shutdown start up threshold (pin 8) (v out increasing) v sd 0.40 0.50 0.60 v shutdown hysteresis (pin 8) v h 0.075 v startup/uvlo uvlo startup threshold (v cc increasing) v su 9.5 10.8 12.1 v uvlo hysteresis (shutdown voltage = v su v h ) v h 0.8 1.0 1.2 v overtemperature trip point (note 2) t sd 140 160 180 c overtemperature hysteresis (note 2) 30 c high voltage startup (pin 16 = 50 v) startup current (into pin 16) i su 5.8 7.2 9.0 ma line pin leakage (pin 16, startup circuit inhibited) i leak 30 a total device operational bias current (c l(driver) = 1.0 nf, f osc = 100 khz) i bias 5.0 10 ma bias current in undervoltage mode i bshutdown 0.5 1.0 ma 2. verified by design.
ncp1651 http://onsemi.com 5 + reference regulator uvlo 8 counter r clk q over temperature sensor - + shutdown 4 v 6.5 v - - + 0.50 v 6.5 v vi converter 20 a reference multiplier vi ac reference buffer 4 v 0.75 v line + k ? i in = v ref 4.5 v 25 k ac error amp 16 k pwm q s r set dominant driver - + average current compensation 20 k 60 k leb ramp compensation oscillator current sense amplifier + ramp comp c t 43 i avg 76i avgfltr i s+ out 1 5 v ref 12 13 v cc startup 16 fb/sd 8 ac input 9 ac ref 10 gnd 2 ac comp 11 3.8 k a p figure 1. block diagram
ncp1651 http://onsemi.com 6 figure 2. switching timing diagram oscillator blanking pulse oscillator ramp gnd 4 v latch q drive pwm gnd 0.5 v ac error amp + ramp comp + inductor current fb/sd figure 3. dividebyeight counter timing diagram shutdown current limit startup shutdown fb/sd output current startup enable v cc 10.8 v 9.8 v off on max 0 0 0.5 v 1 23 7 8 7 7 7 8 7 8 7
ncp1651 http://onsemi.com 7 typical performance characteristics (test circuits are located in the document tnd308/d) 500 200 100 0 figure 4. current sense amplifier gain i s+ (mv) 5 0 v out (v) 300 400 1 2 3 4 pin 7 pin 6 figure 5. fb/sd vi characteristics 1600 400 200 0 i sink ( a) 12 0 v pin 8 (v) 600 800 2 4 8 10 6 1000 1200 1400 40 c 0 c 12 4 2 0 figure 6. bias current in shutdown mode v cc (v) 0.9 0 current (ma) 68 0.1 0.2 0.3 0.7 125 c figure 7. bias current in operating mode 18 12 10 v cc (v) 7 5 current (ma) 14 6 16 0.4 0.5 0.6 0.8 10 25 c 80 c 0, 40 c 125 c 25 c 80 c 40 c 0 c 1000 10 1 figure 8. startup current versus high voltage startup pin voltage (v) 9 0 startup current, pin 16 (ma) 100 1 2 3 7 125 c figure 9. startup leakage versus temperature 125 25 50 temperature ( c) 100 60 leakage current, pin 16 ( a) 25 80 50 4 5 6 8 25 c 80 c 0 70 90 75 100
ncp1651 http://onsemi.com 8 typical performance characteristics (test circuits are located in the document tnd308/d) 25 25 50 figure 10. uvlo versus temperature temperature ( c) 11.2 10 threshold (v) 75 100 10.2 10.4 10.6 11.0 turnon figure 11. fb/sd clamp voltage versus v cc 4 2 0 v cc (v) 1.5 0 clamp voltage, pin 8 (v) 6 0.5 1.0 81012 0 50 125 10.8 turnoff 5 2 1 0 figure 12. reference multiplier gain ac input (v) 5 0 ac ref (v) 3 0.5 1 1.5 3.5 1.6 v figure 13. v cc cap charge time 10,000 10 1 charge time (ms) 1000 1 v cc , capacitance ( f) 100 10 1000 2 2.5 3 4 4 4.5 2.0 v 1.8 v 2.5 v fb/sd = 3.0 v 100 1000 10 1 figure 14. c t versus frequency frequency (khz) 100 k 100 c t (pf) 100 figure 15. ramp peak versus frequency 300 50 0 frequency (khz) 4.40 3.95 ramp peak 150 4.15 1000 10 k 100 4.10 200 250 4.00 4.05 4.30 4.25 4.20 4.35 note: ramp valley voltage is zero for all frequencies
ncp1651 http://onsemi.com 9 typical performance characteristics (test circuits are located in the document tnd308/d) 100 50 0 figure 16. maximum duty cycle versus frequency frequency (khz) 99 96 95 93 maximum duty cycle 150 200 250 300 94 98 97 150 100 50 0 figure 17. capacitance versus 10% to 90% drive rise and fall times 10% to 90% drive rise and fall times 10,000 1000 100 capacitance 200 250 300 350 rise time fall time figure 18. transient response for 6.5 volt reference 2.0 s/div 0 ma 10 ma 50 mv/div v ref v ref load 125 100 50 50 figure 19. frequency versus temperature temperature ( c) 97 96 frequency 98 101 102 0 99 100 75 25 25
ncp1651 http://onsemi.com 10 typical performance characteristics (test circuits are located in the document tnd308/d) 125 75 100 50 25 50 figure 20. peak ramp voltage versus temperature temperature ( c) 4.06 4.04 peak ramp voltage (v) 4.08 4.12 25 0 10 6 4 0 figure 21. v ref load regulation v ref load (ma) 6.44 v ref (v) 28 6.46 4.10 note: valley voltage is zero 6.48 6.50 6.52 125 c 25 c 40 c 18 14 12 10 figure 22. v ref line regulation load current (ma) 6.44 v ref (v) 6.48 6.52 16 6.46 6.50 125 100 75 50 50 figure 23. v ref in shutdown condition temperature ( c) 0.4 0 v ref (v) 0.6 0.8 1 0.2 25 125 c 25 c 40 c 025 no load 10 k 3.3 k
ncp1651 http://onsemi.com 11 figure 24. external shutdown circuit 6.5 v 3.8 k vi converter fb/sd 9 shut down reference multiplier ac input a 470 5 (allows external converters to be synchronized to the switching frequency of this unit.) r 11 0.33 f ncp1651 11 33 k ac comp v ref 12 c 11 bas16lt1 mmbt2907al figure 25. soft start circuit
ncp1651 http://onsemi.com 12 theory of operation introduction optimizing the power factor of units operating off of ac lines is becoming more and more important. there are a number of reasons for this. there are a growing number of government regulations requiring pfc (power factor correction). many of these are originating in europe. regulations such as iec100032 are forcing equipment to utilize input stages with topologies other than a simple offline front end which contains a bridge rectifier and capacitor. there are also system requirements that dictate the use of pfc. in order to obtain the maximum power from an existing circuit in a building, the power factor is very critical. the real power available from such a circuit is: p real v rms i rms pf a typical offline converter will have a power factor of 0.5 to 0.6, which means that for a given circuit breaker rating only 50% to 60% of the maximum power is available. if the power factor is increased to unity, the maximum available power can be obtained. there is a similar situation in aircraft systems, where a limited supply of power is available from the onboard generators. increasing the power factor will increase the load on the aircraft without the need for a larger generator. figure 26. voltage and current waveforms v, i v, i offline converter pfc converter t t v v i i unity power factor is defined as the current waveform being in phase with the voltage, and undistorted. therefore, there are two causes of power factor degradation phase shift and distortion. phase shift is normally caused by reactive loads such as motors which are inductive, or electroluminescent lighting which is highly capacitive. in such a case the power factor is relatively simple to analyze, and is determined by the phase shift. pf cos where is the phase angle between the voltage and the current. reduced power factor due to distortion is more complicated to analyze and is normally measured with ac analyzers, although most circuit simulation programs can also calculate power factor. one of the major causes of distortion is rectification of the line into a capacitive filter. this causes current spikes that do not follow the input voltage waveform. an example of this type of waveform is shown in the upper diagram in figure 26. a power converter with pfc forces the current to follow the input waveform. this reduces the peak current, the rms current and eliminates any phase shift. the ncp1650 accomplishes this for both continuous and discontinuous mode power converters. pfc operation the basic pwm function of the ncp1651 is controlled by a small block of circuitry, which comprises the dc regulation loop and the pfc circuit. these components are shown in figure 27. there are three inputs to this loop. they are the rectified input ac haversine, the instantaneous input current and the error signal at the fb/sd pin. the input current is forced to maintain a near unity power factor due to the control of the ac error amplifier. this amplifier uses information from the ac input voltage and the ac input current to control the power switch in a manner that gives good dc regulation as well as excellent power factor. the reference multiplier sets a reference level for the input haversine waveform. one of its inputs is connected to a scaled down haversine, and the other receives the error signal which has been converted to a current. the error signal adjusts the level of the haversine on the multiplier's output without distorting it. to accomplish this, it is necessary for the bandwidth of the dc error amp to be less than twice the lowest line frequency. typically it is set at a factor of ten less than the rectified frequency (e.g. for a 60 hz input, the bandwidth would be 12 hz).
ncp1651 http://onsemi.com 13 figure 27. simplified block diagram of basic pfc control circuit + - - + 6.5 v vi converter 20 a reference multiplier ac reference buffer v ref ac error amp pwm driver - + average current compensation current sense amplifier + i s+ drive 1 5 ac input 9 3.8 k .75 pwm logic fb/sd 8 470 v line .75 v line + k ? i in = v ref vi ref filter 10 4 v r dc1 r dc2 d 5 c out +bus 2 v error(ac) v error(ac)
ncp1651 http://onsemi.com 14 the key to understanding how the input current is shaped into a high quality sine wave is the operation of the ac error amplifier. the inputs of an operational amplifier operating in its linear range, must be equal. there are several secondary effects, that create small differences between the inverting and noninverting inputs, but for the purpose of this analysis they can be considered to be equal. the haversine output of the reference multiplier is fed into the noninverting input of the ac error amplifier. the inverting input to the ac error amplifier receives a signal that is comprised of the input haversine (which is not modified by the reference multiplier), and summed with the filtered input current. since the two inputs to this amplifier will be at the same potential, the complex signal at the noninverting input will have the same waveshape as the ac reference signal. the ac reference signal (v ref ) is a haversine, and the ac input signal (v line ) is also a haversine, therefore, the ac current signal (i in ), must also be a haversine. this relationship gives the formula: .75 v ref v line (k i in ) the iin signal has a wide bandwidth, and its instantaneous value will not follow the low frequency haversine exactly, however, the output of the ac error amplifier has a low frequency pole that allows the average value of the .75 v line + (k x i in ) to follow v ref . since the ac error amplifier is a transconductance amplifier, it is followed by an inverting unity gain buffer stage with a low impedance output so that the signal can be summed with the instantaneous input switching current (i in ). the output of the buffer is still v error(ac) . figure 28. typical signals for pfc circuit ac input v ref v line k ? i in v line + k ? i in v error(ac) v error(ac) v error(ac) v ref osc 5 v ref gnd gnd 5 v ref the difference between v error(ac) and the 4.0 volt reference, sets the window that the instantaneous current will modulate in, to determine when to turn the power switch off. the switch is turned on by the oscillator, which makes this a fixed frequency controller. under normal operation, the switch will remain on until the instantaneous value of v error(ac) reaches the 4.0 volt reference level, at which time the switch will turn off. since the input current has a fundamental frequency that is twice that of the line, the output filter must have poles lower than the input current to create a reasonable dc waveform. the dc output voltage is compared to a reference voltage by a secondary side error amplifier, and the error signal out of the secondary side amplifier is fed back into the feedback input through an optocoupler.
ncp1651 http://onsemi.com 15 operating description dc reference and buffer the internal dc reference is a precision bandgap design with a nominal output voltage of 4.0 volts. it is temperature compensated, and trimmed for a 1% tolerance of its nominal voltage, with an overall tolerance of 2%. to assure maximum stability, this is only used as a reference so there is minimal loading on this source. the dc reference is fed into a buffer with a gain of 1.625 which creates a 6.5 volt supply. this is used as an internal voltage to power many of the blocks inside of the ncp1651 and is also available for external use. the 6.5 volt reference is designed to be terminated with at 0.1 f capacitor for stability reasons. there is no buffer between the internal and external 6.5 volt supply, so care should be used when connecting external loads. a short or overload on this voltage output will inhibit the operation of the chip. undervoltage lockout an undervoltage lockout circuit (uvlo) is provided to assure that the unit does not exhibit undesirable behavior at low v cc levels. it also reduces power consumption to a level that allows rapid charging of the v cc cap. when the v cc cap is originally charging, the uvlo will hold the unit off, and in a low bias current mode until the v cc voltage reaches a nominal 12 volt level. at this point the unit will begin operation, and the uvlo will no longer be active. if the v cc voltage falls to a level that is 0.5 volts below the turnon point, the uvlo circuit will again become active. when in the active (shutdown) state, the uvlo circuit removes power from all internal circuitry by shutting off the 6.5 volt supply. the 4.0 volt reference remains active, and the uvlo and shutdown comparators are also active. multiplier the ncp1651 uses a new proprietary concept for its reference multiplier. this innovative design allows greatly improved accuracy compared to a conventional linear analog multiplier. the multiplier uses a pwm switching circuit to create a scalable output signal, with a very well defined gain. one input (a) to the multiplier is a voltagetocurrent (vi) converter. by converting the input voltage into a current, an overall multiplier gain can be accomplished. in addition, there will be no error in the output signal due to the series rectifier. the other signal (input p) is input into the pwm comparator. this selects a pulse width for the comparator output. the current signal from the vi converter is factored by the duty cycle of the pwm comparator, and then filtered by the rc network on the output. this network creates a low pass filter, and removes the high frequency content from the original waveform. figure 29. simplified multiplier schematic input a input p ramp output inverting input ni input v to i converter - + the multiplier ramp is generated by the internal oscillator, and is the same signal as is used in the pwm. it will therefore have the same frequency as the power stage. it is not necessary for input p (into the pwm comparator) to be a dc signal, low frequency ac signals (relative to the ramp frequency) work well also. the gain of the multiplier is determined by the currenttovoltage ratio of the vi converter, the load resistor of the output filter and the peak and valley points of the sawtooth ramp. when the p input signal is at the peak of the ramp waveform, the comparator will allow the a input signal to pass without chopping it at all. this gives an output voltage of the a current multiplied by the output filter resistance. when the p input signal is at the ramp valley voltage, the comparator is held low and no current is passed into the output filter. in between these two extremes, the duty cycle (and therefore, the output signal) is proportional to the level of the p input signal. the output filter is a parallel rc network. the pole for this network needs to be greater than twice the highest line frequency (120 hz for a 60 hz line), and less than the switching frequency. a recommended starting point is a factor of 20 to 50 less than the rectified line frequency. the pole is calculated by the formula: f o 1 2 r c so, for a 60 hz line, and a 100 khz switching frequency, a 2.0 khz pole is a good starting point. this would be a factor of 50 below the switching frequency, and is still far enough above the 120 hz rectified line frequency that it won't cause undesirable distortion. the reference multiplier contains an internal loading resistor, with a nominal value of 25 k s. this is because the resistor that converts the a input voltage into a current is
ncp1651 http://onsemi.com 16 internal. making both of these resistors internal, allows for good accuracy and good temperature performance. only a capacitor needs to added externally to properly compensate this multiplier. it is not recommended that an external parallel resistor be used at the aref gaino pin, due to tolerance variations of the internal resistor. there is an offset in the compensation (ainput) to the reference multiplier. it is due to the vi converter that feeds the input. this circuit is the same for the power loop as well as the voltage loop. there is an offset due to nonlinearities in the output of the error amp. the equivalent voltage into the xinput is therefore, v comp v offset , while the voltage into the pinput is simply vac. the fb/sd signal is buffered by a voltagetocurrent converter for the appropriate signal into the multiplier. the schematic for that converter follows. figure 30. multiplier vi converter 1.5 v current mirror - + 20 k 3.8 k 8 fb/sd reference multiplier v fb 6 x i 1 i 1 i mult the output current for this stage is: i mult 6v fb 1.5 v 20 k feedback/shutdown the fb/sd pin is a multiple function pin. its primary function is to port the error signal to the voltagetocurrent converter that feeds the reference multiplier. the operating range for the feedback signal is from 1.0 to 4.0 volts. at an input level of 1.0 volt, the pwm duty cycle is reduced to zero. at 4.0 volts the pwm is operating at its maximum duty cycle. the signal at this pin is also sensed by an internal comparator that will shutdown the unit if the voltage falls below 0.50 volts. under normal operating conditions the signal at this input will be 1.0 volt or greater, and the shutdown circuit will be inactive. the shutdown function can be used for multiple purposes including overvoltage, undervoltage or hotswap control. an external transistor, open collector or open drain gate, connected to this pin can be used to pull it low, which will inhibit the operation of the chip, and change the operating state to a low power standby mode. an example of a shutdown circuit is shown in figure 24. ramp compensation the ramp compensation pin allows the amount of ramp compensation to be adjusted for optimum performance. ramp compensation is necessary in a current mode converter to stabilize the units operation when the duty cycle is greater than 50%. the amount of compensation required is dependant on several variables, including the boost inductor value, and the desires of the designer. the value should be based on the falling di/dt of the inductor current. for a boost inductor with a variable input voltage, this will vary over the ac input cycle, and with changes in the input line. a di/dt chart is included in the design spreadsheet that is available for the ncp1651. for optimum load transient performance, the ramp compensation should equal the falling di/dt at 100% duty cycle. for optimum line transient response, it should equal one half of the falling di/dt at 100% duty cycle. this unit already incorporates a line transient circuit, so it would be prudent to adjust the ramp compensation for load transients. this pin is a buffered output of the oscillator, which provides a voltage equal to the ramp on the oscillator c t pin. a resistor from this pin to ground, programs a current that is transformed via a current mirror to the noninverting input of the pwm comparator. the ramp voltage due to the inductor di/dt at the input to the pwm comparator is the current shunt voltage at pin 5 multiplied by 15, which is the gain of the current amplifier output that feeds the pwm. figure 31. ramp compensation circuit - + oscillator - + 16 k ac ref buffer current sense amp pwm comparator 4 ramp compensation r rc 1.6 i i the current mirror is designed with a 1:3 current ratio. the ramp signal injected can be calculated by the following formula: v ramp 1.6 vosc pk 16 k r rc 102 r rc where: v ramp = peak injected current signal (v) r rc = ramp compensation resistor (k )
ncp1651 http://onsemi.com 17 oscillator the oscillator generates the sawtooth ramp signal that sets the switching frequency, as well as sets the gain for the multipliers. both the frequency and the peaktopeak amplitude are important parameters. the oscillator uses a current source for charging the capacitor on the c t pin. the charge rate is approximately 200 a and is trimmed to maintain an accurate, repeatable frequency. discharge is accomplished by grounding the c t pin with a saturated transistor. a hysteretic comparator monitors that ramp signal and is used to switch between the current source and discharge transistor. while the cap is charging, the comparator has a reference voltage of 4.0 volts. when the ramp reaches that voltage, the comparator switches from the charging circuit to the discharge circuit, and its reference changes from 4.0 to 0.5 volts (overshoot and delays will allow the valley voltage to reach 0 volts). the relationship between the frequency and timing capacitor is: c t 47, 000 f where c t is in pf and f is in khz. it is important not to load the capacitor on this pin, since this could affect the accuracy of the frequency as well as that of the multipliers which use the ramp signal. any use of this signal should incorporate a high impedence buffer. due to the required accuracy of the peak and valley ramp voltages, the ncp1651 is not designed to be synchronized to the frequency of another oscillator. average current compensation the peak current compensation circuit adjusts the maximum current that can occur before the controller limits the current. this allows for higher levels of current under low line conditions than at high line. the input signal to this amplifier is the input haversine. the amplifier is a unity gain amplifier, with a voltage divider on the output that attenuates the signal by a factor of 0.75. this scaled down haversine is summed with the low frequency current signal out of the current sense amplifier. the sum of these signals must equal the signal at the noninverting input to the ac error amplifier, which is the output of the reference multiplier. since there is a hard limit of 4.5 volts at the noninverting input, the sum of the line voltage plus the current cannot exceed this level. a typical universal input design operates from 85 to 265 vac, which is a range of 3.1:1. the output of the current compensation amplifier will change by this amount to allow the maximum current to vary inversely to the line voltage. driver the output driver can be used to directly drive a fet, for low and medium power applications, or a larger driver for high power applications. it is a complementary mos, totem pole design, and is capable of sourcing and sinking over 1.5 amps, with typical rise and fall times of 50 ns with a 1.0 nf load. the totem pole output has been optimized to minimize cross conduction current during high speed operation. additional internal circuitry has been added to keep the driver in its low state whenever the undervoltage lockout is active. this characteristic eliminates the need for an external gate pulldown resistor. ac error amplifier the ac error amplifier is a transconductance amplifier. this amplifier forces a signal which is the sum of the current and input voltage to equal the ac reference signal from the reference multiplier. transconductance amplifiers differ from voltage amplifiers in that the output is a high impedance with a controlled voltagetocurrent gain. this amplifier has a nominal gain of 100 umhos (or 0.0001 amps/volt). this means that an input voltage differential of 10 mv would cause the output current to change by 1.0 a. its maximum output current is 30 a. current sense amplifier the current sense amplifier is a wide bandwidth amplifier with a differential input. it consists of a differential input stage, a high frequency current mirror (pwm output) and a low frequency current mirror (ac error amp output). figure 32. current sense amplifier current mirror - + i avg ac error amp i 2 i 2 i avg fltr current mirror i 1 i 1 i 1 pwm 3 k 30 k 3 k 67 i s+ 5 leb the input to the current sense amplifier is a common base configuration. the voltage developed across the current shunt is sensed at the is+ input. the amplifier input is designed for positive going voltages only; the power stage should resemble the configuration of the application circuit in figure 32. caution should be exercised when designing a filter between the shunt resistor and this input, due to the low impedance of this amplifier. any series resistance due to a filter, will create an offset of: v os 50 a r external which will add a positive offset to the current signal. the effect of this is that the ac error amplifier will try to compensate for
ncp1651 http://onsemi.com 18 the average output current which appears never to go to zero, and cause additional zero crossing distortion. the voltage across the current shunt resistor is converted into a current ( i 1 ), which drives a current mirror. the output of the i 1 current mirror is a high frequency signal that is a replica of the instantaneous current in the inductor. the conversion of the current sense signal to current i 1 is: i 1 vi s 3k the pwm output sends that information directly to the pwm input where it is added to the ac error amp signal and the ramp compensation signal. the other output of the i 1 mirror provides a voltage signal to a buffer amplifier. this signal is the result of i 1 dropped across an internal 15 kw resistor, and filtered by a capacitor at pin 6. this signal, when properly filtered, will be the 2x line frequency haversine. the filter pole on pin 6 should be far enough below the switching frequency to remove most of the high frequency component, but high enough above the line frequency so as not to cause significant distortion to the input haversine waveform. for a 100 khz switching frequency and a 60 hz line frequency, a 10 khz pole will normally work well. the capacitor at pin 6 can be calculated knowing the desired pole frequency by the equation: c 6 5.3 f where: c 6 = pin 6 capacitance (nf) f = pole frequency (khz) or, for a 10 khz pole, c 6 would be 0.5 nf. the gain of the low frequency current buffer is set by the value of the resistor at pin 7. the value of r7 determines the scale factor between the peak current and the average current. the average current will be that of the primary waveform only, since the secondary current will not conduct across the shunt resistor. pwm logic the pwm and logic circuits are comprised of a pwm comparator, an rs flipflop (latch) and an or gate. the latch is set dominant which means that if both r and s are high the s signal will dominate and q will be high, which will hold the power switch off. the ncp1651 uses a voltage mode pulse width modulation scheme based on a fixed frequency oscillator. the oscillator outputs a ramp waveform as well as a pulse which is coincident with the falling edge of the ramp. the pulse is fed into the pwm latch and or gate that follows. during the pulse, the latch is reset, and the output drive is in its low state. on the falling edge of the pulse, the output drive goes high and the power switch begins conduction. the instantaneous inductor current is summed with the ac error amplifier voltage and the ramp compensation signal to create a complex waveform that is compared to the 4.0 volt reference signal on the inverting input to the pwm comparator. when the signal at the noninverting input to the pwm comparator exceeds 4.0 volts, the output of the pwm comparator changes to a high state which drives one of the set inputs to the latch and turns the power switch off until the next oscillator cycle. the or gate that follows the pwm is used to inhibit the drive signal to the power switch. in addition to the oscillator pulse, this gate receives a signal from the shutdown or gate, which can inhibit operation due to an overtemperature condition, shutdown signal, or insufficient v cc . shutdown modes and logic overtemperature a temperature sensor and reference is provided to monitor the junction temperature of the chip. the chip will operate to a nominal temperature of 160 c at which time the output of the temperature sensor will change to a low state. this will set the output of the shutdown nand gate high, which in turn will set the output of the pwm or gate high, and force the driver into a low state. there is a hysteresis of 30 c on this circuit, which will allow the chip to cool down to 130 c before resuming operation. while in the overtemperature shutdown mode, the startup circuit will be operational and the v cc will cycle between 10.8 and 9.8 volts. insufficient v cc if the level of the v cc voltage is not sufficient to maintain operation, the drive of the chip will be inhibited and the dividebyeight timer will be invoked. this will normally occur when the output is overloaded. under this condition, the dividebyeight counter will count for 8 v cc cycles. at the end of the eighth cycle the driver will be enabled and the circuit will attempt to start. if the failure has been corrected, the output will come up and the circuit will resume normal operation. if not, another cycle will begin. the waveforms for overload timeout are shown in figure 3. shutdown the ncp1651 has a shutdown circuit that can be used to inhibit the operation of the chip by reducing the fb/sd pin voltage to less than 0.5 volts. when a shutdown signal is issued, the output of the shutdown comparator goes low. this immediately ceases the operation of the unit by or'ing that signal to the output of the pwm logic, and holding the driver in its low state. the inverted output of the shutdown comparator is fed in to the reset pin of the dividebyeight counter. the counter reset pin sets its count to seven. as long as the reset pin is low, the counter will remain at seven. when the shutdown signal is removed, the reset pin will go high, and the counter will continue to count to eight. the counter is triggered on the negative edge of the startup enable signal. this means that a shutdown signal that is removed on the upward v cc slope will be in the 7 count for the remaining rise and fall of that v cc cycle and will change to 8 on the next cycle. this system assures that the unit will not be enabled until the v cc voltage has a full discharge cycle available, and it also insures that the unit will commence operation in less
ncp1651 http://onsemi.com 19 than two v cc cycles. a timing diagram of this mode of operation is shown in figure 3. the count for the dividebyeight counter is shown as 7, 7, 7, 8 which illustrates the operation of the reset function. if the shutdown signal is terminated before the v cc voltage reaches the lower uvlo limit (i.e. 9.8 volts), the unit will resume operation on the following v cc down slope, and if the shutdown signal is terminated on the v cc upward slope, the unit will resume operation on the second v cc down slope. ac reference buffer the ac reference buffer converts the voltage generated by the ac error amplifier to be converted into a current to be summed with the ramp compensation signal and the instantaneous current signal. figure 33. ac reference buffer schematic current mirror - + i 1 i 1 - + 16 k 6.7 k 2.9 v unity gain amplifier ac error amp ac comp 3 pwm, ramp comp current sense amp the buffer's transfer function is: i out (2.9 v v ac(ea) ) 6.7 k the buffer amplifier, converts the input voltage to a current by creating a current equal to the voltage difference between the ac error amplifier output and the 2.9 volt reference dropped across the 6.7 k resistor. the bipolar transistor level shifts the voltage and maintains the proper current into the current mirror. the current mirror has a 1:1 ratio and delivers its output current to the pwm input. this current is summed with the currents of the ramp compensation signal and the instantaneous current signal to determine the turnoff point in the switching cycle. startup circuit the startup circuit serves several functions. in addition to providing the initial charge on the v cc capacitor, it serves as a timer for the startup, overcurrent, and shutdown modes of operation. due to the nature of this circuit, this chip must be biased using the startup circuit and an auxiliary winding on the power transformer. attempting to operate this chip off of a fixed voltage supply will cause the chip to latch up in some modes of operation. a high voltage fet is biased as a current source to provide current for startup power. on the application of input voltage, the high voltage startup circuit is enabled and current is drawn from the rectified ac line to charge the v cc cap. when the voltage on the v cc cap reaches the turn on point for the uvlo circuit (10.8 volts nominal), the startup circuit is disabled, and the pwm circuit is enabled. with the ncp1651 enabled, the bias current increases from its standby level to the operational level. the dividebyeight counter is preset to the count of 7, so that on startup the chip will not be operational on the first cycle. the second v cc cycle will be number 8, and the chip will be allowed to start at this time. the unit will remain operational as long as the v cc voltage remains above the uvlo undervoltage trip point. if the v cc voltage is reduced to the ovlo undervoltage trip point, operation of the unit will be disabled, and the startup circuit will again be enabled, and will charge the v cc cap up to the turn on voltage level. at this point the startup circuit will turn off and the unit will remain in the shutdown mode. this will continue for the next seven cycles. on the eighth cycle, the npc1651 will again become operational. if the v cc voltage remains above the undervoltage trip point the unit will continue to operate, if not the unit will begin another dividebyeight cycle. the purpose of the dividebyeight counter reduces the power dissipation of the chip under overload conditions and will allow it to recycle indefinitely without overheating the chip. it is critical that the output voltage reaches a level that allows the auxiliary voltage to remain above the uvlo turnoff level before the v cc cap has discharged to that level. if the bias voltage generated by the inductor winding fails to exceed the shutdown voltage before the capacitor reduces to the uvlo undervoltage turnoff level, the unit will shut down and go into a dividebyeight cycle, and will never start. if this occurs, the v cc capacitor value should be increased. softstart circuit the ac error amplifier has been configured such that a low output level will cause the output duty cycle to go to zero. this will have the effect of softstarting the unit at turnon, since the output is coupled to ground through a capacitor. there will be an initial offset of the output voltage due to the output current and the resistor at pin 3. for example, if the output is saturated in the high state at turn on, it will source 50 a. if pin 3 is terminated with a 2.2 k resistor and a 0.01 f capacitor, the initial step will be: 50 a 2.2 k 0.11 volts and the rate of rise will be: 50 a 0.01 f 5mv s or, 560 s until the output is at 2.8 volts, which corresponds to full duty cycle. an external softstart circuit can be added, as shown in figure 25, if additional time is desired.
ncp1651 http://onsemi.com 20 design guidelines 16 figure 34. typical application schematic note: this is a theoretical design, and it is not implied that a circuit designed by this procedure will operate properly without normal troubleshooting and adjustments as are common with any power conversion circuit. on semiconductor provides a spread sheet that incorporates the following equations, and will calculate the bias components for a circuit using the schematic shown. - + - + - + - + ramp compensation oscillator ac error amp uvlo reference regulator 4 v 6.5 v 13 12 v cc v ref driver s r q pwm 4 v 16 k vi current sense amplifier + l 1 r shunt c 12 r 10 r 13 43 76 c t c timing ramp comp i avg fltr i avg 5 60 k 20 k average current compensation ac reference buffer c 3 r 3 c 4 ac comp 11 c ac ac ref ac input 10 gnd 2 reference multiplier a p vi converter 2.5 v c in 9 r ac1 1 f 8 d 3 d 4 d 2 d 1 v in r ac2 25 k 4.5 v out i s+ 0.75 v line + k ? i in = v ref 0.47 f c ref 1 - + - + - + 0.01 f r tn c out 12 v 7.5 k 4.7 k tl431 4.02 k 5.23 k 5.23 k undervoltage comparator error amplifier mc3303 overvoltage comparator 422 453 9.31 k 8 counter fb/sd 6.5 v 3.8 k 20 a overtemperature sensor startup set dominant leb q 1 2 470 shutdown
ncp1651 http://onsemi.com 21 basic specifications the design of any power converter begins with a basic set of specifications. the following parameters should be known before you begin: po max (maximum rated output power) vrms min (minimum operational line voltage) vrms max (maximum operational line voltage) f switch (nominal switching frequency) v out (nominal regulated output voltage) most of these parameters will be dictated by system requirements. transformer for an average current mode, fixed frequency pfc converter, there is no magic formula to determine the optimum value of the inductor. there are several tradeoff's that should be considered. these include peak current vs. average current, and switching losses vs. core losses. all of these are a function of inductance, line and load. these parameters determine when the converter is operating in the continuous conduction mode and when it is operating in the discontinuous conduction mode. for an average current mode, fixed frequency pfc converter, there is no magic formula to determine the optimum value of the transformer's primary inductance. there are several tradeoff's that should be considered. these include peak current vs. average current, switching losses vs. core losses and range of duty cycles over the operational line and load range. all of these are a function of inductance, line and load. these parameters determine when the converter is operating in the continuous conduction mode and when it is operating in the discontinuous conduction mode. if you are designing your own transformer, the on semiconductor spreadsheet ( ncp1651_design.xls ) that is available as a design aid for this part can be of help. enter various values of inductance as well as the turns ratio and observe the variation in duty cycle and peak current vs. average current. the transformer's duty cycle is an important parameter. there are two main limitations for the duty cycle. the output voltage will be reflected back to the primary and will be scaled by the duty cycle. this means that with a 10:1 (pri:sec) turns ratio, and a 12 volt output, the power switch will see the input voltage plus 120 volts (10 x 12 volts) plus spikes. this reflected voltage determines the maximum voltage rating of the power switch. also, there are practical limits to the turns ratio. in general 10:1 is about the maximum, although some transformer manufacturers go as high as 12:1 or even 15:1. turns ratios of 20:1 and above are not normally practicle as they result in very high values of leakage inductance, which creates large spikes on the power switch. they also have a very large reflected voltage associated with them. the other option is to contact a transformer manufacturer such as coiltronics (www.cooperet.com/ ) or coilcraft (www.coilcraft.com/ ). these companies will design and manufacture transformers to your requirements. using the available spreadsheet, with the following parameters, a primary inductance of 330 h and a turns ratio of 10:1 would be a good choice. limits po max = 100 w vin max = 265 v rms vin min = 85 v rms v o = 5 v l p = 330 h f switch = 100 khz n p /n s = 10 figure 35. switching current versus phase angle phase angle ( ) 0 45 90 135 180 current (a) 6 5 4 3 2 1 0 peak current pedistal current figure 36. continuous/discontinuous and duty cycle degrees ( ) 0 45 90 135 180 duty cycle (%) 100 75 50 25 0 100% = discontinuous 50% = continuous duty cycle mode if a secondary winding is desired to provide a bias supply, it should provide a minimum of 12.1 volts (to exceed the
ncp1651 http://onsemi.com 22 uvlo spec) and a maximum of 18 volts. the secondary should be connected such that it conducts when the power switch is off. this will create an output voltage that varies with the input voltage, and near the zero crossings of the line freqency will have a peak voltage equal to the regulated output voltage divided by the turns ratio. the filter cap on the v cc pin needs to be of sufficient size to hold the voltage up over between the zero crossings. error amplifier the error amplifier resides on the secondary side of the circuit, and therefore is not part of the chip. a minimal solution would include either a discrete amplifier and reference, or an integrated circuit that combines both, such as the tl431 series of regulators. figure 37. error amplifier circuit - + fb/sd error amp r fb c fb r dc2 r dc1 r opto v v out v ref2 this configuration for the error amplifier will result in a low cost regulator, however, due to the slow loop response of a pfc regulator it will not protect against overvoltage conditions (e.g. load removal) or droop when a transient load is added. the primary side circuit has been designed such that the pfc controller will operate at maximum duty cycle with the optocouple in a nonconducting state. this is necessary to allow the unit to bring up the output when the system is initially energized. at this time there is not output voltage available to drive the led in the optocoupler. in the circuit of figure 37, the amplifier and reference need to be rated at the maximum voltage that the output will experience, including transient conditions. resistors r dc1 and r dc2 need to be choosen such that the voltage at v is equal to v ref2 when v out is at its regulated voltage. r opto is a current limiting resistor that protects the optocoupler from current transients due to output surges. this design also includes inherent compensation from transients. si nce the bandwidth of the error amplifier is very low, its output can not respond rapidly to changes in the output voltage. a transient change in the output voltage will change the current through r opto . since the output of the error amplifier does not change immediately, if the output voltage increases, the voltage across r opto will increase. this drives more current through the optocoupler, which in turn reduces the output of the converter. an alternate regulator is recommended, which is only slightly more expensive, and offers excellent protection from positive transients, and quick recovery from negative transients. figure 38. error amp with over/undershoot protection - + - + - + 12 v 7.5 k r bias 0.01 f 4.02 k 5.23 k 9.31 k r out 453 422 5.23 k r tn undervoltage capacitor 3.6 k r opto c out error amplifier mc3303 overvoltage comparator tl431 the configuration shown in figure 38, incorporates an error amplifier with slow loop response, plus overvoltage and undervoltage comparators. under normal operation the outputs of the undervoltage and overvoltage comparators are high. the undervoltage comparator provids drive for the optocoupler, while the overvoltage compartor reverse biases the diode on its output and is out of the loop. this circuit is designed with 8% trip points both above and below the regulation limit. if an overvoltage condition exists, the overvoltage comparator will respond very quickly. when its output goes low, it will provide maximum drive to the optocoupler, which will shut off the output of the converter. if the output voltage drops 8% or more below its regulated level, the undervoltage comparator will go low. this will remove the drive from the optocoupler, which will allow the regulator to increase the duty cycle and return the output to its regulation range much faster than the error amplifier could. this configuration will work over a range of 5 to 30 volts, with the appropriate changes in r out , r bias and r opto . r out (k ) = (v out 4.753) / 0.7785 r bias (k ) = (v out 4.4) r opto (k ) = (v out 3) / 2
ncp1651 http://onsemi.com 23 the value for r opto will allow a maximum of 2 ma to drive the optocoupler. if additional current is needed, change the 2 in the denominator of that equation to the current (in ma) that is desired. ac voltage divider the voltage divider from the input rectifiers to ground is a simple but important calculation. for this calculation it is necessary to know the maximum line that the unit can operate at. the peak input voltage will be: vin peak = 1.414 x vrms max the maximum voltage at the ac input (pin 5) is 3.75 volts (this is true for both multipliers). if the maximum line voltage is 265 vac, the peak input voltage is: vin peak = 1.414 x 265 v rms = 375 v pk to keep the power dissipation reasonable for a 1/2 watt resistor (r ac1 ), it should dissipate no more than 1/4 watt. the power in this resistor is: pr ac1 = (375 v 3.75 v)2 / r ac1 = 0.25 watts so: r ac1 = 551 k to minimize dissipation, use the next largest standard value, or 560 k . then, r ac2 = 3.75 v / ((375 v 3.75 v) / 560 k) = 5.6 k current sense resistor/ramp compensation the combination of the voltage developed across the current sense resistor and ramp compensation signal, will determine the peak instantaneous current that the power switch will be allowed to conduct before it is turned off. the vector sum of the three signals that combine to create the signal at the noninverting input to the pwm comparator must add up to 4.0 volts in order to terminate the switch cycle. these signals are the error signal from the ac error amp, the ramp compensation signal, and the instantaneous current. for a worst case condition, the output of the ac error amp could be zero (current), which would require that the sum of the ramp compensation signal and current signal be 4.0 volts. this must be evaluated under full load and low line conditions. for proper ramp compensation, the ramp signal should match the falling di/dt (which has been converted to a dv/dt) of the inductor at 50% duty cycle. 50% duty cycle will occur when the input voltage is 50% of the output voltage. both the falling di/dt and output voltage need to be reflected by the transformer turns ratio to the primary side. thus the following equations for r s and r rc must be satisfied: v in v o 2 n p n s the turns ratio (n p /n s ) reflects the output voltage to the primary side of the transformer. for proper slope compensation, the relationship between r s and r rc is: r s 25.6 l p tv out r rc n s n p for maximum output current, when the error amplifier is saturated in a low state, the ramp compensation signal plus the current signal must equal 4.0 volts, which is the reference level for the pwm comparator. so: r rc 102 t on 4t 5ti pk r s combining these two equations gives: r s l p t on v out (n p n s) 1.25 l p i pk supporting equations: where: r s is the current shunt resistor (ohms) r rc is the ramp compensation resistor (ohms) t on is the on time for the conditions given ( s) t is the period for the switching frequency ( s) l p is the primary inductance of the transformer ( h) v out is the output voltage (vdc) v rms is the rms line voltage at low line (v rms ) p out is the output power at full load (watts) i avg (t) is the avg current for one switching cycle (a) i pk is the instantaneous peak primary side current (a) v (t) is the peak line voltage (volts) n p /n s is the transformer turns ratio (dimensionless) current scaling resistor & filter capacitor r 7 sets the gain of the averaged current signal out of the current sense amplifier which is fed into the ac error amplifier. r 7 is used to scale the current to the appropriate level for protection purposes in the ac error amplifier circuit. r 7 should be calculated to limit the maximum current signal at the input to the ac error amplifier to less than 4.5 volts at low line and full load. 4.5 volts is the clamp voltage at the output of the reference amplifier and limits the maximum averaged current that the unit can process. the equation for r 7 is: r 7 47, 140 p in r s v inll (0.75 v inll ac ratio) where: p in = rated input power (w) where: r s = shunt resistance (w) where: v inll = min. operating rms input voltage (w) where: ac ratio = ac attenuation factor at pin 9 this equation does not allow for tolerances, and it would be advisable to increase the input power to assure operation at maximum power over production tolerance variations. the current sense filter capacitor should be selected to set its pole about a factor of 10 below the switching frequency. c 6 5.3 f where: c 6 = pin 6 capacitance (nf) where: f = pole frequency (khz) so, for a 100 khz switching frequency, a 10 khz pole is desirable, and c 6 would be 0.5 nf.
ncp1651 http://onsemi.com 24 reference multiplier the output of the reference multiplier is a pulse width modulated representation of the analog input. the multiplier is internally loaded with a resistor to ground which will set the dc gain. an external capacitor is required to filter the signal back into one that resembles the input haversine. the pole for this circuit should be greater than the line frequency and lower than the switching frequency. 1200 hz is a recommended starting value for a 60 hz line frequency. the filter capacitor for pin 4 can be determined by the following equation: c 10 1 2 25 k f pole 6.366e6 f pole where: c 10 = pin 4 capacitance (f) where: f pole = ref gain pole freq (hz) ac error amplifier the ac error amplifier is a transonductance amplifier that is terminated with a series r c impedance. this creates a polezero pair. to determine the values of r 3 and c 3 , it is necessary to look at the two signals that reach the pwm inputs. the noninverting input is a slow loop using the averaged current signal. it's gain is: a if 15 k 1k 15 k r 10 (g m r 3) 2.3 where the first two terms are the gains in the current sense amplifier averaging circuit. the next term is the gain of the transconductance amplifier and the constant is the gain of the ac reference buffer. the high frequency path is that of the instantaneous current signal to the pwm noninverting input. this gain is simply 16, since the input signal is converted to a current through a 1 k resistor, and then terminated by the 16 k resistor at the pwm input. for stability, the gain of the low frequency path must be less than the gain of the high frequency path. this can be written as: 517, 500 g m r3 r 10 16 the suggested resistor and capacitor values are: r 11 r 7 56,000 g m and for a zero at 1/10th of the switching frequency c 11 1.59 f sw r 11 where: r 7 & r 11 are in units of ohms where: g m is in units of mhos where: c 11 is in farads where: f sw is in hz loop compensation figure 39. voltage regulation loop - + reference multiplier pwm out 1 logic v ref2 4 v i s+ q1 5 c.s. amp - + 25 k ac error amp r s r 10 7 i avg v ref divider error amp reference signal modulator and output stage v v o r dc2 r dc1 r dc2 f z 1 2 c fb r fb a v 1 2 fc fb r dc1 v ref v fb 1.88 v ac v ac v line r ac2 r ac1 r ac2 v out i in
n p n s r l
t t on 1 r dc1 r dc2 f p 1 2 r l c r ac1 r l c v o v ac v v line i in n p : n s r ac2 c 10 10 ref fltr - + r opto r fb c fb error amp v ea 0.022 f c 8 6.5 v 3.8 k opto transfer v fb v ea 3.8kctr r opto a v r fb r dc1 for f > f z : for f < f z : i in v ref r 7 r s 75, 000 v fb fb/sd 8
ncp1651 http://onsemi.com 25 loop model the model for the voltage loop has been broken down into six sections. the voltage divider, error amplifier, and opto transfer are external to the chip, and the reference signal, modulator and output stage are internal. the modulator and output stage circuitry is greatly simplified b ased on the assumption that that poles and zeros in the current feedback loop are considerably greater than the bandwidth of the overall loop. this should be a good assumption, because a bandwidth in the kilohertz is necessary for a good current waveform, and the voltage error amplifier needs to have a bandwidth of less than the lowest line frequency that will be used. there are two poles in this circuit. the output filter has a pole that varies with the load. the pole on the voltage error amplifier will be determined by this analysis. voltage divider the voltage divider is located on the secondary side circuitry. it is a simple resistive divider that reduces the output voltage to the level required by the internal reference on the voltage error amplifier. if the amplifier circuit of figure 38 is used, there are four resistors instead of 2. to determine the gain of this circuit, r dc1 is the equivalent of the upper two resistors, 9.31 k and 453 ohms respectively, and r dc2 is the equivalent of the lower two resistors, 422 and 5.23 k respectively. voltage error amplifier the voltage error amplifier is constrained by the two equations. when this amplifier is compensated with a polezero pair, there will be a unity gain pole which will be cancelled by the zero at frequency f z . the corresponding bode plot would be: figure 40. polezero bode plot f, frequency gain (db) 20 0 20 unity gain a v f z the gain at frequencies greater than f z is determined by r fb . once r fb is determined, the value of c fb can be easily calculted using the formula for f z . optocoupler transfer the optocoupler is used to allow for galvanic isolation for the error signal from the secondary to primary side circuits. the gain is based on the current transfer ratio of the device. this can change over temperature and time, but will not result in a large change in db. the recommended capacitor at pin 8 is .022 f. if a larger capacitor is used, the pole may become low enough that it will have an effect on the gain phase plots near the unity gain crossover frequency. in this case and additional zero will be required in the error amplifier bias circuitry. reference signal the error signal is transmitted to the primary side circuit via. the optocoupler, is converted to a current by the vi converter and is then used as an input to the reference multiplier. the gain of this block is dependent on the ac input voltage, because of the multiplier which requires two inputs for one output. modultator and output stage the modulator receives an input from the reference multiplier and forces the current to follow the shape and amplitude. the is an internal loop within this section due to the current sense amplifier. based on the assumptions listed in the introduction to this analysis, this is not analyzed separately. the equation for the gain is good for frequencies below the pole. there is a single pole due to the output filter. since the ncp1651 is a current mode converter, the inductor is not part of the output pole as can be seen in that equation. the modulator and output stage transfer functions have been split into two sets of equations. the first defines the relationship between the input current and ac reference signal, and the later, define the output stage gain and pole. due to the nature of a flyback transformer, the gain of the output stage is dependant on the duty cycle (t on /t). for continuous mode operation, the ontime is: t on t n s n p 2 v rms v out 1 calculating the loop gain at this point in the design process, all of the parameters involved in this calculation have been determined with the exception of the polezero pair on the output of the voltage error amplifier. all equations give gains in absolute numbers. it is necessary to convert these to the decibell format using the following formula: a(db) = 20 log 10 (a) for example, the voltage divider would be: a 5.6 k 560 k 5.6 k 0.0099 a(db) = 20 log 10 0.0099 = 40 db the gain of the loop will vary as the input voltage changes. it is recommeded that the compensation for the error amplifier be calculated under high line, full load conditions. this should be the greatest bandwidth that the unit will see.
ncp1651 http://onsemi.com 26 by necessity, the unity gain (0 db) loop bandwidth for a pfc unit, must be less than the line frequency. if the bandwidth approaches or exceeds the line frequency, the voltage error amplifier signal will have freqency components in its output that are greater than the line frequency. these components will cause distortion in the output of the reference amplifier, which is used to shape the current waveform. this in turn will cause distortion in the current and reduce the power factor. typically the maximum bandwidth for a 60 hz pfc converter is 10 hz, and slightly less for a 50 hz system. this can be adjusted to meet the particular requirements of a system. the unity gain bandwidth is determined by the frequency at which the loop gain passes through the 0 db level. for stability purposes, the gain should pass through 0 db with a slope of 20 db for approximately on decade on either side of the unity gain fr equency. this assures a phase margin of greater than 45 . the gain can be calculated graphically using the equations of figure 18 as follows: divider: calculate v /v o in db, this value is constant so it will not change with frequency. optocoupler transfer: calculate v fb /v ea using the equation provided. convert this value into db. reference signal: calculate v ref /v fb using the peak level of the ac input signal at high line that will be seen on pin 9. convert this to db. this is also a constant value. modulator and output stage: calculate the gain in db for di o /dv ref for the modulator, and also the gain in db for the output stage (dv out /di in ). calculate the pole frequency. the gain will be constant for all frequencies less than f p . starting at the pole frequency, this gain will drop off at a rate of 20 db/decade. plot the sum of all of the calculated values. be sure to include the output pole. it should resemble the plot of figure 41. this plot shows a gain of 34 db until the pole of the output filter is reached at 3 hz. after that, the gain is reduced at a rate of 20 db/decade. figure 41. forward gain plot frequency (hz) 0.01 0.1 1 100 1000 gain (db) 40 30 25 20 0 10 15 10 5 5 10 15 35 for a crossover frequency of 10 hz, the error amplifier needs a gain of 25 db at 10 hz, since the forward gain is equal to 25 db at this frequency. the high frequency gain of the error amplifier is: a vhf = r fb / r dc1 where r dc1 is the output voltage divider resistor that is connected from the output of the converter to the input of the error amplifier. if the output circuit of figure 38 is used, r dc1 would be 9.31 k + 453 , or 9.76 k . a gain of 25 db is equal to a divider ratio of: a v = 10 (25/20) = 0.056 so, r fb / r dc1 = 0.056 or, r fb = 0.056 x 9.76 k = 546 the closest standard value resistor is 560 . to offset the 2 hz pole of the output filter, the error amplifier should have a zero of 2 hz or slightly higher. for a 2 hz zero, the compensation capacitor, c fb can be calculated by: c fb 1 2 r fb 3hz 95 f 100 f is the closest standard value capacitor and would be a good choice. this solution will provide a phase margin of close to 90 . in practice the value of capacitance could be cut in half or more and probably remain stable. this can be tested in the circuit, or simulated with a model in spice or a similar analysis program. the gain and phase plots of the completed loop are shown in figures 42 and 43. these include the effects of all of the stages shown. figure 42. loop gain plot frequency (hz) 0.01 0.1 1 100 1000 gain (db) 80 60 40 20 0 20 40 10
ncp1651 http://onsemi.com 27 figure 43. loop phase plot frequency (hz) 0.01 0.1 1 100 1000 phase ( c) 75 105 165 180 10 150 135 120 90
ncp1651 http://onsemi.com 28 package dimensions so16 d suffix case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 so16 mm inches 0.060 1.52 0.275 7.0 0.024 0.6 0.050 1.270 0.155 4.0 footprint for soldering on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp1651/d the product described herein (ncp1651), may be covered by u.s. patents. other patents may be pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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