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S3FB42F 8-bit cmos microcontroller user's manual revision 1
important notice the information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including " typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. S3FB42F 8-bit cmos microcontroller user's manual, revision 1 publication number: 2 1 - s3-fb42f - 052001 ? 2001 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso- 140 01 certification (b vq1 certificate no. 9330 ). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-lee, kiheung-eup yongin-city kyungi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(331 ) -209-1907 fax: ( 8 2) -(331)-209-1889 home-page url: http:// www.samsung semi .com/ printed in the republic of korea
S3FB42F microcontroller iii preface the S3FB42F microcontroller user's manual is designed for application designers and progr ammers who are using the S3FB42F microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has nine chapter s: chapter 1 product overview chapter 2 address spaces chapter 3 register chapter 4 memory map chapter 5 hardware stack chapter 6 exceptions chapter 7 coprocessor interface chapter 8 instruction set chapter 1, "product overview," is a high-l evel introduction to S3FB42F with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data memory spaces . chapter 2 also describes rom code option. chapter 3, " register ," describes the special registers. chapter 4, " memory map ," describes the internal register file. chapter 5, " hardware stack," describes the S3FB42F hardware stack structure in detail . chapter 6, " exception ," describes the S3FB42F exception structure in detail . chapter 7, ?coprocessor interface,? describes the S3FB42F coprocessor interface in detail. chapter 8, ?instruction set,? describes the features and conventions of the instruction set used for all s3fb-series microcontrollers. a basic familiarity with the information in part i will help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the s3fb-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapter s 1 ? 3 carefully. then, briefly look over the detailed information in chapter s 4, 5, 6, 7, and 8 . later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the S3FB42F microcontroller. also included in part ii are electrical, mechanical. it has 19 chapter s: chapter 9 pll (phase locked loop) chapter 10 reset and power-down chapter 1 1 i/o ports chapter 1 2 basic timer chapter 1 3 real timer (watch timer) chapter 1 4 16-bit timer (8-bit timer a & b) chapter 1 5 serial i/o interface chapter 16 uart chapter 17 i 2 s bus (inter-ic sound) chapter 18 ssfdc (solid state floppy disk card) chapter 19 parallel port interface chapter 20 8-bit analog-to-digital converter chapter 21 i 2 c-bus interface chapter 22 random number generator chapter 23 usb chapter 24 embedded flash memory interface chapter 25 mac2424 chapter 26 electrical data chapter 27 mechanical data chapter 25 , "mac2424" describes the mac2424 structure in detail, as well as instructions.
iv ks86c6204/c6208/p6 208 ( preliminary spec ) one order form is included at the back of this manual to facilitate customer order for S3FB42F microcontrollers: the flash factory writing order form. you can photocopy this form, fill it out, and then forward it to your local samsung sales representative.
S3FB42F microcontroller v table of contents part i ? programming model chapter 1 product overview calmrisc overview ................................ ................................ ................................ ............................... 1-1 features ................................ ................................ ................................ ................................ ............. 1-1 pin description ................................ ................................ ................................ ................................ .... 1-9 pin circuit diagrams ................................ ................................ ................................ ............................ 1-13 chapter 2 address spaces overview ................................ ................................ ................................ ................................ ............. 2-1 program memory (rom) ................................ ................................ ................................ ...................... 2-2 data memory organization ................................ ................................ ................................ ................... 2-3 chapter 3 register overview ................................ ................................ ................................ ................................ ............. 3-1 index registers: idh, idl0 and idl1 ................................ ................................ .............................. 3-2 link registers: ilx, ilh and ill ................................ ................................ ................................ .... 3-2 status register 0: sr0 ................................ ................................ ................................ ................ 3-3 status register 1: sr1 ................................ ................................ ................................ ................ 3-4 chapter 4 memory map overview ................................ ................................ ................................ ................................ ............. 4-1 chapter 5 hardware stack overview ................................ ................................ ................................ ................................ ............. 5-1
vi S3FB42F microcontroller table of contents (continued) chapter 6 exceptions overview ................................ ................................ ................................ ................................ ............. 6-1 hardware reset ................................ ................................ ................................ ........................... 6-1 nmi exception (edge sensitive) ................................ ................................ ................................ .... 6-2 irq[0] exception (level-sensitive) ................................ ................................ ................................ . 6-2 irq[1] exception (level-sensitive) ................................ ................................ ................................ . 6-2 hardware stack full exception ................................ ................................ ................................ ..... 6-2 break exception ................................ ................................ ................................ .......................... 6-2 exceptions (or interrupts) ................................ ................................ ................................ ............. 6-3 interrupt mask registers ................................ ................................ ................................ .............. 6-5 interrupt priority register ................................ ................................ ................................ .............. 6-6 chapter 7 coprocessor interface overview ................................ ................................ ................................ ................................ ............. 7-1 chapter 8 instruction set overview ................................ ................................ ................................ ................................ ............. 8-1 glossary ................................ ................................ ................................ ................................ ..... 8-1 instruction set map ................................ ................................ ................................ ............................. 8-2 quick reference ................................ ................................ ................................ ................................ .. 8-9 instruction group summary ................................ ................................ ................................ .................. 8-12 alu instructions ................................ ................................ ................................ .......................... 8-12 shift/rotate instructions ................................ ................................ ................................ ............... 8-16 load instructions ................................ ................................ ................................ ......................... 8-18 branch instructions ................................ ................................ ................................ ...................... 8-21 bit manipulation instructions ................................ ................................ ................................ ......... 8-25 miscellaneous instruction ................................ ................................ ................................ ............. 8-26 pseudo instructions ................................ ................................ ................................ ..................... 8-29
S3FB42F microcontroller vii table of contents (continued) part ii ? hardware descriptions chapter 9 pll (phase locked loop) overview ................................ ................................ ................................ ................................ ............. 9-1 pll register description ................................ ................................ ................................ ...................... 9-2 pll control register (pllcon) ................................ ................................ ................................ .... 9-2 pll frequency divider data register (plldata) ................................ ................................ ........... 9-2 system control circuit ................................ ................................ ................................ ......................... 9-4 oscillator control register (osccon) ................................ ................................ ........................... 9-4 power control register (pcon) ................................ ................................ ................................ .... 9-5 chapter 10 reset and power-down overview ................................ ................................ ................................ ................................ ............. 10-1 chapter 11 i/o ports port data registers ................................ ................................ ................................ ............................. 11-1 port control registers ................................ ................................ ................................ .......................... 11-2 port 0 control register (p0con) ................................ ................................ ................................ ... 11-2 port 1 control register (p1con) ................................ ................................ ................................ ... 11-2 port 2 control low register (p2conl) ................................ ................................ .......................... 11-3 port 2 control high register (p2conh) ................................ ................................ ......................... 11-4 port 3 control low register (p3conl) ................................ ................................ .......................... 11-5 port 3 control high register (p3conh) ................................ ................................ ......................... 11-6 port 3 pull-up register (p3pur) ................................ ................................ ................................ ... 11-6 port 4 control register (p4con) ................................ ................................ ................................ ... 11-7 port 4 interrupt control register (p4intcon) ................................ ................................ ................. 11-7 port 4 interrupt mode register (p4intmod) ................................ ................................ ................... 11-8 port 5 control register (p5con) ................................ ................................ ................................ ... 11-8 port 5 pull-up register (p5pur) ................................ ................................ ................................ ... 11-9 port 5 interrupt control register (p5intcon) ................................ ................................ ................. 11-9 port 5 external interrupt pending register (eintpnd) ................................ ................................ ..... 11-9 port 5 interrupt mode low register (p5intmodl) ................................ ................................ .......... 11-9 port 5 interrupt mode high register (p5intmodh) ................................ ................................ ......... 11-10 port 6 control register (p6con) ................................ ................................ ................................ ... 11-11 port 2 control high register or p6pur (p2conh) ................................ ................................ ........... 11-12 port 7 control register (p7con) ................................ ................................ ................................ ... 11-12 port 8 control register (p8con) ................................ ................................ ................................ ... 11-13 port 9 control register (p9con) ................................ ................................ ................................ ... 11-14
viii S3FB42F microcontroller table of contents (continued) chapter 12 basic timer overview ................................ ................................ ................................ ................................ ............. 12-1 watchdog timer ................................ ................................ ................................ ................................ .. 12-2 block diagram ................................ ................................ ................................ ............................ 12-3 chapter 13 real timer (watch timer) overview ................................ ................................ ................................ ................................ ............. 13-1 watch timer circuit diagram ................................ ................................ ................................ ........ 13-2 chapter 14 16-bit timer (8-bit timer a & b) overview ................................ ................................ ................................ ................................ ............. 14-1 chapter 15 serial i/o interface overview ................................ ................................ ................................ ................................ ............. 15-1 sio pre-scaler register (siops) ................................ ................................ ................................ .......... 15-2 block diagram ................................ ................................ ................................ ................................ .... 15-2 serial i/o timing diagram ................................ ................................ ................................ ..................... 15-3 chapter 16 uart overview ................................ ................................ ................................ ................................ ............. 16-1 uart special registers ................................ ................................ ................................ ....................... 16-2 uart line control register ................................ ................................ ................................ .......... 16-2 uart control register ................................ ................................ ................................ ................. 16-3 uart status register ................................ ................................ ................................ .................. 16-4 uart transmit buffer register ................................ ................................ ................................ ..... 16-5 uart receive buffer register ................................ ................................ ................................ ....... 16-5 uart baud rate prescaler registers ................................ ................................ ........................... 16-6 uart interrupt pending register (upend) ................................ ................................ ...................... 16-6
S3FB42F microcontroller ix table of contents (continued) chapter 17 i 2 s bus (inter-ic sound) overview ................................ ................................ ................................ ................................ ............. 17-1 the i 2 s bus ................................ ................................ ................................ ................................ ........ 17-2 i 2 s special register description ................................ ................................ ................................ ........... 17-6 i 2 s control registers ................................ ................................ ................................ ................... 17-6 i 2 s control registers (iiscon) ................................ ................................ ................................ ..... 17-6 i 2 s mode registers (iismode) ................................ ................................ ................................ ..... 17-8 i 2 s pointer registers (iisptr) ................................ ................................ ................................ ...... 17-9 i 2 s buffer registers (iisbuf) ................................ ................................ ................................ ........ 17-9 chapter 18 ssfdc ( soild state floppy disk card) overview ................................ ................................ ................................ ................................ ............. 18-1 ssfdc register description ................................ ................................ ................................ ................ 18-3 smartmedia control register (smcon) ................................ ................................ ......................... 18-3 smartmedia ecc count register (eccnt) ................................ ................................ .................... 18-3 smartmedia ecc data register (eccdata) ................................ ................................ .................. 18-4 smartmedia ecc result data register (eccrst) ................................ ................................ .......... 18-4 chapter 19 parallel port interface overview ................................ ................................ ................................ ................................ ............. 19-1 ppic operating modes ................................ ................................ ................................ ................ 19-2 ppic special registers ................................ ................................ ................................ ........................ 19-5 parallel port data/command data register ................................ ................................ .................... 19-5 parallel port status control and status register ................................ ................................ ............ 19-6 parallel port control register ................................ ................................ ................................ ........ 19-8 parallel port interrupt event registers ................................ ................................ ........................... 19-11 parallel port ack width register ................................ ................................ ................................ ... 19-12 chapter 20 8-bit analog-to-digital converter overview ................................ ................................ ................................ ................................ ............. 20-1 function description ................................ ................................ ................................ ............................ 20-1 conversion timing ................................ ................................ ................................ ............................... 20-2 a/d c special registers ................................ ................................ ................................ ...................... 20-3 a/d c control registers ................................ ................................ ................................ ............... 20-3 a/d converter data registers ................................ ................................ ................................ ....... 20-3
x S3FB42F microcontroller table of contents (continued) chapter 21 i 2 c bus interface overview ................................ ................................ ................................ ................................ ............. 21-1 functional description ................................ ................................ ................................ ................. 21-2 i 2 c special registers ................................ ................................ ................................ ........................... 21-3 multi-master i 2 c-bus control register ................................ ................................ ........................... 21-3 multi-master i 2 c-bus control/status register (iicsr) ................................ ................................ ..... 21-4 multi-master i 2 c-bus transmit/receive data register (iicdata) ................................ ...................... 21-5 multi-master i 2 c-bus address register (iicaddr) ................................ ................................ .......... 21-5 prescaler counter register (iiccnt) ................................ ................................ .............................. 21-6 chapter 22 random number generator overview ................................ ................................ ................................ ................................ ............. 22-1 functional description ................................ ................................ ................................ ................. 22-3 random number control register ................................ ................................ ................................ . 22-3 ring oscillator ................................ ................................ ................................ ............................ 22-4 linear feedback shift register 8 (lfsr8) ................................ ................................ ..................... 22-5 linear feedback shift register 16 (lfsr16) ................................ ................................ .................. 22-5 chapter 23 usb usb peripheral features ................................ ................................ ................................ ..................... 23-1 functional specification ................................ ................................ ................................ ............... 23-1 usb module block diagram ................................ ................................ ................................ ................. 23-2 function description ................................ ................................ ................................ ............................ 23-3 usb function registers description ................................ ................................ ................................ ..... 23-5 usb releated registers ................................ ................................ ................................ ...................... 23-6 chapter 24 embedded flash memory interface overview ................................ ................................ ................................ ................................ ............. 24-1 tool program mode ................................ ................................ ................................ ..................... 24-1 flash memory control register ................................ ................................ ................................ ..... 24-3
S3FB42F microcontroller xi table of contents (continued) chapter 25 mac2424 introduction ................................ ................................ ................................ ................................ ......... 25-1 architecture features ................................ ................................ ................................ .......................... 25-2 block diagram ................................ ................................ ................................ ................................ .... 25-3 i/o description ................................ ................................ ................................ ................................ .... 25-4 programming model ................................ ................................ ................................ ............................. 25-6 multiplier and accumulator unit ................................ ................................ ................................ .... 25-7 arithmetic unit ................................ ................................ ................................ ............................ 25-11 status register 1 (msr1) ................................ ................................ ................................ ............ 25-16 ram pointer unit ................................ ................................ ................................ ................................ . 25-18 address modification ................................ ................................ ................................ ................... 25-18 data memory spaces and organization ................................ ................................ ......................... 25-23 arithmetic unit ................................ ................................ ................................ ................................ .... 25-24 a, b accumulators ................................ ................................ ................................ ...................... 25-25 overflow protection in a/b accumulators ................................ ................................ ....................... 25-25 arithmetic unit ................................ ................................ ................................ ............................ 25-26 external condition generation unit ................................ ................................ ................................ 25-27 status register 0 (msr0) ................................ ................................ ................................ ............ 25-27 status register 2 (msr2) ................................ ................................ ................................ ............ 25-30 barrel shifter and exponent unit ................................ ................................ ................................ ........... 25-31 barrel shifter ................................ ................................ ................................ ............................... 25-32 exponent block ................................ ................................ ................................ ........................... 25-35 instruction set map and summary ................................ ................................ ................................ ........ 25-37 addressing modes ................................ ................................ ................................ ....................... 25-37 instruction coding ................................ ................................ ................................ ........................ 25-42 quick reference ................................ ................................ ................................ .......................... 25-55 quick reference ................................ ................................ ................................ .......................... 25-56 instruction set ................................ ................................ ................................ ................................ ..... 25-60 glossary ................................ ................................ ................................ ................................ ..... 25-60 instruction description ................................ ................................ ................................ ................. 25-61 chapter 26 electrical data overview ................................ ................................ ................................ ................................ ............. 26-1 chapter 27 mechanical data overview ................................ ................................ ................................ ................................ ............. 27-1

S3FB42F microcontroller xiii list of figures figure title page number number 1-1 top block diagram ................................ ................................ .............................. 1-3 1-2 calmrisc pipeline diagram ................................ ................................ ................. 1-4 1-3 calmrisc pipeline stream diagram ................................ ................................ ...... 1-5 1-4 block diagram ................................ ................................ ................................ .... 1-6 1-5 100-qfp pin assignment ................................ ................................ ..................... 1-7 1-6 100-tqfp pin assignment ................................ ................................ ................... 1-8 1-7 pin circuit type 1 (port 0, p1.0-p1.4, p6.0-p6.5, and port 7) ................................ .. 1-13 1-8 pin circuit type 2 (p6.6 and p6.7) ................................ ................................ ........ 1-13 1-9 pin circuit type 3 (p4.2) ................................ ................................ ...................... 1-14 1-10 pin circuit type 4 (port 2, port 8, and port 9) ................................ ........................ 1-15 1-11 pin circuit type 5 (port 3) ................................ ................................ .................... 1-15 1-12 pin circuit type 6 (p4.0, and p4.1) ................................ ................................ ....... 1-16 1-13 pin circuit type 7 (port 5) ................................ ................................ .................... 1-16 1-14 pin circuit type 8 (reset) ................................ ................................ .................. 1-17 1-15 pin circuit type 9 (test) ................................ ................................ ..................... 1-17 2-1 flash memory (code memory area) ................................ ................................ ...... 2-2 2-2 data memory map ................................ ................................ ............................... 2-3 2-3 data memory map in calmrisc side ................................ ................................ .... 2-4 2-4 data memory map in mac-2424 side ................................ ................................ .... 2-5 2-5 data memory map ................................ ................................ ............................... 2-6 3-1 bank selection by setting of grb bits and idb bit ................................ ................ 3-3 4-1 memory map area ................................ ................................ ............................... 4-1 5-1 hardware stack ................................ ................................ ................................ ... 5-1 5-2 even and odd bank selection example ................................ ................................ . 5-2 5-3 stack operation with pc [19:0] ................................ ................................ ............. 5-3 5-4 stack operation with registers ................................ ................................ ............. 5-4 5-5 stack overflow ................................ ................................ ................................ .... 5-5 6-1 interrupt structure ................................ ................................ ................................ 6-3 6-2 interrupt structure ................................ ................................ ................................ 6-4 6-3 interrupt mask register ................................ ................................ ........................ 6-5 6-4 interr upt priority register ................................ ................................ ...................... 6-6
xiv S3FB42F microcontroller list of figures (continued) figure title page number number 7-1 coprocessor interface diagram ................................ ................................ ............. 7-1 7-2 coprocessor instruction pipeline ................................ ................................ ........... 7-3 9-1 simple circuit diagram ................................ ................................ ........................ 9-1 9-2 pll frequency divider data register (plldata) ................................ ................... 9-3 9-3 system clock circuit diagram ................................ ................................ .............. 9-6 11-1 port data register structure ................................ ................................ ................. 11-1 12-1 basic timer control register (btcon) ................................ ................................ .. 12-1 12-2 watchdog timer control register (wdtcon) ................................ ........................ 12-2 12-3 watchdog timer enable register (wdten) ................................ ........................... 12-2 12-4 basic timer & watchdog timer functional block diagram ................................ ...... 12-3 13-1 watch timer circuit diagram ................................ ................................ ................ 13-2 14-1 timer a control register (tacon) ................................ ................................ ........ 14-1 14-2 timer b control register (tbcon) ................................ ................................ ........ 14-2 14-3 timer a, b function block diagram ................................ ................................ ...... 14-3 15-1 serial i/o module control registers (siocon) ................................ ....................... 15-1 15-2 sio pre-scaler register (siops) ................................ ................................ .......... 15-2 15-3 sio function block diagram ................................ ................................ ................ 15-2 15-4 serial i/o timing in transmit/receive mode (tx at falling, siocon.4=0) ................... 15-3 15-5 serial i/o timing in transmit/receive mode (tx at rising, siocon.4=1) ................... 15-3 16-1 uart block diagram ................................ ................................ ........................... 16-1 16-2 uart line control register (lcon) ................................ ................................ ...... 16-2 17-1 simple system configuration ................................ ................................ ................ 17-1 17-2 i 2 s basic interface format (phillips) ................................ ................................ ...... 17-2 17-3 lsi interface format (sony) ................................ ................................ .................. 17-2 17-4 timing for i 2 s transmitter ................................ ................................ ..................... 17-4 17-5 timing for i 2 s receiver ................................ ................................ ......................... 17-4 18-1 simple system configuration ................................ ................................ ................ 18-2 18-2 ecc processor block diagram ................................ ................................ ............. 18-5
S3FB42F microcontroller xv list of figures (continued) figure title page number number 19-1 compatibility hardware handshaking timing ................................ .......................... 19-3 19-2 ecp hardware handshaking timing (forward) ................................ ........................ 19-4 19-3 ecp h ardware handshaking timing (reverse) ................................ ........................ 19-4 20-1 a/d c block diagram ................................ ................................ ........................... 20-2 21-1 i 2 c-bus block diagram ................................ ................................ ........................ 22-1 21-2 multi-master i 2 c-bus tx/rx data register (iicdata) ................................ .............. 22-5 21-3 multi-master i 2 c-bus address register (iicaddr) ................................ .................. 22-6 22 -1 top block diagram of random number generator ................................ .................. 22-2 22-2 ring oscillator block ................................ ................................ ........................... 22-4 23-1 usb module block diagram ................................ ................................ ................. 23-2 23-2 function address register ................................ ................................ ................... 23-6 23-3 power management register ................................ ................................ ................ 23-7 23-4 frame number low register ................................ ................................ ................ 23-8 23-5 frame number high register ................................ ................................ ................ 23-8 23-6 interrupt pe nding register ................................ ................................ .................... 23-9 23-7 interrupt enable register ................................ ................................ ...................... 23-11 23-8 endpoint index register ................................ ................................ ....................... 23-12 23-9 endpoint direction register ................................ ................................ .................. 23-12 23-10 ep0 csr register (ep0csr) ................................ ................................ ............... 23-14 23-11 incsr register ................................ ................................ ................................ ... 23-16 23-12 out control status register ................................ ................................ ................ 23-18 23-13 in max packet register (inmaxp) ................................ ................................ ........ 23-19 23-14 out max packet register ................................ ................................ ................... 23-20 23-15 ep0 max packet register ................................ ................................ ................... 23-21 23-16 write counter lo regsiter ................................ ................................ ................... 23-22 23-17 write counter hi register ................................ ................................ ..................... 23-22 23-18 usb enable register ................................ ................................ ........................... 23-24 24-1 flash memory structure ................................ ................................ ....................... 24-2 24-2 flash memory control register ................................ ................................ ............. 24-4
xvi S3FB42F microcontroller list of figures (continued) figure title page number number 25-1 mac2424 block diagram ................................ ................................ ..................... 25-3 25-2 mac2424 pin diagram ................................ ................................ ......................... 25-4 25-3 multiplier and accumulator unit block diagram ................................ ...................... 25-7 25-4 mau registers configuration ................................ ................................ ................ 25-10 25-5 integer division example ................................ ................................ ...................... 25-13 25-6 fractional division example ................................ ................................ .................. 25-14 25-7 msr1 register configuration ................................ ................................ ................ 25-16 25-8 ram pointer unit block diagram ................................ ................................ .......... 25-19 25-9 pointer register and index register configuration ................................ ................... 25-20 25-10 modulo control register configuration ................................ ................................ ... 25-21 25-11 data memory space map ................................ ................................ ..................... 25-23 25-12 arithmetic unit block diagram ................................ ................................ .............. 25-24 25-13 ai accumulator register configuration ................................ ................................ ... 25-25 25-14 msr0 register configuration ................................ ................................ ................ 25-27 25-15 msr2 register configuration ................................ ................................ ................ 25-30 25-16 barrel shifter and exponent unit block diagram ................................ ..................... 25-31 25-17 various barrel shifter instruction operation ................................ ............................ 25-34 25-18 indirect addressing example i (read operation) ................................ ..................... 25-37 25-19 indirect addressing example ii (write operation) ................................ .................... 25-38 25-20 short direct addressing example ................................ ................................ ......... 25-39 25-21 long direct addressing example ................................ ................................ .......... 25-40 26-1 input timing for external interrupts (port 4, port5) ................................ ................... 26-3 26-2 input timing for reset ................................ ................................ ........................ 26-3 26-3 stop mode release timing when initiated by a reset ................................ .......... 26-6 26-4 stop mode release timing when initiated by interrupts ................................ .......... 26-7 26-5 serial data transfer timing ................................ ................................ ................... 26-8 26-6 clock timing measurement at x in ................................ ................................ ......... 26-11 27-1 100-qfp-1420c package dimensions ................................ ................................ ... 27-1 27-2 100-tqfp-1414 package dimensions ................................ ................................ ... 27-2
S3FB42F microcontroller xvii list of tables table title page number number 1-1 S3FB42F pin descriptions (100-tqfp) ................................ ................................ . 1-9 3-1 general and special purpose registers ................................ ................................ . 3-1 3-2 status register 0: sr0 ................................ ................................ ........................ 3-3 3-3 status register 1: sr1 ................................ ................................ ........................ 3-4 4-1 registers ................................ ................................ ................................ ............ 4-1 6-1 exceptions ................................ ................................ ................................ ......... 6-1 7-1 coprocessor instructions ................................ ................................ ...................... 7-2 8-1 instruction notation conventions ................................ ................................ ........... 8-1 8-2 overall instruction set map ................................ ................................ ................... 8-2 8-3 instruction encoding ................................ ................................ ............................ 8-4 8-4 index code information ("idx") ................................ ................................ ............... 8-7 8-5 index modification code information ("mod") ................................ ........................... 8-7 8-6 condition code information ("cc") ................................ ................................ .......... 8-7 8-7 "aluop1" code information ................................ ................................ .................. 8-8 8-8 "aluop2" code information ................................ ................................ .................. 8-8 8-9 "modop1" code information ................................ ................................ ................. 8-8 9-1 pll register description ................................ ................................ ...................... 9-2 9-2 system control circuit register description ................................ ........................... 9-4 11-1 port data register summary ................................ ................................ ................ 11-1 13-1 watch timer control register (wtcon): 8-bit r/w ................................ ................ 13-1 17-1 master transmitter with data rate of 2.5 mhz (10%) (unit: ns) ................................ 17-5 17-2 slave receiver with data rate of 2.5 mhz (10%) (unit: ns) ................................ ...... 17-5 17-3 function register description ................................ ................................ ............... 17-6
xviii S3FB42F microcontroller list of tables (continued) table title page number number 18-1 control register description ................................ ................................ ................. 18-3 23-1 general usb features ................................ ................................ ......................... 23-1 23-2 general function features ................................ ................................ ................... 23-1 23-3 usb function registers description ................................ ................................ ..... 23-5 23-4 interrupt pending register ................................ ................................ .................... 23-10 25-1 mac2424 pin description ................................ ................................ .................... 25-5 25-2 exponent evaluation and normalization example ................................ ................... 25-35 26-1 absolute maximum ratings ................................ ................................ .................. 26-1 26-2 d.c. electrical characteristics ................................ ................................ .............. 26-1 26-3 a.c. electrical characteristics ................................ ................................ .............. 26-3 26-4 input/output capacitance ................................ ................................ ..................... 26-3 26-5 a/d converter electrical characteristics ................................ ................................ 26-4 26-6 i 2 s master transmitter with data rate of 2.5 mhz (10%) (unit: ns) .......................... 26-4 26-7 i 2 s slave receiver with data rate of 2.5 mhz (10%) (unit: ns) ................................ 26-5 26-8 flash memory d.c. electrical characteristics ................................ ........................ 26-5 26-9 flash memory a.c. electrical characteristics ................................ ........................ 26-5 26-10 data retention supply voltage in stop mode ................................ ......................... 26-6 26-11 synchronous sio electrical characteristics ................................ ........................... 26-8 26-12 main oscillator frequency (fosc1) ................................ ................................ ......... 26-9 26-13 sub oscillator frequency (fosc2) ................................ ................................ .......... 26-10
S3FB42F microcontroller xix list of programming tips description page number chapter 6 : exceptions interrupt programming tip 1 ................................ ................................ ................................ .................. 6-7 interrupt programming tip 2 ................................ ................................ ................................ .................. 6-8

S3FB42F microcontroller xxi list of instruction descriptions instruction full instruction name page mnemonic number adc add with carry ................................ ................................ ................................ .... 8-31 add add ................................ ................................ ................................ .................... 8-32 and bit-wise and ................................ ................................ ................................ ...... 8-33 and sr0 bit-wise and with sr0call procedure ................................ ................................ ... 8-34 bank bank gpr selection ................................ ................................ ............................ 8-35 bitc bit complement ................................ ................................ ................................ .. 8-36 bitr bit reset ................................ ................................ ................................ ............ 8-37 bits bit set ................................ ................................ ................................ ................ 8-38 bitt bit test ................................ ................................ ................................ .............. 8-39 bmc/bms tf bit clear/set ................................ ................................ ................................ .... 8-40 call conditional subroutine call (pseudo instruction) ................................ ..................... 8-41 calls call subroutine ................................ ................................ ................................ .... 8-42 cld load into coprocessor ................................ ................................ ......................... 8-43 cld load from coprocessor ................................ ................................ ........................ 8-44 com 1's or bit-wise complement ................................ ................................ .................. 8-45 com2 2's complement ................................ ................................ ................................ .. 8-46 comc bit-wise complement with carry ................................ ................................ ........... 8-47 cop coprocessor ................................ ................................ ................................ ....... 8-48 cp compare ................................ ................................ ................................ ............. 8-49 cpc compare with carry ................................ ................................ ............................. 8-50 dec decrement ................................ ................................ ................................ .......... 8-51 decc decrement with carry ................................ ................................ .......................... 8-52 di disable interrupt (pseudo instruction) ................................ ................................ .... 8-53 ei enable interrupt (pseudo instruction) ................................ ................................ .... 8-54 idle idle operation (pseudo instruction) ................................ ................................ ....... 8-55 inc increment ................................ ................................ ................................ ........... 8-56 incc increment with carry ................................ ................................ ............................ 8-57 iret return from interrupt handling ................................ ................................ ............... 8-58 jnzd jump not zero with delay slot ................................ ................................ .............. 8-59 jp conditional jump (pseudo instruction) ................................ ................................ .. 8-60 jr conditional jump relative ................................ ................................ ..................... 8-61 lcall conditional subroutine call ................................ ................................ ................... 8-62 ld adr:8 load into memory ................................ ................................ ................................ 8-63
xxii S3FB42F microcontroller list of instruction descriptions (continued) instruction full instruction name page mnemonic number ld @ idm load into memory indexed ................................ ................................ ................... 8-64 ld load register ................................ ................................ ................................ ...... 8-65 ld load gpr:bankd, gpr:banks ................................ ................................ .............. 8-66 ld load gpr, tbh/tbl ................................ ................................ ............................ 8-67 ld load tbh/tbl, gpr ................................ ................................ ............................ 8-68 ld spr load spr ................................ ................................ ................................ ........... 8-69 ld spr0 load spr0 immediate ................................ ................................ ......................... 8-70 ldc load code ................................ ................................ ................................ .......... 8-71 ljp conditional jump ................................ ................................ ................................ . 8-72 llnk linked subroutine call conditional ................................ ................................ ........ 8-73 lnk linked subroutine call (pseudo instruction) ................................ .......................... 8-74 lnks linked subroutine call ................................ ................................ ......................... 8-75 lret return from linked subroutine call ................................ ................................ ....... 8-76 nop no operation ................................ ................................ ................................ ....... 8-77 or bit-wise or ................................ ................................ ................................ ........ 8-78 or sr0 bit-wise or with sr0 ................................ ................................ .......................... 8-79 pop pop ................................ ................................ ................................ ................... 8-80 pop pop to register ................................ ................................ ................................ .. 8-81 push push register ................................ ................................ ................................ ..... 8-82 ret return from subroutine ................................ ................................ ........................ 8-83 rl rotate left ................................ ................................ ................................ .......... 8-84 rlc rotate left with carry ................................ ................................ .......................... 8-85 rr rotate right ................................ ................................ ................................ ........ 8-86 rrc rotate right with carry ................................ ................................ ........................ 8-87 sbc subtract with carry ................................ ................................ .............................. 8-88 sl shif t left ................................ ................................ ................................ ............. 8-89 sla shift left arithmetic ................................ ................................ ............................. 8-90 sr shift right ................................ ................................ ................................ ........... 8-91 sra shift right arithmetic ................................ ................................ ........................... 8-92 stop stop operation (pseudo instruction) ................................ ................................ ..... 8-93 sub subtract ................................ ................................ ................................ ............. 8-94 swap swap ................................ ................................ ................................ .................. 8-95 sys system ................................ ................................ ................................ .............. 8-96 tm test multiple bits ................................ ................................ ................................ 8-97 xor exclusive or ................................ ................................ ................................ ...... 8-98
S3FB42F product ove rview 1- 1 1 product overview calmrisc overview the S3FB42F single-chip cmos microcontroller is designed for high performance using samsung's newest 8-bit cpu core, calmrisc. calmrisc is an 8-bit low power risc microcontroller. its basic architecture follows harvard style, that is, it has separate program memory and data memory. both instruction and data can be fetched simultaneously without causing a stall, using separate paths for memory access. represented below is the top block diagram of the calmrisc microcontroller. features cpu 8-bit calmrisc core dsp architecture (24 x 24-bit mac) memory code memory: 144k byte (72k word) half flash type memory data memory: 48k byte sram + 69k byte flash type memory stack size: maximu m 16 (word)-level. 65 i/o pins i/o: 59 pins input only: 6 pins 8-bit serial i/o interface 8-bit transmit/receive or 8-bit receive mode. lsb first or msb first transmission selectable. internal and external clock source. 8-bit basic timer & watchdog timer programmable basic timer 8-bit counter + wdt 3-bit counter 8 kinds of clock source overflow signal of 8-bit counter makes a basic timer interrupt. and control the oscillation warm-up time overflow signal of 3-bit counter makes a system reset. one 16-bit timer/counter programmable interval timer two 8-bit timer counter mode and one 16-bit timer counter mode, selectable by s/w one real time clock real time clock generation (0.5 or 1 second) buzzer signal generation (1, 2, 4 or 8 khz) rom code options basic timer counter clock source selecting reset value
product overview s3 fb42f 1- 2 features ( continued) i 2 c, i 2 s interface one- ch multi-master i 2 c controller two- ch sony/phillips i 2 s controller uart interface one full-duplex uart controller usb specification compliance (ver1.0, ver1.1) built in full speed transceiver support 1 device address and 4 endpoints. 1 control endpoint and 3 data endpoints one 16 bytes endpoint, one 32 bytes end point, and two 64 bytes end points. each data endpoint can be configurable as interrupt, bulk and isochronous. parallel port interface controller interrupt-based operation support ieee standard 1284 communication mode (compatibility, nibble, byte and ecp mode). automatic handshaking mode for any forward or reverse protocol with software enable/disable ssfdc (smart media tm card) interface control signals are operated by cpu instruction random number generator two ring oscillators linear feedback shifter register lfsr8/lfsr16 external interrupt 8 source (edge triggered 6 + level triggered 2) adc six 8-bit resolution channels and normal input two power-down modes idle mode: only cpu clock stop. stop mode: system clock and cpu clock stop. oscillation sources clock synthesizer (phase-locked loo p circuit) based on 32.768 khz cpu clock divider circuit (div by 1, 2, 4, 8, 16, 32, 64, 128) instruction execution times 33.3ns at fxx = 30 mhz when 1 cycle instruction 66.6ns at fxx = 30 mhz when 2 cycle instruction operating temperature - 40 c to 85 c operating voltage range 3.0 v to 3.6 v at 30 mhz package types 100-qfp, 100-tqfp
S3FB42F product ove rview 1- 3 bbus[7:0] 20 program memory address generation unit pc[19:0] hardware stack hs[0] hs[15] 8 8 r0 r3 r1 r2 alu abus[7:0] alul alur pa[19:0] pd[15:0] idl0 idl1 sr0 sr1 ilh ilx ill spr idh do[7:0] di[7:0] gpr data memory address generation unit da[15:0] 20 flag rbus tbh tbl figure 1-1. top block diagram
product overview s3 fb42f 1- 4 the calmrisc building blocks consist of: ? an 8-bit alu ? 16 general pur pose registers (gpr) ? 11 special purpose registers (spr) ? 16-level hardware stack ? program memory address generation unit ? data memory address generation unit 16 gpr's are grouped into four banks (bank0 to bank3) and each bank has four 8-bit registers (r0, r1, r2, and r3). spr's, designed for special purposes, include status registers, link registers for branch-link instructions, and data memory index registers. the data memory address generation unit provides the data memory address (denoted as da[15:0] in the top block diagram) for a data memory access instruction. data memory contents are accessed through di[7:0] for read operations and do[7:0] for write operations. the program memory address generation unit contains a program counter, pc[19:0], and supplies the program memory address through pa[19:0] and fetches the corresponding instruction through pd[15:0] as the result of the program memory access. calmrisc has a 16-level hardware stack for low power stack operations as well as a temporary storage area. calmrisc has a 3-stage pipeline as discribed below: instruction fetch (if) instruction decode/ data memory access (id/mem) execution/writeback (exe/wb) figure 1-2. calmrisc pipeline diagram as can be seen in the pipeline scheme, calmrisc adopts a register-memory instruction set. in other words, data memory where r is a gpr, can be one operand of an alu instruction as shown below: the first stage (or cycle) is instruction fetch stage (if for short), where the instruction pointed to by the program counter, pc[19:0] , is read into the instruction register (ir for short). the second stage is instruction decode and data memory access stage (id/mem for short), where the fetched instruction (stored in ir) is decoded and data memory access is performed, if necessary. the final stage is execute and write-back stage (exe/wb), where the required alu operation is executed and the result is written back into the destination registers. since calmrisc instructions are pipelined, the next instruction fetch is not postponed until the current instruction is completely finished, but is performed immediately after the current instruction fetch is done. the pipeline stream of instructions is illustrated in the following diagram.
S3FB42F product ove rview 1- 5 exe/wb if if if if if if if id/mem id/mem id/mem id/mem id/mem id/mem exe/wb exe/wb exe/wb exe/wb exe/wb i 1 i 2 i 3 i 4 i 6 i 5 figure 1-3. calmrisc pipeline stream diagram most calmrisc instructions are 1-word instructions, while same branch instructions such as "lcall" and "ljt" instructions are 2-word instructions. in figure 1-3, the instruction, i 4 , is a long branch instruction and it takes two clock cycles to fetch the instruction. as indicated in the pipeline stream, the number of clocks per instruction (cpi) is 1 except for long branches, which take 2 clock cycles per instruction.
product overview s3 fb42f 1- 6 i/o0-i/o7 p9.0-p9.5 p8.0-p8.3 p7.0-p7.7 p6.0-p6.7 p5.0-p5.5 calmrisc cpu flash memory 213-kbytes sram 48-kbytes dsp core mac 2424 osc & pll control rtc basic timer wdt ssfdc port 9 port 8 port 7 port 6 sio/uart iic/iis so, tx, sod sck, scl, soc si, rx, sda, soi usb dp, dm 8-bit a/d c avss adc0-adc5 avref ext interrupt int0-int5 int8-int9 ppic nstrobe/ninit busy/perror pd0-pd7 timer 0/1 tack/tbck taout port 5 p4.0-p4.3 port 4 p3.0-p3.7 port 3 p2.0-p2.7 port 2 p1.0-p1.4 port 1 p0.0-p0.7 port 0 random number gen. buz x in x out cp, cz fvco figure 1-4. block diagram
S3FB42F product ove rview 1- 7 v dd v ss nwe/p6.7 i/o0/p7.0 i/o1/p7.1 i/o2/p7.2 i/o3/p7.3 v dd v ss i/o4/p7.4 i/o5/p7.5 i/o6/p7.6 sdat /i/o7/p7.7 sclk /nslctin/p8.0 v dd /v dd v ss /v ss x i n x out v pp /test xt in xt o ut reset reset /reset v dd v ss n.c f vco /nstrobe/p8.1 nautofd/p8.2 cp cz v ss p6.6/nre p6.5/nwp p6.4/r/nb p6.3/ale p6.2/cle p6.1/nce1 p6.0/nce0 v dd av ss av ref p5.5/adc5/int5 p5.4/adc4/int4 p5.3/adc3/int3 p5.2/adc2/int2 p5.1/adc1/int1 p5.0/adc0/int0 p4.2/nce2 p4.1/int8 p4.0/int9 p9.6/mclk ninit/p8.3 ppd0/p0.0 ppd1/p0.1 ppd2/p0.2 ppd3/p0.3 ppd4/p0.4 ppd5/p0.5 ppd6/p0.6 ppd7/p0.7 v dd nack/p1.0 busy/p1.1 select/p1.2 perror/p1.3 nfault/p1.4 taclk/p2.0 tbclk/p2.1 taout/p2.2 buz/p2.3 rx/p2.4 v ss v ss v dd p9.5/sd1 p9.4/sclk1 p9.3/ws1 v ss v dd p9.2/sd0 p9.1/sclk0 p9.0/ws0 p3.7 p3.6 p3.5 p3.4/sda v ss v dd p3.3/scl p3.2/sck dm v ss v dd dp p3.1/so p3.0/si p2.7 p2.6 p2.5/tx v ss v dd S3FB42F (100-qfp) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 note: n.c means no - connection. figure 1-5. 100-qfp pin assignment
product overview s3 fb42f 1- 8 v ss v dd p6.6/nre p6.5/nwp p6.4/r/nb p6.3/ale p6.2/cle p6.1/nce1 p6.0/nce0 v dd av ss av ref p5.5/adc5/int5 p5.4/adc4/int4 p5.3/adc3/int3 p5.2/adc2/int2 p5.1/adc1/int1 p5.0/adc0/int0 p4.2/nce2 p4.1/int8 p4.0/int9 p9.6/mclk v ss v ss v dd cp cz v ss ninit/p8.3 ppd0/p0.0 ppd1/p0.1 ppd2/p0.2 ppd3/p0.3 ppd4/p0.4 ppd5/p0.5 ppd6/p0.6 ppd7/p0.7 v dd nack/p1.0 busy/p1.1 select/p1.2 perror/p1.3 nfault/p1.4 tack/p2.0 tbck/p2.1 taout/p2.2 buz/p2.3 rx/p2.4 v dd v ss p9.5/sd1 p9.4/sclk1 p9.3/ws1 v ss v dd p9.2/sd0 p9.1/sclk0 p9.0/ws0 p3.7 p3.6 p3.5 p3.4/sda v ss v dd p3.3/scl p3.2/sck dm v ss v dd dp p3.1/so p3.0/si p2.7 p2.6 p2.5/tx nwe/p6.7 i/o0/p7.0 i/o1/p7.1 i/o2/p7.2 i/o3/p7.3 v dd v ss i/o4/p7.4 i/o5/p7.5 i/o6/p7.6 sdat /i/o7/p7.7 sclk /nslctin/p8.0 v dd /v dd v ss /v ss x in x out v pp /test xt i n xt o ut reset v dd v ss n.c f vco /nstrobe/p8.1 nautofd/p8.2 S3FB42F (100-tqfp-1414c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 note: n.c means no - connection figure 1-6. 100-tqfp pin assignment
S3FB42F product ove rview 1- 9 pin description table 1-1. S3FB42F pin descriptions (100-tqfp) pin name pin type pin description circuit type pin number share pins p0.0-p0.7 i/o i/o port with bit programmable pins; input or output mode selected by software; alternately can be used as parallel port data bus pins, ppd0-ppd7. p0.0/ppd0-p0.7/ppd7: parallel port data bus 1 30-37 (32-39) ppd0- ppd7 p1.0-p1.4 i/o i/o port with bit programmable pins; push-pull output mode is selected by software; alternately can be used as parallel port control bus pins, nack, busy, select, perror and nfault pin. p1.0/nack: not parallel port acknowledge. p1.1/busy: parallel port busy. p1.2/select: parallel port select. p1.3/perror: parallel port paper error p1.4/nfault: not parallel port fault. 1 39-43 (41-45) nack- nfault p2.0-p2.7 i/o i/o port with bit programmable pins; input and output mode are selected by software; alternately can be used as taclk, tbclk, taout, buz, rx and tx. p2.0/ taclk: timer 0 clock or capture input p2.1/tbclk: timer 1 clock input p2.2/taout: timer 2 capture input or, pwm or toggle output p2.3/buz: buzzer output p2.4/rx: receive input in uart p2.5/tx: transmit output in uart p2.6: normal input/output pin p2.7: normal input/output pin 4 44-48, 51-53 (46-50, 53-55) taclk- tx p3.0-p3.7 i/o i/o port with bit programmable pins; input or output mode selected by software; alternately can be used as si, so, sck, scl and sda. n-channel open drains are configurable. p3.0/si: serial data input pin in sio(spi) p3.1/so: serial data output pin in sio(spi) p3.2/sck: serial clock pin in sio(spi) p3.3/scl: serial clock pin in i 2 c p3.4/sda: serial data pin in i 2 c p3.5: normal input/output pin p3.6: normal input/output pin p3.7: normal input/output pin 5 54-55, 60-61, 64-67 (56-57, 62-63, 66-69) si-sda note: parentheses indicate pin number for 100-qfp package.
product overview s3 fb42f 1- 10 table 1 - 1. S3FB42F pin descriptions (100-tqfp) (continued) pin name pin type pin description circuit type pin number share pins p4.0-p4.2 i/o i/o port with bit programmable pins; input and output mode are selected by software; p4.0-p4.1 can be used as inputs for external interrupts int9-int8. (with noise filter) and assigned pull-up by software; alternately p4.2 can be used as ce2 for smartmedia chip select signal. p4.0/int9: external interrupt 9 input p4.1 /int8: external interrupt 8 input p4.2/ ce2 : normal in/output pin 6, 3 80-82 (82-84) int9-int8 ce2 p5.0-p5.5 i input port with bit programmable pins; input or adc input mode selected by software; software assignable pull-up; port 5 can be used as inputs for external interrupts int0-int5 or adc block. p5.0/int0/adc0: ext interrupt 0 or adc0 input p5.1/int1/adc1: ext interrupt 1 or adc1 input p5.2/int2/adc2: ext interrupt 2 or adc2 input p5.3/int3/adc3: ext interrupt 3 or adc3 input p5.4/int4/adc4: ext interrupt 4 or adc4 input p5.5 /int5/adc5: ext interrupt 5 or adc5 input 7 83-88 (85-90) int0/adc0- int5/adc5 p6.0-p6.7 i/o i/o port with bit programmable pins; alternately port 6 can be used as ce0 , ce1 , cle, ale, we , wp, re and r/ b for smartmedia control signal. p6.0/ ce0 : chip select strobe output 0 for sm. p6.1/ ce1 : chip select strobe output 1 for sm. p6.2/cle: command latch enable output for sm. p6.3/ale: address latch enable output for sm. p6.4/r/ b : ready and busy status input for sm. p6.5/wp: write protect output for sm. p6.6/ re : read enable strobe output for sm. p6.7/ we : write enable strobe output for sm. 1, 2 92-98, 1 (94-100, 3) ce0 - we p7.0-p7.7 i/o i/o port with bit programmable pins; alternately port 7 can be used as i/o port for smartmedia control signal. p7.0/i/o0-p7.7/i/o7: i/o port for smartmedia control signal. 1 2-5, 8-11 (4-7, 10-13) i/o0-i/o7 note: parentheses indicate pin number for 100-qfp package.
S3FB42F product ove rview 1- 11 table 1 - 1. S3FB42F pin descriptions (100-tqfp) (continued) pin name pin type pin description circuit type pin number share pins p8.0-p8.3 i/o i/o port with bit programmable pins; alternately can be used as parallel port control bus pins, nslctin, nstrobe, nautofd and ninit pin. p8.0/nslctin: not select information input. p8.1/nstrobe/f vco : not strobe input or f vco output p8.2/nautofd: not auto-feed input p8.3/ninit: not parallel port initialization. 4 12, 24, 25, 29 (14, 26, 27, 31) nslctin- ninit p9.0-p9.6 i/o i/o port with bit programmable pins; alternately can be used as serial data interface pins, ws0, sclk0, sd0, ws1, sclk1, sd1 and mclk. p9.0/ws0: word select pin in i 2 s0 p9.1/sclk0: bit serial clock pin in i 2 s0. p9.2/sd0: serial data pin in i 2 s0 p9.3/ws1: word select pin in i 2 s1. p9.4/sclk1: bit serial clock pin in i 2 s1. p9.5/sd1: serial data pin in i 2 s1. p9.6/mclk: master clock pin in i 2 s0. 4 68-70, 73-76, 79 (70-72, 75-77, 79) ws0- mclk dm i/o only be used usb transceive/receive port ? 59 (61) ? dp i/o only be used usb transceive/receive port ? 56 (58) ? v dd, v dd ? power supply ? 6, 13, 21, 26, 38, 49, 57, 62, 71, 76, 91, 99 (1, 8, 15, 23, 28, 40, 52, 59, 64, 73, 78, 93) ? v ss, v ss ? ground ? 7, 14, 22, 27, 28, 50, 58, 63, 72, 77, 78, 100 (2, 9, 16, 24, 29, 30, 51, 60, 65, 74, 79, 80) ? note: parentheses indicate pin number for 100-qfp package.
product overview s3 fb42f 1- 12
S3FB42F product ove rview 1- 13 table 1 - 1. S3FB42F pin descriptions (100-tqfp) (continued) pin name pin type pin description circuit type pin number share pins x in, x out ? crystal, ceramic oscillator signal for pll reference frequency (for external clock input, use x in and input x in 's reverse phase to x out ) ? 15, 16 (17, 18) ? xt in, xt out ? crystal, ceramic oscillator (for external clock input, use xt in and input xt in 's reverse phase to xt out ) ? 18, 19 (20,21) ? cp, cz ? low pass filter circuit for pll ? 26, 27 (28, 29) ? test i test signal input 9 17 (19) ? reset i reset signal 8 20 (22) ? av ref , av ss ? power supply pin and ground pin for a/d converter. ? 89, 90 (91, 92) ? sdat i/o serial data in/output pin for serial program block 1 11 (13) p7.7 sclk i serial clock input pin for serial program block 1 12 (14) p8.0 v dd ? power supply pin for serial program block ? 13 (15) ? v ss ? ground pin for serial program block ? 14 (16) ? v pp ? flash cell power supply pin or mode selection pin for serial program block ? 17 (19) test reset i reset pin for serial program block 8 20 (22) reset note: parentheses indicate pin number for 100-qfp package.
product overview s3 fb42f 1- 14 pin circuit diagrams v dd in/out m u x v ss select port data alternative signal output disable alternative input normal input data figure 1-7. pin circuit type 1 (port 0, p1.0-p1.4, p6.0-p6.5, and port 7) v dd in/out m u x v ss select port data alternative signal output disable alternative input normal input pull-up resistor v dd pull-up enable data figure 1-8. pin circuit type 2 (p6.6 and p6.7)
S3FB42F product ove rview 1- 15 v dd in/out m u x v ss select port data alternative signal output disable alternative input normal input pull-up resistor v dd pull-up enable data figure 1-9. pin circuit type 3 (p4.2)
product overview s3 fb42f 1- 16 v dd in/out m u x v ss select port data alternative signal output disable alternative input normal input data figure 1-10. pin circuit type 4 (port 2, port 8, and port 9) v dd m u x v ss select port data alternative signal output disable alternative input normal input pull-up resistor v dd pull-up enable data open-drain in/out figure 1-11. pin circuit type 5 (port 3)
S3FB42F product ove rview 1- 17 v dd in/out v ss output disable input external interrupt input pull-up resistor v dd pull-up enable noise filter data figure 1-12. pin circuit type 6 (p4.0, and p4.1) normal input mode normal input interrupt input noise filter in pull-up resistor v dd pull-up resistor enable v ref a/d c logic + - figure 1-13. pin circuit type 7 (port 5)
product overview s3 fb42f 1- 18 in v dd figure 1-14. pin circuit type 8 ( reset reset ) in figure 1-15. pin circuit type 9 (test)
S3FB42F product ove rview 1- 19 notes
S3FB42F address spa ce 2- 1 2 address space overview calmrisc has 20-bit program address lines, pa[19:0] , which supports up to 1m-word program memory. the 1m-word program memory space is divided into 256 pages and each page is 4k words long as shown in the next page. the upper 8 bits of the program counter, pc[19:12], points to a specific page and the lower 12 bits, pc[11:0], specify the offset address of the page. calmrisc also has 16-bit data memory address lines, da[15:0], which supports up to 64k-byte data memory. the 64k-byte data memory space is divided into 256 pages and each page has 256 bytes. the upper 8 bits of the data address, da[15:8], points to a specific page and the lower 8 bits, da[7:0], specify the offset address of the page. S3FB42F has 72k-word (144k-byte) flash rom type program memory, 34.5k-word (69k-byte) flash rom type data memory and 48k-byte ram type data memory. memory configuration in calmrisc side data memory: total size - 117k bytes (flash rom type, 69k bytes and sram type, 48k bytes) code memory: total size - 144k bytes (flash rom type, 144k bytes) memory configuration in mac-2424 side data memory: x-memory area - sram, 12k lwords (36k bytes) y-memory area - sram, 4k lwords (12k bytes) and flash rom, 23k lwords (69k bytes) code memory: total size - 72k words (flash rom type, 144k byte) memory type flash rom: 213k bytes sram: 48k bytes
address space s3fb4 2f 2- 2 program memory (rom) 00h fffh 18 page 72k-word (144k-byte) 00h fffh 4k-word (8k-byte) 16-bit 00000h 11fffh 00020h 0001fh vector and option area flash rom memory (4k-word x 18 page = 72k-word) 72k-word code momory ~ ~ ~ ~ figure 2-1. flash memory (code memory area) from 00000h to 00004h addresses are used for the vector address of exceptions, and 0001eh, 0001fh are used for the option only. aside from these addresses others are reserved in the vector and option area. program memory area from the address 00020h to 11ffh can be used for normal programs. S3FB42F's program memory is 72k words (144k bytes).
S3FB42F address spa ce 2- 3 data memory organization the total data memory bank address space is 64 k-byte, addressed by da[15:0], which is also divided into 256 pages, each page consists of 256 bytes as shown below. S3FB42F has 2 data bank memory. 64k-byte ffh 00h 8-bit bank 0 00h ffh 256 pages ffh 00h 128 pages (x-memory) 128 pages (y-memory) 8-bit bank 1 256-byte ffh 256-byte figure 2-2. data memory map
address space s3fb4 2f 2- 4 sram sram blank 8000h 7fffh 4000h 3fffh 0100h 12k-byte page 144 page 128 page 63 page 16 bank 1 sram blank 9fffh 8000h 7fffh 2000h 1fffh 0100h 8k-byte 24k-byte 7.75k-byte page 128 page 127 page 1 bank 0 y-memory x-memory sram page 0 00ffh page address i/o area 4k-byte blank 8fffh 1000h page 31 page 32 ffffh c000h b800h d000h 16kb 18kb 12kb 2 1 yrom bank 0 flash rom ffffh e000h dc00h e800h 8kb 9kb 6kb 2 1 yrom bank 0 flash rom 0000h mac access unit, lword = 3-byte long. (1-byte to bank 1, and 2-byte of bank 0) bank 0 xm = 2000h + mac offset x 2 ym = 8000h + mac offset x 2 bank 1 xm = 1000h + mac offset ym = 8000h + mac offset figure 2-3. data memory map in calmrisc side
S3FB42F address spa ce 2- 5 4000h 3fffh 1000h 0fffh 0000h 4k-lword 12k-lword sram y-memory x-memory sram blank 7fffh 6000h 5c00h 6800h 2 1 yrom bank 0 flash rom 6k-lw 9k-lw 8k-lw where, lword: 3-byte long. (1-byte of bank 1, and 2-byte of bank 0) xm mac offset = mac address - 1000h ym mac offset = mac address - 4000h 4fffh 4k-lword figure 2-4. data memory map in mac-2424 side
address space s3fb4 2f 2- 6 sram (24kb) 9fffh 8000h 7fffh 2000h sram (8kb) y-memory x-memory bank 1 bank 0 page 0 00ffh 0000h 8000h 3fffh 1000h calmrisc memory space mac2424 memory space e000h dc00h e800h flash rom (8kb) 9kb 6kb 8fffh ffffh c000h b800h flash rom (16kb) 18kb d000h 12kb 3fffh 1000h sram (12k-lword) 5fffh 4fffh 4000h 5000h blank (4k-lword) sram (4k-lword) 7fffh 6000h 5c00h flash rom (8k-lword) 9k-lw 6800h 6k-lw sram (4kb) sram (12kb) i/o area figure 2-5. data memory map
S3FB42F registers 3- 1 3 registers overview the registers of calmrisc are grouped into 2 parts: general purpose registers and special purpose registers. table 3-1. general and special purpose registers registers mnemonics description reset value general purpose registers (gpr) r0 general r egister 0 unknown r1 general r egister 1 unknown r2 general r egister 2 unknown r3 general r egister 3 unknown special purpose registers (spr) group 0 (spr0) idl0 l ower byte of i n d ex register 0 unknown idl1 l ower byte of i n d ex register 1 unknown idh h igher byte of i n d ex register unknown sr0 s tatus r egister 0 00h group 1 (spr1) ilx i nstruction pointer l ink register for e x tended byte unknown ilh i nstruction pointer l ink register for h igher byte unknown ill i nstruction pointer l ink register for l ower byte unknown sr1 s tatus r egister 1 unknown gpr ? s can be used in most instructions such as alu instructions, stack instructions, load instructions, etc (see the instruction set sections). from the programming standpoint, they have almost no restriction whatsoever. calmrisc has 4 banks of gpr ? s and each bank has 4 registers, r0, r1, r2, and r3. hence, 16 gpr ? s in total are available. the gpr bank switching can be done by setting an appropriate value in sr0[4:3] (see sr0 for details). the alu operations between gpr ? s from different banks are not allowed. spr ? s are designed for their own dedicated purposes. they have some restrictions in terms of instructions that can access them. for example, direct alu operations cannot be performed on spr ? s. however, data transfers between a gpr and an spr are allowed and stack operations with spr ? s are also possible (see the instruction sections for details).
registers s3f b42f 3- 2 index registers: idh, idl0 and idl1 idh in concatenation with idl0 (or idl1) forms a 16-bit data memory address. note that calmrisc ? s data memory address space is 64k bytes (addressable by 16-bit addresses). basically, idh points to a page index and idl0 (or idl1) corresponds to an offset of the page. like gpr ? s, the index registers are 2-way banked. there are 2 banks in total, each of which has its own index registers, idh, idl0 and idl1. the banks of index registers can be switched by setting an appropriate value in sr0[2] (see sr0 for details). normally, programmers can reserve an index register pair, idh and idl0 (or idl1), for software stack operations. link registers: ilx, ilh and ill the link registers are specially designed for link-and-branch instructions (see lnk and lret instructions in the instruction sections for details). when an lnk instruction is executed, the current pc[19:0] is saved into ilx, ilh and ill registers, i.e., pc[19:16] into ilx[3:0], pc[15:8] into ilh [7:0], and pc[7:0] into ill[7:0], respectively. when an lret instruction is executed, the return pc value is recovered from ilx, ilh, and ill, i.e., ilx[3:0] into pc[19:16], ilh[7:0] into pc[15:8] and ill[7:0] into pc[7:0], respectively. these registers are used to access program memory by ldc/ldc+ instructions. when an ldc or ldc+ instruction is executed, the (code) data residing at the program address specified by ilx:ilh:ill will be read into tbh:tbl. ldc+ also increments ill after accessing the program memory. there is a special core input pin signal, np64kw , which is reserved for indicating that the program memory address space is only 64 k word. by grounding the signal pin to zero, the upper 4 bits of pc, pc[19:16], is deactivated and therefore the upper 4 bits , pa[19:16], of the program memory address signals from calmrisc core are also deactivated. by doing so, power consumption due to manipulating the upper 4 bits of pc can be totally eliminated (see the core pin description section for details). from the programmer ? s standpoint, when np64kw is tied to the ground level, then pc[19:16] is not saved into ilx for lnk instructions and ilx is not read back into pc[19:16] for lret instructions. therefore, ilx is totally unused in lnk and lret instructions when np64kw = 0.
S3FB42F registers 3- 3 status register 0: sr0 sr0 is mainly reserved for system control functions and each bit of sr0 has its own dedicated function. table 3-2. status register 0: sr0 flag name bit description reset value eid 0 data memory page selection in direct addressing 1 ie 1 global interrupt enable x idb 2 index register banking selection 0 grb[1:0] 4,3 gpr bank selection 00 exe 5 stack overflow/underflow exception enable x ie0 6 interrupt 0 enable x ie1 7 interrupt 1 enable x sr0[0] (or eid) selects which page index is used in direct addressing. if eid = 0, then page 0 (page index = 0) is used. otherwise ( eid = 1), idh of the current index register bank is used for page index. sr0[1] (or ie) is the global interrupt enable flag. as explained in the interrupt/exception section, calmrisc has 3 interrupt sources (non- maskable interrupt, interrupt 0, and interrupt 1) and 1 stack exception. both interrupt 0 and interrupt 1 are masked by setting sr0[1] to 0 (i.e., ie = 0). when an interrupt is serviced, the global interrupt enable flag ie is automatically cleared. the execution of an iret instruction (return from an interrupt service routine) automatically sets ie = 1. sr0[2] (or idb) and sr0[4:3] (or grb[1:0]) selects an appropriate bank for index registers and gpr?s, respectively as shown below: r3 r0 r2 r1 r3 r0 r2 r1 r3 r0 r2 r1 r3 r0 r2 r1 idh idl0 idl1 idh idl0 idl1 bank 0 bank 1 bank 2 bank 3 11 10 01 00 grb [1:0] 0 1 idb figure 3-1. bank selection by setting of grb bits and idb bit sr0[5] (or exe) enables the stack exception, that is, the stack overflow/underflow exception. if exe = 0, the stack exception is disabled. the stack exception can be used for program debugging in the software development stage. sr0[6] (or ie0) and sr0[7] (or ie1) are enabled, by setting them to 1. even though ie0 or ie1 are enabled, the interrupts are ignored (not serviced) if the global interrupt enable flag ie is set to 0.
registers s3f b42f 3- 4 status register 1: sr1 sr1 is the register for status flags such as alu execution flag and stack full flag. table 3-3. status register 1: sr1 flag name bit description c 0 carry flag v 1 overflow flag z 2 zero flag n 3 negative flag sf 4 stack full flag ? 5,6,7 reserved sr1[0] (or c) is the carry flag of alu executions. sr1[1] (or v) is the overflow flag of alu executions. it is set to 1 if and only if the carry-in into the 8-th bit position of addition/subtraction differs from the carry-out from the 8-th bit position. sr1[2] (or z) is the zero flag, which is set to 1 if and only if the alu result is zero. sr1[3] (or n) is the negative flag. basically, the most significant bit (msb) of alu results becomes n flag. note a load instruction into a gpr is considered an alu instruction. however, if an alu instruction touches the overflow flag (v) like add, sub, cp, etc , n flag is updated as exclusive-or of v and the msb of the alu result. this implies that even if an alu operation results in overflow, n flag is still valid. sr1[4] (or sf) is the stack overflow flag. it is set when the hardware stack is overflowed or underflowed. programmers can check if the hardware stack has any abnormalities by the stack exception or testing if sf is set (see the hardware stack section for great details). note: when an interrupt occur sr0 and sr1 are not saved by hardware, so the sr1 register values must be saved by software.
S3FB42F memory map 4- 1 4 memory map overview to support the control of peripheral hardware, the address for peripheral control registers are memory-mapped to page 0 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. in this section, detailed descriptions of the S3FB42F control registers are presented in an easy-to-read format. you can use this section as a quick-reference source when writing application programs. this memory area can be accessed with the whole method of data memory access. ? if sr0 bit 0 is "0" then the accessed register area is always page 0. ? if sr0 bit 0 is "1" then the accessed register page is controlled by the proper idh register's value. so if you want to access the memory map area, clear the sr0.0 and use the direct addressing mode. this method is used for most cases. this control register is divided into five areas. here, the system control register area is same in every device. ffh control register system control register area port data register area peripheral control register (1 x 16 or 2 x 8) reserved area (1 x 16 or 2 x 8) specially in S3FB42F the area from 60h-7fh can be used for external device. so if you want to use some peripheral externally, then you can control that by means of this special area. peripheral control register (4 x 8) port control register area (4 x 8) 80h 7fh 70h 6fh 40h 3fh 20h 1fh 10h 0fh 00h standard exhortative area standard area ~ ~ ~ ~ figure 4-1. memory map area
memory map S3FB42F 4- 2 table 4-1. registers register name mnemonic decimal hex reset r/w location 1ah-1fh are not mapped port 9 data register p9 25 19h 00h r/w port 8 data register p8 24 18h 00h r/w port 7 data register p7 23 17h 00h r/w port 6 data register p6 22 16h 00h r/w port 5 data register p5 21 15h 00h r port 4 data register p4 20 14h 00h r/w port 3 data register p3 19 13h 00h r/w port 2 data register p2 18 12h 00h r/w port 1 data register p1 17 11h 00h r/w port 0 data register p0 16 10h 00h r/w watchdog timer control register wdtcon 15 0fh 00h r/w watchdog timer enable register wdten 14 0eh 00h r/w basic timer counter btcnt 13 0dh 00h r basic timer control register btcon 12 0ch 00h r/w interrupt id register 1 iir1 11 0bh ? r/w interrupt priority register 1 ipr1 10 0ah 00h r/w interrupt mask register 1 imr1 9 09h 00h r/w interrupt request register 1 irq1 8 08h ? r/w interrupt id register 0 iir0 7 07h ? r/w interrupt priority register 0 ipr0 6 06h 00h r/w interrupt mask register 0 imr0 5 05h 00h r/w interrupt request register 0 irq0 4 04h - r/w oscillator control register osccon 3 03h 00h r/w power control register (stop or idle mode) pcon 2 02h 04h r/w locations 00h-01h are not mapped notes: 1. '?' means underlined. 2. if you want to clear the bit of irqx, then write the number which you want to clear to iirx. for example, when clear irq0.4 then ld r0, #04h and ld iir0, r0.
S3FB42F memory map 4- 3 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w port 0 control register p0con 32 20h 00h r/w port 1 control register p1con 33 21h 00h r/w port 2 control register low p2conl 34 22h 00h r/w port 2 control register high p2conh 35 23h 30h r/w port 3 control register low p3conl 36 24h 00h r/w port 3 control register high p3conh 37 25h 00h r/w port 3 pull-up resistor p3pur 38 26h 00h r/w location 27h is not mapped port 5 control register p5con 40 28h 00h r/w port 5 pull-up resistor p5pur 41 29h 00h r/w port 5 int. control register p5intcon 42 2ah 00h r/w port 5 int. mode register low p5intmodl 43 2bh 00h r/w port 5 int. mode register high p5intmodh 44 2ch 00h r/w external int. pending register eintpnd 45 2dh 00h r/w locations 2e-2fh are not mapped port 4 control register p4con 48 30h 00h r/w port 4 int. control register p4intcon 49 31h 00h r/w port 4 int. mode register p4intmod 50 32h 00h r/w location 33h is not mapped port 6 control register p6con 52 34h 00h r/w port 7 control register p7con 53 35h 00h r/w port 8 control register p8con 54 36h 00h r/w port 9 control register p9con 55 37h 00h r/w locations 38h-3fh are not mapped timer a control register tacon 64 40h 00h r/w timer a data register tadata 65 41h 00h r/w timer a counter tacnt 66 42h ? r location 43h is not mapped timer b control register tbcon 68 44h 00h r/w timer b data register tbdata 69 45h 00h r/w timer b counter tbcnt 70 46h ? r locations 47h-4bh are not mapped watch timer control register wtcon 76 4ch 00h r/w locations 4dh-4fh are not mapped
memory map S3FB42F 4- 4 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w serial i/o control register siocon 80 50h 00h r/w serial i/o pre-scale register siops 81 51h 00h r/w serial i/o data register siodata 82 52h 00h r/w location 53h is not mapped a/d c control register adcon 84 54h 00h r/w a/d conversion result data register addata 85 55h ? r locations 56h-57h are not mapped iis control register 0 iiscon0 88 58h 00h r/w iis mode register 0 iismode0 89 59h 00h r/w iis buffer pointer register 0 iisptr0 90 5ah 00h r/w location 5bh is not mapped iis control register 1 iiscon1 92 5ch 00h r/w iis mode register 1 iismode1 93 5dh 00h r/w iis buffer pointer register 1 iisptr1 94 5eh 00h r/w location 5fh is not mapped parallel port data register ppdata 96 60h 00h r/w parallel port command data register ppcdata 97 61h 00h r/w parallel port status control register ppscon 98 62h 08h r/w parallel port status register ppstat 99 63h 3fh r/w parallel port control register low ppconl 100 64h 00h r/w parallel port control register high ppconh 101 65h 00h r/w parallel port int. control register low ppintconl 102 66h 00h r/w parallel port int. control register high ppintconh 103 67h 00h r/w parallel port int. pending register low ppintpndl 104 68h 00h r/w parallel port int. pending register high ppintpndh 105 69h 00h r/w parallel port ack. width data register ppackd 106 6ah xxh r/w locations 6bh-6fh are not mapped smartmedia control register smcon 112 70h 00h r/w ecc counter eccnt 113 71h 00h r/w ecc data register low eccl 114 72h 00h r/w ecc data register high ecch 115 73h 00h r/w ecc data register extension eccx 116 74h 00h r/w ecc result register low eccrstl 117 75h 00h r/w
S3FB42F memory map 4- 5 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w ecc result register high eccrsth 118 76h 00h r/w ecc clear register eccclr 119 77h ? w flash memory control register fmcon 120 78h 00h r/w location 79h is not mapped flash user programming serial clock register fsclk 122 7ah 00h r/w flash user programming serial data register fsdat 123 7bh 00h r/w locations 7ch-7fh are not mapped function address register funaddr 128 80h 00h r power management register pwrman 129 81h 00h r frame number lo register framelo 130 82h 00h r frame number hi register framehi 131 83h 00h r interrupt pending register intreg 132 84h 00h r/w interrupt enable register intena 133 85h 00h r/w endpoint index register epindex 134 86h 00h r/w locations 87h-88h are not mapped endpoint direction register epdir 137 89h 00h w in control status register incsr 138 8ah 00h r/w out control status register outcsr 139 8bh 00h r/w in max packet register inmaxp 140 8ch 00h r/w out max packet register outmaxp 141 8dh 00h r/w write counter lo register wrtcntlo 142 8eh 00h r/w write counter hi register wrtcnthi 143 8fh 00h r/w endpoint 0 fifo register ep0fifo 144 90h 00h r/w endpoint 1 fifo register ep1fifo 145 91h 00h r/w endpoint 2 fifo register ep2fifo 146 92h 00h r/w endpoint 3 fifo register ep3fifo 147 93h 00h r/w
memory map S3FB42F 4- 6 table 4-1. registers (continued) register name mnemonic decimal hex reset r/w control register for random number generator rancon 168 a8h ? r/w 8-bit linear feedback shift register lfsr8 169 a9h ? r/w 16-bit linear feedback shift register lower lfsr16l 170 aah ? r/w 16-bit linear feedback shift register higher lfsr16h 171 abh ? r/w pll data register lower plldatal 172 ach ? r/w pll data register higher plldatah 173 adh ? r/w pll control register pllcon 174 aeh 0 r/w location afh is not mapped uart line control register lcon 176 b0h 00h r/w uart control register ucon 177 b1h 00h r/w uart status register ussr 178 b2h c0h r uart transmit buffer register tbr 179 b3h ? w uart receive buffer register rbr 180 b4h ? r uart band rate divisor register ubrdr 181 b5h 00h r/w uart interrupt pending register upend 182 b6h 00 r/w location bfh is not mapped iic control register iiccon 184 b8h 00h r/w iic status register iicsr 185 b9h 00h r/w iic data register iicdata 186 bah ? r/w iic address register iicaddr 187 bbh ? r/w iic pre- scaler register iicps 188 bch ffh r/w iic pre- scaler count register for test iiccnt 189 bdh ? r locations beh-bfh is not mapped 64-byte iis i/o buffer buf64 c0h ffh ? r/w
S3FB42F hardware st ack 5- 1 5 hardware stack overview the hardware stack in calmrisc has two usages: ? to save and restore the return pc[19:0] on lcall, calls, ret, and iret instructions. ? temporary storage space for registers on push and pop instructions. when pc[19:0] is saved into or restored from the hardware stack, the access should be 20 bits wide. on the other hand, when a register is pushed into or popped from the hardware stack, the access should be 8 bits wide. hence, to maximize the efficiency of the stack usage, the hardware stack is divided into 3 parts: the extended stack bank (xstack, 4-bits wide), the odd bank (8-bits wide), and the even bank (8-bits wide). 3 0 7 0 7 0 level 0 level 1 level 2 level 14 level 15 xstack odd bank even bank hardware stack 0 1 5 stack pointer sptr [5:0] odd or even bank selector stack level pointer figure 5-1. hardware stack
hardware stack s3fb 42f 5- 2 the top of the stack (tos) is pointed to by a stack pointer, called sptr[5:0] . the upper 5 bits of the stack pointer, sptr[5:1], points to the stack level into which either pc[19:0] or a register is saved. for example, if sptr[5:1] is 5h or tos is 5, then level 5 of xstack is empty and either level 5 of the odd bank or level 5 of the even bank is empty. in fact, sptr[0], the stack bank selection bit, indicates which bank(s) is empty. if sptr[0] = 0, both level 5 of the even and the odd banks are empty. on the other hand, if sptr[0] = 1, level 5 of the odd bank is empty, but level 5 of the even bank is occupied. this situation is well illustrated in the figure below. level 0 level 1 level 2 level 15 xstack odd bank even bank 0 1 5 sptr [5:0] bank selector stack level pointer level 3 level 4 level 5 0 0 1 1 0 0 level 0 level 1 level 2 level 15 xstack odd bank even bank 0 1 5 sptr [5:0] bank selector stack level pointer level 3 level 4 level 5 0 0 1 1 1 0 figure 5-2. even and odd bank selection example as can be seen in the above example, sptr[5:1] is used as the hardware stack pointer when pc[19:0] is pushed or popped and sptr[5:0] as the hardware stack pointer when a register is pushed or popped. note that xstack is used only for storing and retrieving pc[19:16]. let us consider the cases where pc[19:0] is pushed into the hardware stack (by executing lcall/calls instructions or by interrupts/exceptions being served) or is retrieved from the hardware stack (by executing ret/iret instructions). regardless of the stack bank selection bit ( sptr[0]), tos of the even bank and the odd bank store or return pc[7:0] or pc[15:8], respectively. this is illustrated in the following figures.
S3FB42F hardware st ack 5- 3 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector stack level pointer level 5 0 1 1 0 0 0 level 6 0 pc[7:0] stack level pointer level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 1 1 0 0 0 level 6 0 by executing ret, iret by executing call, calls or interrupts/exceptions stack level pointer stack level pointer pc[19:16] pc[15:8] pc[15:8] pc[19:16] pc[7:0] by executing ret, iret by executing call, calls or interrupts/exceptions figure 5-3. stack operation with pc [19:0] as can be seen in the figures, when stack operations with pc[19:0] are performed, the stack level pointer sptr[5:1] ( not sptr[5:0]) is either incremented by 1 (when pc[19:0] is pushed into the stack) or decremented by 1 (when pc[19:0] is popped from the stack). the stack bank selection bit ( sptr[0]) is unchanged. if a calmrisc core input signal np64kw is 0, which signifies that only pc[15:0] is meaningful, then any access to xstack is totally deactivated from the stack operations with pc. therefore, xstack has no meaning when the input pin signal, np64kw , is tied to 0. in that case, xstack doesn ? t have to even exist. as a matter of fact, xstack is not included in calmrisc core itself and it is interfaced through some specially reserved core pin signals ( npush, nstack , xhsi[3:0] , xsho[3:0] ), if the program address space is more than 64k words (see the core pin signal section for details). with regards to stack operations with registers, a similar argument can be made. the only difference is that the data written into or read from the stack are a byte. hence, the even bank and the odd bank are accessed alternately as shown below.
hardware stack s3fb 42f 5- 4 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector stack level pointer level 5 1 0 1 1 0 0 level 6 0 register stack level pointer level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 1 0 1 1 0 0 level 6 0 level 0 level 15 xstack odd bank even bank 1 5 sptr [5:0] bank selector level 5 0 1 1 0 0 0 level 6 0 register pop register push register stack level pointer stack level pointer pop register push register figure 5-4. stack operation with registers when the bank selection bit ( sptr[0]) is 0, then the register is pushed into the even bank and the bank selection bit is set to 1. in this case, the stack level pointer is unchanged. when the bank selection bit ( sptr[0]) is 1, then the register is pushed into the odd bank, the bank selection bit is set to 0, and the stack level pointer is incremented by 1. unlike the push operations of pc[19:0], any data are not written into xstack in the register push operations. this is illustrated in the example figures. when a register is pushed into the stack, sptr[5:0] is incremented by 1 ( not the stack level pointer sptr[5:1]). the register pop operations are the reverse processes of the register push operations. when a register is popped out of the stack, sptr[5:0] is decremented by 1 ( not the stack level pointer sptr[5:1]). hardware stack overflow/underflow happens when the msb of the stack level pointer, sptr[5], is 1. this is obvious from the fact that the hardware stack has only 16 levels and the following relationship holds for the stack level pointer in a normal case. suppose the stack level pointer sptr[5:1] = 15 (or 01111b in binary format) and the bank selection bit sptr[0] = 1. here if either pc[19:0] or a register is pushed, the stack level pointer is incremented by 1. therefore, sptr[5:1] = 16 (or 10000b in binary format) and sptr[5] = 1, which implies that the stack is overflowed. the situation is depicted in the following.
S3FB42F hardware st ack 5- 5 level 0 level 15 xstack odd bank even bank push register 1 1 1 1 1 0 1 5 sptr [5:0] 0 level 1 level 14 level 0 level 15 xstack odd bank even bank 0 0 0 0 0 1 1 5 sptr [5:0] 0 level 1 level 14 level 0 level 15 1 0 0 0 0 1 1 5 sptr [5:0] 0 level 1 level 14 xstack odd bank even bank push pc [19:0] register pc[19:16] pc[15:8] pc[7:0] figure 5-5. stack overflow the first overflow happens due to a register push operation. as explained earlier, a register push operation increments sptr[5:0] (not sptr[5:1]) , which results in sptr[5] = 1, sptr[4:1] = 0 and sptr[0] = 0. as indicated by sptr[5] = 1, an overflow happens. note that this overflow doesn ? t overwrite any data in the stack. on the other hand, when pc[19:0] is pushed, sptr[5:1] is incremented by 1 instead of sptr[5:0], and as expected, an overflow results. unlike the first overflow, pc[7:0] is pushed into level 0 of the even bank and the data that has been there before the push operation is overwritten . a similar argument can be made about stack underflows. note that any stack operation, which causes the stack to overflow or underflow, doesn ? t necessarily mean that any data in the stack are lost, as is observed in the first example. in sr1, there is a status flag, sf (stack full flag), which is exactly the same as sptr[5]. in other words, the value of sptr[5] can be checked by reading sf (or sr1[4]). sf is not a sticky flag in the sense that if there was a stack overflow/underflow but any following stack access instructions clear sptr[5] to 0, then sf = 0 and programmers cannot tell whether there was a stack overflow/underflow by reading sf. for example, if a program pushes a register 64 times in a row, sptr[5:0] is exactly the same as sptr[5:0] before the push sequence. therefore, special attention should be paid.
hardware stack s3fb 42f 5- 6 another mechanism to detect a stack overflow/underflow is through a stack exception. a stack exception happens only when the execution of any stack access instruction results in sf = 1 (or sptr[5] = 1). suppose a register push operation makes sf = 1 (the sf value before the push operation doesn ? t matter). then the stack exception due to the push operation is immediately generated and served if the stack exception enable flag (exe of sr0) is 1. if the stack exception enable flag is 0, then the generated interrupt is not served but pending. sometime later when the stack exception enable flag is set to 1, the pending exception request is served even if sf = 0. more details are available in the stack exception section.
S3FB42F exceptions 6- 1 6 exceptions overview exceptions in calmrisc are listed in the table below. exception handling routines, residing at the given addresses in the table, are invoked when the corresponding exception occurs. the starting address of each exception routine is specified by concatenating 0h (leading 4 bits of 0) and the 16-bit data in the exception vector listed in the table. for example, the interrupt service routine for nmi starts from 0h:pm[00001h]. note that ?:? means concatenation and pm[*] stands for the 16-bit content at the address * of the program memory. aside from the exception due to reset release, the current pc is pushed in the stack on an exception. when an exception is executed due to nmi/irq[1:0]/iexp, the global interrupt enable flag, ie bit (sr0[1]), is set to 0, whereas ie is set to 1 when iret or an instruction that explicitly sets ie is executed. table 6-1. exceptions name address priority description reset 00000h 1 st exception due to reset release. nmi 00001h 2 nd exception due to nnmi signal. non- maskable. irq[0] 00002h 4 th exception due to nirq[0] signal. maskable by setting ie/ie0. irq[1] 00003h 5 th exception due to nirq[1] signal. maskable by setting ie/ie1. iexp 00004h 3 rd exception due to stack full. maskable by setting exe. ? 00005h ? reserved. ? 00006h ? reserved. ? 00007h ? reserved. note: break mode due to bkreq has a higher priority than all the exceptions above. that is, when bkreq is active, even the exception due to reset release is not executed. hardware reset when hardware reset is active (the reset input signal pin nres = 0), the control pins in the calmrisc core are initialized to be disabled, and sr0 and sptr (the hardware stack pointer) are initialized to be 0. additionally, the interrupt sensing block is cleared. when hardware reset is released ( nres = 1), the reset exception is executed by loading the jp instruction in ir (instruction register) and 0h:0000h in pc. therefore, when hardware reset is released, the ?jp {0h:pm[00000h]}? instruction is executed. when the reset exception is executed, a core output signal nexpack is generated to acknowledge the exception.
exceptions S3FB42F 6- 2 nmi exception (edge sensitive) on the falling edge of a core input signal nnmi , the nmi exception is executed by loading the call instruction in ir and 0h:0001h in pc. therefore, when nmi exception is activated, the "call {0h:pm[00001h]}" instruction is executed. when the nmi exception is executed, the ie bit (sr0[1]) becomes 0 and a core output signal nexpack is generated to acknowledge the exception. irq[0] exception (level-sensitive) when a core input signal nirq[0] is low, sr0[6] (ie0) is high, and sr0[1] ( ie) is high, irq[0] exception is generated, and this will load the call instruction in ir (instruction register) and 0h:0002h in pc. therefore, on an irq[0] exception, the "call {0h:pm[00002h]}" instruction is executed. when the irq[0] exception is executed, sr0[1] ( ie) is set to 0 and a core output signal nexpack is generated to acknowledge the exception. irq[1] exception (level-sensitive) when a core input signal nirq[1] is low, sr0[7] (ie1) is high, and sr0[1] ( ie) is high, irq[1] exception is generated, and this will load the call instruction in ir (instruction register) and 0h:0003h in pc. therefore, on an irq[1] exception, the "call {0h:pm[00003h]}" instruction is executed. when the irq[1] exception is executed, sr0[1] ( ie) is set to 0 and a core output signal nexpack is generated to acknowledge the exception. hardware stack full exception a stack full exception occurs when a stack operation is performed and as a result of the stack operation sptr[5] (sf) is set to 1. if the stack exception enable bit, exe (sr0[5]), is 1, the stack full exception is served. one exception to this rule is when nnmi causes a stack operation that sets sptr[5] (sf), since it has higher priority. handling a stack full exception may cause another stack full exception. in this case, the new exception is ignored. on a stack full exception, the call instruction is loaded in ir (instruction register) and 0h:0004h in pc. therefore, when the stack full exception is activated, the "call {0h:pm[00004h]}" instruction is executed. when the exception is executed, sr0[1] ( ie) is set to 0, and a core output signal nexpack is generated to acknowledge the exception. break exception break exception is reserved only for an in-circuit debugger. when a core input signal, bkreq , is high, the calmrisc core is halted or in the break mode, until bkreq is deactivated. another way to drive the calmrisc core into the break mode is by executing a break instruction, break. when break is fetched, it is decoded in the fetch cycle (if stage) and the calmrisc core output signal nbkack is generated in the second cycle (id/mem stage). an in-circuit debugger generates bkreq active by monitoring nbkack to be active. break instruction is exactly the same as the nop (no operation) instruction except that it does not increase the program counter and activates nbkack in the second cycle (or id/mem stage of the pipeline). there, once break is encountered in the program execution, it falls into a deadlock. break instruction is reserved for in-circuit debuggers only, so it should not be used in user programs.
S3FB42F exceptions 6- 3 exceptions ( or interrupts) non-maskable interrupt - nmi 0001h - ext int 8 iis1 int wt int tb int ta int ivec0 0002h ivec1 0003h ext int 4 ext int 5 h/w h/w (s/w) vector source level reset (clear) reset or wdt overflow reset 0000h h/w iis0 int h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) notes: 1. nmi has the highest priority for an interrupt level, followed by sf_excep, ivec0 and ivec1. 2. in the case of ivec0 and ivec1, one interrupt vector has several interrupt sources. the priority of the sources is controlled by setting the ipr register. 3. external interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting, ext int0-ext int5 have no interrupt pending bit but have an enable bit. 4. after system reset, iis0 int has the highest priority in the ivec0 level, followed by iis1 int and other interrupt sources. 5. the interrupt priority can be changed by setting of ipr register. 6. the pending bit is cleared by hardware when cpu reads the iir register value. h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) ext int 0 ext int 1 ext int 2 ext int 3 bt sio int iic int uart rx/error/tx int h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w (s/w) h/w usb/ppic int ext int 9 stack full exception 0004h sf_excep figure 6-1. interrupt structure
exceptions S3FB42F 6- 4 ipr0 logic iir0 cpu ivec0 ipr0 imr0 logic imr0 stop & idle release imr1 logic imr1 irp1 ipr1 logic ivec1 iir1 irq0.0 irq0.1 irq0.2 irq0.3 irq0.4 irq0.5 irq0.6 irq0.7 irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 irq1.5 irq1.6 irq1.7 ext int9 usb int ppic int uart_rx int uart_err int uart_tx int iic int sio int bt int ext int0 ext int1 ext int2 ext int3 ext int4 ext int5 note: the irq register value is cleared by h/w when the iir register is read by the programmer in an interrupt service routine. however, if you want to clear by s/w, then write the proper value to the iir register like above examples. for clear all the bits of irqx register at one time write "#08h" to the iirx register. iis0 int iis1 int ext int8 ta int tb int nt int clear (when writing clear bit value to bit .2 .1 .0) exmp) ld r0, #05h clear (when writing clear bit value to bit .2 .1 .0) exmp) ld r0, #02h ld iir0, r0 irq.5 is cleared ld iir1, r0 irq1.2 is cleared figure 6-2. interrupt structure
S3FB42F exceptions 6- 5 interrupt mask registers .7 .6 .5 .4 .3 .2 .1 .0 interrupt mask register0 (imr0) 05h, r/w irq0.0 irq0.1 irq0.2 irq0.3 irq0.4 irq0.5 irq0.6 irq0.7 interrupt request enable bits: 0 = disable interrupt request 1 = enable interrupt request note: if you want to change the value of the imr register, then you first make disable global int by di instruction, and change the value of the imr register. .7 .6 .5 .4 .3 .2 .1 .0 interrupt mask register1 (imr1) 09h, r/w irq1.0 irq1.1 irq1.2 irq1.3 irq1.4 irq1.5 irq1.6 irq1.7 figure 6-3. interrupt mask register
exceptions S3FB42F 6- 6 interrupt priority register group a 0 = irq0 > irq1 1 = irq1 > irq0 interrupt priority registers (ipr0:06h,ipr1:0ah, r/w ) ipr group a note: if you want to change the value of the ipr register, then you first make disable global int by di instruction, and change the value of the ipr register. ipr group b ipr group c irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 group b 0 = irq2 > (irq3,irq4) 1 = (irq3,irq4) > irq2 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq5 > (irq6,irq7) 1 = (irq6,irq7) > irq5 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 .7 .6 .5 .4 .3 .2 .1 .0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 not used b>c>a a>b>c b>a>c c>a>b c>b>a a>c>b not used .7 .4 .1 group priority: figure 6-4. interrupt priority register
S3FB42F exceptions 6- 7 f f programming tip ? interrupt programming tip 1 jumped from vector 2 push sr1 push r0 and sr0, #0feh ld r0, iir0 cp r0, #03h jr ule, lte03 cp r0, #05h jr ule, lte05 cp r0, #06h jp eq, irq6_srv jp irq7_srv lte05 cp r0, #04h jp eq, irq4_srv jp irq5_srv lte03 cp r0, #01h jr ule, lte01 cp r0, #02h jp eq, irq2_srv jp irq3_srv lte01 cp r0, #00h jp eq, irq0_srv jp irq1_srv irq0_srv ? service for irq0 pop r0 pop sr1 iret irq1_srv ? service for irq1 pop r0 pop sr1 iret irq7_srv ? service for irq7 pop r0 pop sr1 iret note: if the sr0 register is changed in the interrupt service routine, then the sr0 register must be pushed and poped in the interrupt service routine.
exceptions S3FB42F 6- 8 f f programming tip ? interrupt programming tip 2 jumped from vector 2 push sr1 push r0 push r1 ld r0, iir0 sl r0 ld r1, # < tbl_intx add r0, # > tbl_intx push r0 push r1 ret tbl_intx ljp irq0_svr ljp irq1_svr ljp irq2_svr ljp irq3_svr ljp irq4_svr ljp irq5_svr ljp irq6_svr ljp irq7_svr irq0_srv ? service for irq0 pop r1 pop r0 pop sr1 iret irq1_srv ? service for irq1 pop r1 pop r0 pop sr1 iret irq7_srv ? service for irq7 pop r1 pop r0 pop sr1 iret notes: 1. if the sr0 register is changed in the interrupt service routine, then the sr0 register must be pushed and poped in the interrupt service routine. 2. above example is assumed that the rom size is less than 64kword and all the ljp instructions which is in the jump table (tbl- intx) is in the same page.
S3FB42F coprocessor interface 7- 1 7 coprocessor interfa ce overview calmrisc supports an efficient and seamless interface with coprocessors. by integrating a mac (multiply and accumulate) dsp coprocessor engine with the calmrisc core, not only the microcontroller functions but also complex digital signal processing algorithms can be implemented in a single development platform (or mds). calmrisc has a set of dedicated signal pins, through which data/command/status are exchanged to and from a coprocessor. figure 7-1 depicts the coprocessor signal pins and the interface between two processors. data bus [7:0] syscp [11:0] ncopid ncldid cldwr ec[2:0] coprocessor calmrisc program rom [23:0] data ram [23:0] [7:0] figure 7-1. coprocessor interface diagram
coprocessor interface S3FB42F 7- 2 as shown in the coprocessor interface diagram above, the coprocessor interface signals of calmrisc are: syscp[11:0] , ncopid , ncldid , ncldwr , and ec[2:0] . the data are exchanged through data buses, di[7:0] and do[7:0] . a command is issued from calmrisc to a coprocessor through syscp[11:0] in cop instructions. the status of a coprocessor can be sent back to calmrisc through ec[2:0] and these flags can be checked in the condition codes of branch instructions. the coprocessor instructions are listed in the following table table 7-1. coprocessor instructions mnemonic op 1 op 2 description cop #imm:12 ? coprocessor operation cld gpr imm:8 data transfer from coprocessor into gpr cld imm:8 gpr data transfer of gpr to coprocessor jp(or jr) call lnk ec2?ec0 label conditional branch with coprocessor status flags the coprocessor of calmrisc does not have its own program memory (i.e., it is a passive coprocessor) as shown in figure 7 -1. in fact, the coprocessor instructions are fetched and decoded by calmrisc, and calmrisc issues the command to the coprocessor through the interface signals. for example, if ?cop #imm:12? instruction is fetched, then the 12-bit immediate value (imm:12) is loaded on syscp[11:0] signal with ncopid active in id/mem stage, to request the coprocessor to perform the designated operation. the interpretation of the 12-bit immediate value is totally up to the coprocessor. by arranging the 12-bit immediate field, the instruction set of the coprocessor is determined. in other words, calmrisc only provides a set of generic coprocessor instructions, and its installation to a specific coprocessor instruction set can differ from one coprocessor to another. cld write instructions ( ? cld imm:8, gpr ? ) put the content of a gpr register of calmrisc on the data bus ( do[7:0] ) and issue the address(imm:8) of the coprocessor internal register on syscp[7:0] with ncldid active and cldwr active. cld read instructions ( ? cld gpr, imm:8 ? in table 7-1) work similarly, except that the content of the coprocessor internal register addressed by the 8-bit immediate value is read into a gpr register through di[7:0] with ncldid active and cldwr deactivated. the timing diagram given below is a coprocessor instruction pipeline and shows when the coprocessor performs the required operations. suppose i 2 is a coprocessor instruction. first, it is fetched and decoded by calmrisc (at t = t(i- 1)). once it is identified as a coprocessor instruction, calmrisc indicates to the coprocessor the appropriate command through the coprocessor interface signals (at t = t( i)). then the coprocessor performs the designated tasks at t = t( i) and t = t(i+1). hence if from calmrisc and then id/mem and ex from the coprocessor constitute the pipeline for i 2 . similarly, if i 3 is a coprocessor instruction, the coprocessor ? s id/mem and ex stages replace the corresponding stages of calmrisc.
S3FB42F coprocessor interface 7- 3 calmrisc if id/mem ex if id/mem if ex id/mem ex i 2 : coprocessor instruction t (i -1) t (i) t (i +1) i 1 : normal instruction i 3 : coprocessor instruction for i 3 for i 2 id/mem ex id/mem ex coprocessor i 2: i 3 : coprocessor interface signals figure 7-2. coprocessor instruction pipeline in a multi-processor system, the data transfer between processors is an important factor to determine the efficiency of the overall system. suppose an input data stream is accepted by a processor, in order for the data to be shared by another processors. there should be some efficient mechanism to transfer the data to the processors. in calmrisc, data transfers are accomplished through a single shared data memory. the shared data memory in a multi-processor has some inherent problems such as data hazards and deadlocks. however, the coprocessor in calmrisc accesses the shared data memory only at the designated time by calmrisc at which time calmrisc is guaranteed not to access the data memory, and therefore there is no contention over the shared data memory. another advantage of the scheme is that the coprocessor can access the data memory in its own bandwidth.
coprocessor interface S3FB42F 7- 4 notes
S3FB42F instruction set 8- 1 8 instruction set overview glossary this chapter describes the calmrisc instruction set and the details of each instruction are listed in alphabetical order. the following notations are used for the description. table 8-1. instruction notation conventions notation interpretation operand n. n can be omitted if there is only one operand. typically, is the destination (and source) operand and is a source operand. gpr general purpose register spr special purpose register (idl0, idl1, idh, sr0, ilx, ilh, ill, sr1) adr:n n-bit address specifier @idm content of memory location pointed by id0 or id1 (adr:n) content of memory location specified by adr:n cc:4 4-bit condition code. table 8-6 describes cc:4. imm:n n-bit immediate number & bit-wise and | bit-wise or ~ bit-wise not ^ bit-wise xor n**m mth power of n (n) m m-based number n as additional note, only the affected flags are described in the tables in this section. that is, if a flag is not affected by an operation, it is not specified.
instruction set s3f b42f 8- 2 instruction set map table 8-2. overall instruction set map ir [12:10]000 001 010 011 100 101 110 111 [15:13,7:2] 000 xxxxxx add gpr, #imm:8 sub gpr, #imm:8 cp gpr, #imm8 ld gpr, #imm:8 tm gpr, #imm:8 and gpr, #imm:8 or gpr, #imm:8 xor gpr, #imm:8 001 xxxxxx add gpr, @idm sub gpr, @idm cp gpr, @idm ld gpr, @idm ld @idm, gpr and gpr, @idm or gpr, @idm xor gpr, @idm 010 xxxxxx add gpr, adr:8 sub gpr, adr:8 cp gpr, adr:8 ld gpr, adr:8 bitt adr:8.bs bits adr:8.bs 011 xxxxxx adc gpr, adr:8 sbc gpr, adr:8 cpc gpr, adr:8 ld adr:8, gpr bitr adr:8.bs bitc adr:8.bs 100 000000 add gpr, gpr sub gpr, gpr cp gpr, gpr bms/bmc ld spr0, #imm:8 and gpr, adr:8 or gpr, adr:8 xor gpr, adr:8 100 000001 adc gpr, gpr sbc gpr, gpr cpc gpr, gpr invalid 100 000010 invalid invalid invalid invalid 100 000011 and gpr, gpr or gpr, gpr xor gpr, gpr invalid 100 00010x sla/sl/ rlc/rl/ sra/sr/ rrc/rr/ gpr inc/incc/ dec/ decc/ com/ com2/ comc gpr invalid invalid 100 00011x ld spr, gpr ld gpr, spr swap gpr, spr ld tbh/tbl, gpr 100 00100x push spr pop spr invalid invalid 100 001010 push gpr pop gpr ld gpr, gpr ld gpr, tbh/tbl
S3FB42F instruction set 8- 3 table 8-2. overall instruction set map (continued) ir [12:10]000 001 010 011 100 101 110 111 100 001011 pop invalid ldc invalid ld spr0, #imm:8 and gpr, adr:8 or gpr, adr:8 xor gpr, adr:8 100 00110x ret/lret/i ret/nop/ break invalid invalid invalid 100 00111x invalid invalid invalid invalid 100 01xxxx ld gpr:bank, gpr:bank and sr0, #imm:8 or sr0, #imm:8 bank #imm:2 100 100000 100 110011 invalid invalid invalid invalid 100 1101xx lcall cc:4, imm:20 (2-word instruction) 100 1110xx llnk cc:4, imm:20 (2-word instruction) 100 1111xx ljp cc:4, imm:20 (2-word instruction) [15:10] 101 xxx jr cc:4, imm:9 110 0xx calls imm:12 110 1xx lnks imm:12 111 xxx cld gpr, imm:8 / cld imm:8, gpr / jnzd gpr, imm:8 / sys #imm:8 / cop #imm:12 note: ? invalid ? - invalid instruction.
instruction set s3f b42f 8- 4 table 8-3. instruction encoding instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add gpr, #imm:8 000 000 gpr imm[7:0] sub gpr, #imm:8 001 cp gpr, #imm:8 010 ld gpr, #imm:8 011 tm gpr, #imm:8 100 and gpr, #imm:8 101 or gpr, #imm:8 110 xor gpr, #imm:8 111 add gpr, @idm 001 000 gpr idx mod offset[4:0] sub gpr, @idm 001 cp gpr, @idm 010 ld gpr, @idm 011 ld @idm, gpr 100 and gpr, @idm 101 or gpr, @idm 110 xor gpr, @idm 111 add gpr, adr:8 010 000 gpr adr[7:0] sub gpr, adr:8 001 cp gpr, adr:8 010 ld gpr, adr:8 011 bitt adr:8.bs 10 bs bits adr:8.bs 11 adc gpr, adr:8 011 000 gpr adr[7:0] sbc gpr, adr:8 001 cpc gpr, adr:8 010 ld adr:8, gpr 011 bitr adr:8.bs 10 bs bitc adr:8.bs 11
S3FB42F instruction set 8- 5 table 8-3. instruction encoding (continued ) instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 add gprd, gprs 100 000 gprd 000000 gprs sub gprd, gprs 001 cp gprd, gprs 010 bms/bmc 011 adc gprd, gprs 000 000001 sbc gprd, gprs 001 cpc gprd, gprs 010 invalid 011 invalid ddd 000010 and gprd, gprs 000 000011 or gprd, gprs 001 xor gprd, gprs 010 invalid 011 aluop1 000 gpr 00010 aluop1 aluop2 001 gpr aluop2 invalid 010?011 xx xxx ld spr, gpr 000 gpr 00011 spr ld gpr, spr 001 gpr spr swap gpr, spr 010 gpr spr ld tbl, gpr 011 gpr x 0 x ld tbh, gpr x 1 x push spr 000 xx 00100 spr pop spr 001 xx spr invalid 010?011 xx xxx push gpr 000 gpr 001010 gpr pop gpr 001 gpr gpr ld gprd, gprs 010 gprd gprs ld gpr, tbl 011 gpr 0 x ld gpr, tbh 1 x pop 000 xx 001011 xx ldc @il 010 0 x ldc @il+ 1 x invalid 001, 011 xx note: "x" means not applicable.
instruction set s3f b42f 8- 6 table 8-3. instruction encoding (concluded ) instruction 15-13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 nd word modop1 100 000 xx 00110 modop1 ? invalid 001?011 xx xxx invalid 000 xx 01 xxxxxx and sr0, #imm:8 001 imm[7:6] imm[5:0] or sr0, #imm:8 010 imm[7:6] bank #imm:2 011 xx x imm [1:0] xxx invalid 0 xxxx 10000000-11001111 lcall cc, imm:20 cc 1101 imm[19:16] imm[15:0] llnk cc, imm:20 ljp cc, imm:20 ld spr0, #imm:8 1 00 spr0 imm[7:0] ? and gpr, adr:8 01 gpr adr[7:0] or gpr, adr:8 10 xor gpr, adr:8 11 jr cc, imm:9 101 imm [8] cc imm[7:0] calls imm:12 110 0 imm[11:0] lnks imm:12 1 cld gpr, imm:8 111 0 00 gpr imm[7:0] cld imm:8, gpr 01 gpr jnzd gpr, imm:8 10 gpr sys #imm:8 11 xx cop #imm:12 1 imm[11:0] notes: 1. "x" means not applicable. 2. there are several modop1 codes that can be used, as described in table 8-9. 3. the operand 1(gpr) of the instruction jnzd is bank 3?s register.
S3FB42F instruction set 8- 7 table 8-4. index code information (?idx?) symbol code description id0 0 index 0 idh:idl0 id1 1 index 1 idh:idl1 table 8-5. index modification code information (?mod?) symbol code function @idx + offset:5 00 dm[idx], idx ? idx + offset @[idx - offset:5] 01 dm[idx + (2?s complement of offset:5)], idx ? idx + (2?s complement of offset:5) @[idx + offset:5]! 10 dm[idx + offset], idx ? idx @[idx - offset:5]! 11 dm[idx + (2?s complement of offset:5)], idx ? idx note: carry from idl is propagated to idh. in case of @[idx - offset:5] or @[idx - offset:5]!, the assembler should convert offset:5 to the 2?s complement format to fill the operand field (offset[4:0]). furthermore, @[idx - 0] and @[idx - 0]! are converted to @[idx + 0] and @[idx + 0]!, respectively. table 8-6. condition code information (?cc?) symbol (cc:4) code function blank 0000 always nc or ult 0001 c = 0, unsigned less than c or uge 0010 c = 1, unsigned greater than or equal to z or eq 0011 z = 1, equal to nz or ne 0100 z = 0, not equal to ov 0101 v = 1, overflow - signed value ule 0110 ~c | z, unsigned less than or equal to ugt 0111 c & ~z, unsigned greater than zp 1000 n = 0, signed zero or positive mi 1001 n = 1, signed negative pl 1010 ~n & ~z, signed positive zn 1011 z | n, signed zero or negative sf 1100 stack full ec0-ec2 1101-1111 ec[0] = 1/ec[1] = 1/ec[2] = 1 note: ec[2:0] is an external input (calmrisc core?s point of view) and used as a condition.
instruction set s3f b42f 8- 8 table 8-7. ?aluop1? code information symbol code function sla 000 arithmetic shift left sl 001 shift left rlc 010 rotate left with carry rl 011 rotate left sra 100 arithmetic shift right sr 101 shift right rrc 110 rotate right with carry rr 111 rotate right table 8-8. ?aluop2? code information symbol code function inc 000 increment incc 001 increment with carry dec 010 decrement decc 011 decrement with carry com 100 1?s complement com2 101 2?s complement comc 110 1?s complement with carry ? 111 reserved table 8-9. ?modop1? code information symbol code function lret 000 return by il ret 001 return by hs iret 010 return from interrupt (by hs) nop 011 no operation break 100 reserved for debugger use only ? 101 reserved ? 110 reserved ? 111 reserved
S3FB42F instruction set 8- 9 quick reference operation op1 op2 function flag # of word / cycle and or xor add sub cp gpr adr:8 #imm:8 gpr @idm op1 ? op1 & op2 op1 ? op1 | op2 op1 ? op1 ^ op2 op1 ? op1 + op2 op1 ? op1 + ~op2 + 1 op1 + ~op2 + 1 z,n z,n z,n c,z,v,n c,z,v,n c,z,v,n 1w1c adc sbc cpc gpr gpr adr:8 op1 ? op1 + op2 + c op1 ? op1 + ~op2 + c op1 + ~op2 + c c,z,v,n c,z,v,n c,z,v,n tm gpr #imm:8 op1 & op2 z,n bits bitr bitc bitt r3 adr:8.bs op1 ? (op2[bit] ? 1) op1 ? (op2[bit] ? 0) op1 ? ~(op2[bit]) z ? ~(op2[bit]) z z z z bms/bmc ? ? tf ? 1 / 0 ? push pop gpr ? hs[sptr] ? gpr, (sptr ? sptr + 1) gpr ? hs[ sptr - 1], (sptr ? sptr - 1) ? z,n push pop spr ? hs[sptr] ? spr, (sptr ? sptr + 1) spr ? hs[ sptr - 1], (sptr ? sptr - 1) ? pop ? ? sptr ? sptr ? 2 ? sla sl rlc rl sra sr rrc rr inc incc dec decc com com2 comc gpr ? c ? op1[7], op1 ? {op1[6:0], 0} c ? op1[7], op1 ? {op1[6:0], 0} c ? op1[7], op1 ? {op1[6:0], c} c ? op[7], op1 ? {op1[6:0], op1[7]} c ? op[0], op1 ? {op1[7],op1[7:1]} c ? op1[0], op1 ? {0, op1[7:1]} c ? op1[0], op1 ? {c, op1[7:1]} c ? op1[0], op1 ? {op1[0], op1[7:1]} p1 ? op1 + 1 op1 ? op1 + c op1 ? op1 + 0ffh op1 ? op1 + 0ffh + c op1 ? ~op1 op1 ? ~op1 + 1 op1 ? ~op1 + c c,z,v,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,n c,z,v,n c,z,v,n c,z,v,n c,z,v,n z,n c,z,v,n c,z,v,n
instruction set s3f b42f 8- 10 quick reference ( continued ) operation op1 op2 function flag # of word / cycle ld gpr :bank gpr :bank op1 ? op2 z,n 1w1c ld spr0 #imm:8 op1 ? op2 ? ld gpr gpr spr adr:8 @idm #imm:8 tbh/tbl op1 ? op2 z,n ld spr tbh/tbl gpr op1 ? op2 ? ld adr:8 gpr op1 ? op2 ? ld @idm gpr op1 ? op2 ? ldc @il @il+ ? (tbh:tbl) ? pm[(ilx:ilh:ill)], ill++ if @il+ ? 1w2c and or sr0 #imm:8 sr0 ? sr0 & op2 sr0 ? sr0 | op2 ? 1w1c bank #imm:2 ? sr0[4:3] ? op2 ? swap gpr spr op1 ? op2, op2 ? op1 (excluding sr0/sr1) ? lcall cc imm:20 ? if branch taken, push xstack, hs[15:0] ? {pc[15:12],pc[11:0] + 2} and pc ? op1 else pc[11:0] ? pc[11:0] + 2 ? 2w2c llnk cc imm:20 ? if branch taken, il[19:0] ? {pc[19:12], pc[11:0] + 2} and pc ? op1 else pc[11:0] ? pc[11:0] + 2 ? calls imm:12 ? push xstack, hs[15:0] ? {pc[15:12], pc[11:0] + 1} and pc[11:0] ? op1 ? 1w2c lnks imm:12 ? il[19:0] ? {pc[19:12], pc[11:0] + 1} and pc[11:0] ? op1 ? jnzd rn imm:8 if (rn == 0) pc ? pc[delay slot] - 2?s complement of imm:8, rn-- else pc ? pc[delay slot]++, rn-- ? ljp cc imm:20 ? if branch taken, pc ? op1 else pc[11:0] < pc[11:0] + 2 ? 2w2c jr cc imm:9 ? if branch taken, pc[11:0] ? pc[11:0] + op1 else pc[11:0] ? pc[11:0] + 1 ? 1w2c note: op1 - operand1, op2 - operand2, 1w1c - 1-word 1-cycle instruction, 1w2c - 1-word 2-cycl e instruction, 2w2c - 2-word 2-cycle instruction. the rn of instruction jnzd is bank 3?s gpr.
S3FB42F instruction set 8- 11 quick reference ( concluded ) operation op1 op2 function flag # of word / cycle lret ret iret nop break ? ? pc ? il[19:0] pc ? hs[ sptr - 2], (sptr ? sptr - 2) pc ? hs[ sptr - 2], (sptr ? sptr - 2) no operation no operation and hold pc ? 1w2c 1w2c 1w2c 1w1c 1w1c sys #imm:8 ? no operation but generates syscp[7:0] and nsysid ? 1w1c cld imm:8 gpr op1 ? op2, generates syscp[7:0], ncldid, and cldwr ? cld gpr imm:8 op1 ? op2, generates syscp[7:0], ncldid, and cldwr z,n cop #imm:12 ? generates syscp[11:0] and ncopid ? notes: 1. op1 - operand1, op2 - operand2, sptr - stack pointer register, 1w1c - 1-word 1-cycle instruction, 1w2c - 1-word 2-cycle instruction 2. pseudo instructions ? scf/rcf carry flag set or reset instruction ? stop/idle mcu power saving instructions ? ei/di exception enable and disable instructions ? jp/lnk/call if jr/lnks/calls commands (1 word instructions) can access the target address, there is no conditional code in the case of call/lnk, and the jp/lnk/call commands are assembled to jr/lnks/calls in linking time, or else the jp/lnk/call commands are assembled to ljp/llnk/lcall (2 word instructions) instr uctions.
instruction set s3f b42f 8- 12 instruction group summary alu instructions ?alu instructions? refer to the operations that use alu to generate results. alu instructions update the values in status register 1 (sr1), namely carry (c), zero (z), overflow (v), and negative (n), depending on the operation type and the result. aluop gpr, adr:8 performs an alu operation on the value in gpr and the value in dm[adr:8] and stores the result into gpr. aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not dm[adr:8])+1 is performed. adr:8 is the offset in a specific data memory page. the data memory page is 0 or the value of idh (index of data memory higher byte register), depending on the value of eid in status register 0 (sr0). operation gpr ? gpr aluop dm[00h:adr:8] if eid = 0 gpr ? gpr aluop dm[idh:adr8] if eid = 1 note that this is an 8-bit operation. example add r0, 80h // assume eid = 1 and idh = 01h // r0 ? r0 + dm[0180h] aluop gpr, #imm:8 stores the result of an alu operation on gpr and an 8-bit immediate value into gpr. aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not #imm:8)+1 is performed. #imm:8 is an 8-bit immediate value. operation gpr ? gpr aluop #imm:8 example add r0, #7ah // r0 ? r0 + 7ah
S3FB42F instruction set 8- 13 aluop gprd, gprs store the result of aluop on gprs and gprd into gprd. aluop = add, sub, cp, and, or, xor for sub and cp, gprd + (not gprs) + 1 is performed. gprs and gprd need not be distinct. operation gprd ? gprd aluop gprs gprd - gprs when aluop = cp (comparison only) example add r0, r1 // r0 ? r0 + r1 aluop gpr, @idm performs aluop on the value in gpr and dm[id] and stores the result into gpr. index register id is idh:idl (idh:idl0 or idh:idl1). aluop = add, sub, cp, and, or, xor for sub and cp, gpr+(not dm[idm])+1 is performed. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1) operation gpr - dm[idm] when aluop = cp (comparison only) gpr ? gpr aluop dm[idx], idx ? idx + offset:5 when idm = idx + offset:5 gpr ? gpr aluop dm[idx - offset:5], idx ? idx - offset:5 when idm = [idx - offset:5] gpr ? gpr aluop dm[idx + offset:5] when idm = [idx + offset:5]! gpr ? gpr aluop dm[idx - offset:5] when idm = [idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example add r0, @id0+2 // assume id0 = 02ffh // r0 ? r0 + dm[02ffh], idh ? 03h and idl0 ? 01h add r0, @[id0-2] // assume id0 = 0201h // r0 ? r0 + dm[01ffh], idh ? 01h and idl0 ? ffh add r0, @[id1+2]! // assume id1 = 02ffh // r0 ? r0 + dm[0301], idh ? 02h and idl1 ? ffh add r0, @[id1-2]! // assume id1 = 0200h // r0 ? r0 + dm[01feh], idh ? 02h and idl1 ? 00h
instruction set s3f b42f 8- 14 aluopc gprd, gprs performs aluop with carry on gprd and gprs and stores the result into gprd. aluopc = adc, sbc, cpc gprd and gprs need not be distinct. operation gprd ? gprd + gprs + c when aluopc = adc gprd ? gprd + (not gprs) + c when aluopc = sbc gprd + (not gprs) + c when aluopc = cpc (comparison only) example add r0, r2 // assume r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. adc r1, r3 // to add two 16-bit numbers, use add and adc. sub r0, r2 // assume r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. sbc r1, r3 // to su btract two 16-bit numbers, use sub and sbc. cp r0, r2 // assume both r1:r0 and r3:r2 are 16-bit unsigned numbers. cpc r1, r3 // to compare two 16-bit unsigned numbers, use cp and cpc. aluopc gpr, adr:8 performs aluop with carry on gpr and dm[adr:8]. operation gpr ? gpr + dm[adr:8] + c when aluopc = adc gpr ? gpr + (not dm[adr:8]) + c when aluopc = sbc gpr + (not dm[adr:8]) + c when aluopc = cpc (comparison only) cplop gpr (complement operations ) cplop = com, com2, comc operation com gpr not gpr (logical complement) com2 gpr not gpr + 1 (2?s complement of gpr) comc gpr not gpr + c (logical complement of gpr with carry) example com2 r0 // assume r1:r0 is a 16-bit signed number. comc r1 // com2 and comc can be used to get the 2?s complement of it.
S3FB42F instruction set 8- 15 incdec gpr (increment/decrement operations) incdec = inc, incc, dec, decc operation inc gpr increase gpr, i.e., gpr ? gpr + 1 incc gpr in crease gpr if carry = 1, i.e., gpr ? gpr + c dec gpr decrease gpr, i.e., gpr ? gpr + ffh decc gpr decrease gpr if carry = 0, i.e., gpr ? gpr + ffh + c example inc r0 // assume r1:r0 is a 16-bit number incc r1 // to increase r1:r0, use inc and incc. dec r0 // assume r1:r0 is a 16-bit number decc r1 // to decrease r1:r0, use dec and decc.
instruction set s3f b42f 8- 16 shift/rotate instructions shift (rotate) instructions shift (rotate) the given operand by 1 bit. depending on the operation performed, a number of status register 1 (sr1) bits, namely carry (c), zero (z), overflow (v), and negative (n), are set. sl gpr operation c 7 0 0 gpr carry (c) is the msb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. zero (z) will be 1 if the result is 0. sla gpr operation c 7 0 0 gpr carry (c) is the msb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) will be 1 if the msb of the result is different from c. z will be 1 if the result is 0. rl gpr operation c 7 0 gpr carry (c) is the msb of gpr before rotating. negative (n) is the msb of gpr after rotatin/g. overflow (v) is not affected. zero (z) will be 1 if the result is 0. rlc gpr operation c 7 0 gpr carry (c) is the msb of gpr before rotating, negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0.
S3FB42F instruction set 8- 17 sr gpr operation c 7 0 0 gpr carry (c) is the lsb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. zero (z) will be 1 if the result is 0. sra gpr operation c 7 0 gpr carry (c) is the lsb of gpr before shifting, negative (n) is the msb of gpr after shifting. overflow (v) is not affected. z will be 1 if the result is 0. rr gpr operation c 7 0 gpr carry (c) is the lsb of gpr before rotating. negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0. rrc gpr operation c 7 0 gpr carry (c) is the lsb of gpr before rotating, negative (n) is the msb of gpr after rotating. overflow (v) is not affected. zero (z) will be 1 if the result is 0.
instruction set s3f b42f 8- 18 load instructions load instructions transfer data from data memory to a register or from a register to data memory, or assigns an immediate value into a register. as a side effect, a load instruction placing a value into a register sets the zero (z) and negative (n) bits in status register 1 (sr1), if the placed data is 00h and the msb of the data is 1, respectively. ld gpr, adr:8 loads the value of dm[adr:8] into gpr. adr:8 is offset in the page specified by the value of eid in status register 0 (sr0). operation gpr ? dm[00h:adr:8] if eid = 0 gpr ? dm[idh:adr:8] if eid = 1 note that this is an 8-bit operation. example ld r0, 80h // assume eid = 1 and idh= 01h // r0 ? dm[0180h] ld gpr, @idm loads a value from the data memory location specified by @idm into gpr. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1) operation gpr ? dm[idx], idx ? idx + offset:5 when idm = idx + offset:5 gpr ? dm[idx - offset:5], idx ? idx - offset:5 when idm = [idx - offset:5] gpr ? dm[idx + offset:5] when idm = [idx + offset:5]! gpr ? dm[idx - offset:5] when idm = [idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example ld r0, @[id0 + 03h]! // assume idh:idl0 = 0270h // r0 ? dm[0273h], idh:idl0 ? 0270h
S3FB42F instruction set 8- 19 ld reg, #imm:8 loads an 8-bit immediate value into reg. reg can be either gpr or an spr0 group register - idh (index of data memory higher byte register), idl0 (index of data memory lower byte register)/ idl1, and status register 0 (sr0). #imm:8 is an 8-bit immediate value. operation reg ? #imm:8 example ld r0 #7ah // r0 ? 7ah ld idh, #03h // idh ? 03h ld gpr:bs:2, gpr:bs:2 loads a value of a register from a specified bank into another register in a specified bank. example ld r0:1, r2:3 // r0 in bank 1, r2 in bank 3 ld gpr, tbh/tbl loads the value of tbh or tbl into gpr. tbh and tbl are 8-bit long registers used exclusively for ldc instructions that access program memory. therefore, after an ldc instruction, ld gpr, tbh/tbl instruction will usually move the data into gprs, to be used for other operations. operation gpr ? tbh (or tbl) example ldc @il // gets a program memory item residing @ ilx:ilh:ill ld r0, tbh ld r1, tbl ld tbh/tbl, gpr loads the value of gpr into tbh or tbl. these instructions are used in pair in interrupt service routines to save and restore the values in tbh/tbl as needed. operation tbh (or tbl) ? gpr ld gpr, spr loads the value of spr into gpr. operation gpr ? spr example ld r0, idh // r0 ? idh
instruction set s3f b42f 8- 20 ld spr, gpr loads the value of gpr into spr. operation spr ? gpr example ld idh, r0 // idh ? r0 ld adr:8, gpr stores the value of gpr into data memory (dm). adr:8 is offset in the page specified by the value of eid in status register 0 (sr0). operation dm[00h:adr:8] ? gpr if eid = 0 dm[idh:adr:8] ? gpr if eid = 1 note that this is an 8-bit operation. example ld 7ah, r0 // assume eid = 1 and idh = 02h. // dm[027ah] ? r0 ld @idm, gpr loads a value into the data memory location specified by @idm from gpr. idm = idx+off:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1) operation dm[idx] ? gpr, idx ? idx + offset:5 when idm = idx + offset:5 dm[idx - offset:5] ? gpr, idx ? idx - offset:5 when idm = [idx - offset:5] dm[idx + offset:5] ? gpr when idm = [idx + offset:5]! dm[idx - offset:5] ? gpr when idm = [idx - offset:5]! when carry is generated from idl (on a post-increment or pre-decrement), it is propagated to idh. example ld @[id0 + 03h]!, r0 // assume idh:idl0 = 0170h // dm[0173h] ? r0, idh:idl0 ? 0170h
S3FB42F instruction set 8- 21 branch instructions branch instructions can be categorized into jump instruction, link instruction, and call instruction. a jump instruction does not save the current pc, whereas a call instruction saves (?pushes?) the current pc onto the stack and a link instruction saves the pc in the link register il. status registers are not affected. each instruction type has a 2-word format that supports a 20-bit long jump. jr cc:4, imm:9 imm:9 is a signed number (2?s complement), an offset to be added to the current pc to compute the target (pc[19:12]:(pc[11:0] + imm:9)). operation pc[11:0] ? pc[11:0] + imm:9 if branch taken (i.e., cc:4 resolves to be true) pc[11:0] ? pc[11:0] + 1 otherwise example l18411: // assume current pc = 18411h. jr z, 107h // next pc is 18518 (18411h + 107h) if zero (z) bit is set. ljp cc:4, imm:20 jumps to the program address specified by imm:20. if program size is less than 64k word, pc[19:16] is not affected. operation pc[15:0] ? imm[15:0] if branch taken and program size is less than 64k word pc[19:0] ? imm[19:0] if branch taken and program size is equal to 64k word or more pc [11:0] ? pc[11:0] + 1 otherwise example l18411: // assume current pc = 18411h. ljp z, 10107h // next instruction?s pc is 10107h if zero (z) bit is set jnzd rn, imm:8 jumps to the program address specified by imm:8 if the value of the bank 3 register rn is not zero. jnzd performs only backward jumps, with the value of rn automatically decreased. there is one delay slot following the jnzd instruction that is always executed, regardless of whether jnzd is taken or not. operation if (rn == 0) pc ? pc[delay slot] (-) 2?s complement of imm:8, rn ? rn - 1 else pc ? pc[delay slot] + 1, rn ? rn - 1.
instruction set s3f b42f 8- 22 example loop_a: // start of loop body jnzd r0, loop_a // jump back to loop_a if r0 is not zero add r1, #2 // delay slot, always executed (you must use one cycle instruction only) calls imm:12 saves the current pc on the stack (?pushes? pc) and jumps to the program address specified by imm:12. the current page number pc[19:12] is not changed. since this is a 1-word instruction, the return address pushed onto the stack is (pc + 1). if np64kw is low when pc is saved, pc[19:16] is not saved in the stack. operation hs[sptr][15:0] ? current pc + 1 and sptr ? sptr + 2 (push stack) if np64kw = 0 hs[sptr][19:0] ? current pc + 1 and sptr ? sptr + 2 (push stack) if np64kw = 1 pc[11:0] ? imm:12 example l18411: // assume current pc = 18411h. calls 107h // call the subroutine at 18107h, with the current pc pushed // onto the stack (hs ? 18412h) if np64kw = 1. lcall cc:4, imm:20 saves the current pc onto the stack (pushes pc) and jumps to the program address specified by imm:20. since this is a 2-word instruction, the return address saved in the stack is (pc + 2). if np64kw, a core input signal is low when pc is saved, 0000111111pc[19:16] is not saved in the stack and pc[19:16] is not set to imm[19:16]. operation hs[sptr][15:0] ? current pc + 2 and sptr + 2 (push stack) if branch taken and np64kw = 0 hs[sptr][19:0] ? current pc + 2 and sptr + 2 (push stack) if branch taken and np64kw = 1 pc[15:0] ? imm[15:0] if branch taken and np64kw = 0 pc[19:0] ? imm[19:0] if branch taken and np64kw = 1 pc[11:0] ? pc[11:0] + 2 otherwise example l18411: // assume current pc = 18411h. lcall nz, 10h:107h // call the subroutine at 10107h with the current pc pushed // onto the stack (hs ? 18413h)
S3FB42F instruction set 8- 23 lnks imm:12 saves the current pc in il and jumps to the program address specified by imm:12. the current page number pc[19:12] is not changed. since this is a 1-word instruction, the return address saved in il is (pc + 1). if the program size is less than 64k word when pc is saved, pc[19:16] is not saved in ilx. operation il[15:0] ? current pc + 1 if program size is less than 64k word il[19:0] ? current pc + 1 if program size is equal to 64k word or more pc[11:0] ? imm:12 example l18411: // assume current pc = 18411h. lnks 107h // call the subroutine at 18107h, with the current pc saved // in il (il[19:0] ? 18412h) if program size is 64k word or more. llnk cc:4, imm:20 saves the current pc in il and jumps to the program address specified by imm:20. since this is a 2-word instruction, the return address saved in il is (pc + 2). if the program size is less than 64k word when pc is saved, pc[19:16] is not saved in ilx. operation il[15:0] ? current pc + 2 if branch taken and program size is less than 64k word il[19:0] ? current pc + 2 if branch taken and program size is 64k word or more pc[15:0] ? imm[15:0] if branch taken and program size is less than 64k word pc[19:0] ? imm[19:0] if branch taken and program size is 64k word or more pc[11:0] ? pc[11:0] + 2 otherwise example l18411: // assume current pc = 18411h. llnk nz, 10h:107h // call the subroutine at 10107h with the current pc saved // in il (il[19:0] ? 18413h) if program size is 64k word or more ret, iret returns from the current subroutine. iret sets ie (sr0[1]) in addition. if the program size is less than 64k word, pc[19:16] is not loaded from hs[19:16]. operation pc[15:0] ? hs[sptr - 2] and sptr ? sptr - 2 (pop stack) if program size is less than 64k word pc[19:0] ? hs[sptr - 2] and sptr ? sptr - 2 (pop stack) if program size is 64k word or more example ret // assume sptr = 3h and hs[1] = 18407h. // the next pc will be 18407h and sptr is set to 1h
instruction set s3f b42f 8- 24 lret returns from the current subroutine, using the link register il. if the program size is less than 64k word, pc[19:16] is not loaded from ilx. operation pc[15:0] ? il[15:0] if program size is less tha n 64k word pc[19:0] ? il[19:0] if program size is 64k word or more example lret // assume il = 18407h. // the next instruction to execute is at pc = 18407h // if program size is 64k word or more jp/lnk/call jp/lnk/call instructions are pseudo instructions. if jr/lnks/calls commands (1 word instructions) can access the target address, there is no conditional code in the case of call/lnk and the jp/lnk/call commands are assembled to jr/lnks/calls in linking time or else the jp/lnk/call commands are assembled to ljp/llnk/lcall (2 word instructions) instructions.
S3FB42F instruction set 8- 25 bit manipulation instructions bitop adr:8.bs performs a bit operation specified by op on the value in the data memory pointed by adr:8 and stores the result into r3 of current gpr bank or back into memory depending on the value of tf bit. bitop = bits, bitr, bitc, bitt bits: bit set bitr: bit reset bitc: bit complement bitt: bit test (r3 is not touched in this case) bs: bit location specifier, 0 - 7. operation r3 ? dm[00h:adr:8] bitop bs if eid = 0 r3 ? dm[idh:adr:8] bitop bs if eid = 1 (no register transfer for bitt) set the zero (z) bit if the result is 0. example bits 25h.3 // assume eid = 0. set bit 3 of dm[00h:25h] and store the result in r3. bitt 25h.3 // check bit 3 of dm[00h:25h] if eid = 0. bmc/bms clears or sets the tf bit, which is used to determine the destination of bitop instructions. when tf bit is clear, the result of bitop instructions will be stored into r3 (fixed); if the tf bit is set, the result will be written back to memory. operation tf ? 0 (bmc) tf ? 1 (bms) tm gpr, #imm:8 performs and operation on gpr and imm:8 and sets the zero (z) and negative (n) bits. no change in gpr. operation z, n flag ? gpr & #imm:8 bitop gpr.bs performs a bit operation on gpr and stores the result in gpr. since the equivalent functionality can be achieved using or gpr, #imm:8, and gpr, #imm:8, and xor gpr, #imm:8, this instruction type doesn?t have separate op codes.
instruction set s3f b42f 8- 26 and sr0, #imm:8/or sr0, #imm:8 sets/resets bits in sr0 and stores the result back into sr0. operation sr0 ? sr0 & #imm:8 sr0 ? sr0 | #imm:8 bank #imm:2 loads sr0[4:3] with #imm[1:0]. operation sr0[4:3] ? #imm[1:0] miscellaneous instruction swap gpr, spr swaps the values in gpr and spr. sr0 and sr1 can not be used for this instruction. no flag is updated, even though the destination is gpr. operation temp ? spr spr ? gpr gpr ? temp example swap r0, idh // assume idh = 00h and r0 = 08h. // after this, idh = 08h and r0 = 00h. push reg saves reg in the stack (pushes reg into stack). reg = gpr, spr operation hs[sptr][7:0] ? reg and sptr ? sptr + 1 example push r0 // assume r0 = 08h and sptr = 2h // then hs[2][7:0] ? 08h and sptr ? 3h
S3FB42F instruction set 8- 27 pop reg pops stack into reg. reg = gpr, spr operation reg ? hs[sptr-1][7:0] and sptr ? sptr ? 1 example pop r0 // assume sptr = 3h and hs[2] = 18407h // r0 ? 07h and sptr ? 2h pop pops 2 bytes from the stack and discards the popped data. nop does no work but increase pc by 1. break does nothing and does not increment pc. this instruction is for the debugger only. when this instruction is executed, the processor is locked since pc is not incremented. therefore, this instruction should not be used under any mode other than the debug mode. sys #imm:8 does nothing but increase pc by 1 and generates syscp[7:0] and nsysid signals. cld gpr, imm:8 gpr ? (imm:8) and generates syscp[7:0], ncldid, and ncldwr signals. cld imm:8, gpr (imm:8) ? gpr and generates syscp[7:0], ncldid, and ncldwr signals. cop #imm:12 generates syscp[11:0] and ncopid signals.
instruction set s3f b42f 8- 28 ldc loads program memory item into register. operation [tbh:tbl] ? pm[ilx:ilh:ill] (ldc @il) [tbh:tbl] ? pm[ilx:ilh:ill], ill++ (ldc @il+) tbh and tbl are temporary registers to hold the transferred program memory items. these can be accessed only by ld gpr and tbl/tbh instruction. example ld ilx, r1 // assume r1:r2:r3 has the program address to access ld ilh, r2 ld ill, r3 ldc @il // get the program data @(ilx:ilh:ill) into tbh:tbl
S3FB42F instruction set 8- 29 pseudo instructions ei/di exceptions enable and disable instruction. operation sr0 ? or sr0,#00000010b (ei) sr0 ? and sr0,#11111101b (di) exceptions are enabled or disabled through this instruction. if there is an ei instruction, the sr0.1 is set and reset, when di instruction. example di ei scf/rcf carry flag set and reset instruction. operation cp r0,r0 (scf) and r0,r0 (rcf) carry flag is set or reset through this instruction. if there is an scf instruction, the sr1.0 is set and reset, when rcf instruction. example scf rcf stop/idle mcu power saving instruction. operation sys #0ah (stop) sys #05h (idle) the stop instruction stops the both cpu clock and system clock and causes the microcontroller to enter stop mode. the idle instruction stops the cpu clock while allowing system clock oscillation to continue. example stop(or idle) nop nop nop
instruction set s3f b42f 8- 30 adc ? add with carry format: adc , : gpr : adr:8, gpr operation: ? + + c adc adds the values of and and carry (c) and stores the result back into flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. . n: exclusive or of v and msb of result. example: adc r0, 80h // if eid = 0, r0 ? r0 + dm[0080h] + c // if eid = 1, r0 ? r0 + dm[idh:80h] + c adc r0, r1 // r0 ? r0 + r1 + c add r0, r2 adc r1, r3 in the last two instructions, assuming that register pair r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. even if the result of ?add r0, r2? is not zero, z flag can be set to ?1? if the result of ?adc r1,r3? is zero. note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit addition, take care of the change of z flag.
S3FB42F instruction set 8- 31 add ? add format: add , : gpr : adr:8, #imm:8, gpr, @idm operation: ? + add adds the values of and and stores the result back into . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. . n: exclusive or of v and msb of result. example: given: idh:idl0 = 80ffh, eid = 1 add r0, 80h // r0 ? r0 + dm[8080h] add r0, #12h // r0 ? r0 + 12h add r1, r2 // r1 ? r1 + r2 add r0, @id0 + 2 // r0 ? r0 + dm[80ffh], idh ? 81h, idl0 ? 01h add r0, @[id0 ? 3] // r0 ? r0 + dm[80fch], idh ? 80h, idl0 ? fch add r0, @[id0 + 2]! // r0 ? r0 + dm[8101h], idh ? 80h, idl0 ? ffh add r0, @[id0 ? 2]! // r0 ? r0 + dm[80fdh], idh ? 80h, idl0 ? ffh in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
instruction set s3f b42f 8- 32 and ? bit-wise and format: and , : gpr : adr:8, #imm:8, gpr, @idm operation: ? & and performs bit-wise and on the values in and and stores the result in . flags: z: set if result is zero. reset if not. n: set if the msb of result is 1. reset if not. example: given: idh:idl0 = 01ffh, eid = 1 and r0, 7ah // r0 ? r0 & dm[017ah] and r1, #40h // r1 ? r1 & 40h and r0, r1 // r0 ? r0 & r1 and r1, @id0 + 3 // r1 ? r1 & dm[01ffh], idh:idl0 ? 0202h and r1, @[id0 ? 5] // r1 ? r1 & dm[01fah], idh:idl0 ? 01fah and r1, @[id0 + 7]! // r1 ? r1 & dm[0206h], idh:idl0 ? 01ffh and r1, @[id0 ? 2]! // r1 ? r1 & dm[01fdh], idh:idl0 ? 01ffh in the first instruction, if eid bit in sr0 is zero, register r0 has garbage value because data memory dm[0051h-007fh] are not mapped in s3cb018/s3fb018. in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
S3FB42F instruction set 8- 33 and sr0 ? bit-wise and with sr0 format: and sr0, #imm:8 operation: sr0 ? sr0 & imm:8 and sr0 performs the bit-wise and operation on the value of sr0 and imm:8 and stores the result in sr0. flags: ? example: given: sr0 = 11000010b nie equ ~02h nie0 equ ~40h nie1 equ ~80h and sr0, #nie | nie0 | nie1 and sr0, #11111101b in the first example, the statement ?and sr0, #nie|nie0|nie1? clear all of bits of the global interrupt, interrupt 0 and interrupt 1. on the contrary, cleared bits can be set to ?1? by instruction ?or sr0, #imm:8?. refer to instruction or sr0 for more detailed explanation about enabling bit. in the second example, the statement ?and sr0, #11111101b? is equal to instruction di, which is disabling interrupt globally.
instruction set s3f b42f 8- 34 bank ? gpr bank selection format: bank #imm:2 operation: sr0[4:3] ? imm:2 flags: ? note: for explanation of the calmrisc banked register file and its usage, please refer to chapter 3. example: bank #1 // select register bank 1 ld r0, #11h // bank1?s r0 ? 11h bank #2 // select register bank 2 ld r1, #22h // bank2?s r1 ? 22h
S3FB42F instruction set 8- 35 bitc ? bit complement format: bitc adr:8.bs bs: 3-digit bit specifier operation: r3 ? ((adr:8) ^ (2**bs)) if (tf == 0) (adr:8) ? ((adr:8) ^ (2**bs)) if (tf == 1) bitc complements the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = ffh, eid = 1 bmc // tf ? 0 bitc 80h.0 // r3 ? feh, dm[0180h] = ffh bms // tf ? 1 bitc 80h.1 // dm[0180h] ? fdh
instruction set s3f b42f 8- 36 bitr ? bit reset format: bitr adr:8.bs bs: 3-digit bit specifier operation: r3 ? ((adr:8) & ((11111111) 2 - (2**bs))) if (tf == 0) (adr:8) ? ((adr:8) & ((11111111) 2 - (2**bs))) if (tf == 1) bitr resets the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = ffh, eid = 1 bmc // tf ? 0 bitr 80h.1 // r3 ? fdh, dm[0180h] = ffh bms // tf ? 1 bitr 80h.2 // dm[0180h] ? fbh
S3FB42F instruction set 8- 37 bits ? bit set format: bits adr:8.bs bs: 3-digit bit specifier. operation: r3 ? ((adr:8) | (2**bs)) if (tf == 0) (adr:8) ? ((adr:8) | (2**bs)) if (tf == 1) bits sets the specified bit of a value read from memory and stores the result in r3 or back into memory, depending on the value of tf. tf is set or clear by bms/bmc instruction. flags: z: set if result is zero. reset if not. note: since the destination register r3 is fixed, it is not specified explicitly. example: given: idh = 01, dm[0180h] = f0h, eid = 1 bmc // tf ? 0 bits 80h.1 // r3 ? 0f2h, dm[0180h] = f0h bms // tf ? 1 bits 80h.2 // dm[0180h] ? f4h
instruction set s3f b42f 8- 38 bitt ? bit test format: bitt adr:8.bs bs: 3-digit bit specifier. operation: z ? ~((adr:8) & (2**bs)) bitt tests the specified bit of a value read from memory. flags: z: set if result is zero. reset if not. example: given: dm[0080h] = f7h, eid = 0 bitt 80h.3 // z flag is set to ?1? jr z, %1 // jump to label %1 because condition is true. %1 bits 80h.3 nop
S3FB42F instruction set 8- 39 bmc/bms ? tf bit clear/set format: bms/bmc operation: bmc/bms clears (sets) the tf bit. tf ? 0 if bmc tf ? 1 if bms tf is a single bit flag which determines the destination of bit operations, such as bitc, bitr, and bits. flags: ? note: bmc/bms are the only instructions that modify the content of the tf bit. example: bms // tf ? 1 bits 81h.1 bmc // tf ? 0 bitr 81h.2 ld r0, r3
instruction set s3f b42f 8- 40 call ? conditional subroutine call (pseudo instruction) format: call cc:4, imm:20 call imm:12 operation: if calls can access the target address and there is no conditional code (cc:4), call command is assembled to calls (1-word instruction) in linking time, else the call is assembled to lcall (2-word ins truction). example: call c, wait // hs[sptr][15:0] ? current pc + 2, sptr ? sptr + 2 // 2-word instruction call 0088h // hs[sptr][15:0] ? current pc + 1, sptr ? sptr + 2 // 1-word instruction wait: nop // address at 0088h nop nop nop nop ret
S3FB42F instruction set 8- 41 calls ? call subroutine format: calls imm:12 operation: hs[sptr][15:0] ? current pc + 1, sptr ? sptr + 2 if the program size is less than 64k word. hs[sptr][19:0] ? current pc + 1, sptr ? sptr + 2 if the program size is equal to or over 64k word. pc[11:0] ? imm:12 calls unconditionally calls a subroutine residing at the address specified by imm:12. flags: ? example: calls wait wait: nop nop nop ret because this is a 1-word instruction, the saved returning address on stack is (pc + 1).
instruction set s3f b42f 8- 42 cld ? load into coprocessor format: cld imm:8, : gpr operation: (imm:8) ? cld loads the val ue of into (imm:8), where imm:8 is used to access the external coprocessor's address space. flags: ? example: ah equ 00h al equ 01h bh equ 02h bl equ 03h cld ah, r0 // a[15:8] ? r0 cld al, r1 // a[7:0] ? r1 cld bh, r2 // b[15:8] ? r2 cld bl, r3 // b[7:0] ? r3 the registers a[15:0] and b[15:0] are arithmetic unit (au) registers of mac816. above instructions generate syscp[7:0], ncldid and cldwr signals to access mac816.
S3FB42F instruction set 8- 43 cld ? load from coprocessor format: cld , imm:8 : gpr operation: ? (imm:8) cld loads a value from the coprocessor, whose address is specified by imm:8. flags: z: set if the loaded value in is zero. reset if not. n: set if the msb of the loaded value in is 1. reset if not. example: ah equ 00h al equ 01h bh equ 02h bl equ 03h cld r0, ah // r0 ? a[15:8] cld r1, al // r1 ? a[7:0] cld r2, bh // r2 ? b[15:8] cld r3, bl // r3 ? b[7:0] the registers a[15:0] and b[15:0] are arithmetic unit (au) registers of mac816. above instructio ns generate syscp[7:0], ncldid and cldwr signals to access mac816.
instruction set s3f b42f 8- 44 com ? 1's or bit-wise complement format: com : gpr operation: ? ~ com takes the bit-wise complement operation on and stores the result in . flags: z: set if result is zero. reset if not. n: set if the msb of result is 1. reset if not. example: given: r1 = 5ah com r1 // r1 ? a5h, n flag is set to ?1?
S3FB42F instruction set 8- 45 com2 ? 2's complement format: com2 : gpr operation: ? ~ + 1 com2 computes the 2's complement of and stores the result in . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. example: given: r0 = 00h, r1 = 5ah com2 r0 // r0 ? 00h, z and c flags are set to ?1?. com2 r1 // r1 ? a6h, n flag is set to ?1?.
instruction set s3f b42f 8- 46 comc ? bit-wise complement with carry format: comc : gpr operation: ? ~ + c comc takes the bit-wise complement of , adds carry and stores the result in . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: if register pair r1:r0 is a 16-bit number, then the 2?s complement of r1:r0 can be obtained by com2 and comc as following. com2 r0 comc r1 note that z flag do not exactly reflect result of 16-bit operation. for example, if 16-bit register pair r1: r0 has value of ff01h, then 2?s complement of r1: r0 is made of 00ffh by com2 and comc. at this time, by instruction comc, zero (z) flag is set to ?1? as if the result of 2?s complement for 16- bit number is zero. therefore when programming 16-bit comparison, take care of the change of z flag.
S3FB42F instruction set 8- 47 cop ? coprocessor format: cop #imm:12 operation: cop passes imm:12 to the coprocessor by generating syscp[11:0] and ncopid signals. flags: ? example: cop #0d01h // generate 1 word instruction code(fd01h) cop #0234h // generate 1 word instruction code(f234h) the above two instructions are equal to statement ?eld a, #1234h? for mac816 operation. the microcode of mac instruction ?eld a, #1234h? is ?fd01f234?, 2-word instruction. in this, code ?f? indicates ?cop? instruction.
instruction set s3f b42f 8- 48 cp ? compare format: cp , : gpr : adr:8, #imm:8, gpr, @idm operation: + ~ + 1 cp compares the values of and by subtracting from . contents of and are not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero (i.e., and are same). reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: r0 = 73h, r1 = a5h, idh:idl0 = 0123h, dm[0123h] = a5, eid = 1 cp r0, 80h // c flag is set to ?1? cp r0, #73h // z and c flags are set to ?1? cp r0, r1 // v flag is set to ?1? cp r1, @id0 // z and c flags are set to ?1? cp r1, @[id0 ? 5] cp r2, @[id0 + 7]! cp r2, @[id0 ? 2]! in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
S3FB42F instruction set 8- 49 cpc ? compare with carry format: cpc , : gpr : adr:8, gpr operation: ? + ~ + c cpc compares and by subtracting from . unlike cp, however, cpc adds (c - 1) to the result. contents of and are not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: if register pair r1:r0 and r3:r2 are 16-bit signed or unsigned numbers, then use cp and cpc to compare two 16-bit numbers as follows. cp r0, r1 cpc r2, r3 because cpc considers c when comparing and , cp and cpc can be used in pair to compare 16-bit operands. but note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit comparison, take care of the change of z flag.
instruction set s3f b42f 8- 50 dec ? decrement format: dec : gpr operation: ? + 0ffh dec decrease the value in by adding 0ffh to . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: r0 = 80h, r1 = 00h dec r0 // r0 ? 7fh, c, v and n flags are set to ?1? dec r1 // r1 ? ffh, n flags is set to ?1?
S3FB42F instruction set 8- 51 decc ? decrement with carry format: decc : gpr operation: ? + 0ffh + c decc decrease the value in when carry is not set. when there is a carry, there is no change in the value of . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: if register pair r1:r0 is 16-bit signed or unsigned number, then use dec and decc to decrement 16-bit number as follows. dec r0 decc r1 note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit decrement, take care of the change of z flag.
instruction set s3f b42f 8- 52 di ? disable interrupt (pseudo instruction) format: di operation: disables interrupt globally. it is same as ?and sr0, #0fdh? . di instruction sets bit1 (ie: global interrupt enable) of sr0 register to ?0? flags: ? example: given: sr0 = 03h di // sr0 ? sr0 & 11111101b di instruc tion clears sr0[1] to ?0?, disabling interrupt processing.
S3FB42F instruction set 8- 53 ei ? enable interrupt (pseudo instruction) format: ei operation: enables interrupt globally. it is same as ?or sr0, #02h? . ei instruction sets the bit1 (ie: global interrupt enable) of sr0 register to ?1? flags: ? example: given: sr0 = 01h ei // sr0 ? sr0 | 00000010b the statement ?ei? sets the sr0[1] to ?1?, enabling all interrupts.
instruction set s3f b42f 8- 54 idle ? idle operation (pseudo instruction) format: idle operation: the idle instruction stops the cpu clock while allowing system clock oscillation to continue. idle mode can be released by an interrupt or reset operation. the idle instruction is a pseudo instruction. it is assembled as ?sys #05h?, and this generates the syscp[7-0] signals. then these signals are decoded and the decoded signals execute the idle operation. flags: ? note: the next instruction of idle instruction is executed, so please use the nop instruction after the idle instruction. example: idle no p nop nop the idle instruction stops the cpu clock but not the system clock.
S3FB42F instruction set 8- 55 inc ? increment format: inc : gpr operation: ? + 1 inc increase the value in . flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: r0 = 7fh, r1 = ffh inc r0 // r0 ? 80h, v flag is set to ?1? inc r1 // r1 ? 00h, z and c flags are set to ?1?
instruction set s3f b42f 8- 56 incc ? increment with carry format: incc : gpr operation: ? + c incc increase the value of only if there is carry. when there is no carry, the value of is not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: exclusive or of v and msb of result. example: if register pair r1:r0 is 16-bit signed or unsigned number, then use inc and incc to increment 16-bit number as following. inc r0 incc r1 assume r1:r0 is 0010h, statement ?inc r0? increase r0 by one without carry and statement ?incc r1? set zero (z) flag to ?1? as if the result of 16-bit increment is zero. note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit increment, take care of the change of z flag.
S3FB42F instruction set 8- 57 iret ? return from interrupt handling format: iret operation: pc ? hs[sptr - 2], sptr ? sptr - 2 iret pops the return address (after interrupt handling) from the hardware stack and assigns it to pc. the ie (i.e., sr0[1]) bit is set to allow further interrupt generation. flags: ? note: the program size (indicated by the np64kw signal) determines which portion of pc is updated. when the program size is less than 64k word, only the lower 16 bits of pc are updated (i.e., pc[15:0] ? hs[sptr ? 2] ) . when the program size is 64k word or more, the action taken is pc[19:0] ? hs[sptr - 2]. example: sf_excep: nop // stack full exception service routine iret
instruction set s3f b42f 8- 58 jnzd ? jump not zero with delay slot format: jnzd , imm:8 : gpr (bank 3?s gpr only) imm:8 is an signed number operation: pc ? pc[delay slot] - 2?s complement of imm:8 ? - 1 jnzd performs a backward pc-relative jump if evaluates to be non-zero. furthermore, jnzd decrease the value of . the instruction immediately following jnzd (i.e., in delay slot) is always executed, and this instruction must be 1 cycle instruction. flags: ? note: typically, the delay slot will be filled with an instruction from the loop body. it is noted, however, that the chosen instruction should be ?dead? outside the loop for it executes even when the loop is exited (i.e., jnzd is not taken). example: given: idh = 03h, eid = 1 bank #3 ld r0, #0ffh // r0 is used to loop counter ld r1, #0 %1 ld idl0, r0 jnzd r0, %b1 // if r0 of bank3 is not zero, jump to %1. ld @id0, r1 // clear register pointed by id0 this example can be used for ram clear routine. the last instruction is executed even if the loop is exited.
S3FB42F instruction set 8- 59 jp ? conditional jump (pseudo instruction) format: jp cc:4 imm:20 jp cc:4 imm:9 operation: if jr can access the target address, jp command is assembled to jr (1 word instruction) in linking time, else the jp is assembled to ljp (2 word instruction) instruction. there are 16 different conditions that can be used, as described in table 8-6. example: %1 ld r0, #10h // assume address of label %1 is 020dh jp z, %b1 // address at 0264h jp c, %f2 // address at 0265h %2 ld r1, #20h // assume address of label %2 is 089ch in the above example, the statement ?jp z, %b1? is assembled to jr instruction. assuming that current pc is 0264h and condition is true, next pc is made by pc[11:0] ? pc[11:0] + offset, offset value is ?64h + a9h? without carry. ?a9? means 2?s complement of offset value to jump backward. therefore next pc is 020dh. on the other hand, statement ?jp c, %f2? is assembled to ljp instruction because offset address exceeds the range of imm:9.
instruction set s3f b42f 8- 60 jr ? conditional jump relative format: jr cc:4 imm:9 cc:4: 4-bit condition code operation: pc[11:0] ? pc[11:0] + imm:9 if condition is true. imm:9 is a signed number, which is sign- extended to 12 bits when added to pc. there are 16 different conditions that can be used, as described in table 8-6. flags: ? note: unlike ljp, the target address of jr is pc-relative. in the case of jr, imm:9 is added to pc to compute the actual jump address, while ljp directly jumps to imm:20, the target. example: jr z, %1 // assume current pc = 1000h %1 ld r0, r1 // address at 10a5h after the first instruction is executed, next pc has become 10a5h if z flag bit is set to ?1?. the range of the relative address is from +255 to ?256 because imm:9 is signed number.
S3FB42F instruction set 8- 61 lcall ? conditional subroutine call format: lcall cc:4, imm:20 operation: hs[sptr][15:0] ? current pc + 2, sptr ? sptr + 2, pc[15:0] ? imm[15:0] if the condition holds and the program size is less than 64k word. hs[sptr][19:0] ? current pc + 2, sptr ? sptr + 2, pc[19:0] ? imm:20 if the condition holds and the program size is equal to or over 64k word. pc[11:0] ? pc[11:0] + 2 otherwise. lcall instruction is used to call a subroutine whose starting address is specified by imm:20. flags: ? example: lcall l1 lcall c, l2 label l1 and l2 can be allocated to the same or other section. because this is a 2-word instruction, the saved returning address on stack is (pc + 2).
instruction set s3f b42f 8- 62 ld adr:8 ? load into memory format: ld adr:8, : gpr operation: dm[00h:adr:8] ? if eid = 0 dm[idh:adr:8] ? if eid = 1 ld adr:8 loads the value of into a memory location. the memory location is determined by the eid bit and adr:8. flags: ? example: given: idh = 01h ld 80h, r0 if eid bit of sr0 is zero, the statement ?ld 80h, r0? load value of r0 into dm[0080h], else eid bit was set to ?1?, the statement ?ld 80h, r0? load value of r0 into dm[0180h]
S3FB42F instruction set 8- 63 ld @idm ? load into memory indexed format: ld @idm, : gpr operation: (@idm) ? ld @idm loads the value of into the memory location determined by @idm. details of the @idm format and how the actual address is calculated can be found in chapter 2. flags: ? example: given r0 = 5ah, idh:idl0 = 8023h, eid = 1 ld @id0, r0 // dm[8023h] ? 5ah ld @id0 + 3, r0 // dm[8023h] ? 5ah, idl0 ? 26h ld @[id0-5], r0 // dm[801eh] ? 5ah, idl0 ? 1eh ld @[id0+4]!, r0 // dm[8027h] ? 5ah, idl0 ? 23h ld @[id0-2]!, r0 // dm[8021h] ? 5ah, idl0 ? 23h in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
instruction set s3f b42f 8- 64 ld ? load register format: ld , : gpr : gpr, spr, adr:8, @idm, #imm:8 operation: ? ld loads a value specified by into the register designated by . flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: given: r0 = 5ah, r1 = aah, idh:idl0 = 8023h, eid = 1 ld r0, r1 // r0 ? aah ld r1, idh // r1 ? 80h ld r2, 80h // r2 ? dm[8080h] ld r0, #11h // r0 ? 11h ld r0, @id0+1 // r0 ? dm[8023h], idl0 ? 24h ld r1, @[id0-2] // r1 ? dm[8021h], idl0 ? 21h ld r2, @[id0+3]! // r2 ? dm[8026h], idl0 ? 23h ld r3, @[id0-5]! // r3 ? dm[801eh], idl0 ? 23h in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
S3FB42F instruction set 8- 65 ld ? load gpr:bankd, gpr:banks format: ld , : gpr: bankd : gpr: banks operation: ? ld loads a value of a register in a specified bank (banks) into another register in a specified bank (bankd). flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: ld r2:1, r0:3 // bank1?s r2 ? bank3?s r0 ld r0:0, r0:2 // bank0?s r0 ? bank2?s r0
instruction set s3f b42f 8- 66 ld ? load gpr, tbh/tbl format: ld , : gpr : tbh/tbl operation: ? ld loads a value specified by into the register designated by . flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: given: register pair r1:r0 is 16-bit unsigned data. ldc @il // tbh:tbl ? pm[ilx:ilh:ill] ld r1, tbh // r1 ? tbh ld r0, tbl // r0 ? tbl
S3FB42F instruction set 8- 67 ld ? load tbh/tbl, gpr format: ld , : tbh/tbl : gpr operation: ? ld loads a value specified by into the register designated by . flags: ? example: given: register pair r1:r0 is 16-bit unsigned data. ld tbh, r1 // tbh ? r1 ld tbl, r0 // tbl ? r0
instruction set s3f b42f 8- 68 ld spr ? load spr format: ld , : spr : gpr operation: ? ld spr loads the value of a gpr into an spr. refer to table 3-1 for more detailed explanation about kind of spr . flags: ? example: given: register pair r1:r0 = 1020h ld ilh, r1 // ilh ? 10h ld ill, r0 // ill ? 20h
S3FB42F instruction set 8- 69 ld spr0 ? load spr0 immediate format: ld spr0, #imm:8 operation: spr0 ? imm:8 ld spr0 loads an 8-bit immediate value into spr0. flags: ? example: given: eid = 1, idb = 0 (index register bank 0 selection) ld idh, #80h // idh point to page 80h ld idl1, #44h ld idl0, #55h l d sr0, #02h the last instruction set ie (global interrupt enable) bit to ?1?. special register group 1 (spr1) registers are not supported in this addressing mode.
instruction set s3f b42f 8- 70 ldc ? load code format: ldc : @il, @il+ operation: tbh:tbl ? pm[ilx:ilh:ill] ill ? ill + 1 (@il+ only) ldc loads a data item from program memory and stores it in the tbh:tbl register pair. @il+ increase the value of ill, efficiently implementing table lookup operations. flags: ? example: ld ilx, r1 ld ilh, r2 ld ill, r3 ldc @il // loads value of pm[ilx:ilh:ill] into tbh:tbl ld r1, tbh // move data in tbh:tbl to gprs for further processing ld r0, tbl the statement ?ldc @il? do not increase, but if you use statement ?ldc @il+?, ill register is increased by one after instruction execution.
S3FB42F instruction set 8- 71 ljp ? conditional jump format: ljp cc:4, imm:20 cc:4: 4-bit condition code operation: pc[15:0] ? imm[15:0] if condition is true and the program size is less than 64k word. if the program is equal to or larger than 64k word, pc[19:0] ? imm[19:0] as long as the condition is true. there are 16 different conditions that can be used, as described in table 8-6. flags: ? note: ljp cc:4 imm:20 is a 2-word instruction whose immediate field directly specifies the target address of the jump. example: ljp c, %1 // assume current pc = 0812h %1 ld r0, r1 // address at 10a5h after the first instruction is executed, ljp directly jumps to address 10a5h if condition is true.
instruction set s3f b42f 8- 72 llnk ? linked subroutine call conditional format: llnk cc:4, imm:20 cc:4: 4-bit condition code operation: if condition is true, il[19:0] ? {pc[19:12], pc[11:0] + 2}. further, when the program is equal to or larger than 64k word, pc[19:0] ? imm[19:0] as long as the condition is true. if the program is smaller than 64k word, pc[15:0] ? imm[15:0]. there are 16 different conditions that can be used, as described in table 8-6. flags: ? note: llnk is used to conditionally to call a subroutine with the return address saved in the link register (il) without stack operation. this is a 2-word instruction. example: llnk z, %1 // address at 005ch, ilx:ilh:ill ? 00:00:5eh nop // address at 005eh %1 ld r0, r1 lret
S3FB42F instruction set 8- 73 lnk ? linked subroutine call (pseudo instruction) format: lnk cc:4, imm:20 lnk imm:12 operation: if lnks can access the target address and there is no conditional code (cc:4), lnk command is assembled to lnks (1 word instruction) in linking time, else the lnk is assembled to llnk (2 word instruction). example: lnk z, link1 // equal to ?llnk z, link1? lnk link2 // equal to ?lnks link2? nop link2: nop lret subroutines section code, abs 0a00h subroutines link1: nop lret
instruction set s3f b42f 8- 74 lnks ? linked subroutine call format: lnks imm:12 operation: il[19:0] ? {pc[19:12], pc[11:0] + 1} and pc[11:0] ? imm:12 lnks saves the current pc in the link register and jumps to the address specified by imm:12. flags: ? note: lnks is used to call a subroutine with the return address saved in the link register (il) without stack operation. example: lnks link1 // address at 005ch, ilx:ilh:ill ? 00:00:5dh nop // address at 005dh link1: nop lret
S3FB42F instruction set 8- 75 lret ? return from linked subroutine call format: lret operation: pc ? il[19:0] lret returns from a subroutine by assigning the saved return address in il to pc. flags: ? example: lnk link1 link1: nop lret ; pc[19:0] ? ilx:ilh:ill
instruction set s3f b42f 8- 76 nop ? no operation format: nop operation: no operation. when the instruction nop is executed in a program, no operation occurs. instead, the instruction time is delayed by approximately one machine cycle per each nop instruction encountered. flags: ? example: nop
S3FB42F instruction set 8- 77 or ? bit-wise or format: or , : gpr : adr:8, #imm:8, gpr, @idm operation: ? | or performs the bit-wise or operation on and and stores the result in . flags: z: set if result is zero. reset if not. n: exclusive or of v and msb of result. example: given: idh:idl0 = 031eh, eid = 1 or r0, 80h // r0 ? r0 | dm[0380h] or r1, #40h // mask bit6 of r1 or r1, r0 // r1 ? r1 | r0 or r0, @id0 // r0 ? r0 | dm[031eh], idl0 ? 1eh or r1, @[id0-1] // r1 ? r1 | dm[031dh], idl0 ? 1dh or r2, @[id0+1]! // r2 ? r2 | dm[031fh], idl0 ? 1eh or r3, @[ id0-1]! // r3 ? r3 | dm[031dh], idl0 ? 1eh in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
instruction set s3f b42f 8- 78 or sr0 ? bit-wise or with sr0 format: or sr0, #imm:8 operation: sr0 ? sr0 | imm:8 or sr0 performs the bit-wise or oper ation on sr0 and imm:8 and stores the result in sr0. flags: ? example: given: sr0 = 00000000b eid equ 01h ie equ 02h idb1 equ 04h ie0 equ 40h ie1 equ 80h or sr0, #ie | ie0 | ie1 or sr0, #00000010b in the first example, the statement ?or sr0, #eid|ie|ie0? set global interrupt(ie), interrupt 0(ie0) and interrupt 1(ie1) to ?1? in sr0. on the contrary, enabled bits can be cleared with instruction ?and sr0, #imm:8?. refer to instruction and sr0 for more detailed explanation about disabling bit. in the second example, the statement ?or sr0, #00000010b? is equal to instruction ei, which is enabling interrupt globally.
S3FB42F instruction set 8- 79 pop ? pop format: pop operation: sptr ? sptr ? 2 pop decrease sptr by 2. the top two bytes of the hardware stack are therefore invalidated. flags: ? example: given: sptr[5:0] = 001010b pop this pop instruction decrease sptr[5:0] by 2. therefore sptr[5:0] is 001000b.
instruction set s3f b42f 8- 80 pop ? pop to register format: pop : gpr, spr operation: ? hs[sptr - 1], sptr ? sptr - 1 pop copies the value on top of the stack to and decrease sptr by 1. flags: z: set if the value copied to is zero. reset if not. n: set if the value copied to is negative. reset if not. when is spr, no flags are affected, including z and n. example: pop r0 // r0 ? hs[sptr-1], sptr ? sptr-1 pop idh // idh ? hs[sptr-1], sptr ? sptr-1 in the first instruction, value of hs[sptr-1] is loaded to r0 and the second instruction ?pop idh? load value of hs[sptr-1] to register idh. refer to chapter 5 for more detailed explanation about pop operations for hardware stack.
S3FB42F instruction set 8- 81 push ? push register format: push : gpr, spr operation: hs[sptr] ? , sptr ? sptr + 1 push stores the value of on top of the stack and increase sptr by 1. flags: ? example: push r0 // hs[sptr] ? r0, sptr ? sptr + 1 push idh // hs[sptr] ? idh, sptr ? sptr + 1 in the first instruction, value of register r0 is loaded to hs[sptr-1] and the second instruction ?push idh? load value of register idh to hs[sptr-1]. current hs pointed by stack point sptr[5:0] be emptied. refer to chapter 5 for more detailed explanation about push operations for hardware stack.
instruction set s3f b42f 8- 82 ret ? return from subroutine format: ret operation: pc ? hs[sptr - 2], sptr ? sptr ? 2 ret pops an address on the hardware stack into pc so that control returns to the subroutine call site. flags: ? example: given: sptr[5:0] = 001010b calls wait // address at 00120h wait: nop // address at 01000h nop nop nop nop ret after the first instruction calls execution, ?pc+1?, 0121h is loaded to hs[5] and hardware stack pointer sptr[5:0] have 001100b and next pc became 01000h. the instruction ret pops value 0121h on the hardware stack hs[sptr-2] and load to pc then stack pointer sptr[[5:0] became 001010b.
S3FB42F instruction set 8- 83 rl ? rotate left format: rl : gpr operation: c ? [7], ? {[6:0], [7]} rl rotates the value of to the left and stores the result back into . the original msb of is copied into carry (c). flags: c: set if the msb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r0 = 01001010b, r1 = 10100101b rl r0 // n flag is set to ?1?, r0 ? 10010100b rl r1 // c flag is set to ?1?, r1 ? 01001011b
instruction set s3f b42f 8- 84 rlc ? rotate left with carry format: rlc : gpr operation: c ? [7], ? {[6:0], c} rlc rotates the value of to the left and stores the result back into . the original msb of is copied into carry (c), and the original c bit is copied into [0]. flags: c: set if the msb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r2 = a5h, if c = 0 rlc r2 // r2 ? 4ah, c flag is set to ?1? rl r0 rlc r1 in the second example, assuming that register pair r1:r0 is 16-bit number, then rl and rlc are used for 16-bit rotate left operation. but note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit decrement, take care of the change of z flag.
S3FB42F instruction set 8- 85 rr ? rotate right format: rr : gpr operation: c ? [0], ? {[0], [7:1]} rr rotates the value of to the right and stores the result back into . the original lsb of is copied into carry (c). flags: c: set if the lsb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r0 = 01011010b, r1 = 10100101b rr r0 // no change of flag, r0 ? 00101101b rr r1 // c and n flags are set to ?1?, r1 ? 11010010b
instruction set s3f b42f 8- 86 rrc ? rotate right with carry format: rrc : gpr operation: c ? [0], ? {c, [7:1]} rrc rotates the value of to the right and stores the result back into . the original lsb of is copied into carry (c), and c is copied to the msb. flags: c: set if the lsb of (before rotating) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after rotating) is 1. reset if not. example: given: r2 = a5h, if c = 0 rrc r2 // r2 ? 52h, c flag is set to ?1? rr r0 rrc r1 in the second example, assuming that register pair r1:r0 is 16-bit number, then rr and rrc are used for 16-bit rotate right operation. but note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit decrement, take care of the change of z flag.
S3FB42F instruction set 8- 87 sbc ? subtract with carry format: sbc , : gpr : adr:8, gpr operation: ? + ~ + c sbc computes ( - ) when there is carry and ( - - 1) when there is no carry. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. n: set if result is negative. reset if not. example: sbc r0, 80h // if eid = 0, r0 ? r0 + ~dm[0080h] + c // if eid = 1, r0 ? r0 + ~dm[idh:80h] + c sbc r0, r1 // r0 ? r0 + ~r1 + c sub r0, r2 sbc r1, r3 in the last two instructions, assuming that register pair r1:r0 and r3:r2 are 16-bit signed or unsigned numbers. even if the result of ?add r0, r2? is not zero, zero (z) flag can be set to ?1? if the result of ?sbc r1,r3? is zero. note that zero (z) flag do not exactly reflect result of 16-bit operation. therefore when programming 16-bit addition, take care of the change of z flag.
instruction set s3f b42f 8- 88 sl ? shift left format: sl : gpr operation: c ? [7], ? {[6:0], 0} sl shifts to the left by 1 bit. the msb of the original is copied into carry (c). flags: c: set if the msb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after shifting) is 1. reset if not. example: given: r0 = 01001010b, r1 = 10100101b sl r0 // n flag is set to ?1?, r0 ? 10010100b sl r1 // c flag is set to ?1?, r1 ? 01001010b
S3FB42F instruction set 8- 89 sla ? shift left arithmetic format: sla : gpr operation: c ? [7], ? {[6:0], 0} sla shifts to the left by 1 bit. the msb of the original is copied into carry (c). flags: c: set if the msb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. v: set if the msb of the result is different from c. reset if not. n: set if the msb of (after shifting) is 1. reset if not. example: given: r0 = aah sla r0 // c, v, n flags are set to ?1?, r0 ? 54h
instruction set s3f b42f 8- 90 sr ? shift right format: sr : gpr operation: c ? [0], ? {0, [7:1]} sr shifts to the right by 1 bit. the lsb of the original (i.e., [0]) is copied into carry (c). flags: c: set if the lsb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after shifting) is 1. reset if not. example: given: r0 = 01011010b, r1 = 10100101b sr r0 // no change of flags, r0 ? 00101101b sr r1 // c flag is set to ?1?, r1 ? 01010010b
S3FB42F instruction set 8- 91 sra ? shift right arithmetic format: sra : gpr operation: c ? [0], ? {[7], [7:1]} sra shifts to the right by 1 bit while keeping the sign of . the lsb of the original (i.e., [0]) is copied into carry (c). flags: c: set if the lsb of (before shifting) is 1. reset if not. z: set if result is zero. reset if not. n: set if the msb of (after shifting) is 1. reset if not. note: sra keeps the sign bit or the msb ([7]) in its original position. if sra is executed ?n? times, n significant bits will be set, followed by the shifted bits. example: given: r0 = 10100101b sra r0 // c, n flags are set to ?1?, r0 ? 11010010b sra r0 // n flag is set to ?1?, r0 ? 11101001b sra r0 // c, n flags are set to ?1?, r0 ? 11110100b sra r0 // n flags are set to ?1?, r0 ? 11111010b
instruction set s3f b42f 8- 92 stop ? stop operation (pseudo instruction) format: stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter the stop mode. in the stop mode, the contents of the on-chip cpu registers, peripheral registers, and i/o port control and data register are retained. a reset operation or external or internal interrupts can release stop mode. the stop instruction is a pseudo instruction. it is assembled as ?sys #0ah?, which generates the syscp[7-0] signals. these signals are decoded and stop the operation. note: the next instruction of stop instruction is executed, so please use the nop instruction after the stop instruction. example: stop nop nop nop in this example, the nop instructions provide the necessary timing delay for oscillation stabilization before the next instruction in the program sequence is executed. refer to the timing diagrams of oscillation stabilization, as described in figure 18-3, 18-4
S3FB42F instruction set 8- 93 sub ? subtract format: sub , : gpr : adr:8, #imm:8, gpr, @idm operation: ? + ~ + 1 sub adds the value of with the 2's complement of to perform subtraction on and flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. v: set if overflow is generated. reset if not. n: set if result is negative. reset if not. example: given: idh:idl0 = 0150h, dm[0143h] = 26h, r0 = 52h, r1 = 14h, eid = 1 sub r0, 43h // r0 ? r0 + ~dm[0143h] + 1 = 2ch sub r1, #16h // r1 ? feh, n flag is set to ?1? sub r0, r1 // r0 ? r0 + ~r1 + 1 = 3eh sub r0, @id0+1 // r0 ? r0 + ~dm[0150h] + 1, idl0 ? 51h sub r0, @[id0-2] // r0 ? r0 + ~dm[014eh] + 1, idl0 ? 4eh sub r0, @[id0+3]! // r0 ? r0 + ~dm[0153h] + 1, idl0 ? 50h sub r0, @[id0-2]! // r0 ? r0 + ~dm[014eh] + 1, idl0 ? 50h in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. the example in the sbc description shows how sub and sbc can be used in pair to subtract a 16-bit number from another. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
instruction set s3f b42f 8- 94 swap ? swap format: swap , : gpr : spr operation: ? , ? swap swaps the values of the two operands. flags: ? note: among the sprs, sr0 and sr1 can not be used as . example: given: idh:idl0 = 8023h, r0 = 56h, r1 = 01h swap r1, idh // r1 ? 80h, idh ? 01h swap r0, idl0 // r0 ? 23h, idl0 ? 56h after execution of instructions, index registers idh:idl0 (id0) have address 0156h.
S3FB42F instruction set 8- 95 sys ? system format: sys #imm:8 operation: sys generates syscp[7:0] and nsysid signals. flags: ? note: mainly used for system peripheral interfacing. example: sys #0ah sys #05h in the first example, statement ?sys #0ah? is equa l to stop instruction and second example ?sys #05h? is equal to idle instruction. this instruction does nothing but increase pc by one and generates syscp[7:0] and nsysid signals.
instruction set s3f b42f 8- 96 tm ? test multiple bits format: tm , #imm:8 : gpr operation: tm performs the bit-wise and operation on and imm:8 and sets the flags. the content of is not changed. flags: z: set if result is zero. reset if not. n: set if result is negative. reset if not. example: given: r0 = 01001101b tm r0, #0010001 0b // z flag is set to ?1?
S3FB42F instruction set 8- 97 xor ? exclusive or format: xor , : gpr : adr:8, #imm:8, gpr, @idm operation: ? ^ xor performs the bit-wise exclusive-or operation on and and stores the result in . flags: z: set if result is zero. reset if not. n: set if result is negative. reset if not. example: given: idh:idl0 = 8080h, dm[8043h] = 26h, r0 = 52h, r1 = 14h, eid = 1 xor r0, 43h // r0 ? 74h xor r1, #00101100b // r1 ? 38h xor r0, r1 // r0 ? 46h xor r0, @id0 // r0 ? r0 ^ dm[8080h], idl0 ? 81h xor r0, @[id0-2] // r0 ? r0 ^ dm[807eh], idl0 ? 7eh xor r0, @[id0+3]! // r0 ? r0 ^ dm[8083h], idl0 ? 80h xor r0, @[id0-5]! // r0 ? r0 ^ dm[807bh], idl0 ? 80h in the last two instructions, the value of idh:idl0 is not changed. refer to table 8-5 for more detailed explanation about this addressing mode. idm = idx+offset:5, [idx-offset:5], [idx+offset:5]!, [idx-offset:5]! (idx = id0 or id1)
instruction set s3f b42f 8- 98 notes
S3FB42F pll (phase locked loop) 9- 1 9 pll (phase locked loop) overview S3FB42F builds clock synthesizer for system clock generation, which can operate external crystal (32.768 khz) for reference, using internal phase-locked loop (pll) and voltage-controlled oscillator (vco). for real-time clock, 32.768 khz crystal is recommended to use. system clock circuit the system clock circuit has the following component: external crystal oscillator, 32.768 khz. phase comparator, noise filter and frequency divider. pll control circuit: control register, pllcon and pll frequency divider data register. x-tal oscillator low-pass filter vco phase comparator frequency divider clock control circuit to cpu clock, rtc i 2 c, other peripheral fxm fxm pllcon.2 fx i 2 s, usb cz cp pllcon.0 1/2 fvco figure 9-1. simple circuit diagram
pll (phase locked loop) S3FB42F 9- 2 pll register table 9-1. pll register description register address r/w/c description pllcon aeh r/w pll control register plldata, h ac, adh r/w pll frequency divider data register pll control register (pllcon) register address r/w description reset value pllcon 0xae r/w pll control register 00h bit bit name description [0] enable this bit control the operation of pll block. when this bit is set as "1", phase comparater, filter and vco are activated. [1] f vco output this bit enable or disable the f vco output through p8.1 pin. [2] clock source selection this bit control the selection of f xm or f vco clock. when this bit is set as "1", f vco , pll output frequency is selected as main clock oscillator. [7:3] ? ? pll frequency divider data register (plldata) register address r/w description reset value plldatah,l 0xad, 0xac r/w pll frequency divider data register ? bit bit name description [15:14] postscaler div post- scaler divider value [13:12] data pll frequency divider data (bit 11 to bit 10) these bits have the bit 11 to bit10 of the frequency divider data register setting value. [11:10] ? always "11" [9:0] data pll frequency divider data (bit 9 to bit 0) these bits have the bit 11 to bit10 of the frequency divider data register setting value. this frequency divider circuit divide the vco frequency, f vco , down to reference frequency for phase comparator. the frequency divider data register setting value is like below. 0x1d60: f pll , f usb = 45.158 mhz for 44.1 khz 0x1db6: f pll , f usb = 48 mhz 0x1dda: f pll , f usb = 49.152 mhz for 48 khz
S3FB42F pll (phase locked loop) 9- 3 the pll frequency divider data is n = f vco f xm ? 2 where f vco is the frequency that user wants to obtain and f xm is the main oscillation frequency ( typ. 32.768 khz). lsb msb pll frequency divider data register (plldata) adh, r/w post-scaler divider value always "11" .15 .14 .13 .12 .11 .10 .9 .8 d11 d10 d9 d8 lsb msb ach, r/w .7 .6 .5 .4 .3 .2 .1 .0 d5 d4 d1 d0 d7 d6 d3 d2 figure 9-2. pll frequency divider data register (plldata)
pll (phase locked loop) S3FB42F 9- 4 system control circuit table 9 - 2. system control circuit register description register address r/w description osccon 03h r/w oscillator control register pcon 02h r/w power control register oscillator control register (osccon) register address r/w description reset value osccon 0x03 r/w oscillator control register 00h bit bit name description [0] system clock source selection system ( fxx) clock source selection bit: 0 = main system clock oscillator ( fx) select (pll system oscillator or xout) 1 = subsystem clock oscillator ( fxt or fxm) select. [1] ? ? [2] sub-clock control sub-clock control bit: 0 = sub oscillator run. ( fxt) 1 = sub oscillator stop. [3] main-clock control main-clock control bit: 0 = main-clock oscillator run.( fxm) 1 = main-clock oscillator stop. [7:4] ? ? note: after setting want ed clock selection, fmcon must be set to proper value.
S3FB42F pll (phase locked loop) 9- 5 power control register (pcon) register address r/w description reset value pcon 0x02 r/w power control register 04h bit bit name description [7:6] usb wait selection usb stretch cycle selection bits: 00 = 15 cycle stretch 10 = 14 cycle stretch 01 = 13 cycle stretch 11 = 12 cycle stretch [5] usb high-low selection usb high or low width stretch select. 0 = low width stretch 1 = high width stretch [4:3] ? ? [2:0] system clock selection system clock selection bits: 000 = fxx/128 001 = fxx/64 010 = fxx/32 011 = fxx/16 100 = fxx/8 101 = fxx/4 110 = fxx/2 111 = fxx/1
pll (phase locked loop) S3FB42F 9- 6 int stop release stop release int main-system oscillator circuit selector 1 f x fxt sub-system oscillator & pll circuit osccon.2 stop fxx selector 2 idle/stop control circuit cpu stop signal by idle or stop cpu pcon.2-.0 syscp [7-0] idle or stop instruction makes syscp [7-0] signal note: the main-oscillator of s3fb41d. osccon.3 osccon.0 basic timer timer/counters watch timer (fxx/128) sio uart a/d converter stop 1/1-1/4096 frequency dividing circuit 1/1 1/16 1/32 1/64 1/128 1/2 1/4 1/8 oscillation stop signal watch timer usb iic main stop sub/main figure 9-3. system clock circuit diagram
S3FB42F reset and p ower-down 10- 1 10 reset and power-do wn overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings S3FB42F into a known operating status. for the time for cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. for the minimum time interval, see the electrical characteristic. in summary, the following sequence of events occurs during a reset operation: ? all interrupts are disabled. ? the watchdog function (basic timer) is enabled. ? ports are set to input mode except po rt 1 which is set to output mode. ? peripheral control and data registers are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 00000h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 00000h is fetched and executed. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing ? 1010 0101b ? to the wdten register.
reset and power-down S3FB42F 10- 2 notes
S3FB42F i/o ports 11 - 1 11 i/o ports port data registers all thirteen port data registers have the identical structure shown in figure 11-1 below.: table 11-1. port data register summary register name mnemonic address reset value r/w port 0 data register p0 10h 00h r/w port 1 data register p1 11h 00h r/w port 2 data register p2 12h 00h r/w port 3 data register p3 13h 00h r/w port 4 data register p4 14h 00h r/w port 5 data register p5 15h xxh r port 6 data register p6 16h 00h r/w port 7 data register p7 17h 00h r/w port 8 data register p8 18h 00h r/w port 9 data register p9 19h 00h r/w .7 .6 .5 .4 .3 .2 .1 .0 lsb msb i/o port n data register (n = 0-9) n = 0-4, 6-9: r/w n = 5: r pn.0 pn.1 pn.2 pn.4 pn.3 pn.5 pn.6 pn.7 figure 11-1. port data register structure
i/o ports S3FB42F 11 - 2 port control registers port 0 control register (p0con) register address r/w description reset value p0con 0x20 r/w port 0 control register 00h bit setting description [7:0] 0 or 1 port 0 setting 0: normal c-mos input mode 1: normal c-mos output mode note : the parallel port control (ppconl.1) register can assign port 0 to parallel printer port's data bus mode, which is not effected by p0con setting. port 1 control register (p1con) register address r/w description reset value p1con 0x21 r/w port 1 control register 00h bit setting description [4:0] 0 or 1 p1.0, p1.1, p1.2, p1.3 or p1.4 setting 0: normal c-mos input mode 1: normal c-mos output mode note : the parallel port control (ppconl.1) register can assign port 1 to parallel printer port's control bus mode, which is not effected by p1con.0-5 setting.
S3FB42F i/o ports 11 - 3 port 2 control low register (p2conl) register address r/w description reset value p2conl 0x22 r/w port 2 control low register 00h bit setting description [0] 0 or 1 p2.0 setting 0: schmitt trigger input mode or taclk input mode 1: normal c-mos output mode [1] 0 or 1 p2.1 setting 0: schmitt trigger input mode or tbclk input mode 1: normal c-mos output mode [3:2] 0 or 1 p2.2 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: serial data output (so) for sio (sp1) (c-mos output mode) 11: serial data output (so) for sio (sp1) (n-channel open drain output mode) [5:4] 0 or 1 p2.3 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: serial data output (sck) for sio (sp1) (c-mos output mode) 11: serial data output (sck) for sio (sp1) (n-channel open drain output mode) [6] 0 or 1 p2.4 setting 0: schmitt trigger input mode or rx input mode in uart 1: normal c-mos output mode [7] ? ?
i/o ports S3FB42F 11 - 4 port 2 control high register (p2conh) register address r/w description reset value p2conh 0x23 r/w port 2 control high register 30h bit setting description [1:0] 0 or 1 p2.5 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: tx output mode in uart 11: invalid [2] 0 or 1 p2.6 setting 0: schmitt trigger input mode 1: normal c-mos output mode [3] 0 or 1 p2.7 setting 0: schmitt trigger input mode 1: normal c-mos output mode [4] 0 or 1 p6.6 pull-up resistor setting 0: disable pull-up resistor 1: enable pull-up resistor (reset value) [5] 0 or 1 p6.7 pull-up resistor setting 0: disable pull-up resistor 1: enable pull-up resistor (reset value) note : the pull-up resistors of p6.6 and p6.7can be assigned by p2conh.4, 5.
S3FB42F i/o ports 11 - 5 port 3 control low register (p3conl) register address r/w description reset value p3conl 0x24 r/w port 3 control low register 00h bit setting description [1:0] 0 or 1 p3.0 setting 00: schmitt trigger input mode, serial data input (si) for sio (spi) 01: normal c-mos output mode 10: n- ch open drain output mode 11: n- ch open drain output mode [3:2] 0 or 1 p3.1 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: serial data output (so) for sio(sp1) (cmos output mode) 11: serial data output (so) for sio(sp1) (n-channel open-drain output mode) [5:4] 0 or 1 p3.2 setting 00: schmitt trigger input mode, serial clock input mode (sck) for sio (spi) 01: normal c-mos output mode 10: serial data output (sck) for sio(sp1) (cmos output mode) 11: serial data output (sck) for sio(sp1) (n-channel open-drain output mode) [7:6] 0 or 1 p3.3 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: serial clock port (scl) for i 2 c ( schmitt trigger input or output mode) 11: serial clock port (scl) for i 2 c ( schmitt trigger input or n- ch open drain output mode)
i/o ports S3FB42F 11 - 6 port 3 control high register (p3conh) register address r/w description reset value p3conh 0x25 r/w port 3 control high register 00h bit setting description [1:0] 0 or 1 p3.4 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: serial data port (sda) for i 2 c ( schmitt trigger input/ c-mos output mode) 11: serial data port (sda) for i 2 c ( schmitt trigger input and n- ch open drain output mode) [3:2] 0 or 1 p3.5 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: n- ch open drain output mode 11: n- ch open drain output mode [5:4] 0 or 1 p3.6 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: n- ch open drain output mode 11: n- ch open drain output mode [7:6] 0 or 1 p3.7 setting 00: schmitt trigger input mode 01: normal c-mos output mode 10: n- ch open drain output mode 11: n- ch open drain output mode port 3 pull-up register (p3pur) register address r/w description reset value p3pur 0x26 r/w port 3 pull-up resistor enable register 00h bit setting description [7:0] 0 or 1 p3.0-3.7 pull-up resistor setting 0: disable pull-up resistor 1: enable pull-up resistor
S3FB42F i/o ports 11 - 7 port 4 control register (p4con) register address r/w description reset value p4con 0x30 r/w port 4 control register 00h bit setting description [1:0] 0 or 1 p4.0 setting 00: schmitt trigger input mode or external interrupt 9 input 01: schmitt trigger input mode or external interrupt 9 input with pull-up resistor 10: normal c-mos output mode 11: normal c-mos output mode [3:2] 0 or 1 p4.1 setting 00: schmitt trigger input mode or external interrupt 8 input 01: schmitt trigger input mode or external interrupt 8 input with pull-up resistor 10: normal c-mos output mode 11: normal c-mos output mode [5:4] 0 or 1 p4.2 setting 00: schmitt trigger input mode 01: schmitt trigger input mode with pull-up resistor 10: normal c-mos output mode 11: normal c-mos output mode port 4 interrupt control register (p4intcon) register address r/w description reset value p4intcon 0x31 r/w port 4 interrupt control register 00h bit setting description [1:0] 0 or 1 setting the external interrupt enable of p4.1, p4.0 (int8-9) 0: disable external interrupt 1: enable external interrupt
i/o ports S3FB42F 11 - 8 port 4 interrupt mode register (p4intmod) register address r/w description reset value p4intmod 0x32 r/w port 4 interrupt mode register 00h bit setting description [1:0] [3:2] 0 or 1 setting the external interrupt mode of p4. 0 (int9) and p4.1 (int8) 00: falling edge interrupt enable 01: rising edge interrupt enable 10: high level interrupt enable 11: low level interrupt enable port 5 control register (p5con) register address r/w description reset value p5con 0x28 r/w port 5 control register 00h bit setting description [0] 0 or 1 p5.0 setting 0: normal c-mos input mode or external interrupt 0 input 1: adc0 input mode [1] 0 or 1 p5.1 setting 0: normal c-mos input mode or external interrupt 1 input 1: adc1 input mode [2] 0 or 1 p5.2 setting 0: normal c-mos input mode or external interrupt 2 input 1: adc2 input mode [3] 0 or 1 p5.3 setting 0: normal c-mos input mode or external interrupt 3 input 1: adc3 input mode [4] 0 or 1 p5.4 setting 0: normal c-mos input mode or external interrupt 4 input 1: adc4 input mode [5] 0 or 1 p5.5 setting 0: normal c-mos input mode or external interrupt 5 input 1: adc5 input mode
S3FB42F i/o ports 11 - 9 port 5 pull-up register (p5pur) register address r/w description reset value p5pur 0x29 r/w port 5 pull-up resistor enable register 00h bit setting description [5:0] 0 or 1 p5.0-5.5 pull-up resistor setting 0: disable pull-up resistor 1: enable pull-up resistor port 5 interrupt control register (p5intcon) register address r/w description reset value p5intcon 0x2a r/w port 5 interrupt control register 00h bit setting description [5:0] 0 or 1 setting the external interrupt enable of p5.0-p5.5 (int0-5) 0: disable external interrupt 1: enable external interrupt port 5 external interrupt pending register (eintpnd) register address r/w description reset value eintpnd 0x2d r/w port 5 external interrupt pending register 00h bit setting description [5:0] 0 or 1 setting the external interrupt pending bit of p5.0-p5.5 (int0-5) 0: interrupt is not pending when read. ( when write, pending bit is clear ) 1: interrupt is pending when read. ( when write, pending bit is not effected )
i/o ports S3FB42F 11 - 10 port 5 interrupt mode low register (p5intmodl) register address r/w description reset value p5intmodl 0x2b r/w port 5 interrupt mode low register 00h bit setting description [1:0] [3:2] [5:4] [7:6] 0 or 1 setting the external interrupt mode of p5.0(int0)/p5.1(int1)/p5.2(int2)/p5.3(int3 ) 00: falling edge interrupt enable 01: rising edge interrupt enable 10: falling or rising edge interrupt enable 11: invalid value port 5 interrupt mode high register (p5intmodh) register address r/w description reset value p5intmodh 0x2c r/w port 5 interrupt mode high register 00h bit setting description [1:0] [3:2] 0 or 1 setting the external interrupt mode of p5.4(int4)/p5.5(int5) 00: falling edge interrupt enable 01: rising edge interrupt enable 10: falling or rising edge interrupt enable 11: invalid value
S3FB42F i/o ports 11 - 11 port 6 control register (p6con) register address r/w description reset value p6con 0x34 r/w port 6 control register 00h bit setting description [0] 0 or 1 p6.0 setting 0: normal c-mos input mode 1: normal c-mos output mode; chip enable 1 ( ce1 ) for smartmedia [1] 0 or 1 p6.1 setting 0: normal c-mos input mode 1: normal c-mos output mode; chip enable 0 ( ce0 ) for smartmedia [2] 0 or 1 p6.2 setting 0: normal c-mos input mode 1: normal c-mos output mode; command latch enable (cle) for smartmedia [3] 0 or 1 p6.3 setting 0: normal c-mos input mode 1: normal c-mos output mode; address latch enable (ale) for smartmedia [4] 0 or 1 p6.4 setting 0: normal c-mos input mode; ready/busy (r/ b ) for smartmedia 1: normal c-mos output mode [5] 0 or 1 p6.5 setting 0: normal c-mos input mode 1: normal c-mos output mode; write protect (wp) for smartmedia [6] 0 or 1 p6.6 setting 0: normal c-mos input mode 1: normal c-mos output mode; read enable ( re ) for smartmedia [7] 0 or 1 p6.7 setting 0: normal c-mos input mode 1: normal c-mos output mode; write enable ( we ) for smartmedia notes: 1. when the smartmedia control (smcon) register is enabled, the access of port 7 generate the read or write strobe signal to the smartmedia memory. however, other pins for smartmeida interface should set interface condition and generate interface signal by cpu instruction. this provide the customer with the high speed memory access time, small chip size and small power consumption together. 2. the pull-up resistors of p6.6 and p6.7can be assigned by p2conh.4, 5.
i/o ports S3FB42F 11 - 12 port 2 control high register or p6pur (p2conh) register address r/w description reset value p2conh 0x23 r/w port 2 control high register 30h bit setting description [3:0] 0 or 1 p2.5, 6,7 setting (release see the p2conh register) [4] 0 or 1 p6.6 pull-up resistor setting 0: disable pull-up resistor 1: enable pull-up resistor (reset value) [5] 0 or 1 p6.7 pull-up resistor setting 0: disable pull-up resistor 1: enable pull-up resistor (reset value) port 7 control register (p7con) register address r/w description reset value p7con 0x35 r/w port 7 control register 00h bit setting description [7:0] 0 or 1 port 7 setting 0: normal c-mos input mode 1: normal c-mos output mode note : when the smartmedia control (smcon) register is enabled, the read or write operation for port 7 activate the ecc block. the ecc block capture the data on port 7 access and execute ecc operation.
S3FB42F i/o ports 11 - 13 port 8 control register (p8con) register address r/w description reset value p8con 0x36 r/w port 8 control register 00h bit setting description [0] 0 or 1 p8.0 setting 0: schmitt trigger level input mode 1: normal c-mos output mode [1] 0 or 1 p8.1 setting 0: schmitt trigger level input mode 1: normal c-mos output mode [2] 0 or 1 p8.2 setting 0: schmitt trigger level input mode 1: normal c-mos output mode [3] 0 or 1 p8.3 setting 0: schmitt trigger level input mode 1: normal c-mos output mode note : the parallel port control (ppconh.1) register can assign port 8 to parallel printer port's control bus mode, which is not effected by p8con.0-3 setting.
i/o ports S3FB42F 11 - 14 port 9 control register (p9con) register address r/w description reset value p9con 0x37 r/w port 9 control register 00h bit setting description [0] 0 or 1 p9.0 setting 0: schmitt trigger input mode, word selection input mode (ws0) 1: normal c-mos output mode, word selection output mode (ws0) [1] 0 or 1 p9.1 setting 0: schmitt trigger input mode, bit shift clock input mode (sclk0) 1: normal c-mos output mode, bit shift clock output mode (sclk0) [2] 0 or 1 p9.2 setting 0: schmitt trigger input mode, shift data input mode (sd0) 1: normal c-mos output mode, shift data output mode (sd0) [3] 0 or 1 p9.3 setting 0: schmitt trigger input mode, word selection input mode (ws1) 1: normal c-mos output mode, word selection output mode (ws1) [4] 0 or 1 p9.4 setting 0: schmitt trigger input mode, bit shift clock input mode (sclk1) 1: normal c-mos output mode, bit shift clock output mode (sclk1) [5] 0 or 1 p9.5 setting 0: schmitt trigger input mode, shift data input mode (sd1) 1: normal c-mos output mode, shift data output mode (sd1) [6] 0 or 1 p9.6 setting 0: schmitt trigger input mode 1: normal c-mos output mode, master clock output mode (mclk) for iis0 note: the direction of ws and sclk port is decided by iiscon.3, master, where is the output mode in the master mode or the input mode in the slave mode. also, the direction of sd port is decided by iiscon.2, trans , where is the output mode in the transmitter mode or the input mode in the receive mode.
S3FB42F basic timer 12- 1 12 basic timer overview lsb msb basic timer control register (btcon) 0ch, r/w basic timer input clock selection bits: 000 = fxx/2 001 = fxx/4 010 = fxx/16 011 = fxx/32 100 = fxx/128 101 = fxx/256 110 = fxx/1024 111 = fxx/2048 basic timer counter clear bits when basic timer interrupt is enabled: 0 = no effect 1 = clear btcnt when write. basic timer interrupt enable bit 0 = btint disable 1 = btint enable note: after the reset, btcon.2 is set to "0" and basic timer input clock is fixed at fxx/2048. if you want to change the basic timer input clock, you should set the btcon.2 to "1", and then the btcon .6 .5 .4 are writable by s/w. not used basic timer input clock selection enable bit: 0 = basic timer input clock is fixed at fxx/2048 1 = btcon .6 .5 .4 are writable by s/w .7 .6 .5 .4 .3 .2 .1 .0 not used figure 12-1. basic timer control register (btcon)
basic timer S3FB42F 12- 2 watchdog timer lsb msb watchdog timer control register (wdtcon) 0fh, r/w not used watchdong timer clear bit: 1010 = clear watchdog timer counter other values = don't care .7 .6 .5 .4 .3 .2 .1 .0 figure 12-2. watchdog timer control register (wdtcon) lsb msb watchdog timer enable register (wdten) 0eh, r/w watchdog timer enable bit: 10100101 = disable watchdog timer other values = enable watchdog timer .7 .6 .5 .4 .3 .2 .1 .0 figure 12-3. watchdog timer enable register (wdten)
S3FB42F basic timer 12- 3 block diagram 8-bit basic counter (read only) bt int reset or stop data bus wdt enable cpu start signal (power down release) clear btcon.0 btcon.1 bt ovf btcon .6 .5 .4 3-bit watchdog timer counter clear wdtcon .3 .2 .1 .0 reset stop idle 1/2048 1/1024 1/256 1/128 1/32 1/16 1/4 1/2 bit6 data bus reset ovf m u x mux 1/2048 btcon.2 figure 12-4. basic timer & watchdog timer functional block diagram
basic timer S3FB42F 12- 4 notes
S3FB42F real timer ( watch timer) 13- 1 13 real timer (watch timer) overview real time clock functions include real-time and watch-time measurement and interval timing for the system clock. to start real time clock operation, set bit 1 of the real time clock(watch timer) control register, wtcon.1 to "1". after the real time clock starts and elapses a time, the real time clock interrupt is automatically set to "1", and interrupt requests commence in 3.91ms, or, 0.5 and 1-second intervals. the watch timer can generate a steady 0.5 khz, 1 khz, 2 khz or 4 khz signal to the buzzer output. by setting wtcon.3 and wtcon.2 to "11b", the real time clock will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. ? real-time and watch-time measurement ? using a main oscillator or sub oscillator clock source ? buzzer output frequency generator ? timing tests in high-speed mode table 13-1. watch timer control register (wtcon): 8-bit r/w bit name values function address wtcon.7 ? not used 4ch wtcon.6 ? not used wtcon .5-.4 0 0 0.5 khz buzzer (buz) signal output (when wtcon.1 = "1") 0 1 1 khz buzzer (buz) signal output (when wtcon.1 = "1") 1 0 2 khz buzzer (buz) signal output (when wtcon.1 = "1") 1 1 4 khz buzzer (buz) signal output (when wtcon.1 = "1") wtcon .3-.2 0 0 set watch timer interrupt to 1s (when wtcon.1 = "1") 0 1 set watch timer interrupt to 0.5s (when wtcon.1 = "1") 1 0 set watch timer interrupt to 0.25s (when wtcon.1 = "1") 1 1 set watch timer interrupt to 3.91ms (when wtcon.1 = "1") wtcon.1 0 select fxx/128 as the watch timer clock 1 select x out as the watch timer clock wtcon.0 0 stop watch timer counter; clear frequency dividing circuits 1 run watch timer counter
real timer (watch timer) S3FB42F 13- 2 watch timer circuit diagram frequency ddividing circuit clock selector wtcon .1 wtcon .0 wtcon .2 .3 enable/disable fw (32768 hz) fw/2 7 fw/2 13 fw/2 14 fw/2 15 (1 h z ) fw/2 3 (4 khz) fw/2 4 (2 khz) fw/2 5 (1 khz) fw/2 6 (0.5 khz) fx = main system clock (f vco or fxm) fxx = selected system clock (fx or fxt) fxt = sub system clock fxm = main osillator output fvco = pll vco output mux selector circuit wtcon .4 .5 buzzer output wt int overflow fxx/128 fxm (p2.3) figure 13-1. watch timer circuit diagram
S3FB42F 16-bit time r (8-bit timer a & b) 14- 1 14 16-bit timer (8-bit timer a & b) overview this 16-bit timer has two modes. one is 16-bit timer mode and the other is two 8-bit timer mode. when bit 2 of tbcon is "1", it operates with the 16-bit timer. when it is "0", it operates with two 8-bit timers. when it operates with the 16-bit timer, the tbcnt?s clock source can be selected by setting tbcon.3. if tbcon.3 is "0", the timer a?s overflow would be tbcnt?s clock source. if it is "1", the timer a?s interval out would be tbcnt?s clock source. the timer clock source can be selected by s/w. lsb msb timer a control register (tacon) 40h, r/w, reset: 00h timer a counter clear bit: 0 = no effect 1 = clear the timer a (when write) timer a input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 1x0 = fxx/1 1x1 = taclk not used not used timer a operation enable bit: 0 = stop 1 = run .7 .6 .5 .4 .3 .2 .1 .0 figure 14-1. timer a control register (tacon)
16-bit timer (8-bit timer a & b) s3fb42 f 14- 2 lsb msb timer b control register (tbcon) 44h, r/w, reset: 00h timer b counter clear bit: 0 = no effect 1 = clear the timer b (when write) timer b input clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 1x0 = fxx/4 1x1 = tbclk not used timer b operation enable bit: 0 = stop 1 = run timer b mode selection bits: 0 = 8-bit operation mode 1 = 16-bit operation mode 16-bit operation timer b clock input selection bit: 0 = timer a overflow out 1 = timer a interval out note: at 16-bit operation mode 16-bit counter clock input is selected by tacon .6, .5, .4 .7 .6 .5 .4 .3 .2 .1 .0 figure 14-2. timer b control register (tbcon)
S3FB42F 16-bit time r (8-bit timer a & b) 14- 3 m u x 1 fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 taclk tbcon 2 timer a data register (read/write) mux 0 tacon 0 tacon 6, 5, 4 timer a buffer register 8-bit comparator data bus tacnt (8-bit up-counter, read only) tacon 1 tbcon 1 mux tbcon 2 tbcon 3 mux 1 0 tbcon 6, 5, 4 8-bit comparator tbcon 3 tbcnt (8-bit up-counter, read olny) timer b buffer register timer b data register (read/write) data bus 1 0 and 1 means mux control input tbint tbcon 1 tbcon 0 tbcon 2 0 mux tbcon 3 tbcon 2 m u x fxx/1024 fxx/256 fxx/64 fxx/8 fxx/4 tbclk mux 1 0 mux 0 1 8 8 taout interval output gen. taint tbcon 2 clear clear tbcon 0 figure 14-3. timer a, b function block diagram
16-bit timer (8-bit timer a & b) s3fb42 f 14- 4 notes
S3FB42F serial i/o interface 15- 1 15 serial i/o interface overview lsb msb serial i/o module control registers siocon: 50h, r/w, reset: 00h sio operation enable bit: 0 = disable sio 1 = enable sio not used sio shift clock select bit: 0 = internal clock (p.s clock) 1 = external clock (sck) data direction control bit: 0 = msb-first 1 = lsb-first sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift operation enable bit: 0 = disable shifter and clock 1 = enable shfter and clock sio mode selction bit: 0 = rececive-only mode 1 = transmit/receive mode shift clock edge selction bit: 0 = tx falling edges, rx at rising 1 = tx rising edges, rx at falling .7 .6 .5 .4 .3 .2 .1 .0 notes: 1. siocon.2 and siocon.3 should not be set simultaneously. if it is done, the data can be lost. 2. siocon.3 must be set separately when starting communication. figure 15-1. serial i/o module control registers (siocon) notes: 1. tx: 1) set the bit 1 and 2 of siocon in advance. 2) push data into siodata. 3) set the bit 3 of siocon to start the transm ission. 2. rx: 1) set the bit 1 and 2 of siocon in advance. 2) set the bit 3 of siocon to receive the data. 3) read the data from siodata.
serial i/o interface S3FB42F 15- 2 sio pre-scaler register (siops) the control register for serial i/o interface module, siops, is located at 49h. the value stored in the sio pre- scaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (fxx/2) / (pre- scaler value + 1), or, sclk input clock where the input clock is fxx. lsb msb sio pre-scaler register (siops) 51h,r/w baud rate = (fxx /2)/(siops + 1) .7 .6 .5 .4 .3 .2 .1 .0 figure 15-2. sio pre- scaler register (siops) block diagram 3-bit counter 8-bit sio shift buffer (siodata) 8-bit p.s 1/2 fxx siops (51h) sck siocon.7 (shift clock source select) prescaler value =1/(siops + 1) clear clk clk si siocon.3 siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so sio int siocon.1 (interrupt enable) figure 15-3. sio function block diagram
S3FB42F serial i/o interface 15- 3 serial i/o timing diagram so transmit complete irqs set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 si sck figure 15-4. serial i/o timing in transmit/receive mode ( tx at falling, siocon.4=0) irqs do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 sck transmit complete set siocon.3 si so figure 15-5. serial i/o timing in transmit/receive mode ( tx at rising, siocon.4=1)
serial i/o interface S3FB42F 15- 4 notes
S3FB42F uart 16- 1 16 uart overview an uart contains a programmable baud rate generator, rx and tx port for uart communication, tx and rx shift registers, tx and rx buffer registers, tx and rx control blocks and control registers. important features of the uart block include programmable baud rates, transmit/receive (full duplex mode), one or two stop bit insertion, 5-bit, 6-bit, 7-bit, or 8-bit data transmit/receive, and parity checking. the baud rate generator can be clocked by the internal oscillation clock. the transmitter cotains a tx data buffer register and a tx shift register. similary the receiver cotains a rx data buffer register and a rx shift register. data to be transmitted is written to the tx buffer register, then copied to the tx shift register, and shift out by the transmit data pin ( tx). data received is shifted in by the receive data pin (rx), then copied from shift register to the rx buffer register whenever one data byte is received. the control unit provides control for mode selection and status/interrupt generation. uart baud rate = fxx/(16 x (divisor value + 1)) data bus tx. control rx. control rx. shift register rx. buffer register interrupt control lcon/ucon/ussr tx. buffer register tx. shift register ck ck baud rate generator serial clock generator 8-bit prescaler data bus data bus status tx rx fxx data bus ubrdr figure 16-1. uart block diagram
uart S3FB42F 16- 2 uart special registers uart line control register the uart line control register, lcon, is used to control the uart. register address r/w description reset value lcon 0xb0 r/w uart line control register 00h [1:0] word length (wl). the two-bit word length value indicates the number of data bits to be transmitted or received per frame. the options are 5-bit, 6-bit, 7 -bit, and 8-bit. [2] number of stop bits lcon[2] specifies how many stop bits are used to signal end-of- frame (eof). when it is 0, one bit signals the eof; when it is 1, two bits signal eof. [5:3] parity mode (pmd) the 3-bit parity mode value specifies how parity generation and checking are to be performed during uart transmit and receive operations. there are five options (see figure 16-2). [6] ? [7] ? [1:0] word-length per frame (wl) 00 = 5-bit 01 = 6-bit 10 = 7-bit 11 = 8-bit [2] number of stop bit at end of frame 0 = one stop bit per frame 1 = two stop bits per frame [5:3] parity mode (pmd) 0xx = no parity bit in frame 100 = odd parity 101 = even parity 110 = parity forced/checked as 1 111 = parity forced/checked as 0 wl 7 6 5 3 0 2 1 pmd figure 16-2. uart line control register (lcon)
S3FB42F uart 16- 3 uart control register the uart control register, ucon, is used to control the single-channel uart. register address r/w description reset value ucon 0xb1 r/w uart control register 00h [0] rx interrupt enable uart rx interrupt control: 0 = disable, 1 = enable [1] rx enable uart rx operation control: 0 = disable, 1 = enable [2] rx status interrupt enable this bit enables the uart to generate an interrupt if an exception (break, frame error, parity error, or overrun error) occurs during a receive operation. when ucon[2] is set to 1, a receive status interrupt will be generated each time a rx exception occurs. when ucon[2] is 0, no receive status interrupt will be generated. [3] tx interrupt enable uart tx interrupt control: 0 = disable, 1 = enable [4] tx enable [5] - [6] send break setting ucon[6] causes the uart to send a break. break is defined as a continuous low level signal on the transmit data output with a duration of more than one frame transmission time. by setting this bit when the transmitter is empty (transmitter empty bit, ssr[7] = 1), you can use the transmitter to time the frame. when ssr[7] is 1, write the transmit buffer register, tbr, with the data to be transmitted. then poll the ssr[7] value. when it returns to 1, clear (reset) the send break bit, ucon[6]. [7] loopback bit setting ucon[7] causes the uart to enter loopback mode. in loopback mode, the transmit data output is sent high level and the transmit buffer register (tbr) is internally connected to the receive buffer register (rbr). this mode is provided for test purposes only.
uart S3FB42F 16- 4 uart status register the uart status register, ussr, is a read-only register that is used to monitor the status of serial i/o operations in the single-channel uart. register address r/w description reset value ussr 0xb2 r uart status register c0h [0] overrun error ussr[0] is automatically set to 1 whenever an overrun error occurs during a serial data receive operation. if the receive status interrupt enable bit, ucon[2] is 1, a receive status interrupt will be generated if an overrun error occurs. this bit is automatically cleared to 0 whenever the uart status register (ussr) is read. [1] parity error ussr[1] is automatically set to 1 whenever a parity error occurs during a serial data receive operation. if the receive status interrupt enable bit, ucon[2] is 1, a receive status interrupt will be generated if a parity error occurs. this bit is automatically cleared to 0 whenever the uart status register (ussr) is read. [2] frame error ussr[2] is automatically set to 1 whenever a frame error occurs during a serial data receive operation. if the receive status interrupt enable bit, ucon[2] is 1, a receive status interrupt will be generated if a frame error occurs. the frame error bit is automatically cleared to 0 whenever the uart status register (ussr) is read. [3] break interrupt ussr[3] is automatically set to 1 to indicate that a break signal has been received. if the receive status interrupt enable bit, ucon[2], is 1, a receive status interrupt will be generated if a break occurs. the break interrupt bit is automatically cleared to 0 when you read the uart status register. [4] ? [5] receive data ready ussr[5] is automatically set to 1 whenever the receive data buffer register (rbr) contains valid data received over the serial port. the receive data can then be read from the rbr. when this bit is 0, the rbr does not contain valid data. depending on the current setting of the sio receive mode bits, ucon[1:0], an interrupt or a dma request is generated when ussr[5] is 1. [6] tx buffer register empty ussr[6] is automatically set to 1 when the transmit buffer register (tbr) does not contain valid data. in this case, the tbr can be written with the data to be transmitted. when this bit is 0, the tbr contains valid tx data that has not yet been copied to the transmit shift register. in this case, the tbr cannot be written with new tx data. depending on the current setting of the uart transmit mode bits, ucon[4:3], an interrupt or a dma request will be generated whenever ussr[6] is 1. [7] transmitter empty (t) ussr[7] is automatically set to 1 when the transmit buffer register has no valid data to transmit and when the tx shift register is empty. when the transmitter empty bit is 1, it indicates to software that it can now disable the transmitter function block.
S3FB42F uart 16- 5 uart transmit buffer register the uart transmit holding register, tbr, contains an 8-bit data value to be transmitted over the single-channel uart. register address r/w description reset value tbr 0xb3 w serial transmit buffer register xxh [7:0] transmit data this field contains the data to be transmitted over the single-channel uart. when this register is written, the transmit buffer register empty bit in the status register, ussr[6], should be 1. this prevents overwriting transmit data that may already be present in the tbr. whenever the tbr is written with a new value, the transmit register empty bit, ssr[6], is automatically cleared to 0. uart receive buffer register the receive buffer register, rbr, contains an 8-bit field for received serial data. register address r/w description reset value rbr 0xb4 r serial receive buffer register xxh [7:0] receive data this field contains the data received over the single-channel uart. when this register is read, the receive data ready bit in the uart status register, ussr[5], should be 1. this prevents reading invalid receive data that may already be present in the rbr. whenever the rbr is written with a new value, the receive data ready bit, ussr[5], is automatically cleared to 0.
uart S3FB42F 16- 6 uart baud rate prescaler registers the value stored in the baud rate divisor register, ubrdr, is used to determine the serial tx/rx clock rate (baud rate) as follows: baud rate = fxx/((divisor value + 1) x 16) register address r/w description reset value ubrdr 0xb5 r/w baud rate divisor register 0000h uart interrupt pending register (upend) register address r/w description reset value upend 0xb6 r/w uart interrupt pending register 00h bit setting description [0] 0 or 1 uart rx interrupt pending bit 0: when read, interrupt is not pending. (when write, pending bit is clear) 1: when read, interrupt is pending. (when write, pending bit is not affected) [1] 0 or 1 uart error interrupt pending bit 0: when read, interrupt is not pending. (when write, pending bit is clear) 1: when read, interrupt is pending. (when write, pending bit is not affected) [2] 0 or 1 uart tx interrupt pending bit 0: when read, interrupt is not pending. (when write, pending bit is clear) 1: when read, interrupt is pending. (when write, pending bit is not affected) [7:3] ? ?
S3FB42F i 2 s bus (inter-ic sound) 17- 1 17 i 2 s bus (inter-ic sound) overview many digital audio systems are being introduced into the consumer audio market, including compact disc, digital audio tape, digital sound processors, and digital tv-sound. the digital audio signals in these systems are being processed by a number of (v) lsi ics, such as: a/d and d/a converters; digital signal processors; error correction for compact disc and digital recording; digital filters; digital input/output interfaces. standardized communication structures are vital for both the equipment and the ic manufacturer, because they increase system flexibility. to this end, we have used the inter-ic sound (i 2 s) bus-a serial link especially for digital audio. the bus has only to handle audio data, while the other signals, such as sub-coding and control, are transferred separately. to minimize the number of pins required and to keep wiring simple, a 3-line serial bus is used consisting of a line for two time-multiplexed data channels, a word select line and a clock line. since the transmitter and receiver have the same clock signal for data transmission, the transmitter as the master, has to generate the bit clock, word-select signal and data. in complex systems however, there may be several transmitters and receivers, which makes it difficult to define the master. in such systems, there is usually a system master controlling digital audio data-flow between the various ics. transmitters then, have to generate data under the control of an external clock, and so act as a slave. figure 17-1 illustrates some simple system configurations and the basic interface timing. note that the system master can be combined with a transmitter or receiver, and it may be enabled or disabled under software control or by pin programming. mcu sd ws sclk digital sound interface figure 17-1. simple system configuration
i 2 s bus (inter-ic sound) S3FB42F 17- 2 the i 2 s bus as shown in figure 17-1, the bus has three lines: continuous serial clock (sclk); word select (ws); serial data (sd); and the device generating sclk and ws is the master. sd word n-1 right channel ws sclk ~ ~ ~ ~ ~ ~ msb lsb msb ~ ~ word n left channel word n+1 right channel dummy figure 17-2. i 2 s basic interface format (phillips) sd word n-1 right channel ws sclk ~ ~ ~ ~ ~ ~ msb lsb msb ~ ~ word n left channel word n+1 right channel figure 17-3. lsi interface format (sony)
S3FB42F i 2 s bus (inter-ic sound) 17- 3 serial data serial data is transmitted in two's complement with the msb first. the msb is transmitted first because the transmitter and receiver may have different word lengths. it isn't necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. when the system word length is greater than the transmitter word length, the word is truncated (least significant data bits are set to 0) for data transmission. if the receiver is sent more bits than its word length, the bits after the lsb are ignored. on the other hand, if the receiver is sent fewer bits than its word length, the missing bits are set to zero internally. and so, the msb has a fixed position, whereas the position of the lsb depends on the word length. the transmitter always sends the msb of the next word one clock period after the ws changes. serial data sent by the transmitter may be synchronized with either the trailing (high-to-low) or the leading (low- to-high) edge of the clock signal. however, the serial data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some restrictions when transmitting data that is synchronized with the leading edge (see figure 17-4 and table 17-1). word select the word select line indicates the channel being transmitted: ws = 0; channel 1 (left); ws = 1; channel 2 (right). ws may change either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the ws line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchronous timing of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the previous word and clear the input for the next word (see figure 17-2). timing in the i 2 s format, any device can act as the system master by providing the necessary clock signals. a slave will usually derive its internal clock signal from an external clock input. this means, taking into account the propagation delays between master clock and the data and/or word-select signals, that the total delay is simply the sum of: the delay between the external (master) clock and the slave's internal clock; and the delay between the internal clock and the data and/or word-select signals. for data and word-select inputs, the external to internal clock delay is of no consequence because it only lengthens the effective set-up time (see figure 17-3). the major part of the time margin is to accommodate the difference between the propagation delay of the transmitter, and the time required to set up the receiver. all timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device. this means that higher data rates can be used in the future.
i 2 s bus (inter-ic sound) S3FB42F 17- 4 sclk t lc => 0.35t t hc => 0.35t t ws and sd v h = 2.0 v v l = 0.8 v t rc => 0 t h tr => 0 t d tr =< 0.8t t = clock period t tr = minimum allowed clock period for transmitter t > t tr t rc is only relevant for transmitters in slave mode. figure 17-4. timing for i 2 s transmitter sclk t lc => 0.35t t hc => 0.35t t ws and sd t sr => 0.2t t hr => 0 v h = 2.0 v v l = 0.8 v t = clock period t r = minimum allowed clock period for transmitter t > t tr figure 17-5. timing for i 2 s receiver
S3FB42F i 2 s bus (inter-ic sound) 17- 5 table 17-1. master transmitter with data rate of 2.5 mhz (10%) (unit: ns) min typ max condition clock period t 360 400 440 ttr = 360 clock high thc 160 min > 0.35t = 140 (at typical data rate) clock low tlc 160 min > 0.35t = 140 (at typical data rate) delay tdtr 300 max < 0.80t = 320 (at typical data rate) hold time thtr 100 min > 0 clock rise-time trc 60 max > 0.15t = 54 ( atrelevent in slave mode) table 17-2. slave receiver with data rate of 2.5 mhz (10%) (unit: ns) min typ max condition clock period t 360 400 440 ttr = 360 clock high thc 110 min < 0.35t = 126 clock low tlc 110 min < 0.35t = 126 set-up time tsr 60 min < 0.20t = 72 hold time thtr 0 min < 0
i 2 s bus (inter-ic sound) S3FB42F 17- 6 i 2 s special register description i 2 s control registers table 17-3. function register description register address r/w/c description iiscon0 0x58 r/w i 2 s 0 control register iiscon1 0x5c r/w i 2 s 1 control register iismode0 0x59 r/w i 2 s 0 mode register iismode1 0x5d r/w i 2 s 1 mode register iisptr0 0x5a r/w i 2 s 0 buffer pointer register iisptr1 0x5e r/w i 2 s 1 buffer pointer register iisbuf 0xc0-0xff r/w i 2 s buffer registers i 2 s control registers (iiscon) register address r/w description reset value iiscon0 0x58 r/w i 2 s control register 0 00h iiscon1 0x5c r/w i 2 s control register 1 00h iis control register0 has the following control bit settings: [0] i 2 s0 enable i 2 s0 block when this bit is set as 1. 0: i 2 s0 block disable. 1: i 2 s0 block enable. [1] mclk select normal or mclk output mode 0: normal output 1: mclk output [2] sd0_out select the input or output mode for each i 2 s0 serial data pin. set sd0 pin as an input or an output. 0: input 1: output [3] slave mcu generate the sclk0 and ws0 signal to transmit or receive the serial data. 0: master mode, sclk0 and ws0 is output mode. 1: slave mode, sck0 and ws0 is input mode. [4] sckpol select the serial clock0 polarity. 0: active low 1: active high [5] chpol select the left/right channel polarity. 0: left high 1: left low [6] lsbfirst select msb("0") first at or lsb("1") first in seria l interface
S3FB42F i 2 s bus (inter-ic sound) 17- 7 [7] psmode. select the phillips iis0 interface format or sony lsi interface format. 0: i 2 s , 1: lsi iis control register1 has the following control bit settings: [0] i 2 s1 enable enable i 2 s1 block when this bit is set as 1. 0: i 2 s1 block is disabled. 1: i 2 s1 block is enabled. [1] ? ? [2] sd1_out select the input or output mode for each i 2 s1 serial data pin. set sd1 pin as an input or an output. 0: input 1: output [3] slave mcu generate the sclk1 and ws1 signal to transmit or receive the serial data. 0: master mode, sclk1 and ws1 is output mode. 1: slave mode, sck1 and ws1 is input mode. [4] sckpol select the serial clock1 polarity. 0: active low 1: active high [5] chpol select the left/right channel polarity. 0: left high 1: left low [6] lsbfirst select msb("0") first at or lsb("1") first in serial interface [7] psmode. select the phillips iis0 interface format or sony lsi interface format. 0: i 2 s , 1: lsi
i 2 s bus (inter-ic sound) S3FB42F 17- 8 i 2 s mode registers ( iis mode) register address r/w description reset value iismode0 0x59 r/w i 2 s mode register 0 00h iismode1 0x5d r/w i 2 s model register 1 00h i 2 s control register has the following control bit settings: [1-0] bitpslot: set the bit number per slot 00: 8-bit 01: 16-bit 10: 24-bit 11: 32-bit [5-2] sfreq set the sampling frequency for left/right channel output 0100: select an 11.025 khz as audio sampling frequency 0101: select an 22.05 khz as audio sampling frequency 0110: select an 44.1 khz as audio sampling frequency 0111: select an 88.2 khz as audio sampling frequency 1000: select an 8 khz as audio sampling frequency 1001: select an 16 khz as audio sampling frequency 1010: select an 32 khz as audio sampling frequency 1100: select an 12 khz as audio sampling frequency 1101: select an 24 khz as audio sampling frequency 1110: select an 48 khz as audio sampling frequency 1111: select an 96 khz as audio sampling frequency [7-6] bitpfs set the bit number per sampli ng frequency 01: 32-bit 10: 48-bit (slave only) 11: 64-bit when mclk (master clock) is enabled, mclk frequency is fs x 256.
S3FB42F i 2 s bus (inter-ic sound) 17- 9 i 2 s pointer registers (iisptr) register address r/w description reset value iisptr0 0x5a r/w i 2 s buffer pointer register 0 00h iisptr1 0x5e r/w i 2 s buffer pointer register 1 00h [5-0] pointer buffer pointer register. the bit 5 is not incremented but bit4-0 are automatically incremented whenever buffer operation is done. after pointer value, iisptr[4:0] reached to 0x1f, interrupt request flag is active. iisptr will increment from the initial value to iisptr[4:0] = 0x1f, iisptr[4:0] is cleared to 0x00. however iisptr[5] is not changed. if iisptr[5] = 1, second half buffer (0xe0?0xef) is accessible. otherwise, first half buffer (0xc0?0xdf) is accessible. i 2 s buffer registers (iisbuf) register address r/w description reset value iisbuf 0xc0-0xff r/w i 2 s buffer registers 00h [7-0] data i 2 s buffer registers hold the audio data for transmitting data to audio dac or receiving data from external i.c.
i 2 s bus (inter-ic sound) S3FB42F 17- 10 notes
S3FB42F ssfdc (soil d state floppy disk card) 18- 1 18 ssfdc (solid state floppy disk card) overview S3FB42F build a interface logic for smartmedia? card, called as ssfdc, solid state floppy disk card. the ssfdc interface include the use of simple hardware together with software to generate a basic control signal or ecc for smartmedia?. the built-in ssfdc interface logic consists of ecc block and the read/write strobe signal generation block. the high speed risc cpu core, calmrisc support high speed control for other strobe signal generation and detection. therefore, ale, cle, ce and etc signal should be operated by cpu instruction. this mechanism provide the balanced cost and power consumption without the de-graduation of ssfdc access speed. physical format is necessary to maintain wide compatibility. smartmedia? has a standard physical format. system makers and controller manufacturers are requested to conform their products to such specifications. for logical format, smartmedia? employs a dos format on top of physical format. see pc card standard vol.7 and other references for more information. with all smartmedia? products, physical and logical formatting has been completed at time of shipment.
ssfdc (soild state floppy disk card) S3FB42F 18- 2 nce (p6.0, 1) cle (p6.2) r/b (p6.4) ale (p6.3) nwe (dedicated pins) nre (dedicated pins) ssfdc interface control i/o0-i/o7 (dedicated pins) mux ecc processor port 7 v s db0-db7 figure 18-1. simple system configuration
S3FB42F ssfdc (soil d state floppy disk card) 18- 3 ssfdc register description description of the register in the ssfdc, smartmedia interface is listed the below table. table 18-1. control register description register address r/w/c description smcon 70h r/w smartmedia control register eccnt 71h r/w ecc count register eccl/h/x 72/73/74h r/w ecc data register low/high/extension eccrstl/h 75/76h r/w ecc result data register low/high eccclr 77h w ecc clear register smartmedia control register (smcon) register address r/w description reset value smcon 0x70 r/w smartmedia control register 00h [0] ecc enable this bit enable or disable the ecc operation in the smartmedia block. when this bit is set as "1", ecc block is activated and ecc operation is done whenever accessing the port 7. "1" : enable "0" : disable . [1] enable smartmedia interface this bit control the operation of smartmedia block. when this bit is set as "1", port 7 is activated as i/o data bus of smartmedia interface. smartmedia control signal is generated whenever accessing the port 7. [3:2] wait cycle control these bit control the wait cycle insertion when access to smartmedia card. 00: no wait in nwe or nrd signal 01: 1 wait in nwe or nrd signal 10: 3 wait in nwe or nrd signal 11: invalid setting. smartmedia ecc count register (eccnt) register address r/w description reset value eccnt 0x71 r/w smartmedia ecc count register 00h [7:0] count this field acts as the up-counter. you can know the ecc count number by reading this register. this register is cleared by setting the smcon.0, start bit or overflow of counter.
ssfdc (soild state floppy disk card) S3FB42F 18- 4 smartmedia ecc data register (eccdata) register address r/w description reset value eccx 0x74 r/w smartmedia ecc data extension register 00h ecch 0x73 r/w smartmedia ecc data high register 00h eccl 0x72 r/w smartmedia ecc data low register 00h [7:0] data data field acts as ecc data register when smcon.0, e nable bit is set. the access instruction to port 7 execute an 1byte ecc operation. the writing to eccclr register have all ecc data registers clear to zero smartmedia ecc result data register (eccrst) register address r/w description reset value eccrstl 0x75 r/w smartmedia ecc result data register low 00h eccrsth 0x76 r/w smartmedia ecc result data register high 00h [7:0] data after ecc compare operation is executed, ecc result out to ecc result data register, eccrst. eccrsth[7:0] have the byte location with correctable error bit. eccrstl[2:0] have the bit location where is correctable error bit. eccrstl[5:4] have the error information. 00: no error occurred. 01: detect 1 bit error but recoverable 10: detect the multiple bit error. 11: detect the multiple bit error.
S3FB42F ssfdc (soil d state floppy disk card) 18- 5 i/o0-i/o7 mux port 7 v s db0-db7 ecccnt x-or eccdata (eccx/h/l) eccrst (eccrst/h/l) ssfdc interface control eccrstl[5:4]: error information 00: no error 01: 1 bit error in eccrsth.eccrstl[2:0] (randge: 0x00.0-0xff.7 byte address: eccrsth[7:0] bit location: eccrstl[2:0]) 10: multi bit error 11: multi bit error figure 18-2. ecc processor block diagram
ssfdc (soild state floppy disk card) S3FB42F 18- 6 notes
S3FB42F parallel po rt interface 19- 1 19 parallel port interface overview the S3FB42F's parallel port interface controller (ppic) supports four ieee standard 1284 communication modes: ? compatibility mode ( centronics tm ) ? nibble mode ? byte mode ? enhanced capabilities port (ecp) mode the ppic also supports all variants of these communication modes, including device id requests. the ppic contains specific hardware to support the following operations: ? automatic hardware handshaking between host and peripheral in compatibility and ecp modes these features can substantially improve data transfer rates when S3FB42F operates the parallel port in the compatibility or ecp mode. in addition, hardware handshaking over the parallel port can be enabled or disabled by software. this gives you the direct control of ppic signals as well as the eventual use of future protocols. other operations defined in the ieee standard 1284, such as negotiation, nibble mode and byte mode data transfers, and termination cycles, must be carried out by software. the ieee 1284 epp communications mode is not supported. note here we assume that you are familiar with the parallel port communication protocols specified in the ieee 1284 parallel port standard. if you are not, we strongly recommend for you to read this standard beforehand. it would be helpful for you in understanding the contents described in this section.
parallel port interface S3FB42F 19- 2 ppic operating modes the S3FB42F ppic supports four kinds of handshaking modes for data transfers: ? software handshaking mode to forward and reverse data transfers ? compatibility hardware handshaking mode to forward data transfers ? ecp hardware handshaking mode to forward and reverse data transfers mode selection is specified in the ppic control low register (ppconl). by setting the ppconl[6:4], one of these four modes is enabled. software handshaking mode this mode is enabled by setting the ppconl's mode-selection bits, ppconl[5:4], to "00." in this mode, you can use ppic interrupt event registers (ppintcon and ppintpnd) and the read/write ppic status register (ppstat and ppscon) to detect and control the logic levels on all parallel port signal pins. software can control all parallel port operations, including all four kinds of parallel port communications protocols supported by the S3FB42F (refer to ieee 1284 standard for operation control). in addition, it also gives software the flexibility of adopting new and revised protocols. compatibility hardware handshaking mode compatibility hardware handshaking mode is enabled by setting the ppconl's mode-selection bits as "01", i.e. ppconl[5:4] = 01. in this mode, hardware generates all handshaking signals needed to implement compatibility mode of the parallel port communication protocol. when this mode is enabled, the ppic automatically generates a busy signal to receive the leading edge of nstrobe from the host, and latches the logic levels on ppd7-ppd0 pins into the ppdata register. the ppic then waits for nstrobe to negate it and for the ppdata's data field to be read. after the ppdata is read, the ppic asserts nack for the duration specified in the ack width data register (ppackd), and then negates the nack and busy signal to conclude the data transfer, as shown in figure 19-1. note the busy-control bit initial value in the ppscon register, ppscon[3], which is "1" after a system reset, results in the high logic level on busy output and handshaking disable. to enable hardware handshaking in this mode, the busy-control bit ppscon[3] must be cleared to "0" by software beforehand.
S3FB42F parallel po rt interface 19- 3 data ppd[7:0] nstrobe busy nack figure 19-1. compatibility hardware handshaking timing ecp mode ecp hardware handshaking mode is enabled by setting the ppconl's mode-selection bits to "10", i.e. ppconl[5:4] = 10. in this mode, hardware generates handshaking signals needed to implement ecp mode of the parallel port communication protocol. when receiving data from the host, the ppic automatically responds to the high-to-low transition on the nstrobe by latching the logic levels on the ppd7-ppd0 to ppdata(and ppcdata). the nautofd logic level, which is latched to the ppintpndh[1] or [0], command or data received flags, indicates whether the current data on the ppdata[7:0] is a data-byte or a command-byte. when the ppdata is read, the ppic drives busy to high level and waits for nstrobe to go high level. it then drives busy to low level to conclude one forward data transfer operation, as shown in figure 19-2. the reception of a command byte causes the command received-bit in the ppic interrupt pending register, ppintpndh[1], to be set to "1". by examining the ppdata/ppcdata[7], software will interpret the command byte as a channel address if it is "1" and carry out the corresponding operation, or interpret the command byte as a run- length count if it is "0" and then perform data decompression. during reverse data transfers, software is responsible for data compression, and writing data or command byte in ppdata or ppcdata to define the logic levels on ppd7-ppd0 and busy pins. the write to ppdata or ppcdata indicates whether the current data on the ppd[7:0] is a data-byte or a command-byte. when some value is written to ppdata, that means data-byte type and is output through the busy pin to high. when some value is written to ppcdata, that means command-byte type and is output through the busy pin to low. in response to writing the ppdata or ppcdata, the ppic automatically drives the nack to low level and waits for the nautofd to go to high level. it then drives nack to high level to conclude one reverse data transfer operation, as shown in figure 19-3.
parallel port interface S3FB42F 19- 4 ppd[7:0] nautofd (hostack) nstrobe (hostclk) busy (periphack) byte 1 byte 0 command byte data byte read ppdata or ppcdata read ppdata or ppcdata figure 19-2. ecp hardware handshaking timing (forward) ppd[7:0] busy (periphack) nack (periphack) nautofd (hostack) byte 1 byte 0 command byte data byte write to ppdata write to ppcdata figure 19-3. ecp hardware handshaking timing (reverse)
S3FB42F parallel po rt interface 19- 5 digital filtering the S3FB42F provides digital filtering function on host control signal inputs, nselectin (p1284), nstrobe ( hostclk), nautofd (h0tack) and ninit ( nreverserequest), to improve noise immunity and make the ppic more impervious to the inductive switching noise. the digital filtering function can be enabled regardless of hardware handshaking or software handshaking. if this function is enabled, the host control signal can be detected only when its input level keeps stable during three sampling periods. digital filtering can be disabled to avoid signal missing in some specialized applications with high bandwidth requirement. otherwise, it is recommended that digital filtering be enabled. ppic special registers parallel port data/command data register the parallel port data/command data register, ppdata/ppcdata, contains an 8-bit data field, ppdata/ppcdata[7:0], that defines the logic level on the parallel port data pins, ppd[7:0]. register address r/w description reset value ppdata 0x60 r/w parallel port data register 00h ppcdata 0x61 r/w parallel port command data register 00h [7:0] this is an 8-bit read/write field. when ppconl[7] is zero and this field (ppdata or ppcdata) is read, this field provides the logic level on the ppd[7:0], which is latched when the strobe input from the host ( nstrobe) transits from high to low level. (the ppconl[7] bit determines the forward or reverse dataflow direction of the parallel port.) when ppconl[7] is one and this field(ppdata or ppcdata) is written, the value of this field determines the logic level on the ppd[7:0]. during the ecp forward data transfers, the logic level of the nautofd is read from ppintpndh[1] or [0], command-byte received or data-byte received. the nautofd indicates whether the data in the ppdata/ppcdata is a data-byte or a command-byte. when read ppdata or ppcdata, command-byte: ppintpnd[1:0] = '10b' data-byte: ppintpnd[1:0] = '01b' to read the nautofd from the ppintpndh[1] or [0] the following two conditions are required: 1) nstrobe has transited from high level to low level. 2) the data bus output enable bit in the ppconl[7] is 0. when the ecp data transfers are in reverse and the data bus output enable bit in the parallel port control register, ppconl[7] is 1, the logic level of busy pin is written from ppdata or ppcdata. the busy pin indicates that the data written in the ppdata is a data-byte, or the data written in the ppcdata is a command-byte. busy pin 0 = command-byte in the ppcdata[7:0] 1 = data-byte in the ppdata[7:0]
parallel port interface S3FB42F 19- 6 parallel port status control and status register the parallel port status control and status register, ppscon, ppstat, contain eleven bits to control the parallel port interface signals. these eleven bits consist of four read-only bits to read the logic level of the host input pins, two read-only bits to read the logic level on the busy and nack output pins, and five read/write bits to control the logic levels on the printer output pins by software for handshaking control register address r/w description reset value ppscon 0x62 r/w parallel port status control register 08h [0] nfault control setting this bit drives the nfault output to low level; clearing it drives ( nperiphrequest) the signal high level on the external nfault pin. the nfault informs the host of a fault condition in the printer engine. [1] select control setting this bit to one drives the select output to high level; ( xflag) clearing it to zero drives the signal low on the external select pin. the select informs the host of a response from the printer engine. [2] perror control setting this bit drives perror output to high level; clearing it drives the ( nackreverse) signal low level on the external perror pin. the perror informs the host that a paper error has occurred in the engine. [3] busy control setting this bit drives the external busy output to high level by force. ( periack) this disables hardware handshaking. when this bit is zero, the external busy output is the internal busy signal. [4] nack control setting thi s bit drives the external nack output to low level by force. ( periphclk) this is generally done to disable hardware handshaking. when this bit is zero, the external nack is the internal nack signal.
S3FB42F parallel po rt interface 19- 7 register address r/w description reset value ppstat 0x63 r/w parallel port status register 3fh [0] busy status this read-only bit reflects the logic level on the external busy output ( periphack) pin. after a system reset, the ppscon[3] is "1", which results in one, the value of ppstat[0] being "1". so, for compatibility mode operation, you must clear the ppscon[3] by software beforehand so as to enable the hardware handshaking. [1] nack status this read-only bit reflects the level read on the external nack output ( periphclk) pin. after a system reset, ppstat[1] is "1". when the ppscon[4] is set to be high, this bit is forced to be low and then the internal nack is ignored . [2] nslctin status this read-only bit reflects the level read on the nslctin input pin after (p1284) synchronization and optional digital filtering when the digital filtering enable bit, ppconl[2:3], are not set to zero. [3] nstrobe status this read-only bit reflects the level read on the nstrobe input pin after ( hostclk) synchronization and optional digital filtering when the digital filtering enable bit, ppconl[2:3], are not set to zero. [4] nautofd status this read-only bit reflects the level read on the nautofd input pin after ( hostack) synchronization and optional digital filtering when the digital filtering enable bit, ppconl[2:3], are not set to zero. [5] ninit status this read-only bit reflects the level read on the ninit input pin after ( nreverserequest) synchronization and optional digital filtering when the digital filtering enable bit, ppconl[2:3], are not set to zero.
parallel port interface S3FB42F 19- 8 parallel port control register the parallel port control register, ppcon, is used to configure the ppi operations, such as handshaking, digital filtering, operating mode, data bus output and abort operations. the ppconh[6:4] bits are read-only. register address r/w description reset value ppconl 0x64 r/w parallel port control low register 00h [0] software reset setting the software reset bit causes the ppic's handshaking control c to immediately terminate the current operation and return to software idle state. when ppconl[0] is set to "1", the full status bit, ppconh[5], is automatically cleared to "0". [1] ppic enable setting this bit enables ppic mode. clearing this bit disable ppic operation and enter power saving mode. [3:2] digital filter enable setting this bit enables digital filtering on all four host control signal inputs: nselectin, nstrobe, nautofd, and ninit. 00: disable 01: 2 step filtering 10: 3 step filtering 11: 3 step filtering [6:4] mode selection this three-bit value selects the current operating mode of the parallel port interface x00:software mode x01:compatibility mode 010: forward ecp mode 110: reverse ecp mode software mode : disables all hardware handshaking so that handshaking can be performed by software. compatibility mode : compatibility mode hardware handshaking can be enabled during a forward data transfer. you can change the mode selection at any time, but if a compatibility mode operation is currently in-progress, it will be completed as a normal operation. mode should be changed from compatibility mode to another mode only when busy is high level. this ensures that there is no parallel port activity while the parallel port is being re-configured. ecp mode : ecp mode hardware handshaking support can be enabled during forward or reverse data transfers. you can change the mode selection at any time, but if an ecp cycle is currently in progress, it will be completed as a normal operation.
S3FB42F parallel po rt interface 19- 9 [7] data bus output enable the parallel port data bus output enable bit performs two functions: 1) it controls the state of the tri-state output drivers. 2) it qualifies the data latching from the output drivers into the parallel port data register's data field, ppdata[7:0]. when ppconl[7] is "0", the parallel port data bus lines, ppd[7:0] are disabled. this allows data to be latched onto the ppdata or ppcdata's data field. when ppconl[7] is "1", the ppd[7:0] is enabled and data is prevented from being latched onto the ppdata or ppcdata's data field. in this frozen state, the data field is unaffected by the transition of nstrobe. the setting of the abort bit, ppconh[3], affects the operation of the data bus output enable bit, ppconl[7]. if ppconh[3] is "1", the nselectin must remain high to allow ppconl[7] to be set, or to remain set. if ppconl[7] is "1" and nselectin goes low, the ppconl[7] is cleared and setting this bit will have no effect.
parallel port interface S3FB42F 19- 10 register address r/w description reset value ppconh 0x65 r/w parallel port control high register 00h [0] ? [1] ? [2] abort the abort bit causes the parallel port interface controller to use nselectin to detect the time when the host suddenly aborts a reverse transfer and returns to compatibility mode; if ppconh[2] is "1", the low level on nselectin causes the parallel port data bus output enable bit ppconl[7] to be cleared, and the output drivers for the data bus lines ppd[7:0] to be tri-stated. [3] error cycle the error cycle bit is used to execute an error cycle in compatibility mode. when ppconh[3] is set to "1", the busy status bit in the parallel port status register, ppstat[0], is set to "1". this immediately causes the S3FB42F to drive the busy to high level. if you set the error cycle bit while a compatibility mode handshaking sequence is in progress, the ppstat[0] will remain to be set to one beyond the end of the current cycle. the error cycle bit does not affect the nack pulse if it is already active, but it will delay an nack pulse if it is about to be generated. when ppconh[3] is "1", software can set or clear the parallel port status register control bits: ppscon[0] ( nfault control), ppscon[1] (select control), and ppscon[2] (perror control). when ppconh[3] is cleared to "0", the parallel port interface controller generates a delayed nack pulse and makes busy low active to finish the error cycle. [4] ? [5] data latch status if a data is latched to ppdata, then this bit is set to '1'. it is automatically cleared to zero when the ppdata is read in software, compatibility and forward ecp mode. [6] data empty in reverse ecp mode, thi s bit specifies the ppdata is empty. it is automatically cleared to zero while the ppdata is written with a new data.
S3FB42F parallel po rt interface 19- 11 parallel port interrupt event registers the two parallel port interrupt event registers, ppintcon and ppintpnd, control interrupt-related events for the input signal originating from the host, as well as data reception, command reception, and invalid events. the parallel port interrupt control register, ppintcon, contains the interrupt enable bits for each interrupt event that is indicated by the ppintpnd status bits. if the ppintcon enable bit is "1", the corresponding event causes the S3FB42F cpu to generate an interrupt request. otherwise, no interrupt request is issued. note to clear the corresponding pending bit to zero after a interrupt service routine, write the pending bit to zero. the value of the pending bit is changed from one to zero automatically. register address r/w description reset value ppintconl 0x66 r/w parallel port interrupt control low register 00h ppintpndl 0x68 r/w parallel port interrupt pending low register 00h [0] nslctin low-to-high the bit of ppintpnd is set when a low-to-high transition on nslctin (p1284) is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [1] nslctin high-to-low the bit of ppintpnd is set when a high-to-low transition on nslctin is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [2] nstrobe low-to-high the bit of ppintpnd is set when a low-to-high transition in the ( hostclk) nstrobe is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [3] nstrobe high-to-low the bit of ppintpnd is set when a high-to-low transition in the nstrobe is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [4] nautofd low-to-high the bit of ppintpnd is set when a low-to-high transition in the ( hostack) nautofd is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [5] nautofd high-to-low the bit of ppintpnd is set when a high-to-low transition in the nautofd is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [6] ninit low-to-high the bit of ppintpnd is set when a low-to-high transition in the ninit ( nreverserequest) is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated. [7] ninit high-to-low the bit of ppintpnd is set when a high-to-low transition in the ninit is detected. if the corresponding enable bit is set in the ppintcon register, an interrupt request is generated.
parallel port interface S3FB42F 19- 12 register address r/w description reset value ppintconh 0x67 r/w parallel port interrupt control high register 00h ppintpndh 0x69 r/w parallel port interrupt pending high register 00h [0] data received the bit of ppintpnd is set when data is latched into the ppdata register's data field. this occurs during every high-to-low transition of nstrobe when the parallel port data bus enable bit, ppconl[7], is "0". an interrupt is also generated if the ecp-with-rle mode is enabled, and if a data decompression is in progress. [1] command received the bit of ppintpnd is set when a command byte is latched into the ppdata register data field. if ecp-without-rle mode is enabled, the command received interrupt is issued whenever a run-length or channel address is received. if ecp-with-rle mode is enabled, the command received interrupt is issued only when a channel address is received. this event can be posted only when ecp mode is enabled. the corresponding enable bit in the ppintcon register determines whether or not an interrupt request will be generated when a command byte is received. [2] invalid transition the bit of ppintpnd is set when nslctin transitions high-to-low in the middle of an ecp forward data transfer handshaking sequence. this interrupt is issued if nslctin is low when nstrobe is low or when busy is high. this event can be detected only when ecp mode is enabled and should return to compatibility mode. [3] transmit data empty the bit of ppintpnd is set to one when the transmit data register (=ppdata) can be written during an ecp reverse data transfers parallel port ack width register this register contains the 8-bit nack pulse width field. this value defines the nack pulse width whenever the parallel port interface controller enters compatibility mode, that is, when the parallel port control register mode bits, ppconl[5:4], are set to "01". the nack pulse width is selectable from 0 to 255 x in periods. the nack pulse width can be modified at any time and with any ppic operation mode selection, but it can only be used during a compatibility handshaking cycle. if you change the nack width near the end of a data transfer (when nack is already low), the new pulse width value does not affect the current cycle. the new pulse width value would be used at the start of the next cycle. register address r/w description reset value ppackd 0x6a r/w parallel port acknowledge width data register xxh the value in the 8-bit field defines the nack pulse width when compatibility mode is enabled (ppconl[5:4]=01). the period of the nack pulse can range from 0 to 255 x in with 2 x in steps.
S3FB42F 8-bit analo g-to digital converter 20- 1 20 8-bit analog-to-digital converter overview the S3FB42F has six 8 -bit resolution a/d converter input (adc0 to adc5). the 8-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the six input channels to equivalent 8 -bit digital values (addatah, addatal). the analog input level must lie between the av ref and av ss values. the a/d converter has the following components: analog comparator with successive approximation logic d/a converter logic (resistor string type) adc control register (adcon) six multiplexed analog data input pins (adc0-adc5) 8-bit a/d conversion data output register (addatah, addatal) 6 -bit digital input port av ref and av ss pins function description to initiate an analog-to-digital conversion procedure, you write the channel selection data in the a/d converter control register adcon to select one of the six analog input pins ( adcn, n = 0-5) and set the conversion start or enable bit, adcon.0. the conversion result data load to addata register. during a normal conversion, a/d c logic initially sets the successive approximation register to 80h (the approximate half-way point of an 8-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 8-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.6-4) in the adcon register. to start the a/d conversion, you should set a the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addata register where it can be read. the a/d converter then enters an idle state. remember to read the contents of addata before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the a/d converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the adc0-adc5 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path in a/d block. you must use stop or idle mode after a/d c operation is finished.
8-bit analog-to digital converter S3FB42F 20- 2 conversion timing the a/d conversion process requires 4 steps (4, 16, 32 or 64 clock edges) to convert each bit and 2 steps to setup the a/d converter block. therefore, a total of 14 steps are required to complete an 8-bit conversion. one step can be 1 clock, 4 clocks, 8 clocks or 16 clocks by software. with an 20 mhz cpu clock frequency, one clock cycle is 50 ns. the conversion rate is calculated as follows: start 2 step + (1 step/bit 10 bits) + eoc 2 step = 56 clocks, where 1 step = 4 clocks to get the correct a/d conversion result data, a/d conversion time should be longer than 20 m s whatever oscillation frequency is used. conversion result (addata) - + av ref av ss analog comparator 8-bit d/a converter adcon.0 (ad/c enable) adcon.0 (ad/c enable) to data bus input pins adc0-adc5 (p5.0-p5.5) m u x adcon.4-.6 (input pin select) to adcon.3 (eoc flag) fxx/n (n = 1, 4, 8, 16) clock select to adcon.2 - .1 successive approximation logic & register figure 20-1. a/d c block diagram
S3FB42F 8-bit analo g-to digital converter 20- 3 a/d c special registers a/d c control registers the a/d c control registers, adcon is used to control the operation of the six 8-bit a/d c channel. register address r/w description reset value adcon 0x54 r/w a/d c control register 00h a/d converter control register has the following control bit settings: [0] adstr 0: a/d conversion is disabled. 1: a/d conversion begins and is cleared after conversion. [2:1] select the conversion speed 00: step clock = fxx/16. 01: step clock = fxx/8. 10: step clock = fxx/4. 11: step clock = fxx/1. [3] eoc (read-only) 0: conversion is not completed. 1: this flag is set after conversion. [6:4] a/d c input select 000: select a adc0 001: select a adc1 010: select a adc2 011: select a adc3 100: select a adc4 101: select a adc5 [7] not used. a/d converter data registers the a/d conversion data high register, addata, contains a conversion result value that specify analog input channel. register address r/w description reset value addata 0x55 r a/dc conversion result data register xxh a/d converter data register has the following bits: [7:0] a/d c data this register has the bit 7 to bit 0 of an a/d conversion result value.
8-bit analog-to digital converter S3FB42F 20- 4 notes
S3FB42F i 2 c-bus interface 21- 1 21 i 2 c- bus interface overview the S3FB42F internal iic bus (i 2 c-bus) controller has the following important features: ? it requires only two bus lines, a serial data line (sda) and a serial clock line (scl). when the i 2 c-bus is free, both lines are high level. ? each device that is connected to the bus is software-addressable by a multi master using a unique address. slave relationships on the bus are constant. the bus master can be either a master-transmitter or a master- receiver. the i 2 c bus controller supports multi master mode. ? it supports 8-bit, bi-directional, serial data transfers. ? the number of ics that you can connect to the same i 2 c-bus is limited only by the maximum bus capacitance of 400 pf. figure 21-1 shows a block diagram of the S3FB42F i 2 c-bus controller. sda iicps (prescaler reg.) serial clock prescaler ii c-bus control logic ii ccon iicsr iicdata (shift data reg.) ii caddr (address reg.) intpend fxx scl control data control scl figure 21-1. i 2 c-bus block diagram
i 2 c-bus interface S3FB42F 21- 2 functional description the S3FB42F i 2 c bus controller is the master or slave of the serial i 2 c-bus. using a prescaler register, you can program the serial clock frequency that is supplied to the i 2 c bus controller. the serial clock frequency is calculated as follows: fxx/(4 ( prescaler register (iicps) value + 1) ): iicps must not be 00h. in master tx mode, to start a i2c-bus arbitration, the programmer writes a slave address to the data register, iicdata and ?0x3d? to the control register, iiccon. the bus controller then generates start condition and shifts the 7-bit slave address. the receiver sends an acknowledge by pulling the sda line from high to low during a master scl pulse. after acknowledg3e cycle, the status register, iicsr, is updated corresponding arbitration result and interrupt request is activated if interrupt is enable. after sensing interrupt or polling the status register, the programmer can continue the data shift operation. for the data arbitration, the programmer writes the data to the data register, iicdata and writes ?0x3e? to the control register. for the consecutive read/write operations, you must set the ack bit in the control status register. for read operations, you can read the data after you have confirmed the pending bit in the interrupt pending register. to signal the end of the read operation, you can reset the ack bit to inform the receive/transmitter when the last byte is to be written/read. following a read/write operation, you set iiccon[1:0] to ?3? to generate a stop code. if you want to complete another data transfer before issuing the stop code, you can send the start code using the repeat start command (with iiccon[1:0] = ?1?). when the slave address and read/write control bit have been sent, and when the receive acknowledge ahs been issued to control scl timing, the data transfer is initiated.
S3FB42F i 2 c-bus interface 21- 3 i 2 c special registers multi-master i 2 c-bus control register the i 2 c-bus control register, iiiccon, is used to control the i 2 c module. register address r/w description reset value iiccon 0xb8 r/w i 2 c-bus control register 00h [1:0] i 2 c-bus arbitration control this two-bit value controls i 2 c operations. 00: no interrupt, pending 01: generate start condition and shift address byte 10: shift data byte 11: generate stop condition [3:2] i 2 c-bus tx/rx mode selection this two-bit value determines which mode is current ly able to read/write data from/to iicdata. 00: slave rx mode (default) 01: slave tx mode 10: master rx mode 11: master tx mode [4] i 2 c-bus acknowledge (ack) this bit value determines whether i 2 c-bus enables enable bit or disables the ack signal generation. [5] i 2 c bus enable bit this bit specifies whether i 2 c-bus is enabled or disabled. 0: disable serial tx/rx 1: enable serial tx/rx [6] ? ? [7] reset if '1' is written to this bit, the i 2 c bus controller is reset to its initial state (it is not automatically cleared).
i 2 c-bus interface S3FB42F 21- 4 multi-master i 2 c-bus control/status register (iicsr) the multi-master i 2 c-bus control/status register, iccsr, four bits, iccsr.3?iccsr.0, are read-only status flags. iccsr register settings are used to control or monitor the following i 2 c-bus functions (see figure): ? i 2 c-bus busy status flag ? failed bus arbitration procedure status flag ? slave address/address register match or general call re ceived status flag ? slave address 00000000b (general call) received status flag ? last received bit status flag (not ack = "1", ack = "0") register address r/w description reset value iicsr 0xb9 r/w i 2 c-bus status register 00h [0] last-received bit (lrb) status flag iicsr[0] is automatically set to 1 whenever an ack signal is (read only) not received during a last bit receive operation. when the last receive bit is zero, an ack signal is detected and the last-received bit status flag is cleared. [1] general call status flag iicsr[1] is automatically set to 1 whenever '00000000b', (read only) general call value is issued by the received slave address. when the start/stop condition was occurred, iicsr[1] is cleared. [2] master address call status flag iicsr[2] is automatically set to 1 whenever the received slave (read only) address matches the address value in iicaddr register. this bit is cleared after start/stop condition is occurred. [3] arbitration status flag iicsr[3] is automatically set to 1 to indicate that a bus (read only) arbitration has been failed during i 2 c-bus interface. the zero of iicsr[3] means okay status for the current i 2 c-bus interface. [4] iic operation status flag (read) iicsr[4] is automatically set to 1 to indicate that the end of shifting for byte or stop condition is occurred. this bit is cleared when iic operations are activated by writing iiccon. iic interrupt source enable (write) in write operation for this bit, this bit value determines th at interrupt is enable or not to indicate the end of shifting for byte or stop condition is occurred. 0: no interrupt, pending 1: iic interrupt [5] iic-bus busy status (read-only) iicsr[5] indicates that iic-bus is not busy and the '1' status means iic-bus is busy. this bit is set after start condition is detected and cleared after stop condition is occurred. [7:6] scl/sda digital filter selection setting this bit enables digital filtering on all two signal inputs: scl and sda. 00: disa ble 01: 1 clock period 10: 2 clock period filtering 11: 3 clock period filtering
S3FB42F i 2 c-bus interface 21- 5 multi-master i 2 c-bus transmit/receive data register (iicdata) in a transmit operation, data that is written to the iicdata is transmitted serially, msb first. (for receive operations, the input data is written into the iicdata register lsb first.) the iiccon.5 setting enables or disables serial transmit/receive operations. when iiccon.5 = "1", data can be written to the an i 2 c data register. the i 2 c-bus data register can, however, be read at any time, regardless of the current iiccon.5 setting. register address r/w description reset value iicdata 0xba r/w i 2 c-bus data register xxh [7:0] data this data field acts as serial shift register and read buffer for interfacing to the i 2 c-bus. all read and write operations to/from the i 2 c-bus are done via this register. the iicdata register is a combination of a shift register and a data buffer. 8-bit parallel data is always written to the shift register, and read from the data buffer. i 2 c- bus data is always shifted in or out of the shift register. lsb msb multi-master i 2 c-bus tx/rx data shift register (iicdata) offset address: 0x, r/w 8-bit data shift register for i 2 c-bus tx/rx operations: when iiccon .5 = "1", iicdata is write-enabled. you can read the iicdata value at any time, regardless of the current iiccon .5 setting. .7 .6 .5 .4 .3 .2 .1 .0 figure 21-2. multi-master i 2 c-bus tx/rx data register (iicdata) multi-master i 2 c-bus address register (iicaddr) the address register for the i 2 c-bus interface, iicaddr, is located at address 0xbb. it is used to store a latched 7 -bit slave address. this address is mapped to iicaddr.7?iicaddr.1; bit 0 is not used (see figure 21-3). the latched slave address is compared to the next received slave address. if a match condition is detected, and if the latched value is 00000000b, a general call status is detected. register address r/w description reset value iicaddr 0xbb r/w i 2 c-bus address register xxh
i 2 c-bus interface S3FB42F 21- 6 lsb msb multi-master i 2 c-bus address register (iicaddr) address: 0x8b, r/w 7-bit slave address, latched from the i 2 c-bus: when iiccon.5 = "0", iicaddr is write-enabled. you can read the iicaddr value at any time, regardless of the current iiccon.5 setting. .7 .6 .5 .4 .3 .2 .1 - not used for the s3fb41d figure 21-3. multi-master i 2 c-bus address register (iicaddr) prescaler register (iicps) the prescaler register for the i 2 c-bus is described in the following table. register address r/w description reset value iicps 0xbc r/w i 2 c-bus prescaler register xxh [7:0] prescaler value this prescaler value is used to generate the serial i2c-bus clock. the system clock is divided by (4 ( prescaler value + 1) ) to make the serial i 2 c clock. if the prescaler value is zero, i 2 c operation may be worked incorrectly. prescaler counter register (iiccnt) the prescaler counter register for the i 2 c-bus is described in the following table. register address r/w description reset value iiccnt 0xbd r i 2 c-bus prescaler counter register xxh [7:0] prescaler counter value this 8-bit value is the value of the prescaler counter. it is read (in test mode only) to check the counter's current value.
S3FB42F random numbe r generator 22- 1 22 random number gener ator overview the S3FB42F internal random number generator block has the following features: ? 2 ring oscillators, which run at ?33mhz and ?8mhz. they operate in a fully asynchronous manner with the cpu clock and are used as a clock to lfsr8. ? an 8-bit register lfsr8 is a linear feedback shift register, which changes its state with the clock from the ring oscillators. lfsr8 can serve as a source of the random number generation. ? a 16-bit register lfsr16 is a 16-bit linear feedback shift register, whose coefficients are provided by lfsr8. it changes its state when the lower byte is read. ? for the maximum flexibility, the programmers can use either lfsr8 or lfsr16 as the random number generator of their choice. if 16-bit or longer random numbers are required, lfsr16 can be preferred. otherwise, lfsr8 can be a better choice. figure 22-1 shows a block diagram of the S3FB42F random number generator.
random number generator S3FB42F 22- 2 lfsr16[15:8] (lfsr16h) write or lfsr16[15:8] (lfsr16h) read 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rancon lfsr8 lfsr16[7:0] (lfsr16l) lfsr8 read or write lfsr8 = 0 rancon write rancon[0] lfsr16[15:8] (lfsr16h) toggle3 toggle7 toggle2 toggle1 toggle6 toggle5 toggle4 lfsr16[7:0] write or lfsr16[15:8] read din[7:0] lfsr8[0] toggle0 lfsr8[1] toggle1 lfsr8[2] toggle2 lfsr8[3] toggle3 lfsr8[4] toggle4 lfsr8[5] toggle5 lfsr8[6] toggle6 lfsr8[7] toggle7 rancon[2] toggle0 din[7:0] din[7:0] ring oscillator 7 6 5 4 3 2 1 0 din[7:0] figure 22 -1. top block diagram of random number generator
S3FB42F random numbe r generator 22- 3 functional description the S3FB42F random number generator has 4 registers, lfsr16[15:8] (lfsr16h), lfsr16[7:0] (lfsr16l), lfsr8, and rancon, which are addressed by abh, aah, a9h, and a8h, respectively. for better randomness, it has two ring oscillators, the fast ring oscillator and the slow ring oscillator, which run at ~33mhz and ~8mhz, respectively. random number control register the random number control register, rancon, is used to control the random number generator module. register address r/w description reset value rancon 0xa8 r/w control register for random number generation xxh [0] lfsr8 clock selection or ring oscillator disable this bit is used to select the clock source for lfsr8. lfsr8 can be clocked either by the ring oscillator output or by the access signals from the core. when this bit is set, the ring oscillator output signal is tied to high. see the detailed description for lfsr8 0: core r/w signals 1: ring oscillator [1] ring oscillator selection the ring oscillator block consists of 2 ring oscillators, which run at ~33mhz and ~8mhz, respectively. this bit multiplexes the two ring oscillators to the ring oscillator output. 0: fast ring oscillator 1: slow ring oscillator [2] polynomial switch if this bit is clear, the polynomial coefficients of lfsr16 is not affected by the value of lfsr8. otherwise, the polynomial coefficients are determined by the value of lfsr8. referring to the top block diagram, this serves as the mask bit for toggle0, toggle1, ?, toggle7. 0: toggle bits mask 1: toggle bits on [3] test bit this bit is for test purpose. when rancon[0] is set and the ring oscillator makes a rising transition, then this is set. [4] test bit this bit is for test purpose. when rancon[0] is set and the ring oscillator makes a falling transition, then this is set. [5] slow ring off if this bit value is set, the slow ring oscillator stops. 0: slow ring oscillator run 1: slow ring oscillator stop. [6] fast ring off if this bit value is set, the fast ring oscillator stops. 0: fast ring oscillator run 1: fast ring oscillator stop. [7] ? ?
random number generator S3FB42F 22- 4 ring oscillator the ring oscillator block consist of 2 ring oscillators, one of which runs at ~33mhz, which is called ?fast ring oscillator? and the other runs at ~8mhz, which is called ?slow ring oscillator?. the frequencies of the ring oscillators are determined by the gate size as well as the number of gates in the oscillator loop. depending on a specific application, programmers can select the fast or the slow ring oscillators, which can serve the application best. since the ring oscillators run totally asynchronously with the master clock of the chip, they can clock lfsr8m which, in turn, can be used as an 8-bit random number generator. the ring oscillators are laid out to be sensitive to fabrication conditions, the exact frequencies of the ring oscillators can vary from a chip to another. each ring oscillator can be stopped by setting the corresponding control bit, fast ring off or slow ring off, in order to save power consumption. ring oscillator selection (rancon[1]) ring oscillator disable (rancon[0]) 1 0 fast ring off (rancon[6]) slow ring off (rancon[5]) figure 22-2. ring oscillator block
S3FB42F random numbe r generator 22- 5 linear feedback shift register 8 (lfsr8) lfsr8 is a register for generating 8-bit random numbers. when rancon[0] (lfsr8 clock selection) is set, lfsr8 is linear feedback shifted at the rising edge of the ring oscillator output. when rancon[0] is clear, the core ( calmrisc) can parallel load the data through the input data bus (din[7:0]) by writing the data to the address 0x92h. also the core can read the contents of lfsr8 by reading the address 0xa9, regardless of the value of rancon[0]. note that when the core reads in the contents of lfsr8, a single linear feedback shift operation is performed right after the read operation if rancon[0] = 0. register address r/w description reset value lfsr8 0xa9 r/w 8-bit linear feedback shift register xxh lfsr8[7:0] when rancon[0] = 1, a linear feedback shift operation is performed at the rising edge of the ring oscillator output. in this case, the core ( calmrisc core) cannot write data into lfsr8. when rancon[0] = 0, the core can write data into lfsr8 by a load instruction to the address 0xa9. a read operation on lfsr8 is automatically followed by a linear feedback shift operation. note: when rancon[0] = 1, a write operation by the core has no effect and a linear feedback operation does not automatically ensue after a core read operation. linear feedback shift register 16 (lfsr16) lfsr16 is a 16-bit linear feedback shift register, which can be parallel loaded through a core write operation or linear feedback shifted by a core read operation on lfsr[15:8]. the polynomial coefficients of lfsr is determined by the value of lfsr8, only when rancon[2](polynomial switch) is set. otherwise, the polynomial coefficient is fixed such that lfsr16 performs a simple rotate operation. register address r/w description reset value lfsr16[15:8] (lfsr16h) 0xab r/w 16-bit linear feedback shift register xxh lfsr16[7:0] (lfsr16l) 0xaa r/w xxh
random number generator S3FB42F 22- 6 lfsr16[15:8] and lfsr16[7:0] lfsr16h[15:8] and lfsr16l[7:0] can be individually read and loaded. a linear feedback shift operation is performed on lfsr16[15:0] right after lfsr16h[15:8] is read. the linear feedback shift operations follow the rule below: rancon[2]=0 a simple rotate operation is executed. lfsr16[15] = lfsr16[0] lfsr16[14] = lfsr16[15] lfsr16[0] = lfsr16[1] rancon[2]=1 a linear feedback operation is executed. lfsr16[15] = (toggle0&lfsr16[2])^(toggle1&lfsr16[3])^ (toggle1&lfsr16[5])^(toggle1&lfsr16[9])^ lfsr16[0] lfsr16[14] = lfsr16[15] lfsr16[13] = toggle4^ lfsr16[14] lfsr16[12] = toggle5^ lfsr16[13] lfsr16[11] = lfsr16[12] lfsr16[10] = toggle6^ lfsr16[11] lfsr16[9] = lfsr16[10] lfsr16[8] = lfsr16[9] lfsr16[7] = lfsr16[8] lfsr16[6] = toggle7^ lfsr16[7] lfsr16[5] = lfsr16[6] lfsr16[4] = lfsr16[5] lfsr16[3] = lfsr16[4] lfsr16[2] = lfsr16[3] lfsr16[1] = lfsr16[2] lfsr16[0] = lfsr16[1] where toggle0 = lfsr8[0]&rancon[2] : : toggle7 = lfsr8[7]&rancon[2]
S3FB42F usb 23- 1 23 usb usb peripheral features table 23-1. general usb features complete usb specification yes on-chip usb transceivers yes automatic transmit/receive fifo management yes suspend/resume yes usb rate (full speed) 12 mbps usb interrupt vectors yes table 23-2. general function features control endpoint 1 data endpoints 3 fifo sizes endpoint 0 endpoint 1 endpoint 2 endpoint 3 16 bytes 32 bytes 64 bytes 64 bytes direction of data endpoints in/out supported transfer of data endpoints interrupt/bulk/isochronous transfer functional specification ? power management ? general purpose full speed controller ? each data endpoints support interrupt, bulk and isochronous transfer ? protocol handling in hardware ? built-in full-speed tranceiver
usb S3FB42F 23- 2 the basic blocks are the serial interface engine (sie), mcu interface unit (miu), function interface unit (fiu) and sie interface unit (siu). usb module block diagram pll block serial interface engine (sie) sie interface unit (siu) funtion interface unit (fiu) mcu interface unit (miu) power control mcu transceivers (xcvr) 48 mhz up stream port pwr d- d+ control/status figure 23-1. usb module block diagram
S3FB42F usb 23- 3 function description transceivers (xcvr) the transceiver consists of a differential receiver, two single ended receivers and two drivers. that is capable of transmitting and receiving data at 12 mbit/sec and 1.5 mbit/sec meeting the usb requirements. serial interface engine (sie) the serial interface engine implements the protocol layer of the usb. it does the clock recovery, error checking, data conversion between serial and parallel data, do the handshake on the usb bus if the packet was directed to it, bus timeout if response from the host is late, and all other usb protocol related functions. it consists of phase locked loop (pll) for clock recovery from the incoming data, crc checker and generator, bit stuff and bit removal logic, nrzi encoder/decoder, shift register for serial/parallel conversion, pid decoder, data toggler and sync detect logic. sie interface unit (siu) the sie interface unit interfaces with sie to get the parallel data and pass on to the fiu. other important function of the siu is to compare the device and endpoint address in the token packet with the valid device and endpoint addresses from the embedded function, and generate a address valid signal to the sie so it can complete the handshake to fiu so they can get started waiting for the data phase. function interface unit (fiu) function interface unit consists of endpoint0 and three additional endpoints for the embedded function. the endpoint0 logic consists of 16 byte bi-directional fifo and all the control logic necessary to interface with the siu on one side and with the mcu interface logic on the other side. the control logic keeps track of data toggle bit in a multiple packet transaction and resend of the data when the request is retried by the host. it handles the setting and clearing of the endpoint stall bit. the out/setup data from the fifo is read by the mcu interface and data for the in is loaded into the fifo by mcu interface. the three additional endpoints are programmable as in or out endpoint, and they can be interrupt, bulk or isochronous types. each endpoint consists of 32, and 64 byte bi-directional fifos used in one direction only with direction programmed via a control bit in their respective csr register. the data transfers between the mcu and the fifos are controlled by setting/clearing bits in the csr. interrupt may be generated on occurrence of some significant events and this interrupt can be disabled by the firmware. mcu interface unit (miu) this block of logic will allow the mcu to interface to the fiu units. this block will handle the mcu timing, address decoding and data multiplexing.
usb S3FB42F 23- 4 suspend/resume: the suspend timer is used to detect inactivity on the upstream port. if no sof is received for more than 3 ms device enters a suspend state and suspend signal is asserted. on detecting suspend, stop_clk signal can be asserted by the mcu (or external hardware) to stop the clock in the usb block. when resume is detected by the upstream port control logic the suspend signal is removed and suspend state is reset at the end of resume. mcu can also do a remote wakeup by asserting resume_in to the usb block. mcu programming: mcu firmware need to support the function unit completely, all the traffic related to the embedded port will be relayed to the mcu by the usb block. the host commands supported by the function unit will depend on the device firmware is implementing e.g. in monitor application hid class besides the required standard commands need to be supported. the usb block presents number of registers to the mcu for controlling, monitoring and data transfers.
S3FB42F usb 23- 5 usb function registers description table 23-3. usb function registers description register name addr r/w/c description funaddr 80h r/w function address register pwrman 81h r/w power management register framelo 82h r frame number lo register framehi 83h r frame number hi register intreg 84h r/w interrupt pending register intena 85h r/w interrupt enable register epindex 86h r/w endpoint index register epdir 89h w endpoint direction register incsr 8ah r/w in control status register outcsr 8bh r/w out control status register inmaxp 8ch r/w in max packet register outmaxp 8dh r/w out max packet register wrtcntlo 8eh r/w write counter lo register wrtcnthi 8fh r/w write counter hi register ep0fifo 90h r/w endpoint 0 fifo register ep1fifo 91h r/w endpoint 1 fifo register ep2fifo 92h r/w endpoint 2 fifo register ep3fifo 93h r/w endpoint 3 fifo register usbena 9eh r/w usb enable register
usb S3FB42F 23- 6 usb releated registers some of the registers in the usb function unit are similar, specially pertaining to the endpoints. hence the description of those registers will be presented only once here in the usb related registers to avoid duplication and avoid keep both sets updated. function address register register address r/w description reset value funaddr 0x80 r/w function address register 00h at reset the address is 00h. after the set_address is received by the mcu, it should load the address received into this register. this register is enabled for address comparison after the "status" phase of the set_address control transfer. this is so that the status in packet which will still have "0" address can to be recognized for this embedded function by the hardware in the siu. this register should be loaded before setting dataend and clearing outpktrdy in the ep0 csr. this register is cleared by the core when port reset is received from the host for the embedded port or when usb_reset has been received. lsb msb function address register (funaddr) 80h, r/w, reset: 00h not used usb device address .7 .6 .5 .4 .3 .2 .1 .0 figure 23-2. function address register
S3FB42F usb 23- 7 power management register this register is used for power management in the function controller core. register address r/w description reset value pwrman 0x81 r/w power management register 00h suspend: when the function receives a suspend signaling, the function controller core sets this bit. this also generates an interrupt to the microcontroller. upon seeing this bit set, the microcontroller can store its internal register and enter suspend mode, disabling the clock of the fucntion controller core. uc_resume: when the microcontroller is awakend by keyboard stroke or mouse movement, it starts its wakeup sequence and sets this bit. while this bit is set and the function is in suspend mode, the function generate a resume signaling as long as this bit for a 10 to 15ms duration to start the resume signaling, after the resume signaling, the microcontroller can clear both the suspend and send_resume bits. usb_resume: when the function controller core is in suspend mode and recieves resume signaling this bit is set and an interrupt is generated. the microcontroller, se this bit set, can start wake-up sequence usb_restn: the function contoller core sets this bit, if reset signaling is received from the host. lsb msb power management register (pwrman) 81h, r/w, reset: 00h not used .7 .6 .5 .4 .3 .2 .1 .0 suspend uc_resume usb_resume usb_restn figure 23-3. power management register
usb S3FB42F 23- 8 frame number register register address r/w description reset value framelo 0x82 r frame number low register 00h framehi 0x83 r frame number high register 00h on detection of sof from the host, this register is updated with the frame number received with the sof packet. lsb msb frame number low register (framelo) 82h, r, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 frame number low figure 23-4. frame number low register lsb msb frame number high register (framehi) 83h, r, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 not used frame number high figure 23-5. frame number high register
S3FB42F usb 23- 9 interrupt pending register register address r/w description reset value intreg 0x84 r/w interrupt pending register 00h this register is used to indicate the condition that sent and interrupt to the microcontroller. lsb msb interrupt pending register (intpnd) 84h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 ep0int ep1/in0 ep1/out0 ep2/in1 suspend resume ep3/out2 ep3/in2 ep2/out1 figure 23-6. interrupt pending register
usb S3FB42F 23- 10 table 23-4. interrupt pending register bit description usb mcu condition for interrupt ep0 (control) w r/c the usb sets this bit under the following conditions. 1.out_pkt_rdy is set 2.in_pkt_rdy is set 3.sent_stall is cleared 4.in_pkt_rdy is cleared ep1/in0 w r/c the usb sets this bit under the following conditions. in_pkt_rdy is cleared ep1/out0 w r/c the usb sets this bit under the following conditions. 1.set out_pkt 2.set force_stall endpt2/in1 w r/c the usb sets this bit under the following conditions. in_pkt_rdy is cleared ep2/out1 w r/c the usb sets this bit under the following conditions. 1.set out_pkt 2.set force_stall ep3/in2 w r/c the usb sets this bit under the following conditions. in_pkt_rdy is cleared ep3/out2 w r/c the usb sets this bit under the following conditions. 1.set out_pkt 2.set force_stall
S3FB42F usb 23- 11 interrupt enable register register address r/w description reset value intena 0x85 r/w interrupt enable register 00h this register serves as interrupt mask register. if the corresponding bit = 0 then the respective interrupt is disabled, and when = 1 interrupt is enabled. by default upon reset, all the interrupts are disabled. if an interrupt is being serviced firmware may want to mask the interrupt by masking the corresponding bit(s) or when certain interrupt status bits are going to be polled. lsb msb interrupt enable register (intena) 85h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 ep0int ep1/in0 ep1/out0 ep2/in1 suspend resume ep3/out2 ep3/in2 ep2/out1 0: disable 1: enable figure 23-7. interrupt enable register
usb S3FB42F 23- 12 endpoint index register register address r/w description reset value epindex 0x86 r/w endpoint index register 00h if iso_update bits is set, isocronous transaction is enabled in endpoint 1-6. endpoint 0-3 registers (in_csr,out_csr, cnt, maxp) share the same address space. to select between them, endpoint register is provided and mcu can load the register. the buffer data is available for each endpoint at unique addresses and are independent of the func_ep_sel bits. lsb msb endpoint index register (epindex) 86h, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 not used func_ep_sel iso_update figure 23-8. endpoint index register endpoint direction register register address r/w description reset value epdir 0x89 w endpoint direction register 00h if endpointx direction bit is 1, endpointx is for in transaction else endpointx is for out transaction. lsb msb endpoint direction register (epdir) 89h, w, reset: 00h not used .7 .6 .5 .4 .3 .2 .1 .0 ep1 direction (1: in, 0: out) ep2 direction (1: in, 0: out) ep3 direction (1: in, 0: out) figure 23-9. endpoint direction register
S3FB42F usb 23- 13 endp point 0 control status register when ep select register is equal to zero, endpoint out csr and endpoint in csr select the same endpoint0 csr. reading and writing to either address accesses the same register. this register has control and status bits for ep0, since control transactions involve both in and out token. register address r/w description reset value ep0csr 0x8a, 0x8b r/w ep0 csr register 00h ep0 usb mcu description out_pkt_rdy w r/c packet received from the host is ready in the fifo in_pkt_rdy r/c r/w packet to be sent to the host is ready in the fifo sent_stall w r/c usb sent a stall handshake to the host. data_end r/c r/w set by mcu when last data is loaded in fifo or no data is needed by the command setup_end w r/c set when current control transaction need to be aborted. force_stall r/c r/w force a stall handshake to the host(write only?) clr_out_pkt_rdy r w clear the out pkt rdy bit. clr_setup_end r w clear the setupend bit. out_pkt_rdy : the gfi sets this bits, whenever it has a valid token packet in the endpt0 fifo. the micro controller seeing this bit set, unloads the fifo and clears this bit. if it is the setup phase, then the micro controller also decodes the setup token, and checks to see if it is a valid command and, then clears this bit by doing clr_ep0_outpktrdy. at the time of clearing this bit, the micro controller will also set force_stall if it is a invalid command, and data end if the length of data transfer during data phase is zero (no data phase, viz., set_address). in_pkt_rdy : the micro controller after filling the fifo with a in data, set this bit. mcu should wait for this bit to be cleared by the gfi before loading next in token. if the function receives a valid in token, while in pkt rdy is not set by the micro controller then the endpt0 state machine issues a nak and shake. sent_stall : when the hardware decodes an illegal sequence from the host, it may send a stall on its own to the usb host. this bit is set to inform the mcu that such an event has happened. this is informational only and does not cause an interrupt, and it needs to be cleared by the mcu after it has seen it.
usb S3FB42F 23- 14 data_end : during the data phase of a control transfer, after the micro controller has finished loading/unloading the exact number of bytes as specified in the setup phase, it sets this bit. force_stall : when an illegal or unsupported command is decoded by the firmware it needs to set this bit. when set, this bit causes the hardware to return a stall handshake to the host and is reset by the hardware when handshake has been sent. this bit should not be set when host does a set_feature stall, as this will cause all transfers to/from endpoint 0 to return stall. this behavior is different for other endpoints. once the micro controller sees this bit set, it should end the setup phase, stop loading/unloading the fifo (note: micro controller does not set data_end in this case). the gfi before setting this bit flushes the fifo, and prevents micro controller accesses to the fifo. clr_outpkt_rdy : write a *1* to this bit to clear the out packet ready. this bit not sticky, it can be set in conjunction with other bits. clr_setup_end : write a *1* to this bit to clear setup_end bit. this again is not sticky and can be set together with other bits lsb msb ep0 csr register (ep0csr) 8ah, 8bh, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 out_pkt_rdy in_pkt_rdy sent_stall data_end clr_setup_end clr_out_pkt_rdy force_stall setup_end figure 23-10. ep0 csr register (ep0csr)
S3FB42F usb 23- 15 in control status register for endpoints other than 0, separate in and out registers are available and micro-code should read the register the endpoint has been programmed for. register address r/w description reset value incsr 0x8a r/w in control status register 00h endpt1csr bit usb mcu description in_pkt_rdy r/c r/w when packet has been load into fifo by mcu and ready for transfer to the host, write '1' to this bit. underrun w r/c usb under-run error during iso. force stall r/c r/w force a stall handshake to the host. iso r r/w if set, indicates an isocronous endpoint. intpt_endpt r r/w if set, usb sends packet whatever data is there in the fifo. in_pkt_rdy2 r/c r when mcu writes a '1' to bit 0,this bit is always set. it is cleared by the usb when the data has been transferred to the host. fifo_flush r/c w the mcu sets this bit if it intends to flush the in fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in progress, the usb waits until the transmissions in complete before the fifo is flushed. clr_data_toggle r w when the mcu writes a 1 to this bit, the data toggle bit is cleared. this is a write-only. in_pkt_rdy : the micro controller after filling the fifo with a in data, set this bit. mcu should wait for this bit to be cleared by the usb before loading next in token. if the function receives a valid in token, while in pkt rdy is not set by the micro controller then the endpt state machine issues a nak handshake. under run : this bit is used to isocronous endpoints. it is set if the function times out to an in token. iso : if this bit is set, the endpoint behaves as an isocronous endpoint. force_stall : this bit is set by the micro controller. whenever this bit is set, the function controller issues a stall handshake to the host. this bit may be set by the mcu for any fault condition within the function or when host does a set_feature (endpoint_stall). it is cleared by the micro controller when it receives a clear_feature (endpoint_stall) command from the host. in_pkt_rdy2 : when mcu writes a *1* to bit 0 position, this bit always gets set and is cleared by the hardware when all the packets have been transferred to the host.
usb S3FB42F 23- 16 lsb msb incsr register (incsr) 8ah, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 in_pkt_rdy underrun force_stall iso clr_data_toggle fifo_flush in_pkt_rdy2 inpt_endpt figure 23-11. incsr register
S3FB42F usb 23- 17 out control status register register address r/w description reset value outcsr 0x8b r/w out control status register 00h out csr bit usb mcu description out_pkt_rdy w r/c packet received from the host is ready in the fifo overrun w r/c this is set only in iso mode. usb sets this bit when overrun is detected. send_stall r/c r/w mcu forces a stall handshake to the host. force_stall w r/c usb sets this bit when out transaction ended with stall handshake. this happens when: 1. host sends more then maxp data. 2. usb detected protocol violation. iso r r/w if set, indicates an isocronous endpoint. data_err w r/c this is set only in iso mode. usb sets this bit if at the time of setting outpktrdy if an error has occurred. out_pkt_rdy : the gfi sets this bits, whenever it has a valid token packet in the endpt1 fifo. the micro controller seeing this bit set, unloads the fifo and clears this bit by doing writing a *1* to this bit. at the time of clearing this bit, the micro controller should also set send_stall if a stall condition exists. overrun : this is used for isochronous endpoints only, if an out token packet is receved and the out_pkt_rdy from the pervious transactions is not cleared, the usb discard the data and set this bit to indicate to the micro controller that an out packet was lost. send_stall : this bit is set by the micro controller. whenever this bit is set, the function controller issues a stall handshake to the host. this bit may be set by the mcu for any fault condition within the function or when host does a set_feature(endpoint_stall). it is cleared by the micro controller when it receives a clear_feature(endpoint_stall) command from the host. iso : if this bit is set, the endpoint behaves as an isocronous endpoint. if this bit is dear, the endpoint be haves as a bulk or interrupt endpoint. force_stall : usb sets this bit when out transaction ended with stall handshake. this happens when: 1. host sends more than maxp data. 2. usb detected protocol violation. data_err : for iso endpoint , hw sets out pkt rdy even if the core has a crc/bit stuffing error. but data_err bit is also set in this case. if the microcode is capable of error recovery it can unload the packet, else it can flush the fifo, which will clear out the fifo and reset out pkt rdy.
usb S3FB42F 23- 18 lsb msb out control status register (outcsr) 8bh, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 out_pkt_rdy overrun send_stall iso not used data_err force_stall figure 23-12. out control status register
S3FB42F usb 23- 19 in max packet register register address r/w description reset value inmaxp 0x8c r/w in max packet register 00h name usb mcu description maxp r r/w 0000 maxp = 0 0001 maxp = 8 0010 maxp = 16 0011 maxp = 24 0100 maxp = 32 0101 maxp = 40 0110 maxp = 48 0111 maxp = 56 1000 maxp = 64 this register has maximum packet size for the in endpoint. the packet is selectable in multiple of 8 byte. lsb msb in max packet register (inmaxp) 8ch, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 not used maxp figure 23-13. in max packet register (inmaxp)
usb S3FB42F 23- 20 out max packet register register address r/w description reset value outmaxp 0x8d r/w out max pocket register 00h name usb mcu description maxp r r/w 0000 maxp = 0 0001 maxp = 8 0010 maxp = 16 0011 maxp = 24 0100 maxp = 32 0101 maxp = 40 0110 maxp = 48 0111 maxp = 56 1000 maxp = 64 this register has maximum packet size for the out endpoint. the packet is selectable in multiple of 8byte. lsb msb out max packet register (outmaxp) 8dh, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 not used maxp figure 23-14. out max packet register
S3FB42F usb 23- 21 ep0 max packet register register address r/w description reset value ep0maxp 0x8c, 0x8d r/w ep0 max packet regsiter 00h name usb mcu description maxp r r/w 00 maxp = 8 01 maxp = 16 this register has maximum packet size for the endpoint0. the packet is selected as either 8 or 16 bytes. lsb msb ep0 max packet register (ep0maxp) 8ch, 8dh, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 not used maxp figure 23-15. ep0 max packet register
usb S3FB42F 23- 22 write counter register register address r/w description reset value wrtcntlo 0x8e r/w write counter low register 00h wrtcnthi 0x8f r/w write counter high register 00h when out_pkt_rdy is set for epx, this register maintains the number of bytes in the epx_out_fifo. lsb msb write counter low register (wrtcntlo) 8eh, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 write count value figure 23-16. write counter lo regsiter lsb msb write counter high register (wrtcnthi) 8fh, r/w, reset: 00h .7 .6 .5 .4 .3 .2 .1 .0 reserved figure 23-17. write counter hi register
S3FB42F usb 23- 23 endpoint0 fifo register register address r/w description reset value ep0fifo 0x90 r/w endpoint0 fifo register 00h this register is used to read the endpoint0 fifo. the endpoint0 is bidirectional and can be accessed either by usb or the microcontroller. the default direction is from the gfi to the microcontroller. however, oncethe endpoint0 receives a setup token, and it has decoded the direction of the data phase of the control transfer to be in, the direction of the fifo is changed. endpointx fifo register register address r/w description reset value ep1fifo 0x91 r/w endpoint1 fifo register 00h ep2fifo 0x92 r/w endpoint2 fifo register 00h ep3fifo 0x93 r/w endpoint3 fifo register 00h this register is used to access endpointx whith the microcontroller.
usb S3FB42F 23- 24 usb enable register register address r/w description reset value usbena 0x9e r/w usb enable register 00h if mcu is reseted by power on reset or external reset, you must manuplate this register to enable usb function. lsb msb usb enable register (usb enable) 9eh, r/w, reset: 00h not used usb clk enable .7 .6 .5 .4 .3 .2 .1 .0 usb block enable figure 23-18 usb enable register
S3FB42F embedded fla sh memory interface 24- 1 24 embedded flash memo ry interface overview the S3FB42F has an on-chip flash rom instead of masked rom. the flash rom is accessed by serial data format and the type of a half flash. the S3FB42F's embedded 106.5 k-word (213 k-byte) memory has several operating features below: the S3FB42F has 6 pins used to read/write the flash memory, v dd /v ss, reset, v pp, sdat, sclk. the flash memory control block supports tool program mode : tool program mode the 6 pins are connected to a tool board and programmed by serial otp tool(mds). 12.5v is supplied into the v pp pin. the other modules except flash rom module are at a reset state. this mode doesn't support sector erase but chip erase and two protection modes. (hard lock protection/ read protection)
embedded flash memory interface s3fb42 f 24- 2 00000h 11fffh 13fffh 19fffh 18800h y-rom bank 2 (flash data memory) 17fffh 15c00h 12000h y-rom bank 1 (flash data memory) y-rom bank 0 (flash data memory) code memory (flash program memory) 6kl word 9kl word 8kl word 72k word blank(7klw) blank(2klw) figure 24-1. flash memory structure
S3FB42F embedded fla sh memory interface 24- 3 flash memory control register fmcon register controls what is concerned with an internal flash memory including data memory bank selection. register address r/w description reset value fmcon 0078h r/w flash memory control register 00h [0] data memory bank selection S3FB42F has two banks -bank0, bank1- as data memory in calmrisc side. (see chapter2.address space for the banks) this bank selection bit should be controlled before accessing any address in data memory bank0 or bank1. 0: bank0 1: bank1 [2:1] y-data flash memory bank select this bank selection bit should be controlled before accessing any address in y-data flash memory. 00: no select 01: select bank 0 10: select bank 1 11: select bank 2 [3] flash memory accessing speed selection 0: when fxx is under 4mhz 1: when fxx is more than 4mhz [5:4] i/o area accessing wait cycle selection 1 cycle or 2 cycles delay time can occurs by setting these bits when any address in i/o area is accessed. 00: wait 0 cycle 01: wait 1 cycle 1x: wait 3 cycles [6] rom accessing wait cycle enable 1 cycle or 2 cycles delay time can occur by setting this bit when rom area is accessed. 0: disable 1: enable 1 cycle stretch [6] flash data memory stretch enable it is recommended to enable this bit when calm cpu access to data flash memory. 0: disable 1: enable 1 cycle stretch (don't care when dsp instruction)
embedded flash memory interface s3fb42 f 24- 4 [0] data memory bank selection bit 0 = bank0 1 = bank1 [2:1] y-data flash memory selection bits 00 = no select 01 = selection bank 0 10 = selection bank 1 11 = selection bank 2 [3] flash memory speed selection bit 00 : when fxx is under 4 mhz 01 : when fxx is more than 4 mhz [5:4] i/o area accessing wait cycle selection bit 00 = not-used wait cycle 01 = wait 1 cycle 1x = wait 3 cycles [6] rom accessing wait cycle enable 0 = disable 1 = enable 1 cycle stretch [7] y-data flash memory stretch control 0 = disable 1 = enable 1 cycle stretch (don't care when dsp instruction) 0 6 5 3 2 7 "0" 1 4 x x x x x x x figure 24-2. flash memory control register
S3FB42F mac2424 25- 1 25 mac2424 introduction mac2424 is a 24-bit high performance fixed-point dsp coprocessor for calmrisc microcontroller. mac2424 is designed for the mid to high-end audio applications which require low power consumption and portability. it mainly includes a 24-bit arithmetic unit (aru), a barrel shifter & exponent unit(beu), a 24-bit x 24-bit multiplier accumulation unit (mau), and a ram pointer unit (rpu) for data address generation. main datapaths are constructed to 24-bit width for audio applications, but it can also perform 16-bit data processing efficiently in 16-bit operation mode. mac2424 is designed to be the dsp coprocessor for calmrisc microcontroller. it receives 12-bit instruction code and command information from calmrisc via special coprocessor interface and send internal status information to calmrisc through external condition port.
mac2424 S3FB42F 25- 2 architecture features ? 16-bit barrel shifter with support for multi-precision capability ? 24-bit exponent evaluation with support for multi-precision capability ? four data address ram pointers with post-modification & modulo capability ? four index registers with two extended index registers : up to 8-bit index value ? two direct address ram pointers for short direct addressing ? min/max instruction with pointe r latching and modification ? division step in single cycle ? conditional instruction execution capability 24-bit mode operation ? signed fractional/integer 24 x 24-bit multiplication in single cycle ? 24 x 24-bit multiplication and 52-bit accumulation in a single cycle ? 24-bit arithmetic operation ? two 48-bit multiplier accumulator with 4-bit guard ? 32k x 24-bit data memory spaces 16-bit mode operation ? four-quadrant fractional/integer 16 x 16-bit multiplication in single cycle ? 16 x 16-bit multiplica tion and 40-bit accumulation in a single cycle ? 16-bit arithmetic operation with 8-bit guard ? two 32-bit multiplier accumulator with 8-bit guard ? 32k x 16-bit data memory spaces
S3FB42F mac2424 25- 3 block diagram msr2 msr1 x0/x1 ma0/1 52-bit adder 24 x 24 multiplier p ma0/1 x0/x1 x0/x1 y0/y1 modulo arithmetic rp0-3 sd0-3 mc0-1 rpd0-1 msr0 interface logic mau aru beu rpu status registers control modulo arithmetic xb[23:0] yb[23:0] a/b 24-bit adder a/b sr sg 24-bit exponent detector si sa 16-bit barrel shifter sa si figure 25-1. mac2424 block diagram
mac2424 S3FB42F 25- 4 the block diagram shows the main blocks that compose the mac2424: ? multiplier accumulator unit (mau) ? arithmetic unit (aru) ? barrel shifter & exponent detection unit (beu ) ? ram pointer unit (rpu) ? status registers ? interface unit the mac2424 dsp coprocessor is organized around two 24-bit data buses (xb, yb). data movement between the units and memories occur over xd and yd data buses. each of this data bus has its dedicated 14-bit address bus xa and ya respectively. i/o description mac2424 nxcs nycs mmwr xa ya memory interface 14 14 debug interface xb_dis ngidis bus interface 24 24 24 24 xbi ybi xbo ybo 12 ei iclk nres syscp ncopid nmrcs mrwr mraddr 4 3 host interface strap h16 figure 25-2. mac2424 pin diagram
S3FB42F mac2424 25- 5 two data and address buses are provided with control signals. the address xa and ya are 14-bit, and accesses data memories up to 16 kbyte with 24-bit data width. the host interface signals receive the coprocessor interface signals from calmrisc microcontroller, and send the status information through ei signals. for more information about coprocessor interface signals, please refer to calmrisc architecture manual. table 25-1. mac2424 pin description signal name width direction description iclk 1 i input clock nres 1 i reset bar syscp 12 i instruction bus ncopid 1 i instruction bus valid indication bar mraddr 4 i internal register selection address nmrcs 1 i internal register read/write enable bar mrwr 1 i internal register write enable ei 3 o internal status information nxmcs 1 o x memory chip select bar nymcs 1 o y memory chip select bar mmwr 1 o memory write enable xa 14 o x memory address ya 14 o y memory address xbi 24 i x memory data input bus ybi 24 i y memory data input bus xbo 24 o x memory data output bus ybo 24 o y memory data output bus h16 1 i 16-bit host processor indication xb_dis 1 i x memory data output bus disable ngidis 1 o global interrupt disable for long word instruction
mac2424 S3FB42F 25- 6 programming model in this chapter, the important features of each unit in mac2424 are discussed in details. how the data memories are organized is discussed and data memory addressing modes are explained. the major components of the mac2424 are : multiplier accumulator unit (mau) multiplier ? input registers x0, x1, y0, y1 ? output register p multiplier accumulators ma0, ma1 saturation logic multiplier accumulator shifter 52-bit arithmetic unit status register msr1 arithmetic unit (aru) accumulator a, b saturation logic accumulator shifter 24-bit arithmetic unit status registers msr0, msr2 barrel shifter & exponent detection unit (beu) 24-bit exponent detector 16-bit barrel shifter ? input registers sa, si ? output registers sg, sr ram pointer unit (rpu) two modulo address generators bit-reverse generator indirect address pointers rp0, rp1, rp2, rp3 index registers sd0, sd1, sd2, sd3 extended index registers sd0e, sd3e direct pointers rpd0, rpd1 modulo configuration registrers mc0, mc1
S3FB42F mac2424 25- 7 multiplier and accumulator unit the multiplier and accumulator unit contains two main units, the multiplier unit and the accumulator unit. the detailed block diagram of the multiplier and accumulator unit is shown in figure 25-3. x0 52-bit adder 24 x 24 multiplier p x1 y0 y1 shifter/saturation xb[23:0] yb[23:0] ma0 ma1 align align shifter shifter saturation figure 25-3. multiplier and accumulator unit block diagram
mac2424 S3FB42F 25- 8 multiplier the multiplier unit consists of a 24 by 24 to 48 bit parallel 2?s complement single-cycle, non-pipelined multiplier, 4 24-bit input registers (x0, x1, y0, and y1), a 48-bit output product register (p), and output shifter & saturation logic. the multiplier performs signed by signed multiplication in 24-bit mode, and 4 quadrant multiplication in 16-bit mode. together with 52-bit adder in mau, the mac2424 can perform a single-cycle multiply-accumulate (mac) operation. the multiplier only operates when multiply instruction is executed. the p register is not updated and the multiplier is not operated after a change in the input registers. this scheme reduces power consumption in multiplier. in 16-bit operation mode, multiplier input registers, x and y, are aligned (shifting 4 bits to the left) before multiplication, and 32-bit output result is written in bit 39 to 8 of p register. the bit 47 to 40 of p register is sign- extended, and lower 8-bit part are forced to 0. psh1 bit of msr1 register indicates whether multiplier output is shifted 1 bit to the left or not. if psh1 bit is set, multiplier output is shifted 1 bit to the left. this operation can be used in the signed fractional multiplication. usm bit of msr1 register indicates whether multiplier input register is signed or unsigned in 16-bit operation mode. when usm bit is set in 16-bit mode, x1 and y1 register is interpreted as an unsigned operand. for example, if x1 and y0 register is selected as multiplier input register, unsigned by signed multiplication is performed. if x1 and y1 register is selected, unsigned by unsigned multiplication is performed. note that unsigned operation is only possible in the 16-bit mode. the x or y register is read or written via the xb bus, and y register is written via yb when dual load instruction is executed. the 24-bit most significant portion (msp) of the p register ( ph) or the 24-bit least significant portion (lsp) of the p register (pl) can be written by the xb as an operand. when msp of the p register is written, lsp of the p register is forced to zero. when lsp of the p register is written, msp of the p register is not changed. in 16-bit operation mode, read or write operation on pl register is different from 24-bit operation mode. when pl write operation, the 16-bit most significant portion of pl register is written by the 16-bit least significant portion of xb bus, and 8-bit lsp of pl is forced to zero. on pl read operation, the 16-bit most significant portion of pl register is read to the 16-bit least significant portion of xb bus, and 8-bit msp of xb is sign-extended. the other registers performs the same operation as 24-bit mode. overflow protection in multiplier the only case the multiplier overflow occurs is when multiplying 800000h by 800000h in fractional 24-bit mode, and 8000h by 8000h in signed/signed fractional 16-bit mode. (these cases mean ?1*-1) : the result should be normally 1, which overflows fractional format. thus, in this particular case, a multiplier saturation block forces the multiplier result to 7fffffffffffh (24-bit mode) or 007fffffff00h (16-bit mode) after internal 1-bit shift to the left and write this value to the product register p. ? saturation condition at 24-bit mode: ~prod[47] & prod[46] & psh1 ? saturation condition at 16-bit mode: ~prod[39] & prod[38] & psh1 & sx & sy
S3FB42F mac2424 25- 9 multiplier accumulators each mai (i=0,1) is organized as two regular 24-bit registers (ma0h, ma0l, ma1h, ma1l) and two 4-bit extension nibble (ma0e, ma1e) in msr1 register. the mai accumulators can serve as the source operand, as well as the destination operand of ma relevant instructions. only one ma accumulator can be used as an operand at a time according to the bkma bit of the msr1 register. if bkma is set, ma1 register can be used, and if bkma is reset, ma0 register can be used. data transfer between two ma accumulators is possible through ?eld ma1, ma0? and ?eld ma0, ma1? instructions. these are the only cases when two ma accumulator is accessible independent on bkma bit and a full 52-bit ma accumulator is loaded. the 24-bit most significant portion (msp) of the ma register ( maih) or the 24-bit least significant portion (lsp) of the ma register ( mail) can be written by the xb as an operand. when maih register is written, mail register is forced to zero and maie extension nibble is sign-extended. when mail register is written, maih and maie are not changed. in 16-bit operation mode, read or write operation on mail register is different from 24-bit operation mode. the operation is same as pl register operation. when mail write operation, the 16-bit most significant portion of mail register is written by the 16-bit least significant portion of xb bus, and 8-bit lsp of mail is forced to zero. on mail read operation, the 16-bit most significant portion of mail register is read to the 16-bit least significant portion of xb bus, and 8-bit msp of xb is sign-extended. in case of 16-bit mode maih write operation, maie extension nibble is not sign-extended. extension nibbles extension nibbles ma0e and ma1e in msr1 register offer protection against 48-bit overflows in 24-bit mode operation. when the result of a 52-bit adder output crosses bit 47, it sets vmi flag of msr1 register (ma register overflow flag). when the sign is lost beyond the msb of the extension nibble, it sets mv flag of msr1 (memorized overflow flag) and latches the value. in 16-bit mode, these extension nibbles are not used at all and 8-bit most significant portion of the maih register is used as extension byte. if the result of a 52-bit adder output crosses bit 39, it sets vmi flag. overflow protection in ma registers the multiplier accumulator saturation instruction (esat instruction) sets the destination ma register to the positive negative maximum value, if selected ma register overflows ( vmi bit of msr1 register is set). in case of 24-bit mode, saturation values are 7fffffffffffh (positive overflow) or 800000000000h (negative overflow) for the ma register and extension nibble is sign-extended. in case of 16-bit mode, saturation value is different. when positive overflow occurs, the saturation value is 007fffffff00h for ma register, and when negative overflow, the saturation value is ff8000000000h. another saturation condition is when moving from maih register through xb bus. this saturation mode is enabled when selected ma register overflows ( vmi bit at msr1 register is set), and overflow protection bit is enabled (opm bit at msr1 register is set). in this case the saturation logic will substitute a limited data value having maximum magnitude and the same sign as the source register. the ma register value itself is not changed at all. in case of 24- bit mode, saturation values are 7fffffh (positive overflow) or 800000h (negative overflow) and in 16-bit mode, saturation values are 007fffh or ff8000h. ? saturation by instruction: "esat" instruction & vmi ? saturation by ma read: read maih & vmi & opm
mac2424 S3FB42F 25- 10 p 0 23 24 47 p 0 23 24 47 7 8 40 39 ph pl ph pl ph guard region mai 0 23 24 47 mah mal msr1_mai 48 51 ma guard region mai 0 23 24 47 mah mal msr1_mai 48 51 ma guard region 7 8 40 39 xi/yi 0 23 xi/yi 0 23 xi/yi xi/yi guard region xi/yi 15 16 x0/x1/y0/y1 p ma0/ma1 mode24 mode24 mode24 mode16 mode16 mode16 figure 25-4. mau registers configuration
S3FB42F mac2424 25- 11 arithmetic unit the arithmetic unit performs several arithmetic operations on data operands. it is a 52-bit, single-cycle, non-pipelined arithmetic unit. the arithmetic unit receives one operand from mai, and another operand from p register. the source and destination ma accumulator of arithmetic instruction is always the same. the arithmetic unit can perform positive or negative accumulate, add, subtract, shift, and several other operations, most of them in a single cycle. it uses two's complement arithmetics. some flags ( vmi, mv flag) are affected as a result of the arithmetic unit output value. the flags represent the ma register status. rounding provision rounding (by adding 800000h to the lsp of the ma register) can be performed by special instruction ("ernd" instruction) in a single cycle: two's complement rounding. after rounding operation, the 24-bit least significant portion of ma register are cleared and the 24-bit most significant portion of ma register are filled with the rounded value. ma shifting capabilities 52-bit ma register can be shifted by 1-bit left or right. all of this shift operation is arithmetic shift operation. double precision multiplication support the arithmetic unit support for double precision multiplication by add or subtract instruction with an alignment option of the p register. the p register can be aligned (shifting 24 bits to the right) before accumulating the partial multiplication result. division possibilities two specific instructions ("edivq" and "eresr" instruction) are used to implement a non-restoring conditional add/subtract division algorithm. the division can be only signed and two operands (dividend and divisor) must be all positive number. the dividend must be a 48-bit operand, located in ma register. : 4-bit extension nibble contains the sign extension of the ma register in 24-bit operation mode. in 16-bit operation mode, the dividend must be a 32-bit operand and 8-bit extension nibble in the ma register must be sign-extended. the divisor must be a 24-bit operand(24-bit mode) or 16-bit operand with sign-extended to 24-bit, located in 24-bit most significant portion of the p register. the 24-bit least significant portion of the p register must be zero. to obtain a valid result , the value of the dividend must be strictly smaller than the value of divisor (reading operand as fractional data). else, the quotient could not be expressed in the correct format. (for example, quotient greater than 1 for fractional format). at the end of algorithm, the result is stored in the ma register. (the same which previously contained the dividend) : the quotient in the 24-bit lsp, the significant bit remainder stored in the 24 msp of the ma register. typically 48/24 division can be executed with 24 elementary divide operations (32/24 division with 16 elementary divide operations), preceded by 1 initialization instructions (this instruction is required to perform initial subtraction operation.), and possibly followed by one restoring instruction which restores the true remainder (in case this last one is useful for the next calculations). note that lower precision can also be obtained by decreasing the number of elementary division step applied. the operation of elementary instructions for division is as follows.
mac2424 S3FB42F 25- 12 "edivq" : this single cycle instruction is repeatedly executed to generate division quotient bits. it calculates one bit of the quotient at a time, computes the new partial remainder, sets vmi bit of the msr1 register according to the new partial remainder sign. first, this instruction calculates the new partial remainder by adding or subtracting the divisor from the remainder, depending on current vmi bit value. if current vmi = 0, new partial remainder = old partial remainder ? divisor if current vmi = 1, new partial remainder = old partial remainder + divisor this add or subtract operation is performed between ma register and p register. second, this instruction shifts the new partial remainder one bit to the left and moves one bit quotient into the rightmost bit. the one bit quotient bit is the inverted value of the new partial remainder sign-bit. quotient bit = ~(sign of new partial remainder) third, edivq updates the ma register with shifted new partial remainder value, and updates the vmi bit of msr1 register with sign value of the new partial remainder. this vmi update determines the operation of the next edivq instruction. "eresr": this single cycle instruction restores the true remainder value. in fact, due to the non-restoring nature of the division algorithm, the last remainder has to be restored or not by adding 2 times the divisor, depending on the vmi bit of msr1 register previously computed. if vmi = 0, no operation is performed if vmi = 1, adds two times the divisor to the ma register. (containing the last calculated remainder in the 24-bit most significant portion) the new calculated remainder will have to be 24-bit right arithmetical shifted (16-bit right arithmetic shifted in 16-bit mode), in order to be represented in a usual fractional format.
S3FB42F mac2424 25- 13 dividend : 23 (0001 0111) divisor : 6 (0110) ma p 0 0001 0111 0110 0000 esla : ma 0 0010 1110 edivq : 1 1010 0000 + 1 1100 1110 1 1001 110 0 ma edivq : 0 0110 0000 + 1 1111 1100 1 1111 10 00 ma edivq : 0 0110 0000 + 0 0101 1000 0 1011 0 001 ma edivq : 1 1010 0000 + 0 0101 0001 0 1010 0011 ma eresr : 0 0000 0000 + 0 1010 0011 ma esra : ma 0 0101 0001 dividend : 17 (0001 0001) divisor : 6 (0110) ma p 0 0001 0001 0110 0000 esla : ma 0 0010 0010 edivq : 1 1010 0000 + 1 1100 0010 1 1000 010 0 ma edivq : 0 0110 0000 + 1 1110 0100 1 1100 10 00 ma edivq : 0 0110 0000 + 0 0010 1000 0 0101 0 001 ma edivq : 1 1010 0000 + 1 1111 0001 1 1110 0010 ma eresr : 0 1100 0000 + 0 1010 0011 ma esra : ma 0 0101 0001 quotient (3) quotient (2) remainder (5) remainder (5) figure 25-5. integer division example
mac2424 S3FB42F 25- 14 dividend : 23/128 (0001 0111) divisor : 6/8 (0110) ma p 0 0001 0111 0110 0000 edivq : 1 1010 0000 + 1 1011 0111 1 0110 111 0 ma edivq : 0 0110 0000 + 1 1100 1110 1 1001 11 00 ma edivq : 0 0110 0000 + 1 1111 1100 1 1111 1 000 ma edivq : 0 0110 0000 + 0 0101 1000 0 1011 0001 ma eresr : 0 0000 0000 + 0 1011 0001 ma dividend : 29/128 (0001 1101) divisor : 6/8 (0110) ma p 0 0001 1101 0110 0000 edivq : 1 1010 0000 + 1 1011 1101 1 0111 101 0 ma edivq : 0 0110 0000 + 1 1101 1010 1 1011 01 00 ma edivq : 0 0110 0000 + 0 0001 0100 0 0010 1 001 ma edivq : 1 1010 0000 + 1 1100 1001 1 1001 0010 ma eresr : 0 1100 0000 + 0 0101 0010 ma quotient (1/8) quotient (2/8) remainder (11/128) remainder (5/128) ma 0 0001 0111 ma 0 0001 1101 figure 25-6. fractional division example
S3FB42F mac2424 25- 15 a 48/24 integer division example code is as follows er vm // initialize division step esla ma // arithmetic shift left 1 edivq ma, p // division step ?. edivq ma, p // division step (24 times) eresr ma, p // remainder restoring esra ma // arithmetic shift right 1 a 48/24 fractional division example code is as follows. er vm // initialize division step edivq ma, p // division step ?. edivq ma, p // division step (24 times) eresr ma, p // remainder restoring note that the validity of the division operand must be checked before all of these code : i.e. the dividend is strictly smaller than the divisor. the following two figures show division with 9-bit dividend and 8-bit divisor. (assume that the ma register and p register are 8-bit wide, and ma guard bit is 1-bit wide.)
mac2424 S3FB42F 25- 16 status register 1 (msr1) msr1 register of three mac2424 status registers (msr0, msr1, msr2) is used to hold the flags, control bits, status bits for mau. the contents of each field definitions are described as follows. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ma1e ma0e opm usm mv vm1 vm0 bkma psh1 ma1 register extension nibble ma0 register extension nibble reserved (read as 0) ma register bank select 0 = ma0 register (reset value) 1 = ma1 register product left shift 1 control 0 = no shift (reset value) 1 = 1-bit left shift unsigned multiplication control 0 = signed (reset value) 1 = unsigned x1/y1 ma overflow protection (0 when reset) memorized overflow flag (0 when reset) ma1 overflow flag ma0 overflow flag figure 25-7. msr1 register configuration
S3FB42F mac2424 25- 17 ma1e/ma0e ? bit 15?12/bit 11?8 these four bit nibbles are used as guard bits for ma registers in 24-bit mode operation. these bits are updated when ma register write operation is occurred. in 16-bit mode operation these bits are not affected during ma write operation. these bits are also written during msr1 register write operation. bkma ? bit 6 this bit defines current bank of ma register. only one ma register of two ma registers is accessible at a time except "eld ma1, ma0" or "eld ma0, ma1" instruction. the bkma bit is only affected when msr1 register write operation or "er/es bkma" instruction is used. when this bit is set, current bank of ma register is ma1 register, and when this bit is clear, current bank of ma register is ma0 register. the bkma bit is cleared by a processor reset. psh1 ? bit 5 this bit defines multiplier output shift operation. when this bit is set, multiplier output result is 1-bit shifted left. this property can be used for fractional format operand multiplication. when this bit is clear, no shift is executed on the multiplier output. the psh1 bit can be modified by writing to msr1 register or "er/es psh1" instruction. the psh1 bit is cleared by a processor reset. usm ? bit 4 the usm bit indicates that the x1 or y1 register is signed or unsigned as a multiplicand. it is only used for product calculation in 16-bit mode operation. in 24-bit mode operation, this bit has no effect. when set, selected multiplicand is interpreted as a unsigned number if x1 or y1 register is selected. the other registers (x0, y0) are always signed number. the usm bit can be modified by writing to msr1 register or "er/es usm" instruction. the usm bit is cleared by a processor reset. opm ? bit 3 the opm bit indicates that saturation arithmetic is provided or not when moving from the higher portion of one of the ma registers through the xb bus. when the opm bit is set(overflow protection is enabled), the saturation logic will substitute a limited data value having maximum magnitude and the same sign as the source ma register. if the opm bit is clear, no saturation is performed. this bit has not effect on a "esat" instruction, which always saturates the ma register value. the opm bit is modified by writing the msr1 register or "er/es opm" instruction. the opm bit is cleared by a processor reset. mv ? bit 2 the mv bit is a memorized 52-bit overflow (in 24-bit mode) or 48-bit overflow (in 16-bit mode). this bit indicates that the guard bits of ma register is overflowed during previous arithmetic operations. this bit is set when overflow on guard bits is occurred and is not cleared when this overflow is cleared. it is only cleared when "er mv" instruction or msr1 register write instruction is executed. vm1/vm0 ? bit 1?0 these bits indicates arithmetic overflow on ma1 register and ma0 register respectively. one of these bits is set if an arithmetic overflow (48-bit overflow when 24-bit operation mode or 40-bit overflow when 16-bit operation) occurs after an arithmetic operation, and cleared otherwise. it represents that the result of an operation cannot be represented in 48 bits (in 24-bit mode) or 40 bits (in 16-bit mode). i.e. these bits are set when 5-bit value of ma[51:47] register is not all the same in 24-bit mode or 9-bit value of ma[47:39] register is not all the same in 16-bit mode. these bits are modified by writing the msr1 register and one of these bits is written when "er/es vm" instruction or all arithmetic instruction according to the current bank of ma register (bkma bit).
mac2424 S3FB42F 25- 18 ram pointer unit the ram pointer unit (rpu) performs all address storage and effective address calculations necessary to address data operands in data memories. in addition, it supports latching of the modified register in maximum/minimum operations and bit reverse address generation. this unit operates in parallel with other resources to minimize address generation overhead. the rpu performs two types of arithmetics : linear or modulo. the rpu contains four 16-bit indirect address pointer registers (rp0 ~ rp3, also referred to rpi) for indirect addressing, two 16-bit direct address pointer registers (rpd0 ~ rpd1, also referred to rpdi) for short direct form addressing, four 16-bit indirect index registers (sd0 ~ sd3, also referred to sdi) and its extensions (sd0e and sd3e), and two 16-bit modulo configuration registers (mc0 and mc1, also referred to mci) for modulo control. the mc0 register has effect on rp0 and rp1 pointer register, and the mc1 register has effect on rp2 and rp3 register. all indirect pointer registers ( rpi) and direct pointer registers ( rpdi) can be used for both xa and ya for instructions which use only one address register. in this case the x memory and y memory can be viewed as a single continuous data memory space. the bit 13 to bit 0 of rpi register and rpdi register defines address for x or y memory, and the bit 14 determines whether the address is for x memory or y memory. the bit 15 of rpi indicates whether the selected pointer is updated with modulo arithmetic. the rpu can access two data operand simultaneously over xa and ya buses. in dual access case, rp0 is automatically selected as a x memory pointer and rp3 is selected as a y memory pointer regardless of bit 14 of rp0 and rp3. all registers in the rpu may be read or written to by the xb as 16-bit data. the detailed block diagram of the ram pointer unit is shown in figure 25-8. address modification the rpu can generate up to two 14-bit addresses every instruction cycle which can be post-modified by two modifiers: linear and modulo modifier. the address modifiers allow the creation of data structures in the data memory for circular buffers, delay lines, fifos, etc. address modification is performed using 15-bit two's complement linear arithmetics. linear (step) modifier during one instruction cycle, one or two of the pointer register, rpi, can be post incremented/ decremented by a 2's complement 4-bit step (from ?8 to +7). if xsd bit of msr0 register is set, these 4-bit step is extended to 8-bit (from ? 128 to +127) by concatenating index register with extended index register (sd0e, sd3e) when selected pointer is rp0 or rp3. the selection of linear modifier type (one out of four) is included in the relevant instructions. the four step values are stores in each index register sdi. if the instruction requires a data memory read operation, s0 (bit 3 to bit 0) or s1 (bit 7 to bit 4) field of sdi register is selected as a index value. if the instruction requires a data memory write operation, d0 (bit 11 to bit 8) or d1(bit 15 to bit 12) field of sdi register is selected as an index value.
S3FB42F mac2424 25- 19 rp0 rp1 xb[23:0] rp2 rp3 sd1 sd0/sd0e sd2 sd3/sd3e mc0 mc1 rpd0 rpd1 xa[13:0] ya[13:0] x modulo logic y modulo logic bit-reverse logic figure 25-8. ram pointer unit block diagram modulo modifier the two modulo arithmetic units (x, y modulo logic) can update one or two address registers within one instruction cycle. they are capable of performing modulo calculations of up to 2 10 (=1024). each register can be set independently to be affected or unaffected by the modulo calculation using the me bits in the each pointer register. modulo setting values are stored in 13 least significant bits of modulo configuration registers mc0 and mc1 respectively. the bits 12 to bit 10 of mc0 and mc1 register determines maximum modulo size from 8 to 1024 and the bits 9 to bit 0 of modulo control register defines upper boundary of modulo calculation in the current modulo size. the lower boundary of modulo calculation is automatically defined by modulo size itself. (refer to figure 25-10)
mac2424 S3FB42F 25- 20 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mei ptri modulo enable rpi 0 = rpi modulo mode disable 1 = rpi modulo mode enable address pointer rpi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ptri reserved (readable/writable) address pointer rpdi rpi rpdi 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d1 s0 destination index 1 sdi d0 s1 destination index 0 source index 1 source index 0 figure 25-9. pointer register and index register configuration for proper modulo calculation, the following constraints must be satisfied. (m = modulo size, s = step size) 1. only the p lsbs of rpi can be modified during modulo operation, where p is the minimal integer that satisfies 2 p 3 m. rpi should be initiated with a number whose p lsbs are less than m. 2. m 3 s the modulo modifier operation, which is a post-modification of the rpi register, is defined as follows if (( rpi == upper boundary in k lsbs) and (q > 0)) then rpi k lsb ? 0 else if (( rpi == lower boundary in k lsbs) and (q < 0)) then rpi k lsb ? upper boundary in k lsbs else rpi k lsb ? rpi + q (k lsbs) where k is defined by mci[12:10]
S3FB42F mac2424 25- 21 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 modulo size upper boundary reserved (readable/writable) rp0/rp1 modulo size 000 = 2 10 , modulo area: dddd0000000000 - dddd,mc0[9:0] 001 = 2 3 , modulo area: dddddddddddd000 - ddddddddddd,mc[2:0] 010 = 2 4 , modulo area: ddddddddddd0000 - dddddddddd,mc[3:0] 011 = 2 5 , modulo area: dddddddddd00000 - ddddddddd,mc[4:0] 100 = 2 6 , modulo area: ddddddddd000000 - dddddddd,mc[5:0] 101 = 2 7 , modulo area: dddddddd0000000 - ddddddd,mc[6:0] 110 = 2 8 , modulo area: ddddddd00000000 - dddddd,mc[7:0] 111 = 2 9 , modulo area: dddddd000000000 - ddddd,mc[8:0] mc0 modulo upper boundary 15 14 13 12 11 10 15 15 9 8 7 6 5 4 3 2 1 0 bit-reverse order modulo size upper boundary bit-reverse order 000 = reverse rpi[4:0] 001 = reverse rpi[5:0] 010 = reverse rpi[6:0] 011 = reverse rpi[7:0] 100 = reverse rpi[8:0] 101 = reverse rpi[9:0] 110 = reverse rpi[10:0] 111 = reverse rpi[11:0] rp2/rp3 modulo size 000 = 2 10 , modulo area: dddd0000000000 - dddd,mc0[9:0] 001 = 2 3 , modulo area: dddddddddddd000 - ddddddddddd,mc[2:0] 010 = 2 4 , modulo area: ddddddddddd0000 - dddddddddd,mc[3:0] 011 = 2 5 , modulo area: dddddddddd00000 - ddddddddd,mc[4:0] 100 = 2 6 , modulo area: ddddddddd000000 - dddddddd,mc[5:0] 101 = 2 7 , modulo area: dddddddd0000000 - ddddddd,mc[6:0] 110 = 2 8 , modulo area: ddddddd00000000 - dddddd,mc[7:0] 111 = 2 9 , modulo area: dddddd000000000 - ddddd,mc[8:0] mc1 modulo upper boundary * "d" means don't care figure 25-10. modulo control register configuration
mac2424 S3FB42F 25- 22 the modulo calculation examples are as follows. 1. full modulo with step = 1 (selected by instruction and index register val ue) mc0 = 000_001_0000000111 (upper boundary = 7, lower boundary = 0, modulo size = 8) rpi = 0010h 0010h ? 0011h ? 0012h ? 0013h ? 0014h ? 0015h ? 0016h ? 0017h ? 0010h ? 0011h 2. full modulo with step = 3 (selected by instruction a nd index register value) mc0 = 000_001_0000000111 (upper boundary = 7, lower boundary = 0, modulo size = 8) rpi = 0320h 0320h ? 0323h ? 0326h ? 0321h ? 0324h ? 0327h ? 0322h ? 0325h ? 0320h ? 0323h 3. part modulo with step = -2 (sel ected by instruction and index register value) mc0 = 000_001_0000000101(upper boundary = 5, lower boundary = 0, modulo size = 8) rpi = 2014h 2014h ? 2012h ? 2010h ? 2014h ? 2102h the total number of circular buffer (modulo addressing active area) is defined by 32k/modulo size. i.e. if current modulo size is 32, the total number of circular buffer is 1024. bit reverse capabilities the bit-reverse addressing is useful for radix-2 fft(fast fourier transform) calculations. the mac2424 dsp coprocessor does not support the bit-reverse addressing itself. but it supports the bit field reverse capabilities in the form of instruction. the "erpr" instruction selects a source address pointer rpi and performs bit reverse operation according to the bit field specified in bit 15 to bit 13 of mc1 register. the result bit pattern is written to the rp3 register pointer field. (bit 14 to bit 0) in this way, rp3 has a bit-reversed address value of source pointer value. note that the data buffer size is always a power of 2 up to 2 12 . index extension when an instruction with indirect addressing is executed, the current value of selected address pointer register rpi provides address on xa and ya buses. meanwhile, the current address is incremented by the value contained into the selected index value contained into the selected bit field of selected index register, and stored back into rpi at the end of instruction execution. the 4-bit index values can be considered as a signed number, so the maximum increment value is 7(0111b) and the maximum decrement value is ?8(1000b). if the 4-bit index value is insufficient for use, the index values can be extended to 8-bit values when rp0 or rp3 register is selected as an address pointer register. in this case, all index values are extended to 8-bit by concatenating with sd0e or sd3e register. the bit field of sd0e and sd3e is the same as other index register sdi. the index extension registers are enabled when the xsd bit of msr0 register is set. otherwise, those are disabled. if the extension index registers are enable, index values for indirect addressing becomes to 8-bit during addressing with rp0 and rp3 pointer register, and current index register becomes the extended index register instead of the regular index register: i.e. when a index register is read or written by a load instruction, sd0e register or sd3e register is selected as a source operand or a destination operand, instead of sd0 or sd3 register. for each of sd0/sd0e or sd3/sd3e, only one register is accessible at a time.
S3FB42F mac2424 25- 23 data memory spaces and organization the mac2424 dsp coprocessor has only data memory spaces. the program memory can only be accessed by calmrisc, host processor. the data memory space is shared with host processor. the calmrisc has 16-bit data memory address, so it can access up to 64 kbyte data memory space. the mac2424 access data memory with 24-bit width or 16-bit width. it can access upto 32 kword (word = 2-byte or 3-byte). the data space is divided into a lower 16 kword x data space and a higher 16 kword y data space. when two data memory access are needed in an instruction, one is accessed in x data space, and the other is accessed in y memory space. when one data memory access is needed, the access is occurred in x or y data memory space according to the address. xe (16 kbyte) xh/xl (16 * 2 kbyte) ye (16 kbyte) 7fffh 4000h 3fffh 0000h i/o region (128 byte) 0040h 003fh yh/yl (16 * 2 kbyte) figure 25-11. data memory space map
mac2424 S3FB42F 25- 24 each space is divided into 3 16 kbyte xe/xh/xl or ye/yh/yl region when 24-bit data is needed, or 2 16 kbyte xh/xl or yh/yl region when 16-bit data is needed, respectively. each space can contain ram or rom, and can be off-chip or on-chip. in the x data space, the lower 128 byte locations are reserved for memory-mapped i/o. the mac2424 coprocessor can not access the i/o region. only host processor can access. the configuration of this region depends on the specific chip configuration. when 24-bit width data memory is used, the total memory space becomes to 96 kbyte (16 kbyte * 6). because calmrisc can only access 64 kbyte memory space, the extended memory regions (xe and ye) are shadowed in the high address memory region (xh and yh). so, calmrisc can access xh/xl pair or xe/xl pair in a time. the selection of shadowed region can be accomplished with "sys # imm" instruction in calmrisc. (refer to each evaluation chip specification) arithmetic unit the arithmetic unit (aru) performs all arithmetic operations on data operands. it is a 24-bit, single cycle, non- pipelined arithmetic unit. the mac2424 is a coprocessor of calmrisc microcontroller. so, all the logical operation and other bit manipulation operations can be performed in calmrisc. thus, the mac2424 has not logical units and bit manipulation units at all. the aru receives one operand from ai(a or b) register, and another operand from either the msb part of ma register, the xb bus, or from ai. operations between the two ai register are possible. the source and destination ai register of an aru instruction is always the same. the xb bus input is used for transferring one of the mac2424 register content, an immediate operand, or the content of a data memory location, addressed in direct addressing mode or in indirect addressing mode as a source operand. the flags in the msr0 register are affected as a result of the aru output. in most of the instructions where the aru result is transferred to one of ai registers, the flags represent the ai register status. the detailed block diagram of the arithmetic unit is shown in figure 25-12. 24-bit adder xb[23:0] a b shifter shifter saturation msr0 msr2 ei generation figure 25-12. arithmetic unit block diagram
S3FB42F mac2424 25- 25 the aru can perform add, subtract, compare, several other arithmetic operations (such as increment, decrement, negate, and absolute), and some arithmetic shift operations. it uses two's complement arithmetic. a, b accumulators each ai (a or b) register is organized as a regular 24-bit register. the ai accumulators can serve as the source operand, as well as the destination operand of the aru instructions. the ai registers can be read or written though the xb bus. in the 16-bit mode operation, ai register is organized as a regular 16-bit register (bit 15 to bit 0) and 8-bit extension guard bits. (bit 23 to bit 16) when the result of a 24-bit adder output crosses bit 15, it sets vi(va or vb) bit of msr0 register (a/b register overflow flag). the extension guard bits offer protection against 16-bit overflows up to 255 overflows or underflows. if the sign is lost beyond the msb of the extension guard bits, the result is lost and the value can not be recovered. there is no overflow indication at 24-bit boundary in 16-bit operation mode. in 24-bit operation mode, when the result of a 24-bit adder output crosses bit 23, it sets vi. overflow protection in a/b accumulators the ai accumulator saturation is performed differently according to the current operation mode. in 24-bit operation mode, the selected accumulator value is saturated during arithmetic operation which causes overflow, if overflow protection bit (opa or opb bit in msr0 register) is enabled. the limited values are 7fffffh (positive overflow), or 800000h (negative overflow). during accumulator register read through xb bus, the saturation is not occurred. contrary, in 16-bit operation mode, saturation is not occurred during arithmetic operation. the saturation is only occurred during accumulator register read through xb bus, if overflow protection is enabled and overflow occurred (opa/opb bit of msr0 register is set, and va/vb bit of msr0 register is set). the saturated values are 007fffh (positive overflow) or ff8000h (negative overflow). ? saturation condition at 24-bit mode : arithmetic instruction & 24-bit overflow & opa/opb ? saturation condition at 16-bit mode : read a/b & va/vb & opa/opb a/b 0 23 a/b 0 23 a/b a/b guard region a/b 15 16 a/b mode24 mode16 figure 25-13. ai accumulator register configuration
mac2424 S3FB42F 25- 26 arithmetic unit maximum-minimum possibilities two cycle maximum/minimum operations are available with pointer latching and modification. one of the ai accumulator register holds the maximum value in a "emax" instruction, or the minimum value in a "emin" instruction. in the first cycle, the one accumulator register is compared with the operand by "ecp" instruction, and this instruction updates n flag value. in the second cycle, this value is copied to the above defined accumulator register. the address pointer register which generates address (except rp3) can be post-modified according to the specified mode in the instruction. when the new maximum or minimum number is found, the previous pointer value is latched into the lsb 15-bit field of rp3 pointer register. for more details, refer to "emax" and "emin" instructions on the instruction set. the examples which searches block elements are as follows loop_start: ecp a, @rp0+s0 // compare two values (s0 must be 0) emax(emin) a, @rp0+s1 // conditional load (s1 must be search index) jp loop_start conditional instruction execution some instructions can be performed according to the t flag value of msr0 register. these instructions may operate when the t flag is set, and do nothing if the t flag is cleared. the instructions which have suffix "t" are this type of instructions. ("emod1" type instruction. the conditional instruction execution capabilities can reduce the use of branch instructions which require several cycles. shifting operations a few options of shifting are available in the aru and all of them are performed in a single cycle. all shift operations performed in the aru are arithmetic shift operations : i.e. right shift filling the msbs with sign values and left shift filling with lsbs with zeros. the source and destination operands are one of 24-bit ai accumulator registers. the shift instructions performed in the aru are all conditional instructions. the shift amount is limited to 1 and 8, right or left respectively. the shift with carry is also supported. multi-precision support various instructions which help multi-precision arithmetic operation, are provided in the mac2424. the instructions with suffix "c" indicates that the operation is performed on source operand and current carry flag value. by using this instructions, double precision or more precision arithmetics can be accomplished. the following shows one example of multi-precision arithmetic. // 3-cycle double precision addition (a:b + 2 memory operand) eadd b, @rp0+s0 // lower part addition eincc a // carry propagation eadd a, @rp0+s0 // higher part addition
S3FB42F mac2424 25- 27 external condition generation unit the mac2424 can generates and send the status information or control information after instruction execution to the host processor calmrisc through ei[2:0] pin (refer to pin diagram). the calmrisc can change the program sequence according to this information by use of a conditional branch instruction that uses ei pin values as a branch condition. the ei generation block in the aru selects one of status register value or combination of status register values according to the seci (i=0,1,2) field in the msr2 register. (refer to msr2 register configuration) status register 0 (msr0) msr0 register of three mac2424 status registers (msr0, msr1, msr2) is used to hold the flags, control bits, status bits for the aru and beu(barrel shifter and exponent unit). the contents of each field definitions are described as follows. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 opa vs vb n va z c t reserved (read as 0) operation mode select 0 = 24-bit mode (reset value) 1 = 16-bit mode b accumulator overflow protection (0 when reset) extended index enable 0 = no extension (reset value) 1 = sd0/sd3 extension barrel shifter/exponent overflow flag negative flag zero flag opb xsd m16 a accumulator overflow protection (0 when reset) reserved (read as 0) b accumulator overflow flag a accumulator overflow flag carry flag test flag figure 25-14. msr0 register configuration
mac2424 S3FB42F 25- 28 m16 ? bit 11 this bit defines current operation mode of the mac2424 dsp coprocessor. if this bit is set, it indicates the current operation mode is 16-bit mode, and data registers and flags are configured to 16-bit mode. if this bit is clear (reset state), the mac2424 operates on normal 24-bit mode. the m16bit is only affected when msr0 register write operation or "er/es m16" instruction is used. xsd ? bit 10 this bit defines current bank of index register for index register read or write operation, and the length of index value for address modification. when this bit is set, the current bank of index register is sd0e and sd3e instead of sd0 and sd3, respectively. when clear, the current index registers are sd0 and sd3. (reset state) during indirect addressing mode, pointer register rpi is post-modified by index register value. if xsd is set, the width of index value becomes to 8-bit by concatenating extension index register and normal index register. if clear, the normal 4-bit index value is applied. the xsd bit can be modified by writing to msr0 register or "er/es xsd" instruction. the xsd bit is cleared by a processor reset. opb/opa ? bit 9/bit 8 the opb/opa bit indicates that saturation arithmetic in the aru is provided or not when overflow is occurred during data move or arithmetic operation. the overflow protection can be applied to a and b register respectively. if this bit is set, the saturation logic will substitute a limited value having maximum magnitude and the same sign as the source ai register during overflow. if clear, no saturation is performed, and overflow is not protected by the mac2424. the opa/opb bit can be modified by writing to msr0 register or "er/es opa/opb" instruction. the opa/opb bit is cleared by a processor reset. vs ? bit 6 the vs bit is a overflow flag for beu(barrel shifter and exponent unit). this bit is set if arithmetic overflow is occurred during shift operation or exponent evaluation on beu registers. when the instructions which performs beu operation writes this bit as a overflow flag instead of va or vb bit. the vs bit indicates that the result of a shift operation can not be represented in 16-bit sr register, or the source value of an exponent operation is all zero or all one. the vs bit can be modified by writing to msr0 register instruction.
S3FB42F mac2424 25- 29 vb/va ? bit 5 / bit 4 the va or vb bit is a overflow flag for aru ai accumulators. this bit is set if arithmetic overflow is occurred during arithmetic operation on ai accumulator registers in aru. the va and vb bit indicates that the result of an arithmetic operation can not be represented in 24-bit a and b register in 24-bit mode operation and the result crosses 16-bit boundary in a and b register at 16-bit mode. only one of two bits is updated by arithmetic operation according to the destination operand. the va and vb bit can be modified simultaneously by writing to msr0 register instruction. n ? bit 3 the n bit is a sign flag for aru or beu operation result. this bit is set if aru or beu operation result value is a negative value, and cleared otherwise. the n flag is the same as the msb of the output if current operation does not generate overflow. if overflow is occurred during instruction execution, the value of n flag is the negated value of the msb of the output. the n bit can be modified by instructions writing to msr0 register. z ? bit 2 the z bit is a zero flag for aru or beu operation result. this bit is set when aru or beu operation result value is zero, and cleared otherwise. the z bit can be modified by instructions writing to msr0 register, explicitly. c ? bit 1 the c bit is a carry flag for aru or beu operation result. this bit is set when aru or beu operation generates carry, and cleared otherwise. the c bit is not affected by "eld" instruction because this instruction does not generate carry all the times. the c bit can be modified by instructions writing to msr0 register, explicitly. t ? bit 0 the t bit is a test flag that evaluates various conditions when "etst" instruction is executed. this flag value can be used as a condition during executing a conditional instruction (instructions that have a suffix "t"). the conditional instructions can only be executed when the t bit is set. otherwise, performs no operation. the t bit can be modified by instructions writing to msr0 register, explicitly.
mac2424 S3FB42F 25- 30 status register 2 (msr2) msr2 register of three mac2424 status registers (msr0, msr1, msr2) is used to select ei port of the mac2424 from various flags and status information in msr0 and msr1 register. the msr2 register is used at external condition generation unit in the aru. the contents of each field definitions are described as follows. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sec2 sec1 sec0 reserved (read as 0) ec2 selection 0000 = z 0001 = ~z 0010 = n 0011 = ~n 0100 = c 0101 = ~c 0110 = va 0111 = vb 1000 = gt 1001 = le 1010 = vm0 1011 = vm1 1100 = vs 1101 = reverved 1110 = mv 1111 = t 1101 = reverved ec1 selection 0000 = z 0001 = ~z 0010 = n 0011 = ~n 0100 = c 0101 = ~c 0110 = va 0111 = vb 1000 = gt 1001 = le 1010 = vm0 1011 = vm1 1100 = vs 1110 = mv 1111 = t ec0 selection 0000 = z 0001 = ~z 0010 = n 0011 = ~n 0100 = c 0101 = ~c 0110 = va 0111 = vb 1000 = gt 1001 = le 1010 = vm0 1011 = vm1 1100 = vs 1101 = reverved 1110 = mv 1111 = t figure 25-15. msr2 register configuration
S3FB42F mac2424 25- 31 barrel shifter and exponent unit the barrel shifter and exponent unit (beu) performs several shifting operations and exponent evaluations. it contains a 16-bit, single cycle, non-pipelined barrel shifter and 24-bit exponent evaluation unit. the detailed block diagram of the barrel shifter and exponent unit is shown in figure 25-16. 24-bit exponent sa xb[23:0] from a/b 16-bit barrel shifter sr sg si figure 25-16. barrel shifter and exponent unit block diagram
mac2424 S3FB42F 25- 32 barrel shifter the barrel shifter performs standard arithmetic and logical shift, and several special shift operations. it is a 32-bit left and right, single-cycle, non-pipelined barrel shifter. the barrel shifter receives the source operand from either one of the 24-bit two ai accumulator registers or 16-bit si register. when selected source operand is ai register, 16 lsbs of 24-bit register value are only valid. the upper 8-bit values are ignored. it also receives the shift amount value from either one of the 24-bit two ai accumulator registers or 6-bit sa register. because the maximum amount of shift is from ?32 (right shift 32-bit) to +31 (left shift 31 bit), 6-bit shift amount is sufficient. when ai register is used as the shift amount register, 6 lsbs of 24-bit register value are only valid. the amount of shifts is only determined by a value in the one of these three register and can not be determined by a constant embedded in the instruction opcode (immediate shift amount is not supported). the barrel shifter takes 16-bit input operand and 6-bit amount value, and generates 32-bit shifted output values. the destination of shifted value is two 16-bit shift output register sg and sr register. the sg register holds the value of shifted out, and the sr register holds the shifted 16-bit values. the flags are affected as a result of the barrel shifter output, as well as a result of the aru output. when the result is transferred into the barrel shifter output register, the flags represent the shifter output register status. the c, n, and z flag in msr0 register is used common to the aru and the beu, but the v flag is different. the aru uses the va and vb flags as overflow flag, and the beu uses the vs flag as overflow flag. shifting operations several shift operations are available using the barrel shifter, all of them are performed in a single cycle. the detailed operations of each shift instruction are depicted in figure 2.15. if 6-bit shift amount value is positive, shift left operation is performed and if negative, shift right operation is performed. after all barrel shifter operation is performed, the carry flag has the bit value which is shifted out finally. "esft" instruction performs a standard logical shift operation. the shifted bit pattern is stored into the 16-bit sr register (shifter result register), and the shifted out bit pattern is stored into the 16-bit sg register (shifter guard register). when shift left operation, msbs of sg register and lsbs of sr register is filled with zeros. when shift right operation, lsbs of sg register and msbs of sr register is filled with zeros. "esfta" instruction performs a standard arithmetic shift operation. the operation is all the same as a logical shift except that the msbs of sg register or msbs of sr register is sign-extended instead of being filled with zeros. "esftd" instruction is provided for double precision shift operation. with this instruction, one can shift 32-bit number stored in two registers. unlike standard logical and arithmetic shift, this instruction only updates the sg register with the values that is ored previous sg register value and shifted out result from barrel shifter. the following codes are examples of double precision shift operation. // double precision left ({sg,sr} ? {b,a} <>sa esft b,sa // upper part shift esftd a,sa // lower part shift
S3FB42F mac2424 25- 33 "esftl" instruction is used for bit-stream manipulation. it links the previously shifted data with the current data. the operation of this instruction is the same as logical shift instruction except that the shifted out result is ored with previous sg register values. this oring process makes it possible to concatenate the previous data and the current data. this instruction is valid only when the magnitude of shift amount is greater than 16. the linking process example is as follows. // left link ({sg,sr} ? b<>a and link si esft b,a // previous data shift eadd a,#16 // preprocessing for linking esftl si,a // current data shift
mac2424 S3FB42F 25- 34 input 0's 0's sr sg 0's 0's shifter input shifter output esft (logical shift) esfta (arithmetic shift) esftd (double-precision shift) esftl (linked shift) 0 0 0 15 input 0 15 15 0 15 31 sr sg 0 15 0 15 registers 0 31 input 0's sign's sr sg 0's sign's shifter input shifter output 0 0 0 15 input 0 15 15 0 15 31 sr sg 0 15 0 15 registers 0 31 input 0's 0's 0's 0's shifter input shifter output 0 0 15 input 0 15 31 0 31 sg 0 15 sg 0 15 input 0's 0's 0's 0's shifter input shifter output 0 0 15 input 0 15 31 0 31 sg 0 15 sr 0 15 sg 0 15 sr 0 15 registers registers left shift operations right shift operations figure 25-17. various barrel shifter instruction operation
S3FB42F mac2424 25- 35 bit-field operation the barrel shifter supports a bit-field masking operation. this operation can be used for data bit-stream manipulation only. various bit-field operations such as bit set, bit reset, bit change, and bit test operation is supported in calmrisc, host processor. so the mac2424 need not powerful bit operation capabilities. "enmsk" instruction is provided for bit-pattern masking. this instrucion masks msbs of sg register with selected mask pattern. the mask pattern is generated according to the 4-bit immediate operand embedded in the instruction. exponent block the exponent block performs exponent evaluation of one of the two 24-bit accumulator registers ai. the result of this operation is a signed 6-bit value, and transferred into the shift amount register (sa). the source operand is unaffected by this calculation. the algorithm for determining the exponent result for a 24-bit number is as follows. let n be the number of the sign bits (i.e. the number of msbs equal to bit 23) found in the evaluated number. the exponent result is n-1. this means that the exponent is evaluated with respect to bit 24. therefore, the exponent result is always greater than or equal to zero. (refer to following table as examples) a non-zero result represents an un-normalized number. when evaluating the exponent value of one of the ai accumulator, the result is the amount of left shifts that should be executed in order to normalize the source operand. an exponent result equal to zero represents a normalized number. table 25-2. exponent evaluation and normalization example evaluated number n exponent result normalized number 00001101?. 4 3 (shift left by 3) 01101?. 11101010?. 3 2 (shift left by 2) 101010? 00000011?. 6 5 (shift left by 5) 011?..... 11111011?. 5 4 (shift left by 4) 1011??.
mac2424 S3FB42F 25- 36 normalization full normalization can be achieved in 2 cycles, using "eexp" instruction, followed by "esft" instruction. the "eexp" instruction evaluates the exponent value of one of the ai register. the second instruction "esft" is shifting the evaluated number, according to the exponent result stored at sa register. // normalization eexp a esft a,sa the block normalization is also possible using the exponent unit and "emin" instruction. the "emin" instruction can select the minimum exponent value from all evaluated exponent result. double precision supports the mac2424 coprocessor has an instruction which can evaluate exponent values of double precision 48-bit data operand. double precision exponent evaluation can be achieved in 2 cycles, using a standard exponent valuation instruction ("eexp"), followed by "eexpc" instruction. the "eexp" instruction sets the vs flag when the source operand has the all one value or the all zero value and sets the c flag with the lsb bit value of the source operand. the c flag transfer the sign information of higher 24-bit data. after "eexp" instruction is executed, the "eexpc" instruction evaluates the exponent value of lower 24-bit data and carry if the vs flag is set. and then the calculated exponent value is added with previous sa register value. in this way, full double precision exponent calculation can be done. // double precision exponent evaluation about {a,b} eexp a eexpc b
S3FB42F mac2424 25- 37 instruction set map and summary addressing modes various addressing modes, including indirect linear and modulo addressing, short and long direct addressing, and immediate, are implemented in the mac2424 coprocessor. (1) indirect addressing mode indirect addressing for read operation @rp0+s0, @rp0+s1, @rp1+s0, @rp1+s1, @rp2+s0, @rp2+s1, @rp3+s0, @rp3+s1 one of the rpu pointer registers (rp0, rp1, rp2, rp3) points to one of the 32k data words. the data location content, pointed to by the pointer register, is the source operand. the rpi pointer register is modified with one of two 4-bit or 8-bit source index values (s0 or s1 field) which reside in the index register after the instruction is executed. the source index values are sign extended to 15-bit and added to 15-bit pointer values in rpi register. the rp1 and rp2 register can only use 4-bit source index value. the rp0 and rp3 register can use extended 8-bit source index value if xsd bit of msr0 register is set. eadd a, @rp0+s1 (when xsd = 1) before execution after execution 008010h a rp0 (no modulo) 0010h data loacation 10h 000011h sd0 f3 3 3h sd0e 01 2 2h 008021h 0033h 000011h f3 3 3h 01 22h figure 25-18. indirect addressing example i (read operation)
mac2424 S3FB42F 25- 38 indirect addressing for write operation @rp0+d0, @rp0+d1, @rp1+d0, @rp1+d1, @rp2+d0, @rp2+d1, @rp3+d0, @rp3+d1 one of the rpu pointer registers (rp0, rp1, rp2, rp3) points to one of the 32k data words. the data location content, pointed to by the pointer register, is the destination operand. the rpi pointer register is modified with one of two 4-bit or 8-bit destination index values (d0 or d1 field) which reside in the index register after the instruction is executed. the destination index values are sign extended to 15-bit and added to 15-bit pointer value in rpi register. the rp1 and rp2 register can only use 4-bit source index value. the rp0 and rp3 register can use extended 8-bit source index value if xsd bit of msr0 register is set. eld @rp1+d0, b before execution after execution 008010h b rp1 (no modulo) 0020h data loacation 20h 000011h sd1 1 8 19h 008010h 0018h 008010h 1819h figure 25-19. indirect addressing example ii (write operation)
S3FB42F mac2424 25- 39 (2) direct addressing mode short direct addressing form i : rpd1.adr:4 form ii: rpdi.adr:5 the data location, one of the 32k data word, is one of the source operand or destination operand. the 15-bit data location is composed of the page number in the msb 10 or 11 bits of rpd0 or rpd1 register (except bit 15) and the direct address field (the offset in the page) in the instruction code. the short direct addressing form i only uses rpd1 register as a page value, and the form ii uses rpd0 or rpd1 register specified in instruction code. the lsb 5 or 6 bits of rpd0 or rpd1 register is not used at all. and the bit 15 of rpd0 or rpd1 register is not used, either. eadd a, rpd0.3h before execution after execution 008010h a rpd0 0028h data loacation 23h 000011h 008021h 0028h 000011h address generation 0000000001 00011 14 0 4 5 rpd0[14:5] adr:5 figure 25-20. short direct addressing example
mac2424 S3FB42F 25- 40 long direct addressing adr:15 the data location, one of the 32k data word, is one of the source operand or destination operand. the 15-bit data location is specified as the second word of the instruction. there is no use of the page bits in the rpdi register in this mode. eld 1234h, b before execution after execution 008010h b data loacation 1234h 000011h 008010h 008010h address generation 001001000110100 14 0 adr:15 figure 25-21. long direct addressing example
S3FB42F mac2424 25- 41 (3) immediate mode short immediate form i : #imm:4 form ii: #imm:5 the form i is used for 4-bit register field load in " esdi" instruction and " eseci" instruction, or masking pattern generation in "enmsk" instruction. the form ii is used for one of the source operands. the 5-bit value is right-justified and sign-extended to the 24-bit operand. long immediate form i : #imm:15 form ii: #imm:16 the form i is used only when ?erpn? instruction is executed. the 15-bit immeidate value is used as an long index values for address pointer register modification. the form ii is used for one of the source operands. the 16-bit value is right-justified and sign-extended to the 24-bit operand when the destination operand is 24-bit. when the destination register has 16-bit width, the immediate value is no changed. the long immediate requires the second instruction code.
mac2424 S3FB42F 25- 42 instruction coding (1) abbreviation definition and encoding rps mnemonic encoding description rp0+s0 000 rp0 post-modified by sd0 s0 field rp0+s1 001 rp0 post-modified by sd0 s1 field rp1+s0 010 rp1 post-modified by sd1 s0 field rp1+s1 011 rp1 post-modified by sd1 s1 field rp2+s0 100 rp2 post-modified by sd2 s0 field rp2+s1 101 rp2 post-modified by sd2 s1 field rp3+s0 110 rp3 post-modified by sd3 s0 field rp3+s1 111 rp3 post-modified by sd3 s1 field rpd mnemonic encoding description rp0+d0 000 rp0 post-modified by sd0 d0 field rp0+d1 001 rp0 post-modified by sd0 d1 field rp1+d0 010 rp1 post-modified by sd1 d0 field rp1+d1 011 rp1 post-modified by sd1 d1 field rp2+d0 100 rp2 post-modified by sd2 d0 field rp2+d1 101 rp2 post-modified by sd2 d1 field rp3+d0 110 rp3 post-modified by sd3 d0 field rp3+d1 111 rp3 post-modified by sd3 d1 field rp0s mnemonic encoding description rp0+s0 0 rp0 post-modified by sd0 s0 field rp0+s1 1 rp0 post-modified by sd0 s1 field rp3s mnemonic encoding description rp3+s0 0 rp3 post-modified by sd3 s0 field rp3+s1 1 rp3 post-modified by sd3 s1 field
S3FB42F mac2424 25- 43 abbreviation definition and encoding (continued) mg1/mg1d/mg1s mnemonic encoding description y0 000 y0[23:0] register y1 001 y1[23:0] register x0 010 x0[23:0] register x1 011 x1[23:0] register p 100 p[47:0] / p[47:24] register pl 101 p[23:0] register ma 110 current bank ma[51:0] / ma[47:24] mal 111 current bank ma[23:0] mg2/mg2d/mg2s mnemonic encoding description rp0 000 rp0[15:0] register rp1 001 rp1[15:0] register rp2 010 rp2[15:0] register rp3 011 rp3[15:0] register rpd0 100 rpd0[15:0] register rpd1 101 rpd1[15:0] register mc0 110 mc0[15:0] register mc1 111 mc1[15:0] register rpi mnemonic encoding description rp0 00 rp0[15:0] register rp1 01 rp1[15:0] register rp2 10 rp2[15:0] register rp3 11 rp3[15:0] register sdi/ sdis/ sdid mnemonic encoding description sd0 00 current bank of sd0[15:0] register (sd0 or sd0e) sd1 01 sd1[15:0] register sd2 10 sd2[15:0] register sd3 11 current bank of sd3[15:0] register (sd3 or sd3e)
mac2424 S3FB42F 25- 44 abbreviation definition and encoding (continued) mg mnemonic encoding description y0 00000 y0[23:0] register y1 00001 y1[23:0] register x0 00010 x0[23:0] register x1 00011 x1[23:0] register p 00100 p[47:0] / p[47:24] register pl 00101 p[23:0] register ma 00110 current bank ma[51:0] / ma[47:24] register mal 00111 current bank ma[23:0] register rp0 01000 rp0[15:0] register rp1 01001 rp1[15:0] register rp2 01010 rp2[15:0] register rp3 01011 rp3[15:0] register rpd0 01100 rpd0[15:0] register rpd1 01101 rpd1[15:0] register mc0 01110 mc0[15:0] register mc1 01111 mc1[15:0] register sd0 01000 current bank of sd0[15:0] register (sd0 or sd0e) sd1 01001 sd1[15:0] register sd2 01010 sd2[15:0] register sd3 01011 current bank of sd3[15:0] register (sd3 or sd3e) sa 01100 sa[5:0] register si 01101 si[15:0] register sg 01110 sg[15:0] register sr 01111 sr[15:0] register msr0 11000 msr0[15:0] register msr1 11001 msr1[15:0] register msr2 11010 msr2[15:0] register ? 11011 reserved masr 11100 arithmetic right one bit shifted current ma[47:24] register masl 11101 arithmetic left one bit shifted current ma[47:24] register marn 11110 rounded current ma[47:24] register prn 11111 rounded p[47:24] register * grayed field : read only register
S3FB42F mac2424 25- 45 abbreviation definition and encoding (continued) mgx mnemonic encoding description y0 00 y0[23:0] register y1 01 y1[23:0] register x0 10 x0[23:0] register x1 11 x1[23:0] register mga mnemonic encoding description p 00 p[47:0] / p[47:24] register a 01 a[23:0] register ma 10 current bank ma[51:0] / ma[47:24] register b 11 b[23:0] register srg/ srgd/ srgs mnemonic encoding description sa 00 sa[5:0] register si 01 si[15:0] register sg 10 sg[15:0] register sr 11 sr[15:0] register asr mnemonic encoding description a 00 a[15:0] register b 01 b[15:0] register si 10 si[15:0] register sr 11 sr[15:0] register asa mnemonic encoding description a 00 a[5:0] register b 01 b[5:0] register sa 10 sa[5:0] register ? 11 reserved
mac2424 S3FB42F 25- 46 abbreviation definition and encoding (continued) ai mnemonic encoding description a 0 a[23:0] register b 1 b[23:0] register mci mnemonic encoding description mc0 0 mc0[15:0] register mc1 1 mc1[15:0] register bs mnemonic encoding description opa 0000 msr0[5] opb 0001 msr0[6] ? 0010 reserved ? 0011 reserved me0 0100 rp0[15] me1 0101 rp1[15] me2 0110 rp2[15] me3 0111 rp3[15] opm 1000 msr1[3] psh1 1001 msr1[4] usm 1010 msr1[5] bkma 1011 msr1[6] mv 1100 msr1[2] xsd 1101 msr1[9] m16 1110 msr1[10] vm 1111 msr1[1] or msr1[0] by current ma register bank ns mnemonic encoding description s0 00 sdi[3:0] register s1 01 sdi[7:4] register d0 10 sdi[11:8] register d1 11 sdi[15:12] register
S3FB42F mac2424 25- 47
mac2424 S3FB42F 25- 48 abbreviation definition and encoding (continued) ereg mnemonic encoding description ahl/ah 0000 a[23:16] register ahl/ah 0001 a[23:16] register alh/al 0010 a[15:8] register or a[15:0] register all/al 0011 a[7:0] register or a[15:0] register bhl/bh 0100 b[23:16] register bhl/bh 0101 b[23:16] register blh/bl 0110 b[15:8] register or b[15:0] register bll/bl 0111 b[7:0] register or b[15:0] register sa 1000 sa[5:0] register sa 1001 sa[5:0] register sih/si 1010 si[15:8] register or si[15:0] register sil/si 1011 si[7:0] register or si[15:0] register sgh/sg 1100 sg[15:8] register or sg[15:0] register sgl/sg 1101 sg[7:0] register or sg[15:0] register srh/sr 1110 sr[15:8] register or sr[15:0] register srl/sr 1111 sr[7:0] register or sr[15:0] register 1 st : calmrisc8 as a host / 2 nd : calmrisc16 as a host
S3FB42F mac2424 25- 49 abbreviation definition and encoding (continued) cct mnemonic encoding description z 0000 z = 1 nz 0001 z = 0 neg 0010 n = 1 pos 0011 n = 0 c 0100 c = 1 nc 0101 c = 0 va 0110 va = 1 vb 0111 vb = 1 gt 1000 n = 0 and z = 0 le 1001 n = 1 or z = 1 vm0 1010 vm0 = 1 vm1 1011 vm1 = 1 vs 1100 vs = 1 ? 1101 reserved mv 1110 mv = 1 ? 1111 reserved
mac2424 S3FB42F 25- 50 abbreviation definition and encoding (continued) emod0 mnemonic encoding description eld 00 load eadd 01 add esub 10 subtract ecp 11 compare emod1 mnemonic encoding description esra(t) 0000 arithmetic shift right 1-bit esla(t) 0001 arithmetic shift left 1-bit esra8(t) 0010 arithmetic shift right 8-bit esla8(t) 0011 arithmetic shift left 8-bit esrc(t) 0100 arithmetic shift right 1-bit with carry eslc(t) 0101 arithmetic shift left 1-bit with carry eincc(t) 0110 increment with carry edecc(t) 0111 decrement with carry eneg(t) 1000 negate eabs(t) 1001 absolute efs16(t) 1010 force to sign bit 23 ~ bit 8 by bit 7 efz16(t) 1011 force to zero bit 23 ~ bit 8 efs8(t) 1100 force to sign bit 23 ~ bit 16 by bit 15 efz8(t) 1101 force to zero bit 23 ~ bit 16 eexp(t) 1110 exponent detection eexpc(t) 1111 exponent detection with carry note: ?t? suffix means that instruction is executed when t flag is set. xiyi mnemonic encoding description x0y0 00 x0[23:0] * y0[23:0] x0y1 01 x0[23:0] * y1[23:0] x1y0 10 x1[23:0] * y0[23:0] x1y1 11 x1[23:0] * y1[23:0]
S3FB42F mac2424 25- 51 abbreviation definition and encoding (continued) emod2 mnemonic encoding description esra 0000 arithmetic shift right 1-bit esla 0001 arithmetic shift left 1-bit ernd 0010 rounding ecr 0011 clear esat 0100 saturate eresr 0101 restore remainder ? 0110 reserved ? 0111 reserved eld ma0,ma1 1000 load from ma1 to ma0 eld ma1,ma0 1001 load from ma0 to ma1 eadd ma,p 1010 add ma and p esub ma,p 1011 subtract p from ma eadd ma,psh 1100 add ma and 24-bit right shifted p esub ma,psh 1101 subtract 24-bit right shifted p from ma edivq 1110 division step ? 1111 reserved xi mnemonic encoding description x0 0 x0[23:0] register x1 1 x1[23:0] register yi mnemonic encoding description y0 0 y0[23:0] register y1 1 y1[23:0] register rs mnemonic encoding description er 0 bit reset instruction es 1 bit set instruction
mac2424 S3FB42F 25- 52 (2) overall cop instruction set map instruction 11 10 9 8 7 6 5 4 3 2 1 0 emad xiyi mgx,@rps 0 0 0 0 0 xiyi mgx rps emsb xiyi mgx,@rps 0 0 0 0 1 xiyi mgx rps emld xiyi mgx,@rps 0 0 0 1 0 xiyi mgx rps emul xiyi mgx,@rps 0 0 0 1 1 xiyi mgx rps eadd a,ma mgx,@rps 0 0 1 0 0 0 0 mgx rps esub a,ma mgx,@rps 0 0 1 0 0 0 1 mgx rps eld a,ma mgx,@rps 0 0 1 0 0 1 0 mgx rps eadd ma,p mgx,@rps 0 0 1 0 0 1 1 mgx rps esub ma,p mgx,@rps 0 0 1 0 1 0 0 mgx rps eld ma,p mgx,@rps 0 0 1 0 1 0 1 mgx rps eadd ma,p @ rpd,mga 0 0 1 0 1 1 0 mga rpd esub ma,p @ rpd,mga 0 0 1 0 1 1 1 mga rpd eld ma,p @ rpd,mga 0 0 1 1 0 0 0 mga rpd eadd a,ma @ rpd,mga 0 0 1 1 0 0 1 mga rpd esub a,ma @ rpd,mga 0 0 1 1 0 1 0 mga rpd eld a,ma @ rpd,mga 0 0 1 1 0 1 1 mga rpd eadd a,ma ma,@rps 0 0 1 1 1 0 0 0 0 rps esub a,ma ma,@rps 0 0 1 1 1 0 0 0 1 rps eld a,ma ma,@rps 0 0 1 1 1 0 0 1 0 rps eadd ma,p a,@rps 0 0 1 1 1 0 0 1 1 rps esub ma,p a,@rps 0 0 1 1 1 0 1 0 0 rps eld ma,p a,@rps 0 0 1 1 1 0 1 0 1 rps eld ai,@rps 0 0 1 1 1 0 1 1 ai rps eadd ai,@rps 0 0 1 1 1 1 0 0 ai rps esub ai,@rps 0 0 1 1 1 1 0 1 ai rps ecp ai,@rps 0 0 1 1 1 1 1 0 ai rps eld @ rpd,ai 0 0 1 1 1 1 1 1 ai rpd eld mg1,@rps 0 1 0 0 0 0 mg1 rps eld @rpd,mg1 0 1 0 0 0 1 mg1 rpd note: ?d? means don?t care.
S3FB42F mac2424 25- 53 overall cop instruction set map (continued) instruction 11 10 9 8 7 6 5 4 3 2 1 0 eld srg,@rps 0 1 0 0 1 0 0 srg rps eld @ rpd,srg 0 1 0 0 1 0 1 srg rpd emax ai,@rps 0 1 0 0 1 1 0 0 ai rps emin ai,@rps 0 1 0 0 1 1 0 1 ai rps etst cct 0 1 0 0 1 1 1 0 cct eld xi,@rp0s yi,@rp3s 0 1 0 0 1 1 1 1 yi rp3s xi rp0s emad xiyi xi,@rp0s yi,@rp3s 0 1 0 1 0 0 xiyi yi rp3s xi rp0s emsb xiyi xi,@rp0s yi,@rp3s 0 1 0 1 0 1 xiyi yi rp3s xi rp0s emld xiyi xi,@rp0s yi,@rp3s 0 1 0 1 1 0 xiyi yi rp3s xi rp0s emul xiyi xi,@rp0s yi,@rp3s 0 1 0 1 1 1 xiyi yi rp3s xi rp0s eld rpi,rpd1.adr:4 0 1 1 0 0 0 rpi adr:4 eld rpd1.adr:4,rpi 0 1 1 0 0 1 rpi adr:4 eld rpdi.adr:5,ai 0 1 1 0 1 rpdi ai adr:5 eld ai,rpdi.adr:5 0 1 1 1 0 rpdi ai adr:5 eadd ai,rpdi.adr:5 0 1 1 1 1 rpdi ai adr:5 esub ai,rpdi.adr:5 1 0 0 0 0 rpdi ai adr:5 ecp ai,rpdi.adr:5 1 0 0 0 1 rpdi ai adr:5 eld mgx,#imm:16 1 0 0 1 0 0 mgx imm:16 eld rpi,#imm:16 1 0 0 1 0 1 rpi imm:16 eld sdi,#imm:16 1 0 0 1 1 0 sdi imm:16 erpn rpi,#imm:15 1 0 0 1 1 1 0 rpi imm:15 eld mci,#imm:16 1 0 0 1 1 1 1 mci imm:16 eld ai,#imm:16 1 0 1 0 0 0 0 ai imm:16 eadd ai,#imm:16 1 0 1 0 0 0 1 ai imm:16 esub ai,#imm:16 1 0 1 0 0 1 0 ai imm:16 ecp ai,#imm:16 1 0 1 0 0 1 1 ai imm:16 eld adr:15,ai 1 0 1 0 1 0 0 0 ai adr:15 eld ai,adr:15 1 0 1 0 1 0 0 1 ai adr:15 eadd ai,adr:15 1 0 1 0 1 0 1 0 ai adr:15 esub ai,adr:15 1 0 1 0 1 0 1 1 ai adr:15 ecp ai,adr:15 1 0 1 0 1 1 0 0 ai adr:15 note: ?d? means don?t care. ?gray? means 2 word instruction
mac2424 S3FB42F 25- 54
S3FB42F mac2424 25- 55 overall cop instruction set map (continued) instruction 11 10 9 8 7 6 5 4 3 2 1 0 emod2 ma 1 0 1 0 1 1 0 1 emod2 er/es bs 1 0 1 0 1 1 1 rs bs eld mg1d,mg1s 1 0 1 1 0 0 mg1d mg1s eld mg2d,mg2s 1 0 1 1 0 1 mg2d mg2s eld sdid,sdis 1 0 1 1 1 0 0 0 sdid sdis eld srgd,srgs 1 0 1 1 1 0 0 1 srgd srgs erps rps 1 0 1 1 1 0 1 0 0 rps erpd rpd 1 0 1 1 1 0 1 0 1 rpd erpr rpi 1 0 1 1 1 0 1 1 0 0 rpi reserved 1 0 1 1 1 0 1 1 1 ddd emod1 ai 1 0 1 1 1 1 ts ai emod1 emad xiyi a,ma 1 1 0 0 0 0 0 0 0 0 xiyi emsb xiyi a,ma 1 1 0 0 0 0 0 0 0 1 xiyi emld xiyi a,ma 1 1 0 0 0 0 0 0 1 0 xiyi emul xiyi a,ma 1 1 0 0 0 0 0 0 1 1 xiyi emad xiyi a,masl 1 1 0 0 0 0 0 1 0 0 xiyi emsb xiyi a,masl 1 1 0 0 0 0 0 1 0 1 xiyi emld xiyi a,masl 1 1 0 0 0 0 0 1 1 0 xiyi emul xiyi a,masl 1 1 0 0 0 0 0 1 1 1 xiyi emad xiyi a,masr 1 1 0 0 0 0 1 0 0 0 xiyi emsb xiyi a,masr 1 1 0 0 0 0 1 0 0 1 xiyi emld xiyi a,masr 1 1 0 0 0 0 1 0 1 0 xiyi emul xiyi a,masr 1 1 0 0 0 0 1 0 1 1 xiyi emad xiyi 1 1 0 0 0 0 1 1 0 0 xiyi emsb xiyi 1 1 0 0 0 0 1 1 0 1 xiyi emld xiyi 1 1 0 0 0 0 1 1 1 0 xiyi emul xiyi 1 1 0 0 0 0 1 1 1 1 xiyi esft asr,asa 1 1 0 0 0 1 0 0 asa asr esfta asr,asa 1 1 0 0 0 1 0 1 asa asr esftl asr,asa 1 1 0 0 0 1 1 0 asa asr esftd asr,asa 1 1 0 0 0 1 1 1 asa asr note: ?d? means don?t care.
mac2424 S3FB42F 25- 56 overall cop instruction set map (continued) instruction 11 10 9 8 7 6 5 4 3 2 1 0 eld sa,#imm:5 1 1 0 0 1 0 0 imm:5 enmsk sg,#imm:4 1 1 0 0 1 0 1 0 imm:4 emod0 aid,ais 1 1 0 0 1 0 1 1 emod0 aid ais eld mg,ai 1 1 0 0 1 1 ai mg emod0 ai,mg 1 1 0 1 emod0 ai mg esd0 ns #imm:4 1 1 1 0 0 0 ns imm:4 esd1 ns #imm:4 1 1 1 0 0 1 ns imm:4 esd2 ns #imm:4 1 1 1 0 1 0 ns imm:4 esd3 ns #imm:4 1 1 1 0 1 1 ns imm:4 enop 1 1 1 1 0 0 0 0 dddd esec0 #imm:4 1 1 1 1 0 0 0 1 imm:4 esec1 #imm:4 1 1 1 1 0 0 1 0 imm:4 esec2 #imm:4 1 1 1 1 0 0 1 1 imm:4 eld ai,#imm:5 1 1 1 1 0 1 ai imm:5 eadd ai,#imm:5 1 1 1 1 1 0 ai imm:5 ecp ai,#imm:5 1 1 1 1 1 1 ai imm:5 note: ?d? means don?t care.
S3FB42F mac2424 25- 57 quick reference opc op1 op2 op3 op4 op5 function flag emad xiyi mgx @ rps ? ? ma ? ma+p, p ? xi*yi, op2 ? op3 vmi emsb ma ? ma-p, p ? xi*yi, op2 ? op3 vmi emld ma ? p, p ? xi*yi, op2 ? op3 vmi emul p ? xi*yi, op2 ? op3 ? emad xiyi xi @rp0s yi @rp3s ma ? ma+p, p ? xi*yi, op2 ? op3, op4 ? op5 vmi emsb ma ? ma-p, p ? xi*yi, op2 ? op3, op4 ? op5 vmi emld ma ? p, p ? xi*yi, op2 ? op3, op4 ? op5 vmi emul p ? xi*yi, op2 ? op3, op4 ? op5 ? emad xiyi a ma/ masr/ masl ma ? ma+p, p ? xi*yi, op2 ? op3 vmi,z,va,n emsb ma ? ma-p, p ? xi*yi, op2 ? op3 vmi,z,va,n emld ma ? p, p ? xi*yi, op2 ? op3 vmi,z,va,n emul p ? xi*yi, op2 ? op3 n,va,z emad xiyi ? ? ? ? ma ? ma+p, p ? xi*yi vmi emsb ma ? ma-p, p ? xi*yi vmi emld ma ? p, p ? xi*yi vmi emul p ? xi*yi ? eadd a ma mgx @ rps ? op1 ? op1+op2, op3 ? op4 c,z,va,n esub op1 ? op1-op2, op3 ? op4 c,z,va,n eld op1 ? op2, op3 ? op4 z,va,n eadd ma p mgx @ rps ? op1 ? op1+op2, op3 ? op4 vmi esub op1 ? op1-op2, op3 ? op4 vmi eld op1 ? op2, op3 ? op4 ?
mac2424 S3FB42F 25- 58 quick reference opc op1 op2 op3 op4 op5 function flag eadd a ma @ rpd mga ? op1 ? op1+op2, op3 ? op4 c,z,va,n esub op1 ? op1-op2, op3 ? op4 c,z,va,n eld op1 ? op2, op3 ? op4 z,va,n eadd ma p @ rpd mga ? op1 ? op1+op2, op3 ? op4 vmi esub op1 ? op1-op2, op3 ? op4 vmi eld op1 ? op2, op3 ? op4 ? eadd a ma ma @ rps ? op1 ? op1+op2, op3 ? op4 c,z,va,n,vmi esub op1 ? op1-op2, op3 ? op4 c,z,va,n,vmi eld op1 ? op2, op3 ? op4 z,va,n,vmi eadd ma p a @ rps ? op1 ? op1+op2, op3 ? op4 vmi,z,va,n esub op1 ? op1-op2, op3 ? op4 vmi,z,va,n eld op1 ? op2, op3 ? op4 z,va,n eld ai mg/ @rps ai/adr:15 rpdi.adr:5 #imm:16 ? ? ? op1 ? op2 z,vi,n eadd op1 ? op1+op2 c,z,vi,n esub op1 ? op1-op2 c,z,vi,n ecp op1-op2 c,z,vi,n eld ai #imm:5 op1 ? op2 z,vi,n eadd op1 ? op1+op2 c,z,vi,n ecp op1-op2 c,z,vi,n ecp xi @rp0s yi @rp3s ? op1 ? op2, op3 ? op4 ? note: opc - opcode, op1 - operand1, op2 - operand2, op3 - operand3, op4 - operand4, op5 - operand5 vmi - vm0 or vm1 according to the current ma bank (when vmi is written, mv is written) vi - va or vb according to the ai bit
S3FB42F mac2424 25- 59 quick reference (continued) opc op1 op2 function flag eld @ rpd/mg adr:15 rpdi:adr:5 ai op1 ? op2 ? eld mgx/ mci #imm:16 op1 ? op2 ? eld mg1 mg1/@rps op1 ? op2 -( vmi) (note) eld srg srg/@ rps op1 ? op2 ? eld @ rpd mg1/srg op1 ? op2 ? eld mg2 mg2 op1 ? op2 ? eld rpi rpd1.adr:4 #imm:16 op1 ? op2 ? eld sdi sdi/#imm:16 op1 ? op2 ? eld ma1 ma0 op1 ? op2 vm1 eld ma0 ma1 op1 ? op2 vm0 eld rpd1.adr:4 rpi op1 ? op2 ? eadd ma p/psh op1 ? op1+op2 vmi esub op1 ? op1-op2 vmi emax ai @ rps if (n=1) op1 ? op2, rp3 ? rpi z,vi,n emin if (n=0) op1 ? op2, rp3 ? rpi z,vi,n erpn rpi #imm:15 op1 ? mod(op1+op2) ? erps rps ? op1 ? mod(op1+si) ? erpd rpd ? op1 ? mod(op1+di) ? erpr rpi ? rp3 ? bit_reverse(op1) ? etst cct ? t ? cct t er/es bs ? op1 ? 0/1 ? esft asr asa {sg,sr} ? op1<>op2 logical shift c,z,vs,n esfta {sg,sr} ? op1<>op2 arithmetic shift c,z,vs,n esftd sg ? sg|(op1<>op2) c,z,vs,n esftl sr ? op1<>op2, sg<-sg|(op1<>op2) c,z,vs,n
mac2424 S3FB42F 25- 60 quick reference (continued) opc op1 op2 function flag enmsk sg #imm:4 sg ? sg&mask_pattern by #imm:4 z,vs,n esd0 ns #imm:4 sd0.ns ? op2 ? esd1 sd1.ns ? op2 ? esd2 sd2.ns ? op2 ? esd3 sd3.ns ? op2 ? enop ? ? no operation ? esec0 #imm:4 ? msr2.sec0 ? op2 ? esec1 msr2.sec1 ? op2 ? esec2 msr2.sec2 ? op2 ? edivq ma p if (vmi=0) new remainder = op1-op2 else if (vmi=1) new remainder = op1+op2 if (new remainder>0) op1 ? new_remainder<<1 + 1 else op1 ? new_remainder<<1 vmi note: vmi is affected when op1 is ?ma?
S3FB42F mac2424 25- 61 quick reference (continued) opc op1 op2 function flag eresr ma ? if (vmi=1) op1 ? op1+2*p vmi esla op1 ? op1<<1 arithmetic vmi esra op1 ? op1>>1 arithmetic vmi ecr op1 ? 0 vmi esat op1 ? saturated(op1) vmi ernd op1 ? op1+800000h, op1[23:0]<-0 vmi esla/eslat (note) ai ? op1 ? op1<<1 arithmetic c,z,vi,n esra/esrat (note) op1 ? op1>>1 arithmetic c,z,vi,n esla8/esla8t (note) op1 ? op1<<8 arithmetic c,z,vi,n esra8/esra8t (note) op1 ? op1>>8 arithmetic c,z,vi,n eslc/eslct (note) op1 ? {op1[22:0],c} c,z,vi,n esrc/esrct (note) op1 ? {c,op1[23:1]} c,z,vi,n eincc/eincct (note) op1 ? op1+c c,z,vi,n edecc/edecct (note) op1 ? op1-~c c,z,vi,n eabs/eabst (note) op1 ? |op1| c,z,vi,n eneg/enegt (note) op1 ? ~op1+1 c,z,vi,n efs16/efs16t (note) op1[23:8] ? op1[7] c,z,vi,n efz16/efz16t (note) op1[23:8] ? 0 c,z,vi,n efs8/efs8t (note) op1[23:16] ? op1[16] c,z,vi,n efz8/efz8t (note) op1[23:16] ? 0 c,z,vi,n eexp/eexpt (note) sa ? exponent of (op1) c,z,vs,n eexpc/eexpct (note) if (vs=1) sa ? sa+exponent of ({c,op1}) c,z,vs,n note: if t=1, instruction is executed
mac2424 S3FB42F 25- 62 instruction set glossary this chapter describes the mac2424 instruction set, with the details of each instruction. the following notations are used for the description. notation interpretation < opn> operand n. n can be omitted if there is only one operand. typically, is the destination (and source) operand and is a source operand. < dest>, < src> destination and source operand for load. adr:n n-bit direct address specifier imm:n n-bit immediate number & bit-wise and | bit-wise or ~ bit-wise not ^ bit-wise xor n**m mth power of n it is further noted that only the affected flags are described in the tables in this section. that is, if a flag is not affected by an operation, it is not specified.
S3FB42F mac2424 25- 63 instruction description eabs/eabst * ? absolute format: eabs(t) ai operation: ai ? | ai| this instruction calculates the absolute value of one of 24-bit accumulator(ai), and stores the result back into the same accumulator. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * eabst instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: eabs a eabst b # of words: 1
mac2424 S3FB42F 25- 64 eadd 1) ? add accumulator format: eadd ai, : @ rps rpdi.adr: 5/adr:15 # simm: 5/#simm:16 ai mg operation: ai ? ai + this instruction adds the values of one of 24-bit accumulator(ai) and together, and stores the result back into the same accumulator. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi * : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * vi denotes for va or vb according to ai examples: eadd a, @rp0+s0 eadd b, rpd1.5h eadd a, #0486h eadd b, a eadd a, rp0 # of words: 1 2 when is: adr:15 or #simm:16
S3FB42F mac2424 25- 65 eadd 2) ? add accumulator with one parallel move format: eadd a, ma < dest>,< src> < dest>,< src>: mgx, @ rps ma, @ rps @ rpd, mga operation: a <- a + ma, < dest> <- < src> this instruction adds the values of 24-bit accumulator a and higher 24-bit part of multiplier accumulator ma together, and stores the result back into accumulator a. this instruction also stores source operand from memory or register to destination register or memory. flags: c: set if carry is generated by addition. reset if not. z: set if result is zero by addition. reset if not. va: set if overflow is generated by addition. reset if not. n: exclusive or of v and msb of result by addition. notes: none. examples: eadd a, ma x0,@rp0+s1 eadd a, ma ma,@rp1+s0 eadd a, ma @rp3+d1, a # of words: 1
mac2424 S3FB42F 25- 66 eadd 3) ? add multiplier accumulator format: eadd ma, : p / psh operation: ma ? ma + this instruction adds the values of 52-bit multiplier accumulator ma and together, and stores the result back into multiplier accumulator ma. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: eadd ma, p eadd ma, psh # of words: 1
S3FB42F mac2424 25- 67 eadd 4) ? add multiplier accumulator with one parallel move format: eadd ma, p, < dest>,< src> < dest>,< src>: mgx, @ rps a, @ rps @ rpd, mga operation: ma ? ma + p, < dest> ? < src> this instruction adds the values of 52-bit multiplier accumulator ma and product register p together, and stores the result back into multiplier accumulator ma. this instruction also stores source operand from memory or register to destination register or memory. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: eadd ma, p y0, @rp1+s1 eadd ma, p a, @rp2+s0 eadd ma, p @rp0+d0, b # of words: 1
mac2424 S3FB42F 25- 68 ecld ? coprocessor accumulator load from host processor format: ecld ereg, gpr ecld gpr, ereg operation: ereg ? grp or gpr ? ereg this instruction moves the selected 8-bit general purpose register value of host processor to the selected 8-bit field of ai(a or b) accumulator register or moves the selected 8-bit field of ai(a or b) accumulator register to the 8-bit general purpose register. this instruction is mapped to ?cld? instruction of calmrisc microcontroller. flags: ? notes: ? examples: ecld all, r0 ecld r1, bhl # of words: 1
S3FB42F mac2424 25- 69 ecp ? compare accumulator format: ecp ai, : @ rps rpdi.adr:5 / adr:15 #simm:5 / #simm:16 ai mg operation: ai - this instruction compares the values of accumulator ai and by subtracting from accumulator. content of accumulator is not changed. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi * : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * vi denotes for va or vb according to ai examples: ecp a, @rp0+s0 ecp b, rpd1.5h ecp a, #0486h ecp b, a ecp a, rp0 # of words: 1 2 when is : adr:15 or #simm:16
mac2424 S3FB42F 25- 70 ecr ? clear ma accumulator format: ecr ma operation: ma ? 0 this instruction clears the value of current bank ma accumulator. the extension nibble of selected ma accumulator is also cleared in 24-bit operation mode and unchanged in 16-bit operation mode. flags: vmi * : 0. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: ecr ma # of words: 1
S3FB42F mac2424 25- 71 edecc/edecct * ? decrement with carry format: edecc(t) ai operation: ai ? ai - ~c this instruction subtracts 1 from the value of one of 24-bit accumulator(ai) if current carry flag is cleared, and stores the result back into the same accumulator. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * edecct instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: edecc a edecct b # of words: 1
mac2424 S3FB42F 25- 72 edivq ? division step format: edivq ma,p operation: if ( vmi = 0) adder output ? ma ? p else adder output ? ma + p if (adder output > 0) ma ? adder output * 2 + 1 else ma ? adder output * 2 this instruction adds or subtracts current bank ma accumulator from p register according to the vmi bit value and calculates one bit quotient and new partial remainder. flags: vmi * : if (adder output > 0) vmi ? 0, else vmi ? 1 notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: edivq ma,p # of words: 1
S3FB42F mac2424 25- 73 eexp/eexpt * ? exponent value evaluation format: eexp(t) ai operation: sa ? exponent(ai) this instruction evaluates the exponent value of one of 24-bit accumulator(ai), and stores the result back into 5-bit sa register. flags: c: set if lsb of source ai accumulator is 1. reset if not. z: set if exponent evaluation result is zero. reset if not. vs: set if the value of source ai accumulator is all zeroes or all ones. reset if not. n: reset. notes: * eexpt instruction can be executed only when the t flag is set. otherwise, no operation is performed. examples: eexp a eexpt b # of words: 1
mac2424 S3FB42F 25- 74 eexpc/eexpct * ? exponent value evaluation with carry format: eexpc(t) ai operation: if (vs = 1) sa ? exponent({ c,ai}) else no operation this instruction evaluates the exponent value which concatenates carry and one of 24-bit accumulator(ai), adds the result with sa register value, and stores the added result back into 5- bit sa register. it can be used for multi-precision exponent evaluation. flags: c: set if lsb of source ai accumulator is 1. reset if not. z: set if exponent evaluation result is zero. reset if not. vs: set if the value of carry and source ai accumulator is all zeroes or all ones. reset if not. n: reset. notes: * eexpct instruction can be executed only when the t flag is set. otherwise, no operation is performed. examples: eexpc a eexpct b # of words: 1
S3FB42F mac2424 25- 75 efs16/efs16t * ? force to sign msb16 bits format: efs16(t) ai operation: ai ? {16{ai[7]},ai[7:0]} this instruction forces the value of msb 16 bits of 24-bit accumulator(ai) with byte sign bit of ai register(ai[7]), and stores the result back into the same accumulator. flags: c: reset. z: set if result is zero. reset if not. vi ** : reset. n: msb of result. notes: * efs16t instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: efs16 a efs16t b # of words: 1
mac2424 S3FB42F 25- 76 efs8/efs8t * ? force to sign msb8 bits format: efs8(t) ai operation: ai ? {8{ai[15]},ai[15:0]} this instruction forces the value of msb 8 bits of 24-bit accumulator(ai) with word sign bit of ai register(ai[15]), and stores the result back into the same accumulator. flags: c: reset. z: set if result is zero. reset if not. vi ** : reset. n: msb of result. notes: * efs8t instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: efs8 a efs8t b # of words: 1
S3FB42F mac2424 25- 77 efz16/efz16t * ? force to zero msb16 bits format: efz16(t) ai operation: ai ? {16{0},ai[7:0]} this instruction forces the value of msb 16 bits of 24-bit accumulator(ai) with zero, and stores the result back into the same accumulator. flags: c: reset. z: set if result is zero. reset if not. vi ** : reset. n: reset. notes: * efz16t instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: efz16 a efz16t b # of words: 1
mac2424 S3FB42F 25- 78 efz8/efz8t * ? force to zero msb8 bits format: efz8(t) ai operation: ai ? {8{0},ai[15:0]} this instruction forces the value of msb 8 bits of 24-bit accumulator(ai) with zero, and stores the result back into the same accumulator. flags: c: reset. z: set if result is zero. reset if not. vi ** : reset. n : reset. notes: * efz8t instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: efz8 a efz8t b # of words: 1
S3FB42F mac2424 25- 79 eincc/eincct * ? increment with carry format: eincc(t) ai operation: ai ? ai + c this instruction adds 1 from the value of one of 24-bit accumulator(ai) if current carry flag is set, and stores the result back into the same accumulator. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * eincct instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: eincc a eincct b # of words: 1
mac2424 S3FB42F 25- 80 eld 1) ? load accumulator format: eld ai, : @ rps rpdi.adr:5 / adr:15 #simm:5 / #simm:16 ai mg operation: ai ? this instruction load value to the one of 24-bit accumulator(ai). flags: z: set if result is zero. reset if not. vi * : set if overflow is generated. reset if not. n: set if loaded value is negative. notes: * vi denotes for va or vb according to ai examples: eld a, @rp0+s0 eld b, rpd1.5h eld a, #0486h eld b, a eld a, rp0 # of words: 1 2 when is : adr:15 or #simm:16
S3FB42F mac2424 25- 81 eld 2) ? load accumulator with one parallel move format: eld a, ma < dest>,< src> < dest>,< src>: mgx, @ rps ma, @ rps @ rpd, mga operation: a ? ma, < dest> ? < src> this instruction load higher 24-bit part of multiplier accumulator ma to the 24-bit accumulator a. this instruction also stores source operand from memory or register to destination register or memory. flags: z: set if result is zero by load. reset if not. va: set if overflow is generated by load. reset if not. n: set if loaded value is negative. notes: none. examples: eld a, ma x0,@rp0+s1 eld a, ma ma,@rp1+s0 eld a, ma @rp3+d1, a # of words: 1
mac2424 S3FB42F 25- 82 eld 3) ? load multiplier accumulator format: eld ma0, ma1 eld ma1, ma0 operation: mai ? maj this instruction loads the value of the one 52-bit multiplier accumulator ma from the other multiplier accumulator. flags: vmi * : set if result is overflowed to guard-bits. reset if not. notes: * vmi denotes for vm0 or vm1 according to destination multiplier accumulator. examples: eld ma1, ma0 eld ma0, ma1 # of words: 1
S3FB42F mac2424 25- 83 eld 4) ? load multiplier accumulator with one parallel move format: eld ma, p < dest>,< src> < dest>,< src>: mgx, @ rps a, @ rps @ rpd, mga operation: ma ? a, < dest> ? < src> this instruction load sign-extended 48-bit product register p to the 52-bit multiplier accumulator ma. this instruction also stores source operand from memory or register to destination register or memory. flags: vmi * : set if result is overflowed to guard-bits. reset if not notes: * vmi denotes for vm0 or vm1 according to destination multiplier accumulator. examples: eld ma, p x0,@rp0+s1 eld ma, p a,@rp1+s0 eld ma, p @rp3+d1, a eld ma, p @rp0+d0, ma ; @rp0+d0 ? ma ma ? p # of words: 1
mac2424 S3FB42F 25- 84 eld 5) ? load other registers or memory format: eld < dest>, < src> < dest>,< src>: mg1, @ rps srg, @ rps @ rpd, ai @ rpd, mg1 @ rpd, srg rpi, rpd1.adr:4 rpd1.adr:4, rpi rpdi.adr:5, ai adr:15, ai mgx, #imm:16 rpi, #imm:16 sdi, #imm:16 mci, #imm:16 sa, #imm:5 mg1d, mg1s mg2d, mg2s sdid, sdis srgd, srgs mg, ai operation: < dest> ? < src> this instruction load < src> value to < dest>. if the width of < src> is less than the width of < dest>, < dest> is sign-extended, and if more, lsb part of < src> is written to < dest> flags: no effect when < dest> is not ma or ai. when < dest> is ma : vmi * : set if result is overflowed to guard-bits. reset if not when < dest> is ai : z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: set if loaded value is negative. notes: * vmi denotes for vm0 or vm1 according to destination multiplier accumulator. ** vi denotes for va or vb according to ai examples: eld @rp0+d0, b eld rpd1.5h, rp2 eld mc0, #0486h eld rpd1, mc0 eld x0, y1 eld ma, p ; mah ? ph # of words: 1 2 when < dest> or < src> is : adr:15 or #imm:16
S3FB42F mac2424 25- 85 eld 6) ? double load format: eld xi,@rp0s yi,@rp3s operation: xi ? operand1 by @rp0s, yi ? operand2 by @rp3s this instruction loads two operands from data memory (one from x memory space, and the other from y memory space) to the specified 24-bit xi and yi register, respectively. flags: ? notes: ? examples: eld x0,@rp0+s1 y1,@rp3+s0 # of words: 1
mac2424 S3FB42F 25- 86 emad 1) ? multiply and add format: emad xi,yi operation: ma ? ma + p, p ? xi * yi this instruction adds the values of 52-bit multiplier accumulator ma and p register together, and stores the result back into multiplier accumulator ma. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: emad x1y0 # of words: 1
S3FB42F mac2424 25- 87 emad 2) ? multiply and add with one parallel move format: emad xi,yi < dest>,< src> < dest>,< src>: a,ma a,masr * a,masl ** mgx,@rps operation: ma ? ma + p, p ? xi * yi, < dest> ? < src> this instruction adds the values of 52-bit multiplier accumulator ma and p register together, and stores the result back into multiplier accumulator ma. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores source operand from data memory or 24-bit higher portion of the ma register to the destination register. flags: vmi *** : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. when < dest> is ai z: set if the value to ai is zero by load. reset if not. va: set if overflow is generated by load. reset if not. n: set if loaded value is negative. notes: * masr: 1-bit right shifted ma[47:24] ** masl: 1-bit left shifted ma[47:24] *** vmi denotes for vm0 or vm1 according to the current ma bank. examples: emad x1y0 a,masr emad x0y0 x0,@rp1+s1 # of words: 1
mac2424 S3FB42F 25- 88 emad 3) ? multiply and add with two parallel moves format: emad xi,yi xi,@rp0s yi,@rp3s operation: ma ? ma + p, p ? xi * yi, xi ? operand1 by @rp0s, yi ? operand2 by @rp3s this instruction adds the values of 52-bit multiplier accumulator ma and p register together, and stores the result back into multiplier accumulator ma. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores two source operand from data memory (one from x memory space and one from y memory space) to the 24-bit xi register and yi register respectively. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: emad x1y0 x0,@rp0+s1 y0,@rp3+s0 # of words: 1
S3FB42F mac2424 25- 89 emax ? maximum value load format: emax ai, : @ rps operation: if (n = 1) ai ? , rp3 ? current pointer value else no operation (only pointer is updated) this instruction conditionally loads value to the one of 24-bit accumulator(ai) and latches the current pointer value to the rp3 pointer when n flag of msr0 register is set. otherwise, no operation is performed flags: z: set if result is zero. reset if not. vi * : set if overflow is generated. reset if not. n: set if loaded value is negative. notes: * vi denotes for va or vb according to ai examples: emax a, @rp0+s0 # of words: 1
mac2424 S3FB42F 25- 90 emin ? minimum value load format: emin ai, : @ rps operation: if (n = 0) ai ? , rp3 ? current pointer value else no operation (only pointer is updated) this instruction conditionally loads value to the one of 24-bit accumulator(ai) and latches the current pointer value to the rp3 pointer when n flag of msr0 register is cleared. otherwise, no operation is performed flags: z: set if result is zero. reset if not. vi * : set if overflow is generated. reset if not. n: set if loaded value is negative. notes: * vi denotes for va or vb according to ai examples: emin b, @rp0+s0 # of words: 1
S3FB42F mac2424 25- 91 emld 1) ? multiply and load format: emld xi,yi operation: ma ? p, p ? xi * yi this instruction loads the p register value to the values of 52-bit multiplier accumulator ma at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: emld x1y0 # of words: 1
mac2424 S3FB42F 25- 92 emld 2) ? multiply and load with one parallel move format: emld xi,yi < dest>,< src> < dest>,< src>: a,ma a,masr * a,masl ** mgx,@rps operation: ma ? p, p ? xi * yi, < dest> ? < src> this instruction loads the p register value to the values of 52-bit multiplier accumulator. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores source operand from data memory or 24-bit higher portion of the ma register to the destination register. flags: vmi *** : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. when < dest> is ai z: set if the value to ai is zero by load. reset if not. va: set if overflow is generated by load. reset if not. n: set if loaded value is negative. notes: * masr: 1-bit right shifted ma[47:24] ** masl: 1-bit left shifted ma[47:24] *** vmi denotes for vm0 or vm1 according to the current ma bank. examples: emld x1y0 a,masr emld x0y0 x0,@rp1+s1 # of words: 1
S3FB42F mac2424 25- 93 emld 3) ? multiply and load with two parallel moves format: emld xi,yi xi,@rp0s yi,@rp3s operation: ma ? p, p ? xi * yi, xi ? operand1 by @rp0s, yi ? operand2 by @rp3s this instruction loads the p register value to the values of 52-bit multiplier accumulator. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores two source operands from data memory (one from x memory space and one from y memory space) to the 24-bit xi register and yi register respectively. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: emld x1y0 x0,@rp0+s1 y0,@rp3+s0 # of words: 1
mac2424 S3FB42F 25- 94 emsb 1) ? multiply and subtract format: emsb xi,yi operation: ma ? ma - p, p ? xi * yi this instruction subtracts the p register from the values of 52-bit multiplier accumulator ma, and stores the result back into multiplier accumulator ma. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: emsb x1y0 # of words: 1
S3FB42F mac2424 25- 95 emsb 2) ? multiply and subtract with one parallel move format: emsb xi,yi < dest>,< src> < dest>,< src>: a,ma a,masr * a,masl ** mgx,@rps operation: ma ? ma - p, p ? xi * yi, < dest> ? < src> this instruction subtracts the p register from the values of 52-bit multiplier accumulator ma, and stores the result back into multiplier accumulator ma. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores source operand from data memory or 24-bit higher portion of the ma register to the destination register. flags: vmi *** : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. when < dest> is ai z: set if the value to ai is zero by load. reset if not. va: set if overflow is generated by load. reset if not. n: set if loaded value is negative. notes: * masr: 1-bit right shifted ma[47:24] ** masl: 1-bit left shifted ma[47:24] *** vmi denotes for vm0 or vm1 according to the current ma bank. examples: emsb x1y0 a,masr emsb x0y0 x0,@rp1+s1 # of words: 1
mac2424 S3FB42F 25- 96 emsb 3) ? multiply and subtract with two parallel moves format: emsb xi,yi xi,@rp0s yi,@rp3s operation: ma ? ma - p, p ? xi * yi, xi ? operand1 by @rp0s, yi ? operand2 by @rp3s this instruction subtracts the p register from the values of 52-bit multiplier accumulator ma, and stores the result back into multiplier accumulator ma. at the same time, multiplier multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores two source operand from data memory (one from x memory space and one from y memory space) to the 24-bit xi register and yi register respectively. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: emsb x1y0 x0,@rp0+s1 y0,@rp3+s0 # of words: 1
S3FB42F mac2424 25- 97 emul 1) ? multiply format: emlu xi,yi operation: p ? xi * yi this instruction multiplies xi register value and yi register value, and stores the result to the p register. flags: ? notes: ? examples: emul x1y0 # of words: 1
mac2424 S3FB42F 25- 98 emul 2) ? multiply with one parallel move format: emul xi,yi < dest>,< src> < dest>,< src>: a,ma a,masr * a,masl ** mgx,@rps operation: p ? xi * yi, < dest> ? < src> this instruction multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores source operand from data memory or 24-bit higher portion of the ma register to the destination register. flags: when < dest> is ai z: set if the value to ai is zero by load. reset if not. va: set if overflow is generated by load. reset if not. n: set if loaded value is negative. notes: * masr : 1-bit right shifted ma[47:24] ** masl : 1-bit left shifted ma[47:24] examples: emul x1y0 a,masr emul x0y0 x0,@rp1+s1 # of words: 1
S3FB42F mac2424 25- 99 emul 3) ? multiply with two parallel moves format: emul xi,yi xi,@rp0s yi,@rp3s operation: p ? xi * yi, xi <- operand1 by @rp0s, yi ? operand2 by @rp3s this instruction multiplies xi register value and yi register value, and stores the result to the p register. this instruction also stores two source operand from data memory (one from x memory space and one from y memory space) to the 24-bit xi register and yi register respectively. flags: ? notes: ? examples: emul x1y0 x0,@rp0+s1 y0,@rp3+s0 # of words: 1
mac2424 S3FB42F 25- 100 eneg/enegt * ? negate format: eneg(t) ai operation: ai ? ~ai + 1 this instruction negates the value of one of 24-bit accumulator(ai), and stores the result back into the same accumulator. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * enegt instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: eneg a enegt b # of words: 1
S3FB42F mac2424 25- 101 enmsk ? masking sg format: enmsk sg,#imm:4 operation: sg ? sg & mask pattern this instruction masks msb n bit (n = 16 - #imm:4) of sg register, and stores back the result into the sg register. flags: z: set if result is zero. reset if not. vs: reset. n: msb of result. notes: ? examples: enmsk sg,#3h # of words: 1
mac2424 S3FB42F 25- 102 enop ? no operation format: enop operation: no operation. flags: ? notes: ? examples: enop # of words: 1
S3FB42F mac2424 25- 103 er ? bit reset format: er bs * operation: specified bit in bs field ? 0 this instruction sets the specified bit in bs field to 0. flags: ? notes: * if bs field is vm, the current bank of vmi bit is cleared. i.e. vm0 is cleared when bkma bit is 1 and vm1 is cleared when bkma bit is 0. examples: er opa er me3 # of words: 1
mac2424 S3FB42F 25- 104 eresr ? restoring remainder format: eresr ma,p operation: if ( vmi = 0) adder output ? ma + 0 else adder output ? ma + 2*p this instruction adds two times of the p register and current bank ma accumulator when vmi bit of msr1 register is set. else, performs no operation. it calculates true remainder value of non- restoring division. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: eresr ma,p # of words: 1
S3FB42F mac2424 25- 105 ernd ? round format: ernd ma operation: ma ? ma + 0000000800000h, ma[23:0] ? 0 this instruction adds current bank 52-bit ma accumulator and rounding constant and stores the result value into msb part of the same register. the lsb 24-bit of the ma register is cleared. it performs two?s complement rounding. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: ernd ma # of words: 1
mac2424 S3FB42F 25- 106 erpd ? update pointer with destination index format: erpd rpd operation: rpi ? mod ( rpi + d0/d1) this instruction updates the selected pointer with the selected index value. the modulo arithmetic affect the result value when me bit of selected pointer is set. it only modifies the pointer without memory access. flags: ? notes: ? examples: erpd rp0+d1 # of words: 1
S3FB42F mac2424 25- 107 erpn ? update pointer with immediate value format: erpn rpi,#imm:15 operation: rpi ? mod ( rpi + #imm:15) this instruction updates the selected pointer with 15-bit immediate value. the modulo arithmetic affect the result value when me bit of selected pointer is set. it only modifies the pointer without memory access. flags: ? notes: ? examples: erpn rp3,#1555h # of words: 2
mac2424 S3FB42F 25- 108 erpr ? bit-reverse pointer format: erpr rpi operation: rp3 ? bit-reverse ( rpi) this instruction generates the reversed bit pattern on lsb n bit of the selected pointer according to the mc1[15:13] bit values which specifies bit reverse order. (refer to mc1 register configuration in chapter 2) the result bit pattern is written to rp3 register pointer field. the source pointer value is not changed at all and the me bit of rp3 is not changed, either. flags: ? notes: ? examples: erpr rp2 # of words: 1
S3FB42F mac2424 25- 109 erps ? update pointer with source index format: erps rps operation: rpi ? mod ( rpi + s0/s1) this instruction updates the selected pointer with the selected index value. the modulo arithmetic affect the result value when me bit of selected pointer is set. it only modifies the pointer without memory access. flags: ? notes: ? examples: erps rp0+s1 # of words: 1
mac2424 S3FB42F 25- 110 es ? bit set format: es bs * operation: specified bit in bs field ? 1 this instruction sets the specified bit in bs field to 1. flags: ? notes: * if bs field is vm, the current bank of vmi bit is set. i.e. vm0 is set when bkma bit is 1 and vm1 is set when bkma bit is 0. examples: es opa es me3 # of words: 1
S3FB42F mac2424 25- 111 esat ? saturate format: esat ma operation: if ( vmi == 1) ma ? maximum magnitude this instruction sets the 52-bit ma accumulator to the plus of minus maximum value when selected ma register overflows. when no overflow occur, the ma register is not changed. flags: vmi * : reset notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: esat ma # of words: 1
mac2424 S3FB42F 25- 112 esd0/esd1/esd2/esd3 ? source/destination index load format: esd0 * ns #imm:4 esd1 ns #imm:4 esd2 ns #imm:4 esd3 * ns #imm:4 operation: specified sdi register bit field in ns field ? #imm:4 this instruction loads 4-bit immediate value to the specified bit field of sdi register. only 4-bit field of 16-bit value is changed. flags: ? notes: * if xsd bit of msr0 register is 1, the selected register is the extended index registers (sd0e and sd3e). else, the selected register is the regular index register. (sd0 and sd3) examples: esd0 d0 #3h esd1 s1 # fh # of words: 1
S3FB42F mac2424 25- 113 esec0/esec1/esec2 ? ei selection field load format: esec0 #imm:4 esec1 #imm:4 esec2 #imm:4 operation: specified seci (i=0~2) field of msr2 register ? #imm:4 this instruction loads 4-bit immediate value to the specified bit field of msr2 register. only 4-bit field of 16-bit value is changed. flags: ? notes: ? examples: esec0 #3h esec1 # fh # of words: 1
mac2424 S3FB42F 25- 114 esft ? logical shift by barrel shifter format: esft asr,asa operation: {sr,sg} ? asr<< asa this instruction shifts the value of 16-bit asr values by the amount of 6-bit asa. if the value of asa is positive, left shift operation is performed, and if the value of asa is negative right shift operation is performed. the 16-bit shifted result is stored into sr register and the 16-bit shifted out result is stored into sg register. the other bits of sr and sg register are filled with zeros. flags: c: set if last shifted out bit is 1. reset if not. unchanged when shift amount is 0. z: set if sr result is zero. reset if not. vs: reset. n: msb of sr result. notes: ? examples: esft a, b esft si,sa # of words: 1
S3FB42F mac2424 25- 115 esfta ? arithmetic shift by barrel shifter format: esfta asr,asa operation: {sr,sg} ? asr<< asa this instruction shifts the value of 16-bit asr values by the amount of 6-bit asa. if the value of asa is positive, left shift operation is performed, and if the value of asa is negative right shift operation is performed. the 16-bit shifted result is stored into sr register and the 16-bit shifted out result is stored into sg register. the remainder msb bits of sr or sg register are sign extended and the remainder lsb bits are filled with zeros. flags: c: set if last shifted out bit is 1. reset if not. unchanged when shift amount is 0. z: set if sr result is zero. reset if not. vs: set if overflow is generated. reset if not. n: msb of sr result. notes: ? examples: esfta a, b esfta si,sa # of words: 1
mac2424 S3FB42F 25- 116 esftd ? double shift by barrel shifter format: esftd asr,asa operation: sg ? sg | ( asr<< asa) this instruction shifts the value of 16-bit asr values by the amount of 6-bit asa. if the value of asa is positive, left shift operation is performed, and if the value of asa is negative right shift operation is performed. the 16-bit shifted result is ored with previous sg register value ,and then stored into sg register. flags: c: set if last shifted out bit is 1. reset if not. unchanged when shift amount is 0. z: set if sg result is zero. reset if not. vs: reset. n: msb of sg result. notes: ? examples: esftd a, b esftd si,sa # of words: 1
S3FB42F mac2424 25- 117 esftl ? linked shift by barrel shifter format: esftl asr,asa operation: sr ? asr<< asa, sg ? sg | ( asr<< asa) this instruction shifts the value of 16-bit asr values by the amount of 6-bit asa. if the value of asa is positive, left shift operation is performed, and if the value of asa is negative right shift operation is performed. the 16-bit shifted result is stored into sr register and the 16-bit shifted out result is ored with previous sg value and stored into sg register. the other bits of sr register are filled with zeros. flags: c: set if last shifted out bit is 1. reset if not. unchanged when shift amount is 0. z: set if sr result is zero. reset if not. vs: reset. n: msb of sr result. notes: ? examples: esftl a, b esftl si,sa # of words: 1
mac2424 S3FB42F 25- 118 esla 1) /eslat * ? arithmetic 1-bit left shift accumulator format: esla(t) ai operation: ai ? ai <<1 this instruction shifts the value of one of 24-bit accumulator(ai) to 1-bit left , and stores the result back into the same accumulator. flags: c: set if shifted out bit is 1. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * eslat instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: esla a eslat b # of words: 1
S3FB42F mac2424 25- 119 esla 2) ? arithmetic 1-bit left shift multiplier accumulator format: esla ma operation: ma ? ma <<1 this instruction shifts the value of current bank 52-bit multiplier accumulator ma to 1-bit left , and stores the result back into the same multiplier accumulator. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: esla ma # of words: 1
mac2424 S3FB42F 25- 120 esla8/esla8t * ? arithmetic 8-bit left shift accumulator format: esla8(t) ai operation: ai ? ai <<8 this instruction shifts the value of one of 24-bit accumulator(ai) to 8-bit left , and stores the result back into the same accumulator. flags: c: set if last shifted out bit is 1. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * esla8t instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: esla8 a esla8t b # of words: 1
S3FB42F mac2424 25- 121 eslc/eslct * ? arithmetic 1-bit left shift accumulator with carry format: eslc(t) ai operation: ai ? ai <<1, ai[0] ? c this instruction shifts the value of one of 24-bit accumulator(ai) to 1-bit left with carry : i.e. the carry bit is shifted into lsb of ai register, and stores the result back into the same accumulator. flags: c: set if shifted out bit is 1. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * eslct instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: eslc a eslct b # of words: 1
mac2424 S3FB42F 25- 122 esra 1) /esrat * ? arithmetic 1-bit right shift accumulator format: esra(t) ai operation: ai ? ai >>1 this instruction shifts the value of one of 24-bit accumulator (ai) to 1-bit right, and stores the result back into the same accumulator. flags: c: set if shifted out bit is 1. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * eslrt instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: esra a esrat b # of words: 1
S3FB42F mac2424 25- 123 esra 2) ? arithmetic 1-bit right shift multiplier accumulator format: esra ma operation: ma ? ma >>1 this instruction shifts the value of current bank 52-bit multiplier accumulator ma to 1-bit right, and stores the result back into the same multiplier accumulator. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: esra ma # of words: 1
mac2424 S3FB42F 25- 124 esra8/esra8t * ? arithmetic 8-bit right shift accumulator format: esra8(t) ai operation: ai ? ai >>8 this instruction shifts the value of one of 24-bit accumulator(ai) to 8-bit right, and stores the result back into the same accumulator. flags: c: set if last shifted out bit is 1. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * esra8t instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: esra8 a esra8t b # of words: 1
S3FB42F mac2424 25- 125 esrc/esrct * ? arithmetic 1-bit right shift accumulator with carry format: esrc(t) ai operation: ai ? ai >>1, ai[23] ? c this instruction shifts the value of one of 24-bit accumulator(ai) to 1-bit right with carry : i.e. the carry bit is shifted into msb of ai register, and stores the result back into the same accumulator. flags: c: set if shifted out bit is 1. reset if not. z: set if result is zero. reset if not. vi ** : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * esrct instruction can be executed only when the t flag is set. otherwise, no operation is performed. ** vi denotes for va or vb according to ai examples: esrc a esrct b # of words: 1
mac2424 S3FB42F 25- 126 esub 1) ? subtract accumulator format: esub ai, : @ rps rpdi.adr:5 / adr:15 #simm:16 ai mg operation: ai ? ai - this instruction subtracts value from the value of one of 24-bit accumulator(ai), and stores the result back into the same accumulator. flags: c: set if carry is generated. reset if not. z: set if result is zero. reset if not. vi * : set if overflow is generated. reset if not. n: exclusive or of vi and msb of result. notes: * vi denotes for va or vb according to ai examples: esub a, @rp0+s0 esub b, rpd1.5h esub a, #0486h esub b, a esub a, rp0 # of words: 1 2 when is : adr:15 or #simm:16
S3FB42F mac2424 25- 127 esub 2) ? subtract accumulator with one parallel move format: esub a, ma < dest>,< src> < dest>,< src>: mgx, @ rps ma, @ rps @ rpd, mga operation: a ? a - ma, < dest> ? < src> this instruction subtracts higher 24-bit part of multiplier accumulator ma from the value of 24-bit accumulator a, and stores the result back into accumulator a. this instruction also stores source operand from memory or register to destination register or memory. flags: c: set if carry is generated by addition. reset if not. z: set if result is zero by addition. reset if not. va: set if overflow is generated by addition. reset if not. n: exclusive or of v and msb of result by addition. notes: none. examples: esub a, ma x0,@rp0+s1 esub a, ma ma,@rp1+s0 esub a, ma @rp3+d1, a # of words: 1
mac2424 S3FB42F 25- 128 esub 3) ? subtract multiplier accumulator format: esub ma, : p / psh operation: ma ? ma - this instruction subtracts value from the values of 52-bit multiplier accumulator ma, and stores the result back into multiplier accumulator ma. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: esub ma, p esub ma, psh # of words: 1
S3FB42F mac2424 25- 129 esub 4) ? subtract multiplier accumulator with one parallel move format: esub ma, p < dest>,< src> < dest>,< src>: mgx, @ rps a, @ rps @ rpd, mga operation: ma ? ma - p, < dest> ? < src> this instruction subtracts the value of the product register p from the value of 52-bit multiplier accumulator ma, and stores the result back into multiplier accumulator ma. this instruction also stores source operand from memory or register to destination register or memory. flags: vmi * : set if result is overflowed to guard-bits. reset if not. mv: set if guard-bit is overflowed. unchanged if not. notes: * vmi denotes for vm0 or vm1 according to the current ma bank. examples: esub ma, p y0, @rp1+s1 esub ma, p a, @rp2+s0 esub ma, p @rp0+d0, b # of words: 1
mac2424 S3FB42F 25- 130 etst ? test format: etst cct operation: if ( cct is true) t ? 1 else t ? 0 this instruction sets the t flag of msr0 register to 1 if condition specified in cct field is evaluated to truth. else, resets the t flag. this instruction must be executed before executing the conditional instructions. flags: t: set/reset according to the condition notes: ? examples: etst gt etst neg # of words: 1
S3FB42F electrical data 26- 1 26 electrical data overview table 26-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 4.5 v input voltage v i ? ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current i oh one i/o pin active ? 15 ma high all i/o pins active ? 100 output current i ol one i/o pin active + 20 ma low total pin current for ports 1, 2, 3 + 150 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 26-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 3.6 v) parameter symbol conditions min typ max unit operating voltage v dd f osc = 30 mhz 3.0 ? 3.6 v input high voltage v ih0 reset 0.85 v dd ? v dd v v ih1 test, p2, p3, p4, p8, p9 0.8 v dd v ih2 all input pins except v ih0 ,v ih1 and v ih3 0.7 v dd v ih3 x in , xt in v dd ? 0.5 input low voltage v il1 test, reset , p2, p3, p4, p8, p9 0 ? 0.2 v dd v v il2 all input pins except v il1 and v il3 0.3 v dd
electrical data s3f b42f 26- 2 v il2 x in , xt in 0.4
S3FB42F electrical data 26- 3 table 26-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 3.0 v to 3.6 v) parameter symbol conditions min typ max unit output high voltage v oh1 v dd = 3.0 v to 3.6 v i oh = ? 1 ma v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 3.0 v to 3.6 v i ol = 5 ma all output pins ? ? 1.0 v input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 ua i lih2 v in = v dd x in , xt in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v x in , xt in , reset -20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 5 output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -5 pull-up resistor r l1 v in = 0 v; v dd = 3.3 v; t a =25 c all input pins except r l2 50 100 200 k w r l2 v in = 0 v; v dd = 3.3 v; t a =25 c reset only 100 250 400 supply current (1) i dd1 v dd = 3.3 v 30 mhz crystal oscillator ? 35 70 ma v dd = 3.3 v 32.768khz crystal 210 400 ua i dd2 idle mode: v dd = 3.3 v 30 mhz crystal oscillator ? 5 13 ma idle mode: v dd = 3.3 v 32.768khz crystal oscillator 15 30 ua i dd3 stop mode v dd = 3 v 10% ? 1 10 ua note: 1. supply current does not include current drawn through internal pull-up resistors or external output current loads.
electrical data s3f b42f 26- 4 table 26-3. a.c. electrical characteristics (t a = ?40 c to + 85 c, v dd = 3.0 v to 3.6 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl p4.0-p4.1, p5.0-p5.5 at v dd = 3.3 v 200 ? ? ns reset input low width t rsl v dd = 3.3 v 10 ? ? us note: user must keep a larger value than the min value. t inth t intl 0.8 v dd 0.2 v dd figure 26-1. input timing for external interrupts (port 4, port5) reset t rsl 0.2 v dd figure 26-2. input timing for reset reset table 26-4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 10 pf output capacitance c out
S3FB42F electrical data 26- 5 i/o capacitance c io table 26-5. a/d converter electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 3.6 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? ? ? 8 ? bit total accuracy ? v dd = 3.3 v conversion time = 5us ? ? 2 integral linearity error ile av ref = 3.3 v ? 1 differential linearity error dle av ss = 0 v ? 1 lsb offset error of top eot ? 1 2 offset error of bottom eob ? 0.5 2 conversion time (1) t con ? 20 ? ? us analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? mohm analog reference voltage av ref ? v dd ? v dd v analog ground av ss ? v ss ? v ss v analog input current i adin av ref = v dd = 3.3 v ? ? 10 ua analog block i adc av ref = v dd = 3.3 v 1 3 ma current (2) av ref = v dd = 3 v 0.5 1.5 ma notes : 1. 'conversion time' is the time required from the moment a conversion operation starts until it ends. 2. i adc is an operating current during a/d conversion. table 26-6. i 2 s master transmitter with data rate of 2.5 mhz (10%) (unit: ns) parameter min typ max condition clock period t 360 400 440 ttr = 360 clock high thc 160 ? ? min > 0.35t = 140 (at typical data rate) clock low tlc 160 ? ? min > 0.35t = 140 (at typical data rate) delay tdtr ? ? 300 max < 0.80t = 320 (at typical data rate) hold time thtr 100 ? ? min > 0 clock rise-time trc ? ? 60 max > 0.15t = 54 ( atrelevent in slave mode)
electrical data s3f b42f 26- 6 table 26-7. i 2 s slave receiver with data rate of 2.5 mhz (10%) (unit: ns) parameter min typ max condition clock period t 360 400 440 ttr = 360 clock high thc 110 ? ? min < 0.35t = 126 clock low tlc 110 ? ? min < 0.35t = 126 set-up time tsr 60 ? ? min < 0.20t = 72 hold time thtr 0 ? ? min < 0 table 26-8. flash memory d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 3.6 v, v pp = 12.5v) parameter symbol conditions min typ max unit logic power supply v dd ? 3.0 3.3 3.6 v power supply for programming flash cell v pp ? 12.25 12.5 12.75 v flash memory operating current fi dd1 v dd = 3.0 ? 3.6v during reading ? 20 40 ma (fi dd ) fi dd2 v dd = 3.0 ? 3.6v during programming ? 10 20 ma fi dd3 v dd = 3.0 ? 3.6v during erasing ? 10 20 ma table 26-9. flash memory a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 3.0 v to 3.6 v) parameter symbol conditions min typ max unit programming time (1) ftp v dd = 3.3 ? 3.6v 20 30 300 us chip erasing time (2) ftp1 ? ? 10 ms sector erasing time (3) ftp2 ? 2 ms data access time ft rs ? 50 ? ns number of writing /erasing fnwe ? ? 50,000 times notes: 1. the programming time is the time during which one word (32-bit) is programmed. 2. the chip erasing time is the time during which all 256k-byte block is erased. 3. the sector erasing time is the time during which all 512-byte block is erased.
S3FB42F electrical data 26- 7 table 26-10. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c, v dd = 3.0 v to 3.6v) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 2 ? 3.6 v data retention supply current i dddr v dddr = 2v ? ? 1 a note: supply current does not include a current which drawn through internal pull-up resistors or external output current loads. execution of stop instruction reset occur ~ ~ v dddr ~ ~ stop mode normal operating mode data retention mode t wait reset v dd note: t wait is the same as 2048 x 16 x 1/fxx oscillation stabilization time 0.2v dd figure 26-3. stop mode release timing when initiated by a reset reset
electrical data s3f b42f 26- 8 execution of stop instruction v dddr ~ ~ data retention v dd normal operating mode ~ ~ stop mode osc start up time t wait note: t wait is the same as 2048 x 16 x 1/fxx. the value of 2048 which is selected for the clock source of the basic timer counter can be changed. then the value of t wait will be changed. oscillation stabilization time 0.2v dd int figure 26-4. stop mode release timing when initiated by interrupts
S3FB42F electrical data 26- 9 table 26-11. synchronous sio electrical characteristics (t a = ? 40 c to + 85 c v dd = 3.0 v to 3.6 v, v ss = 0 v, fxx = 30 mhz oscillator ) parameter symbol conditions min typ max unit sck cycle time t cyc ? 200 ? ? ns serial clock high width t sckh ? 60 ? ? serial clock low width t sckl ? 60 ? ? serial output data delay time t od ? ? ? 50 serial input data setup time t id ? 40 ? ? serial input data hold time t ih ? 100 ? ? output data input data sck t sckh t cyc t sckl 0.8 v dd 0.2 v dd t od t id t ih 0.8 v dd 0.2 v dd si so figure 26-5. serial data transfer timing
electrical data s3f b42f 26- 10 table 26-12. main oscillator frequency (fosc1) (t a = ? 40 c to + 85 c v dd = 3.0 v to 3.6 v) oscillator clock circuit test condition min typ max unit crystal x in c1 c2 x out oscillation frequency 32 32.768 35 khz stabilization time ? 1 3 s external clock x in x out x in input frequency 32 ? 35 khz x in input high and low level width (t xh, t xl ) 14 ? 16 us note: oscillation stabilization time (t st1 ) is the time that the amplitude of a oscillator input rich to 0.8 v dd, after a power- on occurs, or when stop mode is ended by a reset or a interrupt signal.
S3FB42F electrical data 26- 11 table 26-13. sub oscillator frequency (fosc2) (t a = ? 40 c to + 85 c v dd = 3.0 v to 3.6 v) oscillator clock circuit test condition min typ max unit crystal x in c1 c2 x out crystal oscillation frequency ? ? 35 mhz stabilization time ? ? 10 ms ceramic x in c1 c2 x out ceramic oscillation frequency ? ? 35 mhz stabilization time ? ? 4 ms external clock x in x out x in input frequency ? ? 35 mhz x in input high and low level width (t xh , t xl ) 14 ? ? ns note: oscillation stabilization time (t st1 ) is the time that the amplitude of a oscillator input rich to 0.8 v dd , after a power- on occurs, or when stop mode is ended by a reset or a interrupt signal.
electrical data s3f b42f 26- 12 x in t xh t xl 1/fosc1 v dd - 0.1 v 0.1 v figure 26-6. clock timing measurement at x in
S3FB42F electrical data 26- 13 notes
S3FB42F mechanical data 27- 1 27 mechanical data overview the S3FB42F is available in a 100-qfp-1420c package and a 100-tqfp-1414 package. 100-qfp-1420c #100 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 0.15 + 0.10 - 0.05 0-8 0.10 max #1 0.65 note : dimensions are in millimeters. (0.58) 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 0.30 + 0.10 - 0.05 (0.83) 0.15 max 0.10 max figure 27-1. 100-qfp-1420c package dimensions
mechanical data s3f b42f 27- 2 100-tqfp-1414 #100 14.00 bsc 16.00 bsc 14.00 bsc 16.00 bsc 0.08 max 0.127 + 0.073 - 0.037 0-7 note : dimensions are in millimeters. #1 0.50 (1.00) 0.45-0.75 0.05-0.15 1.00 0.05 1.20 max 0.20 + 0.07 - 0.03 0.08 max figure 27-2. 100-tqfp-1414 package dimensions

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