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specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. o1012hkpc 20101028-s00001 no.a2131-1/27 ver.1.07 * i 2 c bus is a trademark of philips corporation. LC822973 overview this lsi is tv image viewer. a 16mbit sdram is built-in as image frame buffers, on which an external cpu is able to draw the images, then another part of this lsi displays the sdram images on tv in ntsc/pal after video data encoding. this lsi equips h/v scaling circuit to scal e up qvga size image to vga to display on the tv screen, for instance. the main features of this lsi are specified as below. features ? ntsc/pal video encoder is integrated. various format support itu-r601 (13.5mhz/ntsc&pal) sq (12.27mhz/ntsc, 14.75mhz/pal) ntsc-j, m/pal-b, d, g, h, i/pal-m, n various image adjustment y signal: brightness and contrast adjustment c signal:u gain, v gain, hue and burst amplitude adjustment trap filter trap filters locate on the y signal pass to reduce cross color interference. the trap strength is adjustable by register setup. built-in color bar this is for system test and level adjustment. 10 bit dac with 75 driver a high accuracy video dac of 10bit is built-in. its dac output is able to be connected to tv input or any image devices, thanks for its 75 driver built-in. ? it mounts 16mbit sdram to store multiple vga size imag es. since it has the arbitration function built-in, the access timing from cpu for drawing can be used without any care of real-time access condition for tv display. vga 30fps performance can be achieved with appropriate setting of system clock, the burst size of sdram, scaling ratio etc. continued to the next page. ordering number : ena2131 cmos lsi tv image viewer lsi
LC822973 no.a2131-2/27 continued from the previous page. ? the osd function is installed. osd images consist of binary pixel data to display over the original image. the alfa-blend display is also available. ? scaling from 1 up to 4 in two independent directions, horizont ally and vertically, is available. 256 step arbitrary enlargement is given by register settin gs. the image rotation is available when writing as well. ? the high-speed clock for sdram is generated internally by built-in pll. ? cpu-if with 8/9/16/18/24 bit width data transfer is available. ? built-in video-if supports receiving video rate image input with hsync/vs ync/dotclcok signals. it accepts various digital image formats of 18bit- rgb666, 16bit-rgb565, 16b it-yuv422, 8b it-yuv422, 8bit-yuv422 (bt656) and so on. in addition, it accepts both interlace and non-interlace format. ? the autoview function executes automatic writing/reading sequence. once all the relevant commands are set, then this function properly updates the image banks to write and to read. this bank arbitration avoids well the tearing image (reading outruns writing). ? the filckerfreefilter effectively decr eases the line flicker, a substantia l phenomena of the interlace method. ? high performance c-signal band-limit filter is bu ilt-in. the thorny ?dot cr awl? is thus decreased. ? cgms-a/wss data multiple functions are built-in. ? the i/o voltage of the cpu/vi deo interface is 1.6v-3.4v. ? macrovision? encoding (revision 7.1.l1 in ntsc and pal standards for composite video output applications) are built-in. (LC822973-04vm-e only)* * this device is protected by u.s. patents 5, 583, 936; 6, 516, 132; 6, 836, 549; and 7, 050, 698; and other intellectual property rights. the use of macrovision's copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassemb ly is prohibited. this device can only be sold or distributed to authorized buyers. dc characteristics/ac characteristics absolute maximum ratings at dv ss = 0v parameter symbol conditions ratings unit dv dd 15 max -0.3 to 1.8 v supply voltage dv dd io max -0.3 to 3.96 v input voltage v i io -0.3 to 3.96 *1 v output voltage v o io -0.3 to dv dd io+0.3 v operation surrounding temperature topg -30 to 85 c storage temperature tstg -55 to 125 c hand soldering for 3 seconds 350 c soldering temperature reflow for 10 seconds 255 c i i 15, i o 15 ma in/out current i i io, i o io 20 *2 * 1 input voltage of i/o basic cell in case of without p-ch protection diode. * 2 per 1 cell of i/o basic cell permissible operation range at ta = -30 to 85 c, dv ss = 0v parameter symbol conditions min typ max unit dv dd 15 1.35 1.5 1.65 v dv dd io *3 2.5 3.0 3.4 v dv dd io *4 1.6 1.8 2.0 v dv dd 3 2.7 3.0 3.4 v av dd 3 2.7 3.0 3.4 v supply voltage av dd 15 1.35 1.5 1.65 v input range v in io 0 dv dd io v * 3 at supply = 3.0v (typical) * 4 at supply = 1.8v (typical)
LC822973 no.a2131-3/27 i/o pin capacity at v dd 3 = dv dd io = v i 15 = v i io = dv ss = 0v, ta = -30 to 85 c parameter symbol conditions min typ max unit input pin c in f = 1mhz 10 pf output pin c out 10 pf i/o pin c i/o 10 pf dc characteristics i/o level / v ss = 0v, dv dd io = 2.5 to 3.4v, ta = -30 to 85 c parameter symbol conditions applied pin *5 min typ max unit h v ih io 2.0 v l v il io cmos (1) (2) 0.3dv dd io v h v ih io 2.0 v input level l v il io cmos schmit (3) 0.3dv dd io v h v oh io i oh = -4ma dv dd io-0.4 v l v ol io i ol = 4ma (2) (4) 0.4 v h v output level l v ol io i ol = 4ma (5) 0.4 v input leak current i il v i = dv dd 3, dv ss (1) (2) (3) -10 +10 a output leak current i oz high impedance (4) (5) -10 +10 a * 5 the applied pins correspond to the following names. i/o level / v ss = 0v, dv dd io = 1.6 to 2.0v, ta = -30 to 85 c parameter symbol conditions applied pin *6 min typ max unit h v ih io 0.7dv dd io v l v il io cmos (1) (2) 0.25dv dd io v h v ih io 0.75dv dd io v input level l v il io cmos schmit (3) 0.2dv dd io v h v oh io i oh = -4ma dv dd io-0.4 v l v ol io i ol = 4ma (2) (4) 0.4 v h v output level l v ol io i ol = 4ma (5) 0.4 v input leak current i il v i = dv dd 3, dv ss (1) (2) (3) -10 +10 a output leak current i oz high impedance (4) (5) -10 +10 a * 6 the applied pins correspond to the following names. (input) (1) ... cki, a0, cs, conf3-conf0, mode2-mode0 (2) ... d15-d0, db17, db16 (3) ... xrst, cs, rd, wr, scl, sda (output) (2) ... d15-d0 (4) ... int, mon (5) ... sda (open drain)
LC822973 no.a2131-4/27 dac characteristics the characteristics of dac (10bitdac) for vide o that features this lsi are illustrated. zero scale output voltage within 0v 15mv full scale output voltage within 1.00v 80mv maximum conversion speed 30mhz linear line error within 4lsb (vqfn84 [-10b] : within 4.5lsb) differential linear line error within 1lsb voltage reference level 1.20 20mv (ta = +25 c) current consumption * at the time of dv dd 3 = dv dd io = 3v and dv dd 15 = 1.5v and av dd 3 = 3v and av dd 15 = 1.5v and mclk50mhz * at the time of still picture (640 480) + osd1 all screens + osd2 all screens parameter min typ max unit av dd 15 (pll operation current) 0.5 1 ma dv dd 15 (core operation current) 10 15 ma av dd 3 (dac operation current)* 35 35 ma dv dd io (io operation current) 2 5 ma dv dd 3 (sdram operation current) 8 13 ma standby current (clock input on) 300 a standby current (input clock off)** 100 a standby current (input clock off + sdram/sram off)** 6 18 a * ?typ? here implies only that dacout always outputs its maximum current. ** under the condition of tying input pin levels to h or l. standby current is at the cond ition of room temperature (+25 c)
LC822973 no.a2131-5/27 package dimensions unit : mm (typ) 3442 package dimensions unit : mm (typ) 3443 sanyo : isb63(4.0x5.0) 1234 567 jhgfe dcba 5.0 0.5 0.5 0.5 0.5 4.0 0.23 1.2 max 0.28 side view side view top view bottom view sanyo : vqfn84(10x10) 0.6 0 .22 10.2 10.0 10.2 10.0 0.6 (5.27) (5.00) top view side view side view bottom view 0.95 max 0.02 0.18 0.4 (1.0) 1 2 84
LC822973 no.a2131-6/27 structure outline specification item outline ntsc/pal video encoder multi rate and mu lti format video encoder that supports nt sc/pal and itu-601/sq (square pixel). dac 10bit-1chd/a converter that integrates 7 driver. can be connected to tv directly without op-amp or buffer. cpu i/f support 8/9/16/18/24bit bus (d, wr, rd, cs, a0) of i80 type. video i/f it corresponds to 5 format of rgb565, rgb666, yuv422 (8bit), yuv422 (8bit_bt656mode), and yuv422 (16bit). the writing operation is executed based on sync signals. memory controller controls built-in (mcp ) 16mbitsdram. owns arbitration functi on and cpu access (drawing) is possible as needed. matrix (cpu i/f) performs rgb yuv conversion at the time of cpu memory writing. matrix (video i/f) performs rgb yuv conversion at the time of video port memory writing. pll generates high-speed clock for sdram. osd a reading binary image from sdram is displayed in tv . because the alfa blend function is installed, it is possible to select four st ages by blend register. scaling function 4 scaling processing at maximum is ex ecuted for reading image from sdram. can be set to h and v direction independently. autoview function the issue of the command of each screen is unnecessary. writing/ reading control in the image area (two bank or3 bank) set beforehand is executed automatically. v-blanking period. can insert cgms-a/wss code into v-blanking period. i/o cmos interface operation temperature -30 c to 85 c package isb63 4mm 5mm vqfn84 10mm 10mm power voltage (io) dv dd io (1.6v - 3.4v) for ex. : 1.8v (1.6v - 2.0v), 3.0v (2.5v - 3.4v) power voltage (digital core) 1.5v (1.35v - 1.65v) power voltage (pll) 1.5v (1.35v - 1.65v) power voltage (for stacked sdram) 3.0v (2.7v - 3.4v) power voltage (dac analog part) 3.0v (2.7v - 3.4v)
LC822973 no.a2131-7/27 structure block sdram controller video i/f conf auto view control 16mbitsdram(mcp) (6)videoif block sclk bt656dec. mtx sel register i 2 c cpu i/f linemem linemem osd1 128w 16 2 linemem linemem linemem linemem 128w 16 2 linemem linemem 768w 16 2 linemem linemem 768w 16 768w 16 cgms-a wss (8)vbi control block sclk mclk (3)dram control block copy control pll 1/m 1/n 1/2 osd2 sel sel phase comp sel mtx on/off (2)host access block (1)cpuif block cpui/f 1.8v ? ? ? ? 3.3v wide range i/o dram write timing gen. back ground display window gen. dac with 75 driver 768w 16 2 through(vga) scaling process (4)display access block (7)autoview control block (5)video encoder block video timing gen. iref vref vclk 1 (13.5mhz,12.27mhz) vclk 2 (27mhz,24.54mhz) comp icb dacout conf0 conf1 conf2 cki mode xrst d 16 4 db16 db17 rd wr a cs mon int sda scl conf3 vifhact vifvact vifdot viffi vifvs vifhs tv memory controller ntsc video encoder h/v scaler filter ntsc/pal video encoder
LC822973 no.a2131-8/27 this lsi consists of 9 function blocks in the structure block above. (1) cpu interface (cpuif block) the parameter setup such as mode setup/image area setup/video encoder characteristic of this lsi is possible via bus from cpu. the image data writing to sdram achieves image port writing command that is in the same command class as regular register and the same command cl ass and keep writing continuously. this is a double bank buffer structure and is able to write drawing data for 1 line without wait control. (2) host access (host access block) the image writing is fulfilled from cpu interface for sdram. this obtains line buffer in double bank buffer and the writi ng is carried out to sdram as accessing from cpu. it also mounts 90, 180, 270 degrees rotation writing and writin g function with matrix conversion processing besides regular writing. (3) sdram control (dram control block) this lsi is mcp (multi chip) structure and has 16mbit sdram built-in. this is the memory controller that controls writing from cpu, reading for real-time display to vide o encoder and refresh processing for this memory. (4) reading control for display (display access block) this is the sdram reading processing part that controls transferring real-time imag e data to ntsc/pal video encoder. this consists of scaling part that performs enlargement processing for image data that was read from sdram and the buffer controlling part that provides video signal continuously to video encoder. the background processing circuit that inserts fixed level is m ounted in the buffer control part beside s display window (image from sdram). (5) video encoder (video encoder block) this supports both ntsc/pal methods. all timing signals th at are necessary for video signal are generated in this block. this operates as a sync master and generates tran sfer request of real-time im age data for di splay access block. (6) video interface (videoif block) it is an interface part for the video rate writing. it writes based on a video sync signal and the dot clock. in case of rgb format (rgb565, rgb666 etc.), th e image is input to the host access part by processing the matrix at valid period. the bt656 decoding is done if necessary at th e yuv format. it supports bo th non-interlace and interlace format. when the video interface is used , the data bus (d15 - d0) is treated as a dedicated image bus. the command issue and the register acces s are executed with the i 2 c bus. it has the i 2 c bus control part in cpu interface part. (7) automatic image viewing (autoview control block) automatic writing/reading sequence is executed by altern ating the pre-defined image banks. thus clean images without the scan passing (tearing imag e) are displayed. consecutive image da ta transfer follows after one time command and parameter setting. (8) vbi control (vbi control block) the cgms-a/wss data is inserted. it has aux function for the copy protect control etc. (9) others to combine drawing from cpu and real-time request (continuous video signal is provided to ntsc/pal video encoder), sdram needs to be operated with high-speed clock. the high-speed master clock (mclk) is created and supported by using pll for input clock (cki).
LC822973 no.a2131-9/27 general operation [operation 1.] the rotation processing is performed at the time of sdram wr iting. as a result, a vertically long image of small size such as qqvga, qvga, etc. is rota ted 90 degrees and it is possible to display on tv (vga size image). qqvga-qvga cpu i/f sdram ntsc encoder vga [operation 2.] the enlargement processing can be realized by filter processing that utilized line memory for reading data from sdram. the small size image such as qqvga and qvga can be displayed on tv screen fully (vga size). an enlargement ratio can be set optionally (2 (n+1)/256, n: 128 to 255). if the displayed image after enlargement is smaller than vga size, other than target image can be set to background leve l (brightness/color setup possible). this operation can be combined with the above rotation function. qqvga-qvga cpu i/f sdram ntsc encoder enlarge- ment circuit vga [operation 3.] the enlargement processing can be bypassed if writing imag e size from cpu fits vga image size exactly. degradation of broad area level due to filter processing can be prevented. vga cpu i/f sdram ntsc encoder vga [moving image processing] this lsi is the system that supports moving image that made writing from cpu and competitive operation of tv display (real-time reading from sdram) possible by using high-speed clock operation. the moving image performance (supportable frame rate) improves by raising sdram clock frequency through pll setup. however, the current consumption increases significantly.
LC822973 no.a2131-10/27 corresponding video format the video format that ntsc/pal video encoder corresponds is described in the following tables. ((ntsc)) mode itu-601 sq dot clock 13.500mhz 12.2727mhz dot/line 858 780 horizontal valid period 720 640 vertical cycle 525 lines/frames vertical frequency 59.94hz (field) vertical blanking period 21 lines (line1-line21, line263-line284) burst mask period 9 lines (line1-line9, line264-line272) ((pal)) mode itu-601 sq dot clock 13.500mhz 14.750mhz dot/ line 864 944 horizontal valid period 720 768 vertical cycle 625 lines/frames vertical frequency 50hz (field) vertical blanking period 25 lines (line623-line22, line311-line335) burst mask period 9 lines (line623-line6, line310-line318) *the video encoder is the component signal processing for y and c of 8 bit each as an internal processing. the dot clock in the table above corresponds to the sampling clock at the time of 16bit processing of y+c. to simplify post filter, the video encoder processing performs 2 oversampling. therefore, the operation clock in video encoder part is double of dot clock (27mhz, 24.54mhz, 29.5mhz, etc.).
LC822973 no.a2131-11/27 analog pll pin description pin name pol. dir description of function at reset pin cki - i master clock - 1 xrst l i master reset, low active - 1 db17 - i (bit17) extended bit. use at 18bit mode. - 1 db16 - i (bit16) extended bit. use at 18bit mode - 1 d[15:0]/ vifvd[15:0] - i/o data bus, needs pull-up resistance externally (unnecessary if either device always drives bus). this bus is sharing for the videoif. - 16 a0/ (idsel) - i address/ (idsel at videoif). - 1 rd/ (vifvs) l i read pulse/ (vsync in at videoif). - 1 wr/ (vifhs) l i write pulse/ (hsync in at videoif). - 1 cs/ (viffi) l i chip select/ (field index in at videoif). - 1 int l o interrupt "0" 1 mon h o monitor "0" 1 usevif h i set "h" in case of videoif mode. the command issue is via i 2 c bus. - 1 sda - i/o sda for i 2 c bus. - 1 scl - i scl for i 2 c bus. - 1 dacout ana o dac output - 1 iob ana o dac_iob pin - 1 comp ana o dac_comp pin - 1 vref ana o dac_vref pin - 1 iref ana o dac_iref pin - 1 vcnt ana i vcnt pin - 1 mode[2:0] - i for test * - 3 conf3 - i to decide input format - 1 conf2 / (vifdot) - i to decide input format / (dotclock in at videoif) - 1 conf1 / (vifvact) - i to decide input format / (v-valid period flag in at videoif) - 1 conf0 / (vifhact) - i to decide input format / (h-valid period flag in at videoif) - 1 dv dd 15 pow - dv dd for digital core (1.5v part) - 4 (6) dv dd io pow - dv dd for digital i/o part - 4 (7) dv dd 3 pow - dv dd for stacked sdram (it's controlled by internal switch cell) - 3 (4) av dd 3 pow - av dd for dac analog (analog 3v) - 1 av dd 15 pow - av dd for pll analog (analog 1.5v) - 1 dv ss pow - gnd for digital part - 6 (13) av ss pow - gnd for analog part - 2 total 63 (76) * mode pins are for testing. they should be fixed to "l" normally. analog dac
LC822973 no.a2131-12/27 pin assignment (isb63/ vqfn84/[sqfp100] ) ball [isb] pin [vqfn] reference [sqfp] pin name i/o application - - 1 nc - - - 2 nc - h5 1 3 dv ss p digital gnd g6 2 4 sda b i 2 c data / maintain open at cpuif mode h7 3 5 scl i i 2 c clock / connect to gnd at cpuif mode. f4 4 6 dv dd 15 p v dd (digital core) f6 5 7 conf3 i for format setting at cpuif (bit3). connect to gnd at videoif mode. g7 6 8 conf2/ (vifdot) i for format setting at cpuif (bit2). / dotclock in at videoif mode. f5 7 9 conf1/ (vifvact) i for format setting at cpuif (bit1). / v-valid flag in at videoif mode. f7 8 10 conf0/ (vifhact) i for format setting at cpuif (bit0). / h-valid flag in at videoif mode. e2 9 11 dv dd 3 p v dd (for stacked sdram) h5 10 12 dv ss p digital gnd e7 11 13 cki i system clock input e6 12 14 dv dd io p v dd (digital io) e4 13 15 xrst i system reset ("l"==reset) d7 14 16 int o int signal ("l"==interrupt generation) e5 15 17 mon o monitor pin. h5 16 18 dv ss p digital gnd c7 17 19 a0/ (idsel) i address/id address select at videoif mode. (0 : 8'b0100_000_r, 1 : 8'b0100_001_r). d6 18 20 cs/ (viffi) i /cs signal/field index at videoif mode. b7 19 21 dv dd 15 p v dd (digital core) h5 20 22 dv ss p digital gnd - - 23 nc - - - | | - - - 27 nc - c6 21 28 db17 i bit17 for 18bit data transfer format. a7 22 29 db16 i bit16 for 17bit data transfer format. e6 23 30 dv dd io p v dd (digital io) b6 24 31 d15/ (vifvd15) b cpu data bus/video data bus. (msb) a6 25 32 d14/ (vifvd14) b | c5 26 33 d13/ (vifvd13) b | b5 27 34 d12/ (vifvd12) b | a5 28 35 d11/ (vifvd11) b | d5 29 36 d10/ (vifvd10) b | d4 30 37 d9/ (vifvd9) b | a4 31 38 d8/ (vifvd8) b | b4 32 39 d7/ (vifvd7) b | c4 33 40 wr/ (vifhs) i /wr pulse/hsync at videoif mode. a3 34 41 rd/ (vifvs) i /rd pul se/vsync at videoif mode. e3 35 42 dv dd 15 p v dd (digital core) b3 36 43 dv ss p digital gnd a2 37 44 dv dd io p v dd (digital io) c3 38 45 d6/ (vifvd6) b cpu data bus/video data bus. d3 39 46 d5/ (vifvd5) b | b2 40 47 d4/ (vifvd4) b | a1 41 48 d3/ (vifvd3) b | c2 42 49 d2/ (vifvd2) b cpu data bus/video data bus. * the product version are isb63 and vqfn84. sqfp100 is a package for our evaluation (reliability test). continued to the next page.
LC822973 no.a2131-13/27 continued from the previous page. ball [isb] pin [vqfn] reference [sqfp] pin name i/o application - - 50 nc - - - | | - - 43 54 nc - - 44 55 nc - d2 45 56 dv ss p digital gnd b1 46 57 d1/ (vifvd1) b cpu data bus/video data bus. c1 47 58 d0/ (vifvd0) b cpu data bus/video data bus. (lsb) e3 48 59 dv dd 15 p v dd (digital core) f1 49 60 dv dd io p v dd (digital io) d1 50 61 dv ss p digital gnd e1 51 62 dv dd 3 p v dd (for stacked sdram) d1 52 63 dv ss p digital gnd d1 53 64 dv ss p digital gnd f1 54 65 dv dd io p v dd (digital io) f2 55 66 dv ss p digital gnd g1 56 67 dv dd 3 p v dd (for stacked sdram) g2 57 68 dv ss p digital gnd h1 58 69 dv dd 15 p v dd (digital core) g1 59 70 dv dd 3 p v dd (for stacked sdram) f2 60 71 dv ss p digital gnd - - 72 nc - - - | | - - 61 76 nc - - 62 77 nc - - 63 78 nc - - 64 79 nc - j1 65 80 av dd 3 p av dd (dac analog : 3v part) 66 av dd 3 p av dd (dac analog : 3v part) h2 67 81 av ss 1 p gnd (analog for dac) g3 68 82 vref ana dac_vref pin j2 69 83 comp ana dac_comp pin h3 70 84 iref ana dac_iref pin f3 71 85 iob ana dac_iob pin j3 72 86 dacout ana dac_ video output f1 73 87 dv dd io p v dd (digital io) j4 74 88 mode2 i mode setting (bit2), should be fixed "l" h4 75 89 mode1 i mode setting (bit1), should be fixed "l" g4 76 90 mode0 i mode setting (bit0), should be fixed "l" j5 77 91 usevif i to use videoi f mode ("h":select videoif) f4 78 92 dv dd 15 p v dd (digital core) h5 79 93 dv ss p digital gnd j6 80 94 av dd 15 p av dd (pll analog : 1.5v part) g5 81 95 av ss 2 p gnd(pll analog) h6 82 96 vcnt ana vcnt pin for pll j7 83 97 dv dd io p v dd (digital io) - 84 98 nc - - - 99 nc - - - 100 nc - * the product version are isb63 and vqfn84. sqfp100 is a package for our evaluation (reliability test).
LC822973 no.a2131-14/27 pin layout (isb63) a d3 dv ddio rd d8 d11 d14 db16 b d1 d4 dv ss d7 d12 d15 dv dd 15 c d0 d2 d6 wr d13 db17 a0 d dv ss dv ss d5 d9 d10 cs int e dv dd 3 dv dd 3 dv dd 15 xrst mon dv dd io cki f dv dd io dv ss iob dv dd 15 conf1 conf3 conf0 g dv dd 3 dv ss vref mode0 av ss 2 sda conf2 h dv dd 15 av ss 1 iref mode1 dv ss vcnt scl j av dd 3 comp dacout mode2 usevif av dd 15 dv dd io 1 2 3 4 5 6 7 top view a1 marking
LC822973 no.a2131-15/27 peripheral circuit example system reset setting osc use at 18bit mode. video i/f i 2 c needed pullup idsel(choose id) sda scl vifhact vifvact vifdot vifvs vifhs viffi vifvd a0 sda scl int mon mode2-0 cki xrst conf0 conf1 conf2 conf3 rd wr cs d15-0 db16 db17 monitor pin 39 75 100 f--220 f dac analog dacout iob comp vref iref vcnt pll analog cvbs recommendation: 220 f 1 f av dd av ss 0.1 f 560 3.3 h 330pf an example of lpf "av ss " l lpf 330pf "av ss " 100--150 0.1 f--0.22 f LC822973 LC822973 via cpuif via videoif 39 75 100 f--220 f dac analog dacout iob comp vref iref vcnt pll analog cvbs recommendation: 220 f 1 f av dd av ss 0.1 f 560 3.3 h 330pf an example of lpf "av ss " l lpf 330pf "av ss " 100--150 0.1 f--0.22 f system reset osc use at 18bit mode. cpu i/f setting "0"-command monitor pin open scl mode2-0 conf3-0 cki xrst sda mon int rd wr cs a0 d15-0 db16 db17 * the mode2:0 pins are for test use, so please tie them "l". * please do not leave input pins open. * above figure shows in case of 27mhz (24.54mhz) clock input. when the dot clock is generated with pll (.e.g.: cki== 26mhz), it is necessary to change in pll loop filter's constant. please refer to " 7.12. consideration of 26.0mhz clock input" paragraph for details.
LC822973 no.a2131-16/27 writing image format (via cpu i/f) the hardware adopts 24/18/16/9/8bit rgb format and yuv 422 format of 24/18/16/9/8 as a cpu writing via cpu-i/f. input format is determined by conf[3:0] pins. the rgb yuv matrix processing operates automa tically when rgb input is formatted. conf[3:0] 0 1 2 3 4 5 6 7 8 data rgb565 yuv422 rgb666 rgb565 transfer format 16bit ( 1) 16bit ( 1) 18bit ( 1) 18bit ( 2) 18bit ( 2) 18bit ( 2) 18bit ( 2) 16bit ( 2) 16bit ( 2) trans num 1 1 2 1 1 2 1 1 2 2 1 2 1 2 1 2 db17 17 - - - r5 - - - - - - - - - - - - db16 16 - - - r4 - - - - - - - - - - - - d[15] 15 r5 ya7 yb7 r3 r5 b1 r5 r3 r5 g2 - - r5 g2 - - d[14] 14 r4 ya6 yb6 r2 r4 b0 r4 r2 r4 g1 - - r4 g1 - - d[13] 13 r3 ya5 yb5 r1 r3 - - r1 r3 g0 - - r3 g0 - - d[12] 12 r2 ya4 yb4 r0 r2 - - r0 r2 b5 - - r2 b5 - - d[11] 11 r1 ya3 yb3 g5 r1 - - g5 r1 b4 - - r1 b4 - - d[10] 10 g5 ya2 yb2 g4 r0 - - g4 r0 b3 - - g5 b3 - - d[9] 9 g4 ya1 yb1 g3 g5 - - g3 g5 b2 - - g4 b2 - - d[8] 8 g3 ya0 yb0 g2 g4 - - g2 g4 b1 r5 g2 g3 b1 - - d[7] 7 g2 u7 v7 g1 g3 - - g1 g3 b0 r4 g1 - - r5 g2 d[6] 6 g1 u6 v6 g0 g2 - - g0 - - r3 g0 - - r4 g1 d[5] 5 g0 u5 v5 b5 g1 - - b5 - - r2 b5 - - r3 g0 d[4] 4 b5 u4 v4 b4 g0 - - b4 - - r1 b4 - - r2 b5 d[3] 3 b4 u3 v3 b3 b5 - - b3 - - r0 b3 - - r1 b4 d[2] 2 b3 u2 v2 b2 b4 - - b2 - - g5 b2 - - g5 b3 d[1] 1 b2 u1 v1 b1 b3 - - b1 - - g4 b1 - - g4 b2 d[0] 0 b1 u0 v0 b0 b2 - - b0 - - g3 b0 - - g3 b1 for conf==2:rgb666_18bit mode, r5 and r4 correspond db17 and db16 pins, respectively. otherwise, please connect db17, 16 pins to gnd. conf[3:0] 9 10 11 12 13 14 15 data rgb888 rgb666 rgb888 transfer format 24bit ( 2) 24bit ( 2) 18bit ( 3) 18bit ( 3) 24bit ( 3) 24bit ( 3) 24bit ( 3) trans num 1 2 1 2 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 db17 17 - - - - - - - - - - - - - - - - - - - db16 16 - - - - - - - - - - - - - - - - - - - d[15] 15 r7 b7 r7 g7 r5 g5 b5 - - - ra7 ba7 gb7 ra7 ga7 ba7 - - - d[14] 14 r6 b6 r6 g6 r4 g4 b4 - - - ra6 ba6 gb6 ra6 ga6 ba6 - - - d[13] 13 r5 b5 r5 g5 r3 g3 b3 - - - ra5 ba5 gb5 ra5 ga5 ba5 - - - d[12] 12 r4 b4 r4 g4 r2 g2 b2 - - - ra4 ba4 gb4 ra4 ga4 ba4 - - - d[11] 11 r3 b3 r3 g3 r1 g1 b1 - - - ra3 ba3 gb3 ra3 ga3 ba3 - - - d[10] 10 r2 b2 r2 g2 r0 g0 b0 - - - ra2 ba2 gb2 ra2 ga2 ba2 - - - d[9] 9 r1 b1 r1 g1 - - - - - - ra1 ba1 gb1 ra1 ga1 ba1 - - - d[8] 8 r0 b0 r0 g0 - - - - - - ra0 ba0 gb0 ra0 ga0 ba0 - - - d[7] 7 g7 - - b7 - - - - - - ga7 rb7 bb7 rb7 gb7 bb7 r7 g7 b7 d[6] 6 g6 - - b6 - - - - - - ga6 rb6 bb6 rb6 gb6 bb6 r6 g6 b6 d[5] 5 g5 - - b5 - - - r5 g5 b5 ga5 rb5 bb5 rb5 gb5 bb5 r5 g5 b5 d[4] 4 g4 - - b4 - - - r4 g4 b4 ga4 rb4 bb4 rb4 gb4 bb4 r4 g4 b4 d[3] 3 g3 - - b3 - - - r3 g3 b3 ga3 rb3 bb3 rb3 gb3 bb3 r3 g3 b3 d[2] 2 g2 - - b2 - - - r2 g2 b2 ga2 rb2 bb2 r2 gb2 bb2 r2 g2 b2 d[1] 1 g1 - - b1 - - - r1 g1 b1 ga1 rb1 bb1 rb1 gb1 bb1 r1 g1 b1 d[0] 0 g0 - - b0 - - - r0 g0 b0 ga0 rb0 bb0 rb0 gb0 bb0 r0 g0 b0 * 16bit or 8bit command area is to be sent within heavy-lined area. conf==5, 6, 7, 8, 11, 12, and 15 correspond 8bit command data, and the 16bit parameter register needs double transfer. * hatched area shows unused pins. "l" level is always output, so please keep them open. * for conf==14:24bit ( 3) format, a dummy write of 0 0 data is required every time af ter sending all the frame data. * for conf==1:16bit-yuv422 format, rgb to yuv matrix conversion can be enabled by register setting, sysctl1 (bit5) mtxon, which is useful for the mixed format system of rgb565 and yuv422.
LC822973 no.a2131-17/27 writing image format (via video i/f) writing from video if corresponds to various entry format s such as yuv422 (8bit), yuv422 (8bitbt656decode), yuv422 (16bit), rgb565 (16bit), and rgb666 (18bit). when video if is used, the usevif pin is set to "h". th e viffmt register is set and a necessary input format is decided at the same time. in this ls i, internal processing is yuv system. the rgb yuv matrix processing operates automatically when rgb is input. usevif 1 viffmt[3:0] 0 1 2 3 4 5 6 data format yuv422 rgb565 yuv422 rgb565 rgb666 bt656decode no yes no transfer format 16bit ( 2) 16bit ( 2) 16bit ( 2) 16bit ( 2) 16bit ( 1) 16bit ( 1) 18bit ( 1) trans num 1 2 1 2 1 2 1 2 1 1 1 db17 17 - - - - - - - - - - r5 db16 16 - - - - - - - - - - r4 d15/vifvd15 15 - - - - - - - - y7 r5 r3 d14/vifvd14 14 - - - - - - - - y6 r4 r2 d13/vifvd13 13 - - - - - - - - y5 r3 r1 d12/vifvd12 12 - - - - - - - - y4 r2 r0 d11/vifvd11 11 - - - - - - - - y3 r1 g5 d10/vifvd10 10 - - - - - - - - y2 g5 g4 d9/vifvd9 9 - - - - - - - - y1 g4 g3 d8/vifvd8 8 - - - - - - - - y0 g3 g2 d7/vifvd7 7 u7/v7 y7 u7/v7 y7 r5 g2 g2 r5 u7/v7 g2 g1 d6/vifvd6 6 u6/v6 y6 u6/v6 y6 r4 g1 g1 r4 u6/v6 g1 g0 d5/vifvd5 5 u5/v5 y5 u5/v5 y5 r3 g0 g0 r3 u5/v5 g0 b5 d4/vifvd4 4 u4/v4 y4 u4/v4 y4 r2 b5 b5 r2 u4/v4 b5 b4 d3/vifvd3 3 u3/v3 y3 u3/v3 y3 r1 b4 b4 r1 u3/v3 b4 b3 d2/vifvd2 2 u2/v2 y2 u2/v2 y2 g5 b3 b3 g5 u2/v2 b3 b2 d1/vifvd1 1 u1/v1 y1 u1/v1 y1 g4 b2 b2 g4 u1/v1 b2 b1 d0/vifvd0 0 u0/v0 y0 u0/v0 y0 g3 b1 b1 g3 u0/v0 b1 b0 usevif 1 viffmt[3:0] 7 8 9 10 data format rgb666 rgb888 bt656decode no transfer format 18bit ( 2) 18bit ( 2) 18bit ( 3) 24bit ( 3) trans num 1 2 1 2 1 2 3 1 2 3 db17 17 - - - - - - - - - - db16 16 - - - - - - - - - - d15/vifvd15 15 r5 b1 r5 r3 - - - - - - d14/vifvd14 14 r4 b0 r4 r2 - - - - - - d13/vifvd13 13 r3 - - r1 - - - - - - d12/vifvd12 12 r2 - - r0 - - - - - - d11/vifvd11 11 r1 - - g5 - - - - - - d10/vifvd10 10 r0 - - g4 - - - - - - d9/vifvd9 9 g5 - - g3 - - - - - - d8/vifvd8 8 g4 - - g2 - - - - - - d7/vifvd7 7 g3 - - g1 - - - r7 g7 b7 d6/vifvd6 6 g2 - - g0 - - - r6 g6 b6 d5/vifvd5 5 g1 - - b5 r5 g5 b5 r5 g5 b5 d4/vifvd4 4 g0 - - b4 r4 g4 b4 r4 g4 b4 d3/vifvd3 3 b5 - - b3 r3 g3 b3 r3 g3 b3 d2/vifvd2 2 b4 - - b2 r2 g2 b2 r2 g2 b2 d1/vifvd1 1 b3 - - b1 r1 g1 b1 r1 g1 b1 d0/vifvd0 0 b2 - - b0 r0 g0 b0 r0 g0 b0 * the width of the bus at video if is decided by the register setting. (usevif=="h"). all the image ports are set to the input at video if. please connect an unused bit with gnd (it shows "-" in the table).
LC822973 no.a2131-18/27 command command type/register map there are two types of command. one is to be able to operate by a command itself and the other needs a parameter. in case of writing a command, a0 should be set to 0 and a0 sh ould be set to 1 in case of writing or reading a parameter. if other command is executed before setting a parameter, the command that is in the middle of setting is cancelled. other than 9bit interface how to set command ? command that doesn?t need a parameter ? a[0] 0 d[15:0] command command is valid command setting ? command that needs a parameter ? a[0] 0 d[15:0] command command setting 1 parameter command is valid parameter setting 8bit/9bit interface how to set command ? command that doesn?t need a parameter ? a[0] 0 d[7:0] command command setting 1 parameter command is valid parameter setting ? command that needs a parameter ? command is valid a[0] 0 d[7:0] command command setting a[0] 1 d[15:8] parameter parameter setting a[0] 1 d[7:0] parameter parameter setting * 9bit transfer conf="5", 8bit transfer conf="7"/conf="11" : data bus[15:8] should be used. * 9bit transfer conf="6", 8bit transf er conf="8"/conf="12"/conf="15" : data bus[7:0] should be used.
LC822973 no.a2131-19/27 i 2 c access when video i/f is used (usevif==1), the register access from the host uses the i 2 c bus. one sending data size of the i 2 c bus is 8bit. additionally, i 2 c is not applicable the concept of the address (a 0==0: the command and a0==1: parameter) used with parallel cpuif. therefore, a special access way is n ecessary as follows respectively. stand-alone command : not need parameter--imgwrite,imgreadgo etc.) write "00" into the target address target address+"00" (normal write : need 1word parameter) write sequentially "upper byte" "lower byte" into target address. address is "upper : normal address 2" , "lower : normal address 2+1" in case of i 2 c. target address(upper)+"writing data for upper byte" target address(lower)+"writing data for lower byte" *please keep the order "upper byte lower byte". when the host accessing is finished, intern al transfer w ith word align will start. (normal read : need 1word parameter) read sequentially "upper byte" "lower byte" from target address. address is "upper : normal address 2" , "lower : normal address 2+1" in case of i 2 c. target address(upper)+"reading data for upper byte" target address(lower)+"reading data for lower byte" the read order from upper byte or lower byte doesn't especially have regulations. only one byte accessing is also possible. (image writing command : aut oviewon,imgwrite,osdwrite etc.) write via special imag e port (imgport : 0 fd). after issuing the imag e writing command, the da ta writing is necessary in accurate the order. (upper lower upper lower...) on the other hand, the data writing operation from the host is unnecessary because the automatic writing is done with a pin (image data/dot clock) at video if. target address+"00" issue autoviewon command etc. imgport address+"data writing for upper byte : at 1st pixel" imgport address+"data writing for lower byte : at 1st pixel" imgport address+"data writing for upper byte : at 2nd pixel" ||||| imgport address+"data writing for upper byte : at nth pixel" imgport address+"data writing for lower byte : at nth pixel" (image reading command : imgread) read via special image port (imgport : 0 fd). the access order is same as parallel cpu if : imgreadgo imgread image reading. imgreadgo+"00" issue imgreadgo command. imgread+"00" issue imgread command. imgport address+"reading target pixel's upper byte" imgport address+"reading target pixel's lower byte" please keep the order "upper byte lower byte". because the i 2 c bus is low-speed, status read after imgreadgo command is unnecessary. (status read :) status and a usual register are distinguished referring to the a0 address at parallel if. on the other hand, it correspon ds in a special address in i 2 c. (stat upper : statup : 0 fe, stat lower : statdn : 0 ff). statup address+"reading upper byte of status register" statdn address+"reading upper byte of status register" the read order from upper byte or lower byte doesn't especially have regulations. only one byte accessing is also possible.
LC822973 no.a2131-20/27 list of command (a0==0) the following tables are memory maps for 16bitcpu bus with 16bit width parameters. i 2 c takes big endian system. upper byte : i 2 c_address = add 2 lower byte : i 2 c_address = add 2 + 1 no add command name function length description 1 0 01 clkcont clock control 1wor d vclk_mode, pllon, dacon, dram sleep, mode setting at videoif 2 0 02 div_m pll control 1word 1/m (12bit) 3 0 03 div_n pll control 1word 1/n (12bit) 4 0 04 div_p pll control 1word 1/p (8bit), s0--s3 5 0 05 reserved - - - 6 0 06 int interrupt 1word int factor *) this can be issued during memory writing 7 0 07 inten interrupt 1word int factor clear *) this can be issued during memory writing 8 0 08 sysctl1 system setup 1word scaler and matrix on/off, scan direction, display off, filter setup, enhancer setup, etc. 9 0 09 sysctl2 system setup 1word transfer mode setup, v sync setup, etc. 10 0 0a sysctl3 system setup 1word polarity, sy stem control, etc. (others, spare) 11 0 0b memset1 memctl setup 1word sdram burst length, latency, mode, etc. 12 0 0c memset2 memctl setup 1word sdram refresh interval 13 0 0d memset3 memctl setup 1word sdram initial sequence setup 14 0 0e imgwrite cpu drawing - cpu sdram writing 15 0 0f imgreadgo image reading - sdram cpu reading start 16 0 10 imgread image reading 1word sdram cpu reading (acquiring data) 17 0 11 imgabort drawing end - cpu drawing forced termination 18 0 12 scale scale up 1word scaling image ratio setup 19 0 13 reserved - - - 20 0 14 reserved - - - 21 0 15 wfbhlen coordinate setup 1word sdra m address length for cpu drawing (h) 22 0 16 wfbvlen coordinate setup 1word sdra m address length for cpu drawing (v) 23 0 17 wfbhstart coordinate setup 1word horiz ontal start point for sdram writing 24 0 18 wfbvstart coordinate setup 1word vert ical start point for sdram writing 25 0 19 rfbhofst coordinate setup 1word real -time reading sdram address offset (h) 26 0 1a rfbvofst coordinate setup 1word real-t ime reading sdram address offset (v) 27 0 1b dsphofst coordinate setup 1word real-time reading display position offset (h) 28 0 1c dspvofst coordinate setup 1word real-t ime reading display position offset (v) 29 0 1d dsphlen coordinate setup 1word real-tim e reading display position length (h) 30 0 1e dspvlen coordinate setup 1word real-tim e reading display position length (v) 31 0 1f bgcolor1 background color 1word background color y signal (use only low 8bit) 32 0 20 bgcolor2 background color 1word background color uv signal (u: upper, v: lower) 33 0 21 encmode venc setup 1word operation mode, filter switch, interlace setup 34 0 22 encgain1 venc setup 1word lev el setup, bright, contrast 35 0 23 encgain2 venc setup 1word level setup, color gain 36 0 24 encbst1 venc setup 1word burst gain setup 37 0 25 encbst2 venc setup 1word burst phase setup 38 0 26 encbbplt venc setup 1word blueback pallet setup 39 0 27 encrhval video timing 1word horizontal valid period signal to the memory controller adjustment 40 0 28 enchblk video timing 1word horizontal blanking period adjustment 41 0 29 encvblk video timing 1word vertical blanking period adjustment 42 0 2a version other 1word version register 43 0 2b testmode for test 1word - 44 0 2c osdcont_1 osd1 setup 1word sdram burst length,osd1 on/off, etc. continued to the next page.
LC822973 no.a2131-21/27 continued from the previous page. no add command name function length description 45 0 2d osdwfbhstart osd1, 2 setup 1word sdram address offset for osd drawing (h) 46 0 2e osdwfbvstart osd1, 2 setup 1word sdram address offset for osd drawing (v) 47 0 2f osdwfbhlen osd1, 2 setup 1word sdram address length for osd drawing (h) 48 0 30 osdwfbvlen osd1, 2 setup 1word sdram address length for osd drawing (v) 49 0 31 osdrfbhofst_1 osd1 setup 1word sdram reading address (h) offset for osd1 50 0 32 osdrfbvofst_1 osd1 setup 1word sdram reading address (v) offset for osd1 51 0 33 osdhofst_1 osd1 setup 1word display position offset (h) for osd1 52 0 34 osdvofst_1 osd1 setup 1word display position offset (v) for osd1 53 0 35 osdhlen_1 osd1 setup 1word display position length (h) for osd1 54 0 36 osdvlen_1 osd1 setup 1word display position length (v) for osd1 55 0 37 osdcont_2 osd2 setup 1word burst length (sdram), osd2 on/off, etc. 56 0 38 osdrfbhofst_2 osd2 setup 1word sdram reading address offset (h) for osd2 57 0 39 osdrfbvofst_2 osd2 setup 1word sdram reading address offset (v) for osd2 58 0 3a osdhofst_2 osd2 setup 1word display position offset (h) for osd2 59 0 3b osdvofst_2 osd2 setup 1word display position offset (v) for osd2 60 0 3c osdhlen_2 osd2 setup 1word display position length (h) for osd2 61 0 3d osdvlen_1 osd2 setup 1word display position length (v) for osd2 62 0 3e osdcolor_y osd1,2 setup 1word osd y adjustment (up: osd1/down: osd2) 63 0 3f osdcolor_u osd1,2 setup 1word osd u adjustment (up: osd1/down: osd2) 64 0 40 osdcolor_v osd1,2 setup 1word osd v adjustment (up: osd1/down: osd2) 65 0 41 osdwrite osd drawing - cpuosd sdram draw 66 0 42 osdabort osd drawing - cpuosd draw abort 67 0 43 vifsys videoif setup 1word data ordering, sy nc polarity, internal valid flag on/off etc. 68 0 44 vifhactsta videoif setup 1word internal valid flag (start position of h-flag) 69 0 45 vifhactend videoif setup 1word internal valid flag (end position of h-flag) 70 0 46 vifvactsta videoif setup 1word internal valid flag (start position of v-flag) 71 0 47 vifvactend videoif setup 1word internal valid flag (end position of v-flag) 72 0 48 aviewsys a-view setup 1word nu m of bank at autoview mode 73 0 49 autoviewon a-view start - strat autoviewing 74 0 4a autoviewoff a-view st op - stop autoviewing 75 0 4b avwfbhstart_0 a-view setup 1wor d start position of bank#0 (h) 76 0 4c avwfbvstart_0 a-view setup 1wor d start position of bank#0 (v) 77 0 4d avwfbhstart_1 a-view setup 1wor d start position of bank#1 (h) 78 0 4e avwfbvstart_1 a-view setup 1word start position of bank#1 (v) 79 0 4f avwfbhstart_2 a-view setup 1wor d start position of bank#2 (h) 80 0 50 avwfbvstart_2 a-view setup 1word start position of bank#2 (v) 81 0 51 cgmsa_code cgmsa setup 1word cgmsa code setting 82 0 52 cgmsa_trm cgmsa setup 1word cgmsa position setting 83 0 53 wss_code wss setup 1word wss code setting 84 0 54 wss_trm wss setup 1word wss position setting 85 0 55 reserved | | | 112 0 70 reserved for i 2 c 113 0 7e 0 fc (i 2 c) : no use 0 fd (i 2 c) : imgport image port 114 0 7f 0 fe (i 2 c) : status (upper) 0 ff (i 2 c) : status (lower) status
LC822973 no.a2131-22/27 ac characteristics (cpu bus timing) parallel i/f (i80 like) cpu write cpu read item symbol condition min typ max unit system cycle time (write) [ 1 transfer] tcycw write 3t* cyc system cycle time (read) [ 1 transfer] tcycr read 3t* cyc system cycle time (write) [ 2, 3 transfer] tcycw write 2t* cyc system cycle time (read) [ 2, 3 transfer] tcycr read 2t* cyc address setup time (write) twas a 15 ns address hold time (write) twah a 5 ns address setup time (read) tras a 25 ns address hold time (read) trah a 5 ns cs setup time (write) twcs /cs 15 ns cs hold time (write) twch /cs 5 ns cs setup time (read) trcs /cs 25 ns cs hold time (read) trch /cs 5 ns /wr low side pulse width twlw /wr 20 ns /wr high side pulse width twhw /wr 15 ns /rd low side pulse width trlw /rd 25 ns /rd high side pulse wi dth trhw /rd 15 ns data setup time twds data [15:0] 15 ns data hold time twdh data [15:0] 5 ns read access time tacc* data [15:0] 20 ns data hold time trdh data [15:0] 10 ns * t ? mclk (master clock) 1 cy cle .ex. mclk: 50mhz ? 1t is 20ns. * tacc ? from (/rd) or (/cs) twas twah twlw twhw twds tcycw high twdh twcs twch a cs /wr /rd data tras trah trlw trhw tacc tcycr high trdh trcs trch a cs /wr /rd data
LC822973 no.a2131-23/27 i 2 c transfer sequence and ac characteristics i 2 c slave circuit is equipped to the lsi for the video-i/f mode, which enables to read and to write command registers via sda and scl pins. idsel pin sets one of two pre-defined device id's, idsel: 0 then device id=0 40 (0100_000_r) idsel: 1 then device id=0 42 (0100_001_r) the transfer sequence of i 2 c is explained below. slave address i 2 c writing command issue register address register data (write) start stop writing scl sda 0xxxxxx msb ack ack ack write a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 slave address i 2 c writing command issue register address register data (read) slave address start (no2) start stop reading scl sda 0xxxxxx msb ack ack no_act write a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0100000 ack read i 2 c transfer sequence and transfer time when write command is issued. i 2 c transfer sequence and transfer time when read command is issued.
LC822973 no.a2131-24/27 thigh tbuf thd:sta tr tsu:sto tf tf tr tlow tsu:sta s start condition start condition stop condition sda scl s p i/o timing of i 2 c bus (at the time of scl 400khz cycle mode) symbol item min max unit tbuf bus open period 1.3 s thd: sta hold time (start) 0.6 s tlow scl_lo period 1.3 s thigh scl_hi period 1.3 s tr data rising 300 s tf data falling 300 s tsu: sta setup time (start) 0.6 s tsu: sto setup time (stop) 0.6 s thd:dat tsu:dat thigh sda scl i/o timing of i 2 c bus (at the time of high speed operation) symbol item min max unit tsu: dat setup time (data) 100 ns thd: dat hold time (data) 0 ns thigh scl_hi period 150 ns
LC822973 no.a2131-25/27 ac characteristics (video i/f timing) dotwl dotwh dotcyc vifts tifth db17,db16 vifvd15-0 viffi vifhact vifvact vifhs vifvs vifdot (dotclock) symbolitem symbol condition min typ max unit data/flag setup time vifts db17/16 vifvd, vifhs, vifvs, viffi vifhact vifvact 10 ns data/flag hold time vifth db17/16 vifvd, vifhs, vifvs, viffi vifhact vifvact 5 ns clock low side pulse widt h dotwl vifdot 15 ns clock high side pulse widt h dotwh vifdot 15 ns clock cycle time dotcyc vifdot 30 ns
LC822973 no.a2131-26/27 ac characteristics (reset condition) fixing xrst pin to lo level initializes the internal ff. th e filter circuit that used delay device is embedded inside so that an error operation won?t be performed even if a noise is on xrst pin. the condition of lo period is as follows. xrst 20ns(min) lo period restricyion of xrst pin power turn-on/turn off-conditions this lsi needs digital power (dv dd 15 [core], dv dd 3 [dram], dv dd io), analog power for dac (av dd 3) and analog power for pll (av dd 15). power turn on/turn off conditions is shown in the following sequence diagram. it is desirable for dv dd 15 and dv dd io/dv dd 3 to maintain dv dd 15 > = dv dd io/dv dd 3/av dd 3/av dd 15 relation as below or at the same time. however, the condition is acceptable when the period, which is the reversed relation, is within 1ms. simultaneous of power turn on / turn off of dv dd io/dv dd 3/av dd 3/av dd 15 is all preferable. however, there is no problem even if the time difference is mutually generated. however, please avoid keeping only a certain pow er supply in the state of power turn off. dv dd io dv dd 15 off on same time or dv dd 15 on early same time or dv dd 15 off later dv dd 3 a v dd 3 a v dd 15 simultaneous of power turn on/turn off of dv dd io/dv dd 3/ av dd 3/av dd 15 is all preferable. however, there is no problem even if the time difference is mutually generated. off on off on off on off on power turn-on/turn-off sequence
LC822973 no.a2131-27/27 ps sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. regarding monolithic semiconductors, if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temperature change, even if it is used within the range of absolute maximum ratings or operating conditions, there is a possibility of decrease reliability. please contact us for a confirmation. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equ ipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. this catalog provides information as of october, 2012. specifications and information herein are subject to change without notice.

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