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| version 1.0 912-3000-001 august, 1994 opti ? 82C499 dx system controller data book
opti inc. 2525 walsh avenue santa clara, ca 95051 tel: (408) 980-8178 fax: (408) 980-8860 bbs: (408) 980-9774 copyright copyright ? 1994, opti inc. all rights reserved. no part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any lan- guage or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or oth- erwise, without the prior written permission of opti inc. disclaimer the information contained in the manual is provided for the general use of the customers of opti i nc. opti inc. makes no claims or guarantees as to the accuracy of this documentation and assumes no responsibility for any errors. opti inc. reserves the right to make changes to this documentation and the product described herein without notice or obligation. in no event will opti inc. be liable for damages, direct or indirect, resulting from any error, defect, or omission in this manual. trademarks opti and opti inc. are registered trademarks of opti incorporated. all other trademarks and copyrights are the property of their respective holders. table of contents iii 1.0 features 1 2.0 overview 2 3.0 signal definitions 3 3.1 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.1 cpu interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1.2 at bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1.3 bus arbitration interf ace signals . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.4 numeric processor interface signals . . . . . . . . . . . . . . . . . . . . . 8 3.1.5 cache interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.6 dram interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.7 82c206 signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.8 buffer control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.9 reset signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.10 clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.11 miscellaneous interface signals . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.12 power and ground pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.0 functional description 13 4.1 reset logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 cpu burst mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 cache subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.1 cache bank interleave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.2 write-back cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.3 tag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.4 dirty bit mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 local dram control subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 parity generation/detection logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 refresh logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 shadow ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 system rom bios cycles and flash eprom support . . . . . . . . . . . . 18 4.10 at bus state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 bus arbitration logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.12 numeric coprocessor cycles (npx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14 data bus conversion/data path control logic. . . . . . . . . . . . . . . . . . . . 19 4.15 turbo/slow mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.16 fast gatea20 and reset emulation. . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.17 special cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.0 registers descriptions 21 5.1 i/o port 60h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 i/o port 64h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.0 maximum ratings 29 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 6.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 ac timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.0 mechnical package outline 65 iv list of figures v figure 1-1 address and data path clock diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 3-1 pin diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 6-1 2-1-1-1 double bank cache read hit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 6-2 3-1-1-1 single bank cache read hit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 6-3 zero-wait state write hit cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 6-4 one-wait state cache write hit cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 6-5 dma/isa master transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 6-6 one-wait state dram read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 6-7 one-wait state dram page hit burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 6-8 one-wait state dram burst read, ras# inactive . . . . . . . . . . . . . . . . . . . . . . 40 figure 6-9 one-wait state dram page miss burst read. . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6-10 zero-wait state dram write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 6-11 one-wait state dram write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 6-12 isa bus cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 6-13 keyboard controller access cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6-14 cpu reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 6-15 refresh cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6-16 cache read miss d irty: 2 banks of cache and 0/0 dram wait state (1 of 2) . . 48 figure 6-17 cache read miss d irty: 2 banks of cache and 0/0 dram wait state (2 of 2) . . 49 figure 6-18 cache read miss d irty: 1 bank of ca che and 0/0 dram wait state (1 of 2) . . . 50 figure 6-19 cache read miss d irty: 1 bank of ca che and 0/0 dram wait state (2 of 2) . . . 51 figure 6-20 cache read miss d irty: 2 banks of cache and 1/1 dram wait state (1 of 2) . . 52 figure 6-21 cache read miss d irty: 2 banks of cache and 1/1 dram wait state (2 of 2) . . 53 figure 6-22 cache read miss d irty: 1 bank of ca che and 1/1 dram wait state (1 of 2) . . . 54 figure 6-23 cache read miss d irty: 1 bank of ca che and 1/1 dram wait state (2 of 2) . . . 55 figure 6-24 cache read miss not d irty: 2 banks of cache and 0 dram read wait state . . . 56 figure 6-25 cache read miss not d irty: 2 banks of cache and 1 dram read wait state . . . 57 figure 6-26 rom access cycle (1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6-27 rom access cycle (2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 6-28 dma device read from vesa slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 6-29 dma device write to vesa slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 6-30 isa master read from vesa slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 6-31 isa master write to vesa slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 vi list of tables vii table 3-1 numerical pin cross-reference list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3-2 alphabetical pin cross-reference list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 4-1 address to tag bit mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4-2 cache sram requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4-3 sram speed requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4-4 dram configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4-5 cpu address to ma bus mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5-1 control register 1 - index: 20h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5-2 control register 2 - index: 21h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5-3 shadow ram control register i - index: 22h. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5-4 shadow ram control register ii - index: 23h . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5-5 dram control register i - index: 24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5-6 dram control register ii - index: 25h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5-7 shadow ram control register iii - index: 26h. . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5-8 control register 3 - index: 27h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5-9 non-cacheable block 1 register - index: 28h . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5-10 non-cacheable block 1 register ii - index: 29h . . . . . . . . . . . . . . . . . . . . . . . . 25 table 5-11 non-cacheable block 2 register i - index: 2ah . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5-12 non-cacheable block 2 register ii - index: 2bh . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5-13 rom chip select (romcs#) control register - index: 2dh . . . . . . . . . . . . . . . 26 table 5-14 i/o port 61h(port b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5-15 i/o port 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5-16 port 92h - system controller port a, ps/2 compatibi lity port . . . . . . . . . . . . . . 27 table 6-1 82C499 b1 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 viii 82C499 912-3000-001 pa ge 1 dx system controller opti ? 1.0 features ? supports intel ? 486 sx/dx/dx2, 487sx, and intel 386dx/cyrix ? 486dlc/ibm 486dlc microproces- sors ? single-chip pc/at ? solution: one 208-pin plastic flat package (pfp) ? 1x and 2x clock source, supp orting systems run- ning from 16mhz to 50mhz ? write-back direct mapped, bank interleave cache with size selections: 64kb, 128kb, 256kb, and 512kb ? supports 2-1-1-1, 3-1-1-1, 2-2-2-2, and 3-2-2-2 cache burst cycles ? support for two programmable non-cacheable regions ? built-in tag auto-invalidation circuitry ? option for write-protected, cacheable video and system bios ? programm able cache and dram read/write cycles ? supports four banks of 256kb, 1mb, and 4mb drams for configurations up to 64mb ? shadow ram option ? flash rom support ? hidden refresh and slow refresh supported using the cas-before-ras refresh method ? comprehensive vesa vl and opti high-perfor- mance l ocal bus s upport ? turbo/slow speed selection ? synchronous at bus clock with pro grammable clock division options: ? clki(/6, /5 /4, /3), or clk2i(/6, /5, /4, /3) ? zero or one wait state options for 16-bit at bus cycles ? transparent 8042 emulation for fast cpu reset and gatea20 generation ? supports the 80387 numeric coprocessor ? low-power, high-speed 0.8-micron cmos t echnol- ogy ? integrated peripherals controller figure 1-1 address and data path clock diagram cpu fpu 82C499 bios keyboard rtc cache sram local bus isa bus opti control bus cd[31:0] ca[31:2] ca[18:4] control bus cd[31:0] ca[31:0] ca[23:0] la[23:17] sa[19:0] sa[9:2] sd[15:8] sd[7:0] sd[7:0] sd[15:0] cd[23:16] cd[23:16] xd[7:0] sd[7:0] ma[10:0] ras, cas 1-64mb peripherals controller rom dra m cache control cd[31:0] 82C499 pa ge 2 912-3000-001 opti ? 2.0 overview the opti 82C499 provides a highly integrated solution for fully compatible, high-performance pc/at plat- forms. this chip will su pport the intel 486sx/dx/dx2/ 487sx, intel 386dx and ibm/cyrix 486dlc micropro- cessors in the most cost effective and power efficient designs available t oday. since the device is so critical to the perform ance and cost structure of a pc, this highly integrated approach provides the foundation for a very cost effective platform without compromising perform ance. for power users, this chip offers opti- mum performance for systems running up to 50mhz. the opti dxsc chip provides a solution positi oned to deliver value, without neglecting quality, compatibility, or reliability. the 82C499 integrates a write-back cache controller, a local dram control ler, an integrated peripherals con- troller (82c206), the cpu state machine, the at bus state machine, and data buffers all in a single 208-pin pfp. new on-chip hardware provides the hooks for opti and vesa local bus device support. 82C499 912-3000-001 pa ge 3 opti ? 3.0 signal definitions figure 3-1 pin diagram drq5 drq6 osc gnd vcc drq7 dack0 dack1 dack2 irq1 irq43 irq6 ca32s# ca3 ca2 drtyw# tagwe# beoe# booe# gnd vcc ecawe# ocawe# be0# be1# be2# be3# ma0 ma1 ma2 ma3 ma4 ma5 ma6 ma7 cas0# cas1# gnd cas2# cas3# ma8 ma9 ma10 ras0# ras1# ras2# ras3# dwe# drq0 drq1 drq2 drq3 197 198 199 200 201 202 203 204 205 206 207 208 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 117 116 115 114 113 112 111 110 109 108 107 106 105 a2 cpurst vcc rdy# brdy#/preqo ads# w/r# m/io# d/c# err#/ken# eads#/nprst blst#/preqi 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 tag7 tag6 tag5 tag4 tag3 tag2 tag1 tag0 vcc a31 drams#/lreq# a25 a24 gnd gnd a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 gnd a13 a12 a11 a10 a9 a8 a7 a6 a5 gnd gnd a4 a3 mp2 mp1 mp0 sysrst# vcc gnd pwrgd chck# hlboe2# hlboe1# hlblth# xdir# intr hlda hold rdyi# ldev# turbo nmi vcc gnd busy#/igerr# nperr# nbusy# d31 d30 d29 d28 d27 d26 d25 d24 d15 d14 d13 d12 d11 gnd gnd d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mp3 drty lmgcs#/ 64 63 62 61 60 59 58 57 56 55 54 53 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 xd14 xd15 vcc tc kbdcs#/lgnt# rtcas rtccs# spkd romcs# 0ws# chrdy a20m irq75 irq8 irq9 irq1110 irq14 irq1512 rfsh# ale atclk vcc xd0 xd1 xd2 xd3 gnd gnd xd4 xd5 xd6 xd7 iord# iowr# mrd# mwr# mcs16# clk2 gnd clk1 iocs16# sa0 sa1 sbhe# xd8 xd9 xd10 xd11 gnd gnd xd12 xd13 82C499 dx pc/at system controller kblmcs# 82C499 pa ge 4 912-3000-001 opti ? table 3-1 numerical pin cross-reference list pin name 1 irq75 2 irq8 3 irq9 4 irq1110 5 irq14 6 irq1512 7 rfsh# 8 ale 9atclk 10 vcc 11 xd0 12 xd1 13 xd2 14 xd3 15 gnd 16 gnd 17 xd4 18 xd5 19 xd6 20 xd7 21 iord# 22 iowr# 23 mrd# 24 mwr# 25 mcs16# 26 clk2 27 gnd 28 clk1 29 iocs16# 30 sa0 31 sa1 32 sbhe# 33 xd8 34 xd9 35 xd10 36 xd11 37 gnd 38 gnd 39 xd12 40 xd13 41 xd14 42 xd15 43 vcc 44 tc 45 kbdcs#/lgnt# 46 rtcas 47 rtccs# 48 spkd 49 romcs# 50 0ws# 51 chrdy 52 a20m 53 lmgcs#/kblmcs# 54 xdir# 55 hlblth# 56 hlboe1# 57 hlboe2# 58 chck# 59 pwrgd 60 gnd 61 vcc 62 sysrst# 63 mp0 64 mp1 65 mp2 66 mp3 67 d0 68 d1 69 d2 70 d3 71 d4 72 d5 73 d6 74 d7 75 d8 76 d9 77 d10 78 gnd 79 gnd 80 d11 81 d12 82 d13 83 d14 84 d15 85 d24 86 d25 87 d26 88 d27 89 d28 90 d29 91 d30 92 d31 93 nbusy# 94 nperr# 95 busy#/igerr# 96 gnd 97 vcc 98 nmi 99 turbo 100 ldev# 101 rdyi# 102 hold 103 hlda 104 intr pin name 105 blst#/preqi 106 eads#/nprst 107 err#/ken# 108 d/c# 109 m/io# 110 w/r# 111 ads# 112 brdy#/preqo 113 rdy# 114 vcc 115 cpurst 116 a2 117 a3 118 a4 119 gnd 120 gnd 121 a5 122 a6 123 a7 124 a8 125 a9 126 a10 127 a11 128 a12 129 a13 130 gnd 131 a14 132 a15 133 a16 134 a17 135 a18 136 a19 137 a20 138 a21 139 a22 140 a23 141 gnd 142 gnd 143 a24 144 a25 145 drams#/lreq# 146 a31 147 vcc 148 tag0 149 tag1 150 tag2 151 tag3 152 tag4 153 tag5 154 tag6 155 tag7 156 drty pin name 157 ca32s# 158 ca3 159 ca2 160 drtyw# 161 tagwe# 162 beoe# 163 booe# 164 gnd 165 vcc 166 eca we# 167 ocawe# 168 be0# 169 be1# 170 be2# 171 be3# 172 ma0 173 ma1 174 ma2 175 ma3 176 ma4 177 ma5 178 ma6 179 ma7 180 cas0# 181 cas1# 182 gnd 183 cas2# 184 cas3# 185 ma8 186 ma9 187 ma10 188 ras0# 189 ras1# 190 ras2# 191 ras3# 192 d we# 193 drq0 194 drq1 195 drq2 196 drq3 197 drq5 198 drq6 199 osc 200 gnd 201 vcc 202 drq7 203 dack0 204 dack1 205 dack2 206 irq1 207 irq43 208 irq6 pin name 82C499 912-3000-001 pa ge 5 opti ? table 3-2 alphabetical pin cross-reference list pin name 116 a2 117 a3 118 a4 121 a5 122 a6 123 a7 124 a8 125 a9 126 a10 127 a11 128 a12 129 a13 131 a14 132 a15 133 a16 134 a17 135 a18 136 a19 137 a20 52 a20m 138 a21 139 a22 140 a23 143 a24 144 a25 146 a31 111 ads# 8 ale 9atclk 168 be0# 169 be1# 170 be2# 171 be3# 162 beoe# 105 blst#/preqi 163 booe# 112 brdy#/preqo 95 busy#/igerr# 159 ca2 158 ca3 157 ca32s# 180 cas0# 181 cas1# 183 cas2# 184 cas3# 58 chck# 51 chrdy 28 clk1 26 clk2 115 cpurst 67 d0 68 d1 69 d2 70 d3 71 d4 72 d5 73 d6 74 d7 75 d8 76 d9 77 d10 80 d11 81 d12 82 d13 83 d14 84 d15 85 d24 86 d25 87 d26 88 d27 89 d28 90 d29 91 d30 92 d31 108 d/c# 203 dack0 204 dack1 205 dack2 145 drams#/lreq# 193 drq0 194 drq1 195 drq2 196 drq3 197 drq5 198 drq6 202 drq7 156 drty 160 drtyw# 192 dwe# 106 eads#/ nprst 166 ecawe# 107 err#/ken# 15 gnd 16 gnd 27 gnd 37 gnd 38 gnd 60 gnd 78 gnd 79 gnd 96 gnd 119 gnd 120 gnd 130 gnd pin name 141 gnd 142 gnd 164 gnd 182 gnd 200 gnd 55 hlblth# 56 hlboe1# 57 hlboe2# 103 hlda 102 hold 104 intr 206 irq1 2 irq8 3 irq9 208 irq6 5 irq14 207 irq43 1 irq75 4 irq1110 6 irq1512 29 iocs16# 21 iord# 22 iowr# 45 kbdcs#/lgnt# 100 ldev# 53 lmgcs#/kblmcs# 109 m/io# 172 ma0 173 ma1 174 ma2 175 ma3 176 ma4 177 ma5 178 ma6 179 ma7 185 ma8 186 ma9 187 ma10 25 mcs16# 63 mp0 64 mp1 65 mp2 66 mp3 23 mrd# 24 mwr# 93 nbusy# 98 nmi 94 nperr# 167 ocawe# 199 osc 59 pwrgd 188 ras0# pin name 189 ras1# 190 ras2# 191 ras3# 113 rdy# 101 rdyi# 7 rfsh# 49 romcs# 46 rtcas 47 rtccs# 30 sa0 31 sa1 32 sbhe# 48 spkd 62 sysrst# 44 tc 99 turbo 148 tag0 149 tag1 150 tag2 151 tag3 152 tag4 153 tag5 154 tag6 155 tag7 161 tagwe# 10 vcc 43 vcc 61 vcc 97 vcc 114 vcc 147 vcc 165 vcc 201 vcc 110 w/r# 11 xd0 12 xd1 13 xd2 14 xd3 17 xd4 18 xd5 19 xd6 20 xd7 33 xd8 34 xd9 35 xd10 36 xd11 39 xd12 40 xd13 41 xd14 42 xd15 54 xdir# 50 0ws# pin name 82C499 pa ge 6 912-3000-001 opti ? 3.1 signal descriptions 3.1.1 cpu interface signals name pin type i ol description blst#/preqi 105 i 486 burst last cycle indication: the 82C499 terminates the burst cycle as long as blst# sampled low at the end of each t2 when brdy# is active. during intel 386dx and ibm/cyrix 486dlc mode, this is the preqi signal from the 387. brdy#/ preqo 112 o 8ma burst ready: an output for the cpu to sample the read data during burst cycles. this pin becomes preqo for the intel 386dx and ibm/ cyrix 486dlc mode of operation. be[3:0]# 171:168 i/o 4ma byte enables 3 through 0: these signals are inputs during cpu cycles and are outputs during non-cpu cycles. a31, a[25:24] 156, 144:143 i cpu address lines 31, 25, and 24. a[23:17] 140-134 i/o 4ma cpu address lines 23 through 17: these signals are inputs during cpu, refresh and master cycles. they become outputs during dma cycles. a[16:8] 133:131, 129:124 i/o 4ma cpu address lines 16 through 8: these signals are inputs during non-dma cycles. a[16:9] become outputs which convey dma address lines a[16:9] by latching xd[7:0] during 16-bit dma cycles. a[15:8] convey dma address lines a[15:8] by latching xd[7:0] during 8-bit dma cycles. a[7:2] 123:121, 118:116 i/o 4ma cpu address lines 7 through 2: these signals become outputs during dma cycles. d[31:24], d[15:0] 80:92, 67:77 i/o 4ma cpu data bus bits 31 through 24 and 15 through 0. d/c# 108 i cpu data or code cycle status: when high, this signal indicates data transfer operations. when low, it indicates control operations (code fetch, halt, etc.). m/io# 109 i/o 8ma cpu memory or i/o cycle status: when high, this signal indicates a memory cycl. when low, it indicates an i/o cycle. m/io# becomes an output during dma/master cycles for local device accesses and ibm 486dlc snooping cycles. w/r# 110 i/o 8ma cpu write or read cycle status: this signal indicates a write cycle if high and read cycle if low. it becomes an output during dma/master cycles for local device accesses and ibm 486dlc snooping cycles. a20m# 52 o 4ma emulation of gatea20 or'ed with internal fast gatea20 output to intel 486, ibm/cyrix 486dlc cpu. this signal must remain high during the power-up cpu reset period. in intel 3 86dx mode, this is the ga20 si gnal indirectly buffered to the at bus line la20. ldev# 100 i local bus device cycle indication: this signal is sampled at the end of the first t2, or at the end of the second t2 at 50mhz. drams#/ lreq# 145 i a[30:25] are low decode, connected to a26 normally, except during local bus master support, when mp1 is sampled low by rst4s rising edge, this signal becomes lreq# (local bus master re quest). 82C499 912-3000-001 pa ge 7 opti ? rdyi# 101 i local device ready input: this signal is synchronized by the 82C499 before s ending it to cpu. rdy# 113 i/o 8ma ready output for the cpu to terminate the current cycle. this pin becomes an input dur ing local device cycles if a tristated local bus device's ready was connected. ads# 111 i/o 8ma address strobe: a status input from cpu. this active low si gnal indicates the cpu is starting a new cycle. it becomes an output pin during dma/master cycles for local device accesses and ibm 486dlc snooping cycles. turbo 99 i turbo mode selection: if the turbo pin is tied l ow, the cpu will be forced idle for 2/3 period. 3.1.2 at bus interface name pin type i ol description mcs16# 25 i/o 18ma 16-bit at memory slave cycle status: this pin is a schmitt-trigger input pin normally and is driven low during master cycle. iocs16# 29 i 16-bit i/o slave cycle status: this is a schmitt trigger input pin. ale 8 o 18ma at bus address latch enable: represents that an at cycle has started. sbhe# 32 i/o 18ma at bus high byte enable: this signal is an input pin during master cycles. xd[15:0] 42:39, 36:33, 20:17, 14:11 i/o 18ma at data bus lines. iord# 21 i/o 24ma at i/o read command: this pin is an input during master cycles and an output for cpu and dma cycles. iowr# 22 i/o 24ma at i/o write command: this pin is an input during master cycles and an output for cpu and dma cycles. mrd# 23 i/o 18ma at memory read command: this pin is an input during master cycles and an output for cpu and dma cycles. mwr# 24 i/o 18ma at memory write command: this pin is an input during master cycles and an output for cpu and dma cycles. romcs# 49 o 4ma bios rom output enable: system bios rom accesses could be either 8- or 16-bit. this signal will be asserted from the end of the first t2 to the end of the last t2. chrdy 51 i/o 18ma channel ready: this pin is a schmitt-trigger input from the at bus. lmgcs#/ kblmcs# 53 o 4ma lower memory space (below one megabyte) indicator: this signal is active during refresh cycles. when mp1 is sampled low, this pin becomes kblmcs# only dur ing i/o cycles. this pin must be qualified with m/io# before it goes to the 8042 chip select. 3.1.1 cpu interface signals (cont.) name pin type i ol description 82C499 pa ge 8 912-3000-001 opti ? sa0 30 i/o 24ma system address line 0: this pin is an input during master cycles; an output during cpu, dma, or refresh cycles. sa1 31 i/o 24ma system address line 1: this pin is an input during master cycles and output during cpu, dma, or refresh cycles. 0ws# 50 i zero wait state: this pin is a schmitt-trigger input pin from the at bus. note that the system bios rom is accessed as a one wait state at cycle. 3.1.3 bus arbitration interface signals name pin type i ol description rfsh# 7 i/o 18ma at refresh cycle indication: this signal is an input pin master or dma cycles. note that the 82C499 will not hold the cpu during at refresh cycles. the 82C499 puts the cpu on "waiti ng" if an at refresh cycle is underway. hlda 103 i hold acknowledge from cpu. hold 102 o 4ma hold request to cpu: hidden refresh will not hold the cpu. 3.1.4 numeric processor interface signals name pin type i ol description npbusy# 93 i numeric processor busy: also used to determine intel 386, ibm/ cyrix 486dlc, or intel 486 mode. a high indicates an intel 386 or ibm/cyrix 486 dlc. a low indicates an intel 486. eads#/ nprst 106 o 4ma 486 address snooping strobe: this signal is asserted for two t- states during dma or master cycles. in the intel 386dx or ibm/cyrix 486dlc mode, a reset of the numeric coprocessor can be generated by an i/o write to port f1h, which will trigger nprst. nperr# 94 i numeric processor error indication: used to generate igerr# for the intel 486 cpu. also, it generates npint for at/pc-compatability and will generate busy# for the intel 386 or ibm/cyrix 486dlc. busy#/ igerr# 95 o 4ma busy or ignore error: this is a normally high signal and will become low as soon as the nperr# is asserted. an i/o write to port f0h, or a cpu reset w ill force this signal back to high. during the intel 386dx or ibm/cyrix486dlc mode, this signal is the busy# signal to the cpu. 3.1.5 cache interface signals name pin type i ol description err#/ken# 107 o 4ma error/cache enable: cacheable or non-cacheable status for the internal cache of intel 486 and ibm/cyrix 486dlc. this signal is low normally and is brought high at the end of t1. the 82C499 asserts ken# again if it is a cacheable cycle. during the intel 386 mode, this pin is err# to the cpu. err# for the i bm/cyrix 486 dlc needs to be generated externally. 3.1.2 at bus interface (cont.) name pin type i ol description 82C499 912-3000-001 pa ge 9 opti ? ca[3:2] 158:159 o 8ma cpu address lines 3 and 2. drty 156 i/o 4ma dirty bit of tag ram to indicate its line has been written into. ca32s# 157 o 4ma external cache address line 3 and line 2 select. beoe# 162 o 8ma external cache output enable. booe# 163 o 8ma external cache output enable. ecawe# 166 o 8ma external cache write enable for the even cache bank. ocawe# 167 o 8ma external cache write enable for the odd cache bank. tag[7:0] 155:148 i/o 4ma tag ram output lines 7 through 0. tagwe# 161 o 4ma tag ram write enable: used to update the tag ram. drtyw# 160 o 8ma write strobe to dirty bit of tag ram. 3.1.6 dram interface signals name pin type i ol description cas[3:0]# 184, 183, 181, 180 o 8ma dram column address strobe bits 3 through 0. mp[3:0] 66-63 i/o 4ma dram parity bits 3 through 0: in addition, mp1 is used to enable the internal vesa bus arbitration circuitry. this pin must be pulled down with a 1k resistor if the internal vesa bus arbitration is to be used. mp2 is used to determine the intel 386 or ibm/cyrix 486dlc. this pin must be pulled down with a 1k resistor if the ibm/cyrix 486 dlc is used. mp1 and mp2 are sampled on the rising edge of rst4. ras[3:0]# 188:191 o 8ma dram row address strobe bits 3 through 0. ma[10:0] 187:185, 179:172 o 8ma dram row/column address lines 10 through 0. dwe# 192 o 8ma dram write enable signal. 3.1.7 82c206 signal name pin type i ol description drq[7:0] 202, 198:193 i dma request lines dack[2:0] 205:203 o 5ma encoded dma acknowledgement lines 2 through 0. intr 104 o 4ma interrupt request irq1 206 i interrupt request line 1: schmitt-trigger input. irq43 207 i interrupt request lines 4 and 3: schmitt-trigger input. irq6 208 i interrupt request line 6: schmitt-trigger input. irq75 1 i interrupt request lines 7 and 5: schmitt-trigger input. 3.1.5 cache interface signals (cont.) name pin type i ol description 82C499 pa ge 10 912-3000-001 opti ? irq8 2 i interrupt request line 8: schmitt-trigger input. irq9 3 i interrupt request line 9: schmitt-trigger input. irq1110 4 i interrupt request lines 11 and 10: schmitt-trigger input. irq14 5 i interrupt request line 14: schmitt-trigger input. irq1512 6 i interrupt request lines 15 and 12: schmitt-trigger input. tc 44 o 12ma terminate count. 3.1.8 buffer control signals name pin type i ol description hlboe1# 56 o 4ma byte 2 data buffer output enable: this signal becomes active when: cpu dram cycles for parity checking and generation, cpu at byte 2 write cycle at 486 mode, dma or master byte 2 read dram or, local device cycle. hlblth# 55 o 4ma byte 2 data latch enable: this signal becomes high when: cpu at byte 2 read cycle, dma or master cycle. hlboe2# 57 o 4ma byte 2 data latch output enable: this signal becomes active when: cpu at byte 2 read cycle dma or master byte 2 write to local dram or local device. xdir# 54 o 4ma sd[7:0] to xd[7:0] direction control: this signal is normally high and is driven low when the devices located on xd[7:0] are read. 3.1.9 reset signals name pin type i ol description cpurst 115 o 8ma cpu reset for the microprocessor. sysrst# 62 o 8ma debounced pw rgd# output. pwrgd 59 i power good status or reset switch on indication. 3.1.10 clock signals name pin type i ol description osc 199 i 14.3mhz oscillator input. 3.1.7 82c206 signal (cont.) name pin type i ol description 82C499 912-3000-001 page 11 opti ? atclk 9 o 18ma atclk to at bus. this is a free running clock output. it could be clki/3, clki/4, clki/5 or clki/6 ( indicates that 82C499 is running at 50mhz and ldev# will be sampled at the end of second t2 clock cycle). clk2 26 i clock input which has a frequency equal to twice the rated cpu clock if the 2x-clock scheme is chosen. this signal is used for secondary cache early write option only. if the 1x clock scheme is used, this pin is connected to the same clock source as clki. clk1 28 i single phase clock input for the 82C499 internal state machine. 3.1.11 miscellaneous interface signals name pin type i ol description chck# 58 o channel check: an input from the at bus to indicate that a parity error was generated by the at memory card. (nmi inter rupt request.) kbdcs#/ lgnt# 45 o 4ma keyboard controller chip select or local grant: when i/o to port 60h or 64h is detected, this signal is decoded for the keyboard a[9:0]. when mp1 is pulled low, this signal becomes the vesa bus local grant signal. nmi 98 o 4ma non-m askable interr upt: sent to the cpu and caused by system parity error or at bus channel check. rtcas 46 o 4ma real-time clock address strobe. rtccs# 47 o 4ma real-time clock chip select. spkd 48 o 4ma speaker data output: generated by out2 and port 61h, bit 1. 3.1.12 power and ground pins name pin type i ol description vcc 10, 43, 61, 97, 114, 147, 165, 201 pwr power connection: +5v gnd 15, 16, 27, 37, 38, 60, 78, 79, 96, 119, 120, 130, 141, 142, 164, 182, 200 gnd ground connection 3.1.10 clock signals (cont.) name pin type i ol description 82C499 pa ge 12 912-3000-001 opti ? 82C499 912-3000-001 page 13 opti ? 4.0 functional description 4.1 reset logic the rst1# input to the 82C499 is used to generate the cpu reset (cpurst), the numeric coprocessor reset (nprst), and the system reset (sysrst#) signals. rst1# is a cold reset which is generated when either pwrgd goes low (from the power supply, indicating a low power condition) or when the system reset button is activated. this reset signal is used to force the sys- tem to begin execution at a known state. when rst1# is sensed active, the 82C499 will assert cpurst, nprst, and sysrst#. cpurst is also generated when a shutdown condition is decoded from the cpu bus definition signals. cpurst, nprst, and sysrst# are asserted for (128) clk2 cycles. the 82C499 emulates the keyboard reset function. the keyboard reset is intercepted by moni toring the i/o write cycle fe command to port 64h. this fast cpu reset from the chipset will be generated directly after the i/o write is decoded unless bit 1 of i ndex register 20h is disabled, in which case the reset will not start until a halt instruction is executed. when configured to interface with a math coprocessor, the 82C499 will generate the nprst signal when cpurst is activated or if an i/o write to port f1h is issued. 4.2 system clock generation the 82C499 has two high frequency clock inputs, clk and clk2. this clocking scheme provides both single and double frequency operation to support all 486 plat- forms at system speeds up to 50mhz. the 486 is driven by a 1x clock as opposed to the 2x clock requi red by the 486 dlc and 386 microprocessor. single frequency clocking is only necessary during 486 40mhz and 50mhz operation. in this mode, clk and clk2 are generated by the same source so that the 82C499 will receive only a single 1x clock source (this avoids the necessity of a 100mhz oscillator for 486 50mhz operation). double frequency operation requires that the clk2 input be fed directly by the crys- tal oscillator, while the clk input is derived from the oscillator output divided by two externally. in this mode, the 82C499 will receive both a 1x and 2x clock source. typically for intel 486 cpus, a double frequency clock is recomm ended for 20, 25, and 33mhz operation, while 40 or 50mhz operation requires a single fre- quency c locking scheme. clk is a master single-phase clock which is used to drive all host cpu synchronous si gnals and the 82C499's internal st ate machines. clk2 is used by the cache/dram controller logic and to maintain the clock phase between the cpu and the 82C499 by controlling the cpu reset timing. the 82C499 generates the at bus clock (atclk) from an internal division of clk or clk2. the atclk fre- quency is programmable and can be set to any of four clock division options by programming index register 25h[1:0]. this allows the system designer to tailor the at bus clock freq uency to support a wide range of sys- tem designs and performance platforms. a 2x clock is necessary for running the system with zero-wait-state-cache-write enabled and to conform to the timing requirements specified by t100a and t100b. at 40mhz, intel 386 or ibm 486dlc applications clki, clk2i, and cpuclk must be within 1ns clock skew of each other. this is required for the proper setup of hold time to be met for the cpu and proper synchroni zation of clki to the system. 4.3 cpu burst mode control the dxsc chipset fully supports 486 burst cycles. the 82C499 cache and dram controllers insure t hat data is burst into the cpu whenever the 486 requests a burst linefill. the secondary cache provides data on read-hits and the dram supplies the d ata during cache read-misses. for the cache read-hit cycle, brdy# is asserted at the middle of the first t2 state when a 2-1-1-1 (zero wait state) cache burst cycle is chosen, otherwise it is asserted at the middle of the second t2 state when one wait state is required. if a read-miss occurs, the dram data is first written into cache memory, then it is burst from the cache to the 486 cpu. brdy# is asserted after cache memory is updated for cache read-misses. once asserted, brdy# stays active until blst# is detected during a zero wait state burst cycle. brdy# is never active during dma or master cycles. the 82C499 contains separate burst counters to sup- port dram and external cache burst cycles. the dram burst coun ter performs the cache read-miss lin- efill (dram to external cache) and the cache burst coun ter supports the 486 burst linefill (external cache to the 486 cpu). the burst order of the cache burst coun ter exactly matches the double-word address sequencing expected by the 486 cpu. the dram burst counter is used for cache re ad-miss cycles and dirty linefill write operations. 82C499 pa ge 14 912-3000-001 opti ? 4.4 cache subsystem the integrated cache controller, which uses a direct- mapped, bank-interleaved scheme dramatically boosts the overall performance of the l ocal memory subsystem by caching writes as well as reads (write- back mode). cache memory can be configured as one or two banks, and sizes of 64, 128, 256, and 512kb are supported. provisions for two programmable non- cacheable regions are provided. the cache controller operates in non-pipeline mode, with a fixed 16-byte line size (optimized to match a 486 burst linefill) in order to simplify the motherboard design without increasing cost or degrading system per form ance. for 486 sys- tems, the secondary cache operates independently and in addition to the cpu's internal cache. the cache controller works as the front-end for both the dram and at bus controllers. ads# from the cpu must pass through the cache logic first. when the cache is disabled, ads# just falls through the cache controller and delivers an internal mads# to the dram and at bus controllers. when the cache is enabled, ads# is blocked when a cache cycle is detected. if this cycle is determined to be a nca (non-cacheable address) or a cache miss cycle, ads# is delayed one clk before outputting an internal mads# due to the time needed for nca and cache hit/miss detections. 4.4.1 cache bank interleave in order to support cache burst cycles at elevated fre- quencies and still utilize conventi onal speed srams, a bank interleave cache access method is employed. the addresses are applied to the cache memory one cycle earli er, while cache output enable signals control even/odd bank selection and enable cache ram data to the cpu data bus. since the output enable time is about one-half of the address access time, the 82C499 can achieve a high performance cache burst mode without using the m ore expensive high speed srams. the 82C499 supports one or two cache banks. two cache banks are required to interleave and realize the perform ance advantages of this cache scheme. cache sizes of 128kb and 512kb are single-bank caches, while 64kb and 256kb cache sizes are double-bank. when using a double-bank configuration, the even and odd banks receive the same address lines. signals a2/a3, ecawe#/ocawe#, and beoe#/booe# are used to dictate the even or odd bank access. 4.4.2 write-back cache the write-back cache s cheme derives its s uperior per- form ance by optimizing write cycles. there is no per- form ance penalty in the cache write cycle, since the cache controller does not need to wait for the much slower dram controller to finish its cycle before pro- ceeding to the next cycle. 4.4.3 tag ram a built-in tag comparator improves system perfor- mance while reducing component count on the system board. the comparator internally detects the cache hit/ miss status by comparing the high-order address bits (for the memory cycle in progress) with the stored tag bits from previous cache entries (see table 4-1). when a match is detected, and the location is cache- able, a cache hit cycle takes place. if the comparator does not match, or a non-cach eable location is accessed (based on the internal non-cacheable region registers), the current cycle is a cache miss. the tag is invalidated automatically during memory reads when the cache is disabled; each memory read will write into the corresponding tag location a non-cach eable address (such as a0000 or b0000 of the vi deo memory area). to invalidate the cache, simply disable the cache in configuration register 21h, bit 4, and read a block of memory equal to the size of the cache. the advantage of this invali dation scheme is that no valid bit is necessary and expensive sram can be con- served. to flush the cache, simply read a block twice the size of the cache. this will guarantee that every dirty cache location is flushed to dram. the following table details which cpu address bits are stored as tags for the various cache sizes supported in the 82C499 and how the tag ram bits are addressed for different cache sizes. table 4-1 address to tag bit mapping 4.4.4 dirty bit mechanism the dirty bit is a mechanism for monitoring coherency between the cache system and dram. each tag entry has a corresponding dirty bit to indicate whether the data in the represented cache line has been modified tag bit 64kb 128kb 256kb 512kb 7 a22 a22 a22 a22 6 a21 a21 a21 a21 5 a20 a20 a20 a20 4 a19 a19 a19 a19 3 a18 a18 a18 x 2 a17 a17 a25 a25 1 a16 a24 a24 a24 0 a23 a23 a23 a23 82C499 912-3000-001 page 15 opti ? since it was loaded from system memory. this allows the 82C499 to determine whether the data in memory is stale and needs to be updated before a new mem- ory location is allowed to overwrite the currently indexed cache entry. the write-back cycle causes an entire cache line (16 bytes) to be written back to mem- ory, followed by a line burst from the new memory loca- tion into the cache, and then the final line burst from the cache to the cpu. normally, the perform ance advantage of completing fast writes to the cache out- weigh the write-back read-miss penalties which are incurred while operating the write-back s cheme. cache read-hit the secondary cache provides data to the cpu. for 486 systems, the 82C499 follows the cpu's burst pro- tocol to fill the processor's internal cache line. cache read-miss (dirty bit negated) the cache controller does not need to update the sys- tem memory with the cache's current data because that data has not been modified (evidenced by the dirty bit negation). the cache controller as serts tagwe# causing the tag rams to update with the new address, and asserts ecawe#/o cawe# causing the cache memory to update with data from dram. this data is then presented to the cpu (following burst prot ocol for 486 systems). cache read-miss (dirty bit asserted) the cache controller must upd ate the system memory with data from the cache location that is going to be overwritten. the controller writes the 16-byte line from cache memory into dram, then reads the new line from dram into the cache memory and deasserts the dirty bit. the cache controller ass erts tagwe#, ecawe#/ocawe#, and drtyw# during this linefill. this new data is presented to the cpu (following burst prot ocol for 486 systems). cache wri te-hit because this is a write-back cache, the cache control- ler does not need to update the much slower dram memory. instead, the controller updates the cache memory and sets the dirty bit. dirty may already be set, but that does not affect this cycle. the contents of the tag ram remains unmodified. cache wri te-miss the cache controller bypasses the cache entirely and writes the data directly into dram. dirty is unchanged. table 4-2 shows the cache sizes supported by the 82C499, with the corresponding tag ram address bits, tag ram size, cache ram address bits, cache ram size, and cacheable main memory size. table 4-2 cache sram requirements table 4-3 shows what speed sram and tag sram to use for a particular cpu c lock rate. table 4-3 sram speed requirements *. for the intel 386 or ibm/cyrix 486dlc, only the lead-off cycles of the above corresponding ca che read burst cycles will be used (i.e., 33mhz and below: 2). cache size tag field address / tag ram size dirty srams size cache sram address qty / cache ram size cacheable main memory 64kb a[23:16] / 8kx8 16kx1 a[15:2] / 8ea, 8kx8 16mb 128kb a[24:17] / 8kx8 16kx1 a[16:2] / 4ea, 32kx8 32mb 256kb a[25:18] / 32kx8 16kx1 a[17:2] / 8ea, 32kx8 64mb 512kb a[25:19] / 32kx8 64kx1 a[18:2] / 4ea, 128kx8 64mb speed osc cache sram tag sram dram speed note * 16mhz 32mhz 25ns 25ns 80ns cache write 0ws, cache read burst 2-1-1-1 20mhz 40mhz 25ns 25ns 80ns cache write 0ws, cache read burst 2-1-1-1 25mhz 50mhz 25ns 25ns 80ns cache write 0ws, cache read burst 2-1-1-1 33mhz 66/33mhz 20ns 15ns 80ns cache write 0ws, cache read burst 2-2-2-2 1 bank of cache 33mhz 66/33mhz 20ns 15ns 80ns cache write 0ws, cache read burst 2-1-1-1 2 banks of cache 40mhz 80mhz 20ns 15ns 80ns cache write 1ws, cache read burst 3-2-2-2 50mhz 50mhz 20ns 15ns 80ns cache write 1ws, cache read burst 3-2-2-2 82C499 pa ge 16 912-3000-001 opti ? note dram and cache cycles are at their minimum wait states. 4.5 local dram control subsystem the 82C499 supports up to four banks of pa ge-mode local dram memory for config urations of up to 64mb. 256kb, 1mb, or 4mb page-m ode dram devices may be used. the dram configuration is pro grammable through configuration register 24h. dram perfor- mance features are programmable through configura- tion register 25h. table 4-4 illustrates the dram configurations supported. table 4-5 describes how the dram address lines are multiplexed when different memory device types are used. table 4-4 dram configurations bank0 bank1 bank2 bank3 total register bits [7:4] - [2:0] 256kb x x x 1mb 0 0 0 0 - 1 1 1 256kb 256kb x x 2mb 0 0 0 1 - 1 1 1 1mb x x x 4mb 1 0 0 0 - 1 1 1 256kb 1mb x x 5mb 0 0 1 0 - 1 1 1 1mb 1mb x x 8mb 1 0 0 1 - 1 1 1 1mb 1mb 1mb x 12mb 1 0 0 1 - 0 0 0 256kb 1mb 1mb 1mb 13mb 0 0 1 0 - 0 0 1 1mb 1mb 1mb 1mb 16mb 1 0 0 1 - 0 0 1 4mb x x x 16mb 1 1 0 0 - 1 1 1 256kb 256kb 4mb x 18mb 0 0 0 1 - 1 0 0 1mb 4mb x x 20mb 1 0 1 0 - 1 1 1 4mb 1mb x x 20mb 1 0 1 1 - 1 1 1 1mb 1mb 4mb 1mb 28mb 1 0 0 1 - 0 1 1 1mb 4mb 1mb 1mb 28mb 1 0 1 0 - 0 0 1 4mb 1mb 1mb 1mb 28mb 1 0 1 1 - 0 0 1 4mb 4mb x x 32mb 1 1 0 1 - 1 1 1 1mb 1mb 4mb 4mb 40mb 1 0 0 1 - 1 0 1 1mb 4mb 4mb 1mb 40mb 1 0 1 0 - 0 1 1 4mb 1mb 4mb 1mb 40mb 1 0 1 1 - 0 1 1 4mb 4mb 1mb 1mb 40mb 1 1 0 1 - 0 0 1 4mb 4mb 4mb x 48mb 1 1 0 1 - 1 0 0 1mb 4mb 4mb 4mb 52mb 1 0 1 0 - 1 0 1 4mb 1mb 4mb 4mb 52mb 1 0 1 1 - 1 0 1 4mb 4mb 4mb 1mb 52mb 1 1 0 1 - 0 1 1 4mb 4mb 4mb 4mb 64mb 1 1 0 1 - 1 0 1 82C499 912-3000-001 page 17 opti ? table 4-5 cpu address to ma bus mapping memory address 256kb 1mb 4mb column row column row column row ma0 a2 a11 a2 a21 a2 a21 ma1 a3 a12 a3 a12 a3 a23 ma2 a4 a13 a4 a13 a4 a13 ma3 a5 a14 a5 a14 a5 a14 ma4 a6 a15 a6 a15 a6 a15 ma5 a7 a16 a7 a16 a7 a16 ma6 a8 a17 a8 a17 a8 a17 ma7 a9 a18 a9 a18 a9 a18 ma8 a10 a19 a10 a19 a10 a19 ma9 x x a11 a20 a11 a20 ma10xxxxa12a22 4.6 parity generation/dete ction logic during local dram write cycles, the 82C499 generates a parity bit for each byte of write data from the proces- sor. parity bits are stored into l ocal dram along with each data byte. during a dram read, the parity bit is checked for each data byte. if the logic detects incor- rect parity, the 82C499 will generate nmi to the cpu. the parity error will invoke the nmi, providing that the parity check is e nabled in the configuration register 21h, bit 5. parity check must also be enabled in the port b (61h) register, bits [2:3]. 4.7 refresh logic the 82C499 supports both normal and hidden refresh. normal refresh refers to the classical refresh imple- mentation which places the cpu on hold while a refresh cycle takes place to both the l ocal dram and any at bus memory. this is the default condition at power-up. however, hidden refresh is performed inde- pendent of the cpu and does not suffer from the per- formance restriction of losing processor bandwidth by forcing the cpu into its hold state. hidden refresh delivers higher system perform ance and is recom- mended over normal refresh. as long as the cpu does not try to access local memory or the at bus during a hidden refresh cycle, refresh will be transparent to the cpu. the cpu can continue to execute from its inter- nal and secondary caches as well as execute internal instructions during hidden refresh without any loss in performance due to refresh arbitration. if a local mem- ory or at bus access is required during hidden refresh, wait states will be added to the cpu cycle until the resource becomes available. hi dden refresh also sep- arates refreshing of the at bus and l ocal dram. the dram controller arbitrates between cpu dram accesses and dram refresh cycles, while the at bus controller arbitrates between cpu accesses to the at bus, dma, and at refresh. the at bus controller asserts the rfsh# and memr# commands and out- puts the refresh add ress during at bus refresh cycles. the 82C499 implements refresh cycles to the local dram using cas-before-ras timing. cas-before- ras refresh has lower power consumption than ras- only refresh, which is important when dealing with large memory arrays. cas-before-ras refresh is used for both normal and hidden refresh to l ocal memory. the out put of internal counter 1/timer 1 (out1) inside the 82C499 is programmed as a rate generator to pro- duce the periodic refresh request signal which occurs every 15.9s. requests for refresh cycles are gener- ated by two sources: counter1/timer1, or 16-bit isa masters that activate refresh when they have bus own- ership. these isa masters supply refresh cycles because the refresh controller cannot preempt the bus master to perform the necessary refresh cycles. 16-bit isa masters that hold the bus longer than 15s must supply refresh cycles. by programming config uration register 25h, bit 1, slow refresh is enabled which will further divide the 15.9s period by four to provide a 63.6s slow refresh interval (slow refresh drams must be used with the slow refresh feature). 82C499 pa ge 18 912-3000-001 opti ? 4.8 shadow ram since accesses to local dram are much faster than those to eprom, the 82C499 provides shadow ram capability. with this feature, code from slow devices like rom and eprom memories can be copied to local dram to speed up memory accesses. accesses to the specified eprom space are redirected to the corresponding dram location. shadow ram addresses range from c0000h-fffffh. 16kb granu- larity is provided for the address range c0000h- effffh, while the 64kb range from f0000h-fffffh (the location of system bios) can be shadowed as an entire segment. the shadow ram control is se tup in the configuration registers. first, the rom contents must be copied into the shadow ram area. next, the shadow ram enable bit is set in the configuration register. for the system bios area, once the bit is set, the ram area becomes read-only. for the video and adapter bios area, the user can select read-only or read/write by setting the write protect bit in i ndex register 26h accordingly. video bios at the c0000h-c8000h area can be shad- owed and cached if bit 4 of register 27h is set to 1. system bios at f0000-fffff can also be shadowed if register 22h bit 7 is set to 1. the system bios at f0000-fffff is non-cacheable. 4.9 system rom bios cycles and flash eprom support the 82C499 supports b oth 8- and 16-bit eprom cycles. if the system bios is 16 bits wide, romcs# should be connected to m16# through an open collec- tor gate indicating to the 82C499 that a 16-bit eprom is responding. the system bios resides on the xd bus. the xd to sd data buffer is normally disabled (xdir# inactive) except during i/o read cy cles at addresses below 100h (byte-wide i/o), inta cycles, and 8-bit rom bios cycles. romcs# is generated for the both the e0000-effffh and f0000-fffffh segments. if a combined video/ system rom bios is desired, these two segments should be used. for flash eprom support, register 26h, bit 7, can be set to 1 to enable write cycles for romcs# to support flash eproms. the desired segment must be selected via register 2dh. memory shadowing and caching should be disabled prior to making write accesses to the flash eprom. 4.10 at bus state machine the at bus state machine gains control when the 82c49 9's decoding logic detects a non-l ocal memory cycle. it monitors status signals m16#, io16#, chrdy, and nows# and performs the n ecessary synchroniza- tion of control and status signals between the at bus and the microprocessor. the 82C499 supports 8- and 16-bit memory and i/o devices located on the at bus. an at bus cycle is initiated by asserting ale in at-ts1 state. on the trailing edge of ale, m16# is sampled for a memory cycle to determine the bus size. it then enters at-tc state and provides the command signal. for an i/o cycle, io16# is sampled after the trailing edge of ale until the end of the command. typically, the wait state for an at 8/16-bit transaction is 5/1, respectively. the command cycle is extended when chrdy is detected inactive, or the cycle is terminated when zero wait state request signal (nows#) from the at bus is active. upon expiration of the wait states, the at state machine terminates itself and passes an inter- nal ready to the cpu state machine for outputting a synchronous rdy# to the cpu. bit 2 of index register 20h allows for the addition of an at cycle wait state; bit 3 of this same register allows for the generation of a single ale instead of multiple ales during bus conver- sion cycles. the at bus state machine also routes data and address when an at bus master or dma controller accesses memory. 4.11 bus arb itration logic the 82C499 provides arbitration between the cpu, dma controller, at bus masters, and the refresh logic. during dma, at bus master, and conv enti onal refresh cycles, the 82C499 ass erts hold to the cpu. the cpu will respond to an active hold signal by generat- ing hlda (after completing its current bus cycle) and placing most of its output and i/o pins in a high imped- ance state. after the cpu relinquishes the bus, the 82C499 responds by issuing rfsh# (refresh cycle) or hlda (at bus master or dma cycle), depending on the requesting device. during hidden refresh, hold remains negated and the cpu continues its current program execution as long as it services internal requests or achieves cache hits (please refer to the refresh section for additional i nformation). the at bus controller in the 82C499 arbitrates between hold and refresh requests, deciding which will own the bus once the cpu relinquishes control with the hlda signal. the arbitration between refresh and dma/master is based on a fifo (first in-first out) prior- ity. however, a refresh request (rfsh#) will be inter- 82C499 912-3000-001 page 19 opti ? nally latched and serviced immediately after dma/ master finishes its request if queued behind hrq. hrq must remain active to be serviced if a refresh request comes first. dma and bus masters share the same request pin, hrq. 4.12 numeric coprocessor cycles (npx) the 82C499 monitors nperr# and npbusy# to pro- vide support for the 80387 coprocessor. a coprocessor asserts nperr# during a power-on reset to indicate its presence. the coprocessor ass erts npbusy# while executing a floating-point calculation and asserts rdyi# to the chipset when it is finished. if npbusy# is active and a coprocessor error occurs, (coprocessor asserts nperr#) the 82C499 latches npbusy# and generates int13. latched busy# and int13 can be cleared by an i/o port f0h write command. if the npu is not installed, the 82C499 treats any access to the npu address space as an at cycle. with the npu in place, cpu accesses to the npu address space are direct, except for the re-synchronizing of the numerics coprocessor ready signal (rdyi#) before sending ready# back to the cpu. 4.13 local bus interface the 82C499 allows periph eral devices to share the local bus with the cpu and numerics coprocessor. the performance of these devices (which may include the video subsystem, hard disk adapters, lan and other pc/at controllers) will dramatically increase when allowed to operate in this high-speed environ- ment. these devices are responsible for their own address and bus cycle decode and must be able to operate compatibly at the elevated frequencies required for op eration on the l ocal cpu bus. the ldev# input signal to the 82C499 indicates that a local device is in tercepting the current cycle. if this sig- nal is sampled at the end of the first t2 clock cycle (end of the second t2 at 50mhz, whenever atclk = clki/ 6), then the 82C499 will allow the responding l ocal device to assume responsibility for the current local cycle. when the device has completed its operation, it must terminate the cycle by asserting the rdyi# pin of the 82C499. the rdyi# signal is synchronized by the 82C499 before being sent to the cpu via the rdy# line. alternatively, the l ocal bus device may drive rdy# directly to the cpu. in this case, the l ocal ready sig- nal should be connected to the cpu and 82C499 ready signal. the 82C499 ready signal is bidirec- tional. 4.14 data bus conversion/data path control logic the 82C499 per forms data bus conv ersion w hen the cpu accesses 16- or 8-bit devices through 16- or 32- bit instructions. it also handles dma and at master cycles that transfer data between local dram or cache memory and locations on the at bus. the 82C499 pro- vides all of the signals to control external bidirectional data buffers. 4.15 turbo/slow mode operations turbo mode is controlled through pin 99 of 82C499. if the turbo input is asserted hi gh, (the jumper on the board is opened) the system w ill always run at full speed and non-turbo (slow) mode when the turbo input is pulled low (jum per is closed). slow mode oper- ation is implemented by applying a periodic clock to the hold input of the cpu. osc12 is the clock source used for this operation. osc12 is internally derived from the 14. 31818mhz osc clock input to the 82C499. the hold is maintained for approximately two-thirds of the time, while the cpu is allowed to perform normal external op erations during the remaining one-third interval. for system design, the turbo pin should be pulled high through a 10kohm resistor. 4.16 fast gatea20 and reset emula- tion the 82C499 will intercept commands to p orts 60h and 64h so that it can emulate the keyboard controller, allowing the generation of the fast gatea20 and fast cpurst signals. the decode sequence is software transparent and requires no bios modifi cations to function. the fast gatea20 gen eration sequ ence involves writing d1h to port 64h, then writing data 02h to port 6 0h. the fast cpu warm reset function is generated when a port 64h write cycle with data feh is decoded. a write to port 64h with data d0h will enable the status of gatea20 (bit 1 of p ort 60h) and the warm reset (bit 0 of port 60h) to be readable. 4.17 special cycles the 486 microprocess ors provide special bus cycles to indicate that certain instructions have been executed, or certain conditions have occurred internally. s pecial cycles such as shutdown and halt cycles are covered by dedicated handling logic in the 82C499. based on the operating mi croprocessor mode, this logic decodes the cpu bus status signals m/io#, d/c# and w/r# and takes the appropriate action. 82C499 pa ge 20 912-3000-001 opti ? 82C499 912-3000-001 page 21 opti ? 5.0 registers descriptions table 5-1 control register 1 - index: 20h table 5-2 control register 2 - index: 21h bit(s) default function 7:6 00 revision of 82C499 and is read-only. 5 0 burst wait state control: 1 = secondary cache read-hit cycle is x-2-2-2. 0 = secondary cache read-hit cycle is x-1-1-1. no effect on intel 386, ibm/cyrix 486dlc. 4 0 at clock source selections: 0 = source from clk2i 1 = source from clk1 3 0 single ale enable: 82C499 will activate single ale instead of multiple ales during bus conversion cycle if this bit is enabled. 0 = disable 1 = enable 2 0 extra at cycle wait state enable: insert one extra wait state for the command signals in standard at bus cycle. 0 = disable 1 = enable 1 0 emulation keyboard reset control: 1 = cpu reset is generated immediately after a write to port 64h. 0 = a halt instruction needs to execute after a write to port 64h in order to cause a cpu reset. 0 0 fast reset: the 82C499 generates a cpu reset whenever a halt inst ruction is executed. 0 = disable 1 = enable bits default function 7 0 master mode byte swap enable: 0 = disable 1 = enable 6 0 cache write wait states control 1 = 2 wait states, bit 1 of index register 21h will be ignored 0 = either 0 or 1 wait state, refer to bit 1 of index register 21h 5 0 parity check: 0 = enable 1 = disable 4 0 cache enable: 0 = cache is disabled and dram burst mode is enabled 1 = cache enable and dram burst mode is disabled 3:2 00 cache size: 3 2 cache size 0064kb 01128kb 10256kb 11512kb 1 00 cache write 0/1 wait state control with bit 6 of index register 21h = 0: 0 = 1 wait state 1 = 0 wait state 82C499 pa ge 22 912-3000-001 opti ? table 5-3 shadow ram control register i - index: 22h table 5-4 shadow ram control register ii - index: 23h 0 00 cache read wait state control: for intel 486: 0 = 3-x-x-x cycle 1 = 2-x-x-x cycle for intel 386, ibm/cyrix 486dlc: 0 = 1ws 1 = 0ws bit(s) default function 7 1 rom(f0000-fffffh) enable: 1 = read from rom, write to dram. romcs# is generated during read access only. 0 = read/write on dram and dram is write-protected. 6 0 shadow ram at d0000h-dffffh area: 0 = disable 1 = enable 5 0 shadow ram at e0000h-effffh area: 0 = disable shadow ram, enable romcs#. the e0000-effffh rom is defaulted to reside on xd bus. 1 = enable shadow ram and disable romcs# generation. 4 0 shadow ram at d0000h-dffffh area write protect enable: 0 = disable 1 = enable 3 0 shadow ram at e0000h-effffh area write protect enable: 0 = disable 1 = enable 2 1 hidden refresh enable (without holding cpu): 1 = disable 0 = enable. 1 0 fast gatea20/a20m#: intel 386 mode: i ntel486 ibm/cyrix 486dlc mode: 1 = ga20 is high 1 = a20m# is always high, no address wraps around 0 = controlled by keyboard emulation 0 = controlled by keyboard emulation 0 0 slow refresh enable (four times slower than the normal refresh) 0 = disable 1 = enable bit default function 7 0 shadow ram at ec000h-effffh area: 0 = disable 1 = enable 6 0 shadow ram at e8000h-ebfffh area: 0 = disable 1 = enable 5 0 shadow ram at e4000h-e7fffh area: 0 = disable 1 = enable 4 0 shadow ram at e0000h-e3fffh area: 0 = disable 1 = enable bits default function 82C499 912-3000-001 page 23 opti ? table 5-5 dram control register i - index: 24h table 5-6 dram control register ii - index: 25h 3 0 shadow ram at dc000h-dffffh area: 0 = disable 1 = enable 2 0 shadow ram at d8000h-dbfffh area: 0 = disable 1 = enable 1 0 shadow ram at d4000h-d7fffh area: 0 = disable 1 = enable 0 0 shadow ram at d0000h-d3fffh area 0 = disable 1 = enable bit(s) default function 7 1 0 = 256kb dram mode 1 = 1mb and 4mb dram mode. see table 4, dram configurations, on page 16. 6:4 000 dram types used for bank 0 and bank 1. refer to table 4-4 for detailed description. 3 0 unused 2:0 111 dram types used for bank 2 and bank 3. refer to table 4-4 for detailed description. bit(s) default function 7:6 11 cas# wait state control for dram read cycle: cas# pusle 7 6 width cycle timenotes 0 0 n/a n/a not used. 0 1 3 clks 7-5-5-5 cas# will shift later by 1 clk and the cas# pulse width will increase by 1 clk 1 0 4 clks 8-6-6-6 only cas# pulse width increases 1 1 5 clks 9-7-7-7 only cas# pulse width increases 5:4 11 cas# wait state control for dram write cycle: cas# pulsecas#cycle 5 4 width prechargetime 0 0 2 clks 1 clk 6-3-3-3 0 1 2 clks 3 clks 8-5-5-5 1 0 3 clks 3 clks 9-6-6-6 1 1 4 clks 3 clks 10-7-7-7 3 0 fast decode enable. this function may be enabled in 20/25mhz operation to speed up the dram access. 0 = disable fast decode, dram base wait states is not changed 1 = enable fast decode, dram base wait states is decreased by 1 this bit is automatically disabled even when it is set to 1 when bit 4 of index register 21h (cache enable bit) is enabled. it only affects the dram lead-off cycle. 2 0 cas# delay for dma/master cycles: 0 = disable - cas# will be generated one cpuclk after ras# is asserted. 1 = enable - cas# will be generated after ras# is asserted for two cpuclks. bit default function 82C499 pa ge 24 912-3000-001 opti ? table 5-7 shadow ram control register iii - index: 26h table 5-8 control register 3 - index: 27h 1:0 00 atclk selection (refer to bit 4 of index register 20h): 1 0 atclk selection 0 0 clki/6 (default, indicate 82C499 is running at 50mhz, ldev# will be sampled at the end of the second t2) 0 1 clki/5 1 0 clki/4 1 1 clki/3 bit(s) default function 7 0 enable romcs# for write cycles: 1 = enable, generates romcs# for write cycles to s upport flash roms. 0 = disable 6 0 shadow ram copy enable for address area c0000h-cffffh: 0 = read/write at at bus 1 = read from at bus and write into shadow ram 5 0 shadow write protect at address area c0000h-cffffh: 0 = write protect disable 1 = write protect enable 4 0 shadow ram enable at c0000h-cffffh area: 0 = disable 1 = enable 3 0 enable shadow ram at cc000h- cffff area: 0 = disable 1 = enable 2 0 enable shadow ram at c8000h- cbfff area: 0 = disable 1 = enable 1 0 enable shadow ram at c4000h-c7fffh area: 0 = disable 1 = enable 0 0 enable shadow ram at c0000h-c3fffh area: 0 = disable 1 = enable bit(s) default function 7 1 global cache enable: this bit determines whether all cycles are cacheable in l1 and l2 cache. 0 = disable l1 and l2 cache 1 = enable l1 and l2 cache 6 1 fast at cycle: 0 = disable, bale# will be asserted 1 atclk late as standard at cycles 1 = enable, standard at cycles 5 0 back-to-back i/o delay control: 0 = three blk back-to-back i/o delay 1 = zero back-to-back i/o delay 4 1 video bios at c0000h-c8000h area non-ca cheable: 0 = cacheable 1 = non-cacheable bit(s) default function 82C499 912-3000-001 page 25 opti ? note memory area at 640kb-1mb is defaulted to be non-cacheable. table 5-9 non-cacheable block 1 register - index: 28h this register is used in conju nction with index register 29h to define a non-cacheable block. the st arting address for the non-cacheable block must have the same granularity as the block size. for example, if a 512kb non- cacheable block is selected, its st arting address is a multiple of 512kb; cons equently, only address bits of a[23:19] are significant, a18:16] are "don't care". table 5-10 non-cacheable block 1 register ii - index: 29h 3:0 0001 cacheable address range for local me mory: 3210cac heable address range 0000 0-64mb 0001 0-4mb 0010 0-8mb 0011 0-12mb 0100 0-16mb 0101 0-20mb 0110 0-24mb 0111 0-28mb 1000 0-32mb 1001 0-36mb 1010 0-40mb 1011 0-44mb 1100 0-48mb 1101 0-52mb 1110 0-56mb 1111 0-60mb note if total memory is 1mb or 2mb, the cacheable range is 0-1 or 0-2mb respectively and independent of the value of bits [3:0] of i ndex register 27h. bit(s) default function 7:5 100 size of non-cachable memory block 1: 7 6 5 block size 00064kb 001128kb 010256kb 011512kb 1 xxdisabled 4:2 000 unused 1:0 00 address bits of a25 and a24 of non-cachable me mory block 1 bit(s) default function 7:0 0001 xxxx address bits a[23:16] of non-cacheable me mory bl ock 1 valid starting address bits block size a23 a22 a21 a20 a19 a18 a17 a16 64kb vvvvvvvv 128kb vvvvvvvx 256kb vvvvvvxx 512kb vvvvvxxx bit(s) default function 82C499 pa ge 26 912-3000-001 opti ? x = don't care v = valid bit table 5-11 non-cacheable block 2 register i - index: 2ah this register is used in conjunction with index register 2bh to define a non-cach eable block. the starting address for the non-cacheable block must have the same granularity as the block size. for example, if a 512kb non- cacheable block is selected, its st arting address is a multiple of 512kb; cons equently, only address bits of a[23:19] are significant, [a18:16] are "don't care". table 5-12 non-cacheable block 2 register ii - index: 2bh x = don't care v = valid bit table 5-13 rom chip select (romcs#) control register - index: 2dh bit(s) default function 7:5 100 size of non-cacheable memory block 2: 765block size 0 0 0 64kb 0 0 1 128kb 0 1 0 256kb 0 1 1 512kb 1 x x disabled 4:3 00 ecawe#/ocawe# pulse wi dth for master cache write-hit cycles: 43selections 0 0 3 clks (default) 1 0 1 clk 1 1 unused 0 1 unused 2 0 unused, must be set to 1 by bios. 1:0 0 address bits of a25 and a24 of non-cacheable memory block 2 bit(s) default function 7:0 0001 xxxx address bits a[23:16] of non-cacheable me mory block 2 valid starting address bits block size a23 a22 a21 a20 a19 a18 a17 a16 64kb vvvvvvvv 128kb vvvvvvvx 256kb vvvvvvxx 512kb vvvvvxxx bit(s) default function 7 0 unused 6 1 0 = ibm 486dlc cpu. this bit is write -only. note: this bit must be cleared to 0 by the bios to support the ibm 486dlc (blue lightning) cpu. 5 0 enable romcs# at e8000h-effffh segment: 0 = disable 1 = enable 82C499 912-3000-001 page 27 opti ? 5.1 i/o port 60h port 60h and 64h emulate the registers of a keyboard con troller, allowing the ge neration of a fast gate a20 si gnal. the sequence here is bios transparent and there is no need for the modification of the current bios. the sequence involves writing data d1h to port 64h, then writing data 02h to port 60h. table 5-14 i/o port 61h(port b) 5.2 i/o port 64h i/o port 64h emulates the register inside a keyboard controller by generating a fast reset pulse. writing d ata feh to port 64h asserts the reset pulse. the pulse is generated immediately after the i/o write if bit 6 of index register 21h is set, otherwise the pulse is asserted 2s after the write. table 5-15 i/o port 70h table 5-16 port 92h - system controller port a, ps/2 compatibility port 4 0 enable romcs# at e0000h-e7fffh segment: 0 = disable 1 = enable 3 0 enable romcs# at d8000h-dffffh segment: 0 = disable 1 = enable 2 0 enable romcs# at d0000h-d7fffh segment: 0 = disable 1 = enable 1 0 enable romcs# at c8000h-cffffh segment: 0 = disable 1 = enable 0 0 enable romcs# at c0000h-c7fffh segment: 0 = disable 1 = enable bit(s) type function 0 r/w timer 2 gate 1 r/w speaker output enable 2 r/w parity check enable 3 r/w i/o channel check enable 4 r refresh detect 5 r timer out2 detect 6 r i/o channel check 7 r system parity check bit(s) default function 7 0 nmi enable bit(s) default function 1 1 = set alernate fast gatea20 active 0 1 = set alternate fast reset active 82C499 pa ge 28 912-3000-001 opti ? 82C499 912-3000-001 page 29 opti ? 6.0 maximum ratings stresses above those listed in the following tables may cause perm anent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. 6.1 absolute maximum ratings 6.2 dc characteristics ta = -25c to +70c , vcc = 5.0v 5% symbol parameter min max unit v cc supply voltage +6.5 v v i input voltage -0.5 v cc + 0.3 v v o output voltage -0.5 v cc + 0.3 v t op operating temperature -25 +70 c t stg storage temperature -40 +125 c symbol parameter min max unit condition v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc + 0.3 v v ol output low voltage 0.4 v l ol = 4.0ma v oh output high voltage 2.4 v i oh = -1.6ma i il input leakage current 10 a v in = v cc i oz tristate leakage current 10 a c in input capacitance 10 pf c out output capacitance 10 pf i cc power supply current 80 ma 82C499 pa ge 30 912-3000-001 opti ? 6.3 ac timing characteristics preliminary - temperature: 0c to +70c, vcc: 5v +/- 5% table 6-1 82C499 b1 ac characteristics sym description min typ max units t100a clki delay from clk2i 37ns t100b clki a delay from clk2i 37ns t103 cpurst active delay from clki 420ns t103a cpurst active delay from clk2i 37ns t104 cpurst inactive delay from clki 420ns t104a cpurst inactive delay from clk2i 37ns t201 clki to cas# active delay, refresh 7 21 ns t202 clki a to cas# inactive delay, refresh 7 21 ns t203 clki or clki a to ras# active delay, refresh 7 21 ns t204 clki or clki a to ras# inactive delay, refresh 7 21 ns t205 ras# pulsh width, refresh 4clks t206 cas# pulsh width, refresh 5.5clks t210 ldev# setup time to clki 4ns t211 ldev# hold time to clki 5ns t213 ken# active delay from clki 15 ns t214 ken# inactive delay from address 20 ns t215 rdyi# setup time to clki 4ns t216 rdyi hold time to clki 5ns t301 d(31:0) valid to sd(15:0) valid delay 10 100 ns t302 d(31:0) valid to mp(3:0) valid delay 15 30 ns t303 d(31:0) invalid to sd(15:0) invalid delay 10 25 ns t304 d(31:0) invalid to mp(3:0) invalid delay 15 30 ns t305 sd(15:0) valid to d(31:0) valid delay 10 20 ns t306 sd(15:0) invalid to d(31:0) invalid delay 10 20 ns t313 a(9:0) to kbdcs# active delay 10 100 ns t314 a(9:0) to kbdcs# inactive delay 10 30 ns t402 cpu address and status valid to beoe# active delay 5 21 ns t403 clki to beoe# /booe# inactive delay 5 13 ns t404 clki to beoe#/booe# active delay 5 14 ns t405 clki to ca32s# inactive delay 5 14 ns t406 clki to ca32s# active delay 5 14 ns t407 clki (from tag address valid) to brdy# active delay 5 (9) 15 (15) ns t408 clki to brdy# inactive delay 5 15 ns t411 clk2i to ecaw e#/ocawe# active delay, 0ws (requires 2x clock input) 510ns t412 clk2i to ecaw e#/ocawe# inactive delay, 0ws (requires 2x clock input) 510ns t413 clki a to ecaw e#/ocawe# active delay, 1ws 20 22 ns 82C499 912-3000-001 page 31 opti ? t413a clki to ecawe#/ ocawe# active delay, cache line fill 7 21 ns t414 clki a to ecawe#/ ocawe# i nactive delay, 1ws 10 12 ns t414a clki /clki a to ecawe#/ocawe# inactive delay, cache line fill 7 21 ns t415 clk2i to dtywe# active delay, 0ws (requires 2x clock input) 5 10 ns t416 clk2i to dtywe# inactive delay, 0ws (requires 2x clock input) 5 10 ns t417 clki a to dtywe# active delay, 1ws 20 22 ns t418 clki a to dtywe# inactive delay, 1ws 10 12 ns t419 clki (from tag address valid) to rdy# active delay 5 (9) 15 (15) ns t420 clki to rdy# inactive delay 5 15 ns t421 dtywe# active to drty active 2 4 ns t422 dtywe# inactive to drty inactive 2 4 ns t423 clki a to tagwe# active delay 20 22 ns t424 clki a to tagwe# inactive delay 10 12 ns t425 clki to bea3/bea2oa3 active delay, cache hit (cache line fill) 5 (7) 15 (21) ns t425a clki a to bea3/bea2oa3 active delay, cache hit 5 15 ns t426 clki to bea3/bea2oa3 hi-z 5 15 ns t427 tagwe# active to tag data active 2 4 ns t428 tagwe# inactive to tag data inactive 2 4 ns t429 clki to cas# active delay 5 15 ns t430 clki to cas# inactive delay 5 15 ns t433 clki to ras# inactive delay 5 15 ns t434 clki to ras# active delay 5 15 ns t435 clki to column address valid delay 5 15 ns t436 cpu address valid to row/column address valid delay 5 15 ns t437 clki to dwe# active delay 5 15 ns t438 clki a to dwe# inactive delay 5 15 ns t439 clki to new row address delay 10 25 ns t440 ras# precharge time 3 clki t441 cas# precharge time 1 clki t442 clki to romcs# active delay 7 21 ns t443 clki to romcs# inactive delay 7 21 ns t454 memr# active to beoe#/booe# active delay, dma 10 20 ns t455 memr# inactive to beoe#/booe# inactive delay, dma 10 20 ns t456 clki to eads# active delay, dma 6 18 ns t457 clki to eads# inactive delay, dma 6 18 ns t458 memr#/ memw# active to ras# active delay, dma 10 20 ns t459 memr#/ memw# inactive to cas# inactive delay, dma 10 20 ns t465 memw# active to dwe# active delay, dma 10 20 ns t466 memw# inactive to dwe# inactive delay, dma 10 20 ns t467 drty set up time to clki 4ns table 6-1 82C499 b1 ac characteristics (cont.) sym description min typ max units 82C499 pa ge 32 912-3000-001 opti ? note notes: 1. means rising edge note 2. a means falling edge note 3.the capacitance loading is 50pf t468 drty hold time to clki 5ns t501 bclk a to ale active delay 2 20 ns t502 bclk to ale inactive delay 2 20 ns t503 bclk a to cmd active delay 2 20 ns t504 bclk to cmd inactive delay 2 20 ns t505 bclk to cmd active delay 2 20 ns t506 mcs16# to bclk setup time 10 ns t507 mcs16# to bclk hold time 10 ns t508 iocs16# to bclk setup time 10 ns t509 iocs16# to bclk hold time 10 ns t510 ows# to bclk a setup time 10 ns t511 ows# to bclk a hold time 20 ns t512 chrdy to bclk setup time 10 ns t513 chrdy to bclk hold time 20 ns t515 clk to hold active delay 7 21 ns t516 clk to hold inactive delay 7 21 ns t517 bclk to ref# active delay 8 30 ns t518 bclk to ref# inactive delay 8 30 ns t519 bclk to memr# active delay, refresh 5 25 ns t520 bclk to memr# inactive delay, refresh 5 25 ns t521 bclk to sa[1:0] active delay 7 21 ns t522 bclk to sa[1:0] inactive delay 7 21 ns t523 cmd# active to xdir# active delay 5 15 ns t524 cmd# inactive to xdir# inactive delay 5 15 ns t530 clk to ads# active delay, dma 6 18 ns t531 clk to ads# inactive delay, dma 6 18 ns t532 memr#/memw# active to m/io valid delay, dma 7 21 ns t533 memr#/memw# i nactive to m/io invalid delay, dma 7 21 ns t534 memr#/memw# active to w/r valid delay, dma 7 21 ns t535 memr#/memw# i nactive to w/r invalid delay, dma 7 21 ns t536 lreq# se tup time to clk 4ns t537 lreq# hold time to clk 5ns t538 hlda setup time to clk 4ns t539 hlda hold time to clk 5ns t540 clk to lgnt# active delay 10 25 ns table 6-1 82C499 b1 ac characteristics (cont.) sym description min typ max units 82C499 912-3000-001 page 33 opti ? 6.4 ac timing waveforms figure 6-1 2-1-1-1 double bank cache read hit cycle a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t402 t403 t404 t403 t404 t403 t404 t403 t402 t406 t405 t406 t405 t426 t425a t425 t426 t425a t426 t425a t425 t426 t425a t425 t407a t408 t407 t408 t1 t2 t2 t2 t2 t2 t1 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] booe# beoe# ca32s# bea3 bea2oa3 brdy# ecawe#/ocawe# tagwe# drtyw# drty rdy# 82C499 pa ge 34 912-3000-001 opti ? figure 6-2 3-1-1-1 single bank cache read hit cycle a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t403 t406 t425 t426 t425 t425 t426 t407 t408 t407 t408 t407 t408 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] booe# beoe# ca32s# bea3 bea2oa3 brdy# ecawe#/ocawe# tagwe# drtyw# drty rdy# 82C499 912-3000-001 page 35 opti ? figure 6-3 zero-wait state write hit cycle aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t411 t412 t415 t416 t421 t422 t419 t420 t407 t408 t1 t2 t1 clk2 clki ads# mio, dc, wr, a[31..2] ecawe#/ocawe# drtyw# drty (from '499) tagwe# rdy# brdy# 82C499 pa ge 36 912-3000-001 opti ? figure 6-4 one-wait state cache write hit cycle a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t413 t414 t417 t418 t421 t422 t419 t420 t407 t408 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ecawe#/ocawe# drtyw# drty (from '499) tagwe# rdy# brdy# 82C499 912-3000-001 page 37 opti ? figure 6-5 dma/isa master transfer aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a t458 t433 t439 t435 t429 t459 t429 t459 t454 t455 t465 t466 t456 t457 t413a t414a t413a t414a t456 t457 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t bit 2 of 25h = 0, default bit 2 of 25h = 1 dma/isa master read from dram, ras# & cas# are generated dma/isa master read from cache, only booe#/beoe# is generated only dma/isa master write to dram, with ras#, cas# generated as above and the dwe# dma/isa master write to dram & cache, with ras#, cas#, dwe# generated as above and ecawe#/ocawe# only for isa master when bit 4,3 of 2a =1 default for isa master (bit 4, 3 of 2a = 00and dma t2 t2 t2 t2 clk2 clki atclk ior#/iow# memr#/memw# ras#x ma[10:0] cas[3:0]# cas[3:0]# booe#/beoe# dwe# eads# ecawe#/ocawe# ecawe#/ocawe# eads# 82C499 pa ge 38 912-3000-001 opti ? figure 6-6 one-wait state dram read aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a t433 t434 t433 t434 t429 t430 t429 t430 t429 t430 t436 t439 t435 t436 t439 t435 t436 t419 t420 t419 t420 t419 t420 t1 t2 t2 t2t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t1 t2 page miss t2 t2 t2 t2 page miss page hit t2 t2 t2 t2t2 t2 t2t2 clk2 clki ads# mio, dc, wr, a[31..2] ras0# ras1# cas[3:0]# ma[10:0] dwe# blast# rdy# brdy# different banks 82C499 912-3000-001 page 39 opti ? figure 6-7 one-wait state dram page hit burst read a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a t429 t430 t429 t430 t429 t430 t429 t430 t436 t435 t435 t436 t419 t420 t419 t420 t419 t420 t419 t420 ti ti ti ti ti t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 ti ti t2 t2 t2 t2t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ras0# cas[3:0]# ma[10:0] dwe# blast# brdy# rdy# 82C499 pa ge 40 912-3000-001 opti ? figure 6-8 one-wait state dram burst read, ras# inactive a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t434 t429 t430 t429 t430 t429 t430 t429 t430 t436 t435 t435 t435 t436 t419 t420 t419 t420 t419 t420 t419 t420 ti ti ti t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 ti ti t2 t2 t2 t2t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ras0# cas[3:0]# ma[10:0] dwe# blast# brdy# rdy# 82C499 912-3000-001 page 41 opti ? figure 6-9 one-wait state dram page miss burst read a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t433 t434 t429 t430 t429 t430 t429 t430 t429 t43 0 t436 t439 t435 t435 t435 t436 t419 t420 t419 t420 t419 t420 t419 t42 0 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 ti t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ras0# cas[3:0]# ma[10:0] dwe# blast# brdy# rdy# 82C499 pa ge 42 912-3000-001 opti ? figure 6-10 zero-wait state dram write a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t433 t434 t433 t434 t429 t430 t429 t430 t429 t430 t436 t439 t435 t436 t439 t435 t436 t437 t438 t437 t438 t437 t438 t419 t420 t419 t420 t419 t420 t1 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t1 t2 page miss t2 t2 t2 t2 page miss page hit clk2 clki ads# mio, dc, wr, a[31..2] ras0# ras1# cas[3:0]# ma[10:0] dwe# rdy# brdy# different banks 82C499 912-3000-001 page 43 opti ? figure 6-11 one-wait state dram write a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t433 t434 t433 t434 t429 t430 t429 t430 t429 t430 t436 t439 t435 t436 t439 t435 t436 t437 t438 t437 t438 t437 t438 t419 t420 t419 t420 t419 t420 t1 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t1 t2 page miss t2 t2 t2 t2 page miss page hit t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ras0# ras1# cas[3:0]# ma[10:0] dwe# rdy# brdy# different banks 82C499 pa ge 44 912-3000-001 opti ? figure 6-12 isa bus cycles a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t506 t507 t508 t509 t510 t511 t512 t513 t501 t502 t503 t504 t419 t420 t505 t504 t503 t504 t419 t420 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 one more atclk delay if at extra ws is set 8-bit isa bus cycles bale will be generated 1 atclk late if fast at cycle option is disabled 16-bit isa bus cycles one more atclk delay if at extra ws is set 0ws#, iochrdy will be sampled the same way as in the 8-bit cycle clk2 clki atclk ads# mio, dc, wr, a[31..2] bale 8 -bit isa bus cmd#s mcs16# iocs16# 0ws# iochrdy rdy# 16-bit memr#/memw# 16-bit ior#/iow# mcs16# iocs16# rdy# one more atclk delay if at extra ws is set 82C499 912-3000-001 page 45 opti ? figure 6-13 keyboard controller access cycles a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t501 t502 t523 t524 t313 t314 t503 t504 t419 t420 t1 t2t2 t2t2 t2t2 t2 t2 t2 t2 t2t2 t2t2 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2t2 t2 t2 clk2 clki atclk ads# mio, dc, wr, a[31..2] sa[9:2] bale xdir# kbcs# ior#/iow# rdy# 82C499 pa ge 46 912-3000-001 opti ? figure 6-14 cpu reset a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t103a t104a t103 t104 ti ti ti ti f1 f2 f1 f2 f1 f2 f1 f2 ti ti ti ti f1 f2 f1 f2 f1 f2 f1 f2 cpurst for 2x clock cpus cpurst for 1x clock cpus clk2 clki cpurst clk2 clki cpurst clk2 clki cpurst clk2 clki cpurst 82C499 912-3000-001 page 47 opti ? figure 6-15 refresh cycle a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t206 t206 t205 t205 t201 t202 t204 t203 t204 t204 t203 t204 t204 t203 t204 t204 t203 t204 ti ti ti ti ti ti ti ti ti ti ti ti ti t2 t clk2 clki cas[3:0]# ras0# ras1# ras2# ras3# 82C499 pa ge 48 912-3000-001 opti ? figure 6-16 cache read miss dirty: 2 banks of cache and 0/0 dram wait state (1 of 2) 82C499 912-3000-001 page 49 opti ? figure 6-17 cache read miss dirty: 2 banks of cache and 0/0 dram wait state (2 of 2) a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa t406 t405 t426 t425a t426 t425a t402 t403 t404 t403 t404 t403 t404 t403 t437 t438 t436 t439 t435 t435 t435 t435 t433 t434 t43 t429 t430 t429 t430 t429 t430 t429 t430 t417 t418 t421 t422 t423 t424 t427 t428 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 pa ge 50 912-3000-001 opti ? figure 6-18 cache read miss dirty: 1 bank of cache and 0/0 dram wait state (1 of 2) a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t425 t425 t425 t425 t407 t408 t407 t408 t413a t414a t413a t414a t413a t414a t413a t414a t404 t403 t404 t403 t404 t403 t439 t435 t435 t435 t435 t435 t434 t429 t430 t429 t430 t429 t430 t429 t430 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 912-3000-001 page 51 opti ? figure 6-19 cache read miss dirty: 1 bank of cache and 0/0 dram wait state (2 of 2) a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa t406 t405 t426 t425a t425 t426 t425a t425 t425 t425 t402 t403 t437 t438 t436 t439 t435 t435 t435 t435 t433 t434 t43 t429 t430 t429 t430 t429 t430 t429 t430 t417 t418 t421 t422 t423 t424 t427 t428 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 pa ge 52 912-3000-001 opti ? figure 6-20 cache read miss dirty: 2 banks of cache and 1/1 dram wait state (1 of 2) aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t425 t425 t425 t425 t425 t425 t425 t425 t407 t408 t407 t408 t407 t408 t407 t408 t413a t414a t413a t414a t413a t414a t413a t414a t404 t403 t439 t435 t435 t435 t435 t435 t434 t429 t430 t429 t430 t429 t430 t429 t430 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 912-3000-001 page 53 opti ? figure 6-21 cache read miss dirty: 2 banks of cache and 1/1 dram wait state (2 of 2) aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaa aaa t406 t405 t426 t425a t425 t426 t425a t425 t413a t402 t403 t404 t403 t404 t403 t404 t403 t437 t438 t436 t439 t435 t435 t435 t435 t439 t435 t433 t434 t429 t430 t429 t430 t429 t430 t429 t430 t429 t417 t418 t421 t422 t423 t424 t427 t428 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 pa ge 54 912-3000-001 opti ? figure 6-22 cache read miss dirty: 1 bank of cache and 1/1 dram wait state (1 of 2) a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa 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aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa 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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t425 t425 t425 t425 t407 t408 t407 t408 t413a t414a t413a t414a t414a t413a t414a t404 t403 t404 t403 t404 t403 t435 t435 t435 t435 t430 t429 t430 t429 t430 t429 t430 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 912-3000-001 page 55 opti ? figure 6-23 cache read miss dirty: 1 bank of cache and 1/1 dram wait state (2 of 2) a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 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aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t405 t426 t425a t425 t426 t425a t425 t425 t425 t402 t403 t437 t438 t436 t439 t435 t435 t435 t435 t433 t429 t430 t429 t430 t429 t430 t429 t430 t417 t418 t421 t422 t423 t424 t427 t428 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 pa ge 56 912-3000-001 opti ? figure 6-24 cache read miss not dirty: 2 banks of cache and 0 dram read wait state aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 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aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t425 t425 t425 t425 t425 t425 t425 t425 t407 t408 t407 t408 t407 t408 t407 t408 t413a t414a t413a t414a t413a t414a t413a t414a t404 t403 t439 t435 t435 t435 t435 t435 t434 t429 t430 t429 t430 t429 t430 t429 t430 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 912-3000-001 page 57 opti ? figure 6-25 cache read miss not dirty: 2 banks of cache and 1 dram read wait state a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t405 t406 t426 t425a t425 t425 t425 t426 t425a t425 t425 t425 t407 t408 t407 t408 t413a t414a t413a t414a t413a t414a t413a t414a t402 t403 t404 t403 t404 t403 t404 t403 t436 t439 t435 t435 t435 t435 t435 t433 t434 t429 t430 t429 t430 t429 t430 t429 t430 t421 t422 t427 t428 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 pa ge 58 912-3000-001 opti ? figure 6-26 rom access cycle (1 of 2) a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 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aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t406 t405 t406 t426 t425 t425 t425 t426 t425 t425 t425 t407 t408 t407 t408 t413a t414a t413a t414a t413a t414a t413a t414a t402 t403 t404 t403 t404 t403 t404 t403 t436 t439 t436 t436 t436 t436 t436 t433 t434 t429 t430 t429 t430 t429 t430 t429 t430 t421 t422 t427 t428 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 clk2 clki ads# mio, dc, wr, a[31..2] ca32s# bea3 bea2oa3 brdy# ecawe# ocawe# beoe# booe# dwe# ma[10:0] rasx# cas[3:0]# rdy# drtyw# drty (from '499) tagwe# tag[7:0] (from '499) 82C499 912-3000-001 page 59 opti ? figure 6-27 rom a ccess cycle (2 of 2) aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t442 t521 t521 t521 t523 t524 t523 t524 t5 t501 t502 t501 t502 t501 t502 t503 t504 t503 t504 t503 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t1 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t clk2 clki atclk ads# mio, dc, wr, a[31..2] romcs# sa[1:0] xdir# bale memr# rdy# 82C499 pa ge 60 912-3000-001 opti ? figure 6-28 dma device read from vesa slave aa a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t443 t521 t524 t523 t524 t501 t502 t504 t503 t504 t419 t420 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 t2 clk2 clki atclk ads# mio, dc, wr, a[31..2] romcs# sa[1:0] xdir# bale memr# rdy# 82C499 912-3000-001 page 61 opti ? figure 6-29 dma device write to vesa slave a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa a a aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa t215 t216 t210 t211 t530 t531 t532 t533 t534 t535 t505 t504 t505 t504 t542 t543 t419 t420 clk2 clki atclk ads# m/io w/r ldev# eads# iow# memr# iochrdy lrdy# (from vesa slave) rdy# 82C499 pa ge 62 912-3000-001 opti ? figure 6-30 isa master read from vesa slave a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa t215 t216 t210 t211 t530 t531 t532 t533 t534 t535 t456 t457 t505 t504 t505 t504 t542 t543 t419 t420 clk2 clki atclk ads# m/io w/r ldev# eads# ior# memw# iochrdy lrdy# (from vesa slave) rdy# 82C499 912-3000-001 page 63 opti ? figure 6-31 isa master write to vesa slave aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a aa aa a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a t215 t216 t210 t211 t530 t531 t532 t533 t534 t535 t505 t504 t542 t543 t419 t420 clk2 clki atclk ads# m/io w/r ldev# eads# memr# iochrdy lrdy# (from vesa slave) rdy# 82C499 pa ge 64 912-3000-001 opti ? aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aa aa aa aa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa t215 t216 t210 t211 t530 t531 t532 t533 t534 t535 t456 t457 t505 t504 t542 t543 t419 t420 clk2 clki atclk ads# m/io w/r ldev# eads# memw# iochrdy lrdy# (from vesa slave) rdy# 82C499 912-3000-001 page 65 opti ? 7.0 mechnical package outline symbol millimeter inch min nom max min nom max a1 0.05 0.25 0.50 0.002 0.010 0.020 a2 3.17 3.32 3.47 0.125 0.131 0.137 b 0.10 0.20 0.30 0.004 0.008 0.012 c 0.10 0.15 0.20 0.004 0.006 0.008 d 27.90 28.00 28.10 1.098 1.102 1.106 e 27.90 28.00 28.10 1.098 1.102 1.106 e 0.50 0.020 hd 30.35 30.60 30.85 1.195 1.205 1.215 he 30.35 30.60 30.85 1.195 1.205 1.215 l 0.35 0.50 0.65 0.014 0.020 0.026 l1 1.30 0.051 u 0.08 0.003 q 010010 he e eb c a2 a1 u hd d l l1 0.08(0.003) m q 82C499 pa ge 66 912-3000-001 opti ? |
Price & Availability of 82C499
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