HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor product data supersedes data of 2001 jul 19 2004 apr 15 integrated circuits
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2 2004 apr 15 features ? inputs meet jedec hstl std. jesd 86, and outputs meet level iii specifications ? 12 k w pull-up on d and le inputs ? esd classification testing is done to jedec standard jesd22. protection exceeds 2000 v to hbm per method a114. ? latch-up testing is done to jedec standard jesd78, which exceeds 100 ma. ? packaged in 48-pin plastic thin shrink small outline package (tssop48) description the HSTL16919 is a 9-bit to 18-bit d-type latch designed for 3.15 v to 3.45 v v cc operation. the d inputs accept hstl levels and the q outputs provide lvttl levels. the HSTL16919 is particularly suitable for driving an address bus to two banks of memory. each bank of nine outputs is controlled with its own latch-enable (le ) input. each of the nine d inputs is tied to the inputs of two d-type latches that provide true data (q) at the outputs. while le is low the q outputs of the corresponding nine latches follow the d inputs. when le is taken high, the q outputs are latched at the levels set up at the d inputs. the HSTL16919 is characterized for operation from 0 c to +70 c. pin configuration sw00768 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 2q1 1q1 gnd d1 d2 v cc d3 gnd 1le gnd v ref gnd 2le gnd d4 d5 d6 d7 v cc d8 gnd 2q7 1q7 v cc 2q6 1q6 gnd 2q5 1q5 gnd 2q4 1q4 v cc 2q3 1q3 gnd 2q2 1q2 v cc v cc 21 22 23 24 25 26 27 28 d9 gnd 2q9 1q9 v cc v cc 2q8 1q8 ordering information t amb = 0 c to +70 c type number package name description version HSTL16919dgg tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2004 apr 15 3 pin description pin symbol function 4, 5, 7, 8, 16, 17, 18, 20, 21 d[1:9] inputs 2, 46, 43, 40, 37, 34, 31, 28, 24 1q[1:9] out p uts 1, 45, 42, 39, 36, 33, 30, 27, 23 2q[1:9] o u tp u ts 10 1le latch enable 14 2le latch enable 12 v ref reference voltage 6, 19, 25, 26, 32, 41, 47, 48 v cc supply voltage 3, 9, 11, 13, 15, 22, 29, 35, 38, 44 gnd ground logic diagram (positive logic) 2 10 1le 4 d1 1q1 1d c1 1 14 2le 2q1 1d c1 to eight other channels sw00906 12 k w v cc v ref 12 12 k w 12 k w function table inputs output le d q l h h l l l h x q 0 1 note: 1. output level before the indicated steady-state input conditions were established.
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2004 apr 15 4 absolute maximum ratings 1 over operating free-air temperature range (unless otherwise noted). symbol parameter conditions rating unit v cc supply voltage range 0.5 to +4.6 v v i input voltage range 2 0.5 to v cc +0.5 v v o output voltage range 2 0.5 to v cc +0.5 v i ik input clamp current v i < 0 v 50 ma i ok output clamp current 3 v o < 0 v or v o > v cc 50 ma i o continuous output current v o = 0 v to v cc 50 ma continuous current through each v cc or gnd 100 ma q ja package thermal impedance 4 89 c/w t stg storage temperature range 65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. this current flows only when the output is in the high state and v o > v cc . 4. the package thermal impedance is calculated in accordance with jesd 51. recommended operating conditions 1 symbol parameter limits unit symbol parameter min nom max unit v cc supply voltage 3.15 e 3.45 v v ref reference voltage 0.68 0.75 0.9 v v i input voltage 0 e 1.5 v v ih ac high-level input voltage all inputs v ref + 200 mv e e v v il ac low-level input voltage all inputs e e v ref 200 mv v v ih dc high-level input voltage all inputs v ref + 100 mv e e v v il dc low-level input voltage all inputs e e v ref 100 mv v i oh high-level output current e e 24 ma i ol low-level output current e e 24 ma t amb operating free-air temperature range 0 e +70 c note: 1. all unused inputs of the device must be held at v cc or gnd to ensure proper device operation.
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2004 apr 15 5 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted). symbol parameter test conditions limits unit symbol parameter test conditions min typ 1 max unit v ik v cc = 3.15 v; i i = 18 ma e e 1.2 v v oh high-level output voltage v cc = 3.15 v; i oh = 24 ma 2.4 e e v v ol low-level output voltage v cc = 3.15 v; i ol = 24 ma e e 0.5 v control inputs v cc = 3.45 v; v i = 0 v or 1.5 v e e 500 m a i i data inputs v cc = 3.45 v; v i = 0 v or 1.5 v e e 500 m a v ref v cc = 3.45 v; v ref = 0.68 v or 0.9 v e e 90 m a i cc supply current v cc = 3.45 v; v i = 0 v or 1.5 v e 50 100 ma c control inputs v cc = 0 v or 3.3 v; v i = 0 v or 3.3 v e 2 e pf c i data inputs v cc = 0 v or 3.3 v; v i = 0 v or 3.3 v e 2.5 e pf c o outputs v cc = 0 v; v o = 0 v e 4 e pf note: 1. all typical values are at v cc = 3.3 v; t amb = 25 c. timing requirements over recommended operating free-air temperature range (unless otherwise noted). symbol parameter test conditions v cc = 3.3 v 0.15 v unit symbol parameter test conditions min max unit t w pulse duration le low (figure 1) 3 e ns t su setup time d before le (figure 2) 2 e ns t h hold time d after le (figure 2) 1 e ns t ldr data race condition time d after le e 0 ns note: 1. this is the maximum time after le switches low that the data input can return to the latched state from the opposite state without producing a glitch on the output. switching characteristics over recommended operating free-air temperature range; v ref = 0.75 v. symbol parameter from to v cc = 3.3 v 0.15 v unit symbol parameter (input) (output) min max unit t pro p agation delay (figure 3) d q 1.9 3.4 ns t pd propagation dela y (fig u re 3) le q 1.9 4.2 ns simultaneous switching characteristics over recommended operating free-air temperature range; v ref = 0.75 v symbol parameter from to v cc = 3.3 v 0.15 v unit symbol parameter (input) (output) min max unit t propagation delay; all outputs switching d q 1.9 4.4 ns t pd gy g (figure 3) le q 1.9 5.2 ns
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2004 apr 15 6 voltage waveforms 1.25 v 0.25 v input t w v ref v ref sw00770 figure 1. pulse duration 1.25 v 0.25 v data input v ref v ref v ref le t su t h 1.25 v 0.25 v sw00771 figure 2. setup and hold times v ref v ref 1.5 v 1.5 v 1.25 v 0.25 v v oh v ol t phl t plh input (note 1) output sw00772 figure 3. propagation delay times notes: 1. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r 1 ns, t f 1 ns. 2. the outputs are measured one at a time with one transition per measurement. 3. t phl and t plh are the same as t pd . load circuit c l = 80 pf (see note) 500 w from output under test sw00773 note: c l includes probe and jig capacitance. figure 4. load circuit
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2004 apr 15 7 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1
philips semiconductors product data HSTL16919 9-bit to 18-bit hstl to lvttl memory address latch with 12 kohm pull-up resistor 2004 apr 15 8 revision history rev date description _2 20040415 product data (9397 750 13143). supersedes data of 2001 jul 19 (9397 750 08587). modifications: ? page 3: logic diagram (positive logic) modified. _1 20010719 product data (9397 750 08587). ecn 853-2269 26745of 19 july 2001. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 04-04 document order number: 9397 750 13143
data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii
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