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integrated device technology, inc. military and commercial temperature ranges december 1995 1996 integrated device technology, inc. dsc-2668/6 5.32 1 features: two side-by-side fifo memory arrays for bidirectional data transfers 512 x 18-bit - 512 x 18-bit (idt72511) 1024 x 18-bit - 1024 x 18-bit (idt72521) 18-bit data buses on port a side and port b side can be configured for 18-to-18-bit or 36-to-36-bit com- munication fast 35ns access time fully programmable standard microprocessor interface built-in bypass path for direct data transfer between two ports two fixed flags, empty and full, for both the a-to-b and the b-to-a fifo two programmable flags, almost-empty and almost-full for each fifo programmable flag offset can be set to any depth in the fifo any of the eight flags can be assigned to four external flag pins flexible reread/rewrite capabilities six general-purpose programmable i/o pins standard dma control pins for data exchange with peripherals 68-pin pga and plcc packages description: the idt72511 and idt72521 are highly integrated first-in, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. idt bififos inte- grate two side-by-side memory arrays for data transfers in two directions. the bififos have two ports, a and b, that both have standard microprocessor interfaces. all bififo operations are controlled from the 18-bit wide port a. port b is also 18 bits wide and can be connected to another processor or a peripheral controller. the bififos have a 9-bit bypass path that allows the device connected to port a to pass messages directly to the port b device. ten registers are accessible through port a, a com- mand register, a status register, and eight configuration registers. the idt bififo has programmable flags. each fifo memory array has four internal flags, empty, almost-empty, almost-full and full, for a total of eight internal flags. the almost-empty and almost-full flag offsets can be set to any depth through the configuration registers. these eight inter- nal flags can be assigned to any of four external flag pins (flg a -flg d ) through one configuration register. port b has programmable i/o, reread/rewrite and dma functions. six programmable i/o pins are manipulated through parallel bidirectional fifo 512 x 18 & 1024 x 18 idt72511 idt72521 simplified block diagram data data control flags control dma processor interface a programmable flag logic port b port a bypass 18-bits 9-bits 2668 drw 01 18-bit fifo registers handshake interface processor interface b programmable i/o logic i/o 18-bits 18-bit fifo the idt logo is a registered trademark of integrated device techology, inc.
5.32 2 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges two configuration registers. the reread and rewrite controls will read or write port b data blocks multiple times. the bififo has three pins, req, ack and clk, to control dma transfers from port b devices. pin configurations d b13 d b14 d b17 flg b flg d a 0 d a15 d a13 d a11 d b12 d b15 flg a flg c a 1 d a17 d a14 d a12 d b13 pio 4 d b11 pio 5 d b10 d b9 d a9 d b8 gnd pio 3 gnd r b gnd v cc w b v cc d b16 d b7 gnd d b6 d b5 pio 2 d b4 d b3 da7 d b13 d b2 d b13 d a10 d a8 ldrer ds a rs ldrew d a16 d a6 d b1 clk req rer r/w a pio 0 d a0 d a2 d a5 d b0 ack rew gnd cs a pio 1 d a1 d a3 g68-1 p in 1 designator 10 09 08 07 06 05 04 03 02 01 11 ab cd efgh l k j 2668 drw 02 d a4 pga top view 35 36 37 38 39 40 41 43 42 10 11 12 13 14 60 59 58 57 56 index d b2 d b3 d b5 d b6 d a5 d a6 d a16 pio 2 1 62 61 15 ldrew 55 d b7 16 gnd 54 d b16 17 rs 53 w b 18 v cc 52 v cc 19 ds a 51 r b 20 gnd 50 gnd 21 ldrer 49 gnd 22 pio 3 48 d b8 23 d a8 47 d b9 24 d a9 46 d b10 25 d a10 45 d b11 26 pio 4 44 d b12 2 3 4 5 6 7 8 9 63 64 65 66 67 68 34 33 32 31 30 29 28 27 j68-1 d a7 d b4 (r/w ) b (ds ) b pio 5 d a11 d a12 d a13 d a14 d a15 d a17 a 0 a 1 flg d flg c flg b flg a d b17 d b15 d b14 d b13 d a4 d a3 d a1 d a0 pio 1 pio 0 cs a r/w a gnd rer rew req ack clk d b0 d b1 d a2 2668 drw 03 plcc top view
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 3 pin description 2668 tbl 01 symbol name i/o description d a0- d a17 data a i/o data inputs and outputs for the 18-bit port a bus. cs a chip select a i port a is accessed when chip select a is low. ds a data strobe a i data is written into port a on the rising edge of data strobe when chip select is low. data is read out of port a on the falling edge of data strobe when chip select is low. r/ w a read/write a i this pin controls the read or write direction of port a. when cs a is low and r/ w a is high, data is read from port a on the falling edge of ds a . when cs a is low and r/ w a is low, data is written into port a on the rising edge of ds a . a 0 , a 1 addresses i when chip select a is asserted, a 0 , a 1 , and read/write a are used to select one of six internal resources. d b0 -d b17 data b i/o data inputs and outputs for the 18-bit port b bus. r b ( ds b) read b i or o if port b is programmed to processor mode, this pin functions as an input. if port b is programmed to peripheral mode this pin functions as an output. this pin can function as part of an intel-style interface ( r b ) or as part of a motorola-style interface ( ds b ). as an intel-style interface, data is read from port b on a falling edge of r b. as a motorola-style interface, data is read on the falling edge of ds b or written on the rising edge of ds b through port b. the default is intel-style processor mode. ( r b as an input). w b (r/ w b) write b i or o if port b is programmed to processor mode, this pin functions as an input. if port b is programmed to peripheral mode this pin functions as an output. this pin can function as part of an intel-style interface ( w b ) or as part of a motorola-style interface (r/ w b ). as an intel-style interface, data is written to port b on a rising edge of w b . as a motorola-style interface, data is read (r/ w b = high) or written (r/ w b = low) to port b in conjunction with a data strobe b falling or rising edge. the default is intel-style processor mode ( w b as an input.) rer reread i loads a ? b fifo read pointer with the value of the reread pointer when low. rew rewrite i loads b ? a fifo write pointer with the value of the rewrite pointer when low. ldrer load reread i loads the reread pointer with the value of the a ? b fifo read pointer when high. ldrew load rewrite i loads the rewrite pointer with the value of the b ? a fifo write pointer when high. req request i when port b is programmed in peripheral mode, asserting this pin begins a data transfer. request can be programmed either active high or active low. ack acknowledge o when port b is programmed in peripheral mode, acknowledge is asserted in response to a request signal. this confirms that a data transfer may begin. acknowledge can be programmed either active high or active low. clk clock i this pin is used to generate timing for ack, r b , w b , ds b and r/ w b when port b is in the peripheral mode. flg a - flg d flags o these four outputs pins can be assigned any one of the eight internal flags in the bififo. each of the two internal fifos (a ? b and b ? a) has four internal flags: empty, almost-empty, almost-full and full. pio 0 -pio 5 program- mable inputs/ outputs i/o six general purpose i/o pins. the input or output direction of each pin can be set independently. rs reset i a low on this pin will perform a reset of all bififo functions. v cc power there are two +5v power pins. gnd ground there are five ground pins at 0v.
5.32 4 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges detailed block diagram command status configuration 0 configuration 1 configuration 2 configuration 3 configuration 4 configuration 5 configuration 6 configuration 7 port a control programmable flag logic reread write pointer read pointer reread pointer load reread bypass path read pointer write pointer rewrite pointer load rewrite rewrite programmable i/o logic dma control reset pio5 == pio4 == pio3 == pio2 == pio1 == pio0 == clk ack* req* rs port b d b0 -d b17 port b control ldrer ldrew rer rew r b ( ds b ) == w b (r/ w b ) == flga* flgb* flgc* flgd* cs a ds a r/w a a 1 a 0 port a d a0 -d a17 9 9 18 18 18 18 16 2668 drw 04 a b fifo b a fifo notes: (*) can be programmed either active high or active low in internal configuration registerers. (==) can be programmed through an internal configuration register to be either an input or an output.
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 5 is connected to the bififo, port b is programmed to periph- eral interface mode and the interface pins are outputs. 18- to 18-bit configurations a single bififo can be configured to connect an 18-bit processor to another 18-bit processor or an 18-bit peripheral. the upper bififo shown in each of the figures 1 and 2 can be used in 18- to 18-bit configurations for processor and peripheral interface modes respectively. 36- to 36-bit configurations in a 36- to 36-bit configuration, two bififos operate in parallel. both bififos are programmed simultaneously, 18 data bits to each device. figures 1 and 2 show multiple bififos configured for processor and peripheral interface modes respectively. processor interface mode when a microprocessor or microcontroller is connected to port b, all bififos in the configuration must be programmed to processor interface mode. in this mode, all port b inter- face controls are inputs. both req and clk pins should be pulled low to ensure that the setup and hold time require- ments for these pins are met during reset. figure 1 shows the bififo in processor interface mode. functional description idts bififo family is versatile for both multiprocessor and peripheral applications. data can be sent through both fifo memories concurrently, thus freeing both processors from laborious direct memory access (dma) protocols and frequent interrupts. two full 18-bit wide fifos are integrated into the idt bififo, making simultaneous data exchange possible. each fifo is monitored by separate internal read and write point- ers, so communication is not only bidirectional, it is also totally independent in each direction. the processor con- nected to port a of the bififo can send or receive mes- sages directly to the port b device using the bififos 9-bit bypass path. the bififo can be used in different bus configurations: 18 bits to 18 bits and 36 bits to 36 bits. one bififo can be used for the 18- to 18-bit configuration, and two bififos are required for 36- to 36-bit configuration. this configuration can be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, ) by adding more bififos to the configuration. the microprocessor or microcontroller connected to port a controls all operations of the bififo. thus, all port a interface pins are inputs driven by the controlling processor. port b can be programmed to interface either with a second processor or a peripheral device. when port b is programmed in processor interface mode, the port b interface pins are inputs driven by the second processor. if a peripheral device figure 1. 36-bit processor to 36-bit processor configuration note: 1. 36- to 36-bit processor interface configuration. upper bififo only is used in 18- to 18-bit configuration. note that cntl a refers to cs a, a 1 , a 0 , r/ w a, and ds a; cntl b refers to r/ w b and ds b or r b and w b. idt bififo processor a processor b data data a data b data cntl a cntl b ack address idt bififo data a data b cntl a cntl b control logic ram 36-bit bus 36-bit bus 18 req ack req clk clk control ram control logic control 36 36 2668 drw 05 18
5.32 6 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges when either of the internal fifos are accessed, 18 bits of data are transferred across port a. since the bypass path is only 9 bits wide, the least significant byte (d a0 -d a7, d a16 ) is used on port a. all of the registers are 16 bits wide which means only the data bits (d a0 -d a15 ) are passed by port a. bypass path the bypass path acts as a bidirectional bus transceiver directly between port a and port b. the direct connection requires that the port a interface pins are inputs and the port b interface pins are outputs. the bypass path is 9 bits wide in an 18- to 18-bit configuration or 18 bits wide in a 36- to 36- bit configuration. during bypass operations, the bififos must be pro- grammed into peripheral interface mode. bit 10 of configura- tion register 5 (see table 10) is set to 1 for peripheral interface mode. command register ten registers are accessible through port a, a command register, a status register, and eight configuration registers. peripheral interface mode if port b is connected to a peripheral controller, all bififos in the configuration must be programmed in peri- pheral interface mode. in this mode, all the port b interface pins are all outputs. to assure fixed high states for r b and w b before they are programmed into an output, these two pins should be pulled up to v cc with 10k resistors. of course, only one set of port b interface pins should be used to control a single peripheral device, while the other interface pins are all ignored. figure 2 shows a bififo configuration connected to a peripheral. port a interface the bififo is straightforward to use in microprocessor- based systems because each bififo port has a standard microprocessor control set. port a has access to six re- sources: the a ? b fifo, the b ? a fifo, the 9-bit direct data bus (bypass path), the configuration registers, status and command registers. the port a address and read/write pins determine the resource being accessed as shown in table 1. data strobe is used to move data in and out of the bififo. idt bififo processor peripheral controller data data a data b data cntl a cntl b ack address ack cntl i/o data idt bififo data a data b cntl a cntl b control logic ram 36-bit bus 36-bit bus 18 req req ack req clk clk dma or system clock control 36 18 36 2668 drw 06 figure 2. 36-bit processor to 36-bit peripheral configuration note: 1. 36- to 36-bit peripheral interface configuration. upper bififo only is used in 18- to 18-bit configuration. note that cntl a refers to cs a, a 1 , a 0 , r/ w a, and ds a; cntl b refers to r/ w b and ds b or r b and w b.
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 7 the command register is written by setting cs a = 0, a 1 = 1, a 0 = 1. commands written into the bififo have a 4-bit opcode (bit8 C bit 11) and a 3-bit operand (bit 0 C bit 2) as shown in figure 3. the commands can be used to reset the bififo, to select the configuration register, to perform intel- ligent reread/rewrite, to set the port b dma direction, to set the status register format, and to modify the port b read and write pointers. the command opcodes are shown in table 2. the reset command initializes different portions of the bififo depending on the command operand. table 3 shows the reset command operands. the configuration register address is set directly by the command format 15 12 11 8 7 3 2 0 2668 tbl 02 figure 3. format for commands written into port a x x x x command opcode x x x x x command operand command operands shown in table 4. intelligent reread/rewrite is performed by interchanging the port b read pointer with the reread pointer or by interchanging the port b write pointer with the rewrite pointer. no command operands are required to perform a reread/ rewrite operation. when port b of the bififo is in peripheral mode, the dma direction is controlled by the command register. table 5 shows the port b read/write dma direction operands. two commands are provided to increment the port b read and write pointers. no operands are required for these commands.
5.32 8 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges request dma circuitry can also be reset independently. a software reset all command resets all the pointers, the dma request circuitry, and sets all the configuration registers to their default condition. note that a hardware reset is not the same as a software reset all command. table 6 shows the bififo state after the different hardware and software resets status register the status register reports the state of the programmable flags and the dma read/write direction. the status register is read by setting cs a = 0, a 1 = 1, a 0 = 1 (see table 1). see table 7 for the status register format. configuration registers the eight configuration register formats are shown in reset command functions 2668 tbl 04 table 3. reset command functions dma direction command functions operands function xx0 write b ? a fifo xx1 read a ? b fifo reset operands function 000 no operation 001 reset b ? a fifo (read, write, and rewrite pointers = 0) 010 reset a ? b fifo (read, write, and reread pointers = 0) 011 reset b ? a and a ? b fifo 100 reset internal dma request circuitry 101 no operation 110 no operation 111 reset all reset the idt72511 and idt72521 have a hardware reset pin ( rs ) that resets all bififo functions. a hardware reset re- quires the following four conditions: r b and w b must be high, rer and rew must be high, ldrer and ldrew must be low, and ds a must be high (figure 9). after a hardware reset, the bififo is in the following state: configuration registers 0-3 are 0000h , configuration register 4 is set to 6420h , and configuration registers 5, 6 and 7 are 0000h . additionally, all the pointers including the reread and rewrite pointers are set to 0 , the dma direction is set to b ? a write, and the internal dma request circuitry is cleared (set to its initial state). a software reset command can reset a ? b pointers and the b ? a pointers to 0 independently or together. the internal cs cs a a 1 a 0 read write 000 b ? a fifo a ? b fifo 0 0 1 9-bit bypass path 9-bit bypass path 0 1 0 configuration registers configuration registers 0 1 1 status register command register 1 x x disabled disabled port a resource selection 2668 tbl 03 table 1. accessing port a resources using cs a , a 0 and a 1 command opcode function 0000 reset bififo (see table 3) 0001 select configuration register (see table 4) 0010 load reread pointer with read pointer value 0011 load rewrite pointer with write pointer value 0100 load read pointer with reread pointer value 0101 load write pointer with rewrite pointer value 0110 set dma transfer direction (see table 5) 0111 reserved 1000 increment a ? b fifo read pointer (port b) 1001 increment b ? a fifo write pointer (port b) 1010 reserved 1011 reserved command operations 2668 tbl 07 table 5. set dma direction command functions. command only operates in peripheral interface mode operands function 000 select configuration register 0 001 select configuration register 1 010 select configuration register 2 011 select configuration register 3 100 select configuration register 4 101 select configuration register 5 110 select configuration register 6 111 select configuration register 7 select configuration register/ command functions 2668 tbl 06 table 4. select configuration register functions. 2668 tbl 05 table 2. functions performed by port a commands
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 9 table 8. configuration registers 0-3 contain the programmable flag offsets for the almost-empty and almost-full flags. these offsets are set to 0 when a hardware reset or a software reset all is applied. note that table 8 shows that configuration registers 0-3 are 10 bits wide to accommodate the 1024 locations in each fifo memory of the idt7252/520. only 9 least significant bits are used for the 512 locations of the idt7251/510; the most significant bit, bit 9, must be set to 0 . configuration register 4 is used to assign the internal flags to the external flag pins (flg a -flg d ). each external flag pin is assigned an internal flag based on the four bit codes shown in table 9. the default condition for configuration register 4 is 6420h as shown in table 6. the default flag assignments are: flg d is assigned b ? a full , flg c is assigned b ? a empty , flg b is assigned a ? b full , flg a is assigned a ? b empty . configuration register 5 is a general control register. the format of configuration register 5 is shown in table 10. bit 0 sets the intel-style interface ( r b , w b ) or motorola-style interface ( ds b , r/ w b ) for port b. bits 2 and 3 redefine full and empty flags for reread/rewrite data protection. bits 4-9 control the dma interface and are only applicable in peripheral interface mode. in processor interface mode, these bits are dont care states. bits 4 and 5 set the polarity of the dma control pins req and ack respectively. an internal clock controls all dma operations. this internal clock is derived from the external clock (clk). bit 9 determines the internal clock frequency: the internal clock = clk or the internal clock = clk divided by 2. bit 8 sets whether r b , w b , and ds b are asserted for either one or two internal clocks. bits 6 and 7 set the number of internal clocks between req assertion and ack assertion. the timing can be from 2 to 5 cycles as shown in figure 17. bit 10 controls port b processor or peripheral interface mode. in processor mode, the port b control pins ( r b , w b , ds b , r/ w b ) are inputs and the dma controls are ignored. in peripheral mode, the port b control pins are outputs and the dma controls are active. six pio pins can be programmed as an input or output by the corresponding mask bits in configuration register 7. the format of configuration register 7 is shown in figure 5. each bit of the register set the i/o direction independ- ently. a logic 1 indicates that the corresponding pio pin is an output, while a logic 0 indicates that the pio pin is an input. this i/o mask register can be read or written. a programmed output pio i pin (i = 0, 1, . . . 5) displays the data latched in bit i of configuration register 6. a programmed input pio i pin allows port a bus to sample the data on d ai by reading configuration register 6. state after reset software reset hardware reset ( rs asserted) b ? a(001) a ? b(010) b ? a and a ? b(011) internal request (100) all(111) configuration registers 0-3 0000h 0000h configuration register 4 6420h 6420h configuration register 5 0000h 0000h configuration register 6-7 0000h 0000h status register format 0 b ? a read, write, rewrite pointers 0 0 0 0 a ? b read, write, reread pointers 0 0 0 0 dma direction b ? a write dma internal request clear clear clear 2668 tbl 08 table 6. the bififo state after a reset command bit signal 0 reserved 1 reserved 2 reserved 3 dma direction 4 a ? b empty flag 5 a ? b almost-empty flag 6 b ? a full flag 7 b ? a almost-full flag 8 reserved 9 reserved 10 reserved 11 reserved 12 a ? b full flag 13 a ? b almost-full flag 14 b ? a empty flag 15 b ? a almost-empty flag status register format 2668 tbl 09 table 7. the status register format
5.32 10 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges configuration register formats 2668 tbl 11 table 9. configuration register 4 internal flag assignments to external flag pins assignment code internal flag assigned to flag pin 0000 a ? b empty 0001 a ? b almost-empty 0010 a ? b full 0011 a ? b almost-full 0100 b ? a empty 0101 b ? a almost-empty 0110 b ? a full 0111 b ? a almost-full 1000 a ? b empty 1001 a ? b almost-empty 1010 a ? b full 1011 a ? b almost-full 1100 b ? a empty 1101 b ? a almost-empty 1110 b ? a full 1111 b ? a almost-full external flag assignment codes programmable flags the idt bififo has eight internal flags. associated with each fifo memory array are four internal flags, empty, almost-empty, almost-full and full, for the total of eight internal flags. the almost-empty and almost-full offsets can be set to any depth through the configuration registers 0-3 (see table 8). the flags are asserted at the depths shown in table 11. after a hardware reset or a software reset all, the almost flag offsets are set to 0 . even though the offsets are equivalent, the empty and almost-empty flags have different timing which means that the flags are not coincident. similarly, the full and almost-full flags are not coincident after reset because of timing. these eight internal flags can be assigned to any of four external flag pins (flg a -flg d ) through configuration regis- ter 4 (see table 9). for the specific flag timings, see figures 20-23. the current state of all eight flags is available in the status register. config. reg. 0 config. reg. 1 config. reg. 2 config. reg. 3 config. reg. 4 config. reg. 5 config. reg. 6 config. reg. 7 x x x x x x x x x x x x x x x x x x x x x x x x a ? b fifo almost empty flag offset a ? b fifo almost full flag offset b ? a fifo almost empty flag offset b ? a fifo almost full flag offset flag d pin assignment flag c pin assignment flag b pin assignment flag a pin assignment general control i/o data i/o direction control 15 15 15 15 15 15 15 15 10 10 10 10 9 9 9 9 12 11 8 7 4 3 0 0 0 0 0 0 0 0 2668 drw 02 2668 tbl 10 note: 1. bit 9 of configuration registers 0-3 must be set to 0 on the idt72511. table 8. the bififo configuration register formats
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 11 bit function 0 select port b interface 0 pins are r b and w b (intel-style interface) r b and w b or ds b and r/ w b 1 pins are ds b and r/ w b (motorola-style interface) 1 unused 2 full flag definition 0 write pointer meets read pointer 1 write pointer meets reread pointer 3 empty flag definition 0 read pointer meets write pointer 1 read pointer meets rewrite pointer 4 req pin polarity 0 req pin active high 1 req pin active low 5 ack pin polarity 0 ack pin active low 1 ack pin active high 7-6 req / ack timing 00 2 internal clocks between req assertion and ack assertion 01 3 internal clocks between req assertion and ack assertion 10 4 internal clocks between req assertion and ack assertion 11 5 internal clocks between req assertion and ack assertion 8 port b read & write 0 r b , w b , and ds b are asserted for 1 internal clock timing control for peripheral mode 1 r b , w b , and ds b are asserted for 2 internal clocks 9 internal clock 0 internal clock = clk frequency control 1 internal clock = clk divided by 2 10 port b interface 0 processor interface mode (port b controls are inputs) mode control 1 peripheral interface mode (port b controls are outputs) 11 unused 12 unused 13 unused 14 unused 15 unused configuration register 5 format 15 6 5 4 3 2 1 0 unused pio5 pio4 pio3 pio2 pio1 pio0 2668 tbl 13 figure 4. bififo configuration register 6 format for programmable i/o data configuration register 7 format 2668 tbl 14 figure 5. bififo configuration register 7 format for programmable i/o direction mask unused mio5 mio4 mio3 mio2 mio1 mio0 15 6 5 4 3 2 1 0 2668 tbl 12 table 10. bififo configuration register 5 format configuration register 6 format
5.32 12 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges port b interface port b has reread/rewrite and dma functions. port b can be configured to interface to either intel-style ( r b , w b ) or motorola-style ( ds b , r/ w b ) devices in configuration register 5 (see table 10). port b can also be configured to talk to a processor or a peripheral device through configuration reg- ister 5. in processor interface mode, the port b interface controls are inputs. in peripheral interface mode, the port b interface controls are outputs. after a hardware reset or a software reset all command, port b defaults to an intel-style processor interface; the controls are inputs. dma control interface the bififo has dma control to simplify data transfers with peripherals. for the bififo dma controls (req, ack and clk) to operate, the bififo must be in peripheral interface mode (configuration register 5, table 10). dma timing is controlled by the external clock input, clk. an internal clock is derived from this clk signal to generate the r b , w b , ds b and r/ w b output signals. the internal clock also determines the timing between req assertion and ack assertion. bit 9 of configuration register 5 determines whether the internal clock is the same as clk or whether the internal clock is clk divided by 2. bit 8 of configuration register 5 set whether r b , w b and ds b are asserted for 1 or 2 internal clocks. bits 6 and 7 of configuration register 5 set the number of clocks between req assertion and ack assertion. the clocks between req assertion and ack assertion can be 2, 3, 4 or 5. bits 4 and 5 of configuration register 5 set the polarity of the req and ack pins respectively. a dma transfer command sets the port b read/write direction (see table 5). the timing diagram for dma transfers is shown in figure 17. the basic dma transfer starts with req assertion. after 2 to 5 internal clocks, ack is asserted by the bififo. ack will not be asserted if a read is attempted on an empty a ? b fifo or if a write is attempted on a full b ? a fifo. if the bififo is in motorola-style interface mode, r/ w b is set at the same time that ack is asserted. one internal clock later, ds b is asserted. if the bififo is in intel-style interface mode, either r b or w b is asserted one internal clock after ack assertion. these read/write controls stay asserted for 1 or 2 internal clocks, then ack, ds b , r b and w b are made inactive. this completes the transfer of one 9-bit word. on the next rising edge of clk, req is sampled. if req is still asserted, another dma transfer starts with the assertion of ack. data transfers will continue as long as req is asserted. intelligent reread/rewrite intelligent reread/rewrite is a method the bififo uses to help assure data integrity. port b of the bififo has two extra pointers, the reread pointer and the rewrite pointer.the reread pointer is associated with the a->b fifo read pointer, while the rewrite pointer is associated with the b->a fifo write pointer. the reread pointer holds the start ad- dress of a data block in the a->b fifo ram, and the read pointer is the current address of the same fifo ram array. by loading the read pointer with the value held in the reread pointer (rer asserted), reads will start over at the beginning of the data block. in order to mark the beginning of a data block, the reread pointer should be loaded with the read pointer value (ldrer asserted) before the first read is performed on this data block. figure 6 shows a reread operation. similarly, the rewrite pointer holds the start address of a data block in the b->a fifo ram, while the write pointer is the current address within the ram array. the operation of the rew and ldrew is identical to the rer and ldrer dis- cussed above. figure 7 shows a rewrite operation. for the reread data protection, bit 2 of configuration register 5 can be set to 1 to prevent the data block from being overwritten. in this way, the assertion of a->b full flag will occur when the write pointer meets the reread pointer instead of the read pointer as in the normal definition. for the rewrite data protection, bit 3 of configuration register 5 can be set to 1 to note: 2668 tbl 15 1. bififo flags must be assigned to external flag pins to be observed. d = fifo depth (idt72511 = 512, idt72521 = 1024), n = almost-empty flag offset, m = almost-full flag offset. table 11. internal flag truth table number of words in fifo from to empty flag almost-empty flag almost-full flag full flag 0 0 asserted asserted not asserted not asserted 1 n not asserted asserted not asserted not asserted n + 1 d C (m + 1) not asserted not asserted not asserted not asserted d C m d C 1 not asserted not asserted asserted not asserted d d not asserted not asserted asserted asserted internal flag truth table
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 13 prevent the data block from being read. in this case the assertion of b->a empty flag will occur when the read pointer meets the rewrite pointer instead of the write pointer. in conclusion, bit 2 and 3 of configuration register 5 are used to redefine full & empty flags for data block partition. although it can serve the purpose of data protection, the setting of these 2 bits is independent of the functions caused by rer/rew, or ldrer/ldrew assertions. programmable input/output the biflfo has six programmable i/0 pins (plo 0 - pio 5 ) which are controlled by port a through configuration regis- ters 6 and 7. data from the programmable i/o pins is mapped directly to the six least significant bits of configuration regis- ter 6. figure 4 shows the format of configuration register 6. this data is read or written by port a on the data pins (da 0 - da 5 ). a programmed output pio i pin (i = 0, 1, . . . , 5) displays the data latched in bit i of configuration register 6. a programmed input pio i pin allows port a bus to sample its data on d ai by reading configuration register 6. the read and write timing for the programmable i/o pins is shown in figure 19. the direction of each programmable i/o pin can be set independently by programming the mask in configuration register 7. each p10 pin has a corresponding input/output direction mask bit in configuration register 7. figure 5 shows the format of configuration register 7. setting a mask bit to a logic 1 makes the corresponding i/o pin an output. mask bits set to logic 0 force the corresponding i/o pin to an input. rewrite operations (3,4) reread operations (1,2) 2668 drw 08 notes: 1. if bit 2 is set to 1, empty flag asserted if read = write full flag asserted if reread + fifo size = write 2. if bit 2 is set to 0, empty flag asserted if read = write full flag asserted if read + fifo size = write notes: 1. if bit 3 is set to 1, empty flag asserted if read = rewrite full flag asserted if read + fifo size = write 2. if bit 3 is set to 0, empty flag asserted if read = write full flag asserted if read + fifo size = write write pointer read pointer rewrite pointer b ? a fifo rewrite function load rewrite function figure 7. bififo rewrite operations figure 6. bififo reread operations write pointer reread pointer read pointer a ? b fifo reread function load reread function 2668 drw 09
5.32 14 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges absolute maximum ratings (1) recommended dc operating conditions note: 2668 tbl 16 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. symbol parameter min. typ. max. unit v ccm military supply voltage 4.5 5.0 5.5 v v ccc commercial supply voltage 4.5 5.0 5.5 v gnd supply voltage 0 0 0 v v ih input high voltage commercial 2.0 v v ih input high voltage military 2.2 v v il (1) input low voltage commercial and military 0.8 v note: 2668 tbl 17 1. 1.5v undershoots are allowed for 10ns once per cycle. figure 8. output load * includes jig and scope capacitances dc electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to +70 c; military: v cc = 5v 10%, t a = C55 c to +125 c) input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 8 ac test conditions 2668 tbl 19 capacitance (t a = +25 c, f = 1.0mhz) symbol parameter conditions max. unit c in (2) input capacitance v in = 0v 8 pf c out (1,2) output capacitance v out = 0v 12 pf symbol rating commercial military unit v term terminal voltage with respect to ground C0.5 to +7.0 C0.5 to +7.0 v t a operating temperature 0 to +70 C55 to +125 c t bias temperature under bias C55 to +125 C65 to +135 c t stg storage temperature C55 to +125 C65 to +155 c i out dc output current 50 50 ma notes: 2668 tbl 20 1. with output deselected. 2. characterized values, not currently tested. +5v 1.1 k w 30 pf 680 w d.u.t. 2668 drw 09 * or equivalent circuit idt72511l idt72521l idt72521l commercial military t a = 25, 35, 50ns t a = 40, 50ns symbol parameter min. typ. max. min. typ. max. unit i il (1) input leakage current (any input) C1 1 C10 10 m a i ol (2) output leakage current C10 10 C10 10 m a v oh output logic "1" voltage i out = C1ma 2.4 2.4 v v ol output logic "0" voltage i out = 4ma 0.4 0.4 v i cc1 (3)(4) average vcc power supply current 150 230 180 250 ma i cc2 (3) average standby current ( r b = w b = ds a = v ih ) 16 30 24 50 ma notes: 1. measurements with 0.4v v in v cc , ds a = ds b 3 v ih 2. measurements with 0.4v v out v cc , ds a = ds b 3 v ih 3. measurements are made with outputs open. 2668 tbl 18
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 15 ac electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to + 70 c; military: v cc = 5v 10%, t a = C55 c to + 125 c) 2668 tbl 21 note: 1. the minimum data hold time is 5ns (10ns for the 80ns speed grade) when writing to the command or configuration registers. 2. idt72511 not available in military. commercial military com'l & mil. idt72511l25 idt72511l35 idt72511l50 idt72521l25 idt72521l35 idt72521l40 idt72521l50 timing symbol parameter min. max. min. max. min. max. min. max. unit figure reset timing (port a and port b) t rsc reset cycle time 35 45 50 65 ns 9 t rs reset pulse width 25 35 40 50 ns 9 t rss reset set-up time 25 35 40 50 ns 9 t rsr reset recovery time 10 10 10 15 ns 9 t rsf reset to flag time 35 45 50 65 ns 9 port a timing ta a port a access time 25 35 40 50 ns 12, 14, 15 ta lz read or write pulse low to data bus at low-z 5 5 5 5 ns 12, 15, 16 ta hz read or write pulse high to data bus at high- z 15 20 25 30 ns 12, 14, 15, 16 ta dv data valid from read pulse high 5 5 5 5 ns 12, 14, 16 ta rc read cycle time 35 45 50 65 ns 12 ta rpw read pulse width 25 35 40 50 ns 12, 14, 15 ta rr read recovery time 10 10 10 15 ns 12 tas cs a , a 0 , a 1 , r/ w a set - up time 5 5 5 5 ns 10, 12, 16 ta h cs a , a 0 , a 1 , r/ w a hold time 5 5 5 5 ns 10, 12 ta ds data set-up time 15 18 20 30 ns 11, 12, 14, 15 ta dh (1) data hold time 0 2 5 5 ns 11, 12, 14, 15 ta wc write cycle time 35 45 50 65 ns 12 ta wpw write pulse width 25 35 40 50 ns 11, 12, 14 ta wr write recovery time 10 10 10 15 ns 12 ta wrcom write recovery time after a command 25 35 40 50 ns 11 (2)
5.32 16 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges ac electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to + 70 c; military: v cc = 5v 10%, t a = C55 c to + 125 c) commercial military com'l & mil. idt72511l25 idt72511l35 idt72511l50 idt72521l25 idt72521l35 idt72521l40 idt72521l50 timing symbol parameter min. max. min. max. min. max. min. max. unit figure port b processor interface timing tb a port b access time 25 35 40 50 ns 13, 14, 15 tb lz read or write pulse low to data bus at low-z 5 5 5 5 ns 13, 14, 15 tb hz read or write pulse high to data bus at high-z 15 20 25 30 ns 14, 13, 15 tb dv data valid from read pulse high 5 5 5 5 ns 13, 14, 15, 16 tb rc read cycle time 35 45 50 65 ns 13 tb rpw read pulse width 25 35 40 50 ns 13 tb rr read recovery time 10 10 10 15 ns 13 tb s r/ w b set-up time 5 5 5 5 ns 13 tb h r/ w b hold time 5 5 5 5 ns 13 tb ds data set-up time 15 18 20 30 ns 13, 14, 15 tb dh data hold time 0 2 5 5 ns 13, 14, 15 tb wc write cycle time 35 45 50 65 ns 13 tb wpw write pulse width 25 35 40 50 ns 13, 15 tb wr write recovery time 10 10 10 15 ns 13 port b peripheral interface timing tb a port b access time 25 40 45 55 ns 17 tb ckc clock cycle time 15 20 20 25 ns 17 tb ckh clock pulse high time 6 6 8 10 ns 17 tb ckl clock pulse low time 6 6 8 10 ns 17 tb reqs request set-up time 5 5 5 10 ns 17 tb reqh request hold time 5 5 5 5 ns 17 tb ackl delay from a rising clock edge to ack switching 15 18 20 25 ns 17 2668 tbl 22 (1) note: 1. idt72511 not available in military.
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 17 ac electrical characteristics (commercial: v cc = 5v 10%, t a = 0 c to + 70 c; military: v cc = 5v 10%, t a = C55 c to + 125 c) commercial military com'l & mil. idt72511l25 idt72511l35 idt72511l50 idt72521l25 idt72521l35 idt72521l40 idt72521l50 timing symbol parameter min. max. min. max. min. max. min. max. unit figure port b retransmit timing tb dsbh rer , rew , ldrer, ldrew set-up and recovery time 10 10 10 15 ns 9, 18 programmable i/o timing t pioa programmable i/o access time 20 25 25 30 ns 19 t pios programmable i/o set- up time 8 10 10 15 ns 19 t pioh programmable i/o hold time 8 10 10 15 ns 19 bypass timing t bya bypass access time 18 20 25 30 ns 16 t byd bypass delay 10 15 20 20 ns 16 ta bydv bypass data valid time from ds a 15 15 15 15 ns 16 tb bydv (3) bypass data valid time from ds b 3333ns 16 flag timing (1) (2) t ref read clock edge to empty flag asserted 25 35 40 45 ns 14, 15, 20, 22 t wef write clock edge to empty flag not asserted 25 35 40 45 ns 14, 15, 20, 22 t rff read clock edge to full flag not asserted 25 35 40 45 ns 14, 15, 21, 23 t wff write clock edge to full flag asserted 25 35 40 45 ns 14, 15, 21, 23 t raef read clock edge to almost-empty flag asserted 40 50 55 60 ns 20, 22 t waef write clock edge to almost-empty flag not asserted 40 50 55 60 ns 20, 22 t raff read clock edge to almost-full flag not asserted 40 50 55 60 ns 21, 23 t waff write clock edge to almost-full flag asserted 40 50 55 60 ns 21, 23 notes: 2668 tbl 23 1. read and write are internal signals derived from ds a , r/ w a , ds b , r /w b , r b , and w b . 2. although the flags, empty, almost-empty, almost-full, and full flags are internal flags, the timing given is for those assigned to external pins. 3. values guaranteed by design, not currently tested. 4. idt72511 not available in military. (4)
5.32 18 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges figure 9. hardware reset timing figure 10. basic port a control signal timing (applies to all port a timing) ta s cs a a 0 , a 1 r/ w a ds a ta h 2668 drw 11 t rs t rsc t rss rs w b , r b (or r/ w b , ds b ) rer , rew ldrer, ldrew req ds a flg a , flg c t rsr t rsr t rsf t rsf 2668 drw 10 flg b , flg d
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 19 figure 11. port a command timing (write). figure 12. read and write timing for port a write read ta ds r/ w a ds a input d a0 - d a17 ta dh ta s ta wc ta wpw ta rr ta h r/ w a ds a output d a0 - d a17 ta s ta lz ta a ta hz ta dv ta rpw ta rr ta h ta rc 2668 drw 13 ta ds ta dh r/ w a ds a opcode d a8 - d a12 or operand d a0 - d a12 t wpw t wrcom 2668 drw 12
5.32 20 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges note: 1. r b = 1 tb ds (r/ w b ) w b (or ds b ) input d b0 Cd b8 tb dh tb s tb wc tb wpw tb wr tb h r b (or ds b ) output d b0 Cd b8 tb s tb lz tb a tb hz tb dv tb rpw tb rr tb h tb rc 2668 drw 14 (r/ w b) write read note: 1. w b = 1 figure 13. port b read and write timing, processor interface mode only
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 21 figure 14. port a read and write flow-through timing, processor interface mode only a ? b fifo write flow-through notes: 1. assume the flag pin is programmed active low. 2. r/ w a = 0 b ? a fifo read flow-through notes: 1. assume the flag pin is programmed active low. 2. r/ w a = 1 data output data inputs data out ds a d a0 - d a17 ta wpw ta ds ta dh t wff t rff tb dv tb hz tb lz tb a d b0 - d b17 ds a d a0 - d a17 d b0 - d b17 ta dv ta a data input ta rpw ta lz ta hz t ref t wef tb ds tb dh 2668 drw 15 b ? a empty flag (1) a ? b full flag (1) r b (or d s b ) w b (or d s b )
5.32 22 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges a ? b fifo write flow-through notes: 1. assume the flag pin is programmed active low. 2. r/ w a = 1 a ? b fifo read flow-through figure 15. port b read and write flow-through timing, processor interface mode only notes: 1. assume the flag pin is programmed active low. 2. r/ w a = 0 data out d a0 Cd a17 tb ds tb dh t rff t wff ta hz tb a b ? a full flag - d b0 Cd b8 w b (or ds b ) r b = 1 (or r/ w b = 0) data input ta ds ta dh data input t wef t ref ta lz data out ta hz tb a ta lz tb rpw tb dv 2668 drw 16 ds a d a0 Cd a17 d b0 Cd b8 r b (or ds b ) w b = 1 (or r/ w b = 1) (1) a ? b empty flag - (1) tb wpw ds a
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 23 b ? a read bypass byte 0 byte 1 byte 1 t as byte 0 r/ w a ds a d a0 Cd a7 , d a16 t as t alz t adv t bya byte 1 byte 2 t ah t ahz t byd t byd t byd t byd byte 0 byte 1 byte 2 t byd r b (or ds b ) (r/ w b ) d b0 Cd b8 t ah t blz ta bydv t bya byte 2 t bhz byte 0 byte 2 t byd t byd t byd t byd t byd r/ w a ds a d a0 Cd a7 , d a16 w b (or ds b ) (r/ w b ) d b0 Cd b8 (1) (1) (1) (1) tb bydv 2668 drw 17 notes: 1. once the bypass mode starts, any data change on port b bus (byte 0 ? byte 1) will be passed to port a bus. 2. w b = 1 a ? b write bypass notes: 1. once the bypass mode starts, any data change on port a bus (byte 0 ? byte 1) will be passed to port b bus. 2. r b = 1 figure 16. bypass path timing, bififo must be in peripheral interface mode
5.32 24 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges figure 17. port b read and write dma timing. peripheral interface mode only single word dma transfer block dma transfer clk t reqs req ack (r/ w b ) tb hz tb lz tb dv t reqh t ckh t ckl t ckc 2 to 5 cycles 1 cycle 1 to 2 cycles t ackl write read tb a t ackl t ackl tb dh 2 to 5 cycles 1 to 2 cycles 2 to 5 cycles 1 to 2 cycles clk req w b (or ds b ) output d b0 -d b17 (r/ w b ) r b (or ds b ) input d b0 -d b17 ack , r/ w b r b , w b (or ds b ) 2668 drw 18 tb ds ta ckl ta ckl
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 25 ta ds r/ w a ds a input d a0 -d a5 ta dh ta s ta wc ta wpw ta wr ta h r/ w a ds a output d a0 -d a5 ta s ta lz ta a ta hz ta dv ta rpw ta rr ta h ta rc output pio 0 -pio 5 t pioa t pioh t pioh t pios input pio 0 -pio 5 2668 drw 20 figure 19. programmable i/o timing r b, w b (or r/ w b , ds b ) rer rew tb dsbh ldrer, ldrew tb dsbh tb wpw 2668 drw 19 figure 18. port b reread and rewrite timing for intelligent reread/rewrite port a ? pio write pio ? port a read
5.32 26 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges notes: 1. b ? a fifo is initially empty. 2. assume the flag pins are programmed active low. 3. r/ w a = 1. ds a w b (or r/ w b = 0, ds b ) b ? a empty flag b ? a almost- empty flag t raef read 1 2 n + 1 1 write 2 n + 1 t waef t ref t wef 2668 drw 21 ds a w b (or r/ w b =1, ) b ? a almost- full flag b ? a full flag t rff read 1 2 m + 1 1 write 2 m + 1 t wff t wef t raff 2668 drw 22 (2) (2) figure 20. empty and almost-empty flag timing for b ? a fifo, (n = programmed offset) figure 21. full and almost-full flag timing for b ? a fifo, (m = programmed offset) notes: 1. b ? a fifo initially contains d C (m + 1) data words. d = 512 for idt72511; d = 1024 for idt72521. 2. assume the flag pins are programmed active low. 3. r/ w a = 1.
idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges 5.32 27 1 ds a write 1 2 n + 1 r b (or r/ w b =1, ds b ) a ? b empty flag a ? b almost- empty flag read t raef 2 n + 1 t wae f t ref 2668 drw 23 t wef (2) (2) notes: 1. a ? b fifo is initially empty. 2. assume the flag pins are programmed active low. 3. r/ w a = 1. figure 23. full and almost-full flag timing for a ? b fifo, (m = programmed offset) notes: 1. b ? a fifo initially contains d C (m + 1) data words. d = 512 for idt72511; d = 1024 for idt72521. 2. assume the flag pins are programmed active low. 3. r/ w a = 1. ds a w b (or r/ w b =1, ds b ) b ? a almost- full flag b ? a full flag t rff read 1 2 m + 1 1 write 2 m + 1 t wff t wef t raff 2668 drw 24 (2) (2) figure 22. empty and almost-empty flag timing for a ? b fifo, (n = programmed offset)
5.32 28 idt72511/idt72521 bidirectional first-in first-out memory military and commercial temperature ranges ordering information x power xxx speed x package x process/ temperature range blank commercial (0 c to +70 c) b military (C55 c to +125 c) compliant to mil-std-883, class b g j 68-pin pga 68-pin plcc 25 35 40 50 commercial only commercial only military only * com'l & mil. * l low power xxxxx device type 72511 72521 512 x 18 parallel bififo 1024 x 18 parallel bififo idt access time (t ) in ns a 2668 drw 25 * 40 military only, idt72521 * 50 commercial and military, idt72511 available in commercial only

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