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1/35 september 2004 m41st95y* m41st95w 5.0 or 3.0v, 512 bit (64 bit x8) serial rtc (spi) sram and nvram supervisor * contact local sales office features summary 5.0 or 3.0v operating voltage serial peripheral interface (spi) nvram supervisor for external lpsram 2.5 to 5.5v oscillator operating voltage automatic switch-over and deselect circuitry choice of power-fail deselect voltages: ? m41st95y*: v cc = 4.5 to 5.5v 4.20v v pfd 4.50v ? m41st95w: v cc = 2.7 to 3.6v 2.55v v pfd 24.70v 1.25v reference (for pfi/pfo) counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 44 bytes of general purpose ram programmable alarm and interrupt function (valid even during battery back-up mode) watchdog timer microprocessor power-on reset battery low flag 32khz frequency output available immediately upon power-on (300mil so28 mx package only) automatically records time when power-fail occurs ultra-low battery supply current of 550na (max) packaging includes a 28-lead soic and snaphat ? top (to be ordered separately) soic package provides direct connection for a snaphat top which contains the battery and crystal figure 1. 28-pin soic package* figure 2. 28-pin (300mil) soic package 28 1 soh28 (mh) snaphat (sh) battery & crystal sox28 (mx) embedded crystal
m41st95y*, m41st95w 2/35 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. 28-pin soic package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. 28-pin (300mil) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4. 28-pin soic connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. 28-pin, 300mil soic (mx) connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 7. hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 spi bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8. data and clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 9. input timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 10.output timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 figure 11.write cycle timing: rtc and external sram control signals . . . . . . . . . . . . . . . . . . 11 table 3. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 read and write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12.read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13.write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 power-down time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 timekeeper? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. timekeeper ? register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14.alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. alarm repeat mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 15.back-up mode alarm waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 full-time f 32k square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 (available only in 28-pin, 300mil soic (mx) package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 reset input (rstin1 and rstin2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16.rstin1 and rstin2 timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/35 m41st95y*, m41st95w table 7. reset ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17.power-fail comparator hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output driver pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 t rec bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 preferred power-on defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. t rec definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19.calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 20.ac testing input/output waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 12. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21.power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. power down/up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22.soh28 ? 28-lead plastic small outline, battery snaphat, package outline . . . . . . . . 29 table 15. soh28 ? 28-lead plastic small outline, battery snaphat, package mechanical data 29 figure 23.sh ? 4-pin snaphat housing for 48mah battery & crystal, package outline . . . . . . . 30 table 16. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mechanical data30 figure 24.sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline . . . . . . 31 table 17. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data. . . 31 figure 25.sox28 ? 28-lead plastic small outline, 300mils, embedded crystal, outline . . . . . . . . 32 table 18. sox28 ? 28-lead plastic small, 300mils, embedded crystal, package mech. data . . . 32 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 19. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 table 20. snaphat battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 21. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
m41st95y*, m41st95w 4/35 summary description the m41st95y/w serial timekeeper ? sram is a low power, 512-bit static cmos sram orga- nized as 64 words by 8 bits. a built-in 32,768hz oscillator (external crystal controlled) and 8 bytes of the sram (see table 4., page 16 ) are used for the clock/calendar function and are configured in binary coded decimal (bcd) format. an additional 12 bytes of ram provide status/con- trol of alarm, watchdog and square wave func- tions. addresses and data are transferred serially via a serial spi interface. the built-in address reg- ister is incremented automatically after each write or read data byte. the m41st95y/w has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. the energy needed to sustain the sram and clock op- erations can be supplied by a small lithium button- cell supply when a power failure occurs. functions available to the user include a non-volatile, time- of-day clock/calendar, alarm interrupts, watchdog timer and programmable square wave output. other features include a power-on reset as well as two additional debounced inputs (rstin1 and rstin2 ) which can also generate an output reset (rst ). the eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. the m41st95y/w is supplied in a 28-lead soic snaphat ? (mh) package (which integrates both crystal and battery in a single snaphat top), or a 28-pin, 300mil soic package (mx) which includes an embedded 32khz crystal. the 28-pin, 330mil soic provides sockets with gold plated contacts at both ends for direct con- nection to a separate snaphat housing contain- ing the battery and crystal. the unique design allows the snaphat battery/crystal package to be mounted on top of the soic package after the completion of the surface mount process. insertion of the snaphat housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur- face-mounting. the snaphat housing is also keyed to prevent reverse insertion. the snaphat soic and battery/crystal packag- es are shipped separately in plastic anti-static tubes or in tape & reel form. for the 28-lead so- ic, the battery/crystal package (e.g., snaphat) part number is ?m4txx-br12sh? (see table 20., page 33 ). caution: do not place the snaphat battery/crys- tal top in conductive foam, as this will drain the lith- ium button-cell battery. the 300mil, embedded crystal soic requires only a user-supplied battery to provide non-volatile op- eration.
5/35 m41st95y*, m41st95w figure 3. logic diagram note: 1. for sox28 package only. 2. open drain 3. available only in 28-pin, 300mil soic (mx) package. table 1. signal names note: 1. for sox28 package only. 2. available only in 28-pin, 300mil soic (mx) package. ai06369 scl v cc m41st95y/w v ss v bat (1) ex rstin1 irq/ft/out (2) sqw wdi pfi rstin2 rst (2) e con sdo sdi pfo v out f 32k (3) e e con conditioned chip enable output ex external chip enable e chip enable irq /ft/out interrupt/frequency test/out output (open drain) rst reset output (open drain) rstin1 reset 1 input rstin2 reset 2 input scl serial clock input sdi serial data input sdo serial data output sqw square wave output f 32k (2) 32khz square wave output wdi watchdog input pfi power-fail input pfo power-fail output v out voltage output v bat (1) battery supply voltage v cc supply voltage v ss ground nc no connect nf no function
m41st95y*, m41st95w 6/35 figure 4. 28-pin soic connections figure 5. 28-pin, 300mil soic (mx) connections note: 1. no function (nf) pins (1, 2, 3, and 4) pins must be tied to v ss , and are internally shorted together. ai06370 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 rstin1 rstin2 nc nc nc nc wdi nc nc irq/ft/out nc v out nc ex e nc pfi scl sdi nc pfo e con v ss sdo rst nc sqw v cc m41st95y m41st95w ai06370b 8 2 3 4 5 6 7 9 10 11 12 13 14 22 21 20 19 18 17 16 15 28 27 26 25 24 23 1 rstin1 rstin2 nc nf (1) nc nc sqw wdi nf (1) nc irq/ft/out f 32k v out ex e pfi scl sdi pfo e con v ss v bat nc sdo rst nf (1) nf (1) v cc m41st95y m41st95w
7/35 m41st95y*, m41st95w figure 6. block diagram note: 1. open drain output 2. available only in 28-pin, 300mil soic (mx) package. ai06371 compare v pfd v cc compare v so v out f 32k (2) v bl bl compare crystal spi interface real time clock calendar 44 bytes user ram rtc w/alarm & calibration watchdog frequency test output driver square wave sdo e sdi scl 1.25v pfi pfo rstin1 por sqw rst (1) wdi wds afe out ft irq/ft/out (1) v bat 32khz oscillator compare rstin2 ex e con (internal)
m41st95y*, m41st95w 8/35 figure 7. hardware hookup note: 1. cpol (clock polarity) and cpha (clock phase) are bits that may be set in the spi control register of the mcu. ai06372 master (st6, st7, st9, st10, others) spi interface with (cpol, cpha) (1) = ('0','0') or ('1','1') d q c cs3 cs2 cs1 m41st95y/w e xxxxx cqd xxxxx cqd e e cqd
9/35 m41st95y*, m41st95w operation the m41st95y/w clock operates as a slave de- vice on the spi serial bus. each memory device is accessed by a simple serial interface that is spi bus compatible. the bus signals are scl, sdi and sdo (see table 1., page 5 and figure 7., page 8 ). the device is selected when the chip enable input (e ) is held low. all instructions, addresses and data are shifted serially in and out of the chip. the most significant bit is presented first, with the data input (sdi) sampled on the first rising edge of the clock (scl) after the chip enable (e ) goes low. the 64 bytes contained in the device can then be accessed sequentially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. century/hours register 5. day register 6. date register 7. month register 8. year register 9. control register 10. watchdog register 11 - 16.alarm registers 17 - 19.reserved 20. square wave register 21 - 64.user ram the m41st95y/w clock continually monitors v cc for an out-of tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. when v cc falls below v so , the device automati- cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protection continues until v cc reaches v pfd (min) plus t rec (min). for more information on battery storage life refer to application note an1012. spi bus characteristics the serial peripheral interface (spi) bus is intend- ed for synchronous communication between dif- ferent ics. it consists of four signal lines: serial data input (sdi), serial data output (sdo), serial clock (scl) and a chip enable (e ). by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? the device that controls the message is called ?master.? the de- vices that are controlled by the master are called ?slaves.? the e input is used to initiate and terminate a data transfer. the scl input is used to synchronize data transfer between the master (micro) and the slave (m41st95y/w) devices. the scl input, which is generated by the micro- controller, is active only during address and data transfer to any device on the spi bus (see figure 7., page 8 ). the m41st95y/w can be driven by a microcon- troller with its spi peripheral running in either of the two following modes: (cpol, cpha) = ('0', '0') or (cpol, cpha) = ('1', '1'). for these two modes, input data (sdi) is latched in by the low-to-high transition of clock scl, and out- put data (sdo) is shifted out on the high-to-low transition of scl (see table 2., page 10 and fig- ure 8., page 10 ). there is one clock for each bit transferred. ad- dress and data bits are transferred in groups of eight bits. due to memory size the second most significant address bit is a don?t care (address bit 6).
m41st95y*, m41st95w 10/35 signal description serial data output (sdo). the output pin is used to transfer data serially out of the memory. data is shifted out on t he falling edge of the serial clock. serial data input (sdi). the input pin is used to transfer data serially into the device. instructions, addresses, and the data to be written, are each re- ceived this way. input is latched on the rising edge of the serial clock. serial clock (scl). the serial clock provides the timing for the serial interface (as shown in figure 9., page 11 and figure 10., page 11 ). the w/r bit, addresses, or data are latched, from the input pin, on the rising edge of the clock input. the out- put data on the sdo pin changes state after the falling edge of the clock input. the m41st95y/w can be driven by a microcon- troller with its spi peripheral running in either of the two following modes: (cpol, cpha) = ('0', '0') or (cpol, cpha) = ('1', '1'). for these two modes, input data (sdi) is latched in by the low-to-high transition of clock scl, and out- put data (sdo) is shifted out on the high-to-low transition of scl (see table 2 and figure 8 ). chip enable (e ). when e is high, the memory device is deselected, and the sdo output pin is held in its high impedance state. after power-on, a high-to-low transition on e is re- quired prior to the start of any operation. table 2. function table note: 1. sdo remains at high z until eight bits of data are ready to be shifted out during a read. figure 8. data and clock timing mode e scl sdi sdo disable reset h input disabled input disabled high z write l data bit latch high z read l x next data bit shift (1) ai04630 ai04631 ai06368 scl scl msb lsb cpha sdi 0 1 cpol 0 1 msb lsb sdo
11/35 m41st95y*, m41st95w figure 9. input timing requirements figure 10. output timing requirements figure 11. write cycle timing: rtc and external sram control signals ai04633 scl sdi e msb in sdo tdvch high impedance lsb in telch tchdx tdldh tdhdl tchcl tclch tehch tehel tcheh ai04634 scl sdo e lsb out sdi addr. lsb in tehqz tch tcl tqlqh tqhql tclqx tclqv msb out ai03663 ex e con texpd texpd
m41st95y*, m41st95w 12/35 table 3. ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. t ch + t cl 1/f scl 3. value guaranteed by design, not 100% tested in production. symbol parameter (1) min max unit f scl serial clock input frequency dc 2 mhz t ch (2) clock high 200 ns t chcl (3) clock transition (fall time) 1 s t chdx serial clock input high to input data transition 50 ns t cheh serial clock input high to chip enable high 200 ns t cl (2) clock low 200 ns t clch (3) clock transition (rise time) 1 s t clqv serial clock input low to output valid 150 ns t clqx serial clock input low to output data transition 0 ns t dhdl (3) input data transition (fall time) 1 s t dldh (3) input data transition (rise time) 1 s t dvch input data to serial clock input high 40 ns t ehch chip enable high to serial clock input high 200 ns t ehel chip enable high to chip enable low 200 ns t ehqz (3) chip enable high to output high-z 250 ns t elch chip enable low to serial clock input high 200 ns t qhql (3) output data transition (fall time) 100 ns t qlqh (3) output data transition (rise time) 100 ns t expd ex to e con propagation delay m41st95y 10 ns m41st95w 15 ns
13/35 m41st95y*, m41st95w read and write cycles address and data are shifted msb first into the se- rial data input (sdi) and out of the serial data output (sdo). any data transfer considers the first bit to define whether a read or write will occur. this is followed by seven bits defining the address to be read or written. data is transferred out of the sdo for a read operation and into the sdi for a write operation. the address is always the sec- ond through the eighth bit written after the enable (e ) pin goes low. if the first bit is a '1,' one or more write cycles will occur. if the first bit is a '0,' one or more read cycles w ill occur (see figure 12 and figure 13., page 14 ). data transfers can occur one byte at a time or in multiple byte burst mode, during which the ad- dress pointer will be automatically incremented. for a single byte transfer, one byte is read or writ- ten and then e is driven high. for a multiple byte transfer all that is required is that e continue to re- main low. under this condition, the address pointer will continue to increment as stated previously. in- crementing will continue until the device is dese- lected by taking e high. the address will wrap to 00h after incrementing to 3fh. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). although the clock contin- ues to maintain the correct time, this will prevent updates of time and date during either a read or write of these address locations by the user. the update will resume either due to a deselect condition or when the pointer increments to an non-clock or ram address (08h to 3fh). note: this is true both in read and write mode. figure 12. read mode sequence scl sdi e sdo 2 high impedance w/r bit 7 bit address 0 msb data out msb msb (byte 1) data out (byte 2) 1 12 13 14 15 16 17 22 3 4 5 6 7 8 9 2 0 1 3 4 5 6 7 2 0 1 3 4 5 6 7 2 0 1 3 4 5 6 7 ai04635
m41st95y*, m41st95w 14/35 figure 13. write mode sequence data retention mode with valid v cc applied, the m41st95y/w can be accessed as described above with read or write cycles. should the supply voltage decay, the m41st95y/w will automatically deselect, write protecting itself (and any external sram) when v cc falls between v pfd (max) and v pfd (min). this is accomplished by internally in- hibiting access to the clock registers. at this time, the reset pin (rst ) is driven active and will re- main active until v cc returns to nominal levels. ex- ternal ram access is inhibited in a similar manner by forcing e con to a high level. this level is within 0.2 volts of the v bat . e con will remain at this level as long as v cc remains at an out-of-tolerance con- dition. when v cc falls below the battery back-up switchover voltage (v so ), power input is switched from the v cc pin to the snaphat ? battery, and the clock registers and external sram are main- tained from the attached battery supply. all outputs become high impedance. the v out pin is capable of supplying 100 a of current to the at- tached memory with less than 0.3 volts drop under this condition. on power up, when v cc returns to a nominal value, write protection continues for t rec by inhibiting e con . the rst signal also re- mains active during this time (see figure 21., page 28 ). note: most low power srams on the market to- day can be used with the m41st95y/w rtc su- pervisor. there are, however some criteria which should be used in making the final choice of an sram to use. the sram must be designed in a way where the chip enable input disables all other inputs to the sram. this allows inputs to the m41st95y/w and srams to be ?don?t care? once v cc falls be- low v pfd (min). the sram should also guarantee data retention down to v cc = 2.0 volts. the chip enable access time must be sufficient to meet the system needs with the chip enable output propa- gation delays included. if the sram includes a second chip enable pin (e2), this pin should be tied to v out . if data retention lifetime is a critical parameter for the system, it is important to review the data reten- tion current specifications for the particular srams being evaluated. most srams specify a data retention current at 3.0 volts. manufacturers generally specify a typical condition for room tem- perature along with a worst case condition (gener- ally at elevated temperatures). the system level requirements will determine the choice of which value to use. the data retention current value of the srams can then be added to the i bat value of the m41st95y/w to determine the total current re- quirements for data retention. the available bat- tery capacity for the snaphat ? of your choice can then be divided by this current to determine the amount of data retention available (see 20 ). for a further more detailed review of lifetime calcu- lations, please see application note an1012. scl sdi e sdo 7 2 high impedance 0 data byte 7 bit addr w/r bit 10 15 msb msb 6 6 5 5 4 4 3 3 21 1 0 65 4321 0 7 7 7 8 9 ai04636
15/35 m41st95y*, m41st95w clock operation the eight byte clock register (see table 4., page 16 ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of sec- onds, seconds, minutes, and hours are contained within the first four registers. note: the tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d6 and d7 of clock register 03h (century/ hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (de- pending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month and years. the ninth clock register is the control register (this is described in the clock calibration section). bit d7 of register 01h con- tains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expect- ed to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce cur- rent drain. when reset to a '0' the oscillator restarts within one second. the eight clock registers may be read one byte at a time, or in a sequential block. the control reg- ister (address location 08h) may be accessed in- dependently. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock ad- dress is being read, an update of the clock regis- ters will be halted. this will prevent a transition of data during the read. power-down time-stamp when a power failure occurs, the halt update bit (ht) will automatically be set to a '1.' this will pre- vent the clock from updating the clock registers, and will allow the user to read the exact time of the power-down event. resetting the ht bit to a '0' will allow the clock to update the clock registers with the current time. timekeeper ? registers the m41st95y/w offers 20 internal registers which contain clock, alarm, watchdog, flag, square wave and control data (see table 4., page 16 ). these registers are memory loca- tions which contain external (user accessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external cop- ies are independent of internal functions except that they are updated periodically by the simulta- neous transfer of the incremented internal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock ad- dress. the system-to-user transfer of clock data will be halted whenever the clock addresses (00h to 07h) are being written. the update will resume either due to a deselect condition or when the pointer in- crements to a non-clock or ram address. timekeeper and alarm registers store data in bcd. control, watchdog and square wave reg- isters store data in binary format.
m41st95y*, m41st95w 16/35 table 4. timekeeper ? register map keys: s = sign bit ft = frequency test bit st = stop bit 0 = must be set to '0' bl = battery low flag (read only) bmb0-bmb4 = watchdog multiplier bits ceb = century enable bit cb = century bit out = output level afe = alarm flag enable flag rb0-rb1 = watchdog resolution bits wds = watchdog steering bit abe = alarm in battery back-up mode enable bit rpt1-rpt5 = alarm repeat mode bits wdf = watchdog flag (read only) af = alarm flag (read only) sqwe = square wave enable rs0-rs3 = sqw frequency ht = halt update bit tr = t rec bit addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h ceb cb 10 hours hours (24 hour format) century/hours 0-1/00-23 04h tr 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h 0 0 0 10m month month 01-12 07h 10 years year year 00-99 08h out ft s calibration control 09h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe abe al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 ht ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fhwdfaf0bl0 0 0 0 flags 10h00000000reserved 11h00000000reserved 12h00000000reserved 13h rs3 rs2 rs1 rs0 0 0 0 0 sqw
17/35 m41st95y*, m41st95w calibrating the clock the m41st95y/w is driven by a quartz-controlled oscillator with a nominal frequency of 32,768hz. uncalibrated clock accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1.53 minutes per month. when the calibration circuit is properly em- ployed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes with tem- perature (see figure 18., page 24 ). therefore, the m41st95y/w design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 19., page 24 . the number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the control register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the control register (8h). these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indi- cates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 osc illator cycles. if a bi- nary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillator is running at exactly 32,768hz, each of the 31 increments in the calibration byte would represent +10.7 or ?5.35 seconds per month which corresponds to a total range of +5.5 or ?2.75 minutes per month. two methods are available for ascertaining how much calibration a given m41st95y/w may re- quire. the first involves setting the clock, letting it run for a month and comparing it to a known accurate ref- erence and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934: tim ekeeper calibration. this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that ac- cesses the calibration byte. the second approach is better suited to a manu- facturing environment, and involves the use of the irq /ft/out pin. the pin will toggle at 512hz, when the stop bit (st, d7 of 1h) is '0,' the fre- quency test bit (ft, d6 of 8h) is '1,' the alarm flag enable bit (afe, d7 of ah) is '0,' and the watch- dog steering bit (wds, d7 of 9h) is '1' or the watchdog register (9h = 0) is reset. any deviation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124hz would indicate a +20 ppm oscillator frequency error, requiring a ?10 (xx001010) to be loaded into the calibration byte for correction. note: setting or changing the calibration byte does not affect the frequency test output fre- quency. the irq /ft/out pin is an open drain output which requires a pull-up resistor for proper opera- tion. a 500 to 10k ? resistor is recommended in or- der to control the rise time. the ft bit is cleared on power-down. setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. it can also be pro- grammed to go off while the m41st95y/w is in the battery back-up to serve as a system wake-up call. bits rpt5-rpt1 put the alarm in the repeat mode of operation. table 5., page 18 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5-rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set, the alarm condi- tion activates the irq /ft/out pin. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last address writ- ten is the ?alarm seconds,? the address pointer will increment to the flag address, causing this sit- uation to occur.
m41st95y*, m41st95w 18/35 to disable the alarm, write '0' to the alarm date register and to rpt1-5. the irq /ft/out output is cleared by a read to the flags register as shown in figure 14 . a subsequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' the irq /ft/out pin can also be activated in the battery back-up mode. the irq /ft/out will go low if an alarm occurs and both abe (alarm in bat- tery back-up mode enable) and afe are set. the abe and afe bits are reset during power-up, therefore an alarm generated during power-up will only set af. the user can read the flag register at system boot -up to determine if an alarm was generated while the m41st95y/w was in the de- select mode during power-up. figure 15., page 19 illustrates the back-up mode alarm timing. figure 14. alarm interrupt reset waveform table 5. alarm repeat mode rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 11111once per second 11110once per minute 11100once per hour 11000once per day 10000once per month 00000once per year ai03664 irq/ft/out active flag 0fh 0eh 10h high-z
19/35 m41st95y*, m41st95w figure 15. back-up mode alarm waveforms watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolu- tion, where 00 = 1 / 16 second, 01 = 1 / 4 second, 10 = 1 second, and 11 = 4 seconds. the amount of time-out is then determined to be the multiplica- tion of the five-bit multiplier value with the resolu- tion. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). note: accuracy of timer is within the selected resolution. if the processor does not reset the timer within the specified period, the m41st95y/w sets the wdf (watchdog flag) and generates a watchdog inter- rupt or a microprocessor reset. wdf is reset by reading the flags register (0fh). the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a '0,' the watchdog will activate the irq /ft/out pin when timed-out. when wds is set to a '1,' the watchdog will output a negative pulse on the rst pin for t rec . the watchdog register and the afe, abe, sqwe, and ft bits will reset to a '0' at the end of a watch- dog time-out when the wds bit is set to a '1.' the watchdog timer can be reset by two methods: 1. a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (wdi), or 2. the microprocessor can perform a write of the watchdog register. the time-out period then starts over. the wdi pin should be tied to v ss if not used. in order to per- form a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. should the watchdog timer time-out, and the wds bit is programmed to output an interrupt, a value of 00h needs to be written to the watchdog register in order to clear the irq /ft/out pin. this will also disable the watchdog function until it is again pro- grammed correctly. a read of the flags register will reset the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft/out pin and the frequency test (ft) function is activated, the watchdog function pre- vails and the frequency test function is denied. ai03920 v cc irq/ft/out v pfd abe, afe bits in interrupt register af bit in flags register high-z v so high-z trec
m41st95y*, m41st95w 20/35 square wave output the m41st95y/w offers the user a programma- ble square wave function which is output on the sqw pin. rs3-rs0 bits located in 13h establish the square wave output frequency. these fre- quencies are listed in table 6 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. table 6. square wave output frequency full-time f 32k square wave output (available only in 28-pin, 300mil soic (mx) package). the m41st95y/w offers the user a special 32khz square wave function which is always output on the f 32k pin (pin 21) as long as v cc v so , and the oscillator is running (st bit = '0'). this function is available within four seconds of initial power-up and can only be disabled by setting the st bit to '1,' or while the device is in back-up. if not used, the f 32k pin should be disconnected and allowed to float. square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 0 0 0 1 32.768 khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
21/35 m41st95y*, m41st95w power-on reset the m41st95y/w continuously monitors v cc . when v cc falls to the power fail detect trip point, the rst pulls low (open drain) and remains low on power-up for t rec after v cc passes v pfd (max). the rst pin is an open drain output and an appro- priate pull-up resistor should be chosen to control rise time. reset input (rstin1 and rstin2 ) the m41st95y/w provides two independent in- puts which can generate an output reset. the du- ration and function of these resets is identical to a reset generated by a power cycle. table 7 and fig- ure 16 illustrate the ac reset characteristics of this function. pulses shorter than t rlrh1 and t rlrh2 will not gener ate a reset condition. rstin1 and rstin2 are each internally pulled up to v cc through a 100k ? resistor. figure 16. rstin1 and rstin2 timing waveforms note: 1. open drain output table 7. reset ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. pulse width less than 50ns will result in no reset (for noise immunity). 3. pulse width less than 20ms will result in no reset (for noise immunity). 4. programmable (see table 8., page 23 ) 5. after crystal oscillator has started symbol parameter (1) min max unit t rlrh1 (2) rstin1 low to rstin1 high 200 ns t rlrh2 (3) rstin2 low to rstin2 high 100 ms t r1hrh (4) rstin1 high to rst high 96 98 ms t r2hrh (4,5) rstin2 high to rst high 96 98 ms ai03665 rstin2 rst (1) rstin1 trlrh1 trlrh2 tr1hrh tr2hrh
m41st95y*, m41st95w 22/35 power-fail input/output the power-fail input (pfi) is compared to an in- ternal reference voltage (1.25v). if pfi is less than the power-fail threshold (v pfi ), the power-fail output (pfo) will go low. this function is intended for use as an under-voltage detector to signal a failing power supply. typically pfi is connected through an external voltage divider (see figure 17 ) to either the unregulated dc input (if it is available) or the regulated output of the v cc regulator. the voltage divider can be set up such that the voltage at pfi falls below v pfi several milliseconds before the regulated v cc input to the m41st95y/w or the microprocessor drops below the minimum operat- ing voltage. during battery back-up, the power-fail comparator turns off and pfo goes (or remains) low. this oc- curs after v cc drops below v pfd (min). when pow- er returns, pfo is forced high, irrespective of v pfi for the write protect time (t rec ), which is the time from v pfd (max) until the inputs are recognized. at the end of this time, the power-fail comparator is enabled and pfo follows pfi. if the comparator is unused, pfi should be connected to v ss and pfo left unconnected. figure 17. power-fail comparator hookup note: 1. available only in 28-pin, 300mil soic (mx) package. ai06373 v cc v out v cc pfo sdi scl m41st95y/w wdi rstin2 rstin1 pfi v ss v bat irq/ft/out sqw rst sdo unregulated voltage regulator v cc v in e ex e con pushbutton reset from mcu to rst to led display to nmi to int f 32k (1) r1 r2 v cc e
23/35 m41st95y*, m41st95w century bit bits d7 and d6 of clock register 03h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to tog- gle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. output driver pin when the ft bit, afe bit and watchdog register are not set, the irq /ft/out pin becomes an out- put driver that reflects the contents of d7 of the control register. in other words, when d7 (out bit) and d6 (ft bit) of address location 08h are a '0,' then the irq /ft/out pin will be driven low. note: the irq /ft/out pin is an open drain which requires an external pull-up resistor. battery low warning the m41st95y/w automatically performs battery voltage monitoring upon power-up and at factory- programmed time intervals of approximately 24 hours. the battery low (bl) bit, bit d4 of flags register 0fh, will be asserted if the battery voltage is found to be less than approximately 2.5v. the bl bit will remain asserted until completion of bat- tery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. if a battery low is generated during a power-up se- quence, this indicates that the battery is below ap- proximately 2.5 volts and may not be able to maintain data integrity in the sram. data should be considered suspect and verified as correct. a fresh battery should be installed. if a battery low indication is generated during the 24-hour interval check, this indicates that the bat- tery is near end of life. however, data is not com- promised due to the fact that a nominal v cc is supplied. in order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. the snaphat ? top may be replaced while v cc applied to the device. the m41st95y/w only monitors the battery when a nominal v cc is applied to the device. thus appli- cations which require extensive durations in the battery back-up mode should be powered-up peri- odically (at least once every few months) in order for this technique to be beneficial. additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. t rec bit bit d7 of clock register 04h contains the t rec bit (tr). t rec refers to the automatic continuation of the deselect time after v cc reaches v pfd . this al- lows for a voltage setting time before writes may again be performed to the device after a power- down condition. the t rec bit will allow the user to set the length of this deselect time as defined by table 8 . preferred power-on defaults upon initial application of power to the device, the following register bits are set to a '0' state: watch- dog register, tr, ft, afe, abe, and sqwe. the following bits are set to a '1' state: out and ht (see table 9 ). table 8. t rec definitions note: 1. default setting; after oscillator has started table 9. default values note: 1. wds, bmb0-bmb4, rb0, rb1. 2. state of other control bits undefined. 3. uc = unchanged. t rec bit (tr) stop bit (st) t rec time units min max 0096 98 (1) ms 0140200ms 1 x 50 2000 s condition tr st ht out ft afe abe sqwe watchdog register (1) initial power-up (battery attach for snaphat) (2) 0011000 0 0 subsequent power-up (with battery back-up) (3) uc uc 1 uc 0 0 0 0 0
m41st95y*, m41st95w 24/35 figure 18. crystal accuracy across temperature figure 19. calibration waveform ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k ? f = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594b normal positive calibration negative calibration
25/35 m41st95y*, m41st95w maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 10. absolute maximum ratings note: 1. for soh28 package, lead-free (pb-free) lead finish: reflow at peak temperature of 260c (total thermal budget not to exc eed 245c for greater than 30 seconds). 2. for soh28 package, standard (snpb) lead finish: reflow at peak temperature of 225c (total thermal budget not to exceed 180c for between 90 to 150 seconds). 3. the sox28 package has lead-free (pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240c (use same reflow profile as standard (snpb) lead finish). caution: negative undershoots below ?0.3v are not allowed on any pin while in the battery back-up mode. caution: do not wave solder soic to avoid damaging snaphat sockets. symbol parameter value unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage m41st95y ?0.3 to 7 v m41st95w ?0.3 to 4.6 v t sld lead solder temperature for 10 seconds lead-free lead finish (1) 260 c standard (snpb) lead finish (2,3) 240 c t sld (1,2) lead solder temperature for 10 seconds 260 c v io input or output voltage ?0.3 to v cc +0.3 v i o output current 20 ma p d power dissipation 1 w
m41st95y*, m41st95w 26/35 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 11. dc and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 20. ac testing input/output waveforms table 12. capacitance note: 1. effective capacitance measured with power supply at 5v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs are deselected. parameter m41st95y m41st95w v cc supply voltage 4.5 to 5.5v 2.7 to 3.6v ambient operating temperature ?40 to 85c ?40 to 85c load capacitance (c l ) 100pf 50pf input rise and fall times 50ns 50ns input pulse voltages 0.2 to 0.8v cc 0.2 to 0.8v cc input and output timing ref. voltages 0.3 to 0.7v cc 0.3 to 0.7v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sdi and scl) 50 ns
27/35 m41st95y*, m41st95w table 13. dc characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. measured with v out and e con open. 3. rstin1 and rstin2 internally pulled-up to v cc through 100k ? resistor. wdi internally pulled-down to v ss through 100k ? resistor. 4. outputs deselected. 5. external sram must match rtc supervisor chip v cc specification. 6. for rechargeable back-up, v bat (max) may be considered v cc . 7. for pfo , f 32k , and sqw pins (cmos). 8. conditioned output (e con ) can only sustain cmos leakage current in the battery back-up mode. higher leakage currents will re- duce battery life. 9. for irq /ft/out, rst pins (open drain); if pulled-up to supply other than v cc , this supply must be equal to, or less than 3.0v when v cc = 0v (during battery back-up mode). sym parameter test condition (1) m41st95y m41st95w unit min typ max min typ max i bat (2) battery current osc on t a = 25c, v cc = 0v, v bat = 3v 400 550 400 550 na battery current osc off 50 50 na i cc1 supply current f = 2mhz 2 2 ma i cc2 supply current (standby) scl, sdi = v cc ? 0.3v 1.4 1.4 ma i li (3) input leakage current 0v v in v cc 1 1 a input leakage current (pfi) ?25 2 25 ?25 2 25 na i lo (4) output leakage current 0v v in v cc 1 1 a i out1 (5) v out current (active) v out1 > v cc ? 0.3v 175 100 ma i out2 v out current (battery back-up) v out2 > v bat ? 0.3v 100 100 a v ih input high voltage 0.7v cc v cc + 0.3 0.7v cc v cc + 0.3 v v il input low voltage ?0.3 0.3v cc ?0.3 0.3v cc v v bat battery voltage 2.5 3.0 3.5 (6) 2.5 3.0 3.5 (6) v v oh output high voltage (7) i oh = ?1.0ma 2.4 2.4 v power supply voltage (open drain) irq /ft/out, rst 5.5 3.6 v v ohb (8) v oh (battery back-up) i out2 = ?1.0a 2.5 2.9 3.5 2.5 2.9 3.5 v v ol output low voltage i ol = 3.0ma 0.4 0.4 v output low voltage (open drain) (9) i ol = 10ma 0.4 0.4 v v pfd power fail deselect 4.20 4.40 4.50 2.55 2.60 2.70 v v pfi pfi input threshold v cc = 5v(y) v cc = 3v(w) 1.225 1.250 1.275 1.225 1.250 1.275 v pfi hysteresis pfi rising 20 70 20 70 mv v so battery back-up switchover 2.5 2.5 v
m41st95y*, m41st95w 28/35 figure 21. power down/up mode ac waveforms table 14. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 4.5 to 5.5v or 2.7 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc passes v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. programmable (see table 8., page 23 ) 5. after crystal oscillator has started symbol parameter (1) min typ max unit t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t pfd pfi to pfo propagation delay 15 25 s t rec (4,5) power up deselect time 96 98 ms ai03661 v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec rst e con pfo
29/35 m41st95y*, m41st95w package mechanical information figure 22. soh28 ? 28-lead plastic small outline, battery snaphat, package outline note: drawing is not to scale. table 15. soh28 ? 28-lead plastic small outline, battery snaphat, package mechanical data symbol millimeters inches typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.51 0.014 0.020 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e1.27? ?0.050? ? eb 3.20 3.61 0.126 0.142 h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 0 8 0 8 n 28 28 cp 0.10 0.004 soh-a e n d c l a1 1 h a cp be a2 eb
m41st95y*, m41st95w 30/35 figure 23. sh ? 4-pin snaphat housing for 48mah battery & crystal, package outline note: drawing is not to scale. table 16. sh ? 4-pin snaphat housing for 48mah battery & crystal, package mechanical data symbol millimeters inches typ min max typ min max a 9.78 0.3850 a1 6.73 7.24 0.2650 0.2850 a2 6.48 6.99 0.2551 0.2752 a3 0.38 0.0150 b 0.46 0.56 0.0181 0.0220 d 21.21 21.84 0.8350 0.8598 e 14.22 14.99 0.5598 0.5902 ea 15.55 15.95 0.6122 0.6280 eb 3.20 3.61 0.1260 0.1421 l 2.03 2.29 0.0799 0.0902 shtk-a a1 a d e ea eb a2 b l a3
31/35 m41st95y*, m41st95w figure 24. sh ? 4-pin snaphat housing for 120mah battery & crystal, package outline note: drawing is not to scale. table 17. sh ? 4-pin snaphat housing for 120mah battery & crystal, package mech. data symbol millimeters inches typ min max typ min max a 10.54 0.4150 a1 6.73 7.24 0.2650 0.2850 a2 6.48 6.99 0.2551 0.2752 a3 0.38 0.0150 b 0.46 0.56 0.0181 0.0220 d 21.21 21.84 0.8350 0.8598 e 14.22 14.99 0.5598 0.5902 ea 15.55 15.95 0.6122 0.6280 eb 3.20 3.61 0.1260 0.1421 l 2.03 2.29 0.0799 0.0902 shtk-a a1 a d e ea eb a2 b l a3
m41st95y*, m41st95w 32/35 figure 25. sox28 ? 28-lead plastic small outline, 300mils, embedded crystal, outline note: drawing is not to scale. table 18. sox28 ? 28-lead plastic small, 300mils, embedded crystal, package mech. data symbol millimeters inches typ min max typ min max a 2.44 2.69 0.096 0.106 a1 0.15 0.31 0.006 0.012 a2 2.29 2.39 0.090 0.094 b 0.41 0.51 0.016 0.020 c 0.20 0.31 0.008 0.012 d 17.91 18.01 0.705 0.709 ddd 0.10 0.004 e 7.57 7.67 0.298 0.302 e1.27? ?0.050? ? h 10.16 10.52 0.400 0.414 l 0.51 0.81 0.020 0.032 0 8 0 8 n 28 28 e 14 e d c h 15 28 1 b so-e a1 l a1 h x 45? a a2 ddd
33/35 m41st95y*, m41st95w part numbering table 19. ordering information scheme note: 1. contact local sales office 2. the soic package (soh28) requires the snaphat ? battery package which is ordered separately under the part number ?m4txx- br12sh? in plastic tube or ?m4txx-br12shtr? in tape & reel form (see table 20 ). 3. the sox28 package includes an embedded 32,768hz crystal. caution : do not place the snaphat battery package ?m4txx-br12sh? in conductive foam as it will drain the lithium button-cell bat- tery. for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. table 20. snaphat battery table example: m41st 95y mh 6 device type m41st supply voltage and write protect voltage 95y (1) = v cc = 4.5 to 5.5v; 4.20v v pfd 4.50v 95w = v cc = 2.7 to 3.6v; 2.55v v pfd 2.70v package mh (1,2) = soh28 mx (3) = sox28 temperature range 6 = ?40 to 85c shipping method for soh28: blank = tubes (not for new design - use e) e = lead-free package (eco pack ? ), tubes f = lead-free package (eco pack ? ), tape & reel tr = tape & reel (not for new design - use f) for sox28: blank = tubes tr = tape & reel part number description package m4t28-br12sh lithium battery (48mah) and crystal snaphat sh m4t32-br12sh lithium battery (120mah) and crystal snaphat sh
m41st95y*, m41st95w 34/35 revision history table 21. document revision history m41st95, 41st95, st95, m41st95y, 41st95y, st95y, m41st95w, 41st95w, st95w, serial, serial, serial, serial, serial, serial, seri al, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, ac- cess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, a ccess, access, access, access, access, access, access, access, access, access, access, access, access, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, sp i, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, sp i, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, spi, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscilla tor, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscil- lator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, oscillator, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, microprocessor, micro- processor, microprocessor, microprocessor, microprocessor, micr oprocessor, microprocessor, microprocessor, microprocessor, rese t, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, r eset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, reset, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write pr otect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect , write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, ala rm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, al arm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, ala rm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, lo w, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, low, battery, battery, battery, battery, battery, battery, battery, battery, batte ry, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, b attery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, battery, b attery, battery, battery, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, comparator, comparator, comparator, comparator, comparator, compara tor, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, compara tor, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, comparator, power-fail, power-fail, power-f ail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, power-fail, sram, sram, sram, sram, sram, sr am, sram, sram, sram, sram, sram, sram, sram, sram, sram , sram, sram, sram, sram, s ram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram , sram, sram, sram, sram, sr am, sram, sram, sram, snaphat , snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaph at, snaphat, snaphat, snaph at, snaphat, snaphat, sn aphat, snaphat, snapha t, snaphat, snaphat, s naphat, snaph at, snaphat, snaphat, snaphat, snaphat, snaph at, snaphat, snaphat, snaphat, snaphat, snaphat, sn aphat, snaphat, snaphat , snaphat, snaphat, s oic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, 2.7v, 2.7v, 2.7v, 2.7v, 2.7v, 2.7v, 2.7v, 2.7v, 2.7v, 2.7v, 5v, 5v, 5v, 5 v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v date rev. # revision details february 2002 1.0 first draft 27-mar-02 1.1 change t rec definition (table 8 ) 01-apr-02 1.2 addition of new package option and inherent features 12-apr-02 2.0 document promoted 21-jan-03 2.1 add marketing note; (figure 1 ); modify logic, signals (figure 3 ; table 1 ); modify block diagram (figure 6 ) 25-feb-03 2.2 update definitions (table 8 ); correct mechanical dimensions (figure 25 ; table 18 ) 20-mar-03 3.0 document promoted 27-mar-03 3.1 add marketing status (table 19 ) 06-may-03 3.2 update 32khz information (figure 3 , 5 , 6 , 17 ; table 1 , 13 , 14 , 7 ) 15-jun-04 4.0 reformatted; update characteristics; added lead-free information (figure 5 , 6 , 18 ; table 1 , 4 , 7 , 8 , 10 , 13 , 14 , 19 ) 13-sep-04 5.0 update maximum ratings (table 10 )
35/35 m41st95y*, m41st95w information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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