1 aug. 2009 block diagram pin configuration (top view) outline:8p2s 1. hin 2. lin 3. gnd 4. lo 8. v b 7. ho 6. v s 5. v cc applications mosfet and igbt driver for pdp,hid lamp, refrigerator, air-conditioner, washing machine, ac-servomotor and general purpose. features ? floating supply voltage ................................. 600v ? output current ............................................ 3a (typ) ? undervoltage lockout ? input filter ? sop-8 package description M81722FP is high voltage power mosfet and igbt driver for half bridge applications. mitsubishi semiconductors M81722FP high voltage half bridge driver hin v reg filter hv level shift pulse gen inter lock uv detect filter uv detect filter ponr rq r s delay v reg /v cc level shift filter v reg /v cc level shift 1 lin 2 v b 8 ho 7 v s 6 v cc 5 lo 4 gnd 3
2 aug. 2009 absolute maximum ratings (ta=25 c unless otherwise specified) ?.5 ~ 624 v b -24 ~ v b +0.5 ?.5 ~ 24 v s ?.5 ~ v b +0.5 ?.5 ~ 24 ?.5 ~ v cc +0.5 ?.5 ~ v cc +0.5 0.6 4.8 50 ?0 ~ 150 ?0 ~ 125 ?0 ~ 150 260 (10s) v bs = v b -v s hin, lin ta = 25 c , on board ta > 25 c , on board for rohs high side floating supply absolute voltage high side floating supply offset voltage high side floating supply voltage high side output voltage low side fixed supply voltage low side output voltage logic input voltage package power dissipation linear derating factor junction - case thermal resistance junction temperature operation temperature storage temperature solder heat-proof(flow) v v v v v v v w mw/ c c/w c c c c symbol parameter test conditions ratings unit v b v s v bs v ho v cc v lo v in pd k q rth(j-c) tj t opr t stg t l * please adjust the v s potential to 500v or less when the junction temperature (tj) exceeds 125 c. * for proper operation, the device should be used within the recommended conditions. thermal derating factor characteristic (absolute maximum ratings) recommended operating conditions v b > 10v v bs = v b -v s hin, lin high side floating supply absolute voltage high side floating supply offset voltage high side floating supply voltage high side output voltage low side fixed supply voltage logic supply voltage logic input voltage v v v v v v v v b v s v bs v ho v cc v lo v in symbol parameter test conditions limits unit min. v s +10 ? 10 v s 10 0 0 t yp. max. v s +20 500 20 v b 20 v cc 7 mitsubishi semiconductors M81722FP high voltage half bridge driver power dissipation p d (w) 0 0 0.7 0.5 0.6 0.3 0.4 0.1 0.2 25 50 100 75 125 150 ambient temparature ta ( c)
3 aug. 2009 electrical characteristics (ta = 25 c, vcc=v bs (=v b -v s )=15v, unless otherwise specified) floating supply leakage current v bs standby current vcc standby current high level output voltage low level output voltage high level input threshold voltage low level input threshold voltage high level input bias current low level input bias current v bs supply uv reset voltage v bs supply uv hysteresis voltage v bs supply uv filter time vcc supply uv reset voltage vcc supply uv hysteresis voltage vcc supply uv filter time power-on reset voltage power-on reset filter time output high level short circuit pulsed current output low level short circuit pulsed current output high level on resistance output low level on resistance high side turn-on propagation delay high side turn-off propagation delay high side turn-on rise time high side turn-off fall time low side turn-on propagation delay low side turn-off propagation delay low side turn-on rise time low side turn-off fall time delay matching,high side and low side turn-on delay matching,high side and low side turn-off input filter time a ma ma v v v v a a v v s v v s v ns a a ? ? ns ns ns ns ns ns ns ns ns ns ns ns symbol parameter test conditions limits unit min. 13.8 4.0 8.0 0.3 8.0 0.3 300** 2.0 2.0 t yp.* 0.2 0.6 14.4 17 8.9 0.7 7.5 8.9 0.7 7.5 3.0 3.0 10 2.5 200 180 25 20 200 180 25 20 0 0 100 100 max. 1.0 0.5 1.0 0.1 0.8 40 1 9.8 9.8 6.0** 20 3.0 280 260 45 35 280 260 45 35 30 30 * typ. is not specified ** high side circuit only i fs i bs i cc v oh v ol v ih v il i ih i il v bsuvr v bsuvh t vbsuv v ccuvr v ccuvh t vccuv v ponr tp onr (fil) i oh i ol r oh r ol t dlh(ho) t dhl(ho) t rh t fh t dlh(lo) t dhl(lo) t rl t fl ? t dlh ? t dhl in(fil) v b = v s = 600v hin = lin = 0v hin = lin = 0v i o = 0a, lo, ho i o = 0a, lo, ho hin, lin hin, lin v in = 5v v in = 0v v o = 0v, v in = 5v, pwd < 10 m s v o = 15v, v in = 0v, pwd < 10 m s i o = -200ma, r oh = (v oh -v o ) /i o i o = 200ma, r ol = v o / i o cl = 1000pf between ho-vs cl = 1000pf between ho-vs cl = 1000pf between ho-vs cl = 1000pf between ho-vs cl = 1000pf between lo-gnd cl = 1000pf between lo-gnd cl = 1000pf between lo-gnd cl = 1000pf between lo-gnd |tdlh (ho) -tdlh (lo)| |tdhl (ho) -tdhl (lo)| convex pulse : hin, lin concave pulse : hin, lin mitsubishi semiconductors M81722FP high voltage half bridge driver
4 aug. 2009 function table lo = ho = low lo = high ho = high lo = ho = high ho = low, v bs uv tripped lo = high, v bs uv tripped lo = low, vcc uv tripped ho = lo = low, vcc uv tripped hin h l h l l h l h x x h l l h behavioral state lin l h l h l h x x v bs uv h h h h l l h h v cc uv h h h h h h l l ho l l h h l l l l lo l h l h l h l l note1 : ??state of v bs uv, vcc uv means that uv trip voltage. 2 : when input signal (hin and lin) is "h" at the same time, then output signal (both ho and lo) is ?? 3 : x(hin) : l h or h l.x(lin) : h or l. 4 : output signal (ho) is triggered by the edge of input signal. timing requirement hin or lin ho or lo t dlh t r 50% 50% 90% 90% 10% 10% t dhl t f mitsubishi semiconductors M81722FP high voltage half bridge driver hin ho
5 aug. 2009 timing diagram 1. input/output timing diagram high active (when input signal (hin or lin) is ?? then output signal (ho or lo) is ??) because there is not interlock circuit, in the case of both input signals (hin and lin) are ?? output signals (ho and lo) become ?? hin lin ho lo 2. operation sequence diagram mitsubishi semiconductors M81722FP high voltage half bridge driver v cc t vccuv v ponr t vbsuv t vccuv v bs hin lin ho lo v cc uv trip 7 # 4 6 7 5 s j q 7 $ $ 6 7 5 s j q v cc uv reset 7 # 4 6 7 3 f t f u 7 $ $ 6 7 3 f t f u
6 aug. 2009 3. ponr sequence diagram ?logic during uv error lo is locked at ??level during v cc uv error is detected. lo responds to lin ,if v cc exceeds v cc uv reset level. lo responds to lin even if v bs voltage is uv error. ho is locked at ??level during v cc uv error is detected. ho responds to hin ,if v cc exceeds v cc uv reset level. ho is locked at ??level during v cc uv error is detected. after v bs exceeds v bs uv reset level, the undervoltage lockout of ho is removed by "l"input signal of hin,and then ho responds to the input signal. 6 7 & s s p s 7 $ $
6 7 & s s p s 7 # 4
error signal ho lo 4. allowable supply voltage transient it is recommended to supply vcc firstly and supply v bs secondly. in the case of shutting off supply voltage, please shut off v bs firstly and shut off vcc secondly. when applying vcc and v bs , power supply should be applied slowly. if it rises rapidly, output signal (ho or lo) may be malfunction. * when supply voltage is lower than v ponr , then output will go low after tp onr (fil). mitsubishi semiconductors M81722FP high voltage half bridge driver v bsuvt t vbsuv v ponr t ponr (fil) v cc v bs hin ho
7 aug. 2009 p ackage outline consideration as for this product, the terminal of low voltage part and high-voltage part is very clear (the fifth: vcc, the sixth: vs). therefore, pin insulation space distance should be taken enough. mitsubishi semiconductors M81722FP high voltage half bridge driver 8 5 4 1 h e e d index mark *2 *1 *3 e b p y a f c a 2 a 1 l detail f min 4.8 4.2 0.05 0.35 0.13 0 5.9 1.12 0.2 d e a 2 a 1 a b p c q h e e y l nom 5.0 4.4 1.5 0.4 0.15 6.2 1.27 0.4 max 5.2 4.6 1.9 0.5 0.2 10 6.5 1.42 0.1 0.6 dimension in millimeters reference symbol note) 1. dimensions ?1?and ?2 do not include mold flash. 2. dimension ?3?does not include trim offset.
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