AGR21060E 60 w, 2.110 ghz?2.170 ghz, n-channel e-mode, lateral mosfet introduction the AGR21060E is a high-voltage, gold-metalized, enhancement-mode, laterally diffused metal oxide semiconductor (ldmos) rf power transistor suit- able for wideband code division multiple access (w-cdma), single and multicarrier class ab wireless base station power amplifier applications. figure 1. available packages features typical performance for two carrier 3gpp w-cdma systems. f1 = 2135 mhz and f2 = 2145 mhz with 3.84 mhz channel bandwidth (bw), adjacent channel bw = 3.84 mhz at f1 ? 5 mhz and f2 + 5 mhz. third-order distortion is measured over 3.84 mhz bw at f1 ? 10 mhz and f2 + 10 mhz. typical p/a ratio of 8.5 db at 0.01% (probability) ccdf: ? output power: 13.5 w. ? power gain: 14.5 db. ? efficiency: 26%. ? im3: ?34 dbc. ? acpr: ?37 dbc. ? return loss: ?12 db. high-reliability gold-metalization process. low hot carrier injection (hci) induced bias drift over 20 years. internally matched. high gain, efficiency, and linearity. integrated esd protection. device can withstand a 10:1 voltage standing wave ratio (vswr) at 28 vdc, 2140 mhz, 60 w continu- ous wave (cw) output power. large signal impedance parameters available. table 1. thermal characteristics table 2. absolute maximum ratings * * stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are absolute stress rat- ings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. table 3. esd rating * * although electrostatic discharge (esd) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to esd and electrical overstress (eos) during all handling, assembly, and test operations. agere employs a human-body model (hbm), a machine model (mm), and a charged-device model (cdm) qualification requirement in order to determine esd-susceptibility limits and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by jedec's jesd22-a114b (hbm), jesd22-a115a (mm), and jesd22-c101a (cdm) standards. caution: mos devices are susceptible to damage from elec- trostatic charge. reasonable precautions in han- dling and packaging mos devices should be observed. AGR21060Eu (unflanged) AGR21060Ef (flanged) ) 5b 03 style 1 parameter sym value unit thermal resistance, junction to case: AGR21060Eu AGR21060Ef r ? jc r ? jc 1.0 1.0 c /w c /w parameter sym value unit drain-source voltage v dss 65 vdc gate-source voltage v gs ?0.5, 15 vdc total dissipation at t c = 25 c : AGR21060Eu AGR21060Ef p d p d 175 175 w w derate above 25 c: AGR21060Eu AGR21060Ef ? ? 1.0 1.0 w/c w/c operating junction tempera- ture t j 200 c storage temperature range t stg ?65, 150 c AGR21060E minimum (v) class hbm 500 1b mm 50 a cdm 1500 4 peak devices
60 w, 2.110 ghz?2.170 ghz, n-channel e-mode, lateral mosfet e06012rga electrical characteristics recommended operating conditions apply unless otherwise specified: t c = 30 c. table 4. dc characteristics table 5. rf characteristics * 3gpp w-cdma, typical p/a ratio of 8.5 db at 0.01% ccdf, f1 = 2135.0 mhz, and f2 = 2145 mhz. v dd = 28 vdc, i dq = 500 ma, and p out = 13.5 w avg. t i n u x a m p y t n i m l o b m y s retemarap off characteristics drain-source breakdown voltage (v gs = 0, i d = 100 a) v (br)dss 65 ? ? vdc gate-source leakage current (v gs = 5 v, v ds =0v) i gss ? ? 1.8 adc zero gate voltage drain leakage current (v ds = 28 v, v gs =0v) i dss ? ? 5.5 adc on characteristics forward transconductance (v ds = 10 v, i d = 1 a) g fs ? 4.0 ? s gate threshold voltage (v ds = 10 v, i d = 180 a) v gs(th) ? ? 4.8 vdc gate quiescent voltage (v ds = 28 v, i d = 500 ma) v gs(q) ? 3.8 ? vdc drain-source on-voltage (v gs =10v, i d = 0.45 a) v ds(on) ? 0.08 ? vdc t i nuxampytn iml obmys re temarap dynamic characteristics reverse transfer capacitance (v ds = 28 v, v gs = 0, f = 1.0 mhz) (this part is internally matched on both the input and output.) c rss ? 1.3 ? pf functional tests (in agere systems supplied test fixture) g *n i ag rewop re i f i l pma ecruos-nommoc ps ? 14.5 ? db drain efficiency* ? 26 ? % third-order intermodulation distortion* (imd3 measured over 3.84 mhz bw @ f1 ? 10 mhz and f2 + 10 mhz) im3 ? ?34 ? dbc adjacent channel power ratio* (acpr measured over bw of 3.84 mhz @ f1 ? 5 mhz and f2 + 5 mhz) acpr ? ?37 ? dbc output power, 1 db compression point (v dd = 28 v, p out = 60 w (cw), f c = 2140.0 mhz) p 1db ? 60 ? w bd?21??lr i *ssol nruter tupni output mismatch stress (v dd = 28 v, p out = 60 w (cw), i dq = 500 ma, f c = 2140.0 mhz vswr = 10:1; [all phase angles]) no degradation in output power. 300 100 (in supplied test fixture)
e06012rga 60 w, 2.110 ghz?2.170 ghz, n-channel e-mode, lateral mosfet test circuit illustrations for AGR21060E a. schematic parts list: ? microstrip line: z1 0.361 in. x 0.065 in.; z2 0.207 in. x 0.150 in.; z3 0.085 in. x 0.087 in.; z4 0.130 in. x 0.357 in.; z5 0.436 in. x 0.087 in.; z6 0.414 in. x 0.900 in.; z7 0.424 in. x 0.050 in.; z8 1.170 in. x 0.050 in.; z9 0.520 in. x 0.624 in.; z10 0.120 in. x 0.147 in.; z11 0.180 in. x 0.250 in.; z12 0.469 in. x 1.200 in.; z13 0.068 in. x 0.068 in.; z14 0.278 in. x 0.065 in.; z15 1.170 in. x 0.050 in ? atc ? chip capacitor: c1, c2: 15 pf 100b150jca500x; c6, c7: 8.2 pf 100b8r2jca500x; c11: 1.2 pf 100b1r2jca500x; c14, c15: 5.6 pf 100b5r6jca500x. ? sprague ? tantalum surface-mount chip capacitor: c3, c4, c12, c13: 22 f, 35 v, t491d226k035as. ? vitramon ? chip capacitor: c5, c9: 22000 pf. ? 0805 size chip capacitor: c8 0.01 f. ? 1206 size chip capacitor: c10 0.1 f. ? 1206 size 0.25 w chip resistors: r1 1 k ; r2 560 k ; r3 4.7 . ? fair-rite ? ferrite bead: fb1 2743019447. ? taconic ? orcer rf-35: board material, 1 oz. copper, 30 mil thickness, r = 3.5. b. component layout figure 2. AGR21060E test circuit dut r3 c3 r2 r1 + c4 c5 + c6 fb1 z7 z1 c1 z2 z3 z4 z5 z9 z10 z11 z14 c10a a7c a8c a9c z8 a2 1c a3 1c + c11a c14a rf input v gg v dd1 rf c2 c15a output + 1 2 3 pins: 1. drain 2. gate 3. source c10b b7c b8c b9c c13b c12b + c11b c14b v dd2 c15b + z15 z6 z12 z13
60 w, 2.110 ghz?2.170 ghz, n-channel e-mode, lateral mosfet e06012rga typical performance characteristics figure 3. series equivalent input and output impedances mhz (f ) z s ( complex source impedance ) z l (complex optimum load impedance) db t db t ) 1 f ( 0112 db t db t ) 2 f ( 0412 db t db t ) 3 f ( 0712 0.1 0.1 0.1 0.2 0.2 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 0.8 0.8 0.9 0.9 1.0 1.0 1.2 1.2 1.4 1.4 1.6 1.6 1.8 1.8 2.0 2.0 3.0 3.0 4.0 4.0 5.0 5.0 10 10 10 20 20 20 50 50 50 0.2 0.2 0.2 0.4 0.4 0.4 0.6 0.6 0.6 0.8 0 .8 0.8 1.0 1.0 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 170 -170 180 90 -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 0.04 0.05 0.06 0.07 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.23 0.24 0.24 0.25 0.25 0.26 0.26 0.27 0.27 0.28 0.29 0.3 0.31 0.3 2 0.33 0.34 0.35 0.36 0.37 0.38 0.39 0.4 0.41 0.4 2 0 .43 0.44 0.45 0.46 0.47 0.48 0.48 0.49 0.49 0.0 0.0 a n g l e o f t r a n s m i s s i o n c o e f f i c i e n t i n d e g r e e s a n g l e o f r e f l e c t i o n c o e f f i c i e n t i n d e g r e e s e > w a v e l e n g t h s t o w a r d < e w a v e l e n g t h s t o w a r d l o a d < e i n d u c t c a p a c i t i v e r e a c t a n c e c o m p o n e n t ( - j x / z o ) , o r i n d u c t i v e s u s c e p t a n c e ( - j b / y o ) resistance component (r/zo), or conductance component (g/yo) f z 0 = 10 dut z s z l input match output match drain (1) source (3) gate (2)
e06012rga 60 w, 2.110 ghz?2.170 ghz, n-channel e-mode, lateral mosfet package dimensions all dimensions are in inches. tolerances are 0.005 in. unless specified. AGR21060Eu AGR21060Ef pins: 1. drain 2. gate 3. source pins: 1. drain 2. gate 3. source peak devices AGR21060Eu xxxx peak devices AGR21060Ef xxxx xxxx - 4 digit trace code
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