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asahi kasei [AK5700] ms0569-e-01 2006/12 - 1 - general description the AK5700 features a 16-bit mono adc. input circuits include a microphone-amplifier and an alc (auto level control) circuit that is suitable for portable a pplication with recording function. on-chip pll supports base-band clock of mobile phone, therefore it is easy to connect with dsp. the AK5700 is available in a 24pin qfn, utilizing less board space than competitive offerings. features 1. resolution: 16bits 2. recording function - input selector - full-differential or single-ended input - mic amplifier (+30db/+15db or 0db) - input voltage: 1.8vpp@avdd=3.0v (= 0.6 x avdd) - adc performance: s/(n+d): 78db, dr, s/n: 89db@mgain=0db s/(n+d): 77db, dr, s/n: 87db@mgain=+15db s/(n+d): 72db, dr, s/n: 77db@mgain=+30db - digital hpf for dc-offset can cellation (fc=3.4hz@fs=44.1khz) - digital alc (automatic level control) (+36db ? 54db, 0.375db step, mute) 3. sampling rate: - pll slave mode (exlrck pin): 7.35khz 48khz - pll slave mode (exbclk pin): 7.35khz 48khz - pll slave mode (mcki pin): 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz - pll master mode: 8khz, 11.025khz, 12khz, 16khz, 22.05khz, 24khz, 32khz, 44.1khz, 48khz - ext slave mode: 7.35khz 48khz (256fs), 7.35khz 26khz (512fs), 7.35khz 13khz (1024fs) 4. pll input clock: - mcki pin: 27mhz, 26mhz, 24mhz, 19.2mhz, 13.5mhz, 13mhz, 12.288mhz, 12mhz, 11.2896mhz - exlrck pin: 1fs - exbclk pin: 32fs/64fs 5. master/slave mode 6. audio interface format: msb first, 2?s complement - dsp mode, 16bit msb justified, i 2 s 7. p i/f: 3-wire serial 8. power supply: - avdd: 2.4 3.6v - dvdd: 1.6 3.6v 9. power supply current: 6ma 10. ta = ? 30 85 c 11. package: 24pin qfn (4mm x 4mm) 12. pin and register compatible with ak5701 stereo version 16-bit ? mono adc with pll & mic-amp AK5700
asahi kasei [AK5700] ms0569-e-01 2006/12 - 2 - ? block diagram a in1/ain+ vcom a vdd a vss vcoc mcki sdto bclk lrck dvdd adc a udio i/f controller pll pdn s e l mcko exlrck exbclk exsdti control register csn cclk cdti s e l a in2 alc or ivol mpwr dvss csp hpf a in ? figure 1. block diagram
asahi kasei [AK5700] ms0569-e-01 2006/12 - 3 - ? ordering guide AK5700vn ? 30 +85 c 24pin qfn (0.5mm pitch) akd5700 evaluation board for AK5700 ? pin layout mpwr test ain2 ain - ain1 / ain+ vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck AK5700vn top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 ? comparison with ak5701vn function ak5701vn AK5700vn adc channel number 2 channel 1channel input selector 2 stereo input selector 2 mono input selector audio i/f format dsp mode 0, dsp mode 1, left justified, i 2 s dsp mode 0, left justified, i 2 s
asahi kasei [AK5700] ms0569-e-01 2006/12 - 4 - pin/function no. pin name i/o function 1 vcom o common voltage output pin, 0.5 x avdd bias voltage of adc inputs. 2 avss - analog ground pin 3 avdd - analog power supply pin 4 dvdd - digital power supply pin 5 dvss - digital ground pin 6 bclk o audio serial data clock pin 7 lrck o input / output channel clock pin 8 sdto o audio serial data output pin 9 csp i chip select polarity pin ?h?: csn pin = ?h? active, c1-0 = ?01? ?l?: csn pin = ?l? active, c1-0 = ?10? 10 mcko o master clock output pin 11 exsdti i external audio serial data input pin 12 exlrck i external input / output channel clock pin 13 exbclk i external audio serial data clock pin 14 mcki i external master clock input pin 15 cdti i control data input pin 16 cclk i control data clock pin (internal pull-down at csp pin = ?h?) 17 csn i chip select pin 18 pdn i power-down mode pin ?h?: power-up, ?l?: power-down, reset and initializes the control register. 19 mpwr o mic power supply pin 20 test - test pin this pin should be left floating. 21 ain2 i analog input 2 pin 22 ain ? i negative input pin ain1 i analog input 1 pin (mdif1 bit = ?0?: single-ended input) 23 ain+ i positive input pin (mdif1 bit = ?1?: full-differential input) 24 vcoc o output pin for loop filter of pll circuit this pin should be connected to avss with one resistor and capacitor in series. note 1. all input pins except analog input pins (ain1, ain1 ? , ain2) should not be left floating. ? handling of unused pin the unused i/o pins should be processed appropriately as below. classification pin name setting analog mpwr, vcoc, ain1/ain+, ain ? , ain2 these pins should be open. bclk, lrck, sdto, mcko these pins should be open. digital mcki, exbclk, exlrck, exsdti these pins should be connected to dvss.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 5 - absolute maximum ratings (avss, dvss=0v; note 2) parameter symbol min max units power supplies: analog avdd ? 0.3 4.6 v digital dvdd ? 0.3 4.6 v |avss ? dvss| (note 3) gnd - 0.3 v input current, any pin except supplies iin - 10 ma analog input voltage (note 4) vina ? 0.3 avdd+0.3 v digital input voltage (note 5) vind ? 0.3 dvdd+0.3 v ambient temperature (powered applied) ta ? 30 85 c storage temperature tstg ? 65 150 c note 2. all voltages with respect to ground. note 3. avss and dvss must be connected to the same analog ground plane. note 4. ain1/ain+, ain ? , ain2 pins note 5. pdn, csn, cclk, cdti, csp, mcki, exsdti, exlrck, exbclk pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 2) parameter symbol min typ max units power supplies analog avdd 2.4 3.0 3.6 v (note 6) digital dvdd 1.6 3.0 avdd v note 2. all voltages with respect to ground. note 6. the power-up sequence between avdd and dvdd is not critical. when only avdd is powered off, the power supply current of dvdd at power-down mode may be increased. dvdd should not be powerd off while avdd is powered on. * akm assumes no responsibility for the usag e beyond the conditions in this datasheet.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 6 - analog characteristics (ta=25 c; avdd, dvdd=3.0v; avss=dvss=0v; pll master mode; mcki=12mhz, fs=44.0995khz, bclk=64fs; signal frequency=1khz; 16bit data; measurement frequency=20hz 20khz; unless otherwise specified) parameter min typ max units mic amplifier: ain1, ain2 pins; mdif1 bit = ?0? (single-ended inputs) mgain1-0 bits = ?00? 40 60 80 k input resistance mgain1-0 bits = ?01? or ?10? 20 30 40 k mgain1-0 bits = ?00? - 0 - db mgain1-0 bits = ?01? - +15 - db gain mgain1-0 bits = ?10? - +30 - db mic amplifier: ain+, ain ? pins; mdif1 bit = ?1? (full-differential input) input voltage (note 7) mgain1-0 bits = ?01? - - 0.37 vpp mgain1-0 bits = ?10? - - 0.066 vpp mic power supply: mpwr pin output voltage (note 8) 2.02 2.25 2.48 v load resistance 1.0 - - k load capacitance - - 30 pf adc analog input characteristics: ain1/ain2 pins (single-ended inputs) adc ivol, mgain=+15db, ivol=0db, alc=off resolution - - 16 bits mgain=+30db - 0.057 - vpp mgain=+15db 0.27 0.32 0.37 vpp input voltage (note 9) mgain=0db 1.53 1.80 2.07 vpp s/(n+d) ( ? 0.5dbfs) (note 10) 67 77 - db d-range ( ? 60dbfs, a-weighted) (note 11) 79 87 - db s/n (a-weighted) (note 11) 79 87 - db power supplies: power supply current: avdd+dvdd power up (pdn pin = ?h?) (note 12) - 6 12 ma power down (pdn pin = ?l?) (note 13) - 1 20 a note 7. the voltage difference between ain+ and ain ? pins. ac coupling capacitor should be inserted in series at each input pin. full-differential input is not available at mgain1-0 bits = ?00?. maximum input voltage of ain+, ain ? pins is proportional to avdd voltage, respectively. vin = |(ain+) ? (ain ? )| = 0.123 x avdd (max)@mgain1-0 bits = ?01?, 0.022 x avdd (max)@mgain1-0 bits = ?10?. when the signal larger than above value is input to ain+, ain ? pin, adc does not operate normally. note 8. output voltage is proportional to avdd voltage. vout = 0.75 x avdd (typ). note 9. input voltage is proportional to avdd voltage. vin = 0.107 x avdd (typ)@mgain1-0 bits = ?01? (+15db), vin = 0.6 x avdd(typ)@mgain1-0 bits = ?00? (0db). note 10. 80db(typ)@mgain=0db, 70db(typ)@mgain=+30db note 11. 89db(typ)@mgain=0db, 75db(typ)@mgain=+30db note 12. pll master mode (mcki=12mhz), pmadc = pmvcm = pmpll = pmmp = m/s bits = ?1? and mcko bit = ?0?. mpwr pin outputs 0ma. avdd=4.5ma(typ), dvdd=1.5ma(typ). ext slave mode (pmpll = m/s = mcko bits = ?0?): avdd=3.8ma(typ), dvdd=1.2ma(typ). bypass mode (thr bit = ?1?, pmadc = m/s bits = ?0?), fs=8khz: avdd=1 a(typ), dvdd=150 a(typ). note 13. all digital input pins are fixed to dvdd or dvss.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 7 - filter characteristics (ta=25 c; avdd=2.4 3.6v; dvdd=1.6 3.6v; fs=44.1khz) parameter symbol min typ max units adc digital filter (decimation lpf): passband (note 14) 0.1db pb 0 - 17.4 khz ? 1.0db - 20.0 - khz ? 3.0db - 21.1 - khz stopband (note 14) sb 25.7 - - khz passband ripple pr - - 0.1 db stopband attenuation sa 65 - - db group delay (note 15) gd - 18 - 1/fs group delay distortion gd - 0 - s adc digital filter (hpf): hpf1-0 bits = ?00? frequency response (note 14) ? 3.0db fr - 3.4 - hz ? 0.5db - 10 - hz ? 0.1db - 22 - hz note 14. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.454*fs (@ ? 1.0db). each response refers to that of 1khz. note 15. the calculated delay time caused by digital filtering. this time is from the input of analog signal to setting of the 16-bit data from the input register to the output register of the adc. this time includes the group delay of the hpf. dc characteristics (ta=25 c; avdd=2.4 3.6v; dvdd=1.6 3.6v) parameter symbol min typ max units high-level input voltage except csp pin; 2.2v dvdd 3.6v vih 70 % dvdd - - v except csp pin; 1.6v dvdd <2.2v vih 80 % dvdd - - v csp pin vih 90 % dvdd - - v low-level input voltage except csp pin; 2.2v dvdd 3.6v vil - - 30 % dvdd v except csp pin; 1.6v dvdd <2.2v vil - - 20 % dvdd v csp pin vil - - 10 % dvdd v high-level output voltage (iout= ? 200 a) voh dvdd ? 0.2 - - v low-level output voltage (iout= 200 a) vol - - 0.2 v input leakage current (note 16) iin - - 10 a note 16. when csp pin is ?h?, cclk pin has internal pull-down device, normally 100k .
asahi kasei [AK5700] ms0569-e-01 2006/12 - 8 - switching characteristics (ta=25 c; avdd=2.4 3.6v; dvdd=1.6 3.6v; c l =20pf; unless otherwise specified) parameter symbol min typ max units pll master mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bclk output timing period bcko1-0 bit = ?01? tbck - 1/(32fs) - ns bcko1-0 bit = ?10? tbck - 1/(64fs) - ns duty cycle dbck - 50 - % pll slave mode (pll reference clock = mcki pin) mcki input timing frequency fclk 11.2896 - 27 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns mcko output timing frequency fmck 0.2352 - 12.288 mhz duty cycle except 256fs at fs=32khz, 29.4khz dmck 40 50 60 % 256fs at fs=32khz, 29.4khz dmck - 33 - % exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns pll slave mode (pll reference clock = exlrck pin) exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 1/(64fs) - 1/(32fs) ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns
asahi kasei [AK5700] ms0569-e-01 2006/12 - 9 - parameter symbol min typ max units pll slave mode (pll reference clock = exbclk pin) exlrck input timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period pll3-0 bits = ?0010? tbck - 1/(32fs) - ns pll3-0 bits = ?0011? tbck - 1/(64fs) - ns pulse width low tbckl 0.4 x tbck - - ns pulse width high tbckh 0.4 x tbck - - ns external slave mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns exlrck input timing frequency 256fs fs 7.35 - 48 khz 512fs fs 7.35 - 26 khz 1024fs fs 7.35 - 13 khz dsp mode: pulse width high tlrckh tbck ? 60 - 1/fs ? tbck ns except dsp mode: duty cycle duty 45 - 55 % exbclk input timing period tbck 312.5 - - ns pulse width low tbckl 130 - - ns pulse width high tbckh 130 - - ns external master mode mcki input timing frequency 256fs fclk 1.8816 - 12.288 mhz 512fs fclk 3.7632 - 13.312 mhz 1024fs fclk 7.5264 - 13.312 mhz pulse width low tclkl 0.4/fclk - - ns pulse width high tclkh 0.4/fclk - - ns lrck output timing frequency fs 7.35 - 48 khz dsp mode: pulse width high tlrckh - tbck - ns except dsp mode: duty cycle duty - 50 - % bclk output timing period bcko1-0 bit = ?01? tbck - 1/(32fs) - ns bcko1-0 bit = ?10? tbck - 1/(64fs) - ns duty cycle dbck - 50 - %
asahi kasei [AK5700] ms0569-e-01 2006/12 - 10 - parameter symbol min typ max units audio interface timing (dsp mode) master mode lrck ? ? to bclk ? ? (note 17) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns lrck ? ? to bclk ? ? (note 18) tdbf 0.5 x tbck ? 40 0.5 x tbck 0.5 x tbck + 40 ns bclk ? ? to sdto (bckp bit = ?0?) tbsd ? 70 - 70 ns bclk ? ? to sdto (bckp bit = ?1?) tbsd ? 70 - 70 ns slave mode exlrck ? ? to exbclk ? ? (note 17) tlrb 0.4 x tbck - - ns exlrck ? ? to exbclk ? ? (note 18) tlrb 0.4 x tbck - - ns exbclk ? ? to exlrck ? ? (note 17) tblr 0.4 x tbck - - ns exbclk ? ? to exlrck ? ? (note 18) tblr 0.4 x tbck - - ns exbclk ? ? to sdto (bckp bit = ?0?) tbsd - - 80 ns exbclk ? ? to sdto (bckp bit = ?1?) tbsd - - 80 ns audio interface timing (left justified & i 2 s) master mode bclk ? ? to lrck edge (note 19) tmblr ? 40 - 40 ns lrck edge to sdto (msb) (except i 2 s mode) tlrd ? 70 - 70 ns bclk ? ? to sdto tbsd ? 70 - 70 ns slave mode exlrck edge to exbclk ? ? (note 19) tlrb 50 - - ns exbclk ? ? to exlrck edge (note 19) tblr 50 - - ns exlrck edge to sdto (msb) (except i 2 s mode) tlrd - - 80 ns exbclk ? ? to sdto tbsd - - 80 ns note 17. msbs, bckp bits = ?00? or ?11? note 18. msbs, bckp bits = ?01? or ?10? note 19. exbclk rising edge must not occur at the same time as exlrck edge.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 11 - parameter symbol min typ max units control interface timing (csp pin = ?l?) cclk period tcck 142 - - ns cclk pulse width low tcckl 56 - - ns pulse width high tcckh 56 - - ns cdti setup time tcds 28 - - ns cdti hold time tcdh 28 - - ns csn ?h? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns control interface timing (csp pin = ?h?) cclk period tcck 142 - - ns cclk pulse width low tcckl 56 - - ns pulse width high tcckh 56 - - ns cdti setup time tcds 28 - - ns cdti hold time tcdh 28 - - ns csn ?l? time tcsw 150 - - ns csn ? ? to cclk ? ? tcss 50 - - ns cclk ? ? to csn ? ? tcsh 50 - - ns power-down & reset timing pdn pulse width (note 20) tpd 150 - - ns pmadc ? ? to sdto valid (note 21) hpf1-0 bits = ?00? tpdv - 3088 - 1/fs hpf1-0 bits = ?01? tpdv - 1552 - 1/fs hpf1-0 bits = ?10? tpdv - 784 - 1/fs note 20. the AK5700 can be reset by the pdn pin = ?l?. note 21. this is the count of lrck ? ? from the pmadc bit = ?1?.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 12 - ? timing diagram bclk 1/fclk mcki tclkh tclkl vih vil 1/fmck mcko tmckl 50%dvdd tbck tbckh tbckl 50%dvdd dbck = tbckh / tbck x 100 tbckl / tbck x 100 dmck = tmckl x fmck x 100 lrck 1/fs tlrckh tlrckl 50%dvdd duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 2. clock timing (pll/ext master mode) lrck bclk 50%dvdd sdto 50%dvdd tbsd dbck tdbf 50%dvdd tlrckh tbck msb bclk 50%dvdd (bckp = "0") (bckp = "1") figure 3. audio interface timing (pll/ext master mode & dsp mode: msbs = ?0?)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 13 - lrck bclk 50%dvdd sdto 50%dvdd tbsd dbck tdbf 50%dvdd tlrckh tbck msb bclk 50%dvdd (bckp = "1") (bckp = "0") figure 4. audio interface timing (pll/ext master mode & dsp mode: msbs = ?1?) lrck 50%dvdd bclk 50%dvdd sdto 50%dvdd tbsd tmblr tbckl tlrd figure 5. audio interface timing (pll/ext master mode & except dsp mode)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 14 - 1/fs exlrck vih tlrckh vil tbck exbclk tbckh tbckl vih vil tblr exbclk vih vil (bckp = "0") (bckp = "1") figure 6. clock timing (pll slave mode; pll reference clock = exlrck or exbclk pin & dsp mode; msbs = 0) 1/fs exlrck vih tlrckh vil tbck exbclk tbckh tbckl vih vil tblr exbclk vih vil (bckp = "1") (bckp = "0") figure 7. clock timing (pll slave mode; pll reference clock = exlrck or exbclk pin & dsp mode; msbs = 1)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 15 - 1/fclk mcki tclkh tclkl vih vil 1/fs exlrck vih vil tbck exbclk tbckh tbckl vih vil tlrckh tlrckl fmck mcko tmckl 50%dvdd dmck = tmckl x fmck x 100 duty = tlrckh x fs x 100 = tlrckl x fs x 100 figure 8. clock timing (pll slave mode; pll reference clock = mcki pin & except dsp mode) exlrck exbclk sdto 50%dvdd tbsd tlrb tlrckh msb vil vih vil vih exbclk vil vih (bckp = "0") (bckp = "1") figure 9. audio interface timing (pll slave mode & dsp mode; msbs = 0)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 16 - exlrck exbclk sdto 50%dvdd tbsd tlrb tlrckh msb vil vih vil vih exbclk vil vih (bckp = "1") (bckp = "0") figure 10. audio interface timing (pll slave mode, dsp mode; msbs = 1) 1/fclk mcki tclkh tclkl vih vil 1/fs exlrck vih vil tbck exbclk tbckh tbckl vih vil tlrckh tlrckl duty = tlrckh x fs x 100 tlrckl x fs x 100 figure 11. clock timing (ext slave mode)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 17 - exlrck vih vil tblr exbclk vih vil tlrd sdto 50%dvdd tlrb tbsd msb figure 12. audio interface timing (pll/ext slave mode)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 18 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 13. write command input timing (csp pin = ?l?) csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 14. write data input timing (csp pin = ?l?)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 19 - csn vih vil tcss cclk tcds vih vil cdti vih tcckh tcckl tcdh vil c1 c0 r/w tcck figure 15. write command input timing (csp pin = ?h?) csn vih vil tcsh cclk vih vil cdti vih tcsw vil d1 d0 d2 figure 16. write data input timing (csp pin = ?h?)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 20 - pmadc bit tpdv sdto 50%dvdd figure 17. power down & reset timing 1 tpd pdn vil figure 18. power down & reset timing 2
asahi kasei [AK5700] ms0569-e-01 2006/12 - 21 - operation overview ? system clock there are the following five clock modes to interface with external devices (see table 1 and table 2.) mode pmpll bit m/s bit pll3-0 bits figure pll master mode (note 22) 1 1 see table 4 figure 19 pll slave mode 1 (pll reference clock: mcki pin) 1 0 see table 4 figure 20 pll slave mode 2 (pll reference clock: ex lrck or exbclk pin) 1 0 see table 4 figure 21 ext slave mode 0 0 x figure 22 ext master mode (note 23) 0 0 x figure 23 note 22. if m/s bit = ?1?, pmpll bit = ?0? and mcko bit = ?1? during the setting of pll master mode, the invalid clocks are output from mcko pin when mcko bit is ?1?. note 23. in case of ext master mode, the register should be set as figure 45. table 1. clock mode setting (x: don?t care) mode mcko bit mcko pin mcki pin bclk pin, exbclk pin lrck pin, exlrck pin 0 ?l? pll master mode 1 selected by ps1-0 bits selected by pll3-0 bits bclk pin (selected by bcko1-0 bits) lrck pin (1fs) 0 ?l? pll slave mode (pll reference clock: mcki pin) 1 selected by ps1-0 bits selected by pll3-0 bits exbclk pin ( 32fs) exlrck pin (1fs) pll slave mode (pll reference clock: exlrck or exbclk pin) 0 ?l? gnd exbclk pin (selected by pll3-0 bits) exlrck pin (1fs) ext slave mode 0 ?l? selected by fs1-0 bits exbclk pin ( 32fs) exlrck pin (1fs) ext master mode 0 ?l? selected by fs1-0 bits bclk pin (selected by bcko1-0 bits) lrck pin (1fs) table 2. clock pins state in clock mode ? master mode/slave mode the m/s bit selects either master or slave mode. m/s bit = ?1? selects master mode and ?0? selects slave mode. when the AK5700 is power-down mode (pdn pin = ?l?) and exits reset state, the AK5700 is slave mode. after exiting reset state, the AK5700 goes to master mode by changing m/s bit = ?1?. m/s bit mode used pins 0 slave mode exbclk, exlrck default 1 master mode bclk, lrck table 3. select master/salve mode
asahi kasei [AK5700] ms0569-e-01 2006/12 - 22 - ? pll mode when pmpll bit is ?1?, a fully integrated analog phase locked loop (pll) generates a clock that is selected by the pll3-0 and fs3-0 bits. the pll lock time is shown in table 4, whenever the AK5700 is supplied to a stable clocks after pll is powered-up (pmpll bit = ?0? ?1?) or sampling frequency changes. 1) setting of pll mode r and c of vcoc pin mode pll3 bit pll2 bit pll1 bit pll0 bit pll reference clock input pin input frequency r[ ] c[f] pll lock time (max) 0 0 0 0 0 exlrck pin 1fs 6.8k 220n 80ms 2 0 0 1 0 exbclk pin 32fs 10k 4.7n 2ms 10k 10n 4ms 3 0 0 1 1 exbclk pin 64fs 10k 4.7n 2ms 10k 10n 4ms 4 0 1 0 0 mcki pin 11.2896mhz 10k 4.7n 40ms 5 0 1 0 1 mcki pin 12.288mhz 10k 4.7n 40ms 6 0 1 1 0 mcki pin 12mhz 10k 4.7n 40ms 7 0 1 1 1 mcki pin 24mhz 10k 4.7n 40ms 8 1 0 0 0 mcki pin 19.2mhz 10k 4.7n 40ms 9 1 0 0 1 mcki pin 12mhz (note24) 10k 4.7n 40ms default 12 1 1 0 0 mcki pin 13.5mhz 10k 10n 40ms 13 1 1 0 1 mcki pin 27mhz 10k 10n 40ms 14 1 1 1 0 mcki pin 13mhz 10k 220n 60ms 15 1 1 1 1 mcki pin 26mhz 10k 220n 60ms others others n/a note 24. see table 5 regarding the difference between pll3-0 bits = ?0110?(mode 6) and ?1001?(mode 9). clock jitter is lower in mode9 than mode6 respectively. table 4. setting of pll mode (*fs: sampling frequency) 2) setting of sampling frequency in pll mode when pll reference clock input is mcki pin, the sampling frequency is selected by fs3-0 bits as defined in table 5. mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency 0 0 0 0 0 8khz 1 0 0 0 1 12khz 2 0 0 1 0 16khz 3 0 0 1 1 24khz 4 0 1 0 0 7.35khz 7.349918khz (note25) 5 0 1 0 1 11.025khz 11.024877khz (note25) 6 0 1 1 0 14.7khz 14.69984khz (note25) 7 0 1 1 1 22.05khz 22.04975khz (note25) 10 1 0 1 0 32khz 11 1 0 1 1 48khz 14 1 1 1 0 29.4khz 29.39967khz (note25) 15 1 1 1 1 44.1khz 44.0995khz (note25) default others others n/a note 25. in case of pll3-0 bits = ?1001? table 5. setting of sampling frequency at pmpll bit = ?1? and reference clock=mcki pin
asahi kasei [AK5700] ms0569-e-01 2006/12 - 23 - when pll reference clock input is exlrck or exbclk pin, the sampling frequency is selected by fs3 and fs2 bits (see table 6). mode fs3 bit fs2 bit fs1 bit fs0 bit sampling frequency range 0 0 0 don?t care don?t care 7.35khz fs 12khz 1 0 1 don?t care don?t care 12khz < fs 24khz 2 1 don?t care don?t care don?t care 24khz < fs 48khz default others others n/a table 6. setting of sampling frequency at pmpll bit = ?1? and reference=exlrck/exbclk ? pll unlock state 1) pll master mode (pmpll bit = ?1?, m/s bit = ?1?) in this mode, lrck and bclk pins go to ?l? and irregular frequency clock is output from mcko pins at mcko bit is ?1? before the pll goes to lock state after pmpll bit = ?0? ? ?1?. if mcko bit is ?0?, mcko pin goes to ?l? (see table 7). in dsp mode 0, bclk and lrck start to output corresponding to ach data after pll goes to lock state by setting pmpll bit = ?0? ? ?1?. when msbs and bckp bits are ?01? or ?10? in dsp mode 0, bclk ?h? time of the first pulse becomes shorter by 1/(256fs) than ?h? time except for the first pulse. when sampling frequency is changed, bclk and lrck pins do not output irregular frequency clocks but go to ?l? by setting pmpll bit to ?0?. mcko pin pll state mcko bit = ?0? mcko bit = ?1? bclk pin lrck pin after that pmpll bit ?0? ? ?1? ?l? output invalid ?l? output ?l? output pll unlock (except above case) ?l? output invalid invalid invalid pll lock ?l? output see table 9 see table 10 1fs output table 7. clock operation at pll master mode (pmpll bit = ?1?, m/s bit = ?1?) 2) pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) in this mode, an invalid clock is output from mcko pin before the pll goes to lock state after pmpll bit = ?0? ? ?1?. after that, the clock selected by table 9 is output from mcko pin when pll is locked. adc outputs invalid data when the pll is unlocked. mcko pin pll state mcko bit = ?0? mcko bit = ?1? after that pmpll bit ?0? ? ?1? ?l? output invalid pll unlock (except above case) ?l? output invalid pll lock ?l? output see table 9 table 8. clock operation at pll slave mode (pmpll bit = ?1?, m/s bit = ?0?)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 24 - ? pll master mode (pmpll bit = ?1?, m/s bit = ?1?) when an external clock (11.2896mhz, 12mhz, 12.288mhz, 13mhz, 13.5mhz, 19.2mhz, 24mhz, 26mhz or 27mhz) is input to mcki pin, the mcko, bclk and lrck clocks are generated by an internal pll circuit. the mcko output frequency is selected by ps1-0 bits (see table 9) and the output is enabled by mcko bit. the bclk output frequency is selected among 32fs or 64fs, by bcko1-0 bits (see table 10). a k5700 dsp or p mcko bclk lrck sdto bclk lrck sdti mcki 1fs 32fs, 64fs 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz mclk figure 19. pll master mode mode ps1 bit ps0 bit mcko pin 0 0 0 256fs default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs table 9. mcko output frequency (pll mode, mcko bit = ?1?) bcko1 bit bcko0 bit bclk output frequency 0 0 n/a 0 1 32fs default 1 0 64fs 1 1 n/a table 10. bclk output frequency at master mode
asahi kasei [AK5700] ms0569-e-01 2006/12 - 25 - ? pll slave mode (pmpll bit = ?1?, m/s bit = ?0?) a reference clock of pll is selected among the input clocks to mcki, exbclk or exlrck pin. the required clock to the AK5700 is generated by an internal pll circuit. input frequency is selected by pll3-0 bits (see table 4). a) pll reference clock: mcki pin exbclk and exlrck inputs should be synchronized with mcko output. the phase between mcko and exlrck dose not matter. mcko pin outputs the frequency selected by ps1-0 bits (see table 9) and the output is enabled by mcko bit. sampling frequency can be selected by fs3-0 bits (see table 5). a k5700 dsp or p mcko exbclk exlrck sdto bclk lrck sdti mcki 1fs 32fs mclk 256fs/128fs/64fs/32fs 11.2896mhz, 12mhz, 12.288mhz, 13mhz 13.5mhz, 19.2mhz, 24mhz, 26mhz, 27mhz figure 20. pll slave mode 1 (pll reference clock: mcki pin) the external clocks (mcki, exbclk and exlrck) should always be present whenever the adc is in operation (pmadc bit = ?1?). if these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic inte rnally. if the external clocks are not present, the adc should be in the power-down mode (pmadc bit = ?0?). b) pll reference clock: exbclk or exlrck pin sampling frequency corresponds to 7.35khz to 48khz by changing fs3-0 bits (see table 6). a k5700 dsp or p mcki exbclk exlrck sdto bclk lrck sdti 1fs 32fs, 64fs figure 21. pll slave mode 2 (pll reference clock: exlrck or exbclk pin)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 26 - ? ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) when pmpll bit is ?0?, the AK5700 becomes ext mode. master clock is input from mcki pin, the internal pll circuit is not operated. this mode is compatible with i/f of the normal audio codec. the clocks required to operate are mcki (256fs, 512fs or 1024fs), exlrck (fs) and exbclk ( 32fs). the master clock (mcki) should be synchronized with exlrck. the phase between these clocks does not matter. the input frequency of mcki is selected by fs1-0 bits (see table 11). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 512fs 7.35khz 26khz 3 don?t care 1 1 256fs 7.35khz 48khz default table 11. mcki frequency at ext slave mode (pmpll bit = ?0?, m/s bit = ?0?) the external clocks (mcki, exbclk and exlrck) should always be present whenever the adc is in operation (pmadc bit = ?1?). if these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic inte rnally. if the external clocks are not present, the adc should be in the power-down mode (pmadc bit = ?0?). a k5700 dsp or p mcki exbclk exlrck sdto bclk lrck sdti mcko 1fs 32fs mclk 256fs, 512fs or 1024fs figure 22. ext slave mode
asahi kasei [AK5700] ms0569-e-01 2006/12 - 27 - ? ext master mode (pmpll bit = ?0?, m/s bit = ?1?, te3-0 bits = ?0101?, tmaster bit = ?1?) the AK5700 becomes ext master mode by setting as figure 45. master clock is input from mcki pin, the internal pll circuit is not operated. the clock required to operate is mcki (256fs, 512fs or 1024fs). the input frequency of mcki is selected by fs1-0 bits (see table 12). mode fs3-2 bits fs1 bit fs0 bit mcki input frequency sampling frequency range 0 don?t care 0 0 256fs 7.35khz 48khz 1 don?t care 0 1 1024fs 7.35khz 13khz 2 don?t care 1 0 512fs 7.35khz 26khz 3 don?t care 1 1 256fs 7.35khz 48khz default table 12. mcki frequency at ext master mode mcki should always be present whenever the adc is in operation (pmadc bit = ?1?). if mcki is not provided, the AK5700 may draw excess current and it is not possible to operate properly beca use utilizes dynamic refreshed logic internally. if mcki is not present, the adc should be in the power-down mode (pmadc bits = ?0?). a k5700 dsp or p mcki bclk lrck sdto bclk lrck sdti mcko 1fs 32fs or 64fs mclk 256fs, 512fs or 1024fs figure 23. ext master mode bcko1 bit bcko0 bit bclk output frequency 0 0 n/a 0 1 32fs default 1 0 64fs 1 1 n/a table 13. bclk output frequency at master mode
asahi kasei [AK5700] ms0569-e-01 2006/12 - 28 - ? bypass mode when thr bit = ?1?, m/s bit = ?0? and pmadc bit = ?0? input clocks and data of exlrck, exbclk and exsdti pins are bypassed to lrck, bclk and sdto pins, respectively. when thr bit = ?1?, m/s bit = ?0? and pmadc bit = ?1? input clocks of exlrck and exbclk pins are bypassed to lrck and bclk pins, and adc data is output from sdto pin. thr bit m/s bit pmadc bit bclk/lrck sdto mode figure 0 ?l? ?l? power down default 0 1 ?l? adc data slave mode 0 output ?l? power down 0 1 1 output adc data master mode 0 exbclk/exlrck exsdti bypass mode figure 24 0 1 exbclk/exlrck adc data slave & bypass figure 25 0 n/a n/a n/a 1 1 1 output adc data master mode table 14. bypass mode select AK5700 dsp or p bclk lrck sdti lrck sdto 1fs bclk 32fs dsp or p lrck sdto 1fs bclk 32fs exbclk exlrck exsdti figure 24. bypass mode AK5700 dsp or p bclk lrck sdti lrck sdto 1fs bclk 32fs dsp or p lrck analog in 1fs bclk 32fs exbclk exlrck a in figure 25. slave & bypass mode
asahi kasei [AK5700] ms0569-e-01 2006/12 - 29 - ? audio interface format fore types of data format are available and are selected by setting the dif1-0 bits (see table 15). in all modes, the serial data is msb first, 2?s complement format. audio interface formats can be used in both master and slave modes. lrck, bclk and sdto pins are used in master mode. exlrck, exbclk and sdto pins are used in slave mode. in modes 2 and 3, the sdto is clocked out on the falling edge (? ?) of bclk/exbclk. sdto pin outputs same data two times in one period of exlrck/lrck. mode dif1 bit dif0 bit sdto bclk, exbclk figure 0 0 0 dsp mode 0 32fs see table 16 1 0 1 reserved - - 2 1 0 msb justified 32fs figure 30 3 1 1 i 2 s compatible 32fs figure 31 default table 15. audio interface format in mode 0 (dsp mode 0), the audio i/f timing is changed by bckp and msbs bits. when bckp bit is ?0?, sdto data is output by rising edge (? ?) of bclk/exbclk. when bckp bit is ?1?, sdto data is output by falling edge (? ?) of bclk/exbclk. msb data position of sdto can be shifted by msbs bit. the shifted period is a half of bclk/exbclk. dif1 dif0 msbs bckp audio interface format 0 0 msb of sdto is output by the rising edge (? ?) of the first bclk/exbclk after the rising edge (? ?) of lrck/exlrck (figure 26). 0 1 msb of sdto is output by the falling edge (? ?) of the first bclk/exbclk after the rising edge (? ?) of lrck/exlrck (figure 27). 1 0 msb of sdto is output by next rising edge (? ?) of the falling edge (? ?) of the first bclk/exbclk after the rising edge (? ?) of lrck/exlrck (figure 28). 0 0 1 1 msb of sdto is output by next falling edge (? ?) of the rising edge (? ?) of the first bclk/exbclk after the rising edge (? ?) of lrck/exlrck (figure 29). table 16. audio interface format in mode 0 if 16-bit data that adc outputs is converted to 8-bit data by removing lsb 8-bit, ? ? 1? at 16bit data is converted to ? ? 1? at 8-bit data. and when the dac playbacks this 8-bit data, ? ? 1? at 8-bit data will be converted to ? ? 256? at 16-bit data and this is a large offset. this offset can be removed by addi ng the offset of ?128? to 16-bit data before converting to 8-bit data.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 30 - exlrck / lrck (m/s=0) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 exbclk(32fs) bclk(32fs) sdto ( o ) exlrck / lrck (m/s=1) figure 26. mode 0 timing (bckp = ?0?, msbs = ?0?, m/s = ?0? or ?1?) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 exbclk(32fs) bclk(32fs) sdto ( o ) exlrck / lrck (m/s=0) exlrck / lrck (m/s=1) figure 27. mode 0 timing (bckp = ?1?, msbs = ?0?, m/s = ?0? or ?1?) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 exbclk(32fs) bclk(32fs) sdto ( o ) exlrck / lrck (m/s=0) exlrck / lrck (m/s=1) figure 28. mode 0 timing (bckp = ?0?, msbs = ?1?, m/s = ?0? or ?1?) 15 0 1 8 14 15 17 18 30 31 0 1 8 14 15 17 18 30 31 15 8 2 1 16 29 0 15 8 21 0 13 16 15:msb, 0:lsb 1/fs 2 14 14 2 1/fs 15 210 14 15 2 1 0 14 exbclk(32fs) bclk(32fs) sdto ( o ) exlrck / lrck (m/s=0) exlrck / lrck (m/s=1) figure 29. mode 0 timing (bckp = ?1?, msbs = ?1?, m/s = ?0? or ?1?) note : the data from 0 to 15 bits is the same as from 16 to 31 bits at the figure 26, figure 27, figure 28, figure 29
asahi kasei [AK5700] ms0569-e-01 2006/12 - 31 - 0 1 2 8 9 10 12 13 15 0 1 2 8 9 10 12 13 15 0 15 1 14 4 8 7 6 0 32 11 14 1 5 15 14 4 876 0 3 2 1 5 14 11 15 13 0 1 2 3 14 15 17 18 31 0 1 2 14 15 17 18 31 0 15 1 14 0 15 14 1 2 21 15 15:msb, 0:lsb 1/fs 2 1 13 16 0 16 3 13 3 13 13 3 exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) exbclk(64fs) bclk(64fs) sdto ( o ) figure 30. mode 2 timing (msb justified, m/s = ?0? or ?1?) 0 1 2 4 9 10 12 13 15 0 1 2 4 9 10 12 13 15 0 0 1 15 5 13 7 7 1 43 11 14 2 6 0 15 5 13 7 7 1 4 3 2 6 14 11 0 13 0 1 2 3 14 15 17 18 31 0 1 2 4 14 15 17 18 31 0 1 15 0 15 13 2 1 15:msb, 0:lsb 2 1 14 16 0 16 3 14 14 3 2 14 3 4 exlrck lrck exbclk(32fs) bclk(32fs) sdto ( o ) exbclk(64fs) bclk(64fs) sdto ( o ) 1/fs figure 31. mode 3 timing (i 2 s, m/s = ?0? or ?1?) note : the data from 0 to 15 bits is the same as when lrck is ?h? or ?l? at the figure 30, figure 31
asahi kasei [AK5700] ms0569-e-01 2006/12 - 32 - ? digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut-off frequency of the hpf is selected by hpf1-0 bits (see table 17) and scales with sampling rate (fs). the default value is 3.4hz (@fs=44.1khz). fc hpf1 bit hpf0 bit fs=44.1khz fs=22.05khz fs=11.025khz 0 0 3.4hz 1.7hz 0.85hz default 0 1 6.8hz 3.4hz 1.7hz 1 0 13.6hz 6.8hz 3.4hz 1 1 n/a n/a n/a table 17. digital hpf cut-off frequency ? mic/line input selector the AK5700 has input selector. when mdif1 bit is ?0?, ain bit selects ain1or ain2. when mdif1 bit is ?1?, ain1pin become ain+ pin . in this case, full-differential input is available (figure 33). when full-differential input is used, the signal should not be input to the pins marked by ?x? in table 19. mdif1 bit ain bit ach ain1 default 0 ain1 ain2 1 ain2 0 ain1 0 1 n/a n/a x ain+/ ? 1 x ain+/ ? table 18. mic/line in path select register pin mdif1 bit ain1 ain1+ ain2 ain1 ? 0 o o - 1 o x o table 19. handling of mic/line input pins (?-?: n/a; ?x?: signal should not be input.) a in1/ain+ pin a dc a in ? pin ain bit mdif1 bit a in2 pin AK5700 figure 32. mic/line input selector
asahi kasei [AK5700] ms0569-e-01 2006/12 - 33 - ain+ pin ain ? pin mpwr pin a k5700 mic-amp 1k 1k figure 33. connection example for full-differential mic input (mdif1bit = ?1?) ? mic gain amplifier the AK5700 has a gain amplifier for microphone input. the gain of mic-amp is selected by the mgain1-0 bits (see table 20). the typical input impedance is 60k (typ)@mgain1-0 bits = ?00? or 30k (typ)@mgain1-0 bits = ?01? or ?10?. mgain1 bit mgain0 bit input gain 0 0 0db 0 1 +15db default 1 0 +30db 1 1 n/a table 20. mic input gain ? mic power when pmmp bit = ?1?, the mpwr pin supplies power for the microphone. this output voltage is typically 0.75 x avdd and the load resistance is minimum 1.0k . in case of using two sets of mono mic, the load resistance is minimum 2.0k for each channel. no capacitor must not be connected directly to mpwr pin (see figure 34). pmmp bit mpwr pin 0 hi-z default 1 output table 21. mic power mpwr pin 2k mic power microphone a in1 pin microphone a in2 pin 2k figure 34. mic block circuit
asahi kasei [AK5700] ms0569-e-01 2006/12 - 34 - ? alc operation the alc (automatic level control) is done by alc block when alc bit is ?1?. 1. alc limiter operation during the alc limiter operation, when the output exceeds the alc limiter detection level (table 22), the ivl value is attenuated automatically by the amount defined by the alc limiter att step (table 23). when zelmn bit = ?0? (zero cross detec tion is enabled), the ivl value is ch anged by alc limite r operation at the individual zero crossing point of zero crossing timeout. ztm 1-0 bits set the zero crossing timeout period of both alc limiter and recovery operation (table 24). when zelmn bit = ?1? (zero cross detecti on is disabled), ivl value is immedi ately (period: 1/fs) changed by alc limiter operation. attenuation step is fixed to 1 step regardless as the setting of lmat1-0 bits. the attenuation operation is done continuously until the input signal level becomes alc limiter detection level (table 22) or less. after completing the attenuation operation, unless alc bit is changed to ?0?, the operation repeats when the input signal level exceeds lmth1-0 bits. lmth1 lmth0 alc limier detection level alc recovery waiting counter reset level 0 0 alc output ? 2.5dbfs ? 2.5dbfs > alc output ? 4.1dbfs default 0 1 alc output ? 4.1dbfs ? 4.1dbfs > alc output ? 6.0dbfs 1 0 alc output ? 6.0dbfs ? 6.0dbfs > alc output ? 8.5dbfs 1 1 alc output ? 8.5dbfs ? 8.5dbfs > alc output ? 12dbfs table 22. alc limiter detection level / recovery counter reset level zelmn lmat1 lmat0 alc limiter att step 0 0 1 step 0.375db default 0 1 2 step 0.750db 1 0 4 step 1.500db 0 1 1 8 step 3.000db 1 x x 1step 0.375db table 23. alc limiter att step zero crossing timeout period ztm1 ztm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 24. alc zero crossing timeout period
asahi kasei [AK5700] ms0569-e-01 2006/12 - 35 - 2. alc recovery operation the alc recovery operation waits for the wtm1-0 bits (table 25) to be set after completing the alc limiter operation. if the input signal does not exceed ?alc recovery waiting counter reset level? (table 22) during the wait time, the alc recovery operation is done. the ivl value is automatically incremented by rgain1-0 bits (table 26) up to the set reference level (table 27) with zero crossing detection which timeout period is set by ztm1-0 bits (table 24). the alc recovery operation is done at a period set by wtm1-0 bits. if ztm1-0 is longer than wtm1-0 and no zero crossing occurs, the alc recovery operation is done at a period set by ztm1-0 bits. for example, when the current ivol value is 30h and rgain1-0 bits are set to ?01?, ivol is changed to 32h by the auto limiter operation and then the input signal level is gained by 0.75db (=0.375db x 2). when the ivol value exceeds the reference level (ref7-0), the ivol values are not increased. when ?alc recovery waiting counter reset level (lmth1-0) output signal < alc limiter detection level (lmth1-0)? during the alc recovery operation, the waiting timer of alc recovery operation is reset. when ?alc recovery waiting counter reset level (lmth1-0) > output signal?, the waiting timer of alc recovery operation starts. the alc operation corresponds to the impulse noise. when the impulse noise is input, the alc recovery operation becomes faster than a normal recovery operation. when large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. alc recovery operation waiting period wtm1 wtm0 8khz 16khz 44.1khz 0 0 128/fs 16ms 8ms 2.9ms default 0 1 256/fs 32ms 16ms 5.8ms 1 0 512/fs 64ms 32ms 11.6ms 1 1 1024/fs 128ms 64ms 23.2ms table 25. alc recovery operation waiting period rgain1 rgain0 gain step 0 0 1 step 0.375db default 0 1 2 step 0.750db 1 0 3 step 1.125db 1 1 4 step 1.500db table 26. alc recovery gain step ref7-0 gain(db) step f1h +36.0 f0h +35.625 efh +35.25 : : e2h +30.375 e1h +30.0 default e0h +29.625 : : 03h ? 53.25 02h ? 53.625 01h ? 54.0 0.375db 00h mute table 27. reference level at alc recovery operation
asahi kasei [AK5700] ms0569-e-01 2006/12 - 36 - 3. example of alc operation table 28 shows the examples of the alc setting for mic recording. fs=8khz fs=44.1khz register name comment data operation data operation lmth limiter detection level 01 ? 4.1dbfs 01 ? 4.1dbfs zelmn limiter zero crossing de tection 0 enable 0 enable ztm1-0 zero crossing timeout period 00 16ms 10 11.6ms wtm1-0 recovery waiting period *wtm1-0 bits should be the same data as ztm1-0 bits 00 16ms 10 11.6ms ref7-0 maximum gain at recovery operation e1h +30db e1h +30db ivl7-0 gain of ivol 91h 0db 91h 0db lmat1-0 limiter att step 00 1 step 00 1 step rgain1-0 recovery gain step 00 1 step 00 1 step alc alc enable 1 enable 1 enable table 28. example of the alc setting the following registers should not be changed during the alc operation. these bits should be changed after the alc operation is finished by alc bit = ?0? or pmadc bit = ?0?. ? lmth, lmat1-0, wtm1-0, ztm1-0, rgain1-0, ref7-0, zelmn manual mode * the value of ivol should be the same or smaller than ref?s wr (ztm1-0, wtm1-0) wr (ref7-0) wr (ivl7-0) wr (lmat1-0, rgain1-0, zelmn, lmth1-0; alc= ?1?) example: limiter = zero crossing enable recovery cycle = 16ms@8khz limiter and recovery step = 1 maximum gain = +30.0db limiter detection level = ? 4.1dbfs alc bit = ?1? ( 1 ) addr=18h, data=91h (2) addr=1ah, data=00h (3) addr=1bh, data=e1h alc operation (4) addr=1ch, data=81h note : wr : write figure 35. registers set-up sequence at alc operation
asahi kasei [AK5700] ms0569-e-01 2006/12 - 37 - ? input digital volume (manual mode) the input digital volume becomes a manual mode when alc bit is ?0?. this mode is used in the case shown below. 1. after exiting reset state, set-up the registers for the alc operation (ztm1-0, lmth and etc) 2. when the registers for the alc operation (limiter period, recovery period and etc) are changed. for example; when the change of the sampling frequency. 3. when ivol is used as a manual volume. ivl7-0 bits set the gain of the volume control (table 29). the ivol value is changed at zero crossing or timeout. zero crossing timeout period is set by ztm1-0 bits. if ivl7-0 bits are written during pmadc bit = ?0?, ivol opera tion starts with the written values at the end of the adc initialization cycle after pmadc bit is changed to ?1?. ivl7-0 gain (db) step f1h +36.0 f0h +35.625 efh +35.25 : : 92h +0.375 91h 0.0 default 90h ? 0.375 : : 03h ? 53.25 02h ? 53.625 01h ? 54 0.375db 00h mute table 29. input digital volume setting
asahi kasei [AK5700] ms0569-e-01 2006/12 - 38 - when writing to the ivl7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. if not, ivl is not changed since zero crossi ng counter is reset at every write operation. if the same register value as the previous write operation is written to iv l, this write operation is ignored and zero crossing counter is not reset. therefore, ivl can be written by an interval less than zero crossing timeout. a lc bit a lc status disable enable disable ivl7-0 bits e1h(+30db) internal ivl e1h(+30db) e1(+30db) --> f1(+36db) e1(+30db) (1) (2) figure 36. ivol value during alc operation (1) the wait time from alc bit = ?1? to alc operation start by ivl7-0 bits is at most recovery time (wtm1-0 bits) plus zerocross timeout period (ztm1-0 bits). (2) writing to ivl register (18h) is ignored during alc ope ration. after alc is disabled, the ivol changes to the last written data by zero crossing or timeout. when alc is enabled again, alc bit should be set to ?1? by an interval more than zero crossing timeout period after alc bit = ?0?. ? system reset upon power-up, the AK5700 should be reset by bringing the pdn pin = ?l?. this ensures that all internal registers reset to their initial values. the adc enters an initialization cycle that starts when the pmadc bit is changed from ?0? to ?1?. the initialization cycle time is 3088/fs=70.0ms@fs=44.1khz when hpf1-0 bits are ?00? (see table 30 ). during the initia lization cycle, the adc digital data outputs of both channels are forced to a 2?s complement, ?0?. the adc output reflects the analog input signal after the initialization cycle is complete. init cycle hpf1 bit hpf0 bit cycle fs=44.1khz fs=22.05khz fs=11.025khz 0 0 3088/fs 70.0ms (recommendation) 140.0ms 280.1ms default 0 1 1552/fs 35.2ms 70.4ms (recommendation) 140.8ms 1 0 784/fs 17.8ms 35.6ms 71.1ms (recommendation) 1 1 n/a n/a n/a n/a table 30. adc initialization cycle
asahi kasei [AK5700] ms0569-e-01 2006/12 - 39 - ? serial control interface internal registers may be written by using the 3-wire p interface pins (csn, cclk and cdti). csp pin selects the polarity of csn pin and chip address. 1) csp pin = ?l? the data on this interface consists of a 2-bit chip address (fix ed to ?10?), read/write (fixed to ?1?), register address (msb first, 5bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? ?) of cclk. address and data are latched on the 16th cclk rising edge (? ?) after csn falling edge(? ?). clock speed of cclk is 7mhz (max). the value of internal registers are initialized by pdn pin = ?l?. csn cclk 0 1 2 345 67891011 12 13 14 15 cdti c1 c0 a 2 a 3 a 1 a 0 a 4 d7d6d5d4d3d2d1d0 r/w c1-c0: chip address (c1 = ?1?, c0 = ?0?); fixed to ?10? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a 4-a0: register address d7-d0: control data ?1? ?0? ?1? figure 37. serial control i/f timing (csp pin = ?l?) 2) csp pin = ?h? the data on this interface consists of a 2-bit chip address (fix ed to ?01?), read/write (fixed to ?1?), register address (msb first, 5bits) and control data (msb first, 8bits). each bit is clocked in on the rising edge (? ?) of cclk. address and data are latched on the 16th cclk rising edge (? ?) after csn rising edge(? ?). clock speed of cclk is 7mhz (max). the value of internal registers are initialized by pdn pin = ?l?. csn cclk 0 1 2 3 45 67891011 12 13 14 15 cdti c1 c0 a 2 a 3 a 1 a 0 a 4 d7d6d5d4d3d2d1d0 r/w c1-c0: chip address (c1 = ?0?, c0 = ?1?); fixed to ?01? r/w: read/write (?1?: write, ?0?: read); fixed to ?1? a 4-a0: register address d7-d0: control data ?1? ?1? ?0? figure 38. serial control i/f timing (csp pin = ?h?)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 40 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 0 0 0 0 0 pmvcm 0 pmadc 11h pll control 0 0 pll3 pll2 pll1 pll0 m/s pmpll 12h signal select 0 0 0 pmmp 0 mdif1 0 ain 13h mic gain control 0 0 0 0 0 0 mgain1 mgain0 14h audio format select 0 0 1 0 msbs bckp dif1 dif0 15h fs select hpf1 hpf0 bcko1 bcko0 fs3 fs2 fs1 fs0 16h clock output select 0 0 0 0 thr mcko ps1 ps0 17h reserved 0 0 0 0 0 0 0 1 18h input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 19h reserved 1 0 0 1 0 0 0 1 1ah timer select 0 0 0 0 ztm1 ztm0 wtm1 wtm0 1bh alc mode control 1 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 1ch alc mode control 2 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 1dh mode control 1 te3 te2 te1 te0 0 0 0 0 1eh mode control 2 0 0 0 0 0 0 tmaster 0 note 26. pdn pin = ?l? resets the registers to their default values. note 27. ?0? must be sent to the register written as ?0? and ?1? must be sent to the register written as ?1?. for addresses except for 10h to 1eh, data must not be written.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 41 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 10h power management 0 0 0 0 0 pmvcm 0 pmadc default 0 0 0 0 0 0 0 0 pmadc: mic-amp and adc power management 0: power down (default) 1: power up when the pmadc bit is changed from ?0? to ?1?, the initialization cycle (3088/fs=70.0ms@fs= 44.1khz, hpf1-0 bits = ?00?) starts. after initializing, digital data of the adc is output. pmvcm: vcom power management 0: power down (default) 1: power up when any blocks are powered-up, the pmvcm bit must be set to ?1?. pmvcm bit can be set to ?0? only when pmadc=pmpll=pmmp=mcko bits = ?0?. each block can be powered-down respectively by writing ?0? in each bit of this address. when the pdn pin is ?l?, all blocks are powered-down regardless as setting of this address. in this case, register is initialized to the default value. when pmvcm, pmadc, pmpll and mcko bits are ?0?, all bl ocks are powered-down. the register values remain unchanged. power supply current is 20 a(typ) in this case. for fully shut down (typ. 1 a), pdn pin should be ?l?. when the adc is not used, external clocks may not be present. when adc is used, external clocks must always be present. addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h pll control 0 0 pll3 pll2 pll1 pll0 m/s pmpll default 0 0 1 0 0 1 0 0 pmpll: pll power management 0: ext mode and power down (default) 1: pll mode and power up m/s: master / slave mode select 0: slave mode (default) 1: master mode pll3-0: pll reference clock select (see table 4) default: ?1001?(m cki pin=12mhz)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 42 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 12h signal select 0 0 0 pmmp 0 mdif1 0 ain default 0 0 0 0 0 0 0 0 ain: adc input source select 0: ain1 pin (default) 1: ain2 pin mdif1: adc input type select 0: single-ended input (ain1/ain2 pin: default) 1: full-differential input (ain+/ain ? pin) pmmp: mpwr pin power management 0: power down: hi-z (default) 1: power up addr register name d7 d6 d5 d4 d3 d2 d1 d0 13h mic gain control 0 0 0 0 0 0 mgain1 mgain0 default 0 0 0 0 0 0 0 1 mgain1-0: mic-amp gain control (see table 20) default: ?01?(+15db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 14h audio format select 0 0 1 0 msbs bckp dif1 dif0 default 0 0 1 0 0 0 1 1 dif1-0: audio interface format (see table 15) default: ?11? (i 2 s) bckp: bclk/exbclk polarity at dsp mode (see table 16) ?0?: sdto is output by the rising edge (? ?) of bclk/exbclk. (default) ?1?: sdto is output by the falling edge (? ?) of bclk/exbclk. msbs: lrck/exlrck polarity at dsp mode (see table 16) ?0?: the rising edge (? ?) of lrck/exlrck is half clock of bclk/exbclk before the channel change. (default) ?1?: the rising edge (? ?) of lrck/exlrck is one clock of bclk/exbclk before the channel change.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 43 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 15h fs select hpf1 hpf0 bcko1 bcko0 fs3 fs2 fs1 fs0 default 0 0 0 1 1 1 1 1 fs3-0: sampling frequency select (see table 5 and table 6) and mcki frequency select (see table 11) default: ?1111? (44.1khz) fs3-0 bits select sampling frequency at pll mode and mcki frequency at ext mode. bcko1-0: bclk output frequency select at master mode (see table 10) default: ?01? (32fs) hpf1-0: offset cancel hpf cut-off frequency and adc initialization cycle (see table 17, table 30) default: ?00? (fc=3.4hz@fs= 44.1khz, init cycle=3088/fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 16h clock output select 0 0 0 0 thr mcko ps1 ps0 default 0 0 0 0 0 0 0 0 ps1-0: mcko output frequency select (see table 9) default: ?00?(256fs) mcko: master clock output enable 0: disable: mcko pin = ?l? (default) 1: enable: output frequency is selected by ps1-0 bits. thr: bypass mode (table 14) 0: off (default) 1: on addr register name d7 d6 d5 d4 d3 d2 d1 d0 18h input volume control ivl7 ivl6 ivl5 ivl4 ivl3 ivl2 ivl1 ivl0 default 1 0 0 1 0 0 0 1 ivl7-0: input digital volume; 0.375db step, 242 level (see table 29) default: ?91h? (0db)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 44 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ah timer select 0 0 0 0 ztm1 ztm0 wtm1 wtm0 default 0 0 0 0 0 0 0 0 wtm1-0: alc recovery waiting period (see table 25) default: ?00? (128/fs) ztm1-0: alc limiter/recovery operation zero crossing timeout period (see table 24) default: ?00? (128/fs) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1bh alc mode control 1 ref7 ref6 ref5 ref4 ref3 ref2 ref1 ref0 default 1 1 1 0 0 0 0 1 ref7-0: reference value at alc recovery operation. 0.375db step, 242 level (see table 27) default: ?e1h? (+30.0db) addr register name d7 d6 d5 d4 d3 d2 d1 d0 1ch alc mode control 2 alc zelmn lmat1 lmat0 rgain1 rgain0 lmth1 lmth0 default 0 0 0 0 0 0 0 0 lmth1-0: alc limiter detection level / recovery counter reset level (see table 22) default: ?00? rgain1-0: alc recovery gain step (see table 26) default: ?00? lmat1-0: alc limiter a tt step (see table 23) default: ?00? zelmn: zero cro ssing detection enable at alc limiter operation 0: enable (default) 1: disable alc: alc enable 0: alc disable (default) 1: alc enable
asahi kasei [AK5700] ms0569-e-01 2006/12 - 45 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 1dh mode control 1 te3 te2 te1 te0 0 0 0 0 default 1 0 1 0 0 0 0 0 te3-0: ext master mode enable when te3-0 bits is set to ?0101?, the write operation to addr=1eh is enabled. te3-0 bits should be set to ?1010? except for ext master mode. te3-0 bits must not be set to the value except for ?1010? and ?0101?. default: ?1010? addr register name d7 d6 d5 d4 d3 d2 d1 d0 1eh mode control 2 0 0 0 0 0 0 tmaster 0 default 0 0 0 0 0 0 0 0 tmaster: ext master mode the write operation to tmaster bit is enabled when te3-0 bits = ?0101?. 0: except ext master mode (default) 1: ext master mode
asahi kasei [AK5700] ms0569-e-01 2006/12 - 46 - system design figure 39 and figure 40 shows the system connection diagram for the AK5700. an evaluation board [akd5700] is available which demonstrates the optimum layout, power supply arrangements and measurement results. mpwr test a in2 a in ? a in1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck a k5700vn top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 2.2k 2.2k external mic internal mic 0.1u 2.2u 0.1u power supply 2.4 3.6v dsp p rp analog ground digital ground 0.1u 10u 10u power supply 1.6 3.6v cp 0.1 x cp (note) dsp 1u 1u notes: - avss and dvss of the AK5700 should be distributed separately from the ground of external controllers. - all digital input pins should not be left floating. - when the AK5700 is ext mode (pmpll bit = ?0?), a resistor and capacitor of vcoc pin is not needed. - when the AK5700 is pll mode (pmpll bit = ?1?), a resistor and capacitor of vcoc pin is shown in table 4. 0.1 x cp in parallel with cp+rp improves pll jitter characteristics. - mic input ac coupling capacitor should be 1 f or less to start the recording within 100ms. figure 39. typical connection diagram (mic input)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 47 - mpwr test a in2 a in a in1 vcoc pdn csn cclk cdti mcki exbclk vcom avss avdd dvdd dvss bclk exlrck exsdti mcko csp sdto lrck a k5700vn top view 19 20 21 22 23 24 18 17 16 1 12 11 10 9 8 7 15 14 13 2 3 4 5 6 line in 0.1u 2.2u 0.1u power supply 2.4 3.6v dsp p rp analog ground digital ground 0.1u 10u 10u power supply 1.6 3.6v cp 0.1 x cp (note) dsp notes: - avss and dvss of the AK5700 should be distributed separately from the ground of external controllers. - all digital input pins should not be left floating. - when the AK5700 is ext mode (pmpll bit = ?0?), a resistor and capacitor of vcoc pin is not needed. - when the AK5700 is pll mode (pmpll bit = ?1?), a resistor and capacitor of vcoc pin is shown in table 4. 0.1 x cp in parallel with cp+rp improves pll jitter characteristics. figure 40. typical connection diagram (line input)
asahi kasei [AK5700] ms0569-e-01 2006/12 - 48 - 1. grounding and power supply decoupling the AK5700 requires careful attention to power supply and grounding arrangements. avdd and dvdd are usually supplied from the system?s analog supply. if avdd and dvdd are supplied separately, the power-up sequence is not critical. avss and dvss of the AK5700 should be connected to the analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the AK5700 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference vcom is a signal ground of this chip. a 2.2 f electrolytic capacitor in parallel with a 0.1 f ceramic capacitor attached to the vcom pin eliminates the effects of high frequency noise. no load current may be drawn from the vcom pin. all signals, especially clocks, should be kept away from the vcom pin in order to avoid unwanted coupling into the AK5700. 3. analog inputs the analog inputs are single-ended or full-differential and input resistance is 60k (typ)@mgain1-0 bits = ?00?, 30k (typ)@mgain1-0 bits = ?01? or ?10?. the input signal range scales with 0.6 x avdd vpp(typ)@mgain 1-0 bits = ?00? centered around the internal common voltage (0.5 x avdd). usually the input signal is ac coupled using a capacitor. the cut-off frequency is fc = (1/2 rc). the adc output data format is 2?s complement. the dc offset including the adc?s own dc offset is removed by the internal hpf (fc=3.4hz@ hpf1-0 bits = ?00?, fs=44.1khz). the AK5700 can accept input voltages from avss to avdd at single-ended.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 49 - control sequence ? clock set up when adc is powered-up, the clocks must be supplied. 1. pll master mode. bclk pin lrck pin mcko bit (addr:16h, d2) pmpll bit (addr:11h, d0) 40msec(max) output (1) (6) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin (5) (4) input m/s bit (addr:11h, d1) mcko pin output (8) (7) 40msec(max) example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:10h, data:04h (2)addr:11h, data:12h addr:14h, data:23h addr:15h, data:2fh (4)addr:16h, data:04h addr:11h, data:13h mcko, bclk and lrck output figure 41. clock set up sequence (1) (1) after power up, pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) dif1-0, pll3-0, fs3-0, bcko1-0 and m/s bits should be set during this period as follows. (2a) m/s bit = ?1? and setting of pll3-0, fs3-0, bcko1-0 bits. (2b) setting of dif1-0 bits. (3) power upvcom: pmvcm bit = ?0? ? ?1? vcom should first be powered-up before the other block operates. (4) in case of using mcko output: mcko bit = ?1? in case of not using mcko output: mcko bit = ?0? (5) pll operation starts after pmpll bit changes from ?0? to ?1? and mcki is supplied from an external source. pll lock time is 40ms(max) at mcki=12mhz (table 4). (6) the AK5700 starts to output the lrck and bclk clocks after the pll becomes stable. then normal operation starts. (7) the invalid frequency is output from mcko pin during this period if mcko bit = ?1?. (8) the normal clock is output from mcko pin after the pll is locked if mcko bit = ?1?.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 50 - 2. pll slave mode (exlrck or exbclk pin) pmpll bit (addr:11h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) (5) input 4fs of example: audio i/f format : i2s pll reference clock: exbclk exbclk frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:10h, data:04h (2) addr:11h, data:0ch addr:14h, data:23h addr:15h, data:2fh (4) addr:11h, data:0dh figure 42. clock set up sequence (2) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) dif1-0, fs3-0 and pll3-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up before the other block operates. (4) pll starts after the pmpll bit changes from ?0? to ?1? and pll reference clock (exlrck or exbclk pin) is supplied. pll lock time is 160ms(max) when exlrck is a pll reference clock. pll lock time is 2ms(max) when exbclk is a pll reference clock and the external circuit at vcoc pin is 10k+4.7nf (table 4). (5) normal operation stats after that the pll is locked.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 51 - 3. pll slave mode (mcki pin) exbclk pin exlrck pin mcko bit (addr:16h, d2) pmpll bit (addr:11h, d0) (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin (5) (4) input mcko pin output (6) (7) 40msec(max) (8) input example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz mcko: enable sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:10h, data:04h (2)addr:11h, data:10h addr:14h, data:23h addr:15h, data:2fh (4)addr:16h, data:04h addr:11h, data:11h mcko output start exbclk and exlrck input start figure 43. clock set up sequence (3) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) dif1-0, pll3-0, fs3-0, bcko1-0 and m/s bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up before the other block operates. (4) enable mcko output: mcko bit = ?1? (5) pll starts after that the pmpll bit changes from ?0? to ?1? and pll reference clock (mcki pin) is supplied. pll lock time is 40ms(max) at mcki=12mhz (table 4). (6) the normal clock is output from mcko after pll is locked. (7) the invalid frequency is output from mcko during this period. (8) exbclk and exlrck clocks should be synchronized with mcko clock.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 52 - 4. ext slave mode (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) input (4) mcki pin input example: audio i/f format: i2s input mcki frequency: 256fs sampling frequency: 44.1khz mcko: disable (1) power supply & pdn pin = ?l? ? ?h? (3) addr:10h, data:04h (2) addr:11h, data:00h addr:14h, data:23h addr:15h, data:2fh mcki, exbclk and exlrck input figure 44. clock set up sequence (4) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) dif1-0 and fs1-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up before the other block operates. (4) normal operation starts after the mcki, exlrck and exbclk are supplied.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 53 - 5. ext master mode te3-0 bits (addr:1dh, d7-4) "0101" (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) mcki pin input m/s bit (addr:11h, d1) bclk pin lrck pin output tmaster bit (addr:1eh, d1) "1010" example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select: 256fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3)addr:10h, data:04h (2)addr:11h, data:26h addr:14h, data:23h addr:15h, data:2fh addr:1dh, data:50h addr:1eh, data:02h bclk and lrck output figure 45. clock set up sequence (5) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) dif1-0, fs1-0, bcko1-0, m/s, te3-0 and tmaster bits should be set during this period as follows. (2a) m/s bit = ?1?, setting of fs3-0 and bcko1-0 bits. (2b) setting of dif1-0 bits. (2c) te3-0 bits = ?0101? (2d) tmaster bit = ?1?: bclk and lrck start to output. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up before the other block operates. when the clock mode is changed from ext master mode to other modes, the register should be set as above table after pdn pin = ?l? to ?h? or te3-0 bits = ?1010?.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 54 - 6. slave & bypass mode pmpll bit (addr:11h, d0) internal clock (1) power supply pdn pin pmvcm bit (addr:10h, d2) (2) (3) exlrck pin exbclk pin (4) (5) input 4fs of example: audio i/f format : i2s pll reference clock: exbclk exbclk frequency: 64fs sampling frequency: 44.1khz (1) power supply & pdn pin = ?l? ? ?h? (3) addr:10h, data:04h (2) addr:11h, data:0ch addr:14h, data:23h addr:15h, data:2fh addr:16h, data:08h (4) addr:11h, data:0dh figure 46. clock set up sequence (6) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) thr bit should be set to ?1? and dif1-0, fs3-0 and pll3-0 bits should be set during this period. (3) power up vcom: pmvcm bit = ?0? ? ?1? vcom should first be powered up before the other block operates. (4) pll starts after the pmpll bit changes from ?0? to ?1? and pll reference clock (exlrck or exbclk pin) is supplied. pll lock time is 160ms(max) when exlrck is a pll reference clock. pll lock time is 2ms(max) when exbclk is a pll reference clock and the external circuit at vcoc pin is 10k+4.7nf (table 4). (5) normal operation stats after that the pll is locked.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 55 - 7. bypass mode (1) power supply pdn pin thr bit (addr:16h, d3) (2) exlrck pin exbclk pin exsdti pin (3) input (1) power supply & pdn pin = ?l? ? ?h? (2) addr:16h, data:08h mcki, exbclk and exlrck input figure 47. clock set up sequence (7) (1) after power up: pdn pin ?l? ? ?h? ?l? time of 150ns or more is needed to reset the AK5700. (2) thr bit should be set to ?1?. (3) after exlrck, exbclk and exsdti are input, lrck, bclk and sdto start to output.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 56 - ? mic input recording fs3-0 bits (addr:15h, d3-0) mic control (addr:12h, d4 & addr:13h, d1-0) pmadc bit (addr:10h, d0) adc internal state 1111 x,xxx 0, 01 1, 01 power down initialize normal state power down 3088 / fs (1) (2) (6) alc state alc enable alc disable alc disable timer control (addr:1ah) xxh 0ah (3) alc control 1 (addr:1bh) xxh e1h (4) (7) (5) alc control 2 (addr:1ch) xxh 81h 01h (8) example: pll master mode audio i/f format:i2s sampling frequency:44.1khz pre mic amp:+15db mic power on alc setting:refer to figrure 37 alc bit = ?1? (2) addr:12h, data:10h addr:13h, data:01h (3) addr:1ah, data:0ah (1) addr:15h, data:2fh (4) addr:1bh, data:e1h (6) addr:10h, data:05h recording (7) addr:10h, data:04h (5) addr:1ch, data:81h (8) addr:1ch, data:01h figure 48. mic input recording sequence this sequence is an example of alc setting at fs=44.1khz. if the parameter of the alc is changed, please refer to ?figure 35. registers set-up sequence at alc operation?. at first, clocks should be supplied according to ?clock set up? sequence. (1) set up a sampling frequency (fs3-0 bit). when the AK5700 is pll mode, mic and adc should be powered-up in consideration of pll lock time after a sampling frequency is changed. (2) set up mic input (addr: 12h&13h) (3) set up timer select for alc (addr: 1ah) (4) set up ref value for alc (addr: 1bh) (5) set up lmth1-0, rgain1-0, lmat1-0 and alc bits (addr: 1ch) (6) power up mic and adc: pmadc bit = ?0? ?1? the initialization cycle time of adc is 3088/fs=70.0ms@fs=44.1khz, hpf1-0 bits = ?00?. after the alc bit is set to ?1? and mic&adc block is powered-up, the alc ope ration starts from ivol default value (0db). to start the recording within 100ms, the following sequence is required. (6a) pmvcm=pmmp bits = ?1?. (6b) wait for 2ms, then pmpll bit = ?1?. (6c) wait for 6ms, then pmadc bit = ?1?. (7) power down mic and adc: pmadc bit = ?1? ?0? when the registers for the alc operation are not changed, alc bit may be keeping ?1?. the alc operation is disabled because the mic&adc block is powered-down. if the registers for the alc operation are also changed when the sampling frequency is changed, it should be done after the AK5700 goes to the manual mode (alc bit = ?0?) or mic&adc block is powered-down (pmadc bit = ?0?). ivol gain is not reset when pmadc = ?0?, and then ivol operation starts from the setting value when pmadc bit is changed to ?1?. (8) alc disable: alc bit = ?1? ?0?
asahi kasei [AK5700] ms0569-e-01 2006/12 - 57 - ? stop of clock master clock can be stopped when adc is not used. 1. pll master mode external mcki pmpll bit (addr:11h, d0) mcko bit (addr:16h, d2) input (3) (1) (2) "h" or "l" m/s bit (addr:11h, d1) example: audio i/f format: i2s bclk frequency at master mode: 64fs input master clock select at pll mode: 11.2896mhz sampling frequency: 44.1khz (2) addr:16h, data:00h (1) addr:11h, data:10h (3) stop an external mcki figure 49. clock stopping sequence (1) (1) power down pll: pmpll=m/s bits = ?1? ?0? (2) stop mcko clock: mcko bit = ?1? ?0? (3) stop an external master clock. 2. pll slave mode (exlrck, exbclk pin) exbclk pmpll bit (addr:11h, d0) input (1) (2) exlrck input (2) example audio i/f format : i2s pll reference clock: exbclk bclk frequency: 64fs sampling frequency: 44.1khz (1) addr:11h, data:0ch (2) stop the external clocks figure 50. clock stopping sequence (2) (1) power down pll: pmpll bit = ?1? ?0? (2) stop the external exbclk and exlrck clocks * clock stop sequence is the same for slave&bypass mode.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 58 - 3. pll slave mode (mcki pin) external mcki pmpll bit (addr:11h, d0) input (1) (3) mcko bit (addr:16h, d2) (2) example audio i/f format: i2s pll reference clock: mcki exbclk frequency: 64fs sampling frequency: 44.1khz (1) addr:11h, data:10h (3) stop the external clocks (2) addr:16h, data:00h figure 51. clock stopping sequence (3) (1) power down pll: pmpll bit = ?1? ?0? (2) stop mcko output: mcko bit = ?1? ?0? (3) stop the external master clock. 4. ext slave mode exlrck input (1) exbclk input (1) external mcki input (1) example audio i/f format :i2s input mcki frequency:256fs sampling frequency:44.1khz (1) stop the external clocks figure 52. clock stopping sequence (4) (1) stop the external mcki, exbclk and exlrck clocks. * clock stop sequence is the same for bypass mode. 5. ext master mode lrck output bclk output external mcki input (1) "h" or "l" "h" or "l" example audio i/f format :i2s input mcki frequency:256fs sampling frequency:44.1khz (1) stop mcki figure 53. clock stopping sequence (5) (1) stop mcki. bclk and lrck are fixed to ?h? or ?l?.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 59 - ? power down power supply current is typ. 20 a by stopping clocks and setting pmvcm bit = ?0? after all blocks except for vcom are powered-down. power supply current can be shut down (typ. 1 a) by stopping clocks and setting pdn pin = ?l?. when pdn pin = ?l?, the registers are initialized.
asahi kasei [AK5700] ms0569-e-01 2006/12 - 60 - package 24pin qfn (unit: mm) 2.4 0.15 0.5 0.23 0.05 0.2 0.75 0.05 2.4 0.15 1 7 12 19 4.0 0.1 4.0 0.1 0.40 0.1 a b 0.10 m 0.08 6 24 13 18 pin #1 id (0.35 x 45 ) exposed pad note) the exposed pad on the bottom surface of the package must be open or connected to the ground. ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK5700] ms0569-e-01 2006/12 - 61 - marking 5700 x xxx 1 xxxx : date code identifier (4 digits) revision history date (yy/mm/dd) revision reason page contents 06/11/16 00 first edition 06/12/25 01 error correct 40 register map (addr=17h) bit (d0) value was changed: 0 1 important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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