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m1025/26 datasheet rev 1.0 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch integrated circuit systems, inc. product data sheet g eneral d escription the m1025/26 is a vcso (voltage controlled saw oscillator) based clock jitter attenuator pll designed for clock jitter attenuation and frequency translation. the device is ideal for generating the transmit reference clock for optical network systems supporting up to 2.5gb data rates. it can serve to jitter attenuate a stratum reference clock or a recovered clock in loop timing mode. the m1025/26 module includes a proprietary saw (surface acoustic wave) delay line as part of the vcso. this results in a high frequency, high-q, low phase noise os cillator that assures low intrinsic output jitter. f eatures integrated saw delay line; low phase jitter of < 0.5ps rms, typical (12khz to 20mhz) output frequencies of 62.5 to 175 mhz (specify vcso output frequency at time of order) lvpecl clock output (cml and lvds options available) reference clock inputs support differential lvds, lvpecl, as well as single -ended lvcmos, lvttl loss of lock ( lol ) output pin; narrow bandwidth control input ( nbw pin) autoswitch ( auto pin) - automati c (non-revertive) reference clock reselection upon clock failure acknowledge pin ( ref_ack pin) indicates the actively selected reference input hitless switching (hs) options with or without phase build-out (pbo) to enable sonet (gr-253) /sdh (g.813) mtie and tdev comp liance during reselection pin-selectable feedback and reference divider ratios single 3.3v power supply small 9 x 9 mm smt (surface mount) package p in a ssignment (9 x 9 mm smt) figure 1: pin assignment s implified b lock d iagram figure 2: simplified block diagram example i/o clock frequency combinations using m1025-11-155.5200 or m1026-11-155.5200 input reference clock (mhz) pll ratio (pin selectable) output clock (mhz) (pin selectable) (m1025) (m1026) 19.44 or 38.88 (m1025) (m1026) 8 or 4 155.52 or 77.76 77.76 2 155.52 1 622.08 0.25 table 1: example i/o clock frequency combinations m1025 m1026 (top view) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 mr_sel3 gnd nc dif_ref0 ndif_ref0 ref_sel dif_ref1 ndif_ref1 vcc p_sel0 p_sel1 nfout fout gnd ref_ack auto vcc gnd mr_sel2 mr_sel0 mr_sel1 lol nbw vcc dnc dnc dnc nop_in op_out vc nvc nop_out op_in gnd gnd gnd 19 20 21 22 23 24 25 26 27 fout nfout tristate loop filter pll phase detector r div mux 0 ref_sel dif_ref0 ndif_ref0 1 p_sel1:0 nbw dif_ref1 ndif_ref1 auto ref sel 0 1 lol phase detector ref_ack auto m1025/26 vcso p divider lut lol 2 m divider 4 m/r divider lut mr_sel3:0 p divider (1, 2, or tristate) m1025/26 vcso based clock pll with autoswitch
m1025/26 datasheet rev 1.0 2 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet p in d escriptions number name i/o configuration description 1, 2, 3, 10, 14, 26 gnd ground power supply ground connections. 4 9 op_in nop_in input external loop filter connections. see figure 5, external loop filter, on pg. 9. 5 8 nop_out op_out output 6 7 nvc vc input 11, 19, 33 vcc power power supply connection, connect to + 3.3 v. 12 auto input internal pull-down resistor 1 automatic/manual reselection mode for clock input: logic 1 automatic reselection upon clock failure (non-revertive) logic 0 manual selection only (using ref_sel ) 13 ref_ack output reference acknowledgement pin for input mux state; outputs the currently selected reference input pair: logic 1 indicates ndif_ref1, dif_ref1 logic 0 indicates ndif_ref0, dif_ref0 15 16 fout nfout output no internal terminator clock output pair. differential lvpecl (cml, lvds available). 17 18 p_sel1 p_sel0 internal pull-down resistor 1 note 1: for typical values of internal pull-down and pull-up resistors, see dc characteristics on pg. 11. post-pll , p divider selection. lvcmos/lvttl. see table 5, p divider look-up table (lut), on pg. 4. 20 ndif_ref1 input biased to vcc/2 2 note 2: biased tovcc/2, with 50k ? to vcc and 50k ? to ground. see differential inputs biased to vcc/2 on pg. 11. reference clock input pair 1. differential lvpecl or lvds. resistor bias on inverting terminal supports ttl or lvcmos. 21 dif_ref1 internal pull-down resistor 1 22 ref_sel input internal pull-down resistor 1 referenc e clock input selection. lvcmos/lvttl: logic 1 selects dif_ref1, ndif_ref1. logic 0 selects dif_ref0, ndif_ref0 . 23 ndif_ref0 input biased to vcc/2 2 reference clock input pair 0. differential lvpecl or lvds. resistor bias on inverting terminal supports ttl or lvcmos. 24 dif_ref0 internal pull-down resistor 1 25 nc no internal connection. 27 28 29 30 mr_sel3 mr_sel2 mr_sel0 mr_sel1 input internal pull-down resistor 1 m and r divider value selection. lvcmos/ lvttl. see tables 3 and 4, m and r divider look-up tables (lut) on pg. 3. 31 lol output loss of lock indicator output. asserted when internal pll is not tracking the input reference for frequency and phase. 3 logic 1 indicates loss of lock. logic 0 indicates locked condition. note 3: see lv c m o s o u t p u t in dc characteristics on pg. 11. 32 nbw input internal pull-up resistor 1 narrow bandwidth enable. lvcmos/lvttl: logic 1 - narrow loop bandwidth , r in = 2100k ? . logic 0 - wide bandwidth , r in = 100k ? . 34, 35, 36 dnc do not connect. table 2: pin descriptions
m1025/26 datasheet rev 1.0 3 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch product data sheet integrated circuit systems, inc. d etailed b lock d iagram figure 3: detailed block diagram d ivider s election t ables m and r divider look-up tables (lut) the mr_sel3:0 pins select the feedback and reference divider values m and r to enable adjustment of loop bandwidth and jitter tolerance. the look-up tables vary by device variant. m1025 and m1026 are defined in ta b l e s 3 and 4 respectively . m1025 m/r divider lut ables 3 and 4 provide example fin and phase detector frequencies with 155.52mhz vcso devices ( m1025-11-155.5200 and m1026-11-155.5200 ). see ?ordering information? on pg. 14 . m1026 m/r divider lut phase locked loop (pll) m1025/26 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in pll phase detector loop filter amplifier external loop filter components mr_sel3:0 r div mux 0 ref_sel dif_ref0 ndif_ref0 1 m divider nbw r in r in m / r divider lut dif_ref1 ndif_ref1 auto ref sel 0 1 lol phase detector ref_ack auto lol fout nfout p_sel1:0 p divider lut p divider (1, 2, or tristate) 4 2 tristate hitless switching (hs) opt. hs with phase build-out opt. mr_sel3:0 m div r div total pll ratio fin for 155.52mhz vcso (mhz) phase det. freq. for 155.52mhz vcso (mhz) 0 0 0 0 8 1 8 19.44 19.44 0 0 0 1 32 4 8 19.44 4.86 0 0 1 0 128 16 8 19.44 1.215 0 0 1 1 512 64 8 19.44 0.30375 0 1 0 0 2 1 2 77.76 77.76 0 1 0 1 8 4 2 77.76 19.44 0 1 1 0 32 16 2 77.76 4.86 0 1 1 1 128 64 2 77.76 1.215 1 0 0 0 1 1 1 155.52 155.52 1 0 0 1 4 4 1 155.52 38.88 1 0 1 0 16 16 1 155.52 9.72 1 0 1 1 64 64 1 155.52 2.43 1 1 0 0 test mode 1 note 1: factory test mode; do not use. n/a n/a n/a 1 1 0 1 1 4 0.25 622.08 155.52 1 1 1 0 4 16 0.25 622.08 38.88 1 1 1 1 16 64 0.25 622.08 9.72 table 3: m1025 m/r divider lut mr_sel3:0 m div r div total pll ratio fin for 155.52mhz vcso (mhz) phase det. freq. for 155.52mhz vcso (mhz) 0 0 0 0 4 1 4 38.88 38.88 0 0 0 1 16 4 4 38.88 9.72 0 0 1 0 64 16 4 38.88 2.43 0 0 1 1 256 64 4 38.88 0.6075 0 1 0 0 2 1 2 77.76 77.76 0 1 0 1 8 4 2 77.76 19.44 0 1 1 0 32 16 2 77.76 4.86 0 1 1 1 128 64 2 77.76 1.215 1 0 0 0 1 1 1 155.52 155.52 1 0 0 1 4 4 1 155.52 38.88 1 0 1 0 16 16 1 155.52 9.72 1 0 1 1 64 64 1 155.52 2.43 1 1 0 0 test mode 1 note 1: factory test mode; do not use. n/a n/a n/a 1 1 0 1 1 4 0.25 622.08 155.52 1 1 1 0 4 16 0.25 622.08 38.88 1 1 1 1 16 64 0.25 622.08 9.72 table 4: m1026 m/r divider lut
m1025/26 datasheet rev 1.0 4 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet general guidelines for m and r divider selection general guidelines for m/ r divider selection (see following pages for more detail): ? a lower phase detector frequency should be used for loop timing applications to assure pll tracking, especially during gr-253 jitter tolerance testing. the recommended maximum phase detector frequency for loop timing mode is 19.44mhz . the lol pin should not be used during loop timing mode. ? when lol is to be used for system health monitoring, the phase detector frequency should be 5mhz or greater. low phase detector frequencies make lol overly sensitive, and higher phase detector frequencies make lol less sensitive. ? the preceding guideline also applies when using the autoswitch mode, since autoswitch uses the lol output for clock fault detection. p divider look-up table (lut) the p_sel1 and p_sel0 pins select the post-pll divider value p. the output frequency of the saw can be divided by 1 or 2 or the output can be tristated as specified in ta b l e 5 . f unctional d escription the m1025/26 is a pll (phase locked loop) based clock generator that generates an output clock synchro- nized to one of two selectable input reference clocks. an internal high "q" saw delay line provides low jitter signal performance. a pin-selected look-up table is used to select the pll feedback divider (m div) and reference divider (r div) as shown in ta bl e s 3 and 4 on pg. 3 . these look-up tables provide flexibility in both the over all frequency multiplication ratio (total pll ratio) and phase detector frequency. the m1025/26 includes a loss of lock ( lol ) indicator, which provides status information to system management software. a narrow bandwidth ( nbw ) control pin is provided as an additional mechanism for adjusting pll loop bandwidth without affecting the phase detector frequency. an automatic input reselection feature, or ?autoswitch? is also included in the m1025/26. when the autoswitch mode is enabled, the device will automatically switch to the other reference clock input when the currently selected reference clock fails. reference selection is non-revertive, meaning that only one reference reselection will be made each time that autoswitch is re-enabled. in addition to the autoswitch feature, hitless switching and phase build-out options can be ordered with the device. the hitless switching and phase build-out options help assure sonet/sdh mtie and tdev compliance during either a manual or automatic input reference reselection. p_sel1:0 p value m1025-155.5200 or m1026-155.5200 output frequency (mhz) 0 0 2 77.76 0 1 1 155.52 1 0 2 77.76 1 1 tristate n/a table 5: p divider look-up table (lut)
m1025/26 datasheet rev 1.0 5 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch product data sheet integrated circuit systems, inc. input reference clocks two clock reference inputs and a selection mux are provided. either reference clock input can accept a differential clock signal (s uch as lvpecl or lvds) or a single-ended clock input (lvcmos or lvttl on the non-inverting input). a single-ended reference clock on the unselected reference input can cause an increase in output clock jitter. for this reason, differential reference inputs are preferred; interference from a differential input on the non-selected input is minimal. implementation of single-ended input has been facilitated by biasing ndif_ref0 and ndef_ref1 to vcc/2, with 50k ? to vcc and 50k ? to ground. figure 4 shows the input clock structure and how it is used with either lvcmos / lvttl inputs or a dc- coupled lvpecl clock. figure 4: input reference clocks differential lvpecl inputs differential lvpecl inputs are connected to both reference input pins in the usual manner. the external load termination resistors shown in figure 4 (the 127 ? and 82 ? resistors) will work for both ac and dc coupled lvpecl reference cl ock lines. these provide the 50 ? load termination and the vtt bias voltage. single-ended inputs single-ended inputs (lvcmos or lvttl) are connected to the non-inverting reference input pin ( dif_ref0 or dif_ref1 ). the inverting reference input pin ( ndif_ref0 or ndif_ref1 ) must be left unconnected. in single-ended operation, when the unused inverting input pin ( ndif_ref0 or ndef_ref1 ) is left floating (not connected), the input will self-bias at vcc/2. pll operation the m1025/26 is a complete clock pll. it uses a phase detector and configurable dividers to synchronize the output of the vcso with the selected reference clock. the ?m? divider divides the vcso output frequency, feeding the result into the plus input of the phase detector. the output of the ?r? divider is fed into the minus input of the phase detector. the phase detector compares its two inputs. the phase detector output, filtered externally, causes the vcso to increase or decrease in speed as needed to phase- and frequency-lock the vcso to the reference input. the value of the m divider directly affects closed loop bandwidth. the relationship between the nominal vcso center frequency (fvcso), the m divider, the r divider, and the input reference frequency (fin) is: for the available m divider and r divider look-up table combinations, ta b l e s 3 and 4 on pg. 3 list the total pll ratio as well as fin when using the m1025-11-155.5200 or the m1026-11-155.5200 . (?ordering information?, pg. 14 . ) due to the narrow tuning range of the vcso (+ 200ppm), appropriate selection of all of the following are required for the pll be able to lock: vcso center frequency, input frequency, and divider selections. post-pll divider the m1025/26 features a post-pll (p) divider. by using the p divider, the device?s output frequency (fout) can be the vcso center frequency (fvcso) or 1/2 fvcso. the p_sel pin selects the value for the p divider: logic 1 sets p to 2, logic 0 sets p to 1 . (see table 5 on pg. 4.) when the p divider is included, the complete relation- ship for the output frequency (fout) is defined as: due to the narrow tuning range of the vcso (+ 200ppm), appropriate selection of all of the following are required for the pll be able to lock: vcso center frequency, input frequency, and divider selections. mux 0 ref_sel 1 vcc 50k 50k vcc 50k 50k lvcmos/ lvttl lvpecl 50k 50k vcc 82 127 vcc 82 127 m1025/26 x dif_ref0 ndif_ref0 dif_ref1 ndif_ref1 ? ? ? ? ? ? ? ? ? ? fvcso fin m r ---- = fout fvcso p ------------------- = fin m rp ----------------- - =
m1025/26 datasheet rev 1.0 6 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet tristate the tristate feature puts th e lvpecl output driver into a high impedance state, effectively disconnecting the driver from the fout and nfout pins of the device. a logic 0 is then present on the clock net. the impedance of the clock net is then set to 50 ? by the external circuit resistors. (this is in distinction to a cmos output in tristate, in which case the net goes to a high impedance and the logic value floats.) the 50 ? impedance level of the lvpecl tristate allows manufacturing in-circuit test to drive the clock net with an external 50 ? generator to validate the integrity of clock net and the clock load. any unused output (single-ended or differential) should be left unconnected (floati ng) in system application. this minimizes output switching current and therefore minimizes noise modulation of the vcso. loss of lock indicator ( lol ) output pin under normal device operation, when the pll is locked, the lol phase detector drives lol to logic 0 . under circumstances when the vcso cannot lock to the input (as measured by a greater than 4 ns discrepancy between the feedback and reference clock rising edges at the lol phase detector) the lol output goes to logic 1. the lol pin will return back to logic 0 when the phase detector error is less than 2 ns. the loss of lock indicator is a low current lvcmos output. guidelines using lol as described, the lol pin indicates when the pll is out-of-lock with the input reference. the lol condition is also used by the autoswitch circuit to detect a lost reference, as described in following sections. lol is also used by the hitless switching and phase build-out functions (optional device features). to ensure reliable operation of lol and guard against false out-of-lock indications, the following conditions should be met: ? the phase detector frequency should be no less than 5mhz , and preferably it should be 10mhz or greater. phase detector frequency is defined by fin / r. a higher phase detector freq uency will result in lower phase error and less chance of false triggering the lol phase detector. refer to tables 3 and 4 on pg. 3 for phase detector frequency when using the m1025-11-155.5200 or the m1026-11-155.5200 . ? the input reference should have an intrinsic jitter of less than 1 ns pk-pk. if reference jitter is greater than 1 ns pk-pk, the lol circuit might falsely trigger. due to this limitation, the lol circuit should not be used in loop timing mode, nor should it be used with a noisy reference clock. likewise, the autoswitch, hitless switching, or phase build-out features should not be used in loop timing mode or with a noisy reference clock, since these features depend on lol . reference acknowledgement ( ref_ack ) output the ref_ack (reference acknowledgement) pin outputs the value of the reference clock input that is routed to the phase detector. logic 1 indicates input pair 1 ( ndif_ref1, dif_ref1 ); l ogic 0 indicates input pair 0 ( ndif_ref0, dif_ref0 ) . the ref_ack indicator is an lvcmos output.
m1025/26 datasheet rev 1.0 7 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch product data sheet integrated circuit systems, inc. autoswitch ( auto ) reference clock reselection this device offers an automatic reference clock reselection feature for switching input reference clocks upon a reference clock failure. with the auto input pin set to high and the lol output low, the device is placed into automatic reselection (autoswitch) mode. once in autoswitch mode, when lol then goes high (due to a reference clock fault), the input clock reference is automatically reselected inte rnally, as indicated by the state change of the ref_ack output. automatic clock reselection is made only on ce (it is non-revertive). re-arming of automatic mode requires placing the device into manual select ion (manual select) mode ( auto pin low) before returning to autoswitch mode ( auto pin high). using the autoswitch feature see alsotable 6, example autoswitch sequence. in application, the system is powered up with the device in manual select mode ( auto pin is set low), allowing sufficient time for the reference clock and device pll to settle. the ref_sel input selects the reference clock to be used in manual select mode and the initial reference clock used in autoswitch mode. the ref_sel input state must be maintained when s witching to autoswitch mode ( auto pin high) and must still be maintained until a reference fault occurs. once a reference fault occurs, the lol output goes high and the input reference is automatically reselected. the ref_ack output always indicates the reference selection status and the lol output always indicates the pll lock status. a successful automatic reselection is indicated by a change of state of the ref_ack output and a momentary level high of the lol output (minimum high time is 10 ns). if an automatic reselectio n is made to a non-valid reference clock (one to which the pll cannot lock), the ref_ack output will change state but the lol output will remain high. no further automatic reselection is made; only one reselection is made each time the autoswitch mode is armed. autoswitch mode is re-armed by placing the device into manual select mode ( auto pin low) and then into autoswitch mode again ( auto pin high). following an automatic reselection and prior to selecting manual select mode ( auto pin low) , the ref_sel pin has no control of reference selection. to prevent an unintential reference reselection, autoswitch mode must not be re-enabled until the desired state of the ref_sel pin is set and the lol output is low. it is recommended to delay the re-arming of autoswitch mode, following an aut omatic reselection, to ensure the pll is fully locked on the new reference. in most system configurations, where loop bandwidth is in the range of 100-1000 hz and damping factor below 10, a delay of 500 ms should be sufficient. until the pll is fully locked intermitte nt lol pulses may occur. example autoswitch sequence 0 = low; 1 = high. example with ref_sel initially set to 0 ( i.e., dif_ref0 selected) ref_sel selected clock input ref_ack auto lol conditions input output input output initialization 0 dif_ref0 0 0 1 device power-up. manual select mode . dif_ref0 input selected reference, not yet locked to. 0 dif_ref0 0 0 - 0 - lol to 0 : device locked to reference (may get intermittent lol pulses until fully locked). 0 dif_ref0 0 - 1 - 0 auto set to 1 : device placed in autoswitch mode ( with dif_ref0 as initial reference clock). operation & activation 0 dif_ref0 0 1 0 normal operation with autoswitch mode armed , with dif_ref0 as initial reference clock. 0 dif_ref0 0 1 - 1 - lol to 1 : clock fault on dif_ref0 , loss of lock indicated by lol pin, ... 0 -dif_ref1- - 1 - 1 1 ... and immediate automatic reselection to dif_ref1 ( indicated by ref_ack pin ) . 0 dif_ref1 1 1 - 0 - lol to 0 : device locks to dif_ref1 (assuming valid clock on dif_ref1). re-initialization - 1 - dif_ref1 1 1 0 ref_sel set to 1 : p repares for manual selection of dif_ref1 before then re-arming autoswitch. 1 dif_ref1 1 - 0 - 0 auto set to 0 : manual select mode entered briefly, manually selecting dif_ref1 as reference. 1 dif_ref1 1 - 1 - 0 auto set to 1 : device is placed in autoswitch mode (delay recommended to ensure device fully locked), re-initializing autoswitch with dif_ref1 now specified as the initial reference clock. table 6: example autoswitch sequence
m1025/26 datasheet rev 1.0 8 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet optional hitless switching and phase build-out the m1025/26 is available with a hitless switching feature that is enabled during device manufacturing. in addition, a phase build-out feature is also offered. these features are offered as device options and are specified by device order code. refer to ?ordering information? on pg. 14 . the hitless switching feature (with or without phase build-out) is designed for applications where switching occurs between two stable system reference clocks. it should not be used in loop timing applications, or when reference clock jitter is greater than 1 ns pk-pk. hitless switching is triggered by the lol circuit, which is activated by a 4 ns phase transient. this magnitude of phase transient can generated by the cdr (clock & data recovery unit) in lo op timing mode, especially during a system jitter tolerance test. it can also be generated by some types of stratum clock dplls (digital pll), especially those that do not include a post de-jitter apll (analog pll). when the hitless switching feature is enabled, it is always triggered by lol, whether in autoswitch mode ( auto pin high) or select mode ( auto pin low). for example, in manual mode, the hitless switching feature operates when lol goes high even if there is no reselection of the input mux. this enables the use of an upstream clock mux (such as on the host card), while still providing mtie complianc e when readjusting to the resultant phase change. when the m1025/26 is operating in wide bandwidth mode ( nbw = 0 ), the optional hitless switching function puts the device into narrow bandwidth mode when activated. this allows the pll to lock the new input clock phase gradually. with proper configuration of the external loop filter, the output clock complies with mtie and tdev specifications for gr-253 (sonet) and itu g.813 (sdh) during input reference clock changes. the optional proprietary phase build-out (pbo) function enables the pll to absorb most of the phase change of the input clock. the pbo function selects a new vcso clock edge for the pll phase detector feedback clock, selecting the edge closest in phase to the new input clock phase. this reduces re-lock time, the generation of wander, and extra output clock cycles. the hitless switching and phase build-out functions are triggered by the lol circuit. for proper operation, a low phase detector frequency must be avoided. see ?guidelines using lol? on pg. 6 for information regarding the phase detector frequency. hs/pbo triggers the hs function (or the combined hs/pbo function) is armed after the device locks to the input clock refer- ence. once armed, hs is triggered by the occurance of a loss of lock condition. this would typically occur as a consequence of a clock reference failure, a clock failure upstream to the m1025/26, or a m1025/26 clock refer- ence mux reselection. when pin auto = 1 (automatic reference reselection mode) hs is used in conjunction with input reselection. when auto = 0 (manual mode), hs will still occur upon an input phase transient, however the clock input is not reselected (this enables hitless switching when using an external mux for clock selection). hs/pbo operation once triggered, the following hs/pbo sequence occurs: 1. the hs function disables the pll phase detector and puts the device into nbw (narrow bandwidth) mode. the internal resistor rin is changed to 2100k ? . see the narrow bandwidth (nbw) control pin on pg. 8 . 2. if included, the pbo function adds to (builds out) the phase in the clock feedback path (in vcso clock cycle increments) to align the feedback clock with the (new) reference clock input phase. 3. the pll phase detector is enabled, allowing the pll to re-lock. 4. once the pll phase detector feedback and input clocks are locked to within 2 ns for eight consecutive cycles, a timer (wbw timer) for resuming wide bandwidth (in 175 ns) is started. 5. when the wbw timer times out, the device reverts to wide loop bandwidth mode ( i.e., rin is returned to 100k ? ) and the hs/pbo function is re-armed. narrow bandwidth ( nbw ) control pin a narrow loop bandwidth control pin ( nbw pin) is included to adjust the pll loop bandwidth. in wide bandwidth mode ( nbw = 0 ), the internal resistor rin is 100k ? . with the nbw pin asserted, the internal resistor rin is changed to 2100k ? . this lowers the loop bandwidth by a factor of about 21 (approximately 2100 / 100) and lowers the damping factor by a factor of about 4.6 (the square root of 21), assuming the same loop filter components.
m1025/26 datasheet rev 1.0 9 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch product data sheet integrated circuit systems, inc. external loop filter to provide stable pll operation, the m1025/26 requires the use of an external loop filter. this is provided via the provided filter pins (see figure 5). due to the differential signal path design, the implementation requires two identical complementary rc filters as shown here. figure 5: external loop filter see table 7, example external loop filter component values, below. pll bandwidth is affected by loop filter component values, the ?m? value, and the ?pll loop constants? listed in ac characteristics on pg. 12. the mr_sel3:0 settings can be used to actively change pll loop bandwidth in a given application. see ?m and r divider look-up tables (lut)? on pg. 3. pll simulator tool available a free pc software utility is available on the ics website (www.icst.com). the m2000 timing modules pll simulator is a downloadable application that simulates pll jitter and wander transfer characteristics. this enables the user to set appropriate external loop component values in a given application. for guidance on device or loop filter implementa- tion, contact cmbu (co mmercial business unit) product applications at (508) 852-5400. c post c post v c nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in 6 7 5 49 8 example external loop filter component values 1 for m1025-yz-155.5200 and m1026-yz-155.5200 vcso parameters: k vco = 200khz/v, r in = 100k ? (pin nbw = 0), vcso bandwidth = 700khz. device configuration example external loop filter comp. values nominal performance using these values f ref (mhz) f vcso (mhz) mr_sel3:0 mdiv nbw r loop c loop r post c post pll loop bandwidth damping factor passband peaking (db) 19.44 2 155.52 0 0 0 0 8 0 6.8 k ? 10 f 82 k ? 1000 pf 315 hz 5.4 0.068 38.88 3 155.52 0 0 0 1 16 0 12 k ? 10 f 82k ? 1000 pf 270 hz 6.7 0.044 77.76 4 155.52 0 1 0 1 8 0 6.8 k ? 10 f 82k ? 1000 pf 315 hz 5.4 0.068 77.76 5 155.52 0 1 1 0 32 0 22 k ? 4.7 f 82k ? 1000 pf 250 hz 6.0 0.05 155.52 4 155.52 1 0 1 0 16 0 12 k ? 10 f 82k ? 1000 pf 270 hz 6.7 0.044 155.52 5 155.52 1 0 1 1 64 0 47 k ? 2.2 f 82k ? 1000 pf 266 hz 6.2 0.05 table 7: example external loop filter component values note 1: k vco , vcso bandwidth, m divider value, and external loop filter component values determine loop bandwidth, damping factor, and passband peaking. for pll simulator software, go to www.icst.com. note 2: this row is for the m1025 only. note 3: this row is for the m1026 only. note 4: optimal for system clock filtering. note 5: optimal for loop timing mode (lol, autosw itch, or hitless switching should not be used).
m1025/26 datasheet rev 1.0 10 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet a bsolute m aximum r atings 1 symbol parameter rating unit v i inputs - 0.5 to v cc + 0.5 v v o outputs - 0.5 to v cc + 0.5 v v cc power supply voltage 4.6 v t s storage temperature - 45 to + 100 o c table 8: absolute maximum ratings note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress s pecifications only. func tional operation of produc t at these conditions or any conditions beyond those li sted in recommended conditions of operation, dc characteristics, or ac characteristics is not implied. exposure to abs olute maximum rating condit ions for extended periods may affect product reliability . r ecommended c onditions of o peration symbol parameter min typ max unit v cc positive supply voltage 3.135 3.3 3.465 v t a ambient operating temperature commercial 0 + 70 o c industrial -40 + 85 o c table 9: recommended conditions of operation
m1025/26 datasheet rev 1.0 11 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch product data sheet integrated circuit systems, inc. e lectrical s pecifications dc characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), t a = -40 o c to + 85 o c (industrial), f vcso = f out = 150- 175mhz, lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit conditions power supply v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 175 225 ma all differential inputs v p - p peak to peak input voltage dif_ref0, ndif_ref0, dif_ref1, ndif_ref1 0.15 v v cmr common mode input 0.5 v cc - .85 v c in input capacitance 4 pf differential inputs with pull-down i ih input high current (pull-down) dif_ref0, dif_ref1 150 a v cc = v in = 3.456v i il input low current (pull-down) - 5 a r pulldown internal pull-down resistance 50 k ? differential inputs biased to vcc/2 i ih input high current (biased) ndif_ref0, ndif_ref1 150 a v in = 0 to 3.456v i il input low current (biased) - 150 a r bias biased to vcc/2 see figure 4 all lvcmos / lvttl inputs v ih input high voltage auto, ref_sel, mr_sel3, mr_sel2, mr_sel1, mr_sel0, p_sel1, p_sel0, nbw 2 v cc + 0.3 v v il input low voltage - 0.3 0.8 v c in input capacitance 4 pf lvcmos / lvttl inputs with pull-down i ih input high current (pull-down) auto, ref_sel, mr_sel3, mr_sel2, mr_sel1, mr_sel0, p_sel1, p_sel0 150 a v cc = v in = 3.456v i il input low current (pull-down) - 5 a r pulldown internal pull-down resistance 50 k ? lvcmos / lvttl inputs with pull-up i ih input high current (pull-up) nbw 5 a v cc = 3.456v v in = 0 v i il input low current (pull-up) -1 50 a r pullup internal pull-up resistance 50 k ? differential outputs v oh output high voltage fout, nfout v cc - 1.4 v cc - 1.0 v v ol output low voltage v cc - 2.0 v cc - 1.7 v v p - p peak to peak output voltage 1 note 1: single-ended measurement. see figure 6, output rise and fall time, on pg. 12. 0.4 0.85 v lvcmos output v oh output high voltage lol, ref_ack 2.4 v cc v i oh = 1 ma v ol output low voltage gnd 0.4 v i ol = 1 ma table 10: dc characteristics
m1025/26 datasheet rev 1.0 12 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet e lectrical s pecifications ( continued ) p arameter m easurement i nformation output rise and fall time figure 6: output rise and fall time output duty cycle figure 7: output duty cycle ac characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), t a = -40 o c to + 85 o c (industrial), f vcso = f out = 150- 175mhz, lvpecl outputs termnated with 50 ? to v cc - 2v symbol parameter min typ max unit conditions f in input frequency dif_ref0, ndif_ref0, dif_ref1, ndif_ref1 15 700 mhz f out output frequency fout, nfout 62.5 175 mhz apr absolute pull-range of vcso commercial 120 200 ppm industrial 50 150 ppm pll loop constants 1 note 1: parameters needed for pll simulator software; see table 7, example external loop filt er component values, on pg. 9. k vco vco gain 200 khz/v r in internal loop resistor wide bandwidth 100 k ? narrow bandwidth 2100 k ? bw vcso vcso bandwidth 700 khz phase noise and jitter n single side band phase noise @ 155.52 mhz 1 khz offset - 83 dbc/hz fin=19.44 or 38.88_mhz tot. pll ratio = 8 or 4. see pg. 3 10 khz offset - 113 dbc/hz 100 khz offset - 136 dbc/hz j(t) jitter (rms) @ 155.52 mhz 12 khz to 20 mhz 0.4 0.6 ps odc output duty cycle 2 note 2: see parameter measurement information on pg. 12. 45 50 55 % t r output rise time 2 for fout, nfout 350 450 550 ps 20 % to 80 % t f output fall time 2 for fout, nfout 350 450 550 ps 20 % to 80 % table 11: ac characteristics 20% 80% t r 20% t f 80% clock output v p - p nfout fout t pw t period (output pulse width) t period t pw odc =
m1025/26 datasheet rev 1.0 13 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m1025/26 vcso b ased c lock pll with a uto s witch product data sheet integrated circuit systems, inc. d evice p ackage - 9 x 9mm c eramic l eadless c hip c arrier mechanical dimensions: figure 8: device package - 9 x 9mm ceramic leadless chip carrier refer to the saw pll application notes web page at www.icst.com/products/appnotes/sawpllappnotes.htm for application notes, including recommended pcb footprint, solder mask, and furnace profile.
m1025/26 datasheet rev 1.0 14 of 14 revised 28jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high reliability, or other extraordina ry environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. m1025/26 vcso b ased c lock pll with a uto s witch product data sheet o rdering i nformation part numbering scheme figure 9: part numbering scheme standard vcso output frequencies (mhz) * consult ics for the availabilit y of other vcso frequencies. part number: m102x- 1z - xxx.xxxx vcso frequency (mhz) ? - ? = 0 to + 70 o c (commercial) see table 12, right. consult ics for other frequencies. i = - 40 to + 85 o c (industrial) temperature frequency input divider option output type 1 = lvpecl hitless switching / phase build-out options 1 = none (for cml or lvds clock output, consult factory) 3 = hitless switching with phase build-out 5 = fin can equal fvcso divided by: 8, 2, or 1 6 = fin can equal fvcso divided by: 4, 2, or 1 4 = phase build-out (without hitless switching) 2 = hitless switching 125.0000 167.3280 155.5200 167.3316 156.2500 167.7097 156.8324 168.0400 161.1328 172.6423 166.6286 173.3708 167.2820 table 12: standard vcso output frequencies (mhz) note *: fout can equal fvcso divided by: 1 or 2 example part numbers vcso frequency (mhz) temperature order part number (examples) 155.52 commercial m1025 -11 - 155.5200 or m1026- 11 - 155.5200 industrial m1025 -11 i 155.5200 or m1026- 11 i 155.5200 156.25 commercial m1025 -11 - 156.2500 or m1026 -11 - 156.2500 industrial m1025 -11 i 156.2500 or m1026- 11 i 156.2500 table 13: example part numbers

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