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hufa 76407dk8 t_f085 3 .5a, 60v, 0.105 ohm, dual n-channel, logic level ultrafet? power mosfet packaging symbol features ? ultra low on-resistance -r ds (on) = 0 .090 ?, v gs = 10 v -r ds (on) = 0 .105 ?, v gs = 5v simulation models - temperature compensated pspice? and saber? electrical models - spice and saber thermal impedance models - www.fairchildsemi.com peak current vs pulse width curve uis rating curve transient thermal impedance curve vs board mounting area switching time vs r gs cu rves or dering information ab solute maximum ratings t a = 25 o c, unless otherwise specified this product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. for a c opy of the requirements, see aec q101 at: h ttp://w ww.aecouncil.com/ reliability data can be found at: http ://www.f airchildsemi.com/product s/di screte/relia bility/index.html. all fairchild semiconductor products are manufactured, assembled and tested under iso9000 and qs9000 quality systems certif ication. jedec ms-012aa branding dash 1 2 3 4 5 drain 1 (8) source1 (1) drain 1 (7) drain 2 (6) drain 2 (5) source2 (3) gate2 (4) ga te1 (2) p art number package brand hufa76407dk8 t_f085 ms-012aa 76407dk8 note: when ordering, use the entire part number. add the suffix t _f085 to obtain the variant in tape and reel, e.g., hufa76407dk8t _f085 . huf a76407dk8t_f085 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss 60 v dr ain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dg r 60 v g ate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 16 v dr ain current continuous (t a = 25 o c, v gs = 5v) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d c ontinuous (t a = 25 o c, v gs = 10v) (figure 2) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d c ontinuous (t a = 100 o c, v gs = 5v) (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d c ontinuous (t a = 100 o c, v gs = 4.5v) (figure 2) (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d p ulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 3. 5 3.8 1.0 1.0 figure 4 a a a a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . uis figures 6, 17, 18 power dissipation (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d d erate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 20 w mw/ o c o perating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t st g - 55 to 150 o c max imum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l p ackage body for 10s, see techbrief tb334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pk g 300 260 o c o c no tes: 1. t j = 25 o c t o 125 o c. 2. 50 o c/ w measured using fr-4 board with 0.76 in 2 (490. 3 mm 2 ) c opper pad at 1 second. 3. 228 o c/ w measured using fr-4 board with 0.006 in 2 (3. 87 mm 2 ) c opper pad at 1000 seconds. ca ution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress only ratin g and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. d ata sheet october 2010 ? 201 0 fairchild semiconductor corporation hufa76407dk8t _f085 rev. c1 www.fairchildsemi.com 1 qualified to aec q101 rohs compliant
ele ct rical specifications t a = 25 o c, unles s otherwise specified parameter symbol test conditions min typ max units off state specifications drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (f igure 12) 60 - - v i d = 250 a, v gs = 0v , t a = - 40 o c (f i gure 12) 55 - - v zero gate voltage drain current i dss v ds = 55v, v gs = 0v - - 1 a v ds = 50v, v gs = 0v , t a = 15 0 o c - - 250 a gate to source leakage current i gs s v gs = 16v - - 100 na on state specifications gate to source threshold voltage v gs (t h) v gs = v ds , i d = 250 a (figure 11) 1 - 3 v drain to source on resistance r ds( o n) i d = 3. 8a, v gs = 10v (figures 9, 10) - 0.075 0.090 ? i d = 1. 0a , v gs = 5v (figure 9) - 0.088 0.105 ? i d = 1. 0a, v gs = 4.5v (figure 9) - 0.092 0.110 ? thermal specifications thermal resistance junction to ambient r ja p ad a rea = 0.76 in 2 (490. 3 m m 2 ) ( n ote 2) - - 50 o c/w p ad a rea = 0.027 in 2 (17. 4 m m 2 ) (f igure 23) - - 191 o c/w p ad a rea = 0.006 in 2 (3. 87 m m 2 ) (f igure 23) - - 228 o c/w s w itching specifications (v gs = 4. 5v) turn-on time t on v dd = 30v , i d = 1. 0a v gs = 4. 5 v, r gs = 27 ? (f igures 15, 21, 22) - - 57 ns turn-on delay time t d( o n) -8- ns rise time t r -3 0- ns turn-off delay time t d( o ff) -2 5- ns fall time t f -25- ns turn-off time t off - - 75 ns switching specifications (v gs = 10v) t urn-on time t on v dd = 30v , i d = 3. 8a v gs = 10v, r gs = 30? (f igures 16, 21, 22) - - 24 ns turn-on delay time t d( o n) -5 - ns rise time t r -1 1- ns turn-off delay time t d( o ff) -4 6- ns fall time t f -3 1- ns turn-off time t off - - 116 ns gate charge specifications total gate charge q g(t ot) v gs = 0v to 10v v dd = 30v, i d = 1. 0a, i g( r ef) = 1. 0ma (figures 14, 19, 20) - 9.4 11.2 nc gate charge at 5v q g(5) v gs = 0v to 5v - 5.3 6.4 nc threshold gate charge q g(t h) v gs = 0v to 1v - 0.42 0.5 nc gate to source gate charge q gs -1 . 05- nc gate to drain ?miller? charge q gd -2 . 4-nc capacitance specifications input capacitance c is s v ds = 25v, v gs = 0v , f = 1mhz (figure 13) - 330 - pf output capacitance c os s - 100 - pf reverse transfer capacitance c rs s -1 8- pf s our ce to drain diode specifications p a rameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 3.8a - - 1.25 v i sd = 1.0a - - 1.00 v reverse recovery time t rr i sd = 1. 0a, di sd / d t = 100a/ s- - 4 8 n s reverse recovered charge q rr i sd = 1.0a, di sd / d t = 100a/ s- - 8 9 n c huf a76407dk8 t_f085 hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 2
ty pical performance curves figure 1. normalized power dissipation vs ambient temperature figure 2. maximum cont inuous drain current vs ambient temperature figure 3. normalized maximum transient thermal impedance figure 4. peak current capab ility t a , am bient temperature ( o c) po we r dissipation multiplier 0 02 5 5075100 15 0 0. 2 0. 4 0.6 0.8 1.0 1.2 125 1 2 3 4 50 75 100 125 15 0 0 25 i d , dra in current (a) t a , a m bient temperature ( o c) v gs = 4. 5v, r ja = 228 o c/ w v gs = 1 0 v, r ja = 5 0 o c/w 0.0 1 0. 1 1 2 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 0. 0 01 10 -5 t , rectangular pulse duration (s) z ja , no rm alized thermal impedance si ng le pulse no t es: duty factor: d = t 1 /t 2 pea k t j = p dm x z ja x r ja + t a p dm t 1 t 2 dut y cycl e - descending order 0.5 0.2 0.1 0.05 0.01 0.02 r ja = 2 2 8 o c/w 10 10 0 20 0 1 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -5 i dm , p eak current (a) t , pulse width (s) v gs = 5 v r ja = 2 2 8 o c/w t r ansconductance may limit current in this region t c = 2 5 o c i = i 25 1 50 - t a 12 5 fo r temperatures above 25 o c der a te peak cu rre nt as follows: hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 3 huf a76407dk8 t_f085
f igure 5. forward bias safe operating area note: refer to fairchild application notes an9321 and an 9322. figure 6. unclamped inductive switching capability figure 7. transfer characteristics fig ure 8. saturation characteristics figure 9. drain to source on resistance vs gate voltage and drain current figure 10. normalized drain to source on resistance vs junction temperature ty pical performance curves (c ontinued) 1 10 10 2 0 0 50 0 0. 1 1 10 0 s 10 m s 1m s v ds , drain to source voltage (v) i d , drain current (a) li m ited by r ds ( on) area m a y be operation in this t j = ma x rated t a = 2 5 o c si ng le pulse 100 r ja = 228 o c/w 10 0 1 10 50 0. 01 0. 1 1 1 0 i as , a valanche current (a) t av , time in avalanche (ms) t av = ( l )(i as ) / (1.3*rated bv ds s - v dd ) if r = 0 if r 0 t av = ( l/r)ln[(i as *r )/ (1.3*rated bv dss - v dd ) + 1 ] st ar ting t j = 2 5 o c st ar ting t j = 1 5 0 o c 0 5 10 15 20 2. 0 2.5 3.0 3.5 4.5 5 .0 i d, drain current (a) v gs , gate to source voltage (v) pulse dura tion = 80 s duty cycl e = 0.5% max v dd = 1 5 v t j = 2 5 o c t j = 15 0 o c t j = - 5 5 o c 4. 0 5 10 15 20 0 123 4 0 v gs = 4 v i d , drain cu rrent (a) v ds , dra in to source voltage (v) v gs = 3 v v gs = 5 v v gs = 10v t a = 2 5 o c v gs = 4 . 5v v gs = 3 . 5v pul s e duration = 80 s duty cycle = 0.5% max i d = 1 a 60 90 12 0 150 24681 0 v gs , g ate to source voltage (v) i d = 3 . 8a r ds( o n) , drain t o source on resistance (m ? ) pul se dura tion = 80 s duty cycle = 0.5% max 3579 0.5 1.0 1.5 2.0 - 80 -40 0 40 80 120 16 0 no rma lized drain to source t j , j unction temperature ( o c) on resi st ance v gs = 1 0 v, i d = 3. 8a pulse dur a tion = 80 s du t y cycle = 0.5% max 0.5 hufa76407dk8t _f085 rev. c1 www.fairchildsemi.com 4 huf a76407dk8 t_f085
figure 11. normalized gate threshold voltage vs junction temperature figure 12. normalized drain to source breakdown voltage vs junction temperature figure 13. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an 7260. figure 14. gate charge waveforms for constant gate current figure 15. switching time vs gate resistance fi gure 16. switching time vs gate resistance ty pical performance curves (c ontinued) 0. 6 0. 8 1.0 1.2 -80 -40 0 40 80 120 16 0 nor m alized gate t j , j unction temperature ( o c) v gs = v ds , i d = 250 a t h reshold voltage 0. 9 1. 0 1.1 1.2 -80 -40 0 40 80 120 16 0 t j , j unction temperature ( o c) no rmali zed drain to source breakdown voltage i d = 250 a 5 10 10 0 10 00 0.1 1.0 10 6 0 c, cap acitance (pf) v ds , dr ain t o source voltage (v) v gs = 0 v , f = 1mhz c is s = c gs + c gd c oss ? c ds + c gd c rss = c gd 0 2 4 6 8 10 02468 1 0 v gs , ga te to source voltage (v) v dd = 30v q g , gat e charge (nc) i d = 3 . 8a i d = 1 . 0a waveforms in descending order: 20 30 40 50 0 1 02030405 0 0 sw i tching time (ns) r gs , g ate to source resistance ( ? ) v gs = 4. 5v, v dd = 30v, i d = 1 . 0a t d( o ff) t r t f t d(o n) 10 20 40 60 80 0 1 02030405 0 0 sw i tching time (ns) r gs , g ate to source resistance ( ? ) v gs = 10 v, v dd = 30v , i d = 3. 8a t d( o ff) t r t d( o n) t f hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 5 hu f a76407dk8 t_f085
te st circuits and waveforms fi gure 17. unclamped energy test circuit figure 18. unclamped energy waveforms figure 19. gate charge test circuit figure 20. gate charge waveforms figure 21. switching time test circuit figure 22. switching time waveform t p v gs 0. 0 1? l i as + - v ds v dd r g dut va r y t p t o obtain required peak i as 0v v dd v ds bv ds s t p i as t av 0 r l v gs + - v ds v dd dut i g( re f) v dd q g( th) v gs = 1 v q g( 5) v gs = 5 v q g( t ot) v gs = 1 0 v v ds v gs i g( ref) 0 0 q gs q gd v gs r l r gs dut + - v dd v ds v gs t on t d( o n) t r 90% 10 % v ds 90 % 10 % t f t d( o ff) t of f 90 % 50 % 50% 10% pulse width v gs 0 0 hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 6 hu f a76407dk8 t_f085
thermal r esistance vs. mounting pad area th e m aximum rated junction temperature, t jm , a nd the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , i n an application. therefore the application?s ambient temperature, t a ( o c) , and thermal resistance r ja ( o c/w) m ust be reviewed to ensure that t jm is ne ver exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the sop-8 package, the environment in which it is applied will have a significant influence on the part?s current and maximum power dissipation ratings. precise determination of p dm is co mplex and influenced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. the number of copper layers and the thickness of the board. 3. the use of external heat sinks. 4. the use of thermal vias. 5. air flow and board orientation. 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer?s preliminary application evaluation. figure 23 defines the r ja f or the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. displayed on the curve are r ja v al ues listed in the electrical specifications table. the points were chosen to depict the compromise between the c opper board area, the thermal resistance and ultimately the power dissipation, p dm . th er mal resistances corresponding to other copper areas can be obtained from figure 23 or by calculation using equation 2. r ja is defined as the natural log of the area times a cofficient added to a constant. the area, in square inches is the top copper area including the gate and source pads. while equation 2 describes the thermal resistance of a single die, several of the new ultrafets are offered with two die in the sop-8 package. the dual die sop-8 package introduces an additional thermal component, thermal coupling resistance, r ? . equa tion 3 describes r ? as a function of the top copper mounting pad area. the thermal coupling resistance vs. copper area is also graphically depicted in figure 23. it is important to note the thermal resistance (r ja ) a nd thermal coupling resistance ( r ? ) a r e equivalent for both die. for example at 0.1 square inches of copper: r ja 1 = r ja 2 = 15 9 o c/w r ? 1 = r ? 2 = 97 o c/w t j1 an d t j2 de fin e the junction temerature of the respective die. similarly, p 1 an d p 2 defi ne the power dissipated in each die. the steady state junction temperature can be calculated using equation 4 for die 1and equation 5 for die 2. example: to calculate the junction temperature of each die when die 2 is dissipating 0.5 watts and die 1 is dissipating 0 watts. the ambient temperature is 70 o c and the package is mounted to a top copper area of 0.1 square inches per die. use equation 4 to calulate t j1 an d and equation 5 to calulate t j2 . . t j1 = (0 watts)(159 o c/w) + (0.5 watts)(97 o c/w) + 70 o c t j1 = 1 19 o c (eq . 1 p d m t jm t a ? () r ja ---- --- ----------------------- - = ( e q. 2 ) r ja 103. 2 24.3 area () ln ?= 0 50 100 150 200 250 300 0. 0 01 0.01 0.1 1 r ? , ( ) , ( ) = ln ( area) r ? = ln ( area) ( e q. 3 ) r ? 46. 4 21.7 area () ln ?= ( e q. 4 ) t j1 p 1 r ja p 2 r ? t a ++ = hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 7 hu f a76407dk8 t_f085
t j2 = (0.5 watts)(159 o c/w) + (0 watts)(97 o c/w) + 70c t j2 = 1 50 o c the transient thermal impedance (z ja ) is also effected by varied top copper board area. figure 24 shows the effect of copper pad area on single pulse transient thermal impedance. each trace represents a copper pad area in square inches corresponding to the desc ending list in the graph. spice and saber thermal models are provided for each of the listed pad areas. copper pad area has no perceiva ble effect on trans ient thermal impedance for pulse widths less t han 100ms. for pulse widths less than 100ms the trans ient thermal impedance is determined by the die and package. therefore, ctherm1 through ctherm5 and r therm1 through rtherm5 remain constant for each of the thermal models. a listing of the model component values is available in table 1. (e q. 5 ) t j2 p 2 r ja p 1 r ? t a ++ = 0 40 80 12 0 16 0 10 -1 10 0 10 1 10 2 10 3 fi gure 24. thermal resistance vs mounting pad area t , rectangular pulse duration (s) z ja , t h ermal impedance ( o c/w) co pper board are a - descending order 0.020 in 2 0.140 in 2 0. 257 in 2 0. 380 in 2 0. 493 in 2 hufa76407dk8t _f085 rev. c1 www.fairchildsemi.com 8 hu f a76407dk8 t_f085
pspice electrical model .su b ckt hufa76407dk8 2 1 3 ; rev 28 may 1999 ca 12 8 4.55e-10 cb 15 14 5.20e-10 cin 6 8 3.11e-10 dbody 7 5 dbodymod dbreak 5 11 dbreakmod dplcap 10 5 dplcapmod ebreak 11 7 17 18 67.8 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 6 10 6 8 1 evthres 6 21 19 8 1 evtemp 20 6 18 22 1 it 8 17 1 ldrain 2 5 1.0e-9 lgate 1 9 1.5e-9 lsource 3 7 4.86e-10 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 3.00e-2 rgate 9 20 3.37 rldrain 2 5 10 rlgate 1 9 15 rlsource 3 7 4.86 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rso urcemod 3.80e-2 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51) /abs(v (5,5 1)))*(pwr(v (5,5 1)/(1e -6*105),2))} .model dbodymod d (is = 3.17e-13 rs = 2.21e-2 trs1 = 6.25e-4 trs2 = -1.11e-6 cjo = 6.82e-10 tt = 7.98e-8 m = 0.65) .model dbreakmod d (rs = 3.36e- 1trs1 = 1.25e- 4trs2 = 1.34e-6) .model dplcapmod d (cjo = 2.91e-1 0is = 1e-3 0 m = 0.85) .model mmedmod nmos (vto = 2.00 kp = 1 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 3.37) .model mstromod nmos (vto = 2.33 kp = 19 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod nmos (vto = 1.71 kp = 0.02 is = 1e- 30 n = 10 tox = 1 l = 1u w = 1u rg = 33.7 rs = 0.1) .model rbreakmod res (tc1 = 1.06e- 3tc2 = 0) .model rdrainmod res (tc1 = 1.23e-2 tc2 = 2.58e-5) .model rslcmod res (tc1 = 1.0e-3 tc2 = 1.0e-6) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc1 = -2.19e-3 tc2 = -4.97e-6) .model rvtempmod res (tc1 = -1.11e- 3tc2 = 0) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = -7.0 voff= -2.5) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.5 voff= -7.0) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -1.0 voff= 0) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = 0 voff= -1.0) .ends n o te: for further discussion of the pspice m odel, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1 991, written by william j. hepp and c. frank w heatley. 18 22 + - 6 8 + - 5 51 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv t emp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mw e ak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap eslc rslc1 10 5 51 50 rslc 2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 9 hu f a76407dk8 t_f085
sa ber electrical model r e v 28may 1999 template hufa76407dk8 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 3.17e-13, cjo = 6.82e-10, tt = 7.98e-8, m = 0.65) d..model dbreakmod = () d..model dplcapmod = (cjo = 2.91e-10, is = 1e-30, m = 0.85) m..model mmedmod = (type=_n, vto = 2.00, kp = 1, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.33, kp = 19, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.71, kp = 0.02, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7, voff = -2.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -7) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -1.0, voff = 0) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -1) c.ca n12 n8 = 4.55e-10 c.cb n15 n14 = 5.20e-10 c.cin n6 n8 = 3.11e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 1.5e-9 l.lsource n3 n7 = 4.86e-10 m.mmed n16 n6 n8 n8 = model=mmed mod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mst rongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.06e-3, tc2 = 0 res.rdbody n71 n5 = 2.21e-2, tc1 = -6.25e-4, tc2 = -1.11e-6 res.rdbreak n72 n5 = 3.36e-1, tc1 = 1.25e-4, tc2 = 1.34e-6 res.rdrain n50 n16 = 3. 00e-2, tc1 = 1.23e-2, tc2 = 2.58e-5 res.rgate n9 n20 = 3.37 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 15 res.rlsource n3 n7 = 4.86 res.rslc1 n5 n51 = 1e-6, tc1 = 1e-3, tc2 = 1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.80e-2, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.11e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.19e-3, tc2 = -4.97e-6 spe.ebreak n11 n7 n17 n18 = 67.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s 1amod sw_vcsp.s1b n 13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n 13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/105))** 2)) } } 18 22 + - 6 8 + - 19 8 + - 17 18 6 8 + - 5 8 + - rbreak rv t emp vbat rvthres it 17 18 19 22 12 13 15 s1a s1b s2a s2b ca cb egs eds 14 8 13 8 14 13 mw e ak ebreak dbody rsource source 11 7 3 lsource rlsource cin rdrain evthres 16 21 8 mmed mstro drain 2 ldrain rldrain dbreak dplcap iscl rslc1 10 5 51 50 rsl c 2 1 gate rgate evtemp 9 esg lgate rlgate 20 + - + - + - 6 rdbod y rdbreak 72 71 hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 10 huf a76407dk8 t_f085
sp ice thermal model rev 1j une 1999 hufa76407dk8 copper area = 0.02 in 2 ct herm 1 th 8 8.5e-4 ctherm2 8 7 1.8e-3 ctherm3 7 6 5.0e-3 ctherm4 6 5 1.3e-2 ctherm5 5 4 4.0e-2 ctherm6 4 3 9.0e-2 ctherm7 3 2 4.0e-1 ctherm8 2 tl 1.4 rtherm1 th 8 3.5e-2 rtherm2 8 7 6.0e-1 rtherm3 7 6 2 rtherm4 6 5 8 rtherm5 5 4 18 rtherm6 4 3 39 rtherm7 3 2 42 rtherm8 2 tl 48 sa ber thermal model copper area = 0.02 in 2 t em plate thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 8.5e-4 ctherm.ctherm2 8 7 = 1.8e-3 ctherm.ctherm3 7 6 = 5.0e-3 ctherm.ctherm4 6 5 = 1.3e-2 ctherm.ctherm5 5 4 = 4.0e-2 ctherm.ctherm6 4 3 = 9.0e-2 ctherm.ctherm7 3 2 = 4.0e-1 ctherm.ctherm8 2 tl = 1.4 rtherm.rtherm1 th 8 = 3.5e-2 rtherm.rtherm2 8 7 = 6.0e-1 rtherm.rtherm3 7 6 = 2 rtherm.rtherm4 6 5 = 8 rtherm.rtherm5 5 4 = 18 rtherm.rtherm6 4 3 = 39 rtherm.rtherm7 3 2 = 42 rtherm.rtherm8 2 tl = 48 } rt h erm6 rtherm8 rtherm7 rtherm5 rtherm4 rtherm3 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 tl 2 3 4 5 6 7 j unct ion ambient 8 th rt h erm2 rtherm1 ctherm7 ctherm8 t able 1 . thermal models component 0.02 in 2 0.14 i n 2 0.257 i n 2 0.38 i n 2 0.493 i n 2 ct her m6 9.0e-2 1.3e-1 1.5e-1 1.5e-1 1.5e-1 ctherm7 4.0e-1 6.0e-1 4.5e-1 6.5e-1 7.5e-1 ctherm8 1.4 2.5 2.2 3 3 rtherm6 39 26 20 20 20 rtherm7 42 32 31 29 23 rtherm8 48 35 38 31 25 hufa76407dk8t_f08 5 rev. c1 www.fairchildsemi.com 11 huf a76407dk8 t_f085
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