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s3c72h8/p72h8 product overview 1- 1 1 product overview overview the s3c72h8 single-chip cmos microcontroller has been designed for very high performance using samsung's state-of-the-art 4 -bit product developme nt approach, sam47 (samsung arrangeable microcontrollers). its main features are an up-to-13-digit lcd direct drive capability, 2-channel comparator inputs and outputs, and versatile 8-counter/ timers and 16-bit frequency counter. the s3c72h8 gives you an excellent design solution for a variety of lcd-related applications, specially thermostat control application. up to 21 pins of the available 64-pin qfp packages can be dedicated to i/o. and six vectored interrupts provide fast response to internal and external events. in addition, the s3c72h8's advanced cmos technology provides for low power consumption and a wide oper - ating voltage range.
product overview s3c72h8/p72h8 1- 2 features architecture ? sam47 4-bit cpu core memory ? data memory: 512 4 bit s ? program memory: 8196 8 bit s (including lcd display ram) memory-mapped i/o structure ? data memory bank 15 interrupts ? three internal vectored interrupts ? three external vectored interrupts ? two quasi-interrupts 8-bit timer/counter (t0) ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider 16-bit frequency counter (fc) ? a 16-bit binary up-counter ? external event counter ? gate function control watch-dog timer and basic timer ? 8-bit counter + 3-bit counter ? overflow signal of 8-bit counter makes a basic timer interrupt. and control the oscillation warm- up time ? overflow signal of 3-bit counter makes a system reset watch timer ? real-time an d interval time measurement ? four frequency outputs to buzzer sound ? clock source generation for lcd lcd controller/driver ? 26 segment and 4 common terminals ? maximum 13-digit lcd direct drive capability ? display modes: static, 1/2, 1/3, 1/4 duty ? voltage regulator and booster (1/3 bias: 1, 2, or 3v, 1/2 bias: 1.5, 3v) analog comparator ? 2 ch comparator (each cnp, cnn, cnout pins) bit sequential carrier ? support 16-bit serial data transfer in arbitrary format i/o p ort s ? 21 pins for standard i/o ? 26 pins for lcd segment output ? 4 pins for lcd common output ? two input pins for external interrupts oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64 main, and by 4 for sub clock ) power down mode ? idle mode (only cpu clock stops) ? stop mode (main or sub-system oscillation stops) voltage level detector ? v dd level detection circuit (2.2, 2.4, 3, or 4.0v) ? external pin level detect mode operating voltage range ? 1.8v to 5.5v at 3 mhz ? 2.0v to 5.5v at 4.19 mhz package type ? 64 -pin qfp
s3c72h8/p72h8 product overview 1- 3 block diagram program status word stack pointer arithmetic and logic unit internal interrupts reset instruction register 512 x 4-bit data memory p0.0/extref p0.1/sdat p0.2/sclk com0-com3 fcl i/o port 4,5 i/o port 0 i/o port 2 i/o port 3 i/o port 6 p2.0/int0 p2.1/int1 p2.2/tcl0 p2.3/fcl p3.0/tclo0 p3.1/btco p3.2/clo p3.3/buz p4.0/c0p p4.1/c0n p4.2/c0out p4.3/c1out p5.0/c1p p5.1/c1n p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 interrupt control block program counter clock otp block instruction decoder 8 k byte program memory voltage level detector two analog comparator extref cnp cn out cnn int0, int1 v pp / test x out x in xt out xt in sclk sdat voltage booster watch timer basic timer 16-bit freq counter 8-bit timer lcd driver/ controller watchdog timer c0 out c1 out tcl0 tclo0 seg0-seg25 ca, cb v lc0 -v lc2 figure 1 -1 . s3c72h8 simplified block diagram
product overview s3c72h8/p72h8 1- 4 pin assignments ca cb v lc0 v lc1 v lc2 p0.0/extref sdat /p0.1 sclk /p0.2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset / reset p2.0/int0 p2.1/int1 p2.2/tcl0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 p2.3/fcl p3.0/tclo0 p3.1/btco p3.2/clo p3.3/buz p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 p4.0/c0p p4.1/c0n p4.2/c0out p4.3pc1out s3c72h8 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 p5.1/c1n p5.0/c1p 51 50 43 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 figure 1 -2 . s3c72h8 pin assignment diagram
s3c72h8/p72h8 product overview 1- 5 pin descriptions table 1 - 1. s3c72h8 pin descriptions pin name pin type description number (64-qfp) share pin circuit type p0.0 p0.1 p0.2 i/o 3-bit i/o port. 1-bit and 4-bit read/write and test is possible. port 0 is software configurable as input or output. 3-bit pull-up resistors are software assignable. 6 7 8 extref ? ? d-1 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable. 17 18 19 20 int0 int1 tcl0 fcl d-1 p3.0 p3.1 p3.2 p3.3 i/o same as port 2. ports 2 and 3 can be addressed by 1, 4, and 8-bit read/write and test instruction. 21 22 23 24 tclo0 btco clo buz d-1 p4.0-p4.3 p5.0-p5.1 i/o 4/2-bit i/o ports. n-channel open-drain or push-pull output. 1, 4, and 8-bit read/write and test is possible. ports 4 and 5 can be paired to support 8-bit data transfer. pull-up resistors are assignable to port unit by software control. 29-32 33-34 c0p/ c0n/ c0out/ c1out c1p/ c1n e-1 p6.0-p6.3 i/o 4-bit i/o ports. port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 25-28 ks0-ks3 d-1 btco i/o basic timer clock output 22 p3.1 d-1 clo i/o cpu clock output 23 p3.2 d-1 buz i/o 2, 4, 8 or 16 khz frequency output for buzzer sound with 4.19mhz main-system clock or 32.768 khz sub-system clock. 24 p3.3 d-1 x out , x in ? crystal, ceramic, or rc oscillator signal for main- system clock. (for external clock input, use x in and input x in ?s reverse phase to x out ) 11, 12 ? ? xt out , xt in ? crystal oscillator signal for sub-system clock. (for external clock input, use xt in and input xt in ?s reverse phase to xt out ) 14, 15 ? ? int0, int1 i/o external interrupts. the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 17, 18 p2.0, p2.1 d-1
product overview s3c72h8/p72h8 1- 6 table 1 - 1. s3c72h8 pin descriptio ns (continued) pin name pin type description number (64-qfp) share pin circuit type ks0-ks3 i/o quasi-interrupt input with falling edge detection 25-28 p6.0-p6.3 d-1 extref i/o external reference input 6 p0.0 d-1 tcl0 i/o external clock input for timer/counter 0 19 p2.2 d-1 fcl i/o external clock input for frequency counter 20 p2.3 d-1 tclo0 i/o timer/counter 0 clock output 21 p3.0 d-1 com0-com3 o lcd common signal output 61-64 ? h-16 seg0-seg25 o lcd segment output 35-60 ? h-16 ca, cb ? voltage booster capacitor pins 1, 2 ? ? v lc0 -v lc2 ? voltage booster output pins (v lc0 is the regulated output, v lc1 is the 2* v lc0 output, v lc2 is the 3* v lc0 output) 3-5 ? ? c0p, c0n, c0out i/o comparator 0 non-inverting input, inverting input and output. c0out can be configured as c-mos push-pull or n-ch open drain output 29-31 p4.0-p4.2 ? c1p, c1n, c1out i/o i comparator 1 non-inverting input, inverting input and output. c1out can be configured as c-mos push-pull or n-ch open drain output 32-34 p4.3-p5.1 ? reset ? reset signal for chip initialization 16 ? b v dd ? main power supply 9 ? ? v ss ? ground 10 ? ? test ? test signal input (must be connected to v ss ) 13 v pp ? sdat i/o serial data for otp programming 7 p0.1 sclk i/o serial clock for otp programming 8 p0.2 v pp ? power supply pin for eprom cell writing 13 test note: pull-up resistors for ports 0, 2, 3, and 6 are automatically disabled if they are configured to output mo de. but pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.
s3c72h8/p72h8 product overview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1 -3. pin circuit type a v dd out output disable data p-channel n-channel figure 1 -5. pin circuit type c in v dd figure 1 -4. pin circuit type b (reset) i/o circuit type c pull-up resistor p-cannel output disable data v dd resistor enable input disable figure 1 -6. pin circuit type d-1 (p0, p2, p3, p6)
product overview s3c72h8/p72h8 1- 8 v dd pull-up enable v dd in/out pne output disable data input disable to data bus to comparator figure 1 -7 . pin circuit type e-1 (p4, p5) out v lc2 v lc1 seg/com data v lc0 figure 1 -8 . pin circuit type h-16 (com/seg)
s3c72h8/p72h8 address spaces 2 - 1 2 address spaces program memory (rom) overview rom maps for s3c72h8 devices are mask programmable at the factory. s3c72h8 has 8k 8-bit program memory. in its standard configuration, the device's 8,192 8-bit program memory has four areas that are directly addressable by the program counter (pc): ? 14 -byte area for vector addresses ? 96-byte instruction reference area ? 18 -byte general-purpose area ? 8064 -byte general-purpose area general-purpose program memory two program memory areas are allocated for general-purpose use: one area is 18 bytes in size and the other is 8,064 bytes. vector addresses a 1 4 -byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set th eir initial value for the corre sponding service routines. the 1 2 -byte area can be used alternately as general-purpose rom. ref instructions locations 0020h - 007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and three-byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2- 1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h - 000 d h 14 general-purpose program memory 000c h - 001fh 18 ref instruction look-up table area 0020h - 007fh 96 general-purpose program memory 0080h -1 fffh 8064
address spaces s3c72 h8/p72h8 2 - 2 general-purpose memory areas the 18-byte area at rom locations 000c h - 001fh and the 8,064 -byte area at rom locations 0080h -1 fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 1 4 -byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 14 -byte vector addresses are organized as follows: to set up the vector address area for specific programs, use the instruction ventn. 0000h reset intb int0 int1 intg intt0 int3 7 6 5 4 3 2 1 0 0002h 0004h 0006h 0008h 000ah 000ch figure 2-1 . vector address structure emb erb 0 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0
s3c72h8/p72h8 address spaces 2 - 3 + + p rogramming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. when all vector interrupts are used: org 0000h vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address by int0 vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address by int1 vent4 0,0,int g ; emb ? 0, erb ? 0; jump to int g address by intg vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address by intt0 vent6 0,0,int3 ; emb ? 0, erb ? 0; jump to int 3 address by int3 2. when a specific vectored in terrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address by int1 vent4 0,0,int g ; emb ? 0, erb ? 0; jump to intg address by intg o rg 0 00ch ; intt0 interrupt not used vent6 0,0,int3 ; emb ? 0, erb ? 0; jump to int 3 address by int3 org 0010h 3. if an int0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address by reset vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address by intb vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int 1 address by int1 vent4 0,0,int g ; emb ? 0, erb ? 0; jump to int g address by intg vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to in t t 0 address by intt0 vent6 0,0,int3 ; emb ? 0, erb ? 0; jump to int 3 address by int3 org 0010h general-purpose rom area in this example, when an intg interrupt is generated, the corres ponding vector area is not vent4 int g , but vent5 intt0. this causes an int g interrupt to jump incorrectly to the intt0 address and causes a cpu malfunction to occur.
address spaces s3c72 h8/p72h8 2 - 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger b yte sizes that are stored in ad dresses 0020h - 007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two o ne-byte instruct ions, a single two-byte instruc tion, or three-byte instruction such as a jp (jump) or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. by using ref instructions you can execute instructions large than one byte . in summary, there are three ways you can use the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? cal ling subroutines at any location by referencing a call instruction stored in the look-up table. + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; 47, ea ? #00h org 0080 main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
s3c72h8/p72h8 address spaces 2 - 5 data memory (ram) overview in its standard configuration, the 512 x 4 -b it data memory has four areas: ? 32 4-bit working register area in bank 0 ? 224 4 -bit general-purpose area in bank 0 which is also used a s the stack area ? 230 4 -bit general-purpose area in bank 1 ? 26 4 -bit area for lcd data in bank 1 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses to make it easier to reference, the data memory area has three memory banks - bank 0, bank 1 and bank 15. the select memory bank instruction (smb) is used to select the bank you want to select as working data memory. data stored in ram locations are 1, 4, and 8-bit addressable. one exception is the lcd data register area, which is 1-bit and 4-bit addressable only. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset . however, when reset signal is generated in power-down mode, the most of data memory contents are held. working registers (32 x 4 bits) general purpose register and stack area (224 x 4 bits) general purpose registers (230 x 4 bits) lcd data registers (26 x 4 bits) memory mapped i/o address registers (128 x 4 bits) bank 0 bank 1 bank 15 ~ ~ 000h 0ffh 100h 1e5h 1e6h 1ffh 01fh 020h f80h fffh figure 2-2 . data memory (ram) map
address spaces s3c72 h8/p72h8 2 - 6 memory banks 0, 1, and 15 bank 0 (000h - 0ffh) the lowest 32 nibbles of bank 0 (000h - 01fh) are used as working registers; the next 224 nibbles (020h - 0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h - 1ffh) the lowest 230 nibbles of bank1 (100h? 1e5 h) are for general -purpose use; use the remaining of 26 nibbles (1e6 h - 1ffh) as display registers or as general purpose memory. bank 15 (f80h - fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1 or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressin g, you can access locations 000- 07fh of bank 0 and bank 15. with indirect addressing, only bank 0 (000h - 0ffh) can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. lcd data register area bit values for lcd segment data are stored in data memory bank 1. register locations in this area that are not used to store lcd data can be assigned to general-purpose use.
s3c72h8/p72h8 address spaces 2 - 7 table 2- 2. data memory organization and addressing addresses register areas bank emb value smb value 000h - 01fh working registers 0 0, 1 0 020h - 0ffh stack and general-purpose registers 100h -1e5 h general-purpose registers 1 1 1 1e6 h - 1ffh lcd data registers f80h - fffh i/o-mapped hardware registers 15 0, 1 15 + + programming tip ? clearing data memory banks 0 and 1 clear banks 0 and 1 of the data memory area: ramclr smb 1 ; ram (100h - 1ffh) clear ld hl,#00h ld a,#0h rmcl1 ld @hl,a incs hl jr rmcl1 smb 0 ; ram (010h - 0ffh) clear ld hl,#10h rmcl0 ld @hl,a incs hl jr rmcl0
address spaces s3c72 h8/p72h8 2 - 8 working registers working registers, mapped to ram address 000h-01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. a e l h x w z y a ...y a ...y a ...y 000h 001h 002h 003h 004h 005h 006h 007h 008h 00fh 010h 017h 018h 01fh register bank 1 register bank 2 register bank 3 working register bank 0 data memory bank 0 figure 2-3 . working register map
s3c72h8/p72h8 address spaces 2 - 9 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou tines. following this convention helps to prevent possible data corruption duri ng program execution due to con tention in register bank addressing. table 2- 3. working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 ? ? always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e and a, can either be manipulated individually using 4-bit instructions, or together as register pai rs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. (msb) (lsb) (msb) (lsb) y w h e z x l a figure 2-4. register pair configuration
address spaces s3c72 h8/p72h8 2 - 10 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. y a ea 1-bit accumulator 4-bit accumulator 8-bit accumulator figure 2-5 . 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction.
s3c72h8/p72h8 address spaces 2 - 11 + + programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack sm b 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret
address spaces s3c72 h8/p72h8 2 - 12 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp can be read or w ritten by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next instruction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the en able memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. + + p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of sp is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) - 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h - 7fh, f80h - fffh)
s3c72h8/p72h8 address spaces 2 - 13 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decreased by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decreased by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decreased by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. lower register upper register sp -2 sp -1 sp sp -1 sp pc11-pc8 pc13 0 0 pc3-pc0 pc7-pc4 0 0 emb erb 0 0 0 0 sp -2 sp -3 sp -4 sp -5 sp -6 psw sp -1 sp pc11-pc8 0 0 pc3-pc0 pc7-pc4 is1 is0 emb erb c sp -2 sp -3 sp -4 sp -5 sp -6 psw sc2 sc1 sc0 pc12 pc13 pc12 push (after push, sp sp-2) call (after push, sp sp-6) interrupt (when int is acknowledged) sp sp-6) figure 2-6 . push-type stack operations
address spaces s3c72 h8/p72h8 2 - 14 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4- bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. sp pc11-pc8 pc13 0 0 pc3-pc0 pc7-pc4 0 0 emb erb 0 0 0 0 psw pc11-pc8 0 0 pc3-pc0 pc7-pc4 is1 is0 emb erb c psw sc2 sc1 sc0 iret (sp sp+6) ret or sret (sp sp+6) pop (sp sp+2) sp +1 sp +2 lower register upper register sp +5 sp+6 sp+4 sp +3 sp +2 sp +1 sp sp +5 sp+6 sp+4 sp +3 sp +2 sp +1 sp pc12 pc13 pc12 figure 2-7 . pop-type stack operations
s3c72h8/p72h8 address spaces 2 - 15 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@l). (bit addressing is independent of the current emb value.) in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2- 4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret
address spaces s3c72 h8/p72h8 2 - 16 program counter (pc) a 13 -bit program counter (pc) stores addresses for instruction f etches during program execution (s3c7235 microcontroller has 14-bit program counter, pc0?pc13). whenever a reset operation o r an interrupt occurs, bits pc12 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1- byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an inter rupt request has been serviced. psw values are mapped as follows: (msb) (lsb) fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read ins tructions, depending on the spe cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or h ardware interrupt. after the in terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logical zero. table 2- 5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
s3c72h8/p72h8 address spaces 2 - 17 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2- 6 shows the effects of is0 and is1 flag settings. table 2- 6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) are serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re- enable interrupt processing. + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
address spaces s3c72 h8/p72h8 2 - 18 emb flag (emb) the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0, 1 or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h?07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", the general-purpose areas of bank 0, 1 and 15 can be accessed by using the appropriate smb value. + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h,a ; (f90h) ? a, bank 15 is selected 2. when emb = "1": smb 1 ; select memory bank 1 ld a,#9 h ld 90h,a ; (190h) ? a, bank 1 is selected ld 34h,a ; (134h) ? a, bank 1 is selected smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected
s3c72h8/p72h8 address spaces 2 - 19 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea
address spaces s3c72 h8/p72h8 2 - 20 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 in the psw indicate the current program skip conditions and are set and reset automatically during program execution. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2- 7, affect the carry flag. table 2- 7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes : 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. 'intn' refers to the specific interrupt being executed and is not an instruction.
s3c72h8/p72h8 address spaces 2 - 21 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p4.0,c ; output result from carry flag to p4.0
s3c72h8/p72h8 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smbn. you will recall that the smbn instruction is used to select ram bank 0, 1 or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1 or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? always use an even-numbered ram address as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes s3c 72h8/p72h8 3 - 2 notes: 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. addressing mode ram areas working registers da da.b @hl @h+da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 emb = 0 emb = 1 x x x bank 0 (general registers and stack) bank 1 (general registers) bank 1 (display registers) bank 15 (peripheral hardware registers) 000h 01fh 020h 07fh 080h 0ffh 100h 1e5h 1e6h 1ffh f80h fffh smb = 1 smb = 1 smb = 1 smb = 1 smb = 15 smb = 15 ff0h fb0h fbfh fc0h figure 3- 1. ram address structure
s3c72h8/p72h8 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0, reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 vent4 0,1,int g ; emb ? 0, erb ? 1, branch int g vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 vent6 0,1,int 3 ; emb ? 0, erb ? 1, branch int 3 reset ? ? ? bitr emb
addressing modes s3c 72h8/p72h8 3 - 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1 or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: if smb = 0, 000h - 0ffh if smb = 1, 100h - 1ffh if smb = 15, f80h - fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h - 07fh in bank 0 and to locations f80h - fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h - 0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independent of the current status of the emb flag. these exceptions are described in table 3- 1. table 3- 1 . ram addressing not affected by the emb value address addressing method affected hardware program examples 000h - 0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push pop fb0h - fbfh ff0h - fffh 1-bit direct addressing psw, scmod, iex, irqx, i/o bits emb bitr ie4 fc0h - fffh 1-bit indirect addressing using the l register bsc, i/o btst fc3h.@l band c,p3.@l
s3c72h8/p72h8 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con - sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3- 2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 sb register smb 2 smb 1 smb 0 0 0 srb 1 srb 0 smb (f83h) srb (f82h) figure 3- 2 . smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the four available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1 or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting. the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes s3c 72h8/p72h8 3 - 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the s3c7 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3- 2 . 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h - 07fh bank 0 ? da.b direct: bit is indicated by the ram address (da), memory bank selection, and specified bit number (b). 0 f80h - fffh bank 15 all 1-bit addressable peripherals (smb = 15) 1 000h - fffh smb = 0, 1, 15 mema.b direct: bit is indicated by ad - dressable area (mema) and bit number (b). x fb0h - fbfh ff0h - fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: lower two bits of reg - ister l as indicated by the up - per 10 bits of ram area (memb) and the upper two bits of register l. x fc0h - fffh bank 15 bscn.x pn.n @h + da.b indirect: bit indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1,15 all 1-bit addressable peripherals (smb = 15) note : ?x? means don?t care.
s3c72h8/p72h8 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 b its aflag ; 34h.3 ? 1 bits bflag ; f85h.3 ? 1 btst cfla g ; if fbah.0 = 1, skip bits bflag ; else if, fbah.0 = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1
addressing modes s3c 72h8/p72h8 3 - 8 4-bit addressing table 3- 3 . 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h - 07fh bank 0 ? da direct: 4-bit address indicated by the ram address (da) and the memory bank selection 0 f80h - fffh bank 15 all 4-bit ad dressable pe ripherals 1 000h - fffh smb = 0, 1,15 (smb = 15) @hl indirect: 4-bit address indi - cated by the memory bank selection and register hl 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 15 all 4-bit ad dressable pe ripherals (smb = 15) @wx indirect: 4-bit address indi - cated by register wx x 000h - 0ffh bank 0 ? @wl indirect: 4-bit address indi - cated by register wl x 000h - 0ffh bank 0 note : ? x ? means don?t care. + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh (lcon)) ? a 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld a,p3 ; a ? (p3) smb 0 ld adata,a ; (046h) ? a ld bdata,a ; (08eh) ? a
s3c72h8/p72h8 addressing modes 3 - 9 + + programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing (example 1) 1. if emb = "0", compare bank 0 locations 040h - 046h with bank 0 locations 060h - 066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h - 046h) cpse a,@hl ; if bank 0 ( 060h - 066h) = a, skip sret decs l jr comp ret 2. if emb = "1", compare bank 0 locations 040h - 046h to bank 1 locations 160h - 166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h - 046h) cpse a,@hl ; if bank 1 (160h - 166h) = a, skip sret decs l jr comp ret
addressing modes s3c 72h8/p72h8 3 - 10 4-bit indirect addressing (example 2) 1. if emb = "0", exchange bank 0 locations 040h - 046h with bank 0 locations 060h - 066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h - 046h) xchd a,@hl ; bank 0 (060h - 066h) ? a jr trans 2. if emb = "1", exchange bank 0 locations 040h - 046h to bank 1 locations 160h - 166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h - 046h) xchd a,@hl ; bank 1 (160h - 166h) ? a jr trans
s3c72h8/p72h8 addressing modes 3 - 11 8-bit addressing table 3- 4 . 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h - 07fh bank 0 ? da direct: 8-bit address indicated by the ram address ( da = even number ) and memory bank selection 0 f80h - fffh bank 15 all 8-bit ad dressable pe ripherals 1 000h - fffh smb = 0, 1, 15 (smb = 15) @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h - 0ffh bank 0 ? 1 000h - fffh smb = 0, 1, 15 all 8-bit ad dressable pe ripherals (smb = 15) + + programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e 2. if emb = "1": adata e qu 46h bdata equ 8eh smb 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e
addressing modes s3c 72h8/p72h8 3 - 12 + + programming tip ? 8-bit addressing modes (continued) 8-bit indirect addressing 1. if emb = "0": adata equ 46h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) 2. if emb = "1": adata equ 46h smb 1 ld hl,#adata ld ea,@hl ; a ? (146h), e ? (147h)
s3c72h8/p72h8 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4- 1 contains detailed information about i/o mapping for peripheral hardware in b ank 15 (register loca tions f80h - fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non-manipulable) ? read-only, write- only, or read and write addressa bility ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map s3c72h8/p72h8 4 - 2 table 4- 1 . i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 f82h sb "0" "0" srb1 srb0 ? no no no f83h smb3 smb2 smb1 smb0 locations f84h is not mapped. f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt .3 .2 .1 .0 r no no yes f87h .7 .6 .5 .4 f88h wmod .3 .2 .1 .0 w no no yes f89h .7 "0" .5 .4 locations f8ah- f8bh are not mapped. f8ch lmod .3 .2 .1 .0 w .3 no yes f8dh " 0 " " 0 " .5 .4 f8eh lcon .3 " 0 " " 0 " .0 w no yes no location f8fh is not mapped. f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h toe "0" toe0 boe "0" r/w yes no no f93h tol "0" "0" tol0 "0" r yes no no f94h tcnt0 .3 .2 .1 .0 r no no yes f95h .7 .6 .5 .4 f96h tref0 .3 .2 .1 .0 w no no yes f97h .7 .6 .5 .4 f98h wdmod .3 .2 .1 .0 w no no yes f99h .7 .6 .5 .4 f9ah wdflag wdtcf "0" "0" "0" w yes yes no f9bh-fbfh are not mapped. fa0h fcmod .3 .2 .1 .0 r/w .4(r) yes yes fa1h "0" .6 .5 .4(r) .3/.0 (r/w) f9bh-fafh are not mapped. fa4h fcntl .3 .2 .1 .0 r no no yes fa5h .7 .6 .5 .4 fa6h fcnth .3 .2 .1 .0 r no no yes fa7h .7 .6 .5 .4
s3c72h8/p72h8 memory map 4 - 3 table 4- 1 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c ( 1 ) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 .3 "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 fb6h imod2 .3 .2 .1 .0 fb7h scmod .3 .2 "0" .0 w yes no no fb8h int (a) "0" "0" ieb irqb r/w yes yes no location fb9h is not mapped fba h int (b) "0" "0" iew irqw r/w yes yes no fbbh int (b1) "0" "0" ie3 irq3 fbc h int (c) "0" "0" iet0 irqt0 fbd h int (d) "0" "0" ies irqs fbe h int (e) ie1 irq1 ie0 irq0 fbf h int (f) "0" "0" ie2 irq2 fc0h bsc0 .3 .2 .1 .0 r/w yes yes yes fc1h bsc1 .3 .2 .1 .0 fc2h bsc2 .3 .2 .1 .0 fc3h bsc3 .3 .2 .1 .0 fd0h clmod .3 "0" .1 .0 w no yes no locations fd1h-fd5h are not mapped. fd6h pne pne4.3 pne4.2 pne4.1 pne4.0 w no no yes fd7h ? ? pne5.1 pne5.0 fd8h imod3 .3 .2 .1 .0 w no no yes fd9h "0" "0" .5 .4 locations fda h -fdbh are not mapped. fdch pumod pur.3 pur.2 "0" pur.0 w no no yes fddh "0" pur.6 pur.5 pur.4 locations fde h -fdfh are not mapped. fe0h c mod .3 .2 .1 .0 r/ w no yes no fe1h cmpcon .3(r) .2 .1(r) .0 r/ w no yes no fe2h vldcon .3(r) .2 .1 .0 r/ w no yes no locations fe3h- fe 5 h are not mapped.
memory map s3c72h8/p72h8 4 - 4 table 4- 1 . i/o map for memory bank 15 (concluded) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fe6h pmg 0 pm2.3 pm2.2 pm2.1 pm2.0 w no no yes fe7h pm3.3 pm3.2 pm3.1 pm3.0 fe8 h pmg1 pm5 pm4 extref pm0 w no no yes fe9 h pm6.3 pm6.2 pm6.1 pm6.0 locations feah-fefh are not mapped. ff0h port 0 "0" .2 .1 .0 r/w yes yes no locations ff1h is not mapped. ff2h port 2 .3 .2 .1 .0 r/w yes yes no ff3h port 3 .3/.7 .2/.6 .1/.5 .0/.4 r/w ff4h port 4 .3 .2 .1 .0 r/w yes yes yes ff5h port 5 "0" "0" .1/.5 .0/.4 r/w yes yes ff6h port 6 .3 .2 .1 .0 r/w yes yes yes locations ff7h- fffh are not mapped. notes: the carry flag can be read or written by specific bit manipulation instructions only. register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4- 1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions.
s3c72h8/p72h8 memory map 4 - 5 clmod - clock output mode control register clmod.3 enable/disable clock output control bit clmod.2 bit 2 0 always logic zero clmod.1 - .0 clock source and frequency selection control bits 3 2 1 0 bit identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 r = read-only w = write-only r/w = read/write bit value immediately after a reset bit number in msb to lsb order type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) description of the effect of specific bit settings bit identifier used for bit addressing register and bit ids used for bit addressing fd0h register location in ram bank 15 name of individual bit or related bits register name register id select cpu clock souce fx/4, fx/8, fx/64 (1.05 mhz, 524khz, or 65.5 khz), or fxt/4 select system clock fxx/8 (524 khz at 4.19 mhz) select system clock fxx/16 (262 khz at 4.19 mhz) select system clock fxx/64 (65.5 khz at 4.19 mhz) 0 0 1 1 0 1 0 1 0 disable clock output at the clo pin 0 enable clock output at the clo pin figure 4- 1 . register description format
memory map s3c72h8/p72h8 4 - 6 bmod ? basic timer mode register f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 .3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero .2 - .0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: signal stabilization interval: fxx / 2 12 (1.02 khz) 2 20 / fxx (250 ms) 0 1 1 input clock frequency: signal stabilization interval: fxx / 2 9 (8.18 khz) 2 17 / fxx (31.3 ms) 1 0 1 input clock frequency: signal stabilization interval: fxx / 2 7 (32.7 khz) 2 15 / fxx (7.82 ms) 1 1 1 input clock frequency: signal stabilization interval: fxx / 2 5 (131 khz) 2 13 / fxx (1.95 ms) notes : 1 . when a reset occurs, the oscillation stabilization time is 31.3 ms (2 17 /fxx) at 4.19 mhz. 2 . 'fxx' is the system clock rate given a clock frequency of 4.19 mhz.
s3c72h8/p72h8 memory map 4 - 7 clmod ? clock output mode register fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 enable/disable clock output control bit 0 disable clock output 1 enable clock output .2 bit 2 0 always logic zero .1 - .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8, fx/64 , or fx t/ 4 (1.05 mhz, 524 khz, or 65.5 khz) 0 1 select system clock fxx/8 (524 khz) 1 0 select system clock fxx/16 (262 khz) 1 1 select system clock fxx/64 (65.5 khz) note : 'fxx' is the system clock, given a clock frequency of 4.19 mhz.
memory map s3c72h8/p72h8 4 - 8 c mod ? c omparator mode register f e0h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write r/ w r/ w r/ w r/ w bit addressing 4 4 4 4 .3 bit 3 0 select p4.3/c1out as a normal i/o port 1 select p4.3/c1out as a comparator output .2 bit 2 0 select p5.0/c1p, p5.1/c1n as normal i/o port 1 select p5.0/c1p, p5.1/c1n as comparator output .1 bit 1 0 select p4.2/c0out as a normal i/o port 1 select p4.2/c0out as a comparator output .0 bit 0 0 select p4.0/c0p, p4.1/c0n as normal i/o port 1 select p4.0/c0p, p4.1/c0n as comparator output
s3c72h8/p72h8 memory map 4 - 9 cm pc o n ? c omparator control register f e1 h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write r r/ w r r/ w bit addressing 4 4 4 4 cmpcon .3 bit 3 0 comparator 1 (c1out) output is low when c1p c1n 1 comparator 1 (c1out) output is high when c1p > c1n cmpcon .2 bit 2 0 disable comparator 1 1 enable comparator 1 cmpcon .1 bit 1 0 comparator (c0out) output is low when c0p c0n 1 comparator (c0out) output is high when c0p > c0n cmpcon.0 bit 0 0 disable comparator 0 1 enable comparator 0
memory map s3c72h8/p72h8 4 - 10 fc mod ? frequency counter mode register fa1h, f a 0h bit 7 6 5 4 3 2 1 0 identifier "0" fcmod.6 fcmod.5 fcmod.4 fcmod.3 fcmod.2 fcmod.1 fcmod.0 reset value 0 0 0 0 0 0 0 0 read/write r/ w r/ w r/ w r r/ w r/ w r/ w r/ w bit addressing 4 /8 4 /8 4 /8 1/ 4 /8 1/ 4 /8 4 /8 4 /8 1/ 4 /8 . 7 bit 7 0 always logic zero fcmod . 6 - .5 bit 6 - 5 0 0 hold the up-counting operation of fcnt 0 1 enable up- counting in fcnt; select fcl pin at falling edge 1 0 enable up- counting in fcnt; select c0out pin at falling edge 1 1 enable up- counting in fcnt; select c1out pin at falling edge fcmod . 4 bit 4 0 /1 gate flag fcmod . 3 bit 3 1 clear fcnt and irqg. (this bit is automatically cleared to logic zero immediately after counting resumes) ; start bit fcmod . 2 - .0 bit 2 - 0 0 0 0 close gate 0 0 1 open gate; the writing command will start fc operation after clear fcnt and irqg; start bit 0 1 0 select the gate time, fw/2 10 (31.25ms at fw = 32768 hz) 0 1 1 select the gate time, fw/2 11 (62.5ms at fw = 32768 hz) 1 0 0 select the gate time, fw/2 12 (125ms at fw = 32768 hz) 1 0 1 select the gate time, fw/2 13 (250ms at fw = 32768 hz) 1 1 0 select the gate time, fw/2 14 (500ms at fw = 32768 hz) 1 1 1 select the gate time, fw/2 15 (1000ms at fw = 32768 hz)
s3c72h8/p72h8 memory map 4 - 11 ie0, 1 , irq0, 1 ? int0, 1 interrupt enable/request flags fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.)
memory map s3c72h8/p72h8 4 - 12 ie2 , irq2 ? int2 interrupt enable/request flags fbfh bit 3 2 1 0 identifier "0" "0" ie2 irq2 reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the int2 pin 1 enable int2 interrupt requests at the int2 pin irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at int2 or ks0-ks7 respectively . since int2 is a quasi-interrupt, irq2 flag must be cleared by software.)
s3c72h8/p72h8 memory map 4 - 13 ie 3 , irq3 ? int 3 interrupt enable/request flags fb bh bit 3 2 1 0 identifier "0" "0" ie 3 irq3 reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero ie 3 int2 interrupt enable flag 0 disable int 3 interrupt requests at the int 3 pin 1 enable int3 interrupt requests at the int3 pin irq 3 int 3 interrupt request flag ? generate int 3 interrupt (this bit is set and cleared automatically by hardware)
memory map s3c72h8/p72h8 4 - 14 ieb, irqb ? intb interrupt enable/request flags fb8h bit 3 2 1 0 identifier "0" "0" ieb irqb reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bit 3 - 2 0 always logic zero ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
s3c72h8/p72h8 memory map 4 - 15 ie g , irq g ? int g interrupt enable/request flags fbdh bit 3 2 1 0 identifier "0" "0" ie g irq g reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero ie g int g interrupt enable flag 0 disable int g interrupt requests 1 enable intg interrupt requests irqg int g interrupt request flag ? generate intg interrupt (this bit is set and cl eared automatically by hardware)
memory map s3c72h8/p72h8 4 - 16 iet0 , irqt0 ? intt0 interrupt enable/request flags fbch bit 3 2 1 0 identifier "0" "0" iet0 irqt0 reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
s3c72h8/p72h8 memory map 4 - 17 iew , irqw ? intw interrupt enable/request flags fbah bit 3 2 1 0 identifier "0" "0" iew irqw reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 - .2 bits 3 - 2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 1, 0.5 , 0.25 seconds or 3.91 ms.) note : since intw is a quasi-interrupt, the irqw flag must be cleared by software.
memory map s3c72h8/p72h8 4 - 18 imod0 ? external interrupt 0 (int0) mode register fb4h bit 3 2 1 0 identifier .3 "0" .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 interrupt sampling clock selection bit 0 select cpu clock as a sampling clock 1 select sampling clock frequency of the selected system clock (fxx/64) .2 bit 2 0 always logic zero .1 - .0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising signal edge 0 1 interrupt requests are triggered by a falling signal edge 1 0 interrupt requests are triggered by both rising and falling signal edges 1 1 interrupt request flag (irq0 ) cannot be set to logic one
s3c72h8/p72h8 memory map 4 - 19 imod1 ? external interrupt 1 (int1) mode register fb5h bit 3 2 1 0 identifier "0" "0" "0" imod1.0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 - .1 bits 3 - 1 0 always logic zero .0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
memory map s3c72h8/p72h8 4 - 20 imod2 ? external inte rrupt 2 (int2) mode register fb6 h bit 3 2 1 0 identifier imod2.3 imod2.2 imod2.1 imod2.0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod .3 bits 3 0 disable int2 at falling edge of ks3 (p6.3) 1 enable int2 at falling edge of ks3 (p6.3) imod.2 bits 2 0 disable int2 at falling edge of ks2 (p6.2) 1 enable int2 at falling edge of ks2 (p6.2) imod . 1 bits 1 0 disable int2 at falling edge of ks1 (p6.1) 1 enable int2 at falling edge of ks1 (p6.1) imod . 0 bits 0 0 disable int2 at falling edge of ks0 (p6.0) 1 enable int2 at falling edge of ks0 (p6.0)
s3c72h8/p72h8 memory map 4 - 21 imod 3 ? external inte rrupt 3 (int3) mode register fd9h, fd8 h bit 7 6 5 4 3 2 1 0 identifier "0" "0" .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 - .6 bits 7-6 0 always logic zero .5 - .4 bits 5-4 0 0 disable int3 at c1out (cmpcon.3) 0 1 enable int3 at falling edge of c1out (cmpcon.3) 1 0 enable int3 at rising edge of c1out (cmpcon.3) 1 0 enable int3 at falling/rising edge of c1out (cmpcon.3) .3 - .2 bits 3-2 0 0 disable int3 at c0out (cmpcon.1) 0 1 enable int3 at falling edge of c0out (cmpcon.1) 1 0 enable int3 at rising edge of c0out (cmpcon.1) 1 1 enable int3 at falling/rising edge of c0out (cmpcon.1) .1 - .0 bits 1-0 0 0 disable int3 at vldout (vldcon.3) 0 1 enable int3 at falling edge of vldout (vldcon.3) 1 0 enable int3 at rising edge of vldout (vldcon.3) 1 1 enable int3 at falling/rising edge of vldout (vldcon.3)
memory map s3c72h8/p72h8 4 - 22 ipr ? interrupt priority register fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 disable all interrupt processing 1 enable processing for all interrupt service requests .2 - .0 interrupt priority assignment bits 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb interrupts at highest priority 0 1 0 process int0 interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 0 process int g interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process int 3 interrupts at highest priority
s3c72h8/p72h8 memory map 4 - 23 lcon ? lcd output control register f8eh bit 3 2 1 0 identifier "0" " 0 " " 0 " .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 bit 3 0 always logic zero .2 bit 2 0 always logic zero .1 bit 1 0 always logic zero .0 lcd display control bit 0 lcd output low, turns display off: cut off current and turn off voltage regulator and booster 1 if lmod.3 = ?0?: lcd output low; turns display off if lmod.3 = ?1?: com and seg output in display mode; turn display on notes: 1. you can manipulate lcon.0, when you try to turn on/off lcd display internally. 2. to select the lcd bias, you must properly configure both lmod register and the external lcd bias circuit ` connection.
memory map s3c72h8/p72h8 4 - 24 lmod ? lcd mode register f8dh, f8ch bit 3 2 1 0 3 2 1 0 identifier " 0 " " 0 " .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/ 8 8 8 8 .7 - .6 bit 7-6 0 always logic zero .5 - .4 lcd clock (lcdck) frequency selection bits 0 0 fw/ 2 9 = 64 hz 0 1 fw/ 2 8 = 128 hz 1 0 fw/ 2 7 = 256 hz 1 1 fw/ 2 6 = 512 hz .3 - .0 duty and bias selection for lcd display 0 ? ? ? lcd display off 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty, 1/3 bias 1 0 1 1 1/3 duty, 1/2 bias 1 0 1 0 1/2 duty, 1/2 bias 1 1 1 0 static
s3c72h8/p72h8 memory map 4 - 25 pcon ? power control register fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 - .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode .1 - .0 cpu clock frequency selection bits 0 0 if scmod.0 = "0" , fx/64; if scmod.0 = "1", fxt/ 4 1 0 if scmod.0 = "0 ", fx/8; if scmod.0 = "1", fxt/4 1 1 if scmod.0 = "0", fx/4; if scmod.0 = "1", fxt/4 note : 'fx' is the main - system clock; 'fxt' is the sub - system clock.
memory map s3c72h8/p72h8 4 - 26 pmg0 ? port i/o mode flags (group 1: ports 2 and 3) fe7h, fe6 h bit 7 6 5 4 3 2 1 0 identifier pm3.3 pm3. 2 pm3. 1 pm3. 0 pm 2 .3 pm 2 .2 pm 2 .1 pm 2 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm3.3 p3.3 i/o mode selection flag 0 set p3.3 to input mode 1 set p3.3 to output mode pm3. 2 p 3 .2 i/o mode selection flag 0 set p3 .2 to input mode 1 set p3 .2 to output mode pm3. 1 p 3 .1 i/o mode selection flag 0 set p 3 .1 to input mode 1 set p3 .1 to output mode pm3. 0 p 3 .0 i/o mode selection flag 0 set p3 .0 to input mode 1 set p3 .0 to output mode pm 2 .3 p 2 .3 i/o mode selection flag 0 set p2 .3 to input mode 1 set p2 .3 to output mode pm 2 .2 p 2 .2 i/o mode selection flag 0 set p 2 .2 to input mode 1 set p 2 .2 to output mode pm 2 .1 p 2 .1 i/o mode selection flag 0 set p 2 .1 to input mode 1 set p2 .1 to output mode pm 2 .0 p 2 .0 i/o mode selection flag 0 set p 2 .0 to input mode 1 set p 2 .0 to output mode
s3c72h8/p72h8 memory map 4 - 27 pmg 1 ? port i/o mode flags (group 2: ports 0, 4, 5, and 6) fe9h, fe8 h bit 7 6 5 4 3 2 1 0 identifier pm6.3 pm6.2 pm6.1 pm6.0 pm5 pm4 extref (p0.0) pm0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm6.2 bit 6.2 0 set p6.2 to input mode 1 set p6.2 to output mode pm6.1 p6.1 i/o mode selection flag 0 set p 6.1 to input mode 1 set p 6.1 to output mode pm6.0 p 6.0 i/o mode selection flag 0 set p 6.0 to input mode 1 set p 6.0 to output mode pm5 p 5 i/o mode selection flag 0 set p 5 to input mode 1 set p 5 to output mode pm4 p4 i/o mode selection flag 0 set p4 to input mode 1 set p4 to output mode extref (p0.0) p0.0 i/o mode selection flag 0 normal i/o mode 1 set external reference input mode pm0 p0 i/o mode selection flag 0 set p0 to input mode 1 set p0 to output mode
memory map s3c72h8/p72h8 4 - 28 pne ? n-ch annel open-drain mode register fd7h, fd6 h bit 7 6 5 4 3 2 1 0 identifier " 0 " " 0 " pne.5 pne.4 pne.3 pne.2 pne.1 pne.0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 - .6 bit 7-6 0 always logic zero pne.5 p 5 n-channel open-drain configurable bit 0 configure p 5.1 as a push-pull 1 configure p 5.1 as a n-channel open-drain pne.4 p4 n-channel open-drain configurable bit 0 configure p 5.0 as a push-pull 1 configure p5.0 as a n-channel open-drain pne.3 p3 n-channel open-drain configurable bit 0 configure p 4. 3 as a push-pull 1 configure p 4. 3 as a n-channel open-drain pne.2 p 2 n-channel open-drain configurable bit 0 configure p 4. 2 as a push-pull 1 configure p4. 2 as a n-channel open-drain pne.1 p1 n-channel open-drain configurable bit 0 configure p 4.1 as a push-pull 1 configure p4. 1 as a n-channel open-drain pne.0 p 0 n-channel open-drain configurable bit 0 configure p 4. 0 as a push-pull 1 configure p4. 0 as a n-channel open-drain
s3c72h8/p72h8 memory map 4 - 29 psw ? program status word fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4 /8 1/4 /8 1/4 /8 1/4 /8 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 - sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h - fffh) and to the locations 000h - 07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, 2, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
memory map s3c72h8/p72h8 4 - 30 pumod ? pull-up resistor mode register fddh, fdch bit 7 6 5 4 3 2 1 0 identifier " 0 " pur.6 pur.5 pur . 4 pur .3 pur . 2 " 0 " pur . 0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero pur.6 connect/disconnect port 6 pull-up resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor pur.5 connect/disconnect port 5 pull-up resistor control bit 0 disconnect port 5 pull-up resistor 1 connect port 5 pull-up resistor pur . 4 connect/disconnect port 4 pull-up resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor pur . 3 connect/disconnect port 3 pull-up resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor pur . 2 connect/disconnect port 2 pull-up resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor . 1 bit 1 0 always logic zero pur . 0 connect/disconnect port 0 pull-up resistor control bit 0 disconnect port 0 pull-up resistor 1 connect port 0 pull-up resistor note : pull-up resistors for ports 0, 2, 3 and 6 are automatically disabled if they are configured to output mode. but pull-up resistors for ports 4 and 5 are retained its state even though they are configured to output mode.
s3c72h8/p72h8 memory map 4 - 31 scmod ? system clock mode control register fb7h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 1 1 1 1 .3 , .2 and .0 cpu clock selection and main system clock oscillation control bits 0 0 0 select main - system clock (fx) ; enable sub-system clock 0 0 1 select sub - system clock (fxt); enable main - system clock 0 1 0 select main-system clock (fx ); disable sub- system clock 1 0 1 select sub-system clock (fxt); disable main-system clock .1 bit 1 0 strong mode 1 normal mode note : scmod bits 3 and 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions.
memory map s3c72h8/p72h8 4 - 32 tmod0 ? timer/counter 0 mode register f91h, f90h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 .7 bit 7 0 always logic zero .6 - .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 fxx/2 10 (4.09 khz ) 1 0 1 fxx/2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx/ (4.19 mhz) note : ?fxx? = selected system clock of 4.19mhz .3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately (this bit is cleared automatically when counting starts.) .2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 .1 -.0 bit 1 -0 0 always logic zero
s3c72h8/p72h8 memory map 4 - 33 toe ? timer output enable flag register f92h bit 3 2 1 0 identifier "0" toe0 boe "0" reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 bit3 0 always logic zero toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output at the tclo0 pin 1 enable timer/counter 0 output at the tclo0 pin boe basic timer output enable flag 0 disable basic timer output at the btco pin 1 en able basic timer output at the btco pin .0 bits 0 0 always logic zero
memory map s3c72h8/p72h8 4 - 34 vldcon ? voltage level detector control register f e 2h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write r r/w r/w r/w bit addressing 4 4 4 4 .3 bit3 0 v in > v ref (when vld is enabled) 1 v in < v ref (when vld is enabled) .2 bit 2 0 disable the vld 1 enabled the vld .1 - .0 bits 1-0 0 0 v vld = 2.2v 0 1 v vld = 2.4v 1 0 v vld = 3.0v 1 1 v vld = 4.0v
s3c72h8/p72h8 memory map 4 - 35 wdflag ? watchdog timer counter clear flag register f9ah bit 3 2 1 0 identifier wdtcf "0" "0" "0" reset value 0 0 0 0 read/write w w w w bit addressing 1/4 1/4 1/4 1/4 wdtcf watchdog timer counter clear flag 1 clears the watchdog timer counter .2-.0 bits 2-0 0 always logic zero note : after watchdog timer is cleared by writing ?1?, this bit is cleared to ?0? automatically.
memory map s3c72h8/p72h8 4 - 36 wdmod ? watchdog timer mode register f99h, f98h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 wdmod watchdog timer enable/disable control 5ah disable watchdog timer function others enable watchdog timer function
s3c72h8/p72h8 memory map 4 - 37 wmod ? watch timer mode register f89h, f88h bit 7 6 5 4 3 2 1 0 identifier .7 "0" .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output .6 bit 6 0 always logic zero .5 - .4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output .3 - .2 watch timer speed control 0 0 sets irqw to 1 seconds 0 1 sets irqw to 0.5 seconds 1 0 sets irqw to 0.25 seconds 1 1 sets irqw to 3.91 ms .1 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer .0 watch timer clock selection bit 0 select main system clock (fx)/128 as the watch timer clock 1 select a subsystem clock as the watch timer clock
s3c72h8/p72h8 oscillator circuits 6 - 1 6 oscillator circuits overview the s3c72h8 microcontroller has two oscillator circuits: a main-system clock circuit, and a sub-system clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. specifically, a clock pulse is required by the following peripheral modules: ? lcd controller ? basic timer ? timer/counter 0 ? watch timer ? clock output circuit ? frequency counter cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main-system clock fxt sub-system clock fxx selected system clock
oscillator circuits s3c72h8/p72h8 6 - 2 clock control registers when the system clock mode control register, scmod , a nd the power control register, pcon , are both cleared to zero after reset , the normal cpu operating mode is enabled, a main-system clock of fx/64 is selected, and main-system clock oscillation is initiated. pcon is used to select normal cpu operating mode or one of two power-down modes ? stop or idle. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode. the system clock mode control register, scmod, lets you select the main-system clock (fx) or a sub-system clock (fxt) as the cpu clock and to start (or stop) main or sub system clock oscillation. the resulting clock source, either main-system clock or sub-system clock, is referred to as the cpu clock. the main-system clock is selected and oscillation started when all scmod bits are cleared to logic zero. by setting scmod.3 , scmod.2 and scmod.0 to different values, cpu can operate in a sub-system clock source and start or stop main or sub system clock oscillation. to stop main-system clock oscillation, you must use the stop instruction (assuming the main-system clock is selected) or manipulate scmod.3 to ?1? (assuming the sub system clock is selected). the main-system clock frequencies can be divided by 4, 8, or 64 and a sub-system clock frequencies can only be divided by 4. by manipulating pcon bits 1 and 0, you select one of the following frequencies as cpu clock. fx/4, fxt/4, fx/8, fx/64 using a sub-system clock if a sub-system clock is being used as the selected system clock , the idle power-down mode can be initiated by executing an idle instruction. the sub-system clock can be stopped by setting scmod.2 to ?1?. the watch timer, buzzer and lcd display operate normally with a sub-system clock source, since they operate at very slow speeds ( 122 m s at 32.768 khz ) and with very low power consumption.
s3c72h8/p72h8 oscillator circuits 6 - 3 x in x out xt in xt out main-system oscillator circuit main osc stop signal selector fxx selector stop signal sub-system oscillator circuit watch timer lcd controller selector pcon.1 pcon.2 pcon.3 pcon.0 fxt 1/8-1/4096 frequency dividing circuit 1/2 1/16 watch timer basic timer timer 0/counter lcd controller frequecy counter wait release signal internal reset signal power down release signal oscillator control circuit pcon.3, .2 clear 1/4 cpu clock fx : main-system clock fxt: sub-system clock fxx: selected system clock cpu stop signal (by idle or stop instruction) idle stop fx fxt scmod.3 scmod.2 scmod.0 frequency counter sub osc scmod.1 driving ability figure 6- 1. clock circuit diagram
oscillator circuits s3c72h8/p72h8 6 - 4 main-system oscillator circuits x in x out figure 6- 2. crystal/ceramic oscillator x in x out figure 6- 3. external oscillator x in x out r figure 6- 4. rc oscillator sub-system oscillator circuits xt in xt out figure 6 - 5. crystal/ceramic oscillator xt in xt out figure 6- 6. external oscillator
s3c72h8/p72h8 oscillator circuits 6 - 5 power control register (pcon) the power control register ( pcon ) is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. the pcon can be addressed di rectly by 4-bit write instructions or indirectly by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon pcon.3 and pcon.2 can be addressed only by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 can be written only by 4-bit ram control instruction. pcon is a wr ite-only register. there are three basic choices: ? divided fx clock frequency of 4, 8, or 64 ? d ivided fxt clock frequency of 4. pcon.1 and pcon.0 settings are also connected with the system clock mode control register, scmod. if scmod.0 = "0", the main-system clock is always selected by the pcon.1 and pcon.0 setting; if scmod.0 = "1" the sub-system clock is selected. reset clears pcon register values (and scmod) to logic zero. table 6- 1. power control register ( pcon ) organization pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 scmod.0 = 0 scmod.0 = 1 0 0 fx/64 fxt/4 1 0 fx/8 1 1 fx/4 pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu o perating mode 0 1 idle 1 0 stop mode
oscillator circuits s3c72h8/p72h8 6 - 6 + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a instruction cycle times the unit of time that equals one machine cycle varies depending on whether the main-system clock (fx) or a sub- system clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 6 - 2 shows corresponding cycle times in microseconds. table 6 - 2. instruction cycle times for cpu clock rates oscillation source selected cpu clock resulting frequency cycle time ( s ) fx = 4.19 mhz fx/64 65.5 khz 15.3 fx/8 524.0 khz 1.91 fx/4 1.05 mhz 0.95 fxt = 32.768 khz fxt/4 8.19 khz 122.0
s3c72h8/p72h8 oscillator circuits 6 - 7 system clock mode register (scmod) the system clock mode register, scmod, is a 4-bit register that is used to select the cpu clock and to control main and sub- system clock oscillation. scmod is mapped to the ram address fb7h. when main-system clock is used as clock source, main-system clock oscillatio n can be stopped by stop instruction or setting scmod.3 (not recommended) . when the clock source is sub-system clock, main-system clock oscillatio n is stopped by setting scmod.3 . scmod.0 , scmod2, and scmod.3 cannot be simultaneously modified. sub-oscillation goes into stop mode only by scmod.2. pcon which revokes stop mode cannot stop the sub-oscillation. the stop of sub-oscillation is released only by reset . reset clears all scmod values to logic zero, selecting the main-system clock (fx) as the cpu clock and start ing clock oscillation. the reset value of the scmod is 0. scmod.3, scmod.2, and scmod.0 bits can be manipulated by 1-bit write instructions (in other words, scmod.0 , scmod.2, and scmod.3 cannot be modified simultaneously by a 4-bit write). bit 1 is always logic zero. fb7h scmod.3 scmod. 2 scmod.1 scmod.0 scmod a sub-system clock (fxt) can be selected as the system clock by manipulating the scmod.3 and scmod.0 bit settings. if scmod.3 = "0" and scmod.0 = "1", the sub-system clock is selected and main-system clock oscillation continues. if scmod.3 = "1" and scmod.0 = "1", fxt is selected, but main-system clock oscillation stops. if you have selected fx as the cpu clock, setting scmod.3 to "1" will stop main-system clock oscillation. but this mode must not be used. to stop main-system clock oscillation safely, main oscillation clock should be stopped only by a stop instruction in main-system clock mode. table 6-3 . system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.2 scmod.0 fx oscillation fx t oscillation cpu clock (note) 0 0 0 on on fx/4, fx/8, fx/64 0 1 0 on off fx/4, fx/8, fx/64 0 0 1 on on fxt/4 1 0 1 off on fxt/4 note: cpu clock is selected by pcon register settings. to decrease stabilization time of sub-oscillator, you can use strong mode. when scmod.1 is set to 0 (default value at reset), strong mode is selected. because the ic consumes a large amount of current during strong mode operation, it is recommended that the strong mode operation should be kept off unless it is otherwise necessary.
oscillator circuits s3c72h8/p72h8 6 - 8 table 6-4 . main/sub oscillation stop mode mode condition method to issue osc stop osc stop release source (2) main oscillation stop mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. stop instruction: main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). interrupt and reset: after releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. and then the cpu operates. oscillation stabilization time is 1 / {256 x bt clock (fx)}. set scmod.3 to ?1? (1) main oscillator stops, halting the cpu operation. sub oscillator still runs (stops). reset: interrupt can?t start the main oscillation. therefore, the cpu operation can never be restarted. main oscillator runs. sub oscillator runs. system clock is the sub oscillation clock. stop instruction: (1) main oscillator stops. cpu is in idle mode. sub oscillator still runs. btoverflow and reset: after the overflow of basic timer [1 / {256 x bt clock (fxt)}], cpu operation and main oscillation automatically start. set scmod.3 to ?1? main oscillator stops. cpu still operates. sub oscillator still runs. set scmod.3 to ?0? or reset sub oscillation stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. set scmod.2 to ?1? main oscillator still runs. cpu operates. sub oscillator stops. set scmod.2 to ?0? or reset main oscillator runs (stops). sub oscillator runs. system clock is the sub oscillation clock. set scmod.2 to ?1? main oscillator still runs (stops). sub oscillator stops, halting the cpu operation. reset notes : 1. this mode must not be used. 2. oscillation stabilization time by interrupt is 1 / (256 x bt clocks). oscillation stabilization time by a reset is 31.3 ms at 4.19 mhz, main oscillation clock.
s3c72h8/p72h8 oscillator circuits 6 - 9 table 6-5 . system operating mode comparison mode condition stop/idle mode start method current consumption main operating mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. ? a main idle mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. idle instruction b main stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. stop instruction d sub operating mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. ? c sub ldle mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. idle instruction d sub stop mode main oscillator is stopped by scmod.3. sub oscillator runs. system clock is the sub oscillation clock. setting scmod.2 to ?1? this mode can be released only by an external reset. e main/sub stop mode main oscillator runs. sub oscillator is stopped by scmod.2. system clock is the main oscillation clock. stop instruction: this mode can be released by an interrupt and reset. e note : the current consumption is: a > b > c > d > e.
oscillator circuits s3c72h8/p72h8 6 - 10 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, de termine whether a main-system or a sub-system clock is selected as the cpu clock, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and sub-system clocks and to modify operating frequencies. scmod.3 , scmod .2, and scmod.0 select the main-system clock (fx) or a sub-system clock (fxt) and start or stop main or sub system clock oscillation. pcon.1 and pcon.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, 64 , or fxt clock by 4. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ? the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main-system clock of fx/64) and you want to switch from the fx clock to a sub-system clock and to stop the main-system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main-system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can then disable main-system clock oscillation by setting scmod.3 to "1". this same ? stepped ? approach must be taken to switch from a sub-system clock to the main-system clock: f irst, clear scmod.3 to "0" to enable main-system clock oscillation. until main osc is stabilized, system clock must not be changed. then, after a certain number of machine cycles has elapsed, select the main-system clock by clearing all scmod values to logic zero. after reset , cpu operation starts with the lowest main-system clock frequency of 15.3 s at 4.19 mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 6-6 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect.
s3c72h8/p72h8 oscillator circuits 6 - 11 table 6-6 . elapsed machine cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 8 machine cycles n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 16 machine cycles n/a fx/4fxt machine cycle pcon.0 = 1 scmod.0 = 1 n/a n/a fx/4fxt (m/c) n/a notes : 1. even if oscillation is stopped by setting scmod.3 during main-system clock operation, the stop mode is not entered. 2. since the x in input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" or stop instruction when an external clock is used as the main-system clock. 3. when the system clock is switched to the sub-system clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 6-6 . 4. ? n/a ? means ? not available ? . 5. fx: main ?system clock, fxt: sub?system clock, m/c: machine cycle. when fx is 4.19 mhz, and fxt is 32.768 khz. + + programming tip ? switching between main-system and sub-system clock 1. switch from the main-system clock to the sub-system clock: ma2sub bits scmod.0 ; switches to sub-system clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main-system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the sub-system clock to the main-system clock: sub2ma bitr scmod.3 ; start main-system clock oscillation call dly80 ; delay 80 machine cycles call dly80 ; delay 80 machine cycles bitr s cmod.0 ; switch to main-system clock ret
oscillator circuits s3c72h8/p72h8 6 - 12 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is ad dressable by 4-bit write instructions only. f d0 h clmod.3 "0" clmod.1 clmod.0 cl mod reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fxx/8, fxx/16, or fxx/64. table 6-7. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64, fxt/4) 1.05 mhz, 524 khz, 65.5 khz 0 1 fxx/8 524 khz 1 0 fxx/16 262 khz 1 1 fxx/64 65.5 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note : assumes that fxx = 4.19 mhz.
s3c72h8/p72h8 oscillator circuits 6 - 13 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? port mode flag ? clo output pin (p3.2) clmod.2 clmod.1 clmod.0 clmod.3 clock selector clocks (fxx/8, fxx/16, fxx/64, cpu clock) 4 p3.2 output latch pm 3.2 clo figure 6- 7. clo output pin circuit diagram clock output procedure the procedure for outputting clock pulses to the clo pin may be summarized as follows: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load "0" to the output latch of the clo pin (p3.2) . 4. set the p3.2 mode flag (pm3.2) to output mode. 5 . enable clock output by setting clmod.3 to logic one.
oscillator circuits s3c72h8/p72h8 6 - 14 + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb smb 15 ld ea,#0 f0 h ld pmg 2 , ea ; p 3.2 ? output mode bitr p 3.2 ; clear p3.2 pin output latch ld a,# 8 h ld clmod,a
s3c72h8/p72h8 interrupts 7 - 1 7 interrupts overview the s3c72h8 interrupt control circuit has five functional components: ? interrupt enable flags (iex) ? interrupt request flags (irqx) ? interrupt master enable register (ime) ? interrupt priority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 7 - 1. interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pins external interrupts int0, int1, int 3 p2.0, p2.1 internal interrupts intb, intt0, int g not applicable quasi-interrupts int2 (ks0?ks3) p6.0 - p6.3 intw not applicable
interrupts s3c72h8/p72h8 7 - 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (intn) are set to logic one: ? interrupt enable flag (iex) ? interrupt master enable flag (ime) ? interrupt request flag (irqx ) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for resets and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the emb and erb flag values before the interrupt is initiat ed are saved along with the pro gram status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction. power-down mode release an interrupt (with the exception of int0) can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
s3c72h8/p72h8 interrupts 7 - 3 no no retain value until iex = 1 retain value until iex = 1 no interrupt is generated (int xx) iex = 1? ime = 1? is1, 0 = 0, 0? is1, 0 = 0, 1? request flag (irqx) 1 generate corresponding vector interrupt and release power-down mode store contents of pc and psw in the stack area; set pc contents to corresponding vector address high-priority interrupt are both interrupt sources of shared vector address used? is1, 0 = 1, 0 retain value until interrupt service routine is completed no irqx flag value remains 1 jump to interrupt start address verify interrupt source and clear irqx with a btstz instruction reset corresponding irqx flag jump to interrupt start address is1, 0 = 0, 1 yes no yes yes yes yes no figure 7 - 1. interrupt execution flowchart
interrupts s3c72h8/p72h8 7 - 4 ie3 ie2 iew iet0 ie1 ie0 ieg ieb intb ks0-ks3 vldout # imod0 imod1 intt0 intw imod3 @ intg ime ipr is1 is0 vector interrupt generator power-down mode release signal interrupt control unit # @ = nosie filtering circuit = edge detection circuit int0 int1 @ irqb irqg irq0 irq1 irqt0 irqw irq3 irq2 imod2 @ @ @ c0out c1out figure 7 - 2. interrupt control circuit diagram
s3c72h8/p72h8 interrupts 7 - 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, w here either all inter rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 7- 3). whenever an interrupt request is accepted, is1 and is0 are incremented by one and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). high level interrupt generated normal program processing (status 0) set ipr int enable int disable high or low level interrupt processing (status 1) only highest level interrupt processing (status 2) low or high level interrupt generated figure 7 - 3. two-level interrupt handling
interrupts s3c72h8/p72h8 7 - 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed by manipulating the interrupt status flags, is0 and is1 while a high-priority inter rupt is being serviced (see table 7- 2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low - priority requests can be serviced in parallel (see figure 7- 4). table 7- 2. is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of i s x bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? normal program processing (status 0) low or high level interrupt generated int enable low or high level interrupt generated set ipr int disable int disable modify status int enable high level interrupt generated single interrupt status 0 status 0 3-level interrupt status 2 2-level interrupt status 1 status 1 figure 7 - 4. multi-level interrupt handling
s3c72h8/p72h8 interrupts 7 - 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7- 3. standard interrupt priorities the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag (mapped fb2h.3) can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 7- 4. interrupt priority register settings note : during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in table 7- 3 (the default priority assigned by hardware when the lower three ipr bits = "0"). in this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. then, when the high-priority interrupt is returned from its service routine by an iret instruction, the inhibited service routine is started. interrupt default priority intb 1 int0 2 int1 3 int g 4 intt0 5 int3 6 ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb interrupts at highest priority 0 1 0 process int0 interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 0 process int g interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process int 3 interrupts at highest priority
interrupts s3c72h8/p72h8 7 - 8 + + programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0 and 1 mode registers (imod0 and imod1 ) the following components are used to process external interrupts at the int0 and int1 pins: ? noise filtering circuit for int0 ? edge detection circuit ? two mode registers, imod0, imod1 respectively the mode registers are used to control the triggering edge of the input signal. imod0 and imod1 settings let you choose either the rising or falling edge of the incoming signal as the int0 and int1 pins as the interrupt request trigger. fb4h imod0.3 "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 imod0 and imod1 registers are mapped to ram addresses fb4h (imod0), fb5h (imod1) respectively, and are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7- 5. imod0 and imod 1 register organization imod0 imod0.3 "0" imod0.1 imod0.0 effect of imod0 settings 0 select cpu clock for sampling 1 select fxx/64 sampling clock 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 "0" "0" "0" imod1.0 effect of imod1 settings 0 rising edge detection 1 falling edge detection
s3c72h8/p72h8 interrupts 7 - 9 external interrupt 0 and interrupt 1 mode registers (c ontinued ) when a sampling clock rate of fxx/64 is used for int0, an interrupt request flag must be cleared before 16 ma chine cycles have elapsed. since the int0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: ? to trigger an interrupt, the input signal width at int0 must be at least two times wider than the pulse width of the clock se lected by imod0. this is true even when the int0 pin is used for general-purpose input. edge detector imod1 irq1 irq0 imod0 clock selector noise filter int1 (p2.1) int0 (p2.0) cpu clock fxx/64 edge detector figure 7- 5. circuit diagram for int0 and int1 pins when modifying the imod registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrupts with an ei instructions.
interrupts s3c72h8/p72h8 7 - 10 external interrupt 2 mode register (imod2 ) t he mode register for external interrupt 2 at the k s 0 ? ks3 pins, imod2 , is addressable only by 4-bit write instructions. reset clears all imod2 bits to logic zero. fb6h imod2.3 imod2 .2 imod 2 .1 imod2 .0 if a falling edge is detected at any one of the selected k s pin by the imod2 register, the irq 2 flag is set to logic one and a release signal for power-down mode is generated. table 7- 6. imod 2 register organization imod2 imod2.3 imod 2 .2 imod 2 .1 imod 2 .0 effect of imod2 settings 0 disable int2 at falling edge of ks0 (p6.0) 1 enable int2 at falling edge of ks0 (p6.0) 0 disable int2 at falling edge of ks1 (p6.1) 1 enable int2 at falling edge of ks1 (p6.1) 0 disable int2 at falling edge of ks2 (p6.2) 1 enable int2 at falling edge of ks2 (p6.2) 0 disable int2 at falling edge of ks3 (p6.3) 1 enable int2 at falling edge of ks3 (p6.3)
s3c72h8/p72h8 interrupts 7 - 11 ks3 ks2 ks1 ks0 imod2 falling edge detection circuit irq2 p6.0 p6.1 p6.2 p6.3 4 figure 7 -6 . int 2 circuit diagram for ks0-ks3
interrupts s3c72h8/p72h8 7 - 12 external interrupt 3 mode register (imod3 ) imom3 is addressable only by 8-bit write instructions reset clears all imod3 bits to logic zero. fb 8 h .7 .6 .5 .4 .3 .2 .1 .0 if the set condition is occurred, the irq3 flag is set to logic one and a release signal for power-down mode is generated . table 7-7 . imod 3 register organization imod3 0 0 .5 .4 .3 .2 .1 .0 effect of imod3 settings 0 0 disable int3 at cldout (cldcon.3) 0 1 enable int3 at falling edge of cldout (cldcon.3) 1 0 enable int3 at rising edge of cldout (cldcon.3) 1 1 enable int3 at falling/rising edge of cldout (..) 0 0 disable int3 at c0out (cmpcon.1) 0 1 enable int3 at falling edge of c0out (cmpcon.1) 1 0 enable int3 at rising edge of c0out (cmpcon.1) 1 1 enable int3 at falling/rising edge of c0out (..) 0 0 disable int3 at c1out (cmpcon.3) 0 1 enable int3 at falling edge of c1out (cmpcon.3) 1 0 enable int3 at rising edge of c1out (cmpcon.3) 1 1 enable int3 at falling/rising edge of c1out (..) vldout (vldcon.3) irq3 noise filter noise filter noise filter c0out (cmpcon.1) c1out (cmpcon.3) imod3 8 figure 7 -7 . int 3 circuit diagram for vldcon.3, cmpcon.1, .3
s3c72h8/p72h8 interrupts 7 - 13 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable f lags that correspond to each in terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3). it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). interrupt enable flags (iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 7-8 . interrupt enable and interrupt request flag addresses notes: 1. iex refers to corresponding interrupt enab le flags. 2. irqx refers to corresponding interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode. ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts address bit 3 bit 2 bit 1 bit 0 fb8h 0 0 ieb irqb fbah 0 0 iew irqw fbbh 0 0 ie3 irq3 fbch 0 0 iet0 irqt0 fbdh 0 0 ie g irqg fbeh ie1 irq1 ie0 irq0 fbfh 0 0 ie2 irq2
interrupts s3c72h8/p72h8 7 - 14 interrupt request flags (irqx) interrupt request flags are read/write addressable by 1-bit or 4-bit in structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated. when two interrupts share the same service routine start address, interrupt processing may occur in one of two ways: ? when only one interrupt is enabled, the irqx flag is cleared automatically when the interrupt has been serviced. ? when two interrupts are enabled, the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request. in this case, the irqx setting must be cleared manually using a btstz instruction. table 7-9 . interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 int g i completion signal for gate open time 4 irq g intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 int3 e suitable set condition for vld, comparator 5 irq3 int2 (note) (ks0-ks3) e falling edge detected at ks0-ks3 ? irq2 intw i time interval of 1s, 0.5 s, 0.25s or 3.19 ms ? irqw note : the quasi-interrupt int2 is only used for testing incoming signals.
s3c72h8/p72h8 power-down 8 - 1 8 power-down overview the s3c72h8 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mod e, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in main stop mode, main system clock oscillation is halted (assuming main clock is selected as system clock and it is currently operating), and peripheral hard ware components are powered-down. in sub stop mode, (assuming sub clock is selected) sub system clock oscillation is halted by setting scmod.2 to ?1?. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, timer/ counter 0, watch timer, and lcd controller , serial i/o ? and on external interrupt requests, is detailed in table 8- 1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or main stop modes are terminated either by a reset , or by an interrupt which is enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset , a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. sub stop mode can be terminated by reset only. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution starts immediately after the instruction issuing a request to enter power-down mode is executed. the interrupt request flag remains set to logical one. ? if the ime flag = "1", two instructions are executed after the power-down mode release and the vectored interrupt is then initiated. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = "0" condition. assuming that both interrupt enable flag and interrupt request flag are set to "1", the release signal is generated when power-down mode is entered.
power-down s3c72h8/p72h8 8 - 2 table 8- 1. hardware operation during power-down modes mode main stop sub stop main/sub stop idle system clock main clock (fx) sub clock (fxt) main clock (fx) (1) main (fx) or sub clock (fxt) instruction stop setting scmod.2 to ?1? stop idle clock oscillator main clock oscillation stops sub clock oscillation stops main clock oscillation stops only cpu clock stops. (2) basic timer basic timer stops. basic timer stops. basic timer stops. basic timer operates. timer/counter 0 operates only if tcl0 is selected as counter clock. operates only if tcl0 is selected as counter clock. operates only if tcl0 is selected as counter clock. timer/counter 0 operates. watch timer operates only if sub clock (fxt) is selected as counter clock. watch timer stops. watch timer stops. watch timer operates. lcd controller operates only if sub clock (fxt) is selected as lcd clock, lcdck. lcd controller stops. lcd controller stops. lcd controller operates. external interrupts int1 and int2 are acknowledged; int0 is not serviced. int0, int1, and int2 is not serviced. int1 and int2 are acknowledged; int0 is not serviced. int1 and int2 are acknowledged; int0 is not serviced. (3) cpu all cpu operations are disabled. mode release signal interrupt request signals (except int0) pre-enabled by iex or reset input. only reset input interrupt request signals (except int0) pre-enabled by iex or reset input. notes: 1. sub clock stops by setting scmod.2 to ?1?. 2. main and sub clock oscillation continues. 3. if imod0.3 is set to 1 (select fxx/64 sampling clock), int0 can be serviced.
s3c72h8/p72h8 power-down 8 - 3 idle mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset idle instruction normal mode idle mode normal mode clock signal normal oscillation figure 8- 1. timing when idle mode is released by reset clock signal normal oscillation mode release signal idle instruction interrupt acknowledge (ime = 1) normal mode idle mode normal mode figure 8- 2. timing when idle mode is released by an interrupt
power-down s3c72h8/p72h8 8 - 4 stop mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset stop instruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes figure 8- 3. timing when stop mode is released by reset oscillator stabilization wait time (bmod setting) stop instruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes mode release signal int ack(lme=1) figure 8- 4. timing when main stop or main/sub stop mode is release by an interrupt
s3c72h8/p72h8 power-down 8 - 5 + + programming tip ? reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main system clock to a subsystem clock and the lcd display is turned on: keyclk di call ma2sub ; main system clock ? subsystem clock switch subroutine smb 15 ld ea,#0h ld p 3 ,ea ; all key strobe outputs to low level ld a,# 0f h ld imod2 ,a ; select k s 0?k s3 enable smb 0 bitr irqw bitr irq 2 bits iew bits ie2 clks1 call watdis ; execute clock and display changing subroutine btstz irq2 jr cidle call sub2ma ; subsystem clock ? main system cl ock switch subroutine ei ret cidle idle ; engage idle mode nop nop nop jps clks1 note you must program at least three nop instructions after idle and stop instructions, to avoid flowing of leakage current due to the floating state in the internal bus.
power-down s3c72h8/p72h8 8 - 6 port pin configuration for power-down the following method describes how to configure i/o port pins to reduce power consumption during power-down modes (stop, idle): condition 1: if the microcontroller is not configured to an external device: 1. connect unused port pins accordi ng to the information in table 8- 2. 2 . disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. condition 2: if the microcontroller is configured to an external device and the external device's v dd source is turned off in power-down mode. 1. connect unused port pins according to the information in table 8- 2. 2 . dis able pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. 3 . disable the pull-up resistors of input pins connected to the external devi ce by making the necessary modi fications to the pumod register. 4 . configure the output pins that are connected to the external device to low level. reason: when the external device's v dd source is turned off, and if the microcontroller's output pins are set to high level, v dd ? 0.7 v is supplied to the v dd of the external device through its input pin. this causes the device to operate at the level v dd ? 0.7 v. in this case, total current consumption would not be reduced. 5 . determine the correct output pin state necessary to block current pass in a ccording with the external tran sistors (pnp, npn).
s3c72h8/p72h8 power-down 8 - 7 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8-2 . table 8-2 . unused pin connections for reduc ing power consumption pin/share pin names recommended connection p0.0/ extref p0.1 p0.2 input mode: connect to v dd output mode: no connection p 2.0/int0 p2.1/int1 p2.2/tcl0 p2 .3 /fcl connect to v dd output mode: no connection p 3 .0 /tclo0 p3.1/btco p3.2/clo p3 .3 /buz input mode: connect to v dd output mode: no connection p4.0/c0p p4.1/c0n p4.2/c0out p4.3/c1out input mode: connect to v dd output mode: no connection p5.0/c1p p5.1/c1n input mode: connect to v dd output mode: no connection p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 input mode: connect to v dd output mode: no connection seg0? seg25 com0? com3 no connection ca, cb no connection v lc0 ?v lc2 no connection x t in connect xt in to v ss (set scmod.2 to ?1?) x t out no connection test connect to v ss
s3c72h8/p72h8 reset reset 9 - 1 9 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 9 - 1. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y oscillator stabilization (31.3 ms/4.19 mhz) normal mode operating mode idle mode reset operation normal mode or power-down mode reset input figure 9 - 1. timing for oscillation stabilization after reset
reset reset s3c72h8/p72h8 9 - 2 hardware register values after reset table 9 - 1 gives you detailed information about hardware register values after a reset occurs during power-down mode or during normal operation. table 9 - 1. hardware register values after reset hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation program counter (pc) lower five bits of address 0000h are transferred to pc 12- 8, and the contents of 0001h to pc7 - 0. lower five bits of address 0000h are transferred to pc1 2- 8, and the contents of 0001h to pc7 - 0. program status word (psw): carry flag (c) retained undefined skip flag (sc0?sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): working registers e, a, l, h, x, w, z, y values retained undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0?bsc3) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 system clock control reg (scmod) 0 0 interrupts: interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 int 3 mode register (imod3 ) 0 0
s3c72h8/p72h8 reset reset 9 - 3 table 9 - 1. hardware register values after reset (continued) hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation i/o ports; output buffers off off output latches 0 0 port mode flags (pm) 0 0 pul l-up resistor mode reg (pumod ) 0 0 port n-ch open drain reg (pne) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 output enable flags (boe) 0 0 timer/counters 0 count registers (tcnt0) 0 0 reference registers (tref0) ffh ffh mode registers (tmod0) 0 0 output enable flags (toe0) 0 0 frequency counters : counter registers (fcnth/l) 0 0 mode registers (fcmod) 0 0 watch dog timer: wdt mode register (wdmod) a5h a5h wdt clear flag (wdtcf) 0 0 watch timer: watch timer mode register (wmod) 0 0 lcd driver/controller: lcd mode register (lmod) 0 0 lcd control register (lcon) 0 0 display data memory values retained undefined output buffers off off comparator : comparator mode register (cmod) 0 0 comparator control reg (cmpcon) 0 0 voltage level detector : vld control register (vldcon) 0 0
s3c72h8/p72h8 i/o ports 10 - 1 10 i/o ports overview the s3c72h8 h as 6 ports. there are total of 21 configurable i/o pins. pin addresses for all ports are mapped to bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. port mode flags port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod) are used to assign internal pull-up resistors by software to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting (except p4, p5) . n-channel open-drain mode register (pne) the n-channel, open-drain, mode register (pne) is used to configure outputs as n-channel open-drain outputs or as push-pull outputs.
i/o ports s3c72h8/p72h8 10 - 2 table 10- 1. i/o port overview port i/o pins pin names address function description 0 i/o 3 p0.0 - p0. 2 ff0h 3-bit i/o port. 1-bit and 4-bit read/write and test is possible. port 0 is software configurable as input or output. 3 -bit pull-up res istors are software assignable. 2 i/o 4 p2.0 - p2.3 ff2h 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable. 3 i/o 4 p3.0 - p3.3 ff3h same as port2. port2 and 3 can be addressed by 1-, 4-, and 8- bit read/write and test instruction 4 , 5 i/o 6 p4.0 -p4.3 p5.0-p5.1 ff4h ff5h 4/2-bit i/o ports. n-channel open-drain or push-pull output. 1-, 4-, and 8-bit read/write and test is possible. ports 4 and 5 can be paired to support 8-bit data transfer. pull-up resistors are assignable to port unit by software control. 6 i/o 4 p6.0-p6.3 ff6h 4-bit i/o port. port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. table 10- 2. port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c, p 2 .3 a, p 2 ea, p 2 input or test data at each pin input or test data at output latch 1-bit output bitr p2.3 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2, a p2 , ea transfer accumulator data to the output latch transfer accumulator data to the output pin
s3c72h8/p72h8 i/o ports 10 - 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. for convenient program reference, pm flags are organized into two groups ? pmg 0 and pmg 1 as shown in table 10- 3. they are addressable by 8-bit write instructions only. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logical zero, automatically configuring the corresponding i/o ports to input mode. table 10- 3. port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg 0 fe6 h pm2.3 pm2.2 pm2.1 pm2.0 fe7 h pm3.3 pm3.2 pm3.1 pm3.0 pmg1 fe8 h pm5 pm4 extref (p0.0) pm0 fe9 h pm6.3 pm6.2 pm6.1 pm6.0 noet: if bit = ?0? the corresponding i/o pin is set to input mode. if bit = ?1?, the pin is set to output mode. all flags are cleared to ?0? following reset. when the pmg1.1 is set, p0.0/extref pin is assigned as external reference input mode and pull-up resistor, p0.0 input and output circuit is disabled. + + programming tip ? configuring i/o ports to input or output configure ports 2 and 3 as an output port: bits emb smb 15 ld ea,# 0f fh ld pmg0,ea ; p2 and p3 ? output pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod) are used to assign int ernal pull-up resistors by soft ware to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod is addressable by 8-bit write instructions only. reset clears pumod register values to logic zero, automatically disconnecting all software-assignable port pull-up resistors. table 10- 4. pull-up resistor mode register (pumod) organization address bit 3 bit 2 bit 1 bit 0 fdch pur3 pur2 ?0? pur0 fddh ?0? pur6 pur5 pur4 note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pu mod.0 for port 0 , pu mod.2 for port 2 and so on.
i/o ports s3c72h8/p72h8 10 - 4 + + programming tip ? enabling and disabling i/o port pull- u p resistors p2 and p3 are enabled to be pull-up resistors. bits emb smb 15 ld ea,#0ch ld pumod ,ea ; enable the pull-up resistors of p2 and p3 n-channel open-drain mode register (pne) the n-channel open-drain mode register , pne , is used to configure port4, 5 to n-channel open-drain or push-pull modes . when a bit in the pne register is set to "1", the corresponding output pin is configured to n-channel open-drain; when set to "0", the output pin is configured to push-pull mode . the pne register consists of an 8-bit register , as shown below, pne can be addressed by 8-bit write instructions only. table 10-5. n-channel open drain mode register (pne) setting id address bit 3 bit 2 bit 1 bit 0 pne fd6h pne.3 (p4.3) pne.3 (p4.2) pne.3 (p4.1) pne.3 (p4.0) fd7h ? ? pne.3 (p5.1) pne.3 (p5.0) bit setting description 0 c-mos push-pull output mode. 1 n-ch open drain output mode.
s3c72h8/p72h8 i/o ports 10 - 5 comparator mode register (cmod) the comparator mode register, cmod, is used to port 4,5 to normal i/o ports or comparator i/o. when a bit of the cmod register is set to ?1? , the corresponding i/o pin is configured to comparator i/o; when set to ?0?, the i/o pin is configured to normal i/o. the cmod register consists of an 4-bit register, as shown below, cmod can be addressed by 4-bit read/write instructions only. fe0 h cmod.3 cmod.2 cmod.1 cmod.0 cmod cmod.3 cmod.2 cmod.1 cmod.0 effect of cmod settings 0 select p4.0/c0p, p4.1/c0n as normal i/o ports 1 select p4.0/c0p, p4.1/c0n as comparator inputs 0 select p4.2/c0out as a normal i/o port 1 select p4.2/c0out as a output 0 select p5.0/c1p, p5.1/c1n as normal i/o port 1 select p5.0/c1p, p5.1/c1n as comparator input 0 select p4.3/c1out as a normal i/o port 1 select p4.3/c1out as a comparator output note: when bit ?1?, a pull-up resistor, output and input circuit to the corresponding i/o port: p4 and p5 are disabled for comparator own operation.
i/o ports s3c72h8/p72h8 10 - 6 port 0 circuit diagram pumod.0 1,4 pm0 note: p0.3 is always read as an zero, 0. v dd output latch p0.0/extref p0.1 p0.2 1,4 output latch pmg1.1 to voltage level detector figure 10- 1. port 0 circuit diagram
s3c72h8/p72h8 i/o ports 10 - 7 port 2 circuit diagram v dd output latch mux 1, 4 1, 4 p2.0/int0 p2.1/int1 p2.2/tcl0 p2.3/fcl n/r is indicated to noise reduction circuit. note: pm2.0 pm2.1 pm2.2 pm2.3 pumod.2 n/r to int0 to int1 to tc0 to fc figure 10- 2. port 2 circuit diagram
i/o ports s3c72h8/p72h8 10 - 8 port 3 circuit diagram output latch mux 1, 4 1, 4 p3.0/tclo0 p3.1/btco p3.2/clo p3.3/buz v dd n/r is indicated to noise reduction circuit. note: pm3.0 pm3.1 pm3.2 pm3.3 pumod.3 figure 10- 3. port 3 circuit diagram
s3c72h8/p72h8 i/o ports 10 - 9 port 4 circuit diagram c0out mux 1, 4 1, 4 p4.0/c0p p4.1/c0n p4.2/c0out v dd pm4 pumod.4 cmod.1/.0 c0p c0n output latch p4.3/c1out c1out cmod.3 cmod.2 pne.3-.0 c-mos push-pull or n-ch open drain figure 10- 4. port 4 circuit diagram note : when the corresponding bit of cmod is ?1?, each pin is configured to comparator pin, a pull-up resistor, output and input circuit to the corresponding i/o port: p4.0, p4.1 are disabled for comparator own operation.
i/o ports s3c72h8/p72h8 10 - 10 port 5 circuit diagram pumod.5 1,2 pne.5-.4 v dd output latch 1,2 mcu c1p p5.0/c1p p5.1/c1n cmod c1n pm5 figure 10-5 . port 5 circuit diagram note : when the corresponding bit of cmod is ?1?, each pin is configured to comparator pin, a pull-up resistor, output and input ci rcuit to the corresponding i/o port: p5 is disabled for comparator own operation.
s3c72h8/p72h8 i/o ports 10 - 11 port 6 circuit diagram output latch mux 1, 4 1, 4 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 v dd pm6.0 pm6.1 pm6.2 pm6.3 pumod.6 figure 10-6 . port 6 circuit diagram
s3c72h8/p72h8 timer s and counter 11 - 1 11 timer s and counter overview the s3c72h8 microcontroller has four timer and timer/counter modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter (tc0) ? 16 -bit frequency counter ( fc ) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer. it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. when the contents of the basic timer counter register bcnt overflows, a pulse is output to the basic timer output pin, btco. the basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset. the 8-bit timer/counter (tc0) is programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. the 16-bit frequency counter(fc) is an up-counter that is used primarily for event counting of comparator output or fcl input. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. it also generates a clock signal for the lcd controller.
timers and counter s3c72h8/p72h8 11 - 2 basic timer and watch dog timer(bt & wdt) overview the 8-bit basic timer (bt) and 3-bit watch dog timer(wdt) has five functional components: ? clock selector logic ? 4-bit mode register (bmod) ? 8-bit counter register (bcnt) ? 3-bit counter register (wdcnt) ? 8-bit mode register (wdmod) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. the pulses are inputted to watch dog timer's counter when an overflow occurs in the counter register bcnt. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset. bit settings in the basic timer mode register bmod turns the bt module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. interval timer function the basic timer's primary function is to measure elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. to restart the basic timer, one bit setting is required: bit 3 of the mode register bmod is set to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2 - bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs (255). an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to detects an undefined program loop, that is, system or program operation error. for this purpose, instruction that clears the watch-dog timer(bits wdtcf) within a given period should be executed at proper time in a program. if an instruction that clears the watch-dog timer is not done within the period and the watch-dog timer overflows, reset signal is generated and system is restarted with reset status. an operation of watch-dog timer is as follows: ? write some value(except #5ah) to watch-dog timer mode register, wdmod. ? each time bcnt overflows, an overflow signal is sent to the watch-do g timer counter, wdcnt. ? if wdcnt overflows, system reset is generated. oscillation stabilization interval control bits 2-0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as wait time) required to stabilize clock signal oscillation when power-down mode is released by an interrupt. when a reset signal is input, the standard stabilization interval for system clock oscillation following the reset is 31.3 ms at 4.19 mhz.
s3c72h8/p72h8 timer s and counter 11 - 3 table 11- 1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or reset 4-bit f85h 4-bit write-only; bmod.3: 1-bit write-only ? 0 ? bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h - f87h 8-bit read-only ?u? (note) wdmod control controls watchdog timer operation. 8-bit f98h-f99h 8-bit write-only a5h wdtcf control clear the watchdog timer?s counter. 1-bit f9ah.3 1-bit write-only ?0? note: ?u? means that the value is undetermined after a reset . wait c reset bits instruction wdtcf delay clear stop bmod.3 bmod.2 bmod.1 bmod.0 bits instruction overflow clear bcnt "clear" signal interrupt request clear irqb release signal (by interrupts ) reset clock selector wdcnt wdmod reset gen 8 8 bcnt irqb 1-bit r/w clock input 4 (by internal reset ) boe p3.1 pm3.1 btco wait means stabilization time after reset or stabilization time after stop mode release. notes: bit 5 figure 11- 1. bt and wdt block diagram
timers and counter s3c72h8/p72h8 11 - 4 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer; ? control the frequency of clock signal input to the basic timer; ? determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fxx/2 12 to fxx/2 5 , are se lectable. since bmod's reset value is logic zero, the default clock frequency setting is fxx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determines the clock input frequency and oscillation stabilization interval. table 11- 2. basic timer mode register (bmod) organization bmod.3 basic timer restart bit 1 restart basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock interval time 0 0 0 fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 0 1 1 fxx/2 9 (8.18 khz) 2 17 /fxx (31.3 ms) 1 0 1 fxx/2 7 (32.7 khz) 2 15 /fxx (7.82 ms) 1 1 1 fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes : 1. clock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 mhz. 2. fxx = selected system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column ?oscillation stabilization? can also be interpreted as "interrupt interval time." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
s3c72h8/p72h8 timer s and counter 11 - 5 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incremented to hexadecimal ? ffh ? (255 clock pulses), it is cleared to ? 00h ? and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting with incoming clock signal. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set counter buffer bit (bmod.3) to logic o ne to restart the basic timer. 2. bcnt is then incremented by one per each clock pulse corresponding to bmod selection. 3. bcnt overflows if bcnt = 255 (bcnt = ffh). 4. when an overflow occurs, the irqb flag is set by hardware to logic one. 5. the interrupt request is generated. 6. bcnt is then cleared by hardware to logic zero. 7. basic timer resumes counting clock pulses. b t output enable flag (boe) the basic timer output enable flag boe controls output from basic timer to the btco pin. boe is mapped to ram location f92h.1 and is addressable by 1-bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92 h 0 toe0 boe 0
timers and counter s3c72h8/p72h8 11 - 6 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms at 4.19 mhz : bits emb smb 15 ld a,#0bh ld bmod,a ; wait time i s 31.3 ms nop stop ; get into stop for power-down mode nop nop nop cpu operation stop instruction stop mode is released by interrupt normal operating mode stop mode idle mode normal operating mode (31.3 ms) 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
s3c72h8/p72h8 timer s and counter 11 - 7 watchdog timer mode register (wdmod) the watchdog timer mode register, wdmod, is a 8-bit write-only register located at ram address f98h?f99h. wdmod register controls to enable or disable the watchdog function. wdmod values are set to logic ?a5h? following reset and this value enables the watchdog timer, and watchdog timer is set to the longest interval because bt overflow signal is generated with the longest interval. wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function watchdog timer counter (wdcnt) the watchdog timer counter, wdcnt, is a 3-bit counter. wdcnt is automatically cleared to logic zero, and restarts whenever the wdtcf register control bit is set to ?1?. reset , stop, and wait signal clears the wdcnt to logic zero also. wdcnt increments each time a clock pulse of the overflow frequency determined by the current bmod bit setting is generated. when wdcnt has incremented to hexadecimal ?07h?, it is cleared to ?00h? and an overflow is generated. the overflow causes the system reset . watchdog timer counter clear flag (wdtcf) the watchdog timer counter clear flag, wdtcf, is a 1-bit write instruction. when wdtcf is set to one, it clears the wdcnt to zero and restarts the wdcnt. wdtcf register bits 2?0 are always logic zero. table 11-3. watchdog timer interval time bmod bt input clock (frequency) wdcnt input clock (frequency) wdt interval time main clock sub clock x000b fxx/2 12 fxx/(2 12 2 8) fxx/2 12 2 8 2 3 2 sec 256 sec x011b fxx/2 9 fxx/(2 9 2 8) fxx/2 9 2 8 2 3 250 ms 32 sec x101b fxx/2 7 fxx/(2 7 2 8) fxx/2 7 2 8 2 3 62.5 ms 8 sec x111b fxx/2 5 fxx/(2 5 2 8) fxx/2 5 2 8 2 3 15.6 ms 2 sec notes: 1. clock frequencies assume a system oscillator clock frequency (fxx) of: 4.19 mhz main clock or 32.768 khz sub clock 2. fxx = system clock frequency. 3. if the wdmod changes such as disable and enable, you must set wdtcf flag to ?1? for starting wdcnt from zero state.
timers and counter s3c72h8/p72h8 11 - 8 + + programming tip ? using the watchdog timer reset di bits emb smb 15 ld ea,#00h ld sp,ea ld a,#0dh ; wdcnt input clock is 7.82 ms ld bmod,a main bits wdtcf ; m ain routine operation period must be shorter than ; watchdog ; timer?s period jp main
s3c72h8/p72h8 timer s and counter 11 - 9 8-bit timer/counter 0 (tc0) overview timer/counter 0 (tc0) is used to count system ? events ? by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod0 register during program execution. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre - quency. external event counter counts various system "events" based on edge detection of external clock sig - nals at the tc0 input pin, tcl0. to start the event counting operation, tmod0.2 is set to "1" and tmod0.6 is cleared to "0". arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external clock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin.
timers and counter s3c72h8/p72h8 11 - 10 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired number of clock pulses between in - terrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output latch (tol0) where a tc0 clock pulse is stored pending output to the tc0 output pin, tclo0. when the contents of the tcnt0 and tref0 registers coincide, the timer/counter interrupt request flag (irqt0) is set to "1", the status of tol0 is inverted, and an interrupt is generated. output enable flag (toe0) must be set to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) cleared when tc0 operation starts and the tc0 interrupt service routine is executed and enabled whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter 0.
s3c72h8/p72h8 timer s and counter 11 - 11 table 11-4 . tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h - f91h 8-bit write-only; (tmod0.3 is also 1-bit write able) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h - f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h - f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1-bit f92h.2 1-bit write-only "0" to l0 latch where a clock pulse is stored pending out. 1-bit f9 3h.1 1-bit write-only "0" clear set clear inverted clocks (fxx/2 10 , fxx/2 6 , fxx/2 4 , fxx) tcl0 clear clock selector tcnt0 tref0 8 8 8-bit comparator irqt0 tol0 p3.0 latch toe0 pm3.0 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 8 tclo0 figure 11- 2. tc0 circuit diagram
timers and counter s3c72h8/p72h8 11 - 12 tc0 enable/disable procedure enable timer/counter 0 ? set tmod0.2 to logic one ? set the tc0 interrupt enable flag iet0 to logic one ? set tmod0.3 to logic one tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 0 ? set tmod0.2 to logic zero clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary.
s3c72h8/p72h8 timer s and counter 11 - 13 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to program timer/counter 0 to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fxx) and load a counter reference value into the tref0 register. tcnt0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod0.4?tmod0.6 settings. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. the interrupt request mechanism for tc0 includes an interrupt enable flag (iet0) and an interrupt request flag (irqt0). tc0 operation sequence the general sequence of operations for using tc0 can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0. 2. set tmod0.6 to "1" to enable the system clock (fxx) input. 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fxx/2 n ). 4. load a value to tref0 to specify the interval between interrupt requests. 5. set the tc0 interrupt enable flag (iet0) to "1". 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0, and start counting. 7. tcnt0 increments with each internal clock pulse. 8. when the comparator shows tcnt0 = tref0, the irqt0 flag is set to "1" and an interrupt request is generated. 9. output latch (tol0) logic toggles high or low. 10. tcnt0 is cleared to 00h and counting resumes. 11. programmable timer/counter operation continues until tmod0.2 is cleared to "0".
timers and counter s3c72h8/p72h8 11 - 14 tc0 event counter function timer/counter 0 can monitor or detect system ? events ? by using the external clock input at the tcl0 pin as the counter source. the tc0 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod0.4?tmod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enable tc0; ? clear tmod0.6 to "0" to select the external clock source at the tcl0 pin; ? select tcl0 edge dete ction for rising or falling signal edges by loading the appropriate values to tmod0.5 and tmod0.4. table 11-5 . tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges
s3c72h8/p72h8 timer s and counter 11 - 15 tc0 clock frequency output using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to select the clock frequency, load the appropriate values to the tc0 mode register, tmod0. the clock interval is selected by loading the desired reference value into the reference register tref0. to enable the output to the tclo0 pin, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" ? i/o mode flag for p3.0 must be set to output mode ("1") ? output latch value for p3.0 must be set to "0" in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load a refere nce value to tref0. 2. set the internal clock frequency in tmod0. 3. initiate tc0 clock output to tclo0 (tmod0.2 = "1"). 4. s et p3.0 mode flag to "1". 5. clear p3.0 output latch to "0". 6. set toe0 flag to "1". each time tcnt0 overflows and an interrupt request is generated, the state of the output latch tol0 is in verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#10 h ld pmg1,ea ; p3.0 ? output mode bitr p3.0 ; clear p 3.0 output latch bits toe0
timers and counter s3c72h8/p72h8 11 - 16 tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the tref0 register. 2. clear tmod0.6 to "0" to enable external clock input at the tcl0 pin. 3. set tmod0.5 and tmod0.4 to desired tcl0 signal edge detection. 4. set port 3.0 mode fl ag (pm3.0 ) to output ("1"). 5. clear p3.0 output latch to "0". 6. set toe0 flag to "1" to enable output of the divided frequency to the tclo0 pin + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divided by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,#10 h ld pmg1,ea ; p3.0 ? output mode bitr p3.0 ; clear p 3.0 output latch bits toe0
s3c72h8/p72h8 timer s and counter 11 - 17 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. it is located at ram addresses f90h-f91h and is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. the tmod0.6, tmod0.5, and tmod0.4 bit settings are used together to select the tc0 clock source. this selection involves two variables: ? synchronization of timer/counter operations with either the rising edge or the falling edge of the clock sig nal input at the tcl0 pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc0 operation. table 11-6. tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero tmod0.6 f91h tmod0.5 0,1 specify input clock edge and internal frequency tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) tmod0.2 0 disable timer/counter 0; retain tcnt0 contents f90h 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero
timers and counter s3c72h8/p72h8 11 - 18 table 11-7 . tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx /2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx (4.19 m hz ) note : ? fxx ? = selected system clock of 4.19 mhz. + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
s3c72h8/p72h8 timer s and counter 11 - 19 tc0 counter register (tcnt0) the 8-bit counter register for timer/counter 0, tcnt0, is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 is enabled, tcnt0 is cleared to logic zero and counting resumes. tcnt0 register value is incremented at the selected edge each time an incoming pulse with reference clock specified by tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4) is input. each time tcnt0 is incremented, the new value is compared with the referenc e value stored in the tc0 refer ence buffer, tref0. when tcnt0 = tref0, an match signal occurs in the comparator , the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock tref0 tcnt0 ~ ~ interval time tol0 timer start instruction (tmod0.3 is set) irqt0 set irqt0 set 1 2 n-1 0 1 2 n-1 0 1 2 3 match match ~ ~ figure 11- 3. tc0 timing diagram
timers and counter s3c72h8/p72h8 11 - 20 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register. it is addressable by 8-bit ram control instructions. reset initializes the tref0 value to ? ffh ? . tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting (tref0 value 1 0) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is mapped to ram location f92h.2 and is addressable by 1-bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h 0 toe0 boe 0 when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling tc0 output. tc0 output latch (tol0) tol0 is the output latch for timer/counter 0. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 buffer, the tol0 value is inverted the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin at i/o port 3.0. assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irqt0, and counting resumes immedi ately. when tc0 is disabled (tmod0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary. bit 3 bit 2 bit 1 bit 0 f93h 0 0 tol0 0
s3c72h8/p72h8 timer s and counter 11 - 21 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume t he tc0 counter clock = fxx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
timers and counter s3c72h8/p72h8 11 - 22 16-bit frequency counter (fc) overview the 16-bit frequency counter (fc) has three functional components: ? 8-bit mode register (fcmod) ? 16-bit counter register (fcnt) ? gate control logic the frequency counter measures the input frequency at precise intervals. the pulses are inputted to frequency counter during a gate is opened. the gate control circuit, which controls the frequency counting time, is programmed using the fcmod register. six different gate time can be selected using fcmod register setting. during gate time, the 16-bit fc counts the input frequency at the fcl, c0out, or c1out pins. the counting input for the 16-bit frequency counter is selected by fcmod register. the 16-bit binary counter(fcnth - fcntl) can be read by an 8-bit ram control instruction only. by setting fcmod register, the gate is opened for the selected periods and gate flag is cleared. during the open period of the gate, input frequency is counted by the 16-bit counter. when the gate is closed, the counting operation is complete, gate flag is set, and an interrupt is generated. clear clear * fw is selected as fx/128 (4.19mhz/128) or fxt (32.768khz) by wmod.0 fcmod.2-.0 gate control circuit 16 16-bit counter mux c0out c1out fcl data bus fcmod.3 gatef irqg fcmod.4 fcmod.6-.5 gate signal generator fw/2 7 start fw/2 10 fw/2 15 fcmod.3 or open gate figure 11-4. frequency counter block diagram
s3c72h8/p72h8 timer s and counter 11 - 23 fc component summary mode register (fcmod) activates the counter and selects the clock input for the measure frequency. ( fcl pin, c0out, or c1out). counter register (fcnt) counts clock pulses at the selected input. gate signal generator together with the mode register (fcmod), lets you select one gate time of internal clock frequencies. gate control circuit generate an interrupt, irqg after gate period is over. also manipulates the gate flag(gatef) on the gate control signal. gate flag (gatef) (read only) when the gate is opened and start the fc operation, gatef is automatically cleared. gatef will set after gate time elapsed. programmer can know the finishing time of fc operation by reading gate flag.(gatef) interrupt request flag (irqg) cleared when fc operation starts and set to logic one whenever the gate time is elapsed. interrupt enable flag (ieg) must be set to logic one before the interrupt requests generated by frequency counter can be processed. table 11-8. fcmod register overview register name type description size ram address addressing mode reset value fcmod control controls fc ; clears and resumes counting operation; sets input and the gate open time. 8-bit fa0h-fa1h 4/8-bit read/write; 1-bit read/write for .4/.3/.0 (but fcmod.4 is read only) "0" fcnt counter counts clock pulses 16-bit fa4h-fa5h, fa6h-fa7h 8-bit read-only "0" irqg flag gate interrupt request flag 1-bit fbdh.0 1-bit "0"
timers and counter s3c72h8/p72h8 11 - 24 fc mode register (fcmod) fcmod is the 8-bit mode register for frequency counter. it is located at ram addresses fa0h-fa1h and is ad - dressable by 4/8-bit write instructions. the fcmod.4/3/0 bit is also 1-bit write or read addressable. reset clears all fcmod bits to logic zero. following a reset , the frequency is disabled. fa0h fcmod.3 fcmod.2 fcmod.1 fcmod.0 fa1h "0" fcmod.6 fcmod.5 fcmod.4 table 11-9. fc mode register (fcmod) organization bit name setting resulting fc function address fcmod.7 0 always logic zero fcmod.6-.5 0 0 hold the up-counting operation of fcnt. 0 1 enable up-counting in fcnt; select fcl pin at falling edge fa1h 1 0 enable up-counting in fcnt; select c0out pin at falling edge 1 1 enable up-counting in fcnt; select c1out pin at falling edge fcmod.4 0/1 gate flag (gatef) read only fcmod.3 1 clear fcnt and irqg. (this bit is automatically cleared to logic zero immediately after counting resumes.) ; start bit fcmod.2-.0 0 0 0 close gate fa0h 0 0 1 open gate; the writing command will start fc operation after clear fcnt and irqg. ; start bit 0 1 0 select the gate time, fw/2 10 . (31.25ms at fw=32768hz) 0 1 1 select the gate time, fw/2 11 . (62.5ms at fw=32768hz) 1 0 0 select the gate time, fw/2 12 . (125ms at fw=32768hz) 1 0 1 select the gate time, fw/2 13 . (250ms at fw=32768hz) 1 1 0 select the gate time, fw/2 14 . (500ms at fw=32768hz) 1 1 1 select the gate time, fw/2 15 . (1000ms at fw=32768hz)
s3c72h8/p72h8 timer s and counter 11 - 25 gate times when you writes a value to fcmod, the fc gate is open for a selected interval, starting a falling clock edge. when the gate is open, the frequency at the fcl, c0out or c1out pin is counted by the 16-bit counter. when the gate closes, the gate flag(gatef) is set to one. an interrupt is then generated and the gate interrupt request flag(irqg) is set. clock fcmod is written gate opens here gatef is cleared to "0" counting end; gatef and irqg is set to "1" gate time 250ms 500ms 1000ms counting period (fw/2 7 , 3.906ms at fw = 32768 hz) figure 11-5. gate timing diagram
timers and counter s3c72h8/p72h8 11 - 26 watch timer overview the watch timer is a multi-purpose timer which consists of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the main and sub - system clock. it is also used as a clock source for the lcd controller, vld, voltage booster and for generating buzzer (buz) output. real-time and watch-time measurement to start watch timer operation, set bit 2 and 3 of the watch timer mode register (wmod.2, .3) to logic one or zero. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 1, 0.5 or 0.25-second or 3.91mili-second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a main system or subsystem clock source the watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. when the zero bit of the wmod register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if wmod.0 = "0", the main system clock (fx) is used as the signal source, according to the following for - mula: watch timer clock (fw) = s ystem clock (fx x ) 128 = 32.768 khz ( assuming fx = 4.19 mhz) this feature is useful for controlling timer-related operations during stop mode. when stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. by using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag irqw to "1", thereby releasing stop mode. clock source generation for lcd controller the watch timer supplies the clock frequency for the lcd controller (flcd). therefore, if the watch timer is dis - abled, the lcd controller does not operate. buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to select the desired buz frequency, load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit (f89h.3) must be set to "1" ? the output latch for i/o port 3.3 must be cleared to "0" ? the port 3.3 output mode flag (pm3.3) must be set to ?output? mode
s3c72h8/p72h8 timer s and counter 11 - 27 timing tests in high-speed mode by setting wmod.2 and 3 (f88h.2-3) to "11", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. high-speed mode is useful for timing events for program debugging sequences. fw/16 (2 khz) enable/ disable irqw f lcd fw/2 6 (512 hz) fw/2 7 fw (32.768 khz) fx = main-system clock (4.195 mhz) fxt = sub-system clock (32.768 khz) fw = watch timer mux clock selector fxt fx/128 frequency dividing circuit wmod.7 wmod.6 wmod.5 wmod.4 wmod.3 wmod.2 wmod.1 wmod.0 8 p3.3/buz p3.3 latch pm3.3 selector circuit fw/8 (4 khz) fw/4 (8 khz) fw/2 (16 khz) fw/2 13 fw/2 14 fw/2 15 figure 11-6. watch timer circuit diagram
timers and counter s3c72h8/p72h8 11 - 28 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is mapped to ram lo - cations f88h-f89h and is 8-bit write-only addressable. a reset automatically all wmod bits to logic zero. f88h wmod.3 wmod.2 wmod.1 wmod.0 f89h wmod.7 "0" wmod.5 wmod.4 in summary, wmod settings control the following watch timer functions: ? watch timer clock selection (wmod.0) ? enable/disable watch timer (wmod.1) ? watch timer speed control (wmod.2 and wmod.3) ? buzzer frequency selection (wmod.4 and wmod.5) ? enable/disable buzzer output (wmod.7) table 11-10. watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 0 always logic zero wmod.5 - .4 0 0 2 khz buzzer (buz) signal output f89h 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 -.2 0 0 sets irqw to 1 seconds 0 1 sets irqw to 0.5 seconds 1 0 sets irqw to 0.25 seconds 1 1 sets irqw to 3.91 mili-seconds f88h wmod.1 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer wmod.0 0 select (fx/128 ) as the watch timer clock 1 select subsystem clock as watch timer clock note : main system clock frequency (fx) is assumed to be 4.19 mhz.
s3c72h8/p72h8 timer s and counter 11 - 29 + + programming tip ? using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#80 h ld pmg 1 ,ea ; p 3 .3 ? output mode bitr p 3 .3 ld ea,#87 h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
s3c72h8/p72h8 comparator 12 - 1 12 comparator overview the s3c72h8 micro-controller has a built-in comparator circuit which allows comparison of a non-inverting and a inverting input. this comparator specially is used in thermostat controller application. it is very useful in resistor- to-frequency conversion method where resistor value converts to frequency using as an rc oscillator, to detect analog value instead of analog-to-digital converter. the comparator block works only when cmpcon.2 is set. if non-inverting input level is lower than the inverting input voltage, cmpcon.3 will be cleared. if non-inverting input level is higher, cmpcon.3 will be set. this comparator output can be clock source for frequency counter block. please do not operate the comparator block in order to minimize power current consumption. cnout - comparator + cmpcon.3/.1 cnn cnp to frequency counter block to int3 cmp out cmpcon.2/.0 cmp run figure 12-1. block diagram for comparator table 12-1. control register description fe1h bit description cmpcon cmpcon.3 (read only) 0 : comparator 1 (c1out) output is low when c1p c1n 1 : comparator 1 (c1out) output is high when c1p > c1n cmpcon.2 0 : disable comparator 1 1 : enable comparator 1 cmpcon.1 (read only) 0 : comparator 0 (c0out) output is low when c0p c0n 1 : comparator 0 (c0out) output is high when c0p > c0n cmpcon.0 0 : disable comparator 0 1 : enable comparator 0
comparator s3c72h8/p72h8 12 - 2 table 12-2. control register description fd6h bit description pne pne.2 0 : comparator 0 (c0out) output is c-mos push-pull port. 1 : comparator 0 (c0out) output is n-ch open drain port. pne.3 0 : comparator 1 (c1out) output is c-mos push-pull port. 1 : comparator 1 (c1out) output is n-ch open drain port. table 12-3. characteristics of comparator circuit (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit operating voltage of comparator v ddcom ? 1.8 ? 5.5 v comparator input v cp non-inverted input(cnp) v ss -0.3 ? v dd +0.3 v voltage v cn inverted input(cnn) v ss -0.3 ? v dd +0.3 comparator offset voltage v of v i = 0.5 v to 2.5 v when v dd = 3 v ? ? 15 mv response time t da when v dd = 5 v, v cp = 2.5 v, v cn = v cp 15 mv ? ? 3 us output low current i ol when v dd = 5 v, v ol = 0.5 v -6 -12 ? ma output high current i oh when v dd = 5 v, v oh = 4.5 v +4 +10 ?
s3c72h8/p72h8 voltage level detector 13 - 1 1 3 voltage level detector overview the s3c72h8 micro-controller has a built-in vld (voltage level detector) circuit which allows detection of power voltage drop or external input level through software. turning the vld operation on and off can be controlled by software. because the ic consumes a large amount of current during vld operation. it is recommended that the vld operation should be kept off unless it is otherwise necessary. also the vld criteria voltage can be set by the software. the criteria voltage can be set by matching to one of the 4 kinds of voltage below that can be used. 2.2 v, 2.4 v, 3.0 v or 4.0 v (v dd reference voltage), or external input level (external reference voltage) the vld block works only when vldcon.2 is set. if v dd level is lower than the reference voltage selected with vldcon.1-.0, vldcon.3 will be set. if v dd level is higher, vldcon.3 will be cleared. please do not operate the vld block in order to minimize power current consumption. voltage level detecor v dd pin vldcon.3 vld out to int3 voltage level setting mux pmg1.1 extref/p0.0 vldcon.2 vldcon.1 vldcon.0 vld run set the level figure 13-1. block diagram for voltage level detect when vldcon.2 = 1 and v dd level is lower than vldcon.0, .1 setting level, vldcon.3 = 1. when vldcon.2 = 1 and v dd level is higher than vldcon.0, .1 setting level, vldcon.3 = 0.
voltage level detector s3c72h8/p72h8 1 3- 2 voltage level detector control register(vldcon) the bit 2 of vldcon controls to run or disable the operation of voltage level detect. basically this vvld is set as 2.2v by system reset and it can be changed in 4 kind voltage by selecting voltage level detect control register(vldcon). when you write 2 bit data value to vldcon, an established resistor string is selected and the vvld is fixed in accordance with this resistor. table 13-1 shows specific v vld of 4 levels. - comparator + v bat resistor string extref m pmg1.1 vref generator bias v in v ref v ldout voltage level detect control register (vldcon) fe2h, r/w, reset: 0000b .3 .2 .1 .0 lsb msb notes: 1. the reset value of vldcon is #0000b. 2. vref is 1.0 volt. r vld vld enable/disable figure 13-2. voltage level detect circuit and control register table 13-1. vldcon value and detection level. vldcon.1, .0 v vld vldout (vldcon.3) 0 0 2.2v 0 1 2.4v low(0), when vld is enabled and v in > v ref . 1 0 3.0v high(1), when vld is enabled and v in < v ref . 1 1 4.0v
s3c72h8/p72h8 voltage level detector 13 - 3 table 13-2. pmg1.1 value and reference input. pmg1.1 reference input 0 internal reference mode (p0.0 in/out circuit and pull-up resistor can be assigned by program.) 1 external reference mode (p0.0 in/out circuit and pull-up resistor are automatically disabled.) table 13-3. characteristics of voltage level detect circuit (t a = 25 c) parameter symbol conditions min typ max unit operating voltage of vld v ddvld ? 1.8 ? 5.5 v voltage of vld v vld vldcon = 00b 2.05 2.2 2.35 v vldcon = 01b 2.23 2.4 2.57 vldcon = 10b 2.78 3.0 3.22 vldcon = 11b 3.65 4.0 4.35 current consumption i vld vld on v dd = 5.5 v 17 25 ua v dd = 3.0 v ? 10 13 v dd = 2.2 v 6.5 8.1 v dd = 1.8 v 4.7 5.7 hysteresys voltage of d v vldcon = 00b ? 10 100 mv vld vldcon = 11b response time of vld tv fw = 32.768khz 1.0 ms note: to use vld, watch timer must be enabled.
s3c72h8/p72h8 voltage booster 1 4- 1 1 4 voltage booster overview this voltage booster works for the power control of lcd: generates 3 x v r (v lc2 ), 2 x v r (v lc1 ), 1 x v r (v lc0 ) for 1/3 bias lcd, or 2 x v r (v lc2, v lc1 ), 1 x v r (v lc0 ) for 1/2 bias lcd. this voltage booster allows low voltage operation of lcd display with high quality. this voltage booster circuit provides constant lcd contrast level even though battery power supply was lowered. this voltage booster include voltage regulator, and voltage charge/pump circuit. function description the voltage booster has built for driving the lcd. the voltage booster provides the capability of directly connecting an lcd panel to the mcu without having to separately generate and supply the higher voltages required by the lcd panel. the voltage booster operates on an internally generated and regulated lcd system voltage and generates a doubled and a tripled voltage levels to supply the lcd drive circuit. external capacitor are required to complete the power supply circuits. the v dd power line is regulated to get the v lc0 (v r ) level, which become a base level for voltage boosting. then a doubled and a tripled voltage will be made by capacitor charge and pump circuit. lcon.0 control the voltage booster operation. see the 15. lcd controller/driver for detail information.
voltage booster s3c72h8/p72h8 1 4- 2 block diagram c2 c1 c0 v dd voltage regulator cp1 voltage doubler cp1 voltage tripler v lc0 (v r ) v lc1 (2 x v r ) v lc2 (3 x v r ) v ss figure 14-1. voltage booster block diagram v lc0 voltage regulator voltage booster lcd driver v lc1 v lc2 v lc0 com0-3 seg0-seg25 ca cb cp1 v lc2 v lc1 c2 c1 v lc0 c0 v lc0 voltage regulator voltage booster lcd driver v lc1 v lc2 v lc0 com0-3 seg0-seg25 ca cb cp1 v lc2 v lc1 c1 v lc0 c0 1/3 bias 1/2 bias and static figure 14-2. pin connection example
s3c72h8/p72h8 voltage booster 1 4- 3 table 14-1. voltage booster absolute maximum ratings parameter symbol value unit supply voltage v dd ? 0.3 ? 6.5 v operating temperature range t opr ? 40 ? + 85 c storage temperature range t stg ? 65 ? + 150 c table 14-2. voltage booster electrical characteristics (t a = 25 c, v dd = 1.8 v to 5.5 v, v ss = 0 v) parameter symbol test conditions min typ max unit operating voltage v dd 1.8 ? 5.5 v regulated voltage v lc0 i lc0 = 5 ua, 1/3bias mode 0.9 1.0 1.1 v booster voltage v lc1 connect 1m w load between v ss and v lc1 2v lc0 ? 0.1 ? 2v lc0 + 0.1 v v lc2 connect 1m w load between v ss and v lc2 3v lc0 ? 0.1 ? 3v lc0 + 0.1 v regulated voltage v lc0 i lc0 = 5 ua, 1/2bias mode 1.45 1.60 1.75 v booster voltage v lc1 connect 1m w load between v ss and v lc1 2v lc0 ? 0.1 ? 2v lc0 + 0.1 v v lc2 connect 1m w load between v ss and v lc2 operating current consumption i vb v dd =3.0v, without load at v lc0 , v lc1 , and v lc2 ? 3 6 ua notes: 1. to use voltage booster, watch timer must be enabled. 2. we recommend 0.1 m f for external capacitor.
s3c72h8/p72h8 lcd controller/driv er 1 5- 1 1 5 lcd controller/driver overview the s3c72h8 microcontroller can directly drive an up-to-13-digit (104-segment) lcd panel. the lcd module has the following components: ? lcd controller/driver ? display ram (1e6h-1ffh) for storing display data ? 26 segment output pins (seg0 - seg25) ? four common output pins (com0 - com3) ? three lcd operating power supply pins (v lc0 - v lc2 ) bit settings in the lcd mode register, lmod, determine the lcd frame frequency, duty and bias, and the segment pins used for display output. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during stop and idle modes. the lcd control register lcon turns the lcd display on and off and switches current to the charge-pump circuits for the display. lcd data stored in the display ram locations are transferred to the segment signal pins automatically without program control. 2 3 lcd controller/ driver ca - cb v lc0 - v lc2 com0 - com3 8 data bus seg0-seg29 26 4 figure 15-1. lcd function diagram
lcd controller/driver s3c72h8/p72h8 1 5- 2 lcd circuit diagram seg13 seg15 seg14 seg19 seg18 seg17 seg16 seg25 seg24 seg23 seg22 com3 8 m u x 4 4 1ffh.3 1ffh.2 1ffh.1 1ffh.0 1f4h.3 1f4h.2 1f4h.1 1f4h.0 - - - - - - - - 1f6h.3 1f6h.2 1f6h.1 1f6h.0 4 - - - - - - - - - - - - - - - - m u x - - - - - - - - m u x s e g m e n t d r i v e r seg21 seg20 seg0 ... timing controller com control f lcd lmod 4 com2 com1 com0 lcon voltage requlator & booster (charge/pump) lcd voltage control v lc0 v lc1 v lc2 figure 15-2. lcd circuit diagram
s3c72h8/p72h8 lcd controller/driv er 1 5- 3 lcd ram address area ram addresses 1e6h - 1ffh are used as lcd data memory. these locations can be addressed by 1-bit or 4-bit instructions. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0-seg25 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. bit 1 bit2 bit 0 bit 3 ..... ..... ..... ..... 1e6h 1e7h 1f4h 1f5h 1fah 1ffh 1feh 1fdh 1fch 1fbh 1f9h 1f8h 1f7h 1f6h seg0 seg1 seg14 seg15 seg20 seg25 seg24 seg23 seg22 seg21 seg19 seg18 seg17 seg16 com3 com2 com1 com0 figure 15-3. lcd display data ram organization table 15-1. display ram bits and sync clock per duty cycle lcd duty cycle display ram bits (1e6h-1ffh) display synchronization clock (f lcd ) static bit 0 com0 1/2 bits 0-1 com0-com1 1/3 bits 0-2 com0-com2 1/4 bits 0-3 com0-com3
lcd controller/driver s3c72h8/p72h8 1 5- 4 lcd control register (lcon) lcon is a 4-bit write-only register that is mapped to ram address f8eh. bit values in the lcon register turn the lcd display on and off and control the flow of current to charge-pump circuits in the lcd circuit. after a reset, all lcon values are cleared to "0". (this turns the lcd display off and stops the pumping operation of voltage booster.) only one bit in the lcon register is used for lcd display control the lsb, lcon.0. the effect of the lcon.0 setting is dependent upon the current setting of the third bit of the lmod register, lmod.3: ? if lcon.0 is "1" and lmod.3 is "0", the lcd display is turned off; ? if lcon.0 is "1" and lmod.3 is "1", the lcd display is turned on and the com and seg signal outputs operate in normal display mode. when lcon.0 is logic zero, the lcd display is turned off and the current to the charge/pump circuit is turned off, despite the current lmod.3 value. table 15-2. lcd control register (lcon) organization lcon bit setting description lcon.3 0 always logic zero. lcon.2 0 always logic zero. lcon.1 0 always logic zero. lcon.0 0 lcd output low; turn display off and turn off voltage regulator & booster. 1 turn on voltage regulator & booster if lmod.3 = "0": lcd output low; turn display off. if lmod.3 = "1": com and seg output in display mode; turn display on. table 15-3. relationship of lcon.0 and lmod.3 bit settings lcon.0 lmod.3 com0-com3 seg0-seg25 voltage reg. & booster 0 x output low; lcd display off output low; lcd display off off, cut off current path in voltage regulator & booster 1 0 output low; lcd display off output low; lcd display off on, turn on current path in 1 com output corresponds to display mode seg output corresponds to display mode voltage regulator & booster note : ' x ' means 'don't care.
s3c72h8/p72h8 lcd controller/driv er 1 5- 5 lcd mode register ( lmod ) the lcd mode control register lmod is mapped to ram addresses f8ch-f8dh. although the lmod register can be manipulated using 8-bit write instructions, bit 3 (lmod.3) can be also written by 1-bit instructions. f8ch lmod.3 lmod.2 lmod.1 lmod.0 f8dh 0 0 lmod.5 lmod.4 lmod controls these lcd functions: ? lcd enable/disable (lmod.3) ? duty selection (lmod.2-lmod.0) ? lcdck clock frequency selection (lmod.5-lmod.4) the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency.' since lcdck is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the lcd display is turned on. reset clears the lmod register values to logic zero. this produces the following lcd control settings: ? display is turned off ? lcdck frequency is the watch timer clock (fw)/29 = 64 hz the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. table 15-4. lcd clock signal (lcdck) frame frequency lcdck frequency static 1/2 duty 1/3 duty 1/4 duty fw/29 (64 hz) 64 32 21 16 fw/28 (128 hz) 128 64 43 32 fw/27 (256 hz) 256 128 85 64 fw/26 (512 hz) 512 256 171 128 notes: 1. 'fw' is the watch timer clock frequency of 32.768 khz. 2. the watch timer clock frequency for lcdck is shown in parentheses in column one.
lcd controller/driver s3c72h8/p72h8 1 5- 6 table 15-5. lcd mode control register (lmod) organization lmod.7 lmod.6 0 0 always 0. lmod.5 lmod.4 lcd clock (lcdck) frequency 0 0 32.768 khz watch timer clock (fw)/2 9 = 64 hz 0 1 fw/2 8 = 128 hz 1 0 fw/2 7 = 256 hz 1 1 fw/2 6 = 512 hz lmod.3 lmod.2 lmod.1 lmod.0 duty and bias selection for lcd display 0 x x x lcd display off 1 0 0 0 1/4 duty, 1/3 bias 1 0 0 1 1/3 duty, 1/3 bias 1 0 1 1 1/3 duty, 1/2 bias 1 0 1 0 1/2 duty, 1/2 bias 1 1 1 0 static note : ' x ' means 'don't care.' table 15-6. maximum number of display digits per duty cycle lcd duty lcd bias com output pins maximum seg display static static com0 26 1/2 1/2 com0-com1 26 x 2 1/3 1/3 or 1/2 com0-com2 26 x 3 1/4 1/3 com0-com3 26 x 4
s3c72h8/p72h8 lcd controller/driv er 1 5- 7 lcd drive voltage the lcd display is turned on only when the voltage difference between the common and segment signals is greater than v lcd . the lcd display is turned off when the difference between the common and segment signal voltages is less than v lcd . the turn-on voltage, + v lcd or - v lcd , is generated only when both signals are the selected signals of the bias. table 15-7 shows lcd drive voltages for static mode and 1/3 bias. table 15-7. lcd drive voltage values lcd power supply static mode 1 / 2 bias 1 / 3 bias v lc2 v lcd v lcd v lcd v lc1 - v lcd 2/3 v lcd v lc0 - 1/2 v lcd 1/3 v lcd v ss 0 v 0 v 0 v note the lcd panel display may deteriorate if a dc voltage is applied that lies between the common and segment signal voltage. therefore, always drive the lcd panel with ac voltage.
lcd controller/driver s3c72h8/p72h8 1 5- 8 lcd seg/ com signals the 26 lcd segment signal pins are connected to corresponding display ram locations at 1e6h-1ffh. bits 0-3 of the display ram are synchronized with the common signal output pins com0, com1, com2, and com3. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin. each bias has select and no-select signals. table 15-8. select/no-select signals for lcd static display mode seg select non-select com v lc2 / v ss v ss / v lc2 v ss / v lc2 - v lcd / + v lcd 0 v / 0 v com t t t = lcdck seg v ss v lc2 v ss v lc2 select no-select figure 15-4. select/no-select bias signals in static display mode
s3c72h8/p72h8 lcd controller/driv er 1 5- 9 table 15-9. select/no-select signals for lcd 1/2 bias display mode table seg select non-select com v lc1,2 / v ss v ss / v lc1,2 select v ss / vlc1,2 - v lcd / + v lcd 0 v / 0 v non-select v lc0 - 1/2 v lcd / + 1/2 v lcd + 1/2 v lcd / - 1/2 v lcd com t t t = lcdck seg v ss v lc1, 2 v ss select no-select v lc1, 2 v lc0 v lc0 figure 15-5. select/no-select bias signals in 1/2 bias display mode
lcd controller/driver s3c72h8/p72h8 1 5- 10 table 15-10. select/no-select signals for lcd 1/3 bias display mode seg select non-select com v lc2 / v ss v lc0 / v lc1 select v ss / v lc2 - v lcd / + v lcd - 1/3 v lcd / + 1/3 v lcd non-select v lc1 / v lc0 - 1/3 v lcd / + 1/3 v lcd + 1/3 v lcd / - 1/3 v lcd com t t t = lcdck seg select no-select v ss v lc2 v lc0 v lc1 v lc1 v lc0 v lc2 v ss figure 15-6. select/no-select signals in 1/3 bias display mode
s3c72h8/p72h8 electrical data 16- 1 16 electrical data overview in this section, information on s3c72h8 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts stop mode characteristics and timing waveforms ? ram data retention supply volt age in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c72h8/p72h8 16- 2 table 16- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i n ? ? 0.3 to v dd + 0.3 output voltage v o all i/o ports ? 0.3 to v dd + 0.3 output current high i oh one i/o p in active ? 7 ma all i/o ports active ? 40 output current low i ol one i/o pin active + 15 ma total pin circuit + 60 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 table 16- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units operation v oltage v dd f osc = 6 mhz (cpu clock = 1.25 mhz) 2.7 ? 5.5 v f osc = 4.19 mhz (instruction clock = 1.04 mhz) 2.0 5.5 f osc = 3 mhz (cpu clock = 0.75 mhz) 1.8 5.5 input high v i h1 p0, p2, p3, p4, p5 and p6 0.8 v dd ? v dd v oltage v i h 2 reset 0.85 v dd v dd v i h 3 x in v dd -0.1 v dd input l ow v il1 p0, p2, p3, p4, p5 and p6 ? 0.2 v dd v oltage v il2 reset 0.3 v dd v il3 x in 0.1 output high v oltage v oh1 v dd = 5.0 v i oh = ? 1 ma all output pins v dd ? 1 .0 ? ? v i oh = ? 100 m a v dd ? 0.5 output l ow v oltage v ol1 v dd = 5.0 v, i ol = 2 ma all output pins except v ol2 ? 0.4 0.5 v ol2 v dd = 5.0 v , i ol = 1 5 ma ports 2,3, and 4 0.4 1.0
s3c72h8/p72h8 electrical data 16- 3 table 16- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input h igh leakage c urrent (note) i lih1 v in = v dd all input pins ? ? 3 a input low leakage c urrent (note) i lil1 v in = v dd ; all input pins except reset ? ? ? 3 output h igh l eakage c urrent (note) i loh v out = v dd all i/o pins and output pins ? ? 3 output l ow l eakage c urrent (note) i lol v o ut = 0 v all i/o pins and output pins ? ? ? 3 pull-up r esistor s r l1 v in = 0 v , v dd = 5 v t a = 25 c , ports 0-6 25 47 100 k w v dd = 3 v 50 90 150 r l2 v in = 0 v; v dd = 5 .0 v 150 250 350 t a = 25 c , reset oscillator feed back resistors r osc1 v dd = 5.0 v, t a = 25 c x in = v dd , x out = 0v 400 700 1200 r osc2 v dd = 5.0 v, t a = 25 c xt in = v dd , xt out = 0v 1000 1500 3000 |v lc1 -comi| voltage drop (i = 0-3) v dc -15 ua per common pin ? ? 120 mv |v lc1 -segi| voltage drop (i = 0-25) v ds -15 ua per segment pin ? ? 120 note : except x in , x out , xt in , xt out
electrical data s3c72h8/p72h8 16- 4 table 16- 2. d.c. electrical characteristics (con tinu ed) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (note) i dd1 main operation mode: v dd = 5 v 10%, 6-mhz crystal ? 3.5 8 ma v dd = 5 v 10%, 4.19 mhz 2.5 5.5 v dd = 3 v 10%, 6-mhz crystal 1.6 4 v dd = 3 v 10%, 4.19 mhz 1.2 3 i dd2 main idle mode: v dd = 5 v 10%, 6-mhz crystal ? 1.8 3.5 v dd = 5 v 10%, 4.19 mhz 1.4 3.0 v dd = 3 v 10%, 6-mhz crystal 0.6 1.2 v dd = 3 v 10%, 4.19 mhz 0.5 1.1 i dd3 sub operation mode: v dd = 3 v , 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 15 30 ua i dd4 sub idle mode; v dd = 3 .0, 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 6 15 i dd5 stop mode; main & sub osc stop, v dd =5 v 10% except i vd, i vld, icomp and external load. scmod = 0100b xt in = 0v- ? 0.3 3 ua stop & sub osc stop, v dd = 3 v , except i vd, i vld, lcomp and external load. 0.1 1 note: supply current does not include current drawn through internal pull-up resistors or external output current loads. i lcd is lcd controller/driver operating current, i vb is voltage booster current, icomp is comparator current and i vld is voltage level detector current. table 16-3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr 1.0 - 5.5 v data retention supply current i dddr v dddr = 1.0 v stop mode; main & sub osc stop. except i vb , i vld , i lcd and external load. - - 1 ua
s3c72h8/p72h8 electrical data 16- 5 table 16-4 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator c1 c2 x in x out oscillation frequency (1) ? 0.4 ? 6 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 2.0 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator r x in x out frequency (1) v dd = 5 v r = 25 k, v dd = 5 v r = 50 k , v dd = 3 v 0.4 ? 2.0 1.0 2.5 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c72h8/p72h8 16- 6 table 16-5 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in xt out c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 us notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. table 16-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s t ime (1 ) v dd = 1.8 v to 5 .5 v 1.33 ? 64 tcl0 , fcl input f ti0 , f ti0 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz f requency v dd = 1.8 v to 5 .5v 1 tcl0 , fcl i nput t tih0, t til0 v dd = 2.7 v to 5.5 v 150 ? ? ns h igh, low w idth t fch , t fcl v dd = 1.8 v to 5 .5 v 250 interrupt input t inth, int0 (2) ? ? s high, low width t intl int1, int2 (ks0-ks3) 10 reset input low width t rsl input 10 ? ? s notes 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock (fx) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
s3c72h8/p72h8 electrical data 16- 7 1.5 mhz cpu clock 1.05 mhz 750 khz 15.625 khz main osc frequency 4.19 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1.8 v 2.7 v 5.5 v figure 16- 1. standard operating voltage range 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 16- 2. a.c timing measure pints (except for x in and xt in )
electrical data s3c72h8/p72h8 16- 8 execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode operationg mode data retention mode t srel t wait reset v dd figure 16- 3. stop mode release timing when initiated by reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 16- 4. stop release timing when initiated by interrupt request x in t xh t xl 1/fx v dd - 0.5 v 0.4 v figure 16- 5. clock timing measurement at x in
s3c72h8/p72h8 electrical data 16- 9 xt in t xth t xtl 1/fxt v dd - 0.5 v 0.4 v figure 16- 6. clock timing measurement at xt in reset t rsl 0.2 v dd figure 16-7 . input timing for reset reset signal int0, 1 ks0 to ks3 t inth t intl 0.8 v dd 0.2 v dd figure 16-8 . input timing external interrupt
s3c72h8/p72h8 mechanical data 17- 1 17 mechanical data overview the s3c72h8/p72h8 microcontroller is available in a 64-pin qfp package (samsung: 64-qfp-1420f) package dimensions are shown in figure 17-1 64-qfp-1420f #64 #1 note : dimensions are in millimeters. 20.00 0.2 14.00 0.2 17.90 0.3 23.90 0.3 (1.00) (1.00) 0.80 0.20 0.05-0.25 2.65 0.10 3.00 max 0.15 +0.10 -0.05 0-8 1.00 0.15 max 0.40+0.10 -0.05 0.80 0.20 0.10 max figure 17-1. 64 -qfp-14 20f package dimensions
s3c72h8/p72h8 s3p72 h8 otp 18- 1 1 8 S3P72H8 otp overview the S3P72H8 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72h8 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the S3P72H8 is fully compatible with the s3c72h8, both in function and in pin configuration. because of its simple programming requirements, the S3P72H8 is ideal for use as an evaluation chip for the s3c72h8.
S3P72H8 otp s3c72h8/p72h8 18- 2 ca cb v lc0 v lc1 v lc2 p0.0/extref sdat /p0.1 sclk /p0.2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p2.0/int0 p2.1/int1 p2.2/tcl0 com0 com1 com2 com3 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 fcl/p2.3 tclo0/p3.0 btco/p3.1 clo/p3.2 buz/p3.3 ks0/p6.0 ks1/p6.1 ks2/p6.2 ks3/p6.3 c0p/p4.0 c0n/p4.1 c0out/p4.2 c1out/p4.3 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 p5.1/c1n p5.0/c1p S3P72H8 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 figure 18-1. S3P72H8 pin assignments
s3c72h8/p72h8 s3p72 h8 otp 18- 3 table 18-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.1 sdat 7 i/o serial data pin. output port when reading and input port when writing can be assigned as input/push-pull output port respectively. p0.2 sclk 8 i/o serial clock pin. input only pin. test v pp (test) 13 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 16 i chip initialization v dd / v ss v dd / v ss 9/10 i logic power supply pin. v dd should be tied to + 5 v during programming. table 18-2. comparison of S3P72H8 and s3c72h8 features characteristic S3P72H8 s3c72h8 program memory 8 k-byte eprom 8 k-byte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 64 qfp 64 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P72H8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 18-3 below. table 18-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15-a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
S3P72H8 otp s3c72h8/p72h8 18- 4 table 18-4 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units supply current (note) i dd1 main operation mode: v dd = 5 v 10%, 6-mhz crystal ? 3.5 8 ma v dd = 5 v 10%, 4.19 mhz 2.5 5.5 v dd = 3 v 10%, 6-mhz crystal 1.6 4 v dd = 3 v 10%, 4.19 mhz 1.2 3 i dd2 main idle mode: v dd = 5 v 10%, 6-mhz crystal ? 1.8 3.5 v dd = 5 v 10%, 4.19 mhz 1.4 3.0 v dd = 3 v 10%, 6-mhz crystal 0.6 1.2 v dd = 3 v 10%, 4.19 mhz 0.5 1.1 i dd3 sub operation mode: v dd = 3 v , 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 15 30 ua i dd4 sub idle mode; v dd = 3 .0, 32768hz main osc stop, except i vb , i vld , icomp, i lcd and external load. ? 6 15 i dd5 stop mode; main & sub osc stop, v dd =5 v 10% except i vd, i vld, icomp and external load. scmod = 0100b xt in = 0v- ? 0.3 3 ua stop & sub osc stop, v dd = 3 v , except i vd, i vld, lcomp and external load. 0.1 1 note: supply current does not include current drawn through internal pull-up resistors or external output current loads. i lcd is lcd controller/driver operating current, i vb is voltage booster current, icomp is comparator current, and i vld is voltage level detector current.
s3c72h8/p72h8 s3p72 h8 otp 18- 5 1.5 mhz cpu clock 1.05 mhz 750 khz 15.625 khz main osc frequency 4.19 mhz 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1.8 v 2.7 v 5.5 v figure 18-2 . standard operating voltage range
S3P72H8 otp s3c72h8/p72h8 18- 6 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 18-3. otp programming algorithm
s3c72h8/p72h8 development tools 19- 1 19 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7, s3c8, s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's s3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value ? ff ? is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the s3c72h8 microcontroller and otp programmer (gang) are now available.
development tools s3c72h8/p72h8 19- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam4 base unit power supply unit ibm-pc at or compatible tb72h8 target board eva chip target application system figure 19-1 . smds product configuration (smds2+)
s3c72h8/p72h8 development tools 19- 3 tb72h8 target board the tb72h8 target board is used for the s3c72h8/p72h8 microcontroller. it is supported by the smds2+ development system. tb72h8 sm1267a + idle + stop 100-pin connector 25 1 reset to user v cc off on 74hc11 xti mds xtal v lc0 v lc1 ca v lc2 cb j101 40-pin connector 2 1 31 32 j102 40-pin connector 34 33 63 64 120 120 qfp s3e72h0 eva chip 1 figure 19-2 . tb72h8 target board configuration
development tools s3c72h8/p72h8 19- 4 table 19-1. power selection settings for tb72h8 ? to user_vcc ? settings operating mode comments to user_vcc on off target system smds2/smds2+ tb72h8 v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system smds2/smds2+ tb72h8 external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply.
s3c72h8/p72h8 development tools 19- 5 table 19-2. sub-clock selection settings for tb72h8 sub clock setting operating mode comments xtal mds xti no connection smds2/smds2+ 100 pin connector eva chip s3e72h0 xt in xt out set the xti switch to "mds" when the target board is connected to the smds2/smds2+. xtal mds x ti target board eva chip s3e72h0 xt in xt out xtal set the xti switch to "xtal" when the target board is used as a standalone unit, and is not connected to the smds2/smds2+. idle led this led is on when the evaluation chip ( s3e72h0 ) is in idle mode. stop led this led is on when the evaluation chip ( s3e72h0 ) is in stop mode.
development tools s3c72h8/p72h8 19- 6 ca v lc0 v lc2 sdat /p0.1 v dd /v dd x out v pp /test xt out p2.0/int0 p2.2/tcl0 p3.0/tclo0 p3.2/clo p6.0/ks0 p6.2/ks2 p4.0/c0p p4.2/c0out gnd gnd gnd gnd cb v lc1 p0.0/extref sclk/p0.2 v ss / v ss x in xt in reset / reset reset p2.1/int1 p2.3/fcl p3.1/btco p3.3/buz p6.1/ks1 p6.3/ks3 p4.1/c0n p4.3/c1out gnd gnd gnd gnd j101 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 40-pin dip connector p5.0/c1p seg25 seg23 seg21 seg19 seg17 seg15 seg13 seg11 seg9 seg7 seg5 seg3 seg1 com3 com1 gnd gnd gnd gnd p5.1/c1n seg24 seg22 seg20 seg18 seg16 seg14 seg12 seg10 seg8 seg6 seg4 seg2 seg0 com2 com0 gnd gnd gnd gnd j102 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 40-pin dip connector figure 19-3 . 32 -pin connector s for tb72h8 4 0-pin dip connector target board target system target cable for 40 pin connector part name: as40d-a order code: sm6306 j102 1 2 39 40 1 2 39 40 j101 j101 j102 1 2 39 40 1 2 39 40 figure 19-4 . tb72h8 adapter cable for 64-qfp package ( s3c72h8/p72h8 )

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