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rev.3.00, dec.14. 2004, page 1 of 17 hn58x2402sfpiag hn58x2404sfpiag two-wire serial interface 2k eeprom (256-word 8-bit) 4k eeprom (512-word 8-bit) rej03c0133-0300 rev.3.00 dec.14.2004 description hn58x24xxsfpiag series are two-wire serial in terface eeprom (electrically erasable and programmable rom). they realize high speed, low power consumption and a high level of reliability by employing advanced mnos memory technology and cm os process and low voltage circuitry technology. they also have a 8-byte page programming f unction to make their write operation faster. features ? single supply: 1.8 v to 5.5 v ? two-wire serial interface (i 2 c tm serial bus* 1 ) ? clock frequency: 400 khz ? power dissipation: ? standby: 3 a (max) ? active (read): 1 ma (max) ? active (write): 3 ma (max) ? automatic page write: 8-byte/page ? write cycle time: 10 ms (2.7 v to 5.5 v)/15ms (1.8 v to 2.7 v) ? endurance: 10 5 cycles (page write mode) ? data retention: 10 years ? small size packages: sop 8-pin ? shipping tape and reel: 2,500 ic/reel ? lead free products. note: 1. i 2 c is a trademark of philips corporation.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 2 of 17 ordering information type no. internal organization operating voltage frequency package hn58x2402sfpiage 2k bit (256 8-bit) 1.8 v to 5.5 v 400 khz 150 mil 8-pin plastic sop (fp-8dbv) HN58X2404SFPIAGE 4k bit (512 8-bit) lead free pin arrangement 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp scl sda (top view) 8-pin sop pin description pin name function a0 to a2 device address scl serial clock input sda serial data input/output wp write protect v cc power supply v ss ground
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 3 of 17 block diagram control logic high voltage generator address generator x decoder y decoder memory array y-select & sense amp. serial-parallel converter v cc v ss wp a0, a1, a2 scl sda absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.6 to +7.0 v input voltage relative to v ss vin ? 0.5 * 2 to +7.0 * 3 v operating tem perature range * 1 topr ? 40 to +85 c storage temperature range tstg ? 65 to +125 c notes: 1. including electrical c haracteristics and data retention. 2. vin (min): ? 3.0 v for pulse width 50 ns. 3. should not exceed v cc + 1.0 v. dc operating conditions parameter symbol min typ max unit supply voltage v cc 1.8 ? 5.5 v v ss 0 0 0 v input high voltage v ih v cc 0.7 ? v cc + 1.0 v input low voltage v il ? 0.3 * 1 ? v cc 0.3 v operating temperature topr ? 40 ? +85 c note: 1. v il (min): ? 1.0 v for pulse width 50 ns.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 4 of 17 dc characteristics (ta = ? 40 to +85 c, v cc = 1.8 v to 5.5 v) parameter symbol min typ max unit test conditions input leakage current i li ? ? 2.0 a v cc = 5.5 v, vin = 0 to 5.5 v (scl, sda) ? ? 20 a v cc = 5.5 v, vin = 0 to 5.5 v (a0 to a2, wp) output leakage current i lo ? ? 2.0 a v cc = 5.5 v, vout = 0 to 5.5 v standby v cc current i sb ? 1.0 3.0 a vin = v ss or v cc read v cc current i cc1 ? ? 1.0 ma v cc = 5.5 v, read at 400 khz write v cc current i cc2 ? ? 3.0 ma v cc = 5.5 v, write at 400 khz output low voltage v ol2 ? ? 0.4 v v cc = 4.5 to 5.5 v, i ol = 1.6 ma v cc = 2.7 to 4.5 v, i ol = 0.8 ma v cc = 1.8 to 2.7 v, i ol = 0.4 ma v ol1 ? ? 0.2 v v cc = 1.8 to 2.7 v, i ol = 0.2 ma capacitance (ta = +25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (a0 to a2, scl, wp) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (sda) c i/o * 1 ? ? 6.0 pf vout = 0 v note: 1. this parameter is sampled and not 100 % tested.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 5 of 17 ac characteristics (ta = ? 40 to +85 c, v cc = 1.8 to 5.5 v) test conditions ? input pules levels: ? v il = 0.2 v cc ? v ih = 0.8 v cc ? input rise and fall time: 20 ns ? input and output timing reference levels: 0.5 v cc ? output load: ttl gate + 100 pf parameter symbol min typ max unit notes clock frequency f scl ? ? 400 khz clock pulse width low t low 1200 ? ? ns clock pulse width high t high 600 ? ? ns noise suppression time t i ? ? 50 ns 1 access time t aa 100 ? 900 ns bus free time for next mode t buf 1200 ? ? ns start hold time t hd.sta 600 ? ? ns start setup time t su.sta 600 ? ? ns data in hold time t hd.dat 0 ? ? ns data in setup time t su.dat 100 ? ? ns input rise time t r ? ? 300 ns 1 input fall time t f ? ? 300 ns 1 stop setup time t su.sto 600 ? ? ns data out hold time t dh 50 ? ? ns write cycle time v cc = 2.7 v to 5.5 v t wc ? ? 10 ms 2 v cc = 1.8 v to 2.7 v t wc ? ? 15 ms 2 notes: 1. this parameter is sampled and not 100 % tested. 2. t wc is the time from a stop condition to the end of internally controlled write cycle.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 6 of 17 timing waveforms bus timing t f 1/f scl t high t su.sta t hd.sta t hd.dat t su.dat t su.sto t buf t dh t aa t low t r scl sda (in) sda (out) write cycle timing scl sda d0 in write data ack (address (n)) t wc (internally controlled) stop condition start condition
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 7 of 17 pin function serial clock (scl) the scl pin is used to control seri al input/output data timing. the scl input is used to positive edge clock data into eeprom device and ne gative edge clock data out of each device. maximum clock rate is 400 khz. serial input/output data (sda) the sda pin is bidirectional for serial data transfer. the sda pin needs to be pulled up by resistor as that pin is open-drain driven structure. use proper resistor value for your system by considering v ol , i ol and the sda pin capacitance. except for a start condition and a stop condition which will be discussed later, the sda transition needs to be completed during the scl low period. data validity (sda data change timing waveform) scl sda data change data change note: high-to-low and low-to-high change of sda should be done during the scl low period.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 8 of 17 device address (a0, a1, a2) up to eight devices for 2k, four devices for 4k, can be addressed on the same bus by setting the levels on these pins to different combinations. the levels on these pins are compared with the device address code which are input through the sda pin. the device is se lected if the compare is successfully done. these pins are internally pulled-down to v ss . the device read these pins as low if unconnected. as for 4k, it is unnecessary for the a0 pin to be connected because the corresponding device address code is used as memory address a8. pin connections for a0 to a2 pin connection memory size max connect number a2 a1 a0 notes 2k bit 8 v cc /v ss * 1 v cc /v ss v cc /v ss 4k bit 4 v cc /v ss v cc /v ss * 2 use a0 for memory address a8 notes: 1. ?v cc /v ss ? means that the device addre ss pins are connected to v cc or v ss . these pins are v ss if unconnected. 2. = don?t care (open is also approval.) write protect (wp) when the write protect pin (wp) is high, the write protections feature is enabled and operates as shown in the following table. when the wp is low, write operations for all memory array are allowed. the read operation is always activated irrespective of the wp pin status. the wp pin is internally pull-down to v ss . write operations for all memory array are allowed if unconnected. write protect area write protect area wp pin status 2k bit 4k bit v ih entire (2k bit) entire (4k bit) v il normal read/write operation
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 9 of 17 functional description start condition a high-to-low transition of the sda with the scl high is needed in order to start read, write operation. (see start condition and stop condition) stop condition a low-to-high transition of the sda with the scl high is a stop condition. the stand-by operation starts after a read sequence by a stop condition. in the case of write operation, a stop condition terminates the write data inputs and place the device in a internally -timed write cycle to the memories. after the internally-timed write cycle which is specified as t wc , the device enters a standby mode. (see write cycle timing) start condition and stop condition scl sda (in) stop condition start condition
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 10 of 17 acknowledge all addresses and data words are serially transmitted to and from in 8-bit words. the receiver sends a zero to acknowledge that it has received each word. this happens during nint h clock cycle. the transmitter keeps bus open to receive acknowledgment from the receive r at the ninth clock. in the write operation, eeprom sends a zero to acknowledge after receiving ever y 8-bit words. in th e read operation, eeprom sends a zero to acknowledge after receiving the devi ce address word. after sending read data, the eeprom waits acknowledgment by keeping bus open. if the eeprom receives zero as an acknowledge, it sends read data of next address. if the eepro m receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. if the eeprom receives neither acknowledgment "0" nor a stop c ondition, the eeprom keeps bus open without sending read data. acknowledge timing waveform scl sda in sda out 12 8 9 acknowledge out
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 11 of 17 device addressing the eeprom device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. the device address wo rd consists of 4-bit device code, 3-bit device address code and 1-bit read/write(r/w) code. the most significant 4-bit of the device address word are used to distinguish device type and this eeprom uses ?1010? fixed code. the device address word is followed by the 3-bit device address code in the order of a2, a1, a0. the device address code selects one device out of all devices which are connected to the bus. this means that the device is selected if the inputted 3-bit device address code is equal to the corresponding ha rd-wired a2-a0 pin status. as for the 4kbit eeproms, some bits of their device address code may be used as the memory address bits. for example, a0 is used as a8 of memory address for the 4kbit. the eighth bit of the device address word is the read/write(r/w) bit. a write operation is initiated if this bit is low and a read operation is initiated if this bit is high. upon a compare of the device address word, the eeprom enters the read or write operation after outputting the zero as an acknowledge. the eeprom turns to a stand-by state if the device code is not ?1010? or device address code doesn?t coincide with status of the correspond hard-wired device address pins a0 to a2. device address word device address word (8-bit) device code (fixed) device address code * 1 r/w code * 2 2k 1 0 1 0 a2 a1 a0 r/w 4k 1 0 1 0 a2 a1 a8 r/w notes: 1. a2 to a0 are device address and a8 are memory address. 2. r/w=?1? is read and r/w = ?0? is write.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 12 of 17 write operations byte write: a write operation requires an 8-bit device address word with r/w = ?0?. then the eeprom sends acknowledgment "0" at the ninth clock cycle. after these, eeproms recei ve 8-bit memory address word. upon receipt of this memory address, the eepro m outputs acknowledgment "0" and receives a following 8-bit write data. after receipt of write data, the eeprom outputs acknowledgment "0". if the eeprom receives a stop condition, the eeprom enters an intern ally-timed write cycle and terminates receipt of scl, sda inputs until completion of the write cycl e. the eeprom returns to a standby mode after completion of the write cycle. byte write operation 2k, 4k device address memory address (n) write data (n) start stop 1010 w a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 ack ack ack r/w page write: the eeprom is capable of the page write operation which allows any number of bytes up to 8 bytes to be written in a single write cycle. the page write is th e same sequence as the byte write except for inputting the more write data. the page write is initiated by a start condition, devi ce address word, memory address(n) and write data(dn) with every ninth bit acknowledgment. the eeprom enters the page write operation if the eeprom receives more write data(dn+1) instead of receiving a stop condition. the a0 to a2 address bits are automatica lly incremented upon receiving write data(dn+1). the eeprom can continue to receive write data up to 8 bytes. if the a0 to a2 address bits reaches th e last address of the page, the a0 to a2 address bits will roll over to the first address of the same page and previous write data will be overwritten. upon receiving a stop condition, the eeprom stops receiving write data and enters internally-timed write cycle. page write operation device address memory address (n) write data (n+m) write data (n) 2k, 4k 1010 w a7 a6 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack ack r/w ack
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 13 of 17 acknowledge polling: acknowledge polling feature is used to show if the eep rom is in a internally- timed write cycle or not. this feature is initiated by the stop condition after inputting write data. this requires the 8-bit device address word following the start condition during a in ternally-timed write cycle. acknowledge polling will operate when the r/w code = ?0?. acknowledgment ?1? (no acknowledgment) shows the eeprom is in a internally-timed write cycle and acknowledgment ?0? shows that the internally-timed write cycle has completed. see write cycle polling using ack. write cycle polling using ack send write command send stop condition to initiate write cycle send start condition send device address word with r/w = 0 send memory address send start condition send stop condition send stop condition proceed random address read operation proceed write operation next operation is addressing the memory ye s ye s no no ack returned
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 14 of 17 read operation there are three read operations: current address read , random read, and sequential read. read operations are initiated the same way as write operations with the exception of r/w = ?1?. current address read: the internal address counter main tains the last address accessed during the last read or write operation, with incremented by one. current address read accesses the address kept by the in ternal address counter. after receiving a start condition and the device address word(r/w is ?1?), the eeprom outputs the 8-bit current address data from the most significant bit following acknowledgment ?0?. if the eeprom receives acknowledgment ?1? (no acknowledgment) a nd a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. in case the eeprom has accessed the last address of the page at previous write opera tion, the current address will roll over within page addressing and returns to the first address in the same page. the current address is valid while power is on. the current address after power on will be indefinite. the random read operation described below is necessary to define the memory address. current address read operation 2k, 4k device address read data (n+1) start stop 1010 r d7 d6 d5 d4 d3 d2 d1 d0 ack no ack r/w * 1 note: 1. don? care bit for 4k.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 15 of 17 random read: this is a read operation with defined read address. a random read requires a dummy write to set read address. the eeprom receives a start condition, device address word(r/w=0) and memory address sequentially. the eeprom outputs acknowledgment ?0? after receiving memory address then enters a current address read with receiving a start condition. the eeprom output s the read data of the address which was defined in the dummy write ope ration. after receiving acknowledgment ?1?(no acknowledgment) and a following stop condition, th e eeprom stops the random read operation and returns to a standby state. random read operation device address device address memory address (n) read data (n) 2k, 4k 1010 1010 @@@ # # # wr a7 a6 a5 a4 a3 a2 a1 a0 d5 d6 d7 d4 d3 d2 d1 d0 start start ack ack r/w ack r/w note: 1. 2nd device address code (#) should be same as 1st (@). stop no ack dummy write currect address read sequential read: sequential reads are initiated by eith er a current address read or a random read. if the eeprom receives acknowledgment ?0? after 8-bit read data, the read addre ss is incremented and the next 8-bit read data are coming out. this operation can be continued as long as the eeprom receives acknowledgment ?0?. the address will roll over and returns address zero if it reaches the last address of the last page. the sequential read can be continued after roll over. the seque ntial read is terminated if the eeprom receives acknowledgment ?1? (no acknowledgmen t) and a following stop condition. sequential read operation device address read data (n+m) read data (n) read data (n+1) read data (n+2) 2k, 4k 1010 r d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack no ack ack r/w ack
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 16 of 17 notes data protection at v cc on/off when v cc is turned on or off, noise on the scl and sda inputs generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to unintentional program mode. to prevent this unintentional programming, this eeprom has a power on reset function. be careful of the notices described below in order for the power on reset function to operate correctly. ? scl and sda should be fixed to v cc or v ss during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned off after the eep rom is placed in a standby state. ? v cc should be turned on from the ground level(v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on speed should be longer than 10 s. write/erase endurance and data retention time the endurance is 10 5 cycles in case of page programming and 10 4 cycles in case of byte programming (1 % cumulative failure rate). the data retention time is more than 10 years when a device is page-programmed less than 10 4 cycles. noise suppression time this eeprom have a noise suppression function at scl and sda inputs, that cut noise of width less than 50 ns. be careful not to allow noise of width more than 50 ns.
hn58x2402sfpiag/hn58x2404sfpiag rev.3.00, dec.14. 2004, page 17 of 17 package dimensions hn58x2402sfpiage / HN58X2404SFPIAGE (fp-8dbv) package code jedec jeita mass (reference value) fp-8dbv 0.08 g *pd plating 0 ? ?8 ? 1.27 8 5 14 0.10 0.25 m 1.73 max 3.90 4.89 0.14 + 0.114 ?0.038 0.69 max 6.02 ?0.18 0.60 + 0.289 ?0.194 1.06 *0.40 ?0.05 *0.20 ?0.05 5.15 max unit: mm
revision history hn58x2402sfpiag/hn58x2404sfpiag data sheet contents of modification rev. date page description 1.0 mar. 30, 2001 ? ?
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