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october 2007 hyb39s128400f[e/t](l) hy[b/i]39s128800f[e/t](l) hy[b/i]39s128160f[e/t](l) hyb39s128407fe 128-mbit synchronous dram green product sdram data sheet rev. 1.32
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com data sheet hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 10122006-i6lj-wv3h hyb39s128400f[e/t](l), hy[b/i]39s128800f[e/t](l), hy[b/i]39s128160f[e/t](l) revision history: 2007-10, rev. 1.32 page subjects (major chan ges since last revision) all adapted internet version 23 corrected number of refresh cycles previous revision: 2007-06, rev. 1.31 13 corrected operation command "power down / clock suspend ...? in truth table 15 corrected text to "after the mode register is set a nop command is required" 19 corrected text to "one clock delay is required for mode entry and exit", chapter 3.5 19 corrected the line "input capacitances: ck" in table 10, chapter 4 22 corrected tck min in table 14 22 corrected cle setup time in table 14 previous revision: 2007-03, rev. 1.30 15 corrected mode register definition 21 idd for low power option 0.8 ma 22 ?transition time? replaced by ?trans ition time of clock (rise and fall)? 4 added hyi39s128800ft-7, hyi39s128800fe-7, hyi39s128160f t-7, hyi39s128160fe-7 and hyb39s128407fe-7 previous revision: 2006-10, rev. 1.20
data sheet rev. 1.32, 2007-10 3 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 1overview this chapter lists all main features of the product family hy [b/i]39s128[40/80/16][0/7]f[e/t](l) and the ordering information. 1.1 features ? fully synchronous to positive clock edge ? 0 to 70 c standard operating temperature ? -40 to 85 c industrial operating temperature ? four banks controlled by ba0 & ba1 ? programmable cas latency: 2 & 3 ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 and full page ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control (x4, x8) ? data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? power down and clock suspend mode ? 4096 refresh cycles / 64 ms (15.6 s) ? random column address every clk (1-n rule) ? single 3.3 v 0.3 v power supply ? lvttl interface ? plastic packages: p(g)?tsopii?54 400 mil width table 1 performance 1.2 description the hy[b/i]39s128[40/80/ 16][0/7]f[e/t](l) are four bank synchronous dram?s or ganized as 32 mbit x4, 16 mbit x8 and 8 mbit x16 respectively. these synchronous devices achiev e high speed data transfer rates for cas latencies by employing a chip architecture that prefet ches multiple bits and then synchronizes th e output data to a system clock. the chip is fabricated with qimonda?s advanced 0.11 m 128-mbit dram process technology. the device is designed to comply with all industry standard s set for synchronous dram products, both electrically and mechanically. all of the control, address, da ta input and output circuits are synchroni zed with the positive edge of an externa lly supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data ra te is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh oper ation are supported. these devices operate with a single 3.3 v 0.3 v power supply. all 128-mbit components are available in p(g)?tsopii?54 packages. product type speed code ?7 unit speed grade pc133?222 ? max. clock frequency @cl3 f ck3 143 mhz t ck3 7ns t ac3 5.4 ns @cl2 t ck2 7.5 ns t ac2 5.4 ns
data sheet rev. 1.32, 2007-10 4 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram table 2 ordering information for lead-containing products table 3 ordering information for rohs compliant products product type speed grade description package standard operating temperature (0 to 70 c) hyb39s128400ft-7 pc133?222?520 143mhz 32m x 4 sdram p-tsopii-54 hyb39s128400ftl-7 hyb39s128800ft-7 143mhz 16m x 8 sdram hyb39s128800ftl-7 hyb39s128160ft-7 143mhz 8m x 16 sdram hyb39s128160ftl-7 industrial operating temperature (-40 to 85 c) hyi39s128800ft-7 pc133?222?520 143mhz 16m x 8 sdram p-tsopii-54 hyi39s128160ft-7 143mhz 8m x 16 sdram product type speed grade description package note standard operating temperature (0 to 70 c) hyb39s128400fe-7 pc133?222?520 143mh z 32m x 4 sdram pg-tsopii-54 1) 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. hyb39s128400fel-7 hyb39s128407fe-7 hyb39s128800fe-7 143mhz 16m x 8 sdram hyb39s128800fel-7 HYB39S128160FE-7 143mhz 8m x 16 sdram HYB39S128160FEl-7 industrial operating temperature (-40 to 85 c) hyi39s128800fe-7 pc133?222?520 143mh z 16m x 8 sdram pg-tsopii-54 1) hyi39s128160fe-7 143mhz 8m x 16 sdram
data sheet rev. 1.32, 2007-10 5 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 2 chip configuration this chapter contains the pin configuration table, the tsop package drawing, and the block diagrams for the 4, 8, 16 organization of the sdram. 2.1 pin description listed below are the pin configurations sect ions for the various signals of the sdram table 4 pin configuration of the sdram ball no. name pin type buffer type function clock signals 4/ 8/ 16 organization 38 clk i lvttl clock signal ck 37 cke i lvttl clock enable control signals 4/ 8/ 16 organization 18 ras ilvttl row address strobe (ras), column address strobe (cas), write enable (we) 17 cas ilvttl 16 we ilvttl 19 cs ilvttl chip select address signals 4/ 8/ 16 organization 20 ba0 i lvttl bank address signals 1:0 21 ba1 i lvttl 23 a0 i lvttl address signal, address si gnal 10/auto precharge 24 a1 i lvttl 25 a2 i lvttl 26 a3 i lvttl 29 a4 i lvttl 30 a5 i lvttl 31 a6 i lvttl 32 a7 i lvttl 33 a8 i lvttl 34 a9 i lvttl 22 a10 i lvttl 35 a11 i lvttl
data sheet rev. 1.32, 2007-10 6 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram data signals 4 organization 5 dq0 i/o lvttl data signal bus 11 dq1 i/o lvttl 44 dq2 i/o lvttl 50 dq3 i/o lvttl data signals 8 organization 2 dq0 i/o lvttl data signal bus 5 dq1 i/o lvttl 8 dq2 i/o lvttl 11 dq3 i/o lvttl 44 dq4 i/o lvttl 47 dq5 i/o lvttl 50 dq6 i/o lvttl 53 dq7 i/o lvttl data signals 16 organization 2 dq0 i/o lvttl data signal bus 4 dq1 i/o lvttl 5 dq2 i/o lvttl 7 dq3 i/o lvttl 8 dq4 i/o lvttl 10 dq5 i/o lvttl 11 dq6 i/o lvttl 13 dq7 i/o lvttl 42 dq8 i/o lvttl 44 dq9 i/o lvttl 45 dq10 i/o lvttl 47 dq11 i/o lvttl 48 dq12 i/o lvttl 50 dq13 i/o lvttl 51 dq14 i/o lvttl 53 dq15 i/o lvttl data mask 4/ 8 organization 39 dqm i/o lvttl data mask data mask 16 organization 39 udqm i/o lvttl data mask upper byte 15 ldqm i/o lvttl data mask lower byte ball no. name pin type buffer type function
data sheet rev. 1.32, 2007-10 7 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram power supplies 4/ 8/ 16 organization 9 v ddq pwr ? power supply 14 v dd pwr ? power supply 46 v ssq pwr ? power supply ground for dqs 41 v ss pwr ? power supply ground not connected 4 organization 2, 4, 7, 8, 10, 13, 15, 36, 40, 42, 45, 47, 48, 51, 53 nc nc ? not connected not connected 8 organization 4, 7, 10, 13, 15, 36, 40, 42, 45, 48, 51 nc nc ? not connected not connected 16 organization 36, 40 nc nc ? not connected ball no. name pin type buffer type function
data sheet rev. 1.32, 2007-10 8 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 2.2 package p(g)?tsopii?54 listed below are the pin outs of the tsop package. figure 1 pin configuration p(g)-tsopii-54 0 3 3 6 9 ' ' ' 4 9 ' ' 4 9 6 6 4 ' 4 ' 4 9 ' ' 4 ' 4 ' 4 ' 4 ' 4 9 6 6 4 ' 4 9 ' ' /' 4 0 : ( & $6 5 $6 & 6 % $ $ % $ $ $3 $ $ $ $ 9 ' ' 9 ' ' ' 4 9 ' ' 4 9 6 6 4 1 & ' 4 9 ' ' 4 1 & ' 4 1 & ' 4 9 6 6 4 1 & 9 ' ' 1 & : ( & $6 5 $6 & 6 % $ $ $3 $ $ $ $ 9 ' ' 9 ' ' 1 & 9 ' ' 4 9 6 6 4 1 & ' 4 9 ' ' 4 1 & 1 & 1 & ' 4 9 6 6 4 1 & 9 ' ' 1 & : ( & $6 5 $6 & 6 % $ $ $3 $ $ $ $ 9 ' ' 9 6 6 ' 4 9 6 6 4 9 ' ' 4 ' 4 ' 4 9 6 6 4 ' 4 ' 4 ' 4 ' 4 9 ' ' 4 ' 4 8 ' 4 0 & . & . ( 1 & $ $ $ $ $ $ $ $ 9 6 6 9 6 6 9 6 6 ' 4 9 6 6 4 9 ' ' 4 1 & ' 4 9 6 6 4 1 & ' 4 1 & ' 4 9 ' ' 4 1 & ' 4 0 & . & . ( 1 & $ $ $ $ $ $ $ $ 9 6 6 9 6 6 9 6 6 1 & 9 6 6 4 9 ' ' 4 1 & ' 4 9 6 6 4 1 & 1 & 1 & ' 4 9 ' ' 4 1 & ' 4 0 & . & . ( 1 & $ $ $ $ $ $ $ $ 9 6 6 9 6 6 [ [ [ $ % $ $ % $ 1 & $ 1 & $ 1 & $
data sheet rev. 1.32, 2007-10 9 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 3 functional description this chapter list all defined commands and t heir usage for this synchronous dram family. table 5 truth table: operation command operation device state cke n-1 1)2) 1) v = valid, x = don?t care, l = low level, h = high level 2) cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provide d. cke n 1)2) dqm 1)2) ba0 ba1 1)2) ap= a10 1)2) addr. 1)2) cs 1 )2) ras 1)2) cas 1 )2) we 1)2) bank active idle 3) 3) this is the state of the banks designated by ba0, ba1 signals. hxxvvvllhh bank precharge any h x x v l x l l h l precharge all any h x x x h x l l h l write active 3) hxxvlvlhll write with auto precharge active 3) hxxvhvlhll read active 3) hxxvlvlhlh read with auto precharge active 3) hxxvhvlhlh mode register set idle h x x v v v l l l l no operation any h x x x x x l h h h burst stop active h x x x x x l h h l device deselect any h x x x x x h x x x auto refresh idle h h x x x x l l l h self refresh entry idle h l x x x x l l l h self refresh exit idle (self refr.) l h x x x x h x x x lh h x power down/ clock suspend entry active or idle or burst hlxxxxhxxx lh h h power down/ clock suspend exit active or idle or burst lhxxxxhxxx lh h h data write/ output enable active h x l x x x x x x x data write/ output disable active h x h x x x x x x x
data sheet rev. 1.32, 2007-10 10 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram table 6 mode register definition (ba 1:0 = 00 b ) field bits type description bl 2:0 w burst length number of sequential bits per dq related to one read/write command note: all other bit combinations are reserved 000 b 1 001 b 2 010 b 4 011 b 8 111 b full page (sequential burst type only) bt 3 burst type 0 b sequential 1 b interleaved cl 6:4 cas latency number of full clocks from read command to first data valid window. note: all other bit combinations are reserved. 010 b 2 011 b 3 tm 8:7 test mode note: all other bit combinations are reserved. 00 b mode register set wbl 9 write burst length 0 b burst write 1 b single bit write 12:10 reserved, set to zero 03%6 %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ uhjdggu z zzz %7 %/ &/ 70 :%/
data sheet rev. 1.32, 2007-10 11 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram table 7 burst length and sequence notes 1. for a burst length of two, a1-ai selects the two-data-el ement block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai sele cts the four-data-elem ent block; a0-a1 selects the first access within the block. 3. for a burst length of eight, a3-ai selects the eight-data- el ement block; a0-a2 selects the first access with in the block. 4. whenever a boundary of the block is reached within a give n sequence above, the following access wraps within the block. burst length starting column address order of accesses within a burst a2 a1 a0 type=sequential type=interleaved 200?10?1 11?0 1?0 4 0 0 0?1?2?3 0?1?2?3 0 1 1?2?3?0 1?0?3?2 1 0 2?3?0?1 2?3?0?1 1 1 3?0?1?2 3?2?1?0 8 0 0 0 0?1?2?3?4?5?6?7 0?1?2?3?4?5?6?7 0 0 1 1?2?3?4?5?6?7?0 1?0?3?2?5?4?7?6 0 1 0 2?3?4?5?6?7?0?1 2?3?0?1?6?7?4?5 0 1 1 3?4?5?6?7?0?1?2 3?2?1?0?7?6?5?4 1 0 0 4?5?6?7?0?1?2?3 4?5?6?7?0?1?2?3 1 0 1 5?6?7?0?1?2?3?4 5?4?7?6?1?0?3?2 1 1 0 6?7?0?1?2?3?4?5 6?7?4?5?2?3?0?1 1 1 1 7?0?1?2?3?4?5?6 7?6?5?4?3?2?1?0 fullpage n cn, cn+1, cn+2 .... not supported
data sheet rev. 1.32, 2007-10 12 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 4 electrical characteristics 4.1 operating conditions table 8 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. parameter symbol limit values unit note/ test condition min. max. input / output volt age relative to v ss v in , v out ? 1.0 +4.6 v ? voltage on v dd supply relative to v ss v dd ?1.0 +4.6 v ? voltage on v ddq supply relative to v ss v ddq ?1.0 +4.6 v ? operating temperature for hyb... t a 0+70 c? operating temperature for hyi... t a -40 +85 c? storage temper ature range t stg -55 +150 c? power dissipation per sdram component p d ?1w? data out current (short circuit) i out ?50ma?
data sheet rev. 1.32, 2007-10 13 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram table 9 dc characteristics table 10 input and output capacitances parameter symbol values unit note/ test condition min. max. supply voltage v dd 3.0 3.6 v 1)2) 1) t a = 0 to 70 oc 2) all voltages are referenced to v ss i/o supply voltage v ddq 3.0 3.6 v 1)2) input high voltage v ih 2.0 v ddq +0.3 v 1)2)3) 3) v ih may overshoot to v ddq + 2.0 v for pulse width of < 4ns with 3.3 v. v il may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3 v. pulse width measured at 50% points with amplitude measured peak to dc reference. input low voltage v il ? 0.3 +0.8 v 1)2)3) output high voltage ( i out = ? 4.0 ma) v oh 2.4 ? v 1)2) output low voltage ( i out = 4.0 ma) v ol ?0.4 v 1)2) input leakage current, any input(0 v < v in < v dd , all other inputs = 0 v) i il ? 5 +5 a 1) output leakage current(dqs are disabled, 0 v < v out < v ddq ) i ol ? 5 +5 a 1) parameter symbol values 1) 1) capacitance values are shown for ts op-54 packages. capacitance values fo r tfbga packages are lower by 0.5 pf unit note min. max. input capacitances: ck c i1 2.5 3.5 pf 2) 2) t a = 0 to 70 oc; v dd , v ddq = 3.3 v 0.3 v, f = 1 mhz input capacitance (a0-a11, ba0, ba1, ras , cas , we , cs , cke, dqm) c i2 2.5 3.8 pf 2) input/output capacitance (dq) c i0 4.0 6.0 pf 2)
data sheet rev. 1.32, 2007-10 14 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram table 11 idd conditions table 12 i dd specifications and conditions parameter symbol operating current one bank active, burst length = 1 i dd1 precharge standby current in power down mode i dd2p recharge standby current in non-power down mode i dd2n no operating current active state (max. 4 banks) i dd3n i dd3p burst operating current read command cycling i dd4 auto refresh current auto refresh command cycling i dd5 self refresh current (standard components) self refresh mode, cke=0.2 v, t ck =infinity i dd6 self refresh current (low power components) self refresh mode, cke=0.2 v, t ck =infinity symbol ?7 unit note/ test condition max. i dd1 t rc = t rc(min) , i o = 0 ma 80 ma 1)2)3)4) 1) currents values will be added when available. 2) t a = 0 to 70 c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v 3) these parameters depend on the cycle rate. al l values are measured at 133 mhz for -7 with the outputs open. input signals are changed once during t ck . 4) these parameters are measured with continuous data stream during read ac cess and all dq toggling. cl=3 and bl=4 is assumed an d the v ddq current is excluded. i dd2p cs = v ih (min.) , cke v il(max) 2ma 1)2) i dd2n cs = v ih (min.) , cke v ih(min) 22 ma 1)2) i dd3n cs = v ih(min) , cke v ih(min.) 35 ma 1)2) i dd3p cs = v ih(min) , cke v il(max.) 5ma 1)2) i dd4 65 ma 1)2)4) i dd5 t rfc = t rfc(min) 146 ma 1)2)5) 5) t rfc = t rfc(min) ?burst refresh?, t rfc = 15.6 s ?distributed refresh?. t rfc = 15.6 s25ma 1)2) i dd6 3ma 1)2) standard components 0.8 ma 1) low power components at 85 c
data sheet rev. 1.32, 2007-10 15 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 4.2 ac characteristics table 13 ac timing - absolute specifications ?7 parameter symbol ?7 unit note pc133? 222 min. max. clock and clock enable clock frequency t ck 7 7.5 ? ? ns ns cl3 1)2)3) cl2 1)2)3) access time from clock t ac ? ? 5.4 5.4 ns ns cl3 1)2)3) cl2 1)2)3)4)5) clock high pulse width t ch 2.5 ? ns 1)2)3) clock low pulse width t cl 2.5 ? ns 1)2)3) transition time of clock (rise and fall) t t 0.3 1.2 ns 1)2)3) setup and hold times input setup time t is 1.5 ? ns 1)2)3)6) input hold time t ih 0.8 ? ns 1)2)3)6) cke setup time t cks 1.5 ? ns 1)2)3)6) cke hold time t ckh 0.8 ? ns 1)2)3)6) mode register set-up to active delay t rsc 2? t ck 1)2)3) power down mode entry time t sb 07 ns 1)2)3) common parameters row to column delay time t rcd 15 ? ns 1)2)3)7) row precharge time t rp 15 ? ns 1)2)3)7) row active time t ras 37 100k ns 1)2)3)7) row cycle time t rc 60 ? ns 1)2)3)7) row cycle time during auto refresh t rfc 63 ? ns 1)2)3) activate(a) to activa te(b) command period t rrd 14 ? ns 1)2)3)7) cas (a) to cas (b) command period t ccd 1? t ck 1)2)3) refresh cycle refresh period (4096 cycles) t ref ?64 ms 1)2)3) self refresh exit time t srex 1? t ck 1)2)3) data out hold time t oh 3? ns 1)2)3)5) read cycle data out to low impedance time t lz 0? ns 1)2)3) data out to high impedance time t hz 37 ns 1)2)3) dqm data out disable latency t dqz ?2 t ck 1)2)3)
data sheet rev. 1.32, 2007-10 16 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram figure 2 measurement conditions for t ac and t oh write cycle last data input to precharge (write without auto precharge) t wr 14 ? ns 1)2)3)8) last data input to activate(write with auto precharge) t dal(min.) t ck 1)2)3)9) dqm write mask latency t dqw 0? t ck 1)2)3) 1) t a = 0 to 70 c; v ss = 0 v; v dd , v ddq = 3.3 v 0.3 v, t t = 1 ns 2) for proper power-up see the operation section of this data sheet. 3) ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resi stive termination and with an input signal of 1v / ns edge rate between 0.8 v and 2.0 v. 4) if clock rising time is longer than 1 ns, a time (t t /2 - 0.5) ns has to be added to this parameter. 5) access time from clock t ac is 4.6 ns for pc133 components with no termination and 0 pf load,data out hold time t oh is 1.8 ns for pc133 components with no termination and 0 pf load. 6) if t t is longer than 1 ns, a time ( t t - 1) ns has to be added to this parameter. 7) these parameter account for the number of clock cycles and depend on the operating frequency of the clock, as follows:the num ber of clock cycles = specified value of timing per iod (counted in fracti ons as a whole number) 8) it is recommended to use two clock cycles between the last data- in and the precharge command in case of a write command witho ut auto- precharge. one clock c ycle between the last data-in and the precharge command is also supported, but restricted to cycle times t ck greater or equal the specified t wr value, where t ck is equal to the actual system clock time. 9) when a write command with auto precharge has been issued, a time of t dal(min) has be fullfilled before the next activate command can be applied. for each of the terms, if not alread y an integer, round up to the next highest integer. t ck is equal to the act ual system clock time. parameter symbol ?7 unit note pc133? 222 min. max. clock 2.4 v 0.4 v input is t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t ih t 1.4 v io.vsd 50 pf i/o measurement conditions for t ac and t oh
data sheet rev. 1.32, 2007-10 17 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 5 package outlines figure 3 package outline pg-tsopii-54-4 (top view) notes 1. drawing according to iso 8015 2. dimensions in mm 3. general tolerances +/- 0.15 * 3 ; ? ? ? ? ? ? [ ? 0 [ ? ? [ 6 ( $ 7, 1 * 3 /$1 ( ? ? ? * $ 8 * ( 3 /$1 ( 0 $; 0 $; ? , q g h [ 0 d u n l q j ' r h v q r w l q f o x g h g d p e d u s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h s o d v w l f s u r w u x v l r q r i p d [ s h u v l g h ' r h v q r w l q f o x g h s o d v w l f r u p h w d o s u r w u x v l r q r i p d [ s h u v l g h
data sheet rev. 1.32, 2007-10 18 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram figure 1 pin configuration p(g)-tsopii-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2 measurement conditions for t ac and t oh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3 package outline pg-tsopii-54-4 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 list of figures
data sheet rev. 1.32, 2007-10 19 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram table 1 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 ordering information for lead-containing products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3 ordering information for rohs compliant products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 4 pin configuration of the sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 5 truth table: operation command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6 mode register definition (ba 1:0 = 00 b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7 burst length and sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 10 input and output capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 11 idd conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 12 i dd specifications and conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 13 ac timing - absolute specifications ?7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 list of tables
data sheet rev. 1.32, 2007-10 20 10122006-i6lj-wv3h hy[b/i]39s128[40/80/16][0/7]f[e/t](l) 128-mbit synchronous dram 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 chip configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 package p(g)?tsopii?54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table of contents
edition 2007-10 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2007. all rights reserved. legal disclaimer the information given in this data sheet shall in no event be regarded as a guarantee of co nditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com data sheet

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