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1 ? fn7489.6 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2005, 2006. all rights reserved. all other trademarks mentioned are the property of their respective owners. isl59830 true single supply video driver the isl59830 is a revolutionary device that allows true single- supply operation of video amplifiers. the device runs off a single 3.3v supply and generates the required negative voltage internally. this allows for dc-accurate coupling of video onto a 75 double-terminated line. since the buffers have an integrated 6db gain, no external gain setting resistors are required. an input reference voltage can be supplied to shift the analog video level down by an amount equal to the reference (typically 0.6v). features ? triple single-supply buffer ? operates from single +3.3v supply ? no output dc blocking capacitor needed ? fixed gain of 2 output buffer ? output three-statable ? enable/disable function ? 50mhz 0.1db bandwidth ? 200mhz -3db bandwidth ? pb-free plus anneal available (rohs compliant) applications ? driving video pinout isl59830 (16 ld qsop) top view ordering information part number part marking tape & reel package pkg. dwg. # isl59830ia 59830ia - 16 ld qsop m16.15a ISL59830IA-T7 59830ia 7? 16 ld qsop m16.15a isl59830ia-t13 59830ia 13? 16 ld qsop m16.15a isl59830iaz (see note) 59830iaz - 16 ld qsop (pb-free) m16.15a isl59830iaz-t7 (see note) 59830iaz 7? 16 ld qsop (pb-free) m16.15a isl59830iaz-t13 (see note) 59830iaz 13? 16 ld qsop (pb-free) m16.15a note: intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish , which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classi fied at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 rin gin bin ref vee gnd veeout dgnd rout gout bout vcc en vcc nc dvcc data sheet may 4, 2006
2 fn7489.6 may 4, 2006 absolute maxi mum ratings (t a = 25c) v cc , supply voltage between v s and gnd . . . . . . . . . . . . . . . . .5v v in , v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . .vcc+0.3v, vee-0.3v voltage between v in and v ref . . . . . . . . . . . . . . . . . . . . . . . . . .2v maximum continuous output current . . . . . . . . . . . . . . . . . . . 30ma operating temperature . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c lead temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a ac electrical specifications v cc = dv cc = +3.3v, ref = gnd, t a = 25c, r l = 150 , unless otherwise specified. parameter description conditions min typ max unit bw -3db 3db bandwidth v out = 200mv pp 200 mhz v out = 2v pp 100 mhz bw 0.1db 0.1db bandwidth v out = 2v pp 50 mhz s r slew rate v out = 2v pp 500 v/s d g differential gain 0.07 % d p differential phase 0.06 x t hostile crosstalk 6mhz -90 db i input to output isolation 6mhz -70 db v n input noise voltage 20 nv/ hz fcp charge pump switch frequency 168 mhz load reg i ee = 0ma to 10ma 12 60 mv v ripple output amp ripple voltage 30 mv with bead core to dv cc 10 mv dc electrical specifications v cc = d vcc = +3.3v, ref = gnd, t a = 25c, r l = 150 , unless otherwise specified. parameter description conditions min typ max unit v+ supply range 3.0 3.6 v v g % gain error r l = 150 , v in = +2.5v to -1v 1.5 % g gain matching r l = 150 0.5 % r in input resistance v in = 0v to 1.5v 1.0 1.7 15 m v os output offset voltage v ref = 0 -25 7 +25 mv i out + output current r l = 10 , v in = 1.2v 50 ma i out - output current r l = 10 , v in = -0.3v -18 ma z out output impedance enabled 1 three-stated 10 m psrr power supply rejection ratio 60 90 db i s supply current amp enabled 120 150 ma amp disabled 80 ma r ref input reference resistor 4 5 6 k isl59830
3 fn7489.6 may 4, 2006 pin descriptions pin number pin name pin function equivalent circuit 1 rin analog input circuit 1 2 gin analog input reference circuit 1 3 bin analog input reference circuit 1 4 ref reference input circuit 2 5 vee chip substrate circuit 3 6 gnd analog ground 7 vee out charge pump output reference circuit 3 8 dgnd charge pump ground reference circuit 3 9 dvcc charge pump supply voltage reference circuit 3 10 nc not connected 11, 13 vcc positive power supply 12 en chip enable circuit 4 v ee v cc v ee v cc + - 3 ref r in g in b in r out g out b out -+ v ee v cc charge pump charge pump d vcc d gnd v ee out v ee v cc isl59830
4 fn7489.6 may 4, 2006 14 bout analog output circuit 5 15 gout analog output reference circuit 5 16 rout analog output reference circuit 5 pin descriptions (continued) pin number pin name pin function equivalent circuit v ee v cc typical performance curves figure 1. gain vs frequency for various r load figure 2. gain vs frequency for various c load figure 3. v ref pin output frequency respo nse figure 4. gain roll-off 3 2 1 0 -1 -2 -3 1m 10m 100m 1g frequency (hz) normalized gain (db) a v =+2 c l =0pf 1k 500 150 75 5 3 1 -1 -3 -5 100k 1m 100m 1g frequency (hz) normalized gain (db) a v =+2 r l =500 10m 9pf 0pf 2.2pf 4.7pf 5 -5 -15 -25 -30 -35 1 100 400 500 frequency (mhz) normalized output (db) a v =+2 c l =0pf r l =500 300 200 0 -10 -20 300 240 180 120 60 0 2.25 2.8 4.45 5 total supply voltage, v cc - v ee (v) gain roll-off (mhz) a v =+2 r l =500 3.9 -3db roll-off -0.1db roll-off 3.35 isl59830
5 fn7489.6 may 4, 2006 figure 5. peaking vs supply voltage figure 6. cross talk channel to channel (typical) figure 7. input to output isolation vs frequency figure 8. supply current vs supply voltage figure 9. bandwidth vs temperature fi gure 10. supply current vs temperature typical performance curves (continued) 1.6 1.2 0 2.2 2.4 4 supply voltage (v) peaking (db) 3.6 0.4 2.8 3.2 0.8 2.6 3.8 33.4 a v =+2 r l =500 c l =3.9pf -30 -40 -60 -80 -100 -120 100k 1m 100m 1g frequency (hz) cross talk (db) 10m -50 -70 -90 -110 enabled disabled a v =+2 r l =500 -20 -30 -50 -70 -90 -100 100k 1m 100m 1g frequency (hz) isolation (db) 10m -40 -60 -80 a v =+2 r l =500 120 80 40 0 1 1.5 3 3.5 supply voltage (v) supply current (ma) 2.5 100 60 20 2 a v =+2 r l =500 200 120 40 0 25 55 115 145 temperature (c) bandwidth (mhz) 85 160 80 a v =+2 r l =500 -3db -0.1db 95 90 80 75 25 55 145 temperature (c) supply current (ma) 85 85 a v =+2 r l =500 v cl =3.3v 115 isl59830
6 fn7489.6 may 4, 2006 figure 11. output impedance vs frequency fi gure 12. power supply rejection ratio vs frequency figure 13. voltage and current noise vs frequency figure 14. harmonic distortion vs frequency figure 15. figure 16. differential gain typical performance curves (continued) 100 1 0.01 10k 100k 100m frequency (hz) impedance ( ) 1m 10 0.1 10m -10 -30 -70 -110 1k 10k 100m frequency (hz) psrr (db) 10m -50 -90 100k 1m psrr+ psrr- 1k 100 1 0.1 10 100 10m frequency (hz) voltage noise (nv/ hz), current noise (pa/ hz) 1m 10 10k 100k e n 1k i n + i n - -30 -40 -90 -100 03040 fundamental frequency (mhz) harmonic distortion (dbc) 10 -50 20 -60 -70 -80 thd 3rd hd 2nd hd -30 -80 -90 thd (dbc) -40 -50 -60 -70 0.5 3 3.5 output voltage (v p-p ) 12 1.5 2.5 thd f in =10mhz thd f in =1mhz 0 -0.04 -0.08 ire differential gain (%) -0.02 -0.06 isl59830
7 fn7489.6 may 4, 2006 figure 17. differential phase figure 18. disable time figure 19. enable time figure 20. small signal rise & fall times figure 21. large signal rise & fall times figure 22. amp output noise (charge pump oscillation) typical performance curves (continued) 0 -0.04 ire differential phase () -0.02 -0.06 -0.08 volts (500mv/div) time (2s/div) volts (500mv/div) time (200ns/div) volts (50mv/div) time (10ns/div) volts (500mv/div) time (10ns/div) volts (10mv/div) time (20ns/div) isl59830
8 fn7489.6 may 4, 2006 figure 23. maximum output magnitude vs load resistance figure 24. backdrive voltage vs current amp disabled output loading figure 25. package power dissipation vs ambient temperature figure 26. package power dissipation vs ambient temperature typical performance curves (continued) 3.25 3 2.5 50 250 1050 load resistance ( ) output range (v) 850 2.75 450 650 a v =+2 c l =3.9pf 1.6 1.2 0 01 5 backdrive voltage (v) backdrive current (ma) 4 0.8 23 0.4 backdrive across 5 resistor typical channel vcc = 3.3v 791mw j a = 1 5 8 c / w q s o p 1 6 1.4 1.2 1 0.8 0.6 0.2 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-3 low effective thermal conductivity test board 0.4 - + - + - + charge pump 6db 6db 6db v cc y reference pb pr v ee v out = 2v in - v reference r in g in b in r out g out b out block diagram dv cc v ee-out j a = 1 1 2 c / w q s o p 1 6 1.8 1.6 1 0.8 0.6 0.2 0 0 255075100 150 ambient temperature (c) power dissipation (w) 125 85 jedec jesd51-7 high effective thermal conductivity test board 0.4 1.4 1.2 1.116w isl59830
9 fn7489.6 may 4, 2006 isl59830 + dc-restore solution c 9 0.1f c 15 c 14 c 13 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 rin gin bin ref vee gnd veeout dgnd rout gout bout vcc en vcc nc dvcc + r 1 75 r 2 75 r 3 75 v cc reference control r 4 75 r 5 75 r 6 75 v cc c 1 0.1f enable 1 3 2 0.1f c 16 1f v cc v cc v cc gnd 1 2 3 4 8 7 6 5 comp sync out comp video in vsync out gnd back porch out reset out vdd 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 in1 com1 nc1 v- gnd nc4 com4 in4 in2 com2 nc2 v+ nc (no connect) nc3 com3 in3 yo pb pr c 4 0.1f c 5 0.1f c 6 0.1f v ee (-1.6v) c 4 0.1f r 7 2k c 8 0.1f r 13 681k isl43140 el1881 isl59830 r 9 2k r 10 2k c 11 0.1f c 12 20pf 20pf 20pf yo pb pr 1k 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 rin gin bin ref vee gnd veeout dgnd rout gout bout vcc en vcc nc dvcc + r 1 75 r 2 75 r 3 75 v cc reference control c 7 1.0f r 4 75 r 5 75 r 6 75 v cc 0.1f enable 1 3 2 0.1f 1f v cc v cc v cc gnd 1 2 3 4 8 7 6 5 comp sync out comp video in vsync out gnd back porch out reset out vdd 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 in1 com1 v- com4 in4 in2 com2 v+ com3 in3 yo pb pr r 8 c 4 0.1f 0.1f 0.1f ref v ee (-1.6v) c 4 0.1f r 7 2k 0.1f isl43140 el1881 isl59830 r 9 2k 2k 0.1f 20pf 20pf 20pf yo pb pr 499 mmbp 3904 cn = option for lower charge pump noise option: panasonic 120 bead exc3bp121h lower amp output noise from charge pump c 10 0.1f r 11 r 12 d 1 1n4148 (or similar) isl59830
10 fn7489.6 may 4, 2006 demo board schematic description of operat ion and application information theory of operation the isl59830 is a highly practical and robust marriage of three high bandwidth, high speed, low power, rail-to-rail voltage feedback amplifiers with a charge pump, to provide a negative rail without an additional power supply. designed to operate with a single supply voltage range of from 0v to 3.3v, the isl59830 eliminates t he need for a split supply with the incorporation of a charge pump capable of generating a bottom rail as much as 1.6v below ground; for a 4.9v range on a single 3.3v supply. this performance is ideal for ntsc video with its negative-going sync pulses. the amplifier the isl59830 fabricated on a dielectrically isolated high speed 5v bi-cmos process with 4ghz pnps and npn transistor exceeding 20ghz - pe rfect for low distortion, low power demand and high frequency circuits. while the isl59830 utilizes somewhat standard voltage mode feedback topologies, there are many non-standard analog features providing its outstanding bandwidth, rail-to-rail operation, and output drive ca pabilities. the input signal initially passes through a folded cascode, a topology providing enhanced frequency response essentially by fixing the base collector voltage at the junction of the input and gain stage. the collector of eac h input device looks directly into an emitter that is tied closely to ground through a resistor and biased with a very stable dc source. since the voltage of this collector is "locked stable" the effective bandwidth limiting of the miller capacitance is greatly reduced. the signal is then passed through a second fully- realized differential gain stage and finally through a proprietary common emitter output stage for improved rail- to-rail output performance. the result is a highly-stable, low distortion, low power, and high frequency amplifier capable of driving moderately capacitive loads with near rail-to-rail performance. input output range the three amplifier channels have an input common mode voltage range from 0.15v below the bottom rail to within 100mv of the positive supply, v s + pin (note: bottom rail is established by the charge pu mp at negative one half the positive supply). as the input signal moves outside the specified range, the output sign al will exhibit increasingly higher levels of harmonic dist ortion. and of course, as load resistance becomes lower, the current drive capability of the device will be challenged and its ability to drive close to each rail is reduced. for instance, with a load resistance of 1k the output swing is within a 100 mv of the rails, while a load resistance of 150 limits the output swing to within around 300mv of the rails. amplifier output impedance to achieve near rail-to-rail per formance, the output stage of the isl59830 uses transistors in the common emitter configuration, typically pro ducing higher output impedance than the standard emitter fo llower output stage. the exceptionally high open loop gain of the isl59830 and local feedback reduces output impedance to less than a 2 at low frequency. however, since outp ut impedance of the device is 1.0f 1 2 3 4 16 15 14 13 5 6 7 12 11 10 8 9 rin gin bin ref vee gnd veeout dgnd rout gout bout vcc en vcc nc dvcc red_in green_in blue_in r 1 75 r 2 75 r 3 75 v cc reference control c 4 c 2 0.1f r 4 75 r 5 75 r 6 75 v cc red_out green_out blue_out c 3 0.1f enable 1 3 2 c 5 0.1f v cc 1k 1k 499 option: panasonic 120 bead exc3bp121h lower amp output noise from charge pump r 7 r 8 r 4 v cc d 1 1n4148 (or similar) isl59830
11 fn7489.6 may 4, 2006 exponentially modulated by the magnitude of the open loop gain, output impedance increases with frequency as the open loop gain decreases with frequency. this inductive-like effect of the output impedance is countered in the isl59830 with proprietary output stage topology, keeping the output impedance low over a wide frequency range and making it possible to easily and effect ively drive relatively heavy capacitive loads.(see figure 11). the charge pump the isl59830 charge pump provides a bottom rail up to 1.65v below ground while operating on a 0v to 3.3v power supply. the charge pump is internally regulated to one-half the potential of the positive supply. this internal multi-phase charge pump is driven by a 160mhz differential ring oscillator driving a series of inverters and charge storage circuitry. each series inverter charges and places parallel adjoining charge circuitry slightly out of phase with the immediately preceding block. the overall effect is sequential discharge and generation of a very low ripple of about 10mv that is applied to the amplifiers providing a negative rail of up to -1.65v. there are two options to reduc e the output supply noise. ? add a 120 bead in series between v cc and dv cc to further reduce ripple. add a 20pf capacitor between the back load 75 resistor and ground (see the isl59830a + dc-restore solution schematic on page 10). the system operates at sufficiently high frequencies that any related charge pump noise is far beyond standard video bandwidth requirements. still, appropriate bypassing discipline must be observed, and a ll pins related to either the power supply or the charge pump must be properly bypassed. see "power supply bypassing and printed circuit board layout" in this section. to maximize resistance to latch-up, a diode should be added between the veeout pin (anode) and gnd (cathode), as shown in the demo board schematic. this prevents vee from rising more than 0.7v above ground during startup. (vee > 1v above gnd can ca use latchup under some conditions.) i n + i n - bias out figure 27. volts (10mv/div) time (20ns/div) figure 28. charge pump oscillation (amp output) isl59830
12 fn7489.6 may 4, 2006 the v ref pin applying a voltage to the v ref pin simply places that voltage on what would usually be the ground side of the gain resistor of the amplifier, resu lting in a dc-level shift of the output signal. applying 100mv to the vref pin would apply a -100mv dc level shift to the outgoing signal. the charge pump provides sufficient bottom room to accommodate the shifted signal. v ref may be connected to ground for back porch at ground. note: the v ref input is the common point of the 3 amps minus input resistors. an y common resistance on v ref input will share the voltage induc ed on it with all the other amps, so using a resistor source to get offset will cause cross talk and gain change for the offset for all amps and amp +input gain change. offset on the v ref pin must be low impedance to prevent gain error and cross talk. a transistor emitter follower should work like an npn mmbt3904 with the emitter connected to the v ref pin and 1k pull down to v- with 1f cap bypass to ground and the collector to v+ and base to v offset source. if better tempco is needed then a diode may be used in series with the pot to ground. a 499 resistor may be added in series with the collector to prevent damage when testing. see the block diagram on page 8. the v ee pin the v ee pin is the output pin for the charge pump. a voltmeter applied to this pin will display the output of the charge pump. this pin does not affect the functionality of the part. one may use this pin as an additional voltage source. keep in mind that the output of this pin is generated by the internal charge pump and a fully regulated supply that must be properly bypassed. we recommend a 0.1f ceramic capacitor placed as close to the pin and connected to the ground plane of the board. input, output, and supply voltage range the isl59830 is designed to operate with a single supply voltage range of from 0v to 3.3v. the need for a split supply has been eliminated with the inco rporation of a charge pump capable of generating a bottom rail as much as 1.6v below ground, for a 4.9v range on a single 3.3v supply. this performance is ideal for ntsc video with its negative-going sync pulses. video performance for good video performance, an amplifier is required to maintain the same output impedance and the same frequency and phase response as dc levels are changed at the output. this is especially difficult when driving a standard video load of 150 because of the change in output current with changing dc levels. special circuitry has been incorporated into the isl59830 for the reduction of output impedance variation with the current output. this results in outstanding differential gain and differential phase specifications of 0.06% and 0.1, while driving 150 at a gain of +2. driving higher impedance loads would result in similar or better differential gain and differential phase performance. ntsc the isl59830, generating a negativ e rail internally, is ideally suited for ntsc video with its accompanying negative-going sync signals; easily handled by the isl59830 without the need of an additional supply as the isl59830 generates a negative rail with an internal charge pump referenced at negative 1/2 the positive supply. ypbpr ypbpr signals originating from a dvd player requiring three channels of very tightly-controlled amplifier gain accuracy present no difficulty for the isl59830. specifically, this standard encodes sync on the y channel and it is a negative- going signal; easily handled by the isl59830 without the need of an additional supply as the isl59830 generates a negative rail placed at negative 1/2 the positive supply. additionally, the pb and pr are bipolar analog signals and the video signals are negative-going; and again easily handled by the isl59830. driving capacitive loads and cables the isl59830, internally-compensated to drive 75 cables, will drive 10pf loads in parallel with 1k with less than 5db of peaking. if less peaking is re quired, a small series resistor, usually between 5 to 50 , can be placed in series with the output. this will reduce peakin g at the expense of a slight closed loop gain reduction. when used as a cable driver, double termination is always recommended for reflection- free performance. for those applications, a back-termination series resistor at the amplif ier's output will isolate the amplifier from the cable and allow extensive capacitive drive. however, other applications may have high capacitive loads without a back-termination resi stor. again, a small series resistor at the output can help to reduce peaking. the isl59830 is a triple amplifier designed to drive three channels; simply deal with each channel separately as described in this section. dc-restore when the isl59830 is ac-coupled it becomes necessary to restore the dc reference for the signal. this is accomplished with a dc-restore system applie d between the capacitive "ac" coupling and the input of the device. refer to application circuit for reference dc-restore solution. amplifier disable the isl59830 can be disabled and its output placed in a high impedance state. the turn-off time is around 25ns and the turn-on time is around 200ns. when disabled, the amplifier's supply current is reduced to 80ma typically, reducing power consumption. the amplifier's power-down can be controlled by standard ttl or cmos signal levels at isl59830
13 fn7489.6 may 4, 2006 the en pin. the applied logic signal is relative to gnd pin. letting the en pin float or applying a signal that is less than 0.8v above gnd will enable the amplifier. the amplifier will be disabled when the signal at en pin is 2v above gnd. the v ee charge pump remains active. output drive capability the isl59830 does not have internal short-circuit protection circuitry. a short-circuit current of 80ma sourcing and 150ma sinking for the output is conn ected to half way between the rails with a 10 resistor. if the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. maximum reliability is maintained if the output current never exceed s 40ma, after which the electro-migration limit of the process will be exceeded and the part will be damaged. this lim it is set by the design of the internal metal interconnections. power dissipation with the high output drive capa bility of the isl59830, it is possible to exceed the 150c absolute maximum junction temperature under certain load current conditions. therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. the maximum power dissipation allowed in a package is determined according to: where: t jmax = maximum junction temperature t amax = maximum ambi ent temperature ja = thermal resistance of the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the load, or: for sourcing: for sinking: where: v s = supply voltage i smax = maximum quiescent supply current v out = maximum output voltage of the application r load = load resistance tied to ground i load = load current i = number of output channels by setting the two p dmax equations equal to each other, we can solve the output current and r load to avoid the device overheat. power supply bypassing and printed circuit board layout strip line design techniques are recommended for the input and output signal traces. as with any high frequency device, a good printed circuit board layout is necessary for optimum performance. lead lengths should be as short as possible. the power supply pin must be well bypassed to reduce the risk of oscillation. for normal single supply operation, where the v s - pin is connected to the ground plane, a single 4.7f tantalum capacitor in parallel with a 0.1f ceramic capacitor from v s + to gnd will suffice. this same capacitor combination should be placed at each supply pin to ground if split-internal supplies are to be used. in this case, the v s - pin becomes the negative supply rail. for good ac performance, parasitic capacitance should be kept to a minimum. use of wire-wound resistors should be avoided because of their additional series inductance. use of sockets should also be avoided if possible. sockets add parasitic inductance and capacitance can result in compromised performance. minimizing parasitic capacitance at the amplifier's inverting input pin is also very important. pd max t jmax t amax ? ja -------------------------------------------- - = pd max v s i smax v s v out i ? () + v out i r l i ----------------- = pd max v s i smax v out iv s ? () + i load i = isl59830
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7489.6 may 4, 2006 isl59830 shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of ?b? dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink small outline plastic package (0.150? wide body) symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 0 8 0 8 - rev. 2 6/04

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