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32 rev.2.00 revision date: sep. 27, 2007 www.renesas.com renesas 32-bit risc microcomputer superh tm risc engine family/sh7100 series SH7101 hd6437101 SH7101 hardware manual rej09b0394-0200
rev.2.00 sep. 27, 2007 page ii of xxxiv rej09b0394-0200 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials
rev.2.00 sep. 27, 2007 page iii of xxxiv rej09b0394-0200 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products.
rev.2.00 sep. 27, 2007 page iv of xxxiv rej09b0394-0200 configuration of this manual this manual comprises the following items: 1. general precautions on handling of product 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional descrip tion of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that include s this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. index
rev.2.00 sep. 27, 2007 page v of xxxiv rej09b0394-0200 preface the SH7101 single-chip risc (reduced instruction set computer) microcomputer includes a renesas technology-original risc cpu as its co re, and the peripheral functions required to configure a system. target users: this manual was written for users who will be using this lsi in the design of application systems. users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of this lsi to the above users. refer to the sh-1/sh-2/sh-dsp software manual for a detailed description of the instruction set. notes on reading this manual: ? product names the following products are covered in this manual. product classifications and abbreviations basic classification on-chip rom classification part no. SH7101 (80-pin version) mask rom version (rom: 32 kbytes) hd6437101 in this manual, the product abbreviations are used to distinguish products. for example, products are collectively referred to as the SH7101. ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripher al functions and elect rical characteristics. ? in order to understand the details of the cpu's functions read the sh-1/sh-2/sh-dsp software manual. ? in order to understand the details of a register when the user knows its name read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bit names, and initial values of the registers are summarized in section 18, list of registers.
rev.2.00 sep. 27, 2007 page vi of xxxiv rej09b0394-0200 rules: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb (most significant bit) is on the left and the lsb (least significant bit) is on the right. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ SH7101 manuals: document title document no. SH7101 hardware manual this manual sh-1/sh-2/sh-dsp software manual rej09b0171-0500 users manuals for development tools: document title document no. superh c/c++ compiler, assembler, optimizing linkage editor user's manual rej10b0047-0100 superh risc engine simulator/debugger (for windows) user's manual rej10b0210-0300 high-performance embedded workshop user's manual rej10j1554-0100 application notes: document title document no. superh risc engine c/c++ compiler package application note rej05b0463-0400
rev.2.00 sep. 27, 2007 page vii of xxxiv rej09b0394-0200 main revisions for this edition item page revision (see manual for details) all ? ? company name and brand names amended (before) hitachi, ltd. (after) renesas technology corp. 6.5 interrupt exception processing vectors table table 6.2 interrupt exception processing vectors and priorities 79 table amended interrupt source name mtu channel 3 tgia_3 tgib_3 tgic_3 tgid_3 tciv_3 7.5.1 bus control register 1 (bcr1) 89 bit table amended bit bit name initial value r/w description 14 ? 1 r reserved these bits are always read as 1 and should always be written to 1. 8.1 features figure 8.1 block diagram of mtu 94 title and figure amended interrupt request signals channel 3: channel 4: tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tgi4c tgi4d tci4v 8.3.3 timer i/o control register (tior) table 8.13 tiorl_0 (channel 0) 109 table amended description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tioc0c pin funct ion 0 0 0 0 output disable 1 output compare register * initial output is 0 0 output at compare matc h 8.4.4 cascaded operation table 8.30 cascaded combinations 149 note amended note: when phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and the counters operates independently in phase counting mode.
rev.2.00 sep. 27, 2007 page viii of xxxiv rej09b0394-0200 item page revision (see manual for details) 8.4.4 cascaded operation figure 8.18 cascaded operation setting procedure 149 figure amended [1] set bits tpsc2 to tpsc0 in the channel 1 tcr to b'111 to select tcnt_2 overflow/ underflow counting. 8.4.8 complementary pwm mode example of complementary pwm mode setting procedure: 170 description amended 10. set enabling/disabling of pwm waveform output pin output in the timer output master enable register (toer). 11. set bits cst3 and cst4 in tstr to 1 simultaneously to start the count operation. complementary pwm mode output protection function: 192 description amended ? register and counter miswrite prevention function with the exception of the buffer registers, which can be rewritten at any time, access by the cpu can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary pwm mode by means of bit 13 in the bus controller's bus control register 1 (bcr1). some registers in channels 3 and 4 concerned are listed below: total 21 registers of tcr_3 and tcr_4; tmdr_3 and tmdr_4; tiorh_3 and tiorh_4; tiorl_3 and tiorl_4; tier_3 and tier_4; tcnt_3 and tcnt_4; tgra_3 and tgra_4; tgrb_3 and tgrb_4; toer; tocr; tgcr; tcdr; and tddr. this function enables the cpu to prevent miswriting due to the cpu runaway by disabling cpu access to the mode registers, control registers, and counters. in access disabled state, an undefined value is read from the registers concerned, and cannot be modified. 8.5.1 interrupts and priorities underflow interrupt: 194 description amended an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the mtu has two underflow interrupts, one each for channels 1 and 2.
rev.2.00 sep. 27, 2007 page ix of xxxiv rej09b0394-0200 item page revision (see manual for details) 8.7.15 overflow flags in reset sync pwm mode figure 8.81 reset sync pwm mode overflow flag 216 figure amended tgra_3 (h'ffff) h'0000 tcfv_3 tcfv_4 tcnt_3 = tcnt_4 counter cleared by compare match 3a not set not set 8.7.21 simultaneous input capture of tcnt_1 and tcnt_2 in cascade connection 219 description amended when timer counters 1 and 2 (tcnt_1 and tcnt_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to tioc1a and tioc2a or to tioc1b and tioc2b. this is because the input timing of tioc1a and tioc2a or of tioc1b and tioc2b may not be the same when external input-capture signals to be input into tcnt_1 and tcnt_2 are taken in synchronization with the internal clock. for example, tcnt_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from tcnt_2 (the counter for lower 16 bits) but captures the count value before the count-up. in this case, the values of tcnt_1 = h'fff1 and tcnt_2 = h'0000 should be transferred to tgra_1 and tgra_2 or to tgrb_1 and tgrb_2, but the values of tcnt_1 = h'fff0 and tcnt_2 = h'0000 are erroneously transferred.
rev.2.00 sep. 27, 2007 page x of xxxiv rej09b0394-0200 item page revision (see manual for details) 8.9.5 usage note 262 description added (1) symptom (a) regarding the poenf * 1 bits if setting of the poenf bits in the input level control/status registers (icsr1 and icsr2) by the hardware*2 and reading from these bits occur simultaneously, ?0? will be read, where ?1? should be read. furthermore, if clearing of these bits is attempted subsequent to the above condition, the clearing should be ignored*3 but it will be carried out. notes: * 1 for the sh7046-series and sh7047-series, n = 0 to 6; for the sh7144-series, n = 0 to 3. * 2 the poenf bits are set when the signals input to the respective poen pins satisfy the conditions that are specified by the poenm1 and poenm0 of the icsr1 and icsr2. * 3 the correct operation is that clearing of the poenf bits is only possible after ?1? is read from them in order to prevent accidental clearing. (b) regarding the osf bit the same symptom applies to the osf bits of the output level control/status register (ocsr). (2) to avoid this problem please clear the poenf bits or the osf bit in these steps: first execute a read for icsr1, icsr2, or ocsr, then write ?0? to the bits that had a read value of ?1? to clear them while writing ?1? to other bits. if this procedure is not followed, the poenf bits and the osf bit may be cleared unexpectedly if their setting by hardware and reading occur simultaneously. 10.3.2 receive data register (rdr) 280 description added ... rdr cannot be written to by the cpu. the initial value of rdr is h'00. 10.3.4 transmit data register (tdr) 280 description added ... although tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. the initial value of tdr is h'ff.
rev.2.00 sep. 27, 2007 page xi of xxxiv rej09b0394-0200 item page revision (see manual for details) 11.1 features 325 description added ? conversion time: 6.7 s per channel (at p = 20-mhz operation) 5.4 s per channel (at p = 25-mhz operation) 11.7.2 permissible signal source impedance 340 description amended this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less, or 3 k or less. this specification is provided to enable the a/d converter's sample- and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k or 3 k , charging may be insufficient and it may not be possible to guarantee a/d conversion accuracy. ... 17.3.1 sleep mode notes on using sleep mode 395 description added ? there are 4 conditions to clear sleep mode. (1) clearing by an interrupt (2) clearing by dtc address error (3) clearing by the power-on reset (4) clearing by the manual reset when clearing sleep mode by (1) or (2), cpu may run out of control. please clear sleep mode by (3) or (4), don't use (1) or (2). ? do not use dtc module or aud module during sleep mode.
rev.2.00 sep. 27, 2007 page xii of xxxiv rej09b0394-0200 all trademarks and registered trademarks are the property of their respective owners.
rev.2.00 sep. 27, 2007 page xiii of xxxiv rej09b0394-0200 contents section 1 overview............................................................................................... 1 1.1 features ....................................................................................................................... ........... 1 1.2 internal block diagram......................................................................................................... .3 1.3 pin arrangement ................................................................................................................ .... 4 1.4 pin functions .................................................................................................................. ....... 5 1.5 differences from sh7046 group ........................................................................................... 9 section 2 cpu..................................................................................................... 11 2.1 features ....................................................................................................................... ......... 11 2.2 register configuration......................................................................................................... 11 2.2.1 general registers (rn)............................................................................................ 13 2.2.2 control registers .................................................................................................... 13 2.2.3 system registers ..................................................................................................... 14 2.2.4 initial values of registers....................................................................................... 15 2.3 data formats ................................................................................................................... ..... 15 2.3.1 data format in registers......................................................................................... 15 2.3.2 data formats in memory ........................................................................................ 16 2.3.3 immediate data format .......................................................................................... 16 2.4 instruction features........................................................................................................... ... 17 2.4.1 risc-type instruction set...................................................................................... 17 2.4.2 addressing modes .................................................................................................. 20 2.4.3 instruction format................................................................................................... 24 2.5 instruction set ................................................................................................................ ...... 26 2.5.1 instruction set by classification ............................................................................. 26 2.6 processing states.............................................................................................................. .... 41 2.6.1 state transitions...................................................................................................... 41 section 3 mcu operating modes....................................................................... 43 3.1 selection of operating modes.............................................................................................. 43 3.2 input/output pins .............................................................................................................. ... 44 3.3 explanation of operating modes ......................................................................................... 44 3.3.1 mode 3 (single chip mode)..................................................................................... 44 3.3.2 clock m ode............................................................................................................. 44 3.4 address map .................................................................................................................... .... 45 3.5 initial state of this lsi...................................................................................................... .. 46 section 4 clock pulse generator ........................................................................ 47 4.1 oscilla tor..................................................................................................................... ......... 47
rev.2.00 sep. 27, 2007 page xiv of xxxiv rej09b0394-0200 4.1.1 connecting crystal resonator ................................................................................ 47 4.1.2 external clock input method.................................................................................. 49 4.2 function for detecti ng oscillator halt................................................................................. 49 4.3 usage notes .................................................................................................................... ..... 50 4.3.1 note on crystal resonator ...................................................................................... 50 4.3.2 notes on board design ........................................................................................... 50 section 5 exception processing...........................................................................53 5.1 overview....................................................................................................................... ....... 53 5.1.1 types of exception processing and priority ........................................................... 53 5.1.2 exception processing operations............................................................................ 54 5.1.3 exception processing vector table ........................................................................ 55 5.2 resets ........................................................................................................................ ........ 57 5.2.1 types of reset ........................................................................................................ 57 5.2.2 power-on reset ...................................................................................................... 57 5.2.3 manual reset .......................................................................................................... 58 5.3 address errors ................................................................................................................. .... 59 5.3.1 cause of address error exception.......................................................................... 59 5.3.2 address error exception processing....................................................................... 60 5.4 interrupts..................................................................................................................... ......... 60 5.4.1 interrupt sources..................................................................................................... 60 5.4.2 interrupt priority level ........................................................................................... 61 5.4.3 interrupt exception processing ............................................................................... 61 5.5 exceptions triggered by instructions .................................................................................. 62 5.5.1 types of exceptions tri ggered by inst ructions ...................................................... 62 5.5.2 trap instructions ..................................................................................................... 62 5.5.3 illegal slot instructions ........................................................................................... 63 5.5.4 general illegal instructions..................................................................................... 63 5.6 cases when exception sour ces are not accepted ............................................................... 64 5.6.1 immediately after delayed branch instruction ....................................................... 64 5.6.2 immediately after interrupt -disabled instruction ................................................... 64 5.7 stack status after exception processing ends ..................................................................... 65 5.8 usage notes .................................................................................................................... ..... 66 5.8.1 value of stack pointer (sp) .................................................................................... 66 5.8.2 value of vector base register (vbr) .................................................................... 66 5.8.3 address errors caused by stacking of address error exception processing......... 66 section 6 interrupt controller (intc).................................................................67 6.1 features....................................................................................................................... ......... 67 6.2 input/output pins .............................................................................................................. ... 68
rev.2.00 sep. 27, 2007 page xv of xxxiv rej09b0394-0200 6.3 register descriptions .......................................................................................................... .68 6.3.1 interrupt control register 1 (icr1)........................................................................ 69 6.3.2 interrupt control register 2 (icr2)........................................................................ 70 6.3.3 irq status register (isr)....................................................................................... 72 6.3.4 interrupt priority regi sters a, d to i (ipra, iprd to ipri) .................................. 73 6.4 interrupt sources .............................................................................................................. .... 75 6.4.1 external interrupts .................................................................................................. 75 6.4.2 on-chip peripheral mo dule interrupts ................................................................... 77 6.5 interrupt exception processing vectors table..................................................................... 77 6.6 operation...................................................................................................................... ........ 81 6.6.1 interrupt sequence .................................................................................................. 81 6.6.2 stack after interrupt exception processing ............................................................. 83 6.7 interrupt res ponse ti me ...................................................................................................... 84 section 7 bus state controller (bsc)................................................................. 87 7.1 features ....................................................................................................................... ......... 87 7.2 input/output pin............................................................................................................... ..... 87 7.3 register ....................................................................................................................... ......... 87 7.4 address map .................................................................................................................... .... 88 7.5 register description........................................................................................................... .. 89 7.5.1 bus control regist er 1 (b cr1) .............................................................................. 89 7.6 on-chip peripheral i/o register access .............................................................................. 90 section 8 multi-function timer pulse unit (mtu) ........................................... 91 8.1 features ....................................................................................................................... ......... 91 8.2 input/output pins .............................................................................................................. ... 95 8.3 register descriptions .......................................................................................................... .96 8.3.1 timer control register (tcr) ................................................................................ 98 8.3.2 timer mode register (tmdr) ............................................................................. 102 8.3.3 timer i/o control register (tior) ...................................................................... 104 8.3.4 timer interrupt enable register (tier) ............................................................... 122 8.3.5 timer status register (tsr)................................................................................. 124 8.3.6 timer counter (tcnt)......................................................................................... 126 8.3.7 timer general register (tgr) ............................................................................. 127 8.3.8 timer start register (tstr)................................................................................. 127 8.3.9 timer synchro register (tsyr) .......................................................................... 128 8.3.10 timer output master enable register (toer) .................................................... 130 8.3.11 timer output control register (tocr) ............................................................... 131 8.3.12 timer gate control register (tgcr)................................................................... 133 8.3.13 timer subcounter (tcnts) ................................................................................. 135
rev.2.00 sep. 27, 2007 page xvi of xxxiv rej09b0394-0200 8.3.14 timer dead time data register (tddr)............................................................. 135 8.3.15 timer period data register (tcdr) .................................................................... 135 8.3.16 timer period buffer register (tcbr) .................................................................. 135 8.3.17 bus master interface ............................................................................................. 136 8.4 operation ...................................................................................................................... ..... 137 8.4.1 basic functions..................................................................................................... 137 8.4.2 synchronous op eration......................................................................................... 142 8.4.3 buffer operation ................................................................................................... 145 8.4.4 cascaded operation .............................................................................................. 149 8.4.5 pwm modes ......................................................................................................... 150 8.4.6 phase counting mode........................................................................................... 156 8.4.7 reset-synchronized pwm mode.......................................................................... 163 8.4.8 complementary pwm mode................................................................................ 167 8.5 interrupt sources.............................................................................................................. .. 192 8.5.1 interrupts and priorities......................................................................................... 192 8.5.2 a/d converter activation..................................................................................... 194 8.6 operation timing............................................................................................................... 195 8.6.1 input/output timing ............................................................................................. 195 8.6.2 interrupt signal timing......................................................................................... 200 8.7 usage notes .................................................................................................................... ... 204 8.7.1 module standby mode setting ............................................................................. 204 8.7.2 input clock re strictions ....................................................................................... 204 8.7.3 caution on period setting ..................................................................................... 205 8.7.4 contention between tcnt write and clear operations...................................... 205 8.7.5 contention between tcnt write and increment operations............................... 206 8.7.6 contention between tgr write and compare match .......................................... 207 8.7.7 contention between buffer regist er write and compare match ......................... 208 8.7.8 contention between tgr read and input capture............................................... 210 8.7.9 contention between tgr write and input capture.............................................. 211 8.7.10 contention between buffer regist er write and i nput capt ure ............................. 212 8.7.11 tcnt_2 write and overflow/underflow c ontention in cascade connection .... 212 8.7.12 counter value during comple mentary pwm m ode stop .................................... 214 8.7.13 buffer operation setting in complementary pwm mode ................................... 214 8.7.14 reset sync pwm mode buffer oper ation and compare match flag .................. 215 8.7.15 overflow flags in reset sync pwm mode.......................................................... 216 8.7.16 contention between overflow/underflow and counter clearing......................... 217 8.7.17 contention between tcnt write and overflow/underflow................................ 218 8.7.18 cautions on transition from normal operation or pwm mode 1 to reset-synchronous pwm mode........................................................................... 218
rev.2.00 sep. 27, 2007 page xvii of xxxiv rej09b0394-0200 8.7.19 output level in complementary pwm mode and reset-synchronous pwm mode........................................................................... 219 8.7.20 interrupts in m odule standby mode ..................................................................... 219 8.7.21 simultaneous input capture of tcnt_1 and tcnt_2 in cascade connection... 219 8.8 mtu output pin initialization ........................................................................................... 220 8.8.1 operating modes................................................................................................... 220 8.8.2 reset start operation ............................................................................................ 220 8.8.3 operation in case of re-setting due to error during operation, etc. ................. 221 8.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ................................................................ 222 8.9 port output enable (poe).................................................................................................. 252 8.9.1 features................................................................................................................. 252 8.9.2 pin configuration.................................................................................................. 254 8.9.3 register configuration.......................................................................................... 254 8.9.4 operation .............................................................................................................. 259 8.9.5 usage note............................................................................................................ 262 section 9 watchdog timer ............................................................................... 263 9.1 features ....................................................................................................................... ....... 263 9.2 input/output pin............................................................................................................... .. 264 9.3 register descriptions ......................................................................................................... 2 65 9.3.1 timer counter (tcnt)......................................................................................... 265 9.3.2 timer control/status register (tcsr) ................................................................. 266 9.3.3 reset control/status register (rstcsr) ............................................................. 268 9.4 operation...................................................................................................................... ...... 269 9.4.1 watchdog time r mode ......................................................................................... 269 9.4.2 interval timer mode ............................................................................................. 271 9.4.3 clearing software standby mode ......................................................................... 271 9.4.4 timing of setting the ove rflow flag (ovf) ........................................................ 272 9.4.5 timing of setting the watchdog ti mer overflow flag (wovf)......................... 272 9.5 interrupt source............................................................................................................... ... 273 9.6 usage notes .................................................................................................................... ... 273 9.6.1 notes on register access...................................................................................... 273 9.6.2 tcnt write and increment contention................................................................ 275 9.6.3 changing cks2 to cks0 bit values.................................................................... 275 9.6.4 changing between watchdog timer/ interval timer modes................................. 275 9.6.5 system reset by wdtovf signal....................................................................... 276 9.6.6 internal reset in watchdog time r mode.............................................................. 276 9.6.7 manual reset in wa tchdog timer mode .............................................................. 276 9.6.8 notes on using wdtovf pin.............................................................................. 276
rev.2.00 sep. 27, 2007 page xviii of xxxiv rej09b0394-0200 section 10 serial communication interface (sci) ............................................277 10.1 features....................................................................................................................... ....... 277 10.2 input/output pins .............................................................................................................. . 279 10.3 register descriptions ......................................................................................................... 2 79 10.3.1 receive shift register (rsr) ............................................................................... 280 10.3.2 receive data register (rdr) ............................................................................... 280 10.3.3 transmit shift register (tsr) .............................................................................. 280 10.3.4 transmit data register (tdr).............................................................................. 280 10.3.5 serial mode register (smr) ................................................................................ 281 10.3.6 serial control re gister (scr)............................................................................... 283 10.3.7 serial status register (ssr) ................................................................................. 285 10.3.8 serial direction contro l register (sdcr)............................................................ 287 10.3.9 bit rate register (brr) ....................................................................................... 287 10.4 operation in async hronous mode ..................................................................................... 296 10.4.1 data transfer format............................................................................................ 296 10.4.2 receive data sampling timi ng and reception margin in asynchro nous mo de ......................................................................................... 298 10.4.3 clock..................................................................................................................... 299 10.4.4 sci initialization (as ynchronous mode).............................................................. 300 10.4.5 data transmission (as ynchronous mode)............................................................ 301 10.4.6 serial data reception (a synchronous mode)....................................................... 303 10.5 multiprocessor communication function.......................................................................... 307 10.5.1 multiprocessor serial da ta transmission ............................................................. 309 10.5.2 multiprocessor serial data reception .................................................................. 310 10.6 operation in clocked synchronous mode ......................................................................... 313 10.6.1 clock..................................................................................................................... 313 10.6.2 sci initialization (clocked synchronous mode).................................................. 314 10.6.3 serial data transmission (clo cked synchron ous mode ) ..................................... 315 10.6.4 serial data reception (clock ed synchronous mode)........................................... 318 10.6.5 simultaneous serial data transmission and reception (clocked synchr onous m ode) .............................................................................. 320 10.7 interrupts sources ............................................................................................................. . 322 10.7.1 interrupts in normal serial communication interface mode ............................... 322 10.8 usage notes .................................................................................................................... ... 323 10.8.1 tdr write and tdre flag .................................................................................. 323 10.8.2 module standby mode setting ............................................................................. 323 10.8.3 break detection and processing (asynchronous mode only).............................. 323 10.8.4 sending a break signal (asynchronous mode only) ........................................... 323 10.8.5 receive error flags and transmit operations (clocked synchron ous mode only) ..................................................................... 324
rev.2.00 sep. 27, 2007 page xix of xxxiv rej09b0394-0200 10.8.6 cautions on clocked synchro nous external clock mode .................................... 324 10.8.7 caution on clocked synchronous internal clock mode....................................... 324 section 11 a/d converter................................................................................. 325 11.1 features ....................................................................................................................... ....... 325 11.2 input/output pins .............................................................................................................. . 327 11.3 register descriptions ......................................................................................................... 3 28 11.3.1 a/d data registers 8 to 15 (addr8 to addr15) .............................................. 328 11.3.2 a/d control/status registers_0 and _1 (adcsr_0 and adcsr_1) .................. 329 11.3.3 a/d control registers_0 a nd _1 (adcr_0 a nd adcr_1).................................. 330 11.3.4 a/d trigger select register (adtsr) ................................................................. 332 11.4 operation...................................................................................................................... ...... 333 11.4.1 single mode.......................................................................................................... 333 11.4.2 continuous s can mode ......................................................................................... 333 11.4.3 single-cycle scan mode....................................................................................... 335 11.4.4 input sampling and a/ d conversion time........................................................... 335 11.4.5 a/d converter activation by mtu ...................................................................... 337 11.4.6 external trigger input ti ming.............................................................................. 337 11.5 interrupt sources .............................................................................................................. .. 338 11.6 definitions of a/d c onversion accuracy.......................................................................... 338 11.7 usage notes .................................................................................................................... ... 340 11.7.1 module standby mode setting ............................................................................. 340 11.7.2 permissible signal s ource impedance .................................................................. 340 11.7.3 influences on absolute accuracy ......................................................................... 340 11.7.4 range of analog power supp ly and other pin settings ....................................... 341 11.7.5 notes on board design ......................................................................................... 341 11.7.6 notes on noise c ountermeasures ......................................................................... 341 section 12 compare match timer (cmt)........................................................ 343 12.1 features ....................................................................................................................... ....... 343 12.2 register descriptions ......................................................................................................... 3 44 12.2.1 compare match timer start register (cmstr) .................................................. 344 12.2.2 compare match timer control/status register_0 and _1 (cmcsr_0, cmcsr_1) ...................................................................................... 345 12.2.3 compare match timer counter_0 and _1 (cmcnt_0, cmcnt_1)................... 346 12.2.4 compare match timer constant register_0 and _1 (cmcor_0, cmcor_1)... 346 12.3 operation...................................................................................................................... ...... 346 12.3.1 cyclic count operation ........................................................................................ 346 12.3.2 cmcnt count timing......................................................................................... 347 12.4 interrupts ..................................................................................................................... ....... 347
rev.2.00 sep. 27, 2007 page xx of xxxiv rej09b0394-0200 12.4.1 interrupt sources................................................................................................... 347 12.4.2 compare match flag set timing.......................................................................... 347 12.4.3 compare match flag clear timing ...................................................................... 348 12.5 usage notes .................................................................................................................... ... 349 12.5.1 contention between cmcnt write and compare match.................................... 349 12.5.2 contention between cmcnt word write and incrementation ........................... 350 12.5.3 contention between cmcnt byte write and incrementation ............................. 351 section 13 pin function controller (pfc) ........................................................353 13.1 register descriptions ......................................................................................................... 3 60 13.1.1 port a i/o register l (paiorl).......................................................................... 360 13.1.2 port a control registers l3 to l1 (pacrl3 to pacrl1).................................. 361 13.1.3 port b i/o register (pbior) ................................................................................ 364 13.1.4 port b control registers 1 and 2 (pbcr1 a nd pbcr2)....................................... 365 13.1.5 port e i/o registers l and h (peiorl and peiorh)......................................... 366 13.1.6 port e control registers l1, l2, and h (pecrl1, pecrl2, and pecrh) ........ 366 13.2 usage notes .................................................................................................................... ... 370 13.2.1 note on pfc setting ............................................................................................. 370 13.2.2 note on pfc setting order ................................................................................... 370 section 14 i/o ports...........................................................................................371 14.1 port a ........................................................................................................................ ...... 371 14.1.1 register description.............................................................................................. 372 14.1.2 port a data register l (padrl) ......................................................................... 372 14.2 port b ........................................................................................................................ ...... 374 14.2.1 register description.............................................................................................. 374 14.2.2 port b data register (pbdr) ............................................................................... 374 14.3 port e ........................................................................................................................ ...... 376 14.3.1 register descriptions ............................................................................................ 377 14.3.2 port e data registers h and l (pedrh and pedrl) ......................................... 377 14.4 port f ........................................................................................................................ ...... 379 14.4.1 register description.............................................................................................. 379 14.4.2 port f data regi ster (pfdr) ................................................................................ 379 14.5 port g ........................................................................................................................ ...... 381 14.5.1 register description.............................................................................................. 381 14.5.2 port g data register (pgdr)............................................................................... 381 section 15 mask rom ......................................................................................383 15.1 usage note..................................................................................................................... .... 383
rev.2.00 sep. 27, 2007 page xxi of xxxiv rej09b0394-0200 section 16 ram ............................................................................................... 385 16.1 usage note..................................................................................................................... .... 385 section 17 power-down modes ....................................................................... 387 17.1 input/output pins .............................................................................................................. . 389 17.2 register descriptions ......................................................................................................... 3 90 17.2.1 standby control regi ster (sbycr) ..................................................................... 390 17.2.2 system control register (syscr) ....................................................................... 392 17.2.3 module standby control register 1 and 2 (mstcr1 and mstcr2).................. 393 17.3 operation...................................................................................................................... ...... 395 17.3.1 sleep mode ........................................................................................................... 395 17.3.2 software st andby m ode........................................................................................ 396 17.3.3 module standb y mode.......................................................................................... 398 17.4 usage notes .................................................................................................................... ... 399 17.4.1 i/o port status....................................................................................................... 399 17.4.2 current consumption during oscilla tion stabilization wait period..................... 399 17.4.3 on-chip peripheral module interrupt................................................................... 399 17.4.4 writing to mstcr1 and mstcr2 ...................................................................... 399 section 18 list of registers .............................................................................. 401 18.1 register addresses (order of address).............................................................................. 401 18.2 register bits.................................................................................................................. ..... 408 18.3 register states in each operating mode............................................................................ 415 section 19 electrical characteristics ................................................................ 421 19.1 absolute maximum ratings .............................................................................................. 421 19.2 dc charact eristic s ............................................................................................................. 422 19.3 ac charact eristic s ............................................................................................................. 425 19.3.1 test conditions for the ac characteristics........................................................... 425 19.3.2 clock ti ming ........................................................................................................ 426 19.3.3 control signal timing .......................................................................................... 428 19.3.4 multi-function timer puls e unit (mpu) timing................................................. 431 19.3.5 i/o port timing..................................................................................................... 432 19.3.6 watchdog timer (w dt) timing .......................................................................... 433 19.3.7 serial communication inte rface (sci) timing..................................................... 434 19.3.8 output enable (poe) timing ............................................................................... 436 19.3.9 a/d converter timing.......................................................................................... 436 19.4 a/d converter characteristics ........................................................................................... 438 appendix a pin states ...................................................................................... 439
rev.2.00 sep. 27, 2007 page xxii of xxxiv rej09b0394-0200 appendix b product lineup ..............................................................................441 appendix c package dimensions .....................................................................443 index .........................................................................................................445
rev.2.00 sep. 27, 2007 page xxiii of xxxiv rej09b0394-0200 figures section 1 overview figure 1.1 internal bloc k diagram of SH7101............................................................................ 3 figure 1.2 SH7101 pi n arrangement .......................................................................................... 4 section 2 cpu figure 2.1 cpu internal registers............................................................................................. 1 2 figure 2.2 data format in registers.......................................................................................... 15 figure 2.3 data formats in memory ......................................................................................... 16 figure 2.4 transitions between processing states ..................................................................... 41 section 3 mcu operating modes figure 3.1 address map for sh 7101 mask rom version ....................................................... 45 section 4 clock pulse generator figure 4.1 block diagram of clock pulse generator ................................................................ 47 figure 4.2 connection of crystal resonator (example)............................................................ 48 figure 4.3 crystal resonator equivalent circuit ....................................................................... 48 figure 4.4 example of external clock connection ................................................................... 49 figure 4.5 cautions for oscillator circuit system board design.............................................. 50 figure 4.6 recommended external circuitry around pll ........................................................ 51 section 6 interr upt controller (intc) figure 6.1 intc block diagram ............................................................................................... 67 figure 6.2 block diagram of irq3 to irq0 interrupts control................................................ 76 figure 6.3 interrupt sequence flowchart .................................................................................. 82 figure 6.4 stack after interrupt exception processing .............................................................. 83 figure 6.5 example of the pipeline operati on when an irq interrupt is accepted.................. 85 section 8 multi-function timer pulse unit (mtu) figure 8.1 block diagram of mtu ........................................................................................... 94 figure 8.2 complementary pwm m ode output level example ............................................ 132 figure 8.3 example of counter operation setting procedure ................................................. 137 figure 8.4 free-running co unter operation ........................................................................... 138 figure 8.5 periodic c ounter operation.................................................................................... 139 figure 8.6 example of setting procedure fo r waveform output by compare match............. 139 figure 8.7 example of 0 outp ut/1 output operation .............................................................. 140 figure 8.8 example of toggle output operation .................................................................... 140 figure 8.9 example of input captur e operation setting procedure ........................................ 141 figure 8.10 example of input capture operation ..................................................................... 142 figure 8.11 example of synchronous operation setting procedure ......................................... 143 figure 8.12 example of synchronous operation....................................................................... 144
rev.2.00 sep. 27, 2007 page xxiv of xxxiv rej09b0394-0200 figure 8.13 compare match buffer operation.......................................................................... 145 figure 8.14 input capture buffer operation ............................................................................. 146 figure 8.15 example of buffer op eration setting procedure.................................................... 146 figure 8.16 example of buffer operation (1) ........................................................................... 147 figure 8.17 example of buffer operation (2) ........................................................................... 148 figure 8.18 cascaded operation setting procedure .................................................................. 149 figure 8.19 example of cascaded operation ............................................................................ 150 figure 8.20 example of pwm mode setting procedure ........................................................... 152 figure 8.21 example of pwm mode operation (1).................................................................. 153 figure 8.22 example of pwm mode operation (2).................................................................. 154 figure 8.23 example of pwm mode operation (3).................................................................. 155 figure 8.24 example of phase coun ting mode setting procedure............................................ 157 figure 8.25 example of phase counting mode 1 operation ..................................................... 157 figure 8.26 example of phase counting mode 2 operation ..................................................... 158 figure 8.27 example of phase counting mode 3 operation ..................................................... 159 figure 8.28 example of phase counting mode 4 operation ..................................................... 160 figure 8.29 phase counting mode application example ......................................................... 162 figure 8.30 procedure for selecting the reset-synchronized pwm mode............................... 165 figure 8.31 reset-synchronized pwm mode operation example (when the tocr's olsn = 1 and olsp = 1)....................................................... 166 figure 8.32 block diagram of channels 3 and 4 in complementary pwm mode ................... 169 figure 8.33 example of complementar y pwm mode setting procedure................................. 171 figure 8.34 complementary pwm mode counter operation................................................... 173 figure 8.35 example of complementary pwm mode operation ............................................. 175 figure 8.36 example of pwm cycle updating......................................................................... 178 figure 8.37 example of data update in complementary pwm mode..................................... 179 figure 8.38 example of initial output in complementary pwm mode (1).............................. 180 figure 8.39 example of initial output in complementary pwm mode (2).............................. 181 figure 8.40 example of complementary pwm mode waveform output (1) .......................... 183 figure 8.41 example of complementary pwm mode waveform output (2) .......................... 183 figure 8.42 example of complementary pwm mode waveform output (3) .......................... 184 figure 8.43 example of complementary pwm mode 0 % and 100 % waveform output (1) ... 184 figure 8.44 example of complementary pwm mode 0 % and 100 % waveform output (2) ... 185 figure 8.45 example of complementary pwm mode 0 % and 100 % waveform output (3) ... 185 figure 8.46 example of complementary pwm mode 0 % and 100 % waveform output (4) ... 186 figure 8.47 example of complementary pwm mode 0 % and 100 % waveform output (5) ... 186 figure 8.48 example of toggle output wa veform synchronized with pwm output.............. 187 figure 8.49 counter clearing synchr onized with anot her channel ......................................... 188 figure 8.50 example of output phase switching by external input (1) ................................... 189 figure 8.51 example of output phase switching by external input (2) ................................... 190
rev.2.00 sep. 27, 2007 page xxv of xxxiv rej09b0394-0200 figure 8.52 example of output phase switching by means of uf, vf, wf bit settings (1)... 190 figure 8.53 example of output phase switching by means of uf, vf, wf bit settings (2)... 191 figure 8.54 count timing in in ternal clock operation............................................................. 195 figure 8.55 count timing in ex ternal clock operation ........................................................... 195 figure 8.56 count timing in external cloc k operation (phase counting mode)..................... 196 figure 8.57 output compare output timing (normal mode/pwm mode).............................. 196 figure 8.58 output compare output timing (complementary pwm mode/r eset synchronous pwm mode) .......................... 197 figure 8.59 input capture input signal timing......................................................................... 197 figure 8.60 counter clear ti ming (compare match) ............................................................... 198 figure 8.61 counter clear ti ming (input capture) ................................................................... 198 figure 8.62 buffer operation timing (compare match) .......................................................... 199 figure 8.63 buffer operation timing (input capture) .............................................................. 199 figure 8.64 tgi interrupt ti ming (compare match) ................................................................ 200 figure 8.65 tgi interrupt ti ming (input capture).................................................................... 201 figure 8.66 tciv interr upt setting timing............................................................................... 202 figure 8.67 tciu interr upt setting timing............................................................................... 202 figure 8.68 timing for status flag clearing by the cpu ......................................................... 203 figure 8.69 phase difference, overlap, an d pulse width in phase counting mode ................. 204 figure 8.70 contention between tcnt write and clear operations........................................ 205 figure 8.71 contention between tcnt write and increment operations ................................ 206 figure 8.72 contention between tg r write and compare match ........................................... 207 figure 8.73 contention between buffer regist er write and compare match (channel 0) ....... 208 figure 8.74 contention between buffer register write and compare match (channels 3 and 4).................................................................................................. 209 figure 8.75 contention between tg r read and input capture ................................................ 210 figure 8.76 contention between tg r write and input capture ............................................... 211 figure 8.77 contention between buffer re gister write and input capture............................... 212 figure 8.78 tcnt_2 write and overflow/underflow contention with cascade connection.. 213 figure 8.79 counter value during co mplementary pwm mode stop ..................................... 214 figure 8.80 buffer operation and compare-match flags in reset sync pwm mode.............. 215 figure 8.81 reset sync pwm mode overflow flag ................................................................. 216 figure 8.82 contention between over flow and counter clearing ............................................ 217 figure 8.83 contention between tcnt write and overflow.................................................... 218 figure 8.84 error occurrence in normal mode, recovery in normal mode............................ 223 figure 8.85 error occurrence in normal mode, recovery in pwm mode 1............................ 224 figure 8.86 error occurrence in normal mode, recovery in pwm mode 2............................ 225 figure 8.87 error occurrence in normal m ode, recovery in phase counting mode ............... 226 figure 8.88 error occurrence in normal mode , recovery in complementary pwm mode .... 227
rev.2.00 sep. 27, 2007 page xxvi of xxxiv rej09b0394-0200 figure 8.89 error occurrence in normal mode, recovery in reset-synchronous pwm mode........................................................ 228 figure 8.90 error occurrence in pwm mode 1, recovery in normal mode ........................... 229 figure 8.91 error occurrence in pwm mode 1, recovery in pwm mode 1 ........................... 230 figure 8.92 error occurrence in pwm mode 1, recovery in pwm mode 2 ........................... 231 figure 8.93 error occurrence in pwm mode 1, recovery in phase counting mode............... 232 figure 8.94 error occurrence in pwm mode 1, recovery in complementary pwm mode.... 233 figure 8.95 error occurrence in pwm mode 1, recovery in reset-synchronous pwm mode........................................................ 234 figure 8.96 error occurrence in pwm mode 2, recovery in normal mode ........................... 235 figure 8.97 error occurrence in pwm mode 2, recovery in pwm mode 1 ........................... 236 figure 8.98 error occurrence in pwm mode 2, recovery in pwm mode 2 ........................... 237 figure 8.99 error occurrence in pwm mode 2, recovery in phase counting mode............... 238 figure 8.100 error occurrence in phase counting mode, recovery in normal mode............... 239 figure 8.101 error occurrence in phase counting mode, recovery in pwm mode 1............... 240 figure 8.102 error occurrence in phase counting mode, recovery in pwm mode 2............... 241 figure 8.103 error occurrence in phase counting mode, recovery in phase counting mode ........................................................................ 242 figure 8.104 error occurrence in complementar y pwm mode, recovery in normal mode.... 243 figure 8.105 error occurrence in complementary pwm mode, recovery in pwm mode 1.... 244 figure 8.106 error occurrence in complementary pwm mode, recovery in complementary pwm mode ............................................................. 245 figure 8.107 error occurrence in complementary pwm mode, recovery in complementary pwm mode ............................................................. 246 figure 8.108 error occurrence in complementary pwm mode, recovery in reset-synchronous pwm mode........................................................ 247 figure 8.109 error occurrence in reset-synchronous pwm mode, recovery in normal mode..................................................................................... 248 figure 8.110 error occurrence in reset-synchronous pwm mode, recovery in pwm mode 1..................................................................................... 249 figure 8.111 error occurrence in reset-synchronous pwm mode, recovery in complementary pwm mode ............................................................. 250 figure 8.112 error occurrence in reset-synchronous pwm mode, recovery in reset-synchronous pwm mode........................................................ 251 figure 8.113 poe block diagram............................................................................................... 25 3 figure 8.114 low-level detection operation............................................................................. 259 figure 8.115 output-level detection operation......................................................................... 260 figure 8.116 falling edge detection operation.......................................................................... 261 section 9 watchdog timer figure 9.1 block diagram of wdt......................................................................................... 264
rev.2.00 sep. 27, 2007 page xxvii of xxxiv rej09b0394-0200 figure 9.2 operation in watchdog timer mode ..................................................................... 270 figure 9.3 operation in interval timer mode ......................................................................... 271 figure 9.4 timing of setting ovf........................................................................................... 272 figure 9.5 timing of setting wovf....................................................................................... 272 figure 9.6 writing to tcnt and tcsr .................................................................................. 273 figure 9.7 writing to rstcsr ............................................................................................... 274 figure 9.8 contention between tcnt write and increment................................................... 275 figure 9.9 example of system reset circuit using wdtovf signal ................................... 276 section 10 serial comm unication interface (sci) figure 10.1 block diagram of sci............................................................................................ 278 figure 10.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)................................................. 296 figure 10.3 receive data sampling timing in asynchr onous m ode ....................................... 298 figure 10.4 relation between output clock and transmit data phase (asynchro nous mode)............................................................................................ 299 figure 10.5 sample sci in itialization flowchart ...................................................................... 300 figure 10.6 example of operation in transmission in asynchronous mode (example with 8-bit da ta, parity, one stop bit) ................................................... 301 figure 10.7 sample serial transmission flowchart .................................................................. 302 figure 10.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit) .................................................. 303 figure 10.9 sample serial recep tion data flowchart (1) ......................................................... 305 figure 10.9 sample serial recep tion data flowchart (2) ......................................................... 306 figure 10.10 example of communication using multiprocessor format (transmission of data h' aa to receiving station a) ........................................... 308 figure 10.11 sample multiprocessor se rial transmissi on flowchart ......................................... 309 figure 10.12 example of sci operation in reception (example with 8-bit data, mu ltiprocessor bit, one stop bit)............................... 310 figure 10.13 sample multiprocessor se rial reception flowchart (1)......................................... 311 figure 10.13 sample multiprocessor se rial reception flowchart (2)......................................... 312 figure 10.14 data format in clocked sync hronous communication (for lsb-first) ............... 313 figure 10.15 sample sci in itialization flowchart ...................................................................... 314 figure 10.16 sample sci transmission oper ation in clocked synchronous mode ................... 316 figure 10.17 sample serial transmission flowchart .................................................................. 317 figure 10.18 example of sci operation in reception ................................................................ 318 figure 10.19 sample serial reception flowchart ....................................................................... 319 figure 10.20 sample flowchart of simultaneous serial transmit and receive operations ....... 321 section 11 a/d converter figure 11.1 block diagram of a/d converter (for one module) ............................................ 326
rev.2.00 sep. 27, 2007 page xxviii of xxxiv rej09b0394-0200 figure 11.2 operation example in continuous scan mode (three channels selected) (an8 to an10) ........................................................... 334 figure 11.3 a/d conve rsion ti ming......................................................................................... 336 figure 11.4 external tr igger input timing ............................................................................... 337 figure 11.5 definitions of a/d conversion accuracy .............................................................. 339 figure 11.6 definitions of a/d conversion accuracy .............................................................. 339 figure 11.7 example of analog input circuit ........................................................................... 340 figure 11.8 example of analog input protection circuit.......................................................... 342 figure 11.9 analog input pin equivalent circuit ...................................................................... 342 section 12 compare match timer (cmt) figure 12.1 cmt block diagram.............................................................................................. 343 figure 12.2 counter operation.................................................................................................. 346 figure 12.3 c ount ti ming ....................................................................................................... .. 347 figure 12.4 cmf set timing .................................................................................................... 3 48 figure 12.5 timing of cmf clear by cpu ............................................................................... 348 figure 12.6 cmcnt write and compare match contention ................................................... 349 figure 12.7 cmcnt word write and increment contention................................................... 350 figure 12.8 cmcnt byte write and increment contention..................................................... 351 section 14 i/o ports figure 14.1 port a ............................................................................................................. ........ 371 figure 14.2 port b ............................................................................................................. ........ 374 figure 14.3 port e............................................................................................................. ......... 376 figure 14.4 port f............................................................................................................. ......... 379 figure 14.5 port g ............................................................................................................. ........ 381 section 15 mask rom figure 15.1 mask rom block diagram ................................................................................... 383 section 17 power-down modes figure 17.1 mode transition diagram ...................................................................................... 389 figure 17.2 nmi timing in software st andby mo de................................................................ 398 section 19 electrical characteristics figure 19.1 output load circuit ............................................................................................... 4 25 figure 19.2 system clock timing............................................................................................. 427 figure 19.3 extal cloc k input ti ming .................................................................................. 427 figure 19.4 oscillati on settling time ....................................................................................... 427 figure 19.5 reset input timing................................................................................................. 429 figure 19.6 reset input timing................................................................................................. 429 figure 19.7 interrupt si gnal input timing................................................................................. 430 figure 19.8 interrupt si gnal output timing.............................................................................. 430
rev.2.00 sep. 27, 2007 page xxix of xxxiv rej09b0394-0200 figure 19.9 mtu input/output timing..................................................................................... 431 figure 19.10 mtu cloc k input ti ming ...................................................................................... 432 figure 19.11 i/o port input/output timing................................................................................. 433 figure 19.12 wdt timing ........................................................................................................ .. 433 figure 19.13 input clock timing ................................................................................................ 434 figure 19.14 sci inpu t/output timing ....................................................................................... 435 figure 19.15 poe inpu t/output timing ...................................................................................... 436 figure 19.16 external tr igger input timing ............................................................................... 437 appendix c package dimensions figure c.1 fp-80q .............................................................................................................. ..... 443
rev.2.00 sep. 27, 2007 page xxx of xxxiv rej09b0394-0200
rev.2.00 sep. 27, 2007 page xxxi of xxxiv rej09b0394-0200 tables section 1 overview table 1.1 pin functions ............................................................................................................... 5 table 1.2 differences from sh7046 group................................................................................. 9 section 2 cpu table 2.1 initial values of registers.......................................................................................... 15 table 2.2 sign extension of word data .................................................................................... 17 table 2.3 delayed branch instructions...................................................................................... 17 table 2.4 t bit .......................................................................................................................... .18 table 2.5 immediate data accessing......................................................................................... 18 table 2.6 absolute address accessing...................................................................................... 19 table 2.7 displacement accessing ............................................................................................ 19 table 2.8 addressing modes and effective addresses.............................................................. 20 table 2.9 instruction formats .................................................................................................... 24 table 2.10 classification of instructions ..................................................................................... 27 table 2.11 symbols used in instruction code, oper ation, and execution states tables ............ 30 table 2.12 data transfer instructions.......................................................................................... 31 table 2.13 arithmetic operation instructions ............................................................................. 33 table 2.14 logic operation instructions ..................................................................................... 36 table 2.15 shift instructions........................................................................................................ 37 table 2.16 branch instructions .................................................................................................... 38 table 2.17 system control instructions....................................................................................... 39 section 3 mcu operating modes table 3.1 selection of operating modes.................................................................................... 43 table 3.2 maximum operating clock frequency for each clock mode .................................. 43 table 3.3 operating mode pin configuration............................................................................ 44 section 4 clock pulse generator table 4.1 damping resistance values....................................................................................... 48 table 4.2 crystal resonator characteristics .............................................................................. 48 section 5 exception processing table 5.1 types of exception processing and priority .............................................................. 53 table 5.2 timing for exception source detection a nd start of exception processing.............. 54 table 5.3 exception processing vector table ........................................................................... 55 table 5.4 calculating exception processing vector table addresses....................................... 56 table 5.5 reset status................................................................................................................ 57 table 5.6 bus cycles and address errors.................................................................................. 59 table 5.7 interrupt sources........................................................................................................ 60
rev.2.00 sep. 27, 2007 page xxxii of xxxiv rej09b0394-0200 table 5.8 interrupt priority ........................................................................................................ 61 table 5.9 types of exceptions tri ggered by inst ructions ......................................................... 62 table 5.10 generation of exception sources immediately after delayed branch instruction or interrupt-disabled instruction ............................................................................... 64 table 5.11 stack status after exception processing ends ........................................................... 65 section 6 interr upt controller (intc) table 6.1 pin configuration....................................................................................................... 68 table 6.2 interrupt exception processing vectors and priorities .............................................. 78 table 6.3 interrupt res ponse time............................................................................................ 84 section 7 bus st ate controller (bsc) table 7.1 address map.............................................................................................................. 88 table 7.2 on-chip peripheral i/o register access .................................................................... 90 section 8 multi-function timer pulse unit (mtu) table 8.1 mtu functions.......................................................................................................... 92 table 8.2 pin configuration........................................................................................................ 95 table 8.3 cclr0 to cclr2 (channels 0, 3, and 4) .................................................................. 99 table 8.4 cclr0 to cclr2 (cha nnels 1 a nd 2) ....................................................................... 99 table 8.5 tpsc0 to tpsc2 (channel 0) .................................................................................. 100 table 8.6 tpsc0 to tpsc2 (channel 1) .................................................................................. 100 table 8.7 tpsc0 to tpsc2 (channel 2) .................................................................................. 101 table 8.8 tpsc0 to tpsc2 (channels 3 and 4)....................................................................... 101 table 8.9 md0 to md3 ........................................................................................................... 103 table 8.10 tiorh_0 (channel 0) .............................................................................................. 106 table 8.11 tiorh_0 (channel 0) .............................................................................................. 107 table 8.12 tiorl_0 (channel 0)............................................................................................... 108 table 8.13 tiorl_0 (channel 0)............................................................................................... 109 table 8.14 tior_1 (channel 1) ................................................................................................. 110 table 8.15 tior_1 (channel 1) ................................................................................................. 111 table 8.16 tior_2 (channel 2) ................................................................................................. 112 table 8.17 tior_2 (channel 2) ................................................................................................. 113 table 8.18 tiorh_3 (channel 3) .............................................................................................. 114 table 8.19 tiorh_3 (channel 3) .............................................................................................. 115 table 8.20 tiorl_3 (channel 3)............................................................................................... 116 table 8.21 tiorl_3 (channel 3)............................................................................................... 117 table 8.22 tiorh_4 (channel 4) .............................................................................................. 118 table 8.23 tiorh_4 (channel 4) .............................................................................................. 119 table 8.24 tiorl_4 (channel 4)............................................................................................... 120 table 8.25 tiorl_4 (channel 4)............................................................................................... 121 table 8.26 output level sel ect function .................................................................................. 131
rev.2.00 sep. 27, 2007 page xxxiii of xxxiv rej09b0394-0200 table 8.27 output level sel ect function .................................................................................. 132 table 8.28 output level sel ect function.................................................................................... 134 table 8.29 register combinations in buffer operation ............................................................ 145 table 8.30 cascaded combinations........................................................................................... 149 table 8.31 pwm output registers and output pins ................................................................. 151 table 8.32 phase counting mode clock input pins .................................................................. 156 table 8.33 up/down-count conditions in phase counting mode 1......................................... 158 table 8.34 up/down-count conditions in phase counting mode 2......................................... 159 table 8.35 up/down-count conditions in phase counting mode 3......................................... 160 table 8.36 up/down-count conditions in phase counting mode 4......................................... 161 table 8.37 output pins for reset- synchronized pwm mode ................................................... 163 table 8.38 register settings for reset-synchronized pwm mode ........................................... 163 table 8.39 output pins for complementary pwm mode.......................................................... 167 table 8.40 register settings for complementary pwm mode ................................................. 168 table 8.41 registers and counters re quiring initialization ...................................................... 176 table 8.42 mtu interrupts ........................................................................................................ 193 table 8.43 mode transition combinations ............................................................................... 221 table 8.44 pin configuration..................................................................................................... 254 table 8.45 pin combinations..................................................................................................... 254 section 9 watchdog timer table 9.1 pin configuration..................................................................................................... 264 table 9.2 wdt interrupt source (in interval timer mode) .................................................... 273 section 10 serial comm unication interface (sci) table 10.1 pin configuration..................................................................................................... 279 table 10.2 relationships between n setting in brr and effective bit rate b 0 ....................... 288 table 10.3 brr settings for various bit rates (asynchr onous mode).................................... 289 table 10.4 maximum bit rate for each frequency when using baud rate generator (asynchro nous mode) ............................................................................................. 291 table 10.5 maximum bit rate with external cl ock input (asynchronous mode).................... 292 table 10.6 brr settings for various bit rates (clocked synchronous mode)........................ 293 table 10.7 maximum bit rate with external clock input (clocked synchronous mode) ....... 295 table 10.8 serial transfer formats (asynchronous mode)....................................................... 297 table 10.9 ssr status flags and receive data handling ......................................................... 304 table 10.10 sci interrupt sources............................................................................................... 322 section 11 a/d converter table 11.1 pin configuration..................................................................................................... 327 table 11.2 channel select list .................................................................................................. 330 table 11.3 a/d conversion time (single m ode)...................................................................... 336 table 11.4 a/d conversion time (scan mode) ........................................................................ 337
rev.2.00 sep. 27, 2007 page xxxiv of xxxiv rej09b0394-0200 table 11.5 a/d converter interrupt source............................................................................... 338 table 11.6 analog pin speci fications........................................................................................ 342 section 13 pin function controller (pfc) table 13.1 multiplexed pins (port a)........................................................................................ 353 table 13.2 multiplexed pins (port b) ........................................................................................ 354 table 13.3 multiplexed pins (port e) ........................................................................................ 355 table 13.4 multiplexed pins (port f)......................................................................................... 356 table 13.5 multiplexed pins (port g)........................................................................................ 356 table 13.6 pin functions in each operating mode ................................................................... 357 section 14 i/o ports table 14.1 port a data register l (padrl) read/write operations ...................................... 373 table 14.2 port b data register (pbdr) read/write operations............................................. 375 table 14.3 port e data registers h and l (pedrh and pedrl) read/write operations ...... 378 table 14.4 port f data register (pfdr) read/write operations ............................................. 380 table 14.5 port g data register (pgdr) read/write operations ............................................ 382 section 17 power-down modes table 17.1 internal operation states in each mode .................................................................. 388 table 17.2 pin configuration..................................................................................................... 389 section 19 electrical characteristics table 19.1 absolute maximum ratings .................................................................................... 421 table 19.2 dc characteristics ................................................................................................... 422 table 19.3 permitted output current values............................................................................. 424 table 19.4 clock timing ........................................................................................................... 426 table 19.5 control signal timing ............................................................................................. 428 table 19.6 multi-function timer pu lse unit timing................................................................ 431 table 19.7 i/o port timing........................................................................................................ 432 table 19.8 watchdog timer timing.......................................................................................... 433 table 19.9 serial communication interface timing.................................................................. 434 table 19.10 output enable timing ............................................................................................. 436 table 19.11 a/d converter timing............................................................................................. 436 table 19.12 a/d converter characteristics ................................................................................. 438 appendix a pin states table a.1 pin states ................................................................................................................. 439
1. overview rev.2.00 sep. 27, 2007 page 1 of 448 rej09b0394-0200 section 1 overview the SH7101 single-chip risc (reduced instruction set computer) microcomputer integrates a renesas technology-original risc cpu core w ith peripheral functions required for system configuration. the SH7101 cpu has a risc-type instruction set. most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. in addition, the 32- bit internal-bus architecture enhances data processing power. with this cpu, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microcomputers, such as real-time control, which demands high speeds. in addition, the SH7101 includes on-chip peripheral functions necessary for system configuration, such as rom and ram, timers, a serial comm unication interface (sci), an a/d converter, an interrupt controller (intc), and i/o ports. as the on-chip rom, only mask rom version is available. however, when f-ztat tm (flexible zero turn around time) version is required, the sh7046f can be used. 1.1 features ? central processing unit with an internal 32-bit risc (reduced instruction set computer) architecture ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture (basic operati ons are executed between registers) ? sixteen 32-bit general registers ? five-stage pipeline ? on-chip multiplier: multiplication operations (32 bits 32 bits 64 bits) executed in two to four cycles ? c language-oriented 62 basic instructions ? various peripheral functions ? multifunction timer/pulse unit (mtu) ? compare match timer (cmt) ? watchdog timer (wdt) ? asynchronous or clocked synchronous serial communicati on interface (sci) ? 10-bit a/d converter ? clock pulse generator
1. overview rev.2.00 sep. 27, 2007 page 2 of 448 rej09b0394-0200 ? on-chip memory rom model rom ram remarks mask rom version hd6437101 32 kbytes 2 kbytes ? ? maximum operating frequency and operating temperature range model maximum operating frequency (mhz) (system clock ( ) and peripheral clock (p )) operating temperature range ( c) hd6437101f40 (40, 40) ?20 to +75 hd6437101fw40 (40, 40) ?40 to +85 ? i/o ports model no. of i/o pins no. of input-only pins hd6437101 42 12 ? supports various power-down states ? compact package model package package (code) body size pin pitch hd6437101 qfp-80 fp-80q 14.0 14.0 mm 0.65 mm
1. overview rev.2.00 sep. 27, 2007 page 3 of 448 rej09b0394-0200 1.2 internal block diagram : peripheral address bus (12 bits) : peripheral data bus (16 bits) : internal address bus (32 bits) : internal upper data bus (16 bits) : internal lower data bus (16 bits) res wdtovf md3 md2 md1 md0 nmi extal xtal pllvcl pllcap pllvss fwp vcl vcl vcc vcc vcc vss vss vss vss avcc avcc avss avss serial communication interface ( 2 channels) multifunction timer pulse unit interrupt controller bus state controller compare match timer ( 2 channels) a/d converter watchdog timer mask rom 32 kbytes cpu ram 2 kbytes pll pb5/ irq3 / poe3 pb4/ irq2 / poe2 pb3/ irq1 / poe1 pb2/ irq0 / poe0 pe21 pe20 pe19 pe18 pe17 pe16 pe15/tioc4d/ irqout pe14/tioc4c pe13/tioc4b/ mres pe12/tioc4a pe11/tioc3d pe10/tioc3c pe9/tioc3b pe8/tioc3a pe7/tioc2b pe6/tioc2a/sck3 pe5/tioc1b/txd3 pe4/tioc1a/rxd3 pe3/tioc0d pe2/tioc0c pe1/tioc0b pe0/tioc0a pa15 pa14 pa13 pa 1 2 pa 1 1 / adtrg /sck3 pa10/sck2 pa9/tclkd/txd3 pa8/tclkc/rxd3 pa7/tclkb/txd2 pa6/tclka/rxd2 pa5/ irq1 /sck3 pa4/txd3 pa3/rxd3 pa2/ irq0 /sck2 pa1/ poe1 /txd2 pa 0 / poe0 /rxd2 pg3 pg2 pg1 pg0 pf15/an15 pf14/an14 pf13/an13 pf12/an12 pf11/an11 pf10/an10 pf9/an9 pf8/an8 figure 1.1 internal block diagram of SH7101
1. overview rev.2.00 sep. 27, 2007 page 4 of 448 rej09b0394-0200 1.3 pin arrangement avss pf8/an8 avcc pf9/an9 pf10/an10 pf11/an11 pg0 pg1 pg2 pg3 pf12/an12 pf13/an13 pf14/an14 avcc pf15/an15 avss vss pe21 * vcl pe20 * pa 1 / poe1 /txd2 vcl pa 0 / poe0 /rxd2 vss fwp vcc res nmi md3 md2 md1 md0 extal xtal pllvcl pllcap pllvss wdtovf pe0/tioc0a pe1/tioc0b pe2/tioc0c pe3/tioc0d pe4/tioc1a/rxd3 pe5/tioc1b/txd3 pe6/tioc2a/sck3 pe7/tioc2b pe8/tioc3a pe9/tioc3b vss pe10/tioc3c vcc pe11/tioc3d pe12/tioc4a pe13/tioc4b/ mres pe14/tioc4c pe15/tioc4d/ irqout * pe16 * pe17 * pe18 * pe19 pa 2 / irq0 /sck2 pa3/rxd3 pa4/txd3 pa5/ irq1 /sck3 pa6/tclka/rxd2 pa7/tclkb/txd2 pa8/tclkc/rxd3 pa9/tclkd/txd3 pa10/sck2 pa11/ adtrg /sck3 pa12 * pa13 * pa14 * pa15 * pb2/ irq0 / poe0 pb3/ irq1 / poe1 pb4/ irq2 / poe2 vcc pb5/ irq3 / poe3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 qfp-80 (top view) note: * this pin has a pull-up mos. figure 1.2 SH7101 pin arrangement
1. overview rev.2.00 sep. 27, 2007 page 5 of 448 rej09b0394-0200 1.4 pin functions table 1.1 pin functions type symbol i/o name function vcc input power supply power supply pins. connect all these pins to the system power supply. the chip does not operate normally when some of these pins are open. vss input ground ground pins. connect all these pins to the system power supply (0 v). the chip does not operate normally when some of these pins are open. power supply vcl output power supply for internal power-down external capacitance pins for internal power-down power supply. connect these pins to vss via a 0.47 f (?10 % /+100 % ) capacitor (placed close to the pins). clock pllvcl output power supply for pll external capacitance pin for internal power-down power supply for an on-chip pll oscillator. connect this pin to pllvss via a 0.47 f (?10 % /+100 % ) capacitor (placed close to the pin). pllvss input ground for pll on-chip pll oscillator ground pin. pllcap input capacitance for pll external capacitance pin for an on-chip pll oscillator. extal input external clock for connection to a crystal resonator. (an external clock can be supplied from the extal pin.) for examples of crystal resonator connection and external clock input, see section 4, clock pulse generator. xtal input crystal for connection to a crystal resonator. for examples of crystal resonator connection and external clock input, see section 4, clock pulse generator. operating mode control md3 to md0 input set the mode set the operating mode. inputs at these pins should not be changed during operation.
1. overview rev.2.00 sep. 27, 2007 page 6 of 448 rej09b0394-0200 type symbol i/o name function operating mode control fwp input protection against write operation into flash memory pin for the flash memory. this pin is only used in the flash memory version. writing or erasing of flash memory can be protected. this pin becomes the vcc pin for the mask rom version. system control res input power on reset when this pin is driven low, the chip becomes to power on reset state. mres input manual reset when this pin is driven low, the chip becomes to manual reset state. wdtovf output watchdog timer overflow output signal for the watchdog timer overflow. this pin should be pulled down with at least 1 m resistor value. nmi input non-maskable interrupt non-maskable interrupt pin. if this pin is not used, it should be fixed high or low. irq3 to irq0 input interrupt request 3 to 0 these pins request a maskable interrupt. one of the level input or edge input can be selected. in case of the edge input, one of the rising edge, falling edge, or both can be selected. interrupts irqout output interrupt request output shows that an interrupt cause has occurred. multi function timer-pulse unit (mtu) tclka tclkb tclkc tclkd input external clock input for mtu timer these pins input an external clock. tioc0a tioc0b tioc0c tioc0d input/ output mtu input capture/output compare (channel 0) the tgra_0 to tgrd_0 input capture input/output compare output/pwm output pins. tioc1a tioc1b input/ output mtu input capture/output compare (channel 1) the tgra_1 to tgrb_1 input capture input/output compare output/pwm output pins. tioc2a tioc2b input/ output mtu input capture/output compare (channel 2) the tgra_2 to tgrb_2 input capture input/output compare output/pwm output pins.
1. overview rev.2.00 sep. 27, 2007 page 7 of 448 rej09b0394-0200 type symbol i/o name function multi function timer-pulse unit (mtu) tioc3a tioc3b tioc3c tioc3d input/ output mtu input capture/output compare (channel 3) the tgra_3 to tgrd_3 input capture input/output compare output/pwm output pins. tioc4a tioc4b tioc4c tioc4d input/ output mtu input capture/output compare (channel 4) the tgra_4 to tgrb_4 input capture input/output compare output/pwm output pins. txd2 txd3 output transmitted data data output pins. rxd2 rxd3 input received data data input pins. serial com- munication interface (sci) sck2 sck3 input/ output serial clock clock input/output pins. mtu output control poe3 to poe0 input port output control input pins for the signal to request the output pins of mtu waveform to become high impedance state. a/d converter an15 to an8 input analog input pins analog input pins. 8 channels: an15 to an8 adtrg input input of trigger for a/d conversion pin for input of an external trigger to start a/d conversion avcc input analog power supply power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+5 v). connect all avcc pins to the power supply. the chip does not operate normally when some of these pins are open. avss input analog ground the ground pin for the a/d converter. connect this pin to the system power supply (0 v). connect all avss pins to the system power supply. the chip does not operate normally when some of these pins are open.
1. overview rev.2.00 sep. 27, 2007 page 8 of 448 rej09b0394-0200 type symbol i/o name function i/o ports pa15 to pa0 input/ output general purpose port 16-bit general purpose input/output port pins. pa15 to pa12 have a pull-up mos. pb5 to pb2 input/ output general purpose port 4-bit general purpose input/output port pins pe21 to pe0 input/ output general purpose port 22-bit general purpose input/output port pins. pe21 to pe16 have a pull-up mos. pf15 to pf8 input general purpose port 8-bit general purpose input port pins pg3 to pg0 input general purpose port 4-bit general purpose input port pins
1. overview rev.2.00 sep. 27, 2007 page 9 of 448 rej09b0394-0200 1.5 differences from sh7046 group table 1.2 differences from sh7046 group item sh7046f SH7101 dtc, mmt, ubc incorporated not incorporated int registers ipra and iprd to iprk available. registers iprj and iprk deleted. bsc registers bcr1, bcr2, wcr1, and ramer registers bcr2, wcr1, and ramer deleted. poe poe6 to poe0 poe6 to poe4 for mmt deleted. a/d converter 4ch 3 modules an19 to an8 4ch 2 modules an15 to an8 pa2/ irq0 /pcio/sck2 pa2/ irq0 /sck2 i/o port pfc pa3/ poe4 /rxd3 pa3/rxd3 pa4/ poe5 /txd3 pa4/txd3 pa5/ irq1 / poe6 /sck3 pa5/ irq1 /sck3 pa8/tclkc/ irq2 /rxd3 pa8/tclkc/rxd3 pa9/tclkd/ irq3 /txd3 pa9/tclkd/txd3 pa12/ ubctrg pa12 (pulled up when used as general purpose input) pa13/ poe4 pa13 (pulled up when used as general purpose input) pa14/ poe5 pa14 (pulled up when used as general purpose input) pa15/ poe6 pa15 (pulled up when used as general purpose input) pe7/tioc2b/rx d2 pe7/tioc2b pe8/tioc3a/sc k2 pe8/tioc3a pe10/tioc3c/txd2 pe10/tioc3c pe16/puoa/ ubctrg pe16 (pulled up when used as general purpose input) * pe17/pvoa pe17 (pulled up when used as general purpose input) * pe18/pwoa pe18 (pulled up when used as general purpose input) *
1. overview rev.2.00 sep. 27, 2007 page 10 of 448 rej09b0394-0200 item sh7046f SH7101 i/o port pfc pe19/puob pe19 (pulled up when used as general purpose input) * pe20/pvob pe20 (pulled up when used as general purpose input) * pe21/pwob pe21 (pulled up when used as general purpose input) * pg0/an16 pg0 pg1/an17 pg1 pg2/an18 pg2 pg3/an19 pg3 rom flash 256 kbytes mask rom 32 kbytes ram 12 kbytes 2 kbytes operating clock 4 to 50 mhz 10 to 40 mhz note: * pins pe21 to pe16 also functioned as high-c urrent function pins. howwever, in the SH7101, pins pe21 to pe16 are exclusively for general input/output.
2. cpu cpus200a_010020030200 rev.2.00 sep. 27, 2007 page 11 of 448 rej09b0394-0200 section 2 cpu 2.1 features ? general-register architecture ? sixteen 32-bit general registers ? sixty-two basic instructions ? eleven addressing modes ? register direct [rn] ? register indirect [@rn] ? register indirect with post-increment [@rn+] ? register indirect with pre-decrement [@-rn] ? register indirect with displacement [@disp:4,rn] ? register indirect with index [@r0, rn] ? gbr indirect with disp lacement [@disp:8,gbr] ? gbr indirect with index [@r0,gbr] ? program-counter relative with displacement [@disp:8,pc] ? program-counter relative [disp:8/disp:12/rn] ? immediate [#imm:8] 2.2 register configuration the register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers.
2. cpu rev.2.00 sep. 27, 2007 page 12 of 448 rej09b0394-0200 31 0 r0 * 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15, sp (hardware stack pointer) * 2 general registers (rn) status register (sr) global base register (gbr) vector base register (vbr) multiply-accumulate register (mac) procedure register (pr) program counter (pc) 31 9 8 7 6 5 4 3 2 1 0 0 0 31 m gbr 31 vbr qi3i2i1i0 s t 31 0 mach 31 0 pr 31 0 pc macl notes: 1. r0 functions as an index register in the indirect indexed register addressing mode and indirect indexed gbr addressing mode. in some instructions, r0 functions as a fixed source register or destination register. 2. r15 functions as a hardware stack pointer (sp) during exception processing. figure 2.1 cpu internal registers
2. cpu rev.2.00 sep. 27, 2007 page 13 of 448 rej09b0394-0200 2.2.1 general registers (rn) the sixteen 32-bit general registers (rn) are numbered r0 to r15. general registers are used for data processing and address calculation. r0 is also used as an index register. several instructions have r0 fixed as their only usable register. r15 is used as the hardware stack pointer (sp). saving and recovering the status register (sr) and program counter (pc) in exception processing is accomplished by referencing the stack using r15. 2.2.2 control registers the control registers consist of three 32-bit registers: status register (sr), global base register (gbr), and vector base register (vbr). the status register indicates processing states. the global base register functions as a base address for the indirect gbr addressing mode to transfer data to the registers of on-chip peripheral modules. the vect or base register functions as the base address of the exception processing vector area (including interrupts). status register (sr): bit bit name initial value r/w description 31 to 10 ? all 0 r/w reserved this bit is always read as 0. the write value should always be 0. 9 m undefined r/w used by the div0u, div0s, and div1 instructions. 8 q undefined r/w used by the div0u, div0s, and div1 instructions. 7 6 5 4 i3 i2 i1 i0 1 1 1 1 r/w r/w r/w r/w interrupt mask bits. 3, 2 ? all 0 r/w reserved this bit is always read as 0. the write value should always be 0. 1 s undefined r/w s bit used by the mac instruction.
2. cpu rev.2.00 sep. 27, 2007 page 14 of 448 rej09b0394-0200 bit bit name initial value r/w description 0 t undefined r/w t bit the movt, cmp/cond, tas, tst, bt (bt/s), bf (bf/s), sett, and clrt instructions use the t bit to indicate true (1) or false (0). the addv, addc, subv, subc, div0u, div0s, div1, negc, shar, shal , shlr, shll, rotr, rotl, rotcr, and rotcl instructions also use the t bit to indicate carry/borrow or overflow/underflow. global base register (gbr): indicates the base address of the indirect gbr addressing mode. the indirect gbr addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. vector base register (vbr): indicates the base address of th e exception processing vector area. 2.2.3 system registers system registers consist of four 32-bit registers: high and low multiply and accumulate registers (mach and macl), the procedure register (pr), and the program counter (pc). multiply-and-accumulate registers (mac): registers to store the results of multiply-and- accumulate operations. procedure register (pr): registers to store the return addr ess from a subroutine procedure. program counter (pc): registers to indicate the sum of current instruction addresses and four, that is, the address of the second instruction after the current instruction.
2. cpu rev.2.00 sep. 27, 2007 page 15 of 448 rej09b0394-0200 2.2.4 initial values of registers table 2.1 lists the values of the registers after reset. table 2.1 initial values of registers classification register initial value r0 to r14 undefined general registers r15 (sp) value of the stack pointer in the vector address table sr bits i3 to i0 are 1111 (h'f), reserved bits are 0, and other bits are undefined gbr undefined control registers vbr h'00000000 system registers mach, macl, pr undefined pc value of the program counter in the vector address table 2.3 data formats 2.3.1 data format in registers register operands are always longwords (32 bits). if the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 0 longword figure 2.2 data format in registers
2. cpu rev.2.00 sep. 27, 2007 page 16 of 448 rej09b0394-0200 2.3.2 data formats in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address. locate, however, word data at an address 2n, longword data at 4n. otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. in such cases, the data accessed cannot be guaranteed. the hardware stack area, pointed by the hardware stack pointer (sp, r15), uses only longword data starting from address 4n because this area holds the program counter and status register. 31 0 15 23 7 byte byte byte byte word word address 2n address 4n longword address m address m + 2 address m + 1 address m + 3 figure 2.3 data formats in memory 2.3.3 immediate data format byte (8 bit) immediate data resides in an in struction code. immediate data accessed by the mov, add, and cmp/eq instructions is sign-extended and handled in registers as longword data. immediate data accessed by the tst, and, or, and xor instructions is zero-extended and handled as longword data. consequently, and instructions with immediate data always clear the upper 24 bits of the destination register. word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. an immediate data transfer inst ruction (mov) accesses the memory table using the pc relative addressing mode with displacement.
2. cpu rev.2.00 sep. 27, 2007 page 17 of 448 rej09b0394-0200 2.4 instruction features 2.4.1 risc-type instruction set all instructions are risc type. th is section details their functions. 16-bit fixed length : all instructions are 16 bits long, increasing program code efficiency. one instruction per state : the microprocessor can execute basic instructions in one state using the pipeline system. one state is 25 ns at 40 mhz. data length : longword is the standard data length for all operations. memory can be accessed in bytes, words, or longwords. byte or word data accessed from memory is sign-extended and handled as longword data. immediate data is sign-extended for arithmetic operations or zero- extended for logic operations. it also is handled as longword data. table 2.2 sign extension of word data cpu of this lsi description example of conventional cpu mov.w @(disp,pc),r1 add r1,r0 ......... .data.w h'1234 data is sign-extended to 32 bits, and r1 becomes h'00001234. it is next operated upon by an add instruction. add.w #h'1234,r0 note: @(disp, pc) accesses the immediate data. load-store architecture : basic operations are executed betw een registers. for operations that involve memory access, data is loaded to the registers and executed (l oad-store architecture). instructions such as and that manipulate bits, however, are executed directly in memory. delayed branch instructions : unconditional branch instructions are delayed branch instructions. with a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. this reduces the disturbance of the pipeline control in case of branch instructions. there are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. table 2.3 delayed branch instructions cpu of this lsi description example of conventional cpu bra trget add r1,r0 executes the add before branching to trget. add.w r1,r0 bra trget
2. cpu rev.2.00 sep. 27, 2007 page 18 of 448 rej09b0394-0200 multiply/multiply-and-accumulate operations: 16-bit 16-bit 32-bit multiply operations are executed in one to two states. 16-bit 16-bit + 64-bit 4-bit multiply-and-accumulate operations are executed in two to three states. 32-bit 32-bit 64-bit multiply and 32-bit 32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four states. t bit : the t bit in the status regist er changes according to the resu lt of the comparison. whether a conditional branch is taken or not taken depend s upon the t bit condition (true/false). the number of instructions that change the t bit is kept to a minimum to improve the processing speed. table 2.4 t bit cpu of this lsi description example of conventional cpu cmp/ge r1,r0 bt trget0 bf trget1 t bit is set when r0 r1. the program branches to trget0 when r0 r1 and to trget1 when r0 < r1. cmp.w r1,r0 bge trget0 blt trget1 add # ? 1,r0 cmp/eq #0,r0 bt trget t bit is not changed by add. t bit is set when r0 = 0. the program branches if r0 = 0. sub.w #1,r0 beq trget immediate data : byte (8-bit) immediate data is located in an instruction code. word or longword immediate data is not located in instruction codes but in a memory table. an immediate data transfer instruction (mov) accesses the memory table using the pc relative addressing mode with displacement. table 2.5 immediate data accessing classification cpu of this lsi example of conventional cpu 8-bit immediate mov #h'12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 ................. .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 ................. .data.l h'12345678 mov.l #h'12345678,r0 note: @(disp, pc) accesses the immediate data.
2. cpu rev.2.00 sep. 27, 2007 page 19 of 448 rej09b0394-0200 absolute address : when data is accessed by absolute address, the value in the absolute address is placed in the memory table in a dvance. that value is transferre d to the register by loading the immediate data during the executi on of the instruction, and the da ta is accessed in the indirect register addressing mode. table 2.6 absolute address accessing classification cpu of this lsi example of conventional cpu absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 .................. .data.l h'12345678 mov.b @h'12345678,r0 note: @(disp, pc) accesses the immediate data. 16-bit/32-bit displacement : when data is accessed by 16-b it or 32-bit displacement, the displacement value is placed in th e memory table in advance. that value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect indexe d register addressing mode. table 2.7 displacement accessing classification cpu of this lsi example of conventional cpu 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 .................. .data.w h'1234 mov.w @(h'1234,r1),r2 note: @(disp, pc) accesses the immediate data.
2. cpu rev.2.00 sep. 27, 2007 page 20 of 448 rej09b0394-0200 2.4.2 addressing modes table 2.8 describes addressing mode s and effective address calculation. table 2.8 addressing modes and effective addresses addressing mode instruction format effective address calculation equation direct register addressing rn the effective address is register rn. (the operand is the contents of register rn.) ? indirect register addressing @rn the effective address is the contents of register rn. rn rn rn post-increment indirect register addressing @rn+ the effective address is the contents of register rn. a constant is added to the content of rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. rn rn 1/2/4 + rn + 1/2/4 rn (after the instruction executes) byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn pre-decrement indirect register addressing @-rn the effective address is the value obtained by subtracting a constant from rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. rn 1/2/4 rn ? 1/2/4 ? rn ? 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction is executed with rn after this calculation)
2. cpu rev.2.00 sep. 27, 2007 page 21 of 448 rej09b0394-0200 addressing mode instruction format effective address calculation equation indirect register addressing with displacement @(disp:4, rn) the effective address is the sum of rn and a 4-bit displacement (disp). the value of disp is zero- extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indirect indexed register addressing @(r0, rn) the effective address is the sum of rn and r0. rn r0 rn + r0 + rn + r0 indirect gbr addressing with displacement @(disp:8, gbr) the effective address is the sum of gbr value and an 8-bit displacement (disp). the value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 indirect indexed gbr addressing @(r0, gbr) the effective address is the sum of gbr value and r0. gbr r0 gbr + r0 + gbr + r0
2. cpu rev.2.00 sep. 27, 2007 page 22 of 448 rej09b0394-0200 addressing mode instruction format effective address calculation equation indirect pc addressing with displacement @(disp:8, pc) the effective address is the sum of pc value and an 8-bit displacement (disp). the value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. for a longword operation, the lowest two bits of the pc value are masked. pc h'fffffffc pc + disp 2 or pc & h'fffffffc + disp 4 + 2/4 & (for longword) disp (zero-extended) word: pc + disp 2 longword: pc & h'fffffffc + disp 4 pc relative addressing disp:8 the effective address is the sum of pc value and the value that is obtained by doubling the sign- extended 8-bit displacement (disp). pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 disp:12 the effective address is the sum of pc value and the value that is obtained by doubling the sign- extended 12-bit displacement (disp). pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2
2. cpu rev.2.00 sep. 27, 2007 page 23 of 448 rej09b0394-0200 addressing mode instruction format effective address calculation equation pc relative addressing rn the effective address is the sum of the register pc and rn. pc rn pc + rn + pc + rn immediate addressing #imm:8 the 8-bit immediate data (imm) for the tst, and, or, and xor instructions is zero-extended. ? #imm:8 the 8-bit immediate data (imm) for the mov, add, and cmp/eq instructions is sign-extended. ? #imm:8 the 8-bit immediate data (imm) for the trapa instruction is zero-extended and then quadrupled. ?
2. cpu rev.2.00 sep. 27, 2007 page 24 of 448 rej09b0394-0200 2.4.3 instruction format the instruction formats and the meaning of source and destination operand are described below. the meaning of the operand depends on the instruction code. the symbols used are as follows: ? xxxx: instruction code ? mmmm: source register ? nnnn: destination register ? iiii: immediate data ? dddd: displacement table 2.9 instruction formats instruction formats source operand destination operand example 0 format xxxx xxxx xxxx xxxx 15 0 ? ? nop ? nnnn: direct register movt rn control register or system register nnnn: direct register sts mach,rn n format xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn: indirect pre- decrement register stc.l sr,@-rn mmmm: direct register control register or system register ldc rm,sr mmmm: indirect post-increment register control register or system register ldc.l @rm+,sr mmmm: indirect register ? jmp @rm m format xxxx mmmm xxxx xxxx 15 0 mmmm: pc relative using rm ? braf rm
2. cpu rev.2.00 sep. 27, 2007 page 25 of 448 rej09b0394-0200 instruction formats source operand destination operand example mmmm: direct register nnnn: direct register add rm,rn mmmm: direct register nnnn: indirect register mov.l rm,@rn mmmm: indirect post-increment register (multiply- and-accumulate) nnnn * : indirect post-increment register (multiply- and-accumulate) mach, macl mac.w @rm+,@rn+ mmmm: indirect post-increment register nnnn: direct register mov.l @rm+,rn mmmm: direct register nnnn: indirect pre- decrement register mov.l rm,@-rn nm format nnnn xxxx xxxx 15 0 mmmm mmmm: direct register nnnn: indirect indexed register mov.l rm,@(r0,rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd: indirect register with displacement r0 (direct register) mov.b @(disp,rn),r0 nd4 format xxxx xxxx dddd 15 0 nnnn r0 (direct register) nnnndddd: indirect register with displacement mov.b r0,@(disp,rn) mmmm: direct register nnnndddd: indirect register with displacement mov.l rm,@(disp,rn) nmd format nnnn xxxx dddd 15 0 mmmm mmmmdddd: indirect register with displacement nnnn: direct register mov.l @(disp,rm),rn
2. cpu rev.2.00 sep. 27, 2007 page 26 of 448 rej09b0394-0200 instruction formats source operand destination operand example dddddddd: indirect gbr with displacement r0 (direct register) mov.l @(disp,gbr),r0 r0 (direct register) dddddddd: indirect gbr with displacement mov.l r0,@(disp,gbr) dddddddd: pc relative with displacement r0 (direct register) mova @(disp,pc),r0 d format dddd xxxx 15 0 xxxx dddd ? dddddddd: pc relative bf label d12 format dddd xxxx 15 0 dddd dddd ? dddddddddddd: pc relative bra label (label = disp + pc) nd8 format dddd nnnn xxxx 15 0 dddd dddddddd: pc relative with displacement nnnn: direct register mov.l @(disp,pc),rn iiiiiiii: immediate indirect indexed gbr and.b #imm,@(r0,gbr) iiiiiiii: immediate r0 (direct register) and #imm,r0 i format xxxx xxxx i i i i 15 0 i i i i iiiiiiii: immediate ? trapa #imm ni format nnnn i i i i xxxx 15 0 i i i i iiiiiiii: immediate nnnn: direct register add #imm,rn note: * in multiply-and-accumulate instructions, nnnn is the source register. 2.5 instruction set 2.5.1 instruction set by classification table 2.10 lists the instructions according to their classification.
2. cpu rev.2.00 sep. 27, 2007 page 27 of 448 rej09b0394-0200 table 2.10 classification of instructions classification types operation code function no. of instructions mov data transfer, immediate data transfer, peripheral module data transfer, structure data transfer mova effective address transfer movt t bit transfer swap swap of upper and lower bytes data transfer 5 xtrct extraction of the middle of registers connected 39 21 add binary addition 33 addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division arithmetic operations div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate, double-length multiply-and-accumulate operation mul double-length multiply operation muls signed multiplication mulu unsigned multiplication neg negation negc negation with borrow sub binary subtraction subc binary subtraction with borrow subv binary subtraction with underflow
2. cpu rev.2.00 sep. 27, 2007 page 28 of 448 rej09b0394-0200 classification types operation code function no. of instructions 6 and logical and 14 not bit inversion or logical or tas memory test and bit set tst logical and and t bit set logic operations xor exclusive or shift 10 rotl one-bit left rotation 14 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift branch 9 bf conditional branch, conditional branch with delay (branch when t = 0) 11 bt conditional branch, conditional branch with delay (branch when t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure
2. cpu rev.2.00 sep. 27, 2007 page 29 of 448 rej09b0394-0200 classification types operation code function no. of instructions 11 clrt t bit clear 31 system control clrmac mac register clear ldc load to control register lds load to system register nop no operation rte return from exception processing sett t bit set sleep transition to power-down mode stc store control register data sts store system register data trapa trap exception handling total: 62 142 the table below shows the format of instruction codes, operation, and execution states. they are described by using this format according to their classification.
2. cpu rev.2.00 sep. 27, 2007 page 30 of 448 rej09b0394-0200 table 2.11 symbols used in instruction co de, operation, and execu tion states tables item format explanation instruction described in mnemonic. op.sz src,dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement * 2 instruction code described in msb ? lsb order mmmm: source register nnnn: destination register 0000: r0 0001: r1 ? ? ? 1111: r15 iiii: immediate data dddd: displacement , direction of transfer (xx) memory operand m/q/t flag bits in the sr & logical and of each bit | logical or of each bit ^ exclusive or of each bit ~ logical not of each bit <>n n-bit right shift execution states ? value when no wait states are inserted * 1 t bit ? value of t bit after instruction is executed. an em-dash ( ? ) in the column means no change. notes: 1. instruction execution states: the execution states shown in the table are minimums. the actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction. 2. depending on the operand size, displacement is scaled by 1, 2, or 4. for details, refer the sh-1/sh-2/sh-dsp software manual .
2. cpu rev.2.00 sep. 27, 2007 page 31 of 448 rej09b0394-0200 data transfer instructions table 2.12 data transfer instructions instruction instruction code operation execu- tion states t bit mov #imm,rn 1110nnnniiiiiiii #imm sign extension rn 1 ? mov.w @(disp,pc),rn 1001nnnndddddddd (disp 2 + pc) sign extension rn 1 ? mov.l @(disp,pc),rn 1101nnnndddddddd (disp 4 + pc) rn 1 ? mov rm,rn 0110nnnnmmmm0011 rm rn 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn 1 ? mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn 1 ? mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn 1 ? mov.b rm,@?rn 0010nnnnmmmm0100 rn?1 rn, rm (rn) 1 ? mov.w rm,@?rn 0010nnnnmmmm0101 rn?2 rn, rm (rn) 1 ? mov.l rm,@?rn 0010nnnnmmmm0110 rn?4 rn, rm (rn) 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn, rm + 1 rm 1 ? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn, rm + 2 rm 1 ? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn, rm + 4 rm 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp + rn) 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp 2 + rn) 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp 4 + rn) 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp + rm) sign extension r0 1 ? mov.w @(disp,rm),r0 10000101mmmmdddd (disp 2 + rm) sign extension r0 1 ?
2. cpu rev.2.00 sep. 27, 2007 page 32 of 448 rej09b0394-0200 instruction instruction code operation execu- tion states t bit mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp 4 + rm) rn 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0 + rn) 1 ? mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0 + rn) 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0 + rn) 1 ? mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0 + rm) sign extension rn 1 ? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0 + rm) sign extension rn 1 ? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0 + rm) rn 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp + gbr) 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp 2 + gbr) 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp 4 + gbr) 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp + gbr) sign extension r0 1 ? mov.w @(disp,gbr),r0 11000101dddddddd (disp 2 + gbr) sign extension r0 1 ? mov.l @(disp,gbr),r0 11000110dddddddd (disp 4 + gbr) r0 1 ? mova @(disp,pc),r0 11000111dddddddd disp 4 + pc r0 1 ? movt rn 0000nnnn00101001 t rn 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm swap bottom two bytes rn 1 ? swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn 1 ? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn 1 ?
2. cpu rev.2.00 sep. 27, 2007 page 33 of 448 rej09b0394-0200 arithmetic operation instructions table 2.13 arithmetic operation instructions instruction instruction code operation execu- tion states t bit add rm,rn 0011nnnnmmmm1100 rn + rm rn 1 ? add #imm,rn 0111nnnniiiiiiii rn + imm rn 1 ? addc rm,rn 0011nnnnmmmm1110 rn + rm + t rn, carry t 1 carry addv rm,rn 0011nnnnmmmm1111 rn + rm rn, overflow t 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t 1 comparison result cmp/pl rn 0100nnnn00010101 if rn > 0, 1 t 1 comparison result cmp/pz rn 0100nnnn00010001 if rn 0, 1 t 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t 1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn rm) 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t 1 calculation result
2. cpu rev.2.00 sep. 27, 2007 page 34 of 448 rej09b0394-0200 instruction instruction code operation execu- tion states t bit div0u 0000000000011001 0 m/q/t 1 0 dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bits 2 to 4 * ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bits 2 to 4 * ? dt rn 0100nnnn00010000 rn ? 1 rn, when rn is 0, 1 t. when rn is nonzero, 0 t 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 byte in rm is sign- extended rn 1 ? exts.w rm,rn 0110nnnnmmmm1111 word in rm is sign- extended rn 1 ? extu.b rm,rn 0110nnnnmmmm1100 byte in rm is zero- extended rn 1 ? extu.w rm,rn 0110nnnnmmmm1101 word in rm is zero- extended rn 1 ? mac.l @rm+,@rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 32 32 + 64 64 bits 3/ (2 to 4) * ? mac.w @rm+,@rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 16 16 + 64 64 bits 3/(2) * ? mul.l rm,rn 0000nnnnmmmm0111 rn rm macl, 32 32 32 bits 2 to 4 * ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm macl 16 16 32 bits 1 to 3 * ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm macl 16 16 32 bits 1 to 3 * ? neg rm,rn 0110nnnnmmmm1011 0 ? rm rn 1 ? negc rm,rn 0110nnnnmmmm1010 0 ? rm ? t rn, borrow t 1 borrow
2. cpu rev.2.00 sep. 27, 2007 page 35 of 448 rej09b0394-0200 instruction instruction code operation execu- tion states t bit sub rm,rn 0011nnnnmmmm1000 rn ? rm rn 1 ? subc rm,rn 0011nnnnmmmm1010 rn ? rm ? t rn, borrow t 1 borrow subv rm,rn 0011nnnnmmmm1011 rn ? rm rn, underflow t 1 overflow note: * the normal number of execution states is shown. (the number in parentheses is the number of states when there is contention wi th the preceding or following instructions.)
2. cpu rev.2.00 sep. 27, 2007 page 36 of 448 rej09b0394-0200 logic operation instructions table 2.14 logic opera tion instructions instruction instruction code operation execu- tion states t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn 1 ? and #imm,r0 11001001iiiiiiii r0 & imm r0 1 ? and.b #imm,@(r0,gbr) 11001101iiiiiiii (r0 + gbr) & imm (r0 + gbr) 3 ? not rm,rn 0110nnnnmmmm0111 ~rm rn 1 ? or rm,rn 0010nnnnmmmm1011 rn | rm rn 1 ? or #imm,r0 11001011iiiiiiii r0 | imm r0 1 ? or.b #imm,@(r0,gbr) 11001111iiiiiiii (r0 + gbr) | imm (r0 + gbr) 3 ? tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t 1 test result tst.b #imm,@(r0,gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 1 ? xor.b #imm,@(r0,gbr) 11001110iiiiiiii (r0 + gbr) ^ imm (r0 + gbr) 3 ?
2. cpu rev.2.00 sep. 27, 2007 page 37 of 448 rej09b0394-0200 shift instructions table 2.15 shift instructions instruction instruction code operation execu- tion states t bit rotl rn 0100nnnn00000100 t rn msb 1 msb rotr rn 0100nnnn00000101 lsb rn t 1 lsb rotcl rn 0100nnnn00100100 t rn t 1 msb rotcr rn 0100nnnn00100101 t rn t 1 lsb shal rn 0100nnnn00100000 t rn 0 1 msb shar rn 0100nnnn00100001 msb rn t 1 lsb shll rn 0100nnnn00000000 t rn 0 1 msb shlr rn 0100nnnn00000001 0 rn t 1 lsb shll2 rn 0100nnnn00001000 rn<<2 rn 1 ? shlr2 rn 0100nnnn00001001 rn>>2 rn 1 ? shll8 rn 0100nnnn00011000 rn<<8 rn 1 ? shlr8 rn 0100nnnn00011001 rn>>8 rn 1 ? shll16 rn 0100nnnn00101000 rn<<16 rn 1 ? shlr16 rn 0100nnnn00101001 rn>>16 rn 1 ?
2. cpu rev.2.00 sep. 27, 2007 page 38 of 448 rej09b0394-0200 branch instructions table 2.16 branch instructions instruction instruction code operation execu- tion states t bit bf label 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * ? bf/s label 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * ? bt label 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop 3/1 * ? bt/s label 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 2/1 * ? bra label 1010dddddddddddd delayed branch, disp 2 + pc pc 2 ? braf rm 0000mmmm00100011 delayed branch, rm + pc pc 2 ? bsr label 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc 2 ? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc 2 ? jmp @rm 0100mmmm00101011 delayed branch, rm pc 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc 2 ? rts 0000000000001011 delayed branch, pr pc 2 ? note: * one state when the program does not branch.
2. cpu rev.2.00 sep. 27, 2007 page 39 of 448 rej09b0394-0200 system control instructions table 2.17 system co ntrol instructions instruction instruction code operation execu- tion states t bit clrt 0000000000001000 0 t 1 0 clrmac 0000000000101000 0 mach, macl 1 ? ldc rm,sr 0100mmmm00001110 rm sr 1 lsb ldc rm,gbr 0100mmmm00011110 rm gbr 1 ? ldc rm,vbr 0100mmmm00101110 rm vbr 1 ? ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm + 4 rm 3 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm + 4 rm 3 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm + 4 rm 3 ? lds rm,mach 0100mmmm00001010 rm mach 1 ? lds rm,macl 0100mmmm00011010 rm macl 1 ? lds rm,pr 0100mmmm00101010 rm pr 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm + 4 rm 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm + 4 rm 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm + 4 rm 1 ? nop 0000000000001001 no operation 1 ? rte 0000000000101011 delayed branch, stack area pc/sr 4 ? sett 0000000000011000 1 t 1 1 sleep 0000000000011011 sleep 3 * ? stc sr,rn 0000nnnn00000010 sr rn 1 ? stc gbr,rn 0000nnnn00010010 gbr rn 1 ? stc vbr,rn 0000nnnn00100010 vbr rn 1 ? stc.l sr,@?rn 0100nnnn00000011 rn ? 4 rn, sr (rn) 2 ? stc.l gbr,@?rn 0100nnnn00010011 rn ? 4 rn, gbr (rn) 2 ? stc.l vbr,@?rn 0100nnnn00100011 rn ? 4 rn, vbr (rn) 2 ?
2. cpu rev.2.00 sep. 27, 2007 page 40 of 448 rej09b0394-0200 instruction instruction code operation execu- tion states t bit sts mach,rn 0000nnnn00001010 mach rn 1 ? sts macl,rn 0000nnnn00011010 macl rn 1 ? sts pr,rn 0000nnnn00101010 pr rn 1 ? sts.l mach,@?rn 0100nnnn00000010 rn ? 4 rn, mach (rn) 1 ? sts.l macl,@?rn 0100nnnn00010010 rn ? 4 rn, macl (rn) 1 ? sts.l pr,@?rn 0100nnnn00100010 rn ? 4 rn, pr (rn) 1 ? trapa #imm 11000011iiiiiiii pc/sr stack area, (imm 4 + vbr) pc 8 ? note: * the number of execution states before the chip enters sleep mode: the execution states shown in the table are minimums. the actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction.
2. cpu rev.2.00 sep. 27, 2007 page 41 of 448 rej09b0394-0200 2.6 processing states 2.6.1 state transitions the cpu has four processing states: reset, exception processing, program execution and power- down. figure 2.4 shows the transitions between the states. from any state when res = 0 from any state when res = 1 and mres = 0 res = 0 power-on reset state manual reset state program execution state sleep mode software standby mode exception processing state when a power-on reset or manual reset occurred by wdt exception processing source occurs exception processing ends ssby bit set for sleep instruction nmi or irq interrupt occurs power-down state res = 1 res = 1, mres = 1 ssby bit cleared for sleep instruction reset state figure 2.4 transitions between processing states
2. cpu rev.2.00 sep. 27, 2007 page 42 of 448 rej09b0394-0200 reset state: the cpu resets in the reset state. when the res pin level goes low, the power-on reset state is entered. when the res pin is high and the mres pin is low, the manual reset state is entered. exception processing state : the exception processing state is a transient state th at occurs when exception processing sources such as resets or interrupts alter the cpu's processing state flow. for a reset, the initial values of the program counter (pc) (execution start address) and stack pointer (sp) are fetched from the exception pro cessing vector table and stored; the cpu then branches to the execution start address and execution of the program begins. for an interrupt, the stack pointer (sp) is acce ssed and the program counter (pc) and status register (sr) are saved to the stack area. the exception service routine st art address is fetched from the exception processing vector table; the cpu then branches to that address and the program starts executing, thereby enteri ng the program execution state. program execution state : in the program execution state, the cpu sequentially executes the program. power-down state : in the power-down state, the cpu operation halts and power consumption declines. the sleep instruction pl aces the cpu in the sleep mode or the software standby mode.
3. mcu operating modes rev.2.00 sep. 27, 2007 page 43 of 448 rej09b0394-0200 section 3 mcu operating modes 3.1 selection of operating modes this lsi has one operating mode and four clock modes. the operating mode is determined by the setting of md3 to md0, and fwp pins. do not change these pins during lsi operation (while power is on). do not set these pins in the other way than the combination shown in table 3.1. this lsi supports only mode 3. table 3.1 selection of operating modes pin setting mode no. fwp md3 md2 md1 md0 mode name on-chip rom mode 3 1 x x 1 1 single chip mode active note: the symbol x means ?don't care.? the clock mode is selected by the input of md2 and md3 pins. table 3.2 maximum operating clock frequency for each clock mode pin setting md3 md2 maximum operating clock frequency 0 0 10 mhz (input clock 1, maximum of input clock: 10 mhz) 0 1 20 mhz (input clock 2, maximum of input clock: 10 mhz) 1 0 40 mhz (input clock 4 * , maximum of input clock: 10 mhz) 1 1 40 mhz (input clock 4 for system clock, input clock 2 for peripheral clock, maximum of input clock: 10 mhz) note: * the maximum of input clock is 10 mhz so that p is lower or equal to 40 mhz.
3. mcu operating modes rev.2.00 sep. 27, 2007 page 44 of 448 rej09b0394-0200 3.2 input/output pins table 3.3 describes the configuration of operating mode related pins. table 3.3 operating mode pin configuration pin name input/output function md0 input designates operating mode through the level applied to this pin md1 input designates operating mode through the level applied to this pin md2 input designates clock mode through the level applied to this pin md3 input designates clock mode through the level applied to this pin fwp input pin for the hardware protection against writing/erasing the on-chip flash memory. in this lsi, conncet this pin to v cc . 3.3 explanation of operating modes this lsi does not support modes 0 to 2 (mcu extension mode 0 to 2). 3.3.1 mode 3 (single chip mode) all ports can be used in this mode, however the external address cannot be used. the SH7101 supports only this mode. 3.3.2 clock mode the input waveform frequency can be used as is, doubled or quadrupled as system clock frequency.
3. mcu operating modes rev.2.00 sep. 27, 2007 page 45 of 448 rej09b0394-0200 3.4 address map figure 3.1 shows the address map. rom: 32 kbytes, ram: 2 kbytes h'00000000 h'00007fff h'ffff8000 h'ffffbfff h'ffffffff h'fffff800 on-chip rom on-chip ram on-chip peripheral i/o registers mode 3 figure 3.1 address map for SH7101 mask rom version
3. mcu operating modes rev.2.00 sep. 27, 2007 page 46 of 448 rej09b0394-0200 3.5 initial state of this lsi to reduce power consumption, some modules are set to the module stand by states in the initial state in this lsi. therefore, the module standby states should be cancelled to activate these modules. for details, see section 17, power-down modes.
4. clock pulse generator cpg0100a_010020030200 rev.2.00 sep. 27, 2007 page 47 of 448 rej09b0394-0200 section 4 clock pulse generator this lsi has an on-chip clock pulse generator (cpg) that generates the system clock ( ), internal clock ( /2 to /8192, p /2 to p /1024), and peripheral clock (p ). the cpg consists of an oscillator, pll circuit, and prescaler. a block diagram of the clock pulse generator is shown in figure 4.1. the frequency from the oscillator can be modified by the pll circuit. pllcap extal xtal md2 md3 prescaler prescaler oscillator pll circuit clock divider ( 1/2) clock mode control circuitry within the lsi /2 to /8192 p p /2 to p /1024 figure 4.1 block diagram of clock pulse generator 4.1 oscillator clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 connecting crystal resonator circuit configuration: a crystal resonator can be connected as shown in figure 4.2. use the damping resistance (rd) listed in table 4.1. use an at-cut parallel-resonance type crystal resonator that has a resonance frequency of 4 to 10 mhz. it is recommended to consult crystal dealer concerning the compatibility of the crystal resonator and the lsi.
4. clock pulse generator rev.2.00 sep. 27, 2007 page 48 of 448 rej09b0394-0200 extal xtal r d c l2 c l1 c l1 = c l2 = 18?22 pf (recommended value) figure 4.2 connection of crystal resonator (example) table 4.1 damping resistance values frequency (mhz) 4 8 10 rd ( ) 500 200 0 crystal resonator: figure 4.3 shows an equivalent circuit of the crystal resonator. use a crystal resonator with the characteristics listed in table 4.2. xtal at-cut parallel-resonance type c l extal c 0 l r s figure 4.3 crystal resonator equivalent circuit table 4.2 crystal resonator characteristics frequency (mhz) 4 8 10 rs max ( ) 120 80 60 c 0 max (pf) 7 7 7
4. clock pulse generator rev.2.00 sep. 27, 2007 page 49 of 448 rej09b0394-0200 4.1.2 external clock input method figure 4.4 shows an example of an external clock input connection. in this case, make the external clock high level to stop it in standby mode. during operation, make the external input clock frequency 4 to 10 mhz. when leaving the xtal pin open, make sure the parasitic capacitance is less than 10 pf. even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing standby mode, in order to ensure the pll stabilization time. extal xtal external clock input open state figure 4.4 example of external clock connection 4.2 function for detecting oscillator halt this cpg can detect a clock halt and automati cally cause the timer pins to become high- impedance when any system abnormality causes the oscillator to halt. that is, when a change of extal has not been detected, the high-current six pins (pe9/tioc3b, pe11/tioc3d, pe12/tioc4a, pe13/tioc4b/ mres , pe14/tioc4c, and pe15/tioc4d/ irqout ) are set to high-impedance regardless of pfc setting. even in standby mode, these six pins become high-impedance regardless of pfc setting. these pins enter the normal state after standby mode is released. when abnormalities that halt the oscillator occur except in standby mode, other lsi operations become undefined. in this case, lsi operations, including these six pins, become undefined even when the oscillator operation starts again.
4. clock pulse generator rev.2.00 sep. 27, 2007 page 50 of 448 rej09b0394-0200 4.3 usage notes 4.3.1 note on crystal resonator a sufficient evaluation at the user's site is neces sary to use the lsi, by referring the resonator connection examples shown in this section, becau se various characteristics related to the crystal resonator are closely linked to the user's board de sign. as the resonator circuit ratings will depend on the resonator and the floating capacitance of the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 4.3.2 notes on board design measures against radiation noise are taken in this lsi. if radiation noise needs to be further reduced, usage of a multi-layer printed circu it board with ground planes is recommended. when using a crystal resonator, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. do not route any signal lines near the oscillator circuitry as shown in figure 4.5. otherwise, correct oscillation can be interfered by induction. c l2 signal a signal b this lsi c l1 xtal extal avoid figure 4.5 cautions for oscillator circuit system board design a circuitry shown in figure 4.6 is recommended as an external circuitry around the pll. place oscillation stabilization capacitor c1 close to the pllcap pin, and ensure that no other signal lines cross this line. separate pllv cl , pllv ss , v cc , and v ss from the board power supply source, and be sure to insert bypass capacitors cb close to the pins.
4. clock pulse generator rev.2.00 sep. 27, 2007 page 51 of 448 rej09b0394-0200 pllcap pllv cl pllv ss v cc v ss c1: 470 pf cpb = 0.47 f * cb = 0.47 f * (values are recommended values.) note: * cb and cpb are laminated ceramic type. r1: 3 k figure 4.6 recommended external circuitry around pll electromagnetic waves are radiated from an lsi in operation. this lsi has an electromagnetic peak in the harmonics band whose primary frequency is determined by the lower frequency between the system clock ( ) and peripheral clock (p ). for example, when = 40 mhz and p = 40 mhz, the primary frequency is 40 mhz. if this lsi is used adjacent to a device sensitive to electromagnetic interference, e.g. fm/vhf band receiver, a printed circuit board of more than four layers with planes exclusively for system ground is recommended.
4. clock pulse generator rev.2.00 sep. 27, 2007 page 52 of 448 rej09b0394-0200
5. exception processing rev.2.00 sep. 27, 2007 page 53 of 448 rej09b0394-0200 section 5 exception processing 5.1 overview 5.1.1 types of exception processing and priority exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. when several exception processing sources occur at once, they are processed according to the priority. table 5.1 types of exception processing and priority exception source priority reset power-on reset high manual reset address error cpu address error interrupt nmi irq on-chip peripheral modules: ? multifunction timer unit (mtu) ? a/d converter 0 and 1 (a/d0, a/d1) ? compare match timer 0 and 1 (cmt0, cmt1) ? watchdog timer (wdt) ? input/output port (i/o) (mtu) ? serial communication interface 2 and 3 (sci2, sci3) instructions trap instruction (trapa instruction) general illegal instructions (undefined code) illegal slot instructions (undefined code placed directly after a delayed branch instruction * 1 or instructions that rewrite the pc * 2 ) low notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, and braf. 2. instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, and braf.
5. exception processing rev.2.00 sep. 27, 2007 page 54 of 448 rej09b0394-0200 5.1.2 exception processing operations the exception processing sources are detected a nd the processing starts according to the timing shown in table 5.2. table 5.2 timing for exception source det ection and start of ex ception processing exception source timing of source detection and start of processing power-on reset starts when the res pin changes from low to high or when wdt overflows. reset manual reset starts when the mres pin changes from low to high. address error interrupts detected when instruction is decoded and starts when the execution of the previous instruction is completed. trap instruction starts from the execution of a trapa instruction. instructions general illegal instructions starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). illegal slot instructions starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the pc. when exception processing starts , the cpu operates as follows: 1. exception processing triggered by reset: the initial values of the program counter (pc) and stack pointer (sp) are fetched from the exception processing vector table (pc and sp are respectively the h'00000000 and h'00000004 addresses for power-on resets and the h'00000008 and h'0000000c addresses for manual resets). see section 5.1.3, exception pro cessing vector table, for more information. h'00000000 is then written to the vector base re gister (vbr), and h'f (b'1111) is written to the interrupt mask bits (i3 to i0) of the status register (sr). the program begins running from the pc address fetched from the exception processing vector table. 2. exception processing triggered by address errors, interrupts and instructions: sr and pc are saved to the stack indicated by r15. for interrupt exception processing, the interrupt priority level is written to the sr's interrupt mask bits (i3 to i0). for address error and instruction exception processing, the i3 to i0 b its are not affected. the start address is then fetched from the exception processing vector table and the program begins running from that address.
5. exception processing rev.2.00 sep. 27, 2007 page 55 of 448 rej09b0394-0200 5.1.3 exception processing vector table before exception processing begins running, the exception processing vector table must be set in memory. the exception processing vector table st ores the start addresses of exception service routines. (the reset exception processing table holds the initial values of pc and sp.) all exception sources are given different vector numbers and vector table address offsets. the vector table addresses are calculated from these v ector numbers and vector table address offsets. during exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table that is indicated by th is vector table address. table 5.3 shows the vector numbers and vector table address offsets. table 5.4 shows how vector table addresses are calculated. table 5.3 exception processing vector table exception sources vector number s vector table address offset power-on reset pc 0 h'00000000 to h'00000003 sp 1 h'00000004 to h'00000007 manual reset pc 2 h'00000008 to h'0000000b sp 3 h'0000000c to h'0000000f general illegal instruction 4 h'00000010 to h'00000013 (reserved by system) 5 h'00000014 to h'00000017 slot illegal instruction 6 h'00000018 to h'0000001b (reserved by system) 7 h'0000001c to h'0000001f 8 h'00000020 to h'00000023 cpu address error 9 h'00000024 to h'00000027 (reserved by system) 10 h'00000028 to h'0000002b interrupts nmi 11 h'0000002c to h'0000002f (reserved by system) 12 h'00000030 to h'00000033 (reserved by system) 13 h'00000034 to h'00000037 (reserved by system) 14 h'00000038 to h'0000003b (reserved by system) 15 : 31 h'0000003c to h'0000003f : h'0000007c to h'0000007f
5. exception processing rev.2.00 sep. 27, 2007 page 56 of 448 rej09b0394-0200 exception sources vector number s vector table address offset trap instruction (user vector) 32 : 63 h'00000080 to h'00000083 : h'000000fc to h'000000ff interrupts irq0 64 h'00000100 to h'00000103 irq1 65 h'00000104 to h'00000107 irq2 66 h'00000108 to h'0000010b irq3 67 h'0000010c to h'0000010f reserved by system 68 h'00000110 to h'00000113 reserved by system 69 h'00000114 to h'00000117 reserved by system 70 h'00000118 to h'0000011b reserved by system 71 h'0000011c to h'0000011f on-chip peripheral module * 72 : 255 h'00000120 to h'00000124 : h'000003fc to h'000003ff note: * the vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, interrupt controller (intc), and table 6.2, interrupt exception processing vectors and priorities. table 5.4 calculating exception pr ocessing vector table addresses exception source vector table address calculation resets vector table address = (vector table address offset) = (vector number) 4 address errors, interrupts, instructions vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 notes: 1. vbr: vector base register 2. vector table address offset: see table 5.3. 3. vector number: see table 5.3.
5. exception processing rev.2.00 sep. 27, 2007 page 57 of 448 rej09b0394-0200 5.2 resets 5.2.1 types of reset resets have the highest priority of any exception source. there are two types of resets: manual resets and power-on resets. as table 5.5 shows, both types of resets initialize the internal status of the cpu. in power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. table 5.5 reset status conditions for transition to reset status internal status type res wdt overflow mres cpu/intc on-chip peripheral module pfc, io port low ? ? initialized initialized initialized power-on reset high overflow high initialized initialized not initialized manual reset high ? low initialized not initialized not initialized 5.2.2 power-on reset power-on reset by res pin: when the res pin is driven low, the lsi becomes to be a power- on reset state. to reliably reset the lsi, the res pin should be kept at low for at least the duration of the oscillation settling time when applying powe r or when in standby mode (when the clock circuit is halted) or at least 25 t cyc when the clock circuit is running. during power-on reset, cpu internal status and all registers of on-chip peripheral modules are initialized. see appendix a, pin states, for the status of individual pins during the power-on reset status. in the power-on reset status, power-on reset exception processing starts when the res pin is first driven low for a set period of time and then returned to high. the cpu will then operate as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception processing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) of the status register (sr) are set to h'f (b'1111). 4. the values fetched from the exception processi ng vector table are set in pc and sp, then the program begins executing.
5. exception processing rev.2.00 sep. 27, 2007 page 58 of 448 rej09b0394-0200 be certain to always perform power-on reset processing when turning the system power on. power-on reset by wdt: when a setting is made for a power-on reset to be generated in the wdt's watchdog timer mode, and the wdt's tcnt overflows, the lsi becomes to be a power- on reset state. the pin function controller (pfc) registers and i/o port registers are not initialized by the reset signal generated by the wdt (these registers are initialized only by a power-on reset from outside of the chip). if reset caused by the input signal at the res pin and a reset caused by wdt overflow occur simultaneously, the res pin reset has priority, and the wovf bit in rstcsr is cleared to 0. when wdt-initiated power-on reset processing is started, the cpu operates as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception processing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3-i0) of the status register (sr) are set to h'f (b'1111). 4. the values fetched from the exception processi ng vector table are set in the pc and sp, then the program begins executing. 5.2.3 manual reset when the res pin is high and the mres pin is driven low, the lsi en ters a manual reset state. to reliably reset the lsi, the mres pin should be kept at low for at least the duration of the oscillation settling time that is set in wdt in sta ndby mode (when the clock is halted) or at least 25 t cyc when the clock is operating. during manual reset, the cpu internal status is initialized. registers of on-chip peripheral modules are not initialized. when the lsi enters manual reset status in the middle of a bus cycle, manual reset exception processing does not start until the bus cycle has ended. thus, manual resets do not abort bus cycles. however, once mres is driven low, hold the low level until the cpu becomes to be a manual reset mode after the bus cycle ends. (keep at low level for at least the longest bus cycle). see appendix a, pin states, for the status of individual pins during manual reset mode. in the manual reset status, manual reset exception processing starts when the mres pin is first kept low for a set period of time and then returned to high. the cpu will then operate in the same procedures as described for power-on resets.
5. exception processing rev.2.00 sep. 27, 2007 page 59 of 448 rej09b0394-0200 5.3 address errors 5.3.1 cause of address error exception address errors occur when instructions are fetched or data is read or written, as shown in table 5.6. table 5.6 bus cycles and address errors bus cycle type bus master bus cycle description address errors cpu instruction fetched from even address none (normal) instruction fetched from odd address address error occurs instruction fetched from other than on-chip peripheral module space * none (normal) instruction fetched from on-chip peripheral module space * address error occurs instruction fetch instruction fetched from external memory space when in single chip mode address error occurs word data accessed from even address none (normal) word data accessed from odd address address error occurs longword data accessed from a longword boundary none (normal) longword data accessed from other than a long-word boundary address error occurs byte or word data accessed in on-chip peripheral module space * none (normal) longword data accessed in 16-bit on-chip peripheral module space * none (normal) data read/write cpu longword data accessed in 8-bit on-chip peripheral module space * address error occurs external memory space accessed when in single chip mode address error occurs note: * see section 7, bus state controller (bsc) for more information on the on-chip peripheral module space.
5. exception processing rev.2.00 sep. 27, 2007 page 60 of 448 rej09b0394-0200 5.3.2 address error exception processing when an address error occurs, the bus cycle in which the address error occurred ends, the current instruction finishes, and then address error exception processing starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the last executed instruction. 3. the start address of the exception service routine is fetched from the exception processing vector table that corresponds to the occurred address error, and the program starts executing from that address. the jump in this case is not a delayed branch. 5.4 interrupts 5.4.1 interrupt sources table 5.7 shows the sources that start the interrupt exception processing. they are nmi, irq and on-chip peripheral modules. table 5.7 interrupt sources type request source number of sources nmi nmi pin (external input) 1 irq irq0 to irq3 pins (external input) 4 on-chip peripheral module multifunction timer unit 23 compare match timer 2 a/d converter (a/d0 and a/d1) 2 serial communication interface 8 watchdog timer 1 input/output port 1 each interrupt source is allocated a different vector number and vector table offset. see section 6, interrupt controller (intc), and table 6.2, interrupt exception processing vectors and priorities, for more information on vector numbers and vector table address offsets.
5. exception processing rev.2.00 sep. 27, 2007 page 61 of 448 rej09b0394-0200 5.4.2 interrupt priority level the interrupt priority is predetermined. when multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (intc) determines their relative priorities and starts the exception processi ng according to the results. the priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has priority 16 and cannot be masked, so it is always accepted. irq interrupts and on-chip peripheral modu le interrupt priority levels can be set freely using the intc's interrupt priority registers a, d to i (ipra, iprd to ipri) as shown in table 5.8. the priority levels that can be set are 0 to 15. level 16 cannot be set. see section 6.3.4, interrupt priority registers a, d to i (ipra, iprd to ipri), for more information on ipra, iprd to ipri. table 5.8 interrupt priority type priority level comment nmi 16 fixed priority level. cannot be masked. irq on-chip peripheral module 0 to 15 set with interrupt priority registers a, d to i (ipra, iprd to ipri). 5.4.3 interrupt exception processing when an interrupt occurs, the interrupt controller (intc) ascertains its priority level. nmi is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3 to i0) of the status register (sr). when an interrupt is accepted, ex ception processing begins. in inte rrupt exception processing, the cpu saves sr and the program counter (pc) to th e stack. the priority leve l value of the accepted interrupt is written to sr bits i3 to i0. for nmi, however, the priority level is 16, but the value set in i3 to i0 is h'f (level 15). next, the start a ddress of the exception service routine is fetched from the exception processing vector table for the accept ed interrupt, that addr ess is jumped to and execution begins. see section 6.6, operation, for more information on the interrupt exception processing.
5. exception processing rev.2.00 sep. 27, 2007 page 62 of 448 rej09b0394-0200 5.5 exceptions triggered by instructions 5.5.1 types of exceptions tr iggered by instructions exception processing can be triggered by trap instru ction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. table 5.9 types of exceptions triggered by instructions type source instruction comment trap instruction trapa ? illegal slot instructions undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that rewrite the pc delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instructions undefined code anywhere besides in a delay slot ? 5.5.2 trap instructions when a trapa instruction is executed, trap instruction exception processing starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the cpu reads the start addr ess of the exception service rou tine from the exception processing vector table that corresponds to the vector nu mber specified in the tr apa instruction, jumps to that address and starts executing the program. this jump is not a delayed branch.
5. exception processing rev.2.00 sep. 27, 2007 page 63 of 448 rej09b0394-0200 5.5.3 illegal slot instructions an instruction placed imme diately after a delayed branch inst ruction is called ?instruction placed in a delay slot?. when the instruction placed in the delay slot is an undefined code, illegal slot exception processing starts after the undefined code is decoded. illegal slot exception processing also starts when an inst ruction that rewrites the program counte r (pc) is placed in a delay slot and the instruction is decoded. the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the start address of the exception service routine is fetched from the exception processing vector table that corresponds to the exception that occurred. that address is jumped to and the program starts executing. the jump in this case is not a delayed branch. 5.5.4 general illegal instructions when undefined code placed anywhe re other than immediately afte r a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. the cpu handles the general illegal instructions in the same procedures as in the illegal slot instructions. unlike processing of illegal slot instructions, however , the program counter value that is stacked is the start address of the undefined code.
5. exception processing rev.2.00 sep. 27, 2007 page 64 of 448 rej09b0394-0200 5.6 cases when exception sources are not accepted when an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction, it is sometimes not accepted immedi ately but stored instead, as shown in table 5.10. in this case, it will be accepted when an instruction that can accept the exception is decoded. table 5.10 generation of excep tion sources immediately aft er delayed branch instruction or interrupt-disabled instruction exception source point of occurrence address error interrupt immediately after a delayed branch instruction * 1 not accepted not accepted immediately after an interrupt-disabled instruction * 2 accepted not accepted notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, and braf 2. interrupt-disabled instructions: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, and sts.l 5.6.1 immediately after delayed branch instruction when an instruction placed immediat ely after a delayed branch instru ction (delay slot) is decoded, neither address errors nor interrupts are accepte d. the delayed branch instruction and the instruction placed immedi ately after it (delay slot) are alwa ys executed consecutively, so no exception processing occurs during this period. 5.6.2 immediately after interrupt-disabled instruction when an instruction placed imme diately after an interrupt-disa bled instruction is decoded, interrupts are not accepted. address errors can be accepted.
5. exception processing rev.2.00 sep. 27, 2007 page 65 of 448 rej09b0394-0200 5.7 stack status after excep tion processing ends the status of the stack after exception processing ends is shown in table 5.11. table 5.11 stack status after exception processing ends types stack status address error 32 bits 32 bits sr address of instruction after executed instruction sp trap instruction 32 bits 32 bits sr address of instruction after trapa instruction sp general illegal instruction 32 bits 32 bits sr address of instruction after general illegal instruction sp interrupt 32 bits 32 bits sr address of instruction after executed instruction sp illegal slot instruction 32 bits 32 bits sr jump destination address of delay branch instruction sp
5. exception processing rev.2.00 sep. 27, 2007 page 66 of 448 rej09b0394-0200 5.8 usage notes 5.8.1 value of stack pointer (sp) the value of the stack pointer must always be a multiple of four. if it is not, an address error will occur when the stack is accesse d during exception processing. 5.8.2 value of vector base register (vbr) the value of the vector base register must always be a multiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 address errors caused by stacking of address error exception processing when the value of the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start after the first exception processing is ended. address errors will also occur in the stacking for this address error exception processing. to ensure that address error exception processing does not go into an endless loop, no address errors are accep ted at that point. this allows program control to be shifted to the service routine for addr ess error exception and enables error processing. when an address error occurs during exception pr ocessing stacking, the stacking bus cycle (write) is executed. during stacking of the status register (sr) and program counter (pc), the value of sp is reduced by 4 for both of sr and pc, therefore the value of sp is still not a multiple of four after the stacking. the address value output during stacking is the sp value, so the address itself where the error occurred is output. this means that the write data stacked is undefined.
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 67 of 448 rej09b0394-0200 section 6 interrupt controller (intc) the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. 6.1 features ? 16 levels of interrupt priority ? nmi noise canceler function ? occurrence of interrupt can be reported externally ( irqout pin) figure 6.1 shows a block diagram of the intc. irqout nmi irq0 irq1 irq2 irq3 mtu cmt a/d sci wdt i/o (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) input control com- parator interrupt request sr cpu i3 i2 i1 i0 internal bus bus interface ipra to ipri icr1 isr icr2 module bus intc ipr cpu request determination priority determination mtu cmt a/d sci wdt legend: : multifunction timer unit : compare match timer : a/d converter : serial communications interface : watchdog timer i/o icr1, icr2 isr ipra, iprd to ipri sr : i/o port (port output controller) : interrupt control register : irq status register : interrupt priority registers a, d to i : status register figure 6.1 intc block diagram
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 68 of 448 rej09b0394-0200 6.2 input/output pins table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbreviation i/o function non-maskable interrupt input pin nmi i input of non-maskable interrupt request signal interrupt request input pins irq0 to irq3 i input of maskable interrupt request signals interrupt request output pin irqout o output of notification signal when an interrupt has occurred 6.3 register descriptions the interrupt controller has the following registers. for details on register addresses and register states during each processing, refer to section 18, list of registers. ? interrupt control register 1 (icr1) ? interrupt control register 2 (icr2) ? irq status register (isr) ? interrupt priority register a (ipra) ? interrupt priority register d (iprd) ? interrupt priority register e (ipre) ? interrupt priority register f (iprf) ? interrupt priority register g (iprg) ? interrupt priority register h (iprh) ? interrupt priority register i (ipri)
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 69 of 448 rej09b0394-0200 6.3.1 interrupt control register 1 (icr1) icr1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins nmi and irq0 to irq3 and indicates the input signal level at the nmi pin. bit bit name initial value r/w description 15 nmil 1/0 r nmi input level sets the level of the signal input to the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. 0: nmi input level is low 1: nmi input level is high 14 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 nmie 0 r/w nmi edge select 0: interrupt request is detected on falling edge of nmi input (initial value) 1: interrupt request is detected on rising edge of nmi input 7 irq0s 0 r/w irq0 sense select this bit sets the irq0 interrupt request detection mode. 0: interrupt request is detected on low level of irq0 input 1: interrupt request is detected on edge of irq0 input (edge direction is selected by icr2) 6 irq1s 0 r/w irq1 sense select this bit sets the irq1 interrupt request detection mode. 0: interrupt request is detected on low level of irq1 input 1: interrupt request is detected on edge of irq1 input (edge direction is selected by icr2) 5 irq2s 0 r/w irq2 sense select this bit sets the irq2 interrupt request detection mode. 0: interrupt request is detected on low level of irq2 input 1: interrupt request is detected on edge of irq2 input (edge direction is selected by icr2)
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 70 of 448 rej09b0394-0200 bit bit name initial value r/w description 4 irq3s 0 r/w irq3 sense select this bit sets the irq3 interrupt request detection mode. 0: interrupt request is detected on low level of irq3 input 1: interrupt request is detected on edge of irq3 input (edge direction is selected by icr2) 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 6.3.2 interrupt control register 2 (icr2) icr2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins irq0 to irq3. icr2 is, however, valid only when irq interrupt request detection mode is set to the edge detection mode by the sense select bits of irq0 to irq 3 in interrupt control register 1 (icr1). if the irq interrupt request detection mode has been set to low level detection mode, the setting of icr2 is ignored. bit bit name initial value r/w description 15 14 irq0es1 irq0es0 0 0 r/w r/w this bit sets the irq0 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq0 input 01: interrupt request is detected on rising edge of irq0 input 10: interrupt request is detected on both of falling and rising edge of irq0 input 11: cannot be set
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 71 of 448 rej09b0394-0200 bit bit name initial value r/w description 13 12 irq1es1 irq1es0 0 0 r/w r/w this bit sets the irq1 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq1 input 01: interrupt request is detected on rising edge of irq1 input 10: interrupt request is detected on both of falling and rising edge of irq1 input 11: cannot be set 11 10 irq2es1 irq2es0 0 0 r/w r/w this bit sets the irq2 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq2 input 01: interrupt request is detected on rising edge of irq2 input 10: interrupt request is detected on both of falling and rising edge of irq2 input 11: cannot be set 9 8 irq3es1 irq3es0 0 0 r/w r/w this bit sets the irq3 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq3 input 01: interrupt request is detected on rising edge of irq3 input 10: interrupt request is detected on both of falling and rising edge of irq3 input 11: cannot be set 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 72 of 448 rej09b0394-0200 6.3.3 irq status register (isr) isr is a 16-bit register that indicates the interrupt request status of the external interrupt input pins irq0 to irq3. when irq interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to irqnf after reading irqnf = 1. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 5 4 irq0f irq1f irq2f irq3f 0 0 0 0 r/w r/w r/w r/w irq0 to irq3 flags these bits display the irq0 to irq3 interrupt request status. [setting condition] ? when interrupt source that is selected by icr1 and icr2 has occurred. [clearing conditions] ? when 0 is written after reading irqnf = 1 ? when interrupt exception processing has been executed at high level of irqn input under the low level detection mode. ? when irqn interrupt exception processing has been executed under the edge detection mode of falling edge, rising edge or both of falling and rising edge. 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 73 of 448 rej09b0394-0200 6.3.4 interrupt priority registers a, d to i (ipra, iprd to ipri) interrupt priority registers are seven 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except nmi. for the correspondence between interrupt request sources and ipr, refer to table 6.2 interrupt exception processing vectors and priorities. each of the corresponding interrupt priority ranks are establis hed by setting a value from h'0 to h'f in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. reserved bits that are not assigned should be set h'0 (b'0000.) bit bit name initial value r/w description 15 14 13 12 ipr15 ipr14 ipr13 ipr12 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest)
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 74 of 448 rej09b0394-0200 bit bit name initial value r/w description 11 10 9 8 ipr11 ipr10 ipr9 ipr8 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) 7 6 5 4 ipr7 ipr6 ipr5 ipr4 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest)
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 75 of 448 rej09b0394-0200 bit bit name initial value r/w description 3 2 1 0 ipr3 ipr2 ipr1 ipr0 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) note: name in the tables above is represented by a general name. name in the list of register is, on the other hand, represented by a module name. 6.4 interrupt sources 6.4.1 external interrupts there are three types of interrupt sources: nmi, irq, and on-chip peripheral modules. each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). giving an interrupt a priority level of 0 masks it. nmi interrupts: the nmi interrupt has priority 16 and is always accepted. input at the nmi pin is detected by edge. use the nmi edge select bit (nmie) in the interrupt control register 1 (icr1) to select either the rising or falling edge. nmi interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to level 15. irq3 to irq0 interrupts: irq interrupts are requested by input from pins irq0 to irq3 . set the irq sense select bits (irq0s to irq3s) of the interrupt control register 1 (icr1) and irq edge select bit (irq0es[1:0] to irq3es[1:0]) of the interrupt control register 2 (icr2) to select low level detection, falling edge detection, or rising edge detection for each pin. the priority level can be set from 0 to 15 for each pin using the interrupt priority register a (ipra).
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 76 of 448 rej09b0394-0200 when irq interrupts are set to low level detection, an interrupt request signal is sent to the intc during the period the irq pin is low level. interrupt request signals are not sent to the intc when the irq pin becomes high level. interrupt request levels can be confirmed by reading the irq flags (irq0f to irq3f) of the irq status register (isr). when irq interrupts are set to falling edge detection, interrupt request signals are sent to the intc upon detecting a change on the irq pin from high to low level. the results of detection for irq interrupt request are maintained until the in terrupt request is accepted. it is possible to confirm that irq interrupt requests have been detected by reading the irq flags (irq0f to irq3f) of the irq status register (isr), and by writing a 0 after reading a 1, irq interrupt request detection results can be withdrawn. in irq interrupt exception processing, the interrupt mask bits (i3 to i0) of the status register (sr) are set to the priority level value of the accepted irq interrupt. figure 6.2 shows the block diagram of this irq3 to irq0 interrupts. irqns irqnes isr.irqnf irq pins resirqn level detection edge detection sq r selection cpu interrupt request (acceptance of irqn interrupt/writing 0 after reading irqnf = 1) figure 6.2 block diagram of irq3 to irq0 interrupts control
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 77 of 448 rej09b0394-0200 6.4.2 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupt s generated by the following on-chip peripheral modules. as a different interrupt vector is assigned to each interrupt source, the exception service routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers a, d to i (ipra, iprd to ipri). on-chip peripheral module interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.5 interrupt exception processing vectors table table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. each interrupt source is allocated a different vector number and vector table address offset. vector table addresses are calculated from the vector numbers and address offsets. in interrupt exception processing, the exception service r outine start address is fetched fr om the vector table indicated by the vector table address. for the details of calculation of vector table address, see table 5.4, calculating exception processing vector table addresses in the section 5 exception processing. irq interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers a, d to i (ipra, iprd to ipri). however, the smaller vector number has interrupt source, the higher priority ranking is assigned among two or more interrupt sources specified by the same ipr, and the priority ranking cannot be changed. a power-on reset assigns priority level 0 to irq interrupts and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order indicated in table 6.2.
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 78 of 448 rej09b0394-0200 table 6.2 interrupt exception pro cessing vectors and priorities interrupt source name vector no. vector table starting address ipr default priority external pin nmi 11 h'0000002c ? high ? reserved by system 12 h'00000030 ? ? reserved by system 14 h'00000038 ? ? reserved by system 15 h'0000003c ? irq0 64 h'00000100 ipra15 to ipra12 irq1 65 h'00000104 ipra11 to ipra8 irq2 66 h'00000108 ipra7 to ipra4 irq3 67 h'0000010c ipra3 to ipra0 reserved by system 68 h'00000110 ? reserved by system 69 h'00000114 ? reserved by system 70 h'00000118 ? interrupts reserved by system 71 h'0000011c ? reserved by system 72 h'00000120 ? reserved by system 76 h'00000130 ? reserved by system 80 h'00000140 ? ? reserved by system 84 h'00000150 ? tgia_0 88 h'00000160 tgib_0 89 h'00000164 iprd15 to iprd12 tgic_0 90 h'00000168 tgid_0 91 h'0000016c mtu channel 0 tciv_0 92 h'00000170 iprd11 to iprd8 mtu channel 1 tgia_1 96 h'00000180 iprd7 to iprd4 tgib_1 97 h'00000184 tciv_1 100 h'00000190 iprd3 to iprd0 tciu_1 101 h'00000194 low
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 79 of 448 rej09b0394-0200 interrupt source name vector no. vector table starting address ipr default priority mtu channel 2 tgia_2 104 h'000001a0 high tgib_2 105 h'000001a4 ipre15 to ipre12 tciv_2 108 h'000001b0 ipre11 to ipre8 tciu_2 109 h'000001b4 mtu channel 3 tgia_3 112 h'000001c0 ipre7 to ipre4 tgib_3 113 h'000001c4 tgic_3 114 h'000001c8 tgid_3 115 h'000001cc tciv_3 116 h'000001d0 ipre3 to ipre0 mtu channel 4 tgia_4 120 h'000001e0 tgib_4 121 h'000001e4 iprf15 to iprf12 tgic_4 122 h'000001e8 tgid_4 123 h'000001ec tciv_4 124 h'000001f0 iprf11 to iprf8 ? reserved by system 128 to 135 h'00000200 to h'0000021c ? a/d adi0 136 h'00000220 adi1 137 h'00000224 iprg15 to iprg12 ? reserved by system 140 h'00000230 ? cmt cmi0 144 h'00000240 iprg7 to iprg4 cmi1 148 h'00000250 iprg3 to iprg0 watchdog timer iti 152 h'00000260 iprh15 to iprh12 ? reserved by system 153 h'00000264 ? i/o (mtu) mtupoe 156 h'00000270 iprh11 to iprh8 ? reserved by system 160 to 167 h'00000290 to h'0000029c ? sci channel 2 eri_2 168 h'000002a0 ipri15 to ipri12 rxi_2 169 h'000002a4 txi_2 170 h'000002a8 tei_2 171 h'000002ac low
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 80 of 448 rej09b0394-0200 interrupt source name vector no. vector table starting address ipr default priority sci channel 3 eri_3 172 h'000002b0 ipri11 to ipri8 high rxi_3 173 h'000002b4 txi_3 174 h'000002b8 tei_3 175 h'000002bc ? reserved by system 176 h'000002c0 ? reserved by system 177 h'000002c4 reserved by system 178 h'000002c8 reserved by system 179 h'000002cc ? reserved by system 180 h'000002d0 ? reserved by system 181 h'000002d4 ? reserved by system 184 h'000002e0 ? ? reserved by system 188 to 196 h'000002f0 to h'00000310 ? ? reserved by system 200 h'00000320 ? ? reserved by system 204 h'00000330 ? ? reserved by system 208 h'00000340 ? reserved by system 209 h'00000344 reserved by system 210 h'00000348 reserved by system 211 h'0000034c ? reserved by system 212 h'00000350 to h'000003dc ? low
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 81 of 448 rej09b0394-0200 6.6 operation 6.6.1 interrupt sequence the sequence of interrupt operations is explained below. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest priority interrupt in the interrupt requests sent, according to the prio rity levels set in interr upt priority registers a, d to i (ipra, iprd to ipri). interrupts that have lower-priority than that of the selected interrupt are ignored.* if interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest pr iority is selected acco rding to the default priority order indicated in table 6.2. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3 to i0) in the cpu's status register (sr). if the request priority level is equal to or less than the level set in i3 to i0, the request is ignored. if the request priority level is higher than the level in bits i3 to i0, the interrupt contro ller accepts the interrupt and sends an interrupt request signal to the cpu. 4. when the interrupt controller accepts an interrupt, a low level is output from the irqout pin. 5. the cpu detects the interrupt request sent from the interrupt controller when cpu decodes the instruction to be executed. instead of executing the decoded instruction, the cpu starts interrupt exception processing (figure 6.5). 6. sr and pc are saved onto the stack. 7. the priority level of the accepted interrupt is copi ed to the interrupt mask level bits (i3 to i0) in the status register (sr). 8. when the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the irqout pin. when the accepted interrupt is sensed by edge, a high level is output from the irqout pin at the moment when the cpu starts interrupt exception processing instead of instruction execution as noted in (5) above. however, if the interrupt controller accepts an interrupt with a higher priority th an the interrupt just to be accepting, the irqout pin holds low level. 9. the cpu reads the start address of the ex ception service routine fro m the exception vector table for the accepted interrupt, ju mps to that address, and starts executing the program. this jump is not a delay branch. note: * interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. irq interrupts, however, can be cancelled by accessing the irq status register (isr). interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset.
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 82 of 448 rej09b0394-0200 program execution state interrupt? nmi? i3 to i0 level 14? level 14 interrupt? level 1 interrupt? i3 to i0 level 13? i3 to i0 = level 0? no yes no no no no no no yes yes yes yes yes yes yes irqout = low * 1 save sr to stack copy accept-interrupt level to i3 to i0 irqout = high read exception vector table branch to exception service routine * 2 level 15 interrupt? notes: i3 to i0 are interrupt mask bits of status register (sr) in the cpu 1. irqout is the same signal as interrupt request signal to the cpu (see figure 6.1). therefore, irqout is output when the request priority level is higher than the level in bits i3?i0 of sr. 2. when the accepted interrupt is sensed by edge, a high level is output from the irqout pin at the moment when the cpu starts interrupt exception processing instead of instruction execution (namely, before saving sr to stack). however, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the cpu, the irqout pin holds low level. no save pc to stack figure 6.3 interrupt sequence flowchart
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 83 of 448 rej09b0394-0200 6.6.2 stack after interrupt exception processing figure 6.4 shows the stack after interrupt exception processing. 32 bits 32 bits pc * 1 sr address 4n?8 4n?4 4n sp * 2 notes: 1. pc: start address of the next instruction (return destination instruction) after the executing instruction 2. always make sure that sp is a multiple of 4 figure 6.4 stack after interrupt exception processing
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 84 of 448 rej09b0394-0200 6.7 interrupt response time table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. figure 6.5 shows an example of the pipeline operation when an irq interrupt is accepted. table 6.3 interrupt response time number of states item nmi, peripheral module irq remarks idle cycle 0 or 1 1 interrupt priority judgment and comparison with sr mask bits 2 3 wait for completion of sequence currently being executed by cpu x ( 0) x ( 0) the longest sequence is for interrupt or address-error exception processing (x = 4 + m1 + m2 + m3 + m4). if an interrupt-masking instruction follows, however, the time may be even longer. time from start of interrupt exception processing until fetch of first instruction of exception service routine starts 5 + m1 + m2 + m3 5 + m1 + m2 + m3 performs the saving pc and sr, and vector address fetch. total: (7 or 8) + m1 + m2 + m3 + x 9 + m1 + m2 + m3 + x interrupt response time minimum: 10 12 0.25 to 0.28 s maximum: 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 0.48 s * note: * 0.48 s at 40 mhz is the value in the case that m1 = m2 = m3 = m4 = 1. m1 to m4 are the number of states needed for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch first instruction of interrupt service routine
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 85 of 448 rej09b0394-0200 fde mee mme ee fd f 3 1 3 interrupt acceptance irq m1 m2 1 m3 1 5 + m1 + m2 + m3 instruction (instruction replaced by interrupt exception processing) overrun fetch interrupt service routine start instruction legend: f: instruction fetch (instruction fetched from memory where program is stored). d: instruction decoding (fetched instruction is decoded). e: instruction execution (data operation and address calculation is performed according to the results of decoding). m: memory access (data in memory is accessed). figure 6.5 example of th e pipeline operation when an irq interrupt is accepted
6. interrupt controller (intc) rev.2.00 sep. 27, 2007 page 86 of 448 rej09b0394-0200
7. bus state controller (bsc) bsc1000a_010020030200 rev.2.00 sep. 27, 2007 page 87 of 448 rej09b0394-0200 section 7 bus state controller (bsc) the bus state controller (bsc) controls accesse s to the on-chip rom, ram, and peripheral module registers. 7.1 features the bsc has the following features: ? on-chip rom and ram interfaces ? on-chip rom and ram access of 32 bits in 1 state ? accesses to on-chip peripheral module registers 7.2 input/output pin there are no pins corresponding to this function. 7.3 register the bsc has the following register. for details on th ese register addresses and register states in each processing states, refer to s ection 18, list of registers. ? bus control register 1 (bcr1)
7. bus state controller (bsc) rev.2.00 sep. 27, 2007 page 88 of 448 rej09b0394-0200 7.4 address map table 7.1 shows the address map. table 7.1 address map on-chip rom enabled mode address space memory size bus width h'0000 0000 to h'0000 7fff 32 kbytes 32 bits h'0000 8000 to h'0001 ffff reserved 32 bits h'0002 0000 to h'0003 ffff on-chip rom on-chip rom reserved 32 bits h'0004 0000 to h'ffff 7fff reserved reserved reserved h'ffff 8000 to h'ffff bfff on-chip peripheral module on-chip peripheral module 16 kbytes 8, 16 bits h'ffff c000 to h'ffff cfff reserved reserved h'ffff d000 to h'ffff dfff reserved 32 bits h'ffff e000 to h'ffff f7ff on-chip ram on-chip ram reserved 32 bits h'ffff f800 to h'ffff ffff 2 kbytes 32 bits note: reserved area should not be accessed, or operation cannot be guaranteed.
7. bus state controller (bsc) rev.2.00 sep. 27, 2007 page 89 of 448 rej09b0394-0200 7.5 register description 7.5.1 bus control register 1 (bcr1) bcr1 is a 16-bit readable/writable register th at enables access to the mtu control registers. bit bit name initial value r/w description 15 ? 0 r reserved these bits are always read as 0 and should always be written to 0. 14 ? 1 r reserved these bits are always read as 1 and should always be written to 1. 13 mturwe 1 r/w mtu read/write enable this bit enables mtu control register access. for details, refer to mtu section. 0: mtu control register access is disabled 1: mtu control register access is enabled 12 to 8 ? all 0 r reserved these bits are always read as 0 and the write value should always be 0. 7 to 4 ? all 0 r reserved these bits are always read as 0 and the write value should always be 0. 3 to 0 ? all 1 r reserved these bits are always read as 1 and the write value should always be 1.
7. bus state controller (bsc) rev.2.00 sep. 27, 2007 page 90 of 448 rej09b0394-0200 7.6 on-chip peripheral i/o register access on-chip peripheral i/o registers ar e accessed from the bus state controller, as shown in table 7.2. table 7.2 on-chip peripheral i/o register access on-chip peripheral module sci mtu, poe intc pfc, port cmt a/d wdt connected bus width 8 bits 16 bits 16 bits 16 bits 16 bits 8 bits 16 bits access cycle 2 cycles * 1 2 cycles * 1 2 cycles * 2 2 cycles * 2 2 cycles * 1 3 cycles * 1 3 cycles * 2 notes: 1. in terms of the peripheral clock value 2. in terms of the system clock value
8. multi-function timer pulse unit (mtu) timmtu0a_010020030200 rev.2.00 sep. 27, 2007 page 91 of 448 rej09b0394-0200 section 8 multi-functio n timer pulse unit (mtu) this lsi has an on-chip multi-function timer pulse unit (mtu) that comprises five 16-bit timer channels. the block diagram is shown in figure 8.1. 8.1 features ? maximum 16-pulse input/output ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match ? input capture function ? counter clear operation multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture is possible register simultaneous input/output is possible by synchronous counter operation ? a maximum 12-phase pwm output is possible in combination with synchronous operation ? buffer operation settable for channels 0, 3, and 4 ? phase counting mode settable independe ntly for each of channels 1 and 2 ? cascade connection operation ? fast access via internal 16-bit bus ? 23 interrupt sources ? automatic transfer of register data ? a/d converter conversion start trigger can be generated ? module standby mode can be set ? positive and negative 3-phase waveforms (6-phase waveforms in total) can be output in complementary or reset synchronous pwm mode by combining channels 3 and 4. ? ac synchronous motor (brushless dc motor) can be driven in complementary or reset synchronous pwm mode by combining channels 0, 3, and 4. chopping or level output can be selected as drive waveform output.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 92 of 448 rej09b0394-0200 table 8.1 mtu functions item channel 0 channel 1 channel 2 channel 3 channel 4 count clock p /1 p /4 p /16 p /64 tclka tclkb tclkc tclkd p /1 p /4 p /16 p /64 p /256 tclka tclkb p /1 p /4 p /16 p /64 p /1024 tclka tclkb tclkc p /1 p /4 p /16 p /64 p /256 p /1024 tclka tclkb p /1 p /4 p /16 p /64 p /256 p /1024 tclka tclkb general registers tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 tgra_3 tgrb_3 tgra_4 tgrb_4 general registers/ buffer registers tgrc_0 tgrd_0 ? ? tgrc_3 tgrd_3 tgrc_4 tgrd_4 i/o pins tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b tioc3a tioc3b tioc3c tioc3d tioc4a tioc4b tioc4c tioc4d counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output 1 output compare match output toggle output input capture function synchronous operation pwm mode 1 pwm mode 2 ? ? complementary pwm mode ? ? ? reset synchronous pwm mode ? ? ? ac synchronous motor drive mode ? ?
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 93 of 448 rej09b0394-0200 item channel 0 channel 1 channel 2 channel 3 channel 4 phase counting mode ? ? ? buffer operation ? ? a/d converter start trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow 4 sources ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow 5 sources ? compare match or input capture 3a ? compare match or input capture 3b ? compare match or input capture 3c ? compare match or input capture 3d ? overflow 5 sources ? compare match or input capture 4a ? compare match or input capture 4b ? compare match or input capture 4c ? compare match or input capture 4d ? underflow/ overflow legend: : possible ? : not possible
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 94 of 448 rej09b0394-0200 internal data bus a/d converter conversion start signal tcnt tgra tgrb tgrc tgrd tcr tiorh tier tmdr tiorl tsr channel 3 tcnt tgra tgrb tgrc tgrd tmdr tiorl tsr tcr tiorh tier channel 4 tcnts tcdr tcbr tddr toer tocr tgcr bus i/f common tcnt tgra tgrb tmdr tsr tcr tior tier tsyr tstr channel 2 tcnt tgra tgrb tmdr tsr tcr tior tier channel 1 tcnt tgra tgrb tgrc tgrd tmdr tiorl tsr tcr tiorh tier channel 0 control logic module data bus control logic for channel 0 to 2 control logic for channels 3 and 4 legend: tstr: tsyr: tcr: tmdr: tior (h, l): timer start register timer synchro register timer control register timer mode register timer i/o control registers (h, l) tier: tsr: tcnt: tgr (a, b, c, d): timer interrupt enable register timer status register timer counter timer general registers (a, b, c, d) interrupt request signals channel 3: channel 4: tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tgi4c tgi4d tci4v interrupt request signals channel 0: channel 1: channel 2: tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b input/output pins channel 0: channel 1: channel 2: p /1 p /4 p /16 p /64 p /256 p /1024 tclka tclkb tclkc tclkd clock input internal clock: external clock: tioc3a tioc3b tioc3c tioc3d tioc4a tioc4b tioc4c tioc4d input/output pins channel 3: channel 4: figure 8.1 block diagram of mtu
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 95 of 448 rej09b0394-0200 8.2 input/output pins table 8.2 pin configuration channel symbol i/o function all tclka input external clock a input pin (channel 1 phase counting mode a phase input) tclkb input external clock b input pin (channel 1 phase counting mode b phase input) tclkc input external clock c input pin (channel 2 phase counting mode a phase input) tclkd input external clock d input pin (channel 2 phase counting mode b phase input) 0 tioc0a i/o tgra_0 input capture input/output compare output/pwm output pin tioc0b i/o tgrb_0 input capture input/output compare output/pwm output pin tioc0c i/o tgrc_0 input capture input/output compare output/pwm output pin tioc0d i/o tgrd_0 input capture input/output compare output/pwm output pin 1 tioc1a i/o tgra_1 input capture input/output compare output/pwm output pin tioc1b i/o tgrb_1 input capture input/output compare output/pwm output pin 2 tioc2a i/o tgra_2 input capture input/output compare output/pwm output pin tioc2b i/o tgrb_2 input capture input/output compare output/pwm output pin 3 tioc3a i/o tgra_3 input capture input/output compare output/pwm output pin tioc3b i/o tgrb_3 input capture input/output compare output/pwm output pin tioc3c i/o tgrc_3 input capture input/output compare output/pwm output pin tioc3d i/o tgrd_3 input capture input/output compare output/pwm output pin 4 tioc4a i/o tgra_4 input capture input/output compare output/pwm output pin tioc4b i/o tgrb_4 input capture input/output compare output/pwm output pin tioc4c i/o tgrc_4 input capture input/output compare output/pwm output pin tioc4d i/o tgrd_4 input capture input/output compare output/pwm output pin
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 96 of 448 rej09b0394-0200 8.3 register descriptions the mtu has the following registers. for details on register addresses and register states during each process, refer to section 18, list of register s. to distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; tcr for channel 0 is expressed as tcr_0. ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register h_0 (tiorh_0) ? timer i/o control register l_0 (tiorl_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? timer control register_3 (tcr_3)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 97 of 448 rej09b0394-0200 ? timer mode register_3 (tmdr_3) ? timer i/o control register h_3 (tiorh_3) ? timer i/o control register l_3 (tiorl_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? timer control register_4 (tcr_4) ? timer mode register_4 (tmdr_4) ? timer i/o control register h_4 (tiorh_4) ? timer i/o control register l_4 (tiorl_4) ? timer interrupt enable register_4 (tier_4) ? timer status register_4 (tsr_4) ? timer counter_4 (tcnt_4) ? timer general register a_4 (tgra_4) ? timer general register b_4 (tgrb_4) ? timer general register c_4 (tgrc_4) ? timer general register d_4 (tgrd_4) common registers ? timer start register (tstr) ? timer synchro register (tsyr) common registers for timers 3 and 4 ? timer output master enable register (toer) ? timer output control enable register (tocr) ? timer gate control register (tgcr) ? timer cycle data register (tcdr) ? timer dead time data register (tddr) ? timer subcounter (tcnts) ? timer cycle buffer register (tcbr)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 98 of 448 rej09b0394-0200 8.3.1 timer control register (tcr) the tcr registers are 8-bit readable/writable regi sters that control the tcnt operation for each channel. the mtu has a total of five tcr regist ers, one for each channel (channel 0 to 4). tcr register settings should be conducted only when tcnt operation is stopped. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 0 to 2 these bits select the tcnt counter clearing source. see tables 8.3 and 8.4 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 0 and 1 these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. p /4 both edges = /2 rising edge). if phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. internal clock edge selection is valid when the input clock is p /4 or slower. when p /1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: count at rising edge 01: count at falling edge 1x: count at both edges legend: x: don't care 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 0 to 2 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables 8.5 to 8.8 for details.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 99 of 448 rej09b0394-0200 table 8.3 cclr0 to cclr2 (channels 0, 3, and 4) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0, 3, 4 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is set by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. table 8.4 cclr0 to cclr2 (channels 1 and 2) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 1, 2 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is selected by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1 and 2. it is always read as 0. writing is ignored.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 100 of 448 rej09b0394-0200 table 8.5 tpsc0 to tpsc2 (channel 0) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input table 8.6 tpsc0 to tpsc2 (channel 1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on p /256 1 counts on tcnt_2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 101 of 448 rej09b0394-0200 table 8.7 tpsc0 to tpsc2 (channel 2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on p /1024 note: this setting is ignored when channel 2 is in phase counting mode. table 8.8 tpsc0 to tpsc2 (channels 3 and 4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3, 4 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 internal clock: counts on p /256 1 internal clock: counts on p /1024 1 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 102 of 448 rej09b0394-0200 8.3.2 timer mode register (tmdr) the tmdr registers are 8-bit readab le/writable registers that are used to set the operating mode of each channel. the mtu has five tmdr registers, one for each channel. tmdr register settings should be changed only when tcnt operation is stopped. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1, and should only be written with 1. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1 and 2, which have no tgrd, bit 5 is reserved. it is always read as 0, and the write value should always be 0. 0: tgrb and tgrd operate normally 1: tgrb and tgrd used together for buffer operation 4 bfa 0 r/w buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1 and 2, which have no tgrc, bit 4 is reserved. it is always read as 0, and the write value should always be 0. 0: tgra and tgrd operate normally 1: tgra and tgrc used together for buffer operation 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 0 to 3 these bits are used to set the timer operating mode. see table 8.9 for details.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 103 of 448 rej09b0394-0200 table 8.9 md0 to md3 bit 3 md3 bit 2 md2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 1 reserved (do not set) 1 0 pwm mode 1 1 pwm mode 2 * 1 1 0 0 phase counting mode 1 * 2 1 phase counting mode 2 * 2 1 0 phase counting mode 3 * 2 1 phase counting mode 4 * 2 1 0 0 0 reset synchronous pwm mode * 3 1 reserved (do not set) 1 x reserved (do not set) 1 0 0 reserved (do not set) 1 complementary pwm mode 1 (transmit at peak) * 3 1 0 complementary pwm mode 2 (transmit at valley) * 3 1 complementary pwm mode 2 (transmit at peak and valley) * 3 legend: x: don't care notes: 1. pwm mode 2 can not be set for channels 3, 4. 2. phase counting mode can not be set for channels 0, 3, and 4. 3. reset synchronous pwm mode, complementary pwm mode can only be set for channel 3. when channel 3 is set to reset synchronous pwm mode or complementary pwm mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. however, do not set channel 4 to reset synchronous pwm mode or complementary pwm mode. reset synchronous pwm mode and complementary pwm mode can not be set for channels 0, 1, and 2.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 104 of 448 rej09b0394-0200 8.3.3 timer i/o control register (tior) the tior registers are 8-bit read able/writable registers that control the tgr registers. the mtu has eight tior registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. care is required as tior is af fected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. tiorh_0, tior_1, tior_2, tiorh_3, tiorh_4 bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 0 0 0 0 r/w r/w r/w r/w i/o control b0 to b3 specify the function of tgrb. see the following tables. tiorh_0: table 8.10 tior_1: table 8.14 tior_2: table 8.16 tiorh_3: table 8.18 tiorh_4: table 8.22 3 2 1 0 ioa3 ioa2 ioa1 ioa0 0 0 0 0 r/w r/w r/w r/w i/o control a0 to a3 specify the function of tgra. see the following tables. tiorh_0: table 8.11 tior_1: table 8.15 tior_2: table 8.17 tiorh_3: table 8.19 tiorh_4: table 8.23
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 105 of 448 rej09b0394-0200 tiorl_0, tiorl_3, tiorl_4 bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 0 0 0 0 r/w r/w r/w r/w i/o control d0 to d3 specify the function of tgrd. when the tgrd is used as a buffer register of the tgrb, this setting is invalid and input capture/output compare is not generated. see the following tables. tiorl_0: table 8.12 tiorl_3: table 8.20 tiorl_4: table 8.24 3 2 1 0 ioc3 ioc2 ioc1 ioc0 0 0 0 0 r/w r/w r/w r/w i/o control c0 to c3 specify the function of tgrc. when the tgrc is used as a buffer register of the tgra, this setting is invalid and input capture/output compare is not generated. see the following tables. tiorl_0: table 8.13 tiorl_3: table 8.21 tiorl_4: table 8.25
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 106 of 448 rej09b0394-0200 table 8.10 tiorh_0 (channel 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tioc0b pin function 0 output disabled 0 1 initial output is 0 0 output at compare match 0 initial output is 0 1 output at compare match 0 1 1 initial output is 0 toggle output at compare match 0 output disabled 0 1 initial output is 1 0 output at compare match 0 initial output is 1 1 output at compare match 0 1 1 1 output compare register initial output is 1 toggle output at compare match 0 input capture at rising edge 0 1 input capture at falling edge 1 0 1 x input capture register input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count- up/count-down legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 107 of 448 rej09b0394-0200 table 8.11 tiorh_0 (channel 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioc0a pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 108 of 448 rej09b0394-0200 table 8.12 tiorl_0 (channel 0) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tioc0d pin function 0 0 0 0 output disabled 1 initial output is 0 0 output at compare match 1 0 output compare register * initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down legend: x: don't care note: * when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 109 of 448 rej09b0394-0200 table 8.13 tiorl_0 (channel 0) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tioc0c pin function 0 0 0 0 output disable 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt_1 count-up/count-down legend: x: don't care note: * when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 110 of 448 rej09b0394-0200 table 8.14 tior_1 (channel 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tioc1b pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x input capture at generation of tgrc_0 compare match/input capture legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 111 of 448 rej09b0394-0200 table 8.15 tior_1 (channel 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioc1a pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x input capture at generation of channel 0/tgra_0 compare match/input capture legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 112 of 448 rej09b0394-0200 table 8.16 tior_2 (channel 2) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tioc2b pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 113 of 448 rej09b0394-0200 table 8.17 tior_2 (channel 2) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioc2a pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 114 of 448 rej09b0394-0200 table 8.18 tiorh_3 (channel 3) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_3 function tioc3b pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 115 of 448 rej09b0394-0200 table 8.19 tiorh_3 (channel 3) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_3 function tioc3a pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 116 of 448 rej09b0394-0200 table 8.20 tiorl_3 (channel 3) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_3 function tioc3d pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * input capture at both edges legend: x: don't care note: * when the bfb bit in tmdr_3 is set to 1 and tgrd_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 117 of 448 rej09b0394-0200 table 8.21 tiorl_3 (channel 3) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_3 function tioc3c pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * input capture at both edges legend: x: don't care note: * when the bfa bit in tmdr_3 is set to 1 and tgrc_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 118 of 448 rej09b0394-0200 table 8.22 tiorh_4 (channel 4) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_4 function tioc4b pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 119 of 448 rej09b0394-0200 table 8.23 tiorh_4 (channel 4) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_4 function tioc4a pin function 0 0 0 0 output disabled 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 120 of 448 rej09b0394-0200 table 8.24 tiorl_4 (channel 4) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_4 function tioc4b pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care note: * when the bfb bit in tmdr_4 is set to 1 and tgrd_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 121 of 448 rej09b0394-0200 table 8.25 tiorl_4 (channel 4) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_4 function tioc4c pin function 0 0 0 0 output disabled 1 output compare register * initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges legend: x: don't care note: * when the bfa bit in tmdr_4 is set to 1 and tgrc_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 122 of 448 rej09b0394-0200 8.3.4 timer interrupt enable register (tier) the tier registers are 8-bit read able/writable registers that control enabling or disabling of interrupt requests for each channel. the mtu has five tier registers, one for each channel. bit bit name initial value r/w description 7 ttge 0 r/w a/d conversion start request enable enables or disables generation of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 r reserved this bit is always read as 1, and should only be written with 1. 5 tcieu 0 r/w underflow interrupt enable enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1 and 2. in channels 0, 3, and 4, bit 5 is reserved. it is always read as 0, and the write value should always be 0. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled 4 tciev 0 r/w overflow interrupt enable enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled 3 tgied 0 r/w tgr interrupt enable d enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0, 3, and 4. in channels 1 and 2, bit 3 is reserved. it is always read as 0, and the write value should always be 0. 0: interrupt requests (tgid) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 123 of 448 rej09b0394-0200 bit bit name initial value r/w description 2 tgiec 0 r/w tgr interrupt enable c enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0, 3, and 4. in channels 1 and 2, bit 2 is reserved. it is always read as 0, and the write value should always be 0. 0: interrupt requests (tgic) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 124 of 448 rej09b0394-0200 8.3.5 timer status register (tsr) the tsr registers are 8-bit readable /writable registers that indicate the status of each channel. the mtu has five tsr registers, one for each channel. bit bit name initial value r/w description 7 tcfd 1 r count direction flag status flag that shows the direction in which tcnt counts in channels 1, 2, 3, and 4. in channel 0, bit 7 is reserved. it is always read as 1, and should only be written with 1. 0: tcnt counts down 1: tcnt counts up 6 ? 1 r reserved this bit is always read as 1, and should only be written with 1. 5 tcfu 0 r/(w) underflow flag status flag that indicates that tcnt underflow has occurred when channels 1 and 2 are set to phase counting mode. only 0 can be written, for flag clearing. in channels 0, 3, and 4, bit 5 is reserved. it is always read as 0, and the write value should always be 0. [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 4 tcfv 0 r/(w) overflow flag status flag that indicates that tcnt overflow has occurred. only 0 can be written, for flag clearing. [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) in channel 4, when tcnt_4 is underflowed (changes from h'0000 to h'0001) in complementary pwm mode. [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 125 of 448 rej09b0394-0200 bit bit name initial value r/w description 3 tgfd 0 r/(w) input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channels 0, 3, and 4. only 0 can be written, for flag clearing. in channels 1 and 2, bit 3 is reserved. it is always read as 0, and the write value should always be 0. [setting conditions] ? when tcnt = tgrd and tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal and tgrd is functioning as input capture register [clearing condition] ? when 0 is written to tgfd after reading tgfd = 1 2 tgfc 0 r/(w) input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channels 0, 3, and 4. only 0 can be written, for flag clearing. in channels 1 and 2, bit 2 is reserved. it is always read as 0, and the write value should always be 0. [setting conditions] ? when tcnt = tgrc and tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal and tgrc is functioning as input capture register [clearing condition] ? when 0 is written to tgfc after reading tgfc = 1
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 126 of 448 rej09b0394-0200 bit bit name initial value r/w description 1 tgfb 0 r/(w) input capture/output compare flag b status flag that indicates the occurrence of tgrb input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgrb and tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal and tgrb is functioning as input capture register [clearing condition] ? when 0 is written to tgfb after reading tgfb = 1 0 tgfa 0 r/(w) input capture/output compare flag a status flag that indicates the occurrence of tgra input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgra and tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal and tgra is functioning as input capture register [clearing condition] ? when 0 is written to tgfa after reading tgfa = 1 8.3.6 timer counter (tcnt) the tcnt registers are 16-bit r eadable/writable counters. the mtu has five tcnt counters, one for each channel. the initial value is h'0000. the tcnt counters cannot be accessed in 8-bit un its; they must always be accessed as a 16-bit unit.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 127 of 448 rej09b0394-0200 8.3.7 timer general register (tgr) the tgr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture register s. the mtu has 16 tgr registers, four each for channels 0, 3, and 4 and two each for channels 1 and 2. tgrc and tgrd for channels 0, 3, and 4 can also be designated for operation as buffer registers. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. tgr buffer register combinations are tgra- tgrc and tgrb-tgrd. the initial value is h'ffff. 8.3.8 timer start register (tstr) tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bit bit name initial value r/w description 7 6 cst4 cst3 0 0 r/w r/w counter start 4 and 3 these bits select operation or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_4 and tcnt_3 count operation is stopped 1: tcnt_4 and tcnt_3 performs count operation 5 to 3 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits. 2 1 0 cst2 cst1 cst0 0 0 0 r/w r/w r/w counter start 2 to 0 these bits select operation or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_2 and tcnt_0 count operation is stopped 1: tcnt_2 and tcnt_0 performs count operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 128 of 448 rej09b0394-0200 8.3.9 timer synchro register (tsyr) tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. bit bit name initial value r/w description 7 6 sync4 sync3 0 0 r/w r/w timer synchro 4 and 3 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_4 and tcnt_3 operate independently (tcnt presetting/clearing is unrelated to other channels) 1: tcnt_4 and tcnt_3 performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible 5 to 3 ? all 0 r reserved these bits are always read as 0. only 0 should be written to these bits.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 129 of 448 rej09b0394-0200 bit bit name initial value r/w description 2 1 0 sync2 sync1 sync0 0 0 0 r/w r/w r/w timer synchro 2 to 0 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_2 to tcnt_0 operates independently (tcnt presetting /clearing is unrelated to other channels) 1: tcnt_2 to tcnt_0 performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 130 of 448 rej09b0394-0200 8.3.10 timer output master enable register (toer) toer is an 8-bit readable/writable register that enables/disables output settings for output pins tioc4d, tioc4c, tioc3d, tioc4b, tioc4a, and tioc3b. these pins do not output correctly if the toer bits have not been set. set toer of ch3 and ch4 prior to setting tior of ch3 and ch4. bit bit name initial value r/w description 7, 6 ? all 1 r reserved these bits are always read as 1. only 1 should be written to these bits. 5 oe4d 0 r/w master enable tioc4d this bit enables/disables the tioc4d pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 4 oe4c 0 r/w master enable tioc4c this bit enables/disables the tioc4c pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 3 oe3d 0 r/w master enable tioc3d this bit enables/disables the tioc3d pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 2 oe4b 0 r/w master enable tioc4b this bit enables/disables the tioc4b pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 1 oe4a 0 r/w master enable tioc4a this bit enables/disables the tioc4a pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 0 oe3b 0 r/w master enable tioc3b this bit enables/disables the tioc3b pin mtu output. 0: mtu output is disabled 1: mtu output is enabled
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 131 of 448 rej09b0394-0200 8.3.11 timer output control register (tocr) tocr is an 8-bit readable/writable register th at enables/disables pwm synchronized toggle output in complementary pwm mode/reset synchronized pwm mode, and controls output level inversion of pwm output. bit bit name initial value r/w description 7 ? 0 r reserved these bits are always read as 0. only 0 should be written to this bit. 6 psye 0 r/w pwm synchronous output enable this bit selects the enable/disable of toggle output synchronized with the pwm period. 0: toggle output is disabled 1: toggle output is enabled 5 to 2 ? all 0 r reserved these bits are always read as 0. only 0 should be written to this bit. 1 olsn 0 r/w output level select n this bit selects the reverse phase output level in reset- synchronized pwm mode/complementary pwm mode. see table 8.26 0 olsp 0 r/w output level select p this bit selects the positive phase output level in reset- synchronized pwm mode/complementary pwm mode. see table 8.27 table 8.26 output level select function bit 1 function compare match output olsn initial output active level increment count decrement count 0 high level low level high level low level 1 low level high level low level high level note: the reverse phase waveform initial output value changes to active level after elapse of the dead time after count start.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 132 of 448 rej09b0394-0200 table 8.27 output level select function bit 1 function compare match output olsp initial output active level increment count decrement count 0 high level low level low level high level 1 low level high level high level low level figure 8.2 shows an example of complementary pwm mode output (1 phase) when olsn = 1, olsp = 1. tcnt_3, and tcnt_4 values tgra_3 tgra_4 tddr h'0000 time tcnt_4 tcnt_3 positive phase output reverse phase output active level compare match output (up count) initial output initial output active level compare match output (down count) compare match output (down count) compare match output (up count) active level figure 8.2 complementary pwm mode output level example
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 133 of 448 rej09b0394-0200 8.3.12 timer gate control register (tgcr) tgcr is an 8-bit readable/writable register that controls the waveform output necessary for brushless dc motor control in reset-synchronized pwm mode/complementary pwm mode. these register settings are ineffective for anyt hing other than complementary pwm mode/reset- synchronized pwm mode. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 1. only 1 should be written to this bit. 6 bdc 0 r/w brushless dc motor this bit selects whether to make the functions of this register (tgcr) effective or ineffective. 0: ordinary output 1: functions of this register are made effective 5 n 0 r/w reverse phase output (n) control this bit selects whether the level output or the reset- synchronized pwm/complementary pwm output while the reverse pins (tioc3d, tioc4c, and tioc4d) are on-output. 0: level output 1: reset synchronized pwm/complementary pwm output 4 p 0 r/w positive phase output (p) control this bit selects whether the level output or the reset- synchronized pwm/complementary pwm output while the positive pin (tioc3b, tioc4a, and tioc4b) are on- output. 0: level output 1: reset synchronized pwm/complementary pwm output
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 134 of 448 rej09b0394-0200 bit bit name initial value r/w description 3 fb 0 r/w external feedback signal enable this bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the mtu/channel 0 tgra, tgrb, tgrc input capture signals or by writing 0 or 1 to bits 2 to 0 in tgcr. 0: output switching is carried out by external input (input sources are channel 0 tgra, tgrb, tgrc input capture signal) 1: output switching is carried out by software (tgcr's uf, vf, wf settings). 2 1 0 wf vf uf 0 0 0 r/w r/w r/w output phase switch 2 to 0 these bits set the positive phase/negative phase output phase on or off state. the setting of these bits is valid only when the fb bit in this register is set to 1. in this case, the setting of bits 2 to 0 is a substitute for external input. see table 8.28. table 8.28 output level select function function bit 2 bit 1 bit 0 tioc3b tioc4a tioc4b tioc3d tioc4c tioc4d wf vf uf u phase v phase w phase u phase v phase w phase 0 0 0 off off off off off off 1 on off off off off on 1 0 off on off on off off 1 off on off off off on 1 0 0 off off on off on off 1 on off off off on off 1 0 off off on on off off 1 off off off off off off
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 135 of 448 rej09b0394-0200 8.3.13 timer subcounter (tcnts) tcnts is a 16-bit read-only counter that is us ed only in complementary pwm mode. the initial value is h'0000. note: accessing the tcnts in 8- bit units is prohibited. always access in 16-bit units. 8.3.14 timer dead time data register (tddr) tddr is a 16-bit register, used only in complementary pwm mode, that specifies the tcnt_3 and tcnt_4 counter offset values. in complementary pwm mode, when the tcnt_3 and tcnt_4 counters are cleared and then restarted, the tddr register value is loaded into the tcnt_3 counter and the count operation starts. the initial value is h'ffff. note: accessing the tddr in 8- bit units is prohibited. always access in 16-bit units. 8.3.15 timer period data register (tcdr) tcdr is a 16-bit register used only in complementary pwm mode. set half the pwm carrier sync value as the tcdr register value. this register is constantly compared with the tcnts counter in complementary pwm mode, and when a match occurs, the tcnts counter switches direction (decrement to increment). the initial value is h'ffff. note: accessing the tcdr in 8- bit units is prohibited. always access in 16-bit units. 8.3.16 timer period buffer register (tcbr) the timer period buffer register (tcbr) is a 16-bit register used only in complementary pwm mode. it functions as a buffer register for the tcdr register. the tcbr register values are transferred to the tcdr register with the transfer timing set in the tmdr register. the initial value is h'ffff. note: accessing the tcbr in 8- bit units is prohibited. always access in 16-bit units.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 136 of 448 rej09b0394-0200 8.3.17 bus master interface the timer counters (tcnt), general registers (tgr), timer subcounter (tcnts), timer period buffer register (tcbr), and timer dead time data register (tddr), and timer period data register (tcdr) are 16-bit registers. a 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. always access in 16-bit units. all registers other than the above registers are 8- bit registers. these ar e connected to the cpu by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 137 of 448 rej09b0394-0200 8.4 operation 8.4.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. always set the mtu external pins function using the pin function controller (pfc). counter operation when one of bits cst0 to cst4 is set to 1 in tstr, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. example of count operati on setting procedure: figure 8.3 shows an example of the count operation setting procedure. operation selection select counter clock periodic counter select counter clearing source select output compare register set period free-running counter start count operation start count operation [1] [2] [3] [4] [5] [5] [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. [2] for periodic counter operation, select the tgr to be used as the tcnt clearing source with bits cclr2 to cclr0 in tcr. [3] designate the tgr selected in [2] as an output compare register by means of tior. [4] set the periodic counter cycle in the tgr selected in [2]. [5] set the cst bit in tstr to 1 to start the counter operation. figure 8.3 example of counter operation setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 138 of 448 rej09b0394-0200 free-running count operation a nd periodic count operation: immediately after a reset, the mtu's tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up-count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the mtu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 8.4 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 8.4 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, a nd counter clearing by compare match is selected by means of bits cclr0 to cclr2 in tcr. after the settings have been made, tcnt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 139 of 448 rej09b0394-0200 figure 8.5 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software figure 8.5 period ic counter operation waveform output by compare match the mtu can perform 0, 1, or toggle output from the corresponding output pin using compare match. example of setting procedure for waveform output by compare match: figure 8.6 shows an example of the setting procedure for waveform output by compare match. output selection select waveform output mode set output timing start count operation [1] [2] [3] [1] select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of tior. the set initial value is output at the tioc pin until the first compare match occurs. [2] set the timing for compare match generation in tgr. [3] set the cst bit in tstr to 1 to start the count operation. figure 8.6 example of setting procedure for waveform output by compare match
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 140 of 448 rej09b0394-0200 examples of waveform output operation: figure 8.7 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and se ttings have been made such that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 8.7 example of 0 output/1 output operation figure 8.8 shows an example of toggle output. in this example, tcnt has been designated as a periodic counter (with counter clearing on compare match b), and settings have been made su ch that the output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 8.8 example of toggle output operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 141 of 448 rej09b0394-0200 input capture function the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be select ed as the detected edge. for channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. note: when another channel's counter input clock is used as the input capture input for channels 0 and 1, /1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if /1 is selected. example of input capture operation setting procedure: figure 8.9 shows an example of the input capture operation setting procedure. input selection select input capture input start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] set the cst bit in tstr to 1 to start the count operation. figure 8.9 example of input capture operation setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 142 of 448 rej09b0394-0200 example of input capture operation: figure 8.10 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, the falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb time figure 8.10 example of input capture operation 8.4.2 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 4 can all be designated for synchronous operation.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 143 of 448 rej09b0394-0200 example of synchronous operation setting procedure: figure 8.11 shows an example of the synchronous operation setting procedure. no yes set synchronous operation clearing source generation channel? select counter clearing source start count set synchronous counter clearing start count [1] [3] [5] [4] [5] [2] synchronous operation selection [1] set to 1 the sync bits in tsyr corresponding to the channels to be designated for synchronous operation. [2] when the tcnt counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other tcnt counters. [3] use bits cclr2 to cclr0 in tcr to specify tcnt clearing by input capture/output compare, etc. [4] use bits cclr2 to cclr0 in tcr to designate synchronous clearing for the counter clearing source. [5] set to 1 the cst bits in tstr for the relevant channels, to start the count operation. set tcnt synchronous presetting synchronous clearing figure 8.11 example of synchronous operation setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 144 of 448 rej09b0394-0200 example of synchronous operation: figure 8.12 shows an example of synchronous operation. in this example, synchronous operation and pwm m ode 1 have been designated for channels 0 to 2, tgrb_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchronous clearing by tgrb_0 compare match, are performed for channel 0 to 2 tcnt counters, and the data set in tgrb_0 is used as the pwm cycle. for details of pwm modes, see section 8.4.5, pwm modes. tcnt_0 to tcnt_2 values h'0000 tioca_0 tioca_1 tgrb_0 synchronous clearing by tgrb_0 compare match tgra_2 tgra_1 tgrb_2 tgra_0 tgrb_1 tioca_2 time figure 8.12 example of synchronous operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 145 of 448 rej09b0394-0200 8.4.3 buffer operation buffer operation, provided for channels 0, 3, and 4, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 8.29 shows the register combinations used in buffer operation. table 8.29 register combinat ions in buffer operation channel timer general re gister buffer register 0 tgra_0 tgrc_0 tgrb_0 tgrd_0 3 tgra_3 tgrc_3 tgrb_3 tgrd_3 4 tgra_4 tgrc_4 tgrb_4 tgrd_4 ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 8.13. buffer register timer general register tcnt comparator compare match signal figure 8.13 compare match buffer operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 146 of 448 rej09b0394-0200 ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 8.14. buffer register timer general register tcnt input capture signal figure 8.14 input capture buffer operation example of buffer operati on setting procedure: figure 8.15 shows an example of the buffer operation setting procedure. buffer operation select tgr function set buffer operation start count [1] [2] [3] [1] designate tgr as an input capture register or output compare register by means of tior. [2] designate tgr for buffer operation with bits bfa and bfb in tmdr. [3] set the cst bit in tstr to 1 start the count operation. figure 8.15 example of buffer operation setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 147 of 448 rej09b0394-0200 examples of bu ffer operation: ? when tgr is an output compare register figure 8.16 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been desi gnated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been se t, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each tim e that compare match a occurs. for details of pwm modes, see section 8.4.5, pwm modes. tcnt value tgrb_0 h'0000 tgrc_0 tgra_0 h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgra_0 h'0450 h'0200 transfer time figure 8.16 example of buffer operation (1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 148 of 448 rej09b0394-0200 ? when tgr is an input capture register figure 8.17 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon the occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 8.17 example of buffer operation (2)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 149 of 448 rej09b0394-0200 8.4.4 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 counter clock upon overflow/underflow of tcnt_2 as set in bits tp sc0 to tpsc2 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 8.30 shows the register combinations used in cascaded operation. table 8.30 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt_1 tcnt_2 note: when phase counting mode is set for channel 1 or 2, the counter clock setting is invalid and the counters operates independently in phase counting mode. example of cascaded operation setting procedure: figure 8.18 shows an example of the setting procedure for cascaded operation. cascaded operation set cascading start count [1] [2] [1] set bits tpsc2 to tpsc0 in the channel 1 tcr to b'111 to select tcnt_2 overflow/ underflow counting. [2] set the cst bit in tstr for the upper and lower channel to 1 to start the count operation. figure 8.18 cascaded operation setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 150 of 448 rej09b0394-0200 examples of cascaded operation: figure 8.19 illustrates the operation when tcnt_2 overflow/underflow counting has been set for tcnt_1 and phase counting mode has been designated for channel 2. tcnt_1 is incremented by tcnt_2 overflow and decremented by tcnt_2 underflow. tclkc tcnt_2 fffd tcnt_1 0001 tclkd fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 8.19 example of cascaded operation 8.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. the output level can be selected as 0, 1, or toggle output in response to a compare match of each tgr. tgr registers settings can be used to output a pwm waveform in the range of 0 % to 100 % duty cycle. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pw m mode independently. synchronous operation is also possible. there are two pwm modes, as described below. ? pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa0 to ioa3 and ioc0 to ioc3 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob0 to iob3 and iod0 to iod3 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 151 of 448 rej09b0394-0200 ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty cycle registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchroniza tion register compare match, th e output value of each pin is the initial value set in tior. if the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 8-phase pwm output is possible in combination use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 8.31. table 8.31 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 tgra_0 tioc0a tgrb_0 tioc0a tioc0b tgrc_0 tioc0c 0 tgrd_0 tioc0c tioc0d tgra_1 tioc1a 1 tgrb_1 tioc1a tioc1b tgra_2 tioc2a 2 tgrb_2 tioc2a tioc2b tgra_3 cannot be set tgrb_3 tioc3a cannot be set tgrc_3 cannot be set 3 tgrd_3 tioc3c cannot be set tgra_4 cannot be set tgrb_4 tioc4a cannot be set 4 tgrc_4 tioc4c cannot be set tgrd_4 cannot be set note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 152 of 448 rej09b0394-0200 example of pwm mode setting procedure: figure 8.20 shows an example of the pwm mode setting procedure. pwm mode select counter clock select counter clearing source select waveform output level set tgr set pwm mode start count [1] [2] [3] [4] [5] [6] [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr2 to cclr0 in tcr to select the tgr to be used as the tcnt clearing source. [3] use tior to designate the tgr as an output compare register, and select the initial value and output value. [4] set the cycle in the tgr selected in [2], and set the duty in the other tgr. [5] select the pwm mode with bits md3 to md0 in tmdr. [6] set the cst bit in tstr to 1 to start the count operation. figure 8.20 example of pwm mode setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 153 of 448 rej09b0394-0200 examples of pwm mode operation: figure 8.21 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in the tgrb registers are used as the duty cycle. tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 8.21 example of pwm mode operation (1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 154 of 448 rej09b0394-0200 figure 8.22 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgrb_1 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_0 to tgrd_0, tgra_1), outputting a 5-phase pwm waveform. in this case, the value set in tgrb_1 is used as th e cycle, and the values set in the other tgrs are used as the duty cycle levels. tcnt value tgrb_1 h'0000 tioc0a counter cleared by tgrb_1 compare match time tgra_1 tgrd_0 tgrc_0 tgrb_0 tgra_0 tioc0b tioc0c tioc0d tioc1a figure 8.22 example of pwm mode operation (2)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 155 of 448 rej09b0394-0200 figure 8.23 shows examples of pwm waveform output with 0 % duty cycle and 100 % duty cycle in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0 % duty cycle tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100 % duty cycle tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100 % duty cycle tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0 % duty cycle figure 8.23 example of pwm mode operation (3)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 156 of 448 rej09b0394-0200 8.4.6 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt counts up or down accordingly. this mode can be set for channels 1 and 2. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc0 to tpsc2 and bits ckeg0 and ckeg1 in tcr. however, the functions of bits cclr0 and cclr1 in tcr, and of tior, tier, and tgr, are valid, and input capture/compare match and interrupt functions can be used. this can be used for two-phase encoder pulse input. if overflow occurs when tcnt is counting up, the tcfv flag in tsr is set; if underflow occurs when tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag reveals whether tcnt is counting up or down. table 8.32 shows the correspondence betw een external clock pins and channels. table 8.32 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 is set to phase counting mode tclka tclkb when channel 2 is set to phase counting mode tclkc tclkd
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 157 of 448 rej09b0394-0200 example of phase counting mode setting procedure: figure 8.24 shows an example of the phase counting mode setting procedure. phase counting mode select phase counting mode start count [1] [2] [1] select phase counting mode with bits md3 to md0 in tmdr. [2] set the cst bit in tstr to 1 to start the count operation. figure 8.24 example of phase counting mode setting procedure examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between tw o external clocks. there are four modes, according to the count conditions. ? phase counting mode 1 figure 8.25 shows an example of phase counting mode 1 operation, and table 8.33 summarizes the tcnt up/down-count conditions. tcnt value time tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) up-count down-count figure 8.25 example of phase counting mode 1 operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 158 of 448 rej09b0394-0200 table 8.33 up/down-count conditions in phase counting mode 1 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level high level high level down-count low level high level low level legend: : rising edge : falling edge ? phase counting mode 2 figure 8.26 shows an example of phase counting mode 2 operation, and table 8.34 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 8.26 example of phase counting mode 2 operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 159 of 448 rej09b0394-0200 table 8.34 up/down-count conditions in phase counting mode 2 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level low level low level don't care high level up-count high level low level high level don't care low level down-count legend: : rising edge : falling edge ? phase counting mode 3 figure 8.27 shows an example of phase counting mode 3 operation, and table 8.35 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 8.27 example of phase counting mode 3 operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 160 of 448 rej09b0394-0200 table 8.35 up/down-count conditions in phase counting mode 3 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level low level low level don't care high level up-count high level down-count low level don't care high level low level legend: : rising edge : falling edge ? phase counting mode 4 figure 8.28 shows an example of phase counting mode 4 operation, and table 8.36 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 8.28 example of phase counting mode 4 operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 161 of 448 rej09b0394-0200 table 8.36 up/down-count conditions in phase counting mode 4 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level don't care high level high level down-count low level high level don't care low level legend: : rising edge : falling edge phase counting mode application example: figure 8.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coup led with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgrc_0 compare match; tgra_0 and tgrc_0 are used for the compare match function a nd are set with the speed control period and position control period. tgrb_0 is used for input capture, with tgrb_0 and tgrd_0 operating in buffer mode. the channel 1 counter input clock is designated as the tgrb_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. tgra_1 and tgrb_1 for channel 1 are designated for input capture, and channel 0 tgra_0 and tgrc_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. this procedure enables the accurate detection of position and speed.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 162 of 448 rej09b0394-0200 tcnt_1 tcnt_0 channel 1 tgra_1 (speed period capture) tgra_0 (speed control period) tgrb_1 (position period capture) tgrc_0 (position control period) tgrb_0 (pulse width capture) tgrd_0 (buffer operation) channel 0 tclka tclkb edge detection circuit + - + - figure 8.29 phase counting mode application example
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 163 of 448 rej09b0394-0200 8.4.7 reset-synchronized pwm mode in the reset-synchronized pwm mode, three-phase output of positive and negative pwm waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. when set for reset-synchronized pwm mode, the tioc3b, tioc3d, tioc4a, tioc4c, tioc4b, and tioc4d pins function as pwm output pins and tcnt3 functions as an upcounter. table 8.37 shows the pwm output pins used. table 8.38 shows the settings of the registers. table 8.37 output pins for reset-synchronized pwm mode channel output pin description 3 tioc3b pwm output pin 1 tioc3d pwm output pin 1' (negative-phase waveform of pwm output 1) 4 tioc4a pwm output pin 2 tioc4c pwm output pin 2' (negative-phase waveform of pwm output 2) tioc4b pwm output pin 3 tioc4d pwm output pin 3' (negative-phase waveform of pwm output 3) table 8.38 register settings fo r reset-synchronized pwm mode register description of setting tcnt_3 initial setting of h'0000 tcnt_4 initial setting of h'0000 tgra_3 set count cycle for tcnt_3 tgrb_3 sets the turning point for pwm waveform output by the tioc3b and tioc3d pins tgra_4 sets the turning point for pwm waveform output by the tioc4a and tioc4c pins tgrb_4 sets the turning point for pwm waveform output by the tioc4b and tioc4d pins
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 164 of 448 rej09b0394-0200 procedure for selecting the reset-synchronized pwm mode: figure 8.30 shows an example of procedure for selecting the reset synchronized pwm mode. 1. clear the cst3 and cst4 bits in the tstr to 0 to halt the counting of tcnt. the reset- synchronized pwm mode must be set up while tcnt_3 and tcnt_4 are halted. 2. set bits tpsc2 to tpsc0 and ckeg1 and ckeg0 in the tcr_3 to select the counter clock and clock edge for channel 3. set bits cclr2 to cclr0 in the tcr_3 to select tgra compare-match as a counter clear source. 3. when performing brushless dc motor control, set bit bdc in the timer gate control register (tgcr) and set the feedback signal input source and output chopping or gate signal direct output. 4. reset tcnt_3 and tcnt_4 to h'0000. 5. tgra_3 is the period register. set the waveform period value in tgra_3. set the transition timing of the pwm output waveforms in tgrb_3, tgra_4, and tgrb_4. set times within the compare-match range of tcnt_3. x tgra_3 (x: set value). 6. select enabling/disabling of toggle output synchronized with the pmw cycle using bit psye in the timer output control register (tocr), and set the pwm output level with bits olsp and olsn. 7. set bits md3 to md0 in tmdr_3 to b'1000 to select the reset-synchronized pwm mode. tioc3a, tioc3b, tioc3d, tioc4a, tioc4b, tioc4c and tioc4d function as pwm output pins*. do not set to tmdr_4. 8. set the enabling/disabling of the pwm waveform output pin in toer. 9. set the cst3 bit in the tstr to 1 to start the count operation. notes: the output waveform starts to toggle operation at the point of tcnt_3 = tgra_3 = x by setting x = tgra, i.e., cycle = duty cycle. * pfc registers should be specified before this procedure.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 165 of 448 rej09b0394-0200 7 1 2 3 4 stop counting select counter clock and counter clear source set tgr reset-synchronized pwm mode brushless dc motor control setting set tcnt 5 enable waveform output set reset-synchronized pwm mode 6 pwm cycle output enabling, pwm output level setting 8 start count operation 9 reset-synchronized pwm mode figure 8.30 procedure for selectin g the reset-synchronized pwm mode
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 166 of 448 rej09b0394-0200 reset-synchronized pw m mode operation: figure 8.31 shows an example of operation in the reset-synchronized pwm mode. tcnt_3 and tcnt_4 operate as upcounters. the counter is cleared when a tcnt_3 and tgra_3 compare-match occurs, and then begins counting up from h'0000. the pwm output pin output toggles with each oc currence of a tgrb_3, tgra_4, tgrb_4 compare-match, and upon counter clears. tgra_3 tgrb_3 tgrb_4 h'0000 tgra_4 tioc3b tioc3d tioc4a tioc4c tioc4b tioc4d time tcnt_3 and tcnt_4 values figure 8.31 reset-syn chronized pwm mode operation example (when the tocr's olsn = 1 and olsp = 1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 167 of 448 rej09b0394-0200 8.4.8 complementary pwm mode in the complementary pwm mode, three-phase output of non-overlapping positive and negative pwm waveforms can be obtained by combining channels 3 and 4. in complementary pwm mode, tioc3b, tioc3d, tioc4a, tioc4b, tioc4c, and tioc4d pins function as pwm output pins, the tioc3a pin can be set for toggle output synchronized with the pwm period. tcnt_3 and tcnt_4 func tion as increment/d ecrement counters. table 8.39 shows the pwm output pins used. table 8.40 shows the settings of the registers used. a function to directly cut off the pwm output by using an external signal is supported as a port function. table 8.39 output pins for complementary pwm mode channel output pin description 3 tioc3a toggle output synchronized with pwm period (or i/o port) tioc3b pwm output pin 1 tioc3c i/o port * tioc3d pwm output pin 1' (non-overlapping negative-phase waveform of pwm output 1) 4 tioc4a pwm output pin 2 tioc4c pwm output pin 2' (non-overlapping negative-phase waveform of pwm output 2) tioc4b pwm output pin 3 tioc4d pwm output pin 3' (non-overlapping negative-phase waveform of pwm output 3) note: * avoid setting the tioc3c pin as a timer i/o pin in the complementary pwm mode.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 168 of 448 rej09b0394-0200 table 8.40 register settings for complementary pwm mode channel counter/register description read/write from cpu 3 tcnt_3 start of up-count from value set in dead time register maskable by bsc/bcr1 setting * tgra_3 set tcnt_3 upper limit value (1/2 carrier cycle + dead time) maskable by bsc/bcr1 setting * tgrb_3 pwm output 1 compare register maskable by bsc/bcr1 setting * tgrc_3 tgra_3 buffer register always readable/writable tgrd_3 pwm output 1/tgrb_3 buffer register always readable/writable 4 tcnt_4 up-count start, initialized to h'0000 maskable by bsc/bcr1 setting * tgra_4 pwm output 2 compare register maskable by bsc/bcr1 setting * tgrb_4 pwm output 3 compare register maskable by bsc/bcr1 setting * tgrc_4 pwm output 2/tgra_4 buffer register always readable/writable tgrd_4 pwm output 3/tgrb_4 buffer register always readable/writable timer dead time data register (tddr) set tcnt_4 and tcnt_3 offset value (dead time value) maskable by bsc/bcr1 setting * timer cycle data register (tcdr) set tcnt_4 upper limit value (1/2 carrier cycle) maskable by bsc/bcr1 setting * timer cycle buffer register (tcbr) tcdr buffer register always readable/writable subcounter (tcnts) subcounter for dead time generation read-only temporary register 1 (temp1) pwm output 1/tgrb_3 temporary register not readable/writable temporary register 2 (temp2) pwm output 2/tgra_4 temporary register not readable/writable temporary register 3 (temp3) pwm output 3/tgrb_4 temporary register not readable/writable note: * access can be enabled or disabled according to the setting of bit 13 (mturwe) in bsc/bcr1 (bus controller/bus control register 1).
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 169 of 448 rej09b0394-0200 tgrc_3 tddr tcnt_3 tgrd_3 tgrd_4 tgrc_4 tgrb_3 temp 1 tgra_4 temp 2 tgrb_4 temp 3 tcnts tcnt_4 tgra_3 tcdr tcbr comparator comparator match signal match signal output controller output protection circuit pwm cycle output pwm output 1 pwm output 2 pwm output 3 pwm output 4 pwm output 5 pwm output 6 poe0 poe1 poe2 poe3 external cutoff input external cutoff interrupt : registers that can always be read or written from the cpu : registers that cannot be read or written from the cpu (except for tcnts, which can only be read) : registers that can be read or written from the cpu (but for which access disabling can be set by the bus controller) tgra_3 compare- match interrupt tcnt_4 underflow interrupt figure 8.32 block diagram of channels 3 and 4 in complementary pwm mode
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 170 of 448 rej09b0394-0200 example of complementary pwm mode setting procedure: an example of the complementary pwm mode setting procedure is shown in figure 8.33. 1. clear bits cst3 and cst4 in the timer start register (tstr) to 0, and halt timer counter (tcnt) operation. perform complementary pwm mode setting when tcnt_3 and tcnt_4 are stopped. 2. set the same counter clock and clock edge for channels 3 and 4 with bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in the timer control regi ster (tcr). use bits cclr2 to cclr0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary pwm mode operation. 3. when performing brushless dc motor control, set bit bdc in the timer gate control register (tgcr) and set the feedback signal input source and output chopping or gate signal direct output. 4. set the dead time in tcnt_3. set tcnt_4 to h'0000. 5. set only when restarting by a synchronous clear from another channel during complementary pwm mode operation. in this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (tsyr). 6. set the output pwm duty cycle in the duty cycle registers (tgrb_3, tgra_4, tgrb_4) and buffer registers (tgrd_3, tgrc_4, tgrd_4). set the same initial value in each corresponding tgr. 7. set the dead time in the dead time register (tddr), 1/2 th e carrier cycle in the carrier cycle data register (tcdr) and carrier cycle buffer register (tcbr), and 1/2 the carrier cycle plus the dead time in tgra_3 and tgrc_3. 8. select enabling/disabling of toggle output synchronized with the pwm cycle using bit psye in the timer output control register (tocr), and set the pwm output level with bits olsp and olsn. 9. select complementary pwm mode in timer mode register 3 (tmdr_3). pins tioc3a, tioc3b, tioc3d, tioc4a, tioc4b, tioc4c, and tioc4d function as output pins*. do not set in tmdr_4. 10. set enabling/disabling of pwm waveform output pin output in the timer output master enable register (toer). 11. set bits cst3 and cst4 in tstr to 1 simultaneously to start the count operation. note: * pfc registers should be specified before this procedure.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 171 of 448 rej09b0394-0200 complementary pwm mode stop count operation counter clock, counter clear source selection brushless dc motor control setting tcnt setting inter-channel synchronization setting tgr setting dead time, carrier cycle setting pwm cycle output enabling, pwm output level setting complementary pwm mode setting 3 enable waveform output start count operation 2 4 5 6 7 8 9 10 11 1 figure 8.33 example of complementary pwm mode setting procedure
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 172 of 448 rej09b0394-0200 outline of complementary pwm mode operation in complementary pwm mode, 6-phase pwm output is possible. figure 8.34 illustrates counter operation in complementary pwm mode, and figure 8.35 shows an example of complementary pwm mode operation. counter operation: in complementary pwm mode, three counters ? tcnt_3, tcnt_4, and tcnts ? perform up/down-count operations. tcnt_3 is automatically initialized to the value set in tddr when complementary pwm mode is selected and the cst bit in tstr is 0. when the cst bit is set to 1, tcnt_3 counts up to the value set in tgra_3, then switches to down-counting when it matches tgra_3. when the tcnt_3 value matches tddr, the counter switches to up-counting, and the operation is repeated in this way. tcnt_4 is initialized to h'0000. when the cst bit is set to 1, tcnt_4 counts up in synchronization with tcnt_3, and switches to down-counting when it matches tcdr. on r eaching h'0000, tcnt_4 switches to up-counting, and the operation is repeated in this way. tcnts is a read-only counter. it need not be initialized. when tcnt_3 matches tcdr during tcnt_3 and tcnt_4 up/down-counting, down-counting is started, and when tcnts matches tcdr, the operation switches to up-counting. when tcnts matches tgra_3, it is cleared to h'0000. when tcnt_4 matches tddr during tcnt_3 and tcnt_4 down-counting, up-counting is started, and when tcnts matches tddr, the operation switches to down-counting. when tcnts reaches h'0000, it is set with the value in tgra_3. tcnts is compared with the compare register and temporar y register in which the pwm duty cycle is set during the count operation only.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 173 of 448 rej09b0394-0200 counter value tgra_3 tcdr tddr h'0000 tcnt_4 tcnts tcnt_3 tcnt_3 tcnt_4 tcnts time figure 8.34 complementary pwm mode counter operation register operation: in complementary pwm mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. figure 8.35 shows an example of complementary pwm mode operation. the registers which are constantly compared with the counters to perform pwm output are tgrb_3, tgra_4, and tgrb_4. when these registers match the counter, the value set in bits olsn and olsp in the timer output control register (tocr) is output. the buffer registers for these compare re gisters are tgrd_3, tgrc_4, and tgrd_4. between a buffer register and compare register there is a temporary register. the temporary registers cannot be accessed by the cpu. data in a compare register is changed by writing the new data to the corresponding buffer register. the buffer registers can be read or written at any time. the data written to a buffer register is constantly transferred to the temporary register in the ta interval. data is not transferred to the temporary register in the tb interval. data written to a buffer register in this interval is transferred to the temporary register at the end of the tb interval. the value transferred to a temporary register is transferred to the compar e register when tcnts for which the tb interval ends matches tgra_3 when counting up, or h'0000 when counting down. the timing for transfer from the temporary regi ster to the compare regi ster can be selected with bits md3 to md0 in the timer mode register (tmdr). figure 8.35 shows an example in which the mode is selected in which the change is made in the trough.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 174 of 448 rej09b0394-0200 in the tb interval (tb1 in figure 8.35) in which data transfer to the temporary register is not performed, the temporary register has the same f unction as the compare regi ster, and is compared with the counter. in this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. in this interval, the three counters ? tcnt_3, tcnt_4, and tcnts ? and two registers ? compare register and temporary register ? are compared, and pwm output controlled accordingly.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 175 of 448 rej09b0394-0200 tgra_3 tcdr tgra_4 tgrc_4 tddr h'0000 buffer register tgrc_4 temporary register temp2 compare register tgra_4 output waveform output waveform tb2 ta tb1 ta tb2 ta tcnt_3 tcnt_4 tcnts (output waveform is active-low) h'6400 h'0080 h'6400 h'6400 h'0080 h'0080 transfer from temporary register to compare register transfer from temporary register to compare register figure 8.35 example of complementary pwm mode operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 176 of 448 rej09b0394-0200 initialization: in complementary pwm mode, there are six registers that must be initialized. before setting complementary pwm mode with bits md3 to md0 in the timer mode register (tmdr), the following initial register values must be set. tgrc_3 operates as the buffer register for tgra_3, and should be set with 1/2 the pwm carrier cycle + dead time td. the timer cycle buffer register (tcbr) operates as the buffer register for the timer cycle data register (tcdr), and should be set with 1/2 the pwm carrier cycle. set dead time td in the timer dead time data register (tddr). set the respective initial pwm duty cycle values in buffer registers tgrd_3, tgrc_4, and tgrd_4. the values set in the five buffer registers excl uding tddr are transferred simultaneously to the corresponding compare registers when complementary pwm mode is set. set tcnt_4 to h'0000 before setting complementary pwm mode. table 8.41 registers and counters requiring initialization register/counter set value tgrc_3 1/2 pwm carrier cycle + dead time td tddr dead time td tcbr 1/2 pwm carrier cycle tgrd_3, tgrc_4, tgrd_4 initial pwm duty cycle value for each phase tcnt_4 h'0000 note: the tgrc_3 set value must be the sum of 1/2 the pwm carrier cycle set in tcbr and dead time td set in tddr. pwm output level setting: in complementary pwm mode, the pwm pulse output level is set with bits olsn and olsp in the timer output control register (tocr). the output level can be set for each of the three positive phases and three negative phases of 6- phase output. complementary pwm mode should be cleared be fore setting or changing output levels.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 177 of 448 rej09b0394-0200 dead time setting: in complementary pwm mode, pwm pulses are output with a non- overlapping relationship between the positive and ne gative phases. this non-overlap time is called the dead time. the non-overlap time is set in the timer dead time data register (tddr). the value set in tddr is used as the tcnt_3 counter start value, and creates non-overlap between tcnt_3 and tcnt_4. complementary pwm mode should be cleared before changing the contents of tddr. pwm cycle setting: in complementary pwm mode, the pwm pulse cycle is set in two registers ? tgra_3, in which the tcnt_3 upper limit value is set, and tcdr, in which the tcnt_4 upper limit value is set. the settings shoul d be made so as to achieve the following relationship between these two registers: tgra_3 set value = tcdr set value + tddr set value the tgra_3 and tcdr settings are made by setting the values in buffer registers tgrc_3 and tcbr. the values set in tgrc_3 and tcbr are transferred simultaneously to tgra_3 and tcdr in accordance with th e transfer timing selected with b its md3 to md0 in the timer mode register (tmdr). the updated pwm cycle is reflected from the next cy cle when the data update is performed at the crest, and from the current cycle when performed in the trough. figure 8.36 illustrates the operation when the pwm cycle is updated at the crest. see the following section, register data updating, for the method of updating the data in each buffer register.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 178 of 448 rej09b0394-0200 counter value tgrc_3 update tgra_3 update tgra_3 tcnt_3 tcnt_4 time figure 8.36 example of pwm cycle updating register data updating: in complementary pwm mode, the buffer register is used to update the data in a compare register. the update data can be written to the buffer register at any time. there are five pwm duty cycle and carrier cycle registers that have buffer registers and can be updated during operation. there is a temporary register between each of these registers and its buffer register. when subcounter tcnts is not counting, if buffer register data is updated, the temporary register value is also rewritten. transfer is not performed from buffer registers to temporary registers when tcnts is counting; in this case, the value written to a buffer register is transferred after tcnts halts. the temporary register value is transferred to the compare register at the data update timing set with bits md3 to md0 in the timer mode register (tmdr). figure 8.37 shows an example of data updating in complementary pwm mode. this example shows the mode in which data updating is performed at both the counter crest and trough. when rewriting buffer register data, a write to tgrd_4 must be performed at the end of the update. data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to tgrd_4. a write to tgrd_4 must be performed after writing data to the registers to be updated, even when not updating all five regi sters, or when updating the tgrd_4 data . in this case, the data written to tgrd_4 should be the same as the data prior to the write operation.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 179 of 448 rej09b0394-0200 data update timing: counter crest and trough transfer from temporary register to compare register transfer from temporary register to compare register transfer from temporary register to compare register transfer from temporary register to compare register transfer from temporary register to compare register transfer from temporary register to compare register counter value tgra_3 tgrc_4 tgra_4 h'0000 br data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6 temp_r gr time : compare register : buffer register figure 8.37 example of data update in complementary pwm mode
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 180 of 448 rej09b0394-0200 initial output in complementary pwm mode: in complementary pwm mode, the initial output is determined by the setting of bits olsn and olsp in the timer output control register (tocr). this initial output is the pwm pulse non-active level, and is output from when complementary pwm mode is set with the timer mode register (tmdr) until tcnt_4 exceeds the value set in the dead time register (tddr). figure 8.38 shows an example of the initial output in complementary pwm mode. an example of the waveform when the initial pwm duty cycle value is smaller than the tddr value is shown in figure 8.39. timer output control register settings olsn bit: 0 (initial output: high; active level: low) olsp bit: 0 (initial output: high; active level: low) tcnt_3, 4 value tgr4_a tddr tcnt_3 tcnt_4 initial output dead time time active level active level tcnt_3, 4 count start (tstr setting) complementary pwm mode (tmdr setting) positive phase output negative phase output figure 8.38 example of initial output in complementary pwm mode (1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 181 of 448 rej09b0394-0200 timer output control register settings olsn bit: 0 (initial output: high; active level: low) olsp bit: 0 (initial output: high; active level: low) tcnt_3, 4 value tgr_4 tddr tcnt_3 tcnt_4 initial output time active level tcnt_3, 4 count start (tstr setting) complementary pwm mode (tmdr setting) positive phase output negative phase output figure 8.39 example of initial output in complementary pwm mode (2) complementary pwm mode pwm output generation method: in complementary pwm mode, 3-phase output is performed of pwm waveforms with a non-overlap time between the positive and negative phases. this non-ove rlap time is called the dead time. a pwm waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. while tcnts is counting, data register and temporary register values are simultaneously compared to create consecutive pwm pulses from 0 to 100 % . the relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. figures 8.40 to 8.42 show examples of waveform generation in complementary pwm mode.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 182 of 448 rej09b0394-0200 the positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. in the t1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. in the t2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. in normal cases, compare-matches occur in the order a b c d (or c d a' b' ), as shown in figure 8.40. if compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. if compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. if compare-match c occurs first following compare-match a , as shown in figure 8.41, compare- match b is ignored, and the negative phase is turned off by compare-match d . this is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). similarly, in the example in figure 8.42, compare-match a' with the new data in the temporary register occurs before compare-match c , but other compare-matches occurring up to c , which turns off the positive phase, are ignored. as a result, the positive phase is not turned on. thus, in complementary pwm mode, compare-matc hes at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 183 of 448 rej09b0394-0200 t2 period t1 period t1 period ab c a' b' d tgr3a_3 tcdr tddr h'0000 positive phase negative phase figure 8.40 example of complementary pwm mode waveform output (1) t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase negative phase c d a a b b figure 8.41 example of complementary pwm mode waveform output (2)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 184 of 448 rej09b0394-0200 ab c a' b' d t1 period t2 period t1 period tgra_3 tcdr tddr h'0000 positive phase negative phase figure 8.42 example of complementary pwm mode waveform output (3) a b c d a' b' t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase negative phase figure 8.43 example of complementary pwm mode 0 % and 100 % waveform output (1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 185 of 448 rej09b0394-0200 t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase negative phase a c d a b b figure 8.44 example of complementary pwm mode 0 % and 100 % waveform output (2) t2 period t1 period t1 period a b c d tgra_3 tcdr tddr h'0000 positive phase negative phase figure 8.45 example of complementary pwm mode 0 % and 100 % waveform output (3)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 186 of 448 rej09b0394-0200 tgra_3 tcdr tddr h'0000 positive phase negative phase t2 period t1 period t1 period a b c b' d a' figure 8.46 example of complementary pwm mode 0 % and 100 % waveform output (4) cad b t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase negative phase figure 8.47 example of complementary pwm mode 0 % and 100 % waveform output (5)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 187 of 448 rej09b0394-0200 complementary pwm mode 0 % and 100 % duty cycle output: in complementary pwm mode, 0 % and 100 % duty cycles can be output as required. figures 8.43 to 8.47 show output examples. 100 % duty cycle output is performed when the data register value is set to h'0000. the waveform in this case has a positive phase with a 100 % on-state. 0 % duty cycle output is performed when the data register value is set to the same value as tgra_3. the waveform in this case has a positive phase with a 100 % off-state. on and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultane ously, both compare-matches are ignored and the waveform does not change. toggle output synchronized with pwm cycle: in complementary pwm mode, toggle output can be performed in synchronization with the pwm carrier cycle by setting the psye bit to 1 in the timer output control register (tocr). an example of a toggle output waveform is shown in figure 8.48. this output is toggled by a compare-match between tcnt_3 and tgra_3 and a compare-match between tcnt4 and h'0000. the output pin for this toggl e output is the tioc3a pin. the initial output is 1. tgra_3 h'0000 toggle output tioc3a pin tcnt_4 tcnt_3 figure 8.48 example of toggle output waveform synchronized with pwm output
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 188 of 448 rej09b0394-0200 counter clearing by another channel: in complementary pwm mode, by setting a mode for synchronization with another channel by means of the timer synchro register (tsyr), and selecting synchronous clearing with bits cclr2 to cclr0 in the timer control register (tcr), it is possible to have tcnt_3, tcnt_4, and tcnts cleared by another channel. figure 8.49 illustrates the operation. use of this function enables counter clearing and restarting to be performed by means of an external signal. tgra_3 tcdr tddr h'0000 channel 1 input capture a tcnt_1 tcnt_3 tcnt_4 tcnts synchronous counter clearing by channel 1 input capture a figure 8.49 counter clearing sync hronized with another channel example of ac synchronous motor (brushless dc motor) drive waveform output: in complementary pwm mode, a brushless dc motor can easily be controlled using the timer gate control register (tgcr). figures 8.50 to 8.53 show examples of brushless dc motor drive waveforms created using tgcr. when output phase switching for a 3-phase brushless dc motor is performed by means of external signals detected with a hall element, etc., clear the fb bit in tgcr to 0. in this case, the external signals indicating the polarity position are input to channel 0 timer input pins tioc0a, tioc0b,
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 189 of 448 rej09b0394-0200 and tioc0c (set with pfc). when an edge is detected at pin tioc0a, tioc0b, or tioc0c, the output on/off state is switched automatically. when the fb bit is 1, the output on/off state is switched when the uf, vf, or wf bit in tgcr is cleared to 0 or set to 1. the drive waveforms are output from the complementary pwm mode 6-phase output pins. with this 6-phase output, in the case of on output, it is possible to use complementary pwm mode output and perform chopping output by setting the n bit or p bit to 1. when the n bit or p bit is 0, level output is selected. the 6-phase output active level (on output level) can be set with the olsn and olsp bits in the timer output control register (tocr) regardless of the setting of the n and p bits. external input tioc0a pin tioc0b pin tioc0c pin tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 0, p = 0, fb = 0, output active level = high figure 8.50 example of output phase switching by external input (1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 190 of 448 rej09b0394-0200 external input tioc0a pin tioc0b pin tioc0c pin tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 1, p = 1, fb = 0, output active level = high figure 8.51 example of output phase switching by external input (2) tgcr uf bit vf bit wf bit tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 0, p = 0, fb = 1, output active level = high figure 8.52 example of output phase switching by means of uf, vf, wf bit settings (1)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 191 of 448 rej09b0394-0200 tgcr uf bit vf bit wf bit tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 1, p = 1, fb = 1, output active level = high figure 8.53 example of output phase switching by means of uf, vf, wf bit settings (2) a/d conversion start request setting: in complementary pwm mode, an a/d conversion start request can be set using a tgra_3 compare-match or a compare-match on a channel other than channels 3 and 4. when start requests using a tgra_3 compare-match are set, a/d conversion can be started at the center of the pwm pulse. a/d conversion start requests can be set by setting the ttge bit to 1 in the timer interrupt enable register (tier).
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 192 of 448 rej09b0394-0200 complementary pwm mode output protection function complementary pwm mode output has the following protection functions. ? register and counter miswrite prevention function with the exception of the buffer registers, which can be rewritten at any time, access by the cpu can be enabled or disabled for the mode re gisters, control registers, compare registers, and counters used in complementary pwm mode by means of bit 13 in the bus controller's bus control register 1 (bcr1). some registers in ch annels 3 and 4 concerned are listed below: total 21 registers of tcr_3 and tcr_4; tmdr_3 and tmdr_4; tiorh_3 and tiorh_4; tiorl_3 and tiorl_4; tier_3 and tier_4; tcnt_3 and tcnt_4; tgra_3 and tgra_4; tgrb_3 and tgrb_4; toer; tocr; tgcr; tcdr; and tddr. this function enables the cpu to pr event miswriting due to the cpu runaway by disabling cpu access to the mode registers, control registers, and count ers. in access disabled state, an undefined value is read from the registers concerned, and cannot be modified. ? halting of pwm output by external signal the 6-phase pwm output pins can be set automatically to the high-impedance state by inputting specified external signals. there are four external signal input pins. see section 8.9, port output enable (poe), for details. ? halting of pwm output when oscillator is stopped if it is detected that the clock input to this lsi has stopped, the 6-phase pwm output pins automatically go to the high-imp edance state. the pin states ar e not guaranteed when the clock is restarted. for details, see section 4.2, function for detecting oscillator halt. 8.5 interrupt sources 8.5.1 interrupts and priorities there are three kinds of mtu interrupt source; tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by cl earing the status flag to 0. relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. for details, s ee section 6, interrupt controller (intc).
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 193 of 448 rej09b0394-0200 table 8.42 lists the mtu interrupt sources. table 8.42 mtu interrupts channel name interrupt source interrupt flag priority 0 tgi0a tgra_0 input capture/compare match tgfa_0 high tgi0b tgrb_0 input capture/compare match tgfb_0 tgi0c tgrc_0 input capture/compare match tgfc_0 tgi0d tgrd_0 input capture/compare match tgfd_0 tci0v tcnt_0 overflow tcfv_0 1 tgi1a tgra_1 input capture/compare match tgfa_1 tgi1b tgrb_1 input capture/compare match tgfb_1 tci1v tcnt_1 overflow tcfv_1 tci1u tcnt_1 underflow tcfu_1 2 tgi2a tgra_2 input capture/compare match tgfa_2 tgi2b tgrb_2 input capture/compare match tgfb_2 tci2v tcnt_2 overflow tcfv_2 tci2u tcnt_2 underflow tcfu_2 3 tgi3a tgra_3 input capture/compare match tgfa_3 tgi3b tgrb_3 input capture/compare match tgfb_3 tgi3c tgrc_3 input capture/compare match tgfc_3 tgi3d tgrd_3 input capture/compare match tgfd_3 tci3v tcnt_3 overflow tcfv_3 4 tgi4a tgra_4 input capture/compare match tgfa_4 tgi4b tgrb_4 input capture/compare match tgfb_4 tgi4c tgrc_4 input capture/compare match tgfc_4 tgi4d tgrd_4 input capture/compare match tgfd_4 tci4v tcnt_4 overflow tcfv_4 low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 194 of 448 rej09b0394-0200 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt reques t is cleared by clearing the tgf flag to 0. the mtu has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two each for channels 1 and 2. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurren ce of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the mtu has five overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcie u bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underf low on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the mtu has two underflow interrupts, one each for channels 1 and 2. 8.5.2 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match in each channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the mtu conversion start trigger has been selected on the a/d converter at this time, a/d conversion starts. in the mtu, a total of five tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 195 of 448 rej09b0394-0200 8.6 operation timing 8.6.1 input/output timing tcnt count timing: figure 8.54 shows tcnt count timing in internal clock operation, and figure 8.55 shows tcnt count timing in external clock operation (normal mode), and figure 8.56 shows tcnt count timing in external clock operation (phase counting mode). tcnt tcnt input clock internal clock p n-1 n n+1 n+2 falling edge rising edge figure 8.54 count timing in internal clock operation tcnt tcnt input clock external clock p n-1 n n+1 n+2 falling edge rising edge falling edge figure 8.55 count timing in external clock operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 196 of 448 rej09b0394-0200 p external clock tcnt input clock tcnt falling edge falling edge rising edge n-1 n n+1 figure 8.56 count timing in external clock operation (phase counting mode) output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tc nt input clock is generated. figure 8.57 shows output compare output timing (normal mode and pwm mode) and figure 8.58 shows output compare output timing (complementary pwm mode and reset synchronous pwm mode). tgr tcnt tcnt input clock n n n+1 compare match signal tioc pin p figure 8.57 output compare output timing (normal mode/pwm mode)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 197 of 448 rej09b0394-0200 p tcnt input clock tcnt n n+1 tgr compare match signal tioc pin n figure 8.58 output compare output timing (complementary pwm mode/reset synchronous pwm mode) input capture signal timing: figure 8.59 shows input capture signal timing. tcnt input capture input n n+1 n+2 n n+2 tgr input capture signal p figure 8.59 input capture input signal timing
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 198 of 448 rej09b0394-0200 timing for counter clearing by compare match/input capture: figure 8.60 shows the timing when counter clearing on compare match is specified, and figure 8.61 shows the timing when counter clearing on i nput capture is specified. tcnt counter clear signal compare match signal tgr n n h'0000 p figure 8.60 counter clear timing (compare match) tcnt counter clear signal input capture signal tgr n h'0000 n p figure 8.61 counter clear timing (input capture)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 199 of 448 rej09b0394-0200 buffer operation timing: figures 8.62 and 8.63 show the timing in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd n n n nn+1 p figure 8.62 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal tgrc, tgrd n n n n+1 n n n+1 p figure 8.63 buffer operation timing (input capture)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 200 of 448 rej09b0394-0200 8.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 8.64 shows the timing for setting of the tgf flag in tsr on compare match, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n+1 compare match signal tgf flag tgi interrupt p figure 8.64 tgi interrupt timing (compare match)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 201 of 448 rej09b0394-0200 tgf flag setting timing in case of input capture: figure 8.65 shows the timing for setting of the tgf flag in tsr on input capture, and tgi interrupt request signal timing. tgr tcnt input capture signal n n tgf flag tgi interrupt p figure 8.65 tgi interrupt timing (input capture)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 202 of 448 rej09b0394-0200 tcfv flag/tcfu flag setting timing: figure 8.66 shows the timing for setting of the tcfv flag in tsr on overflow, and tciv interrupt request signal timing. figure 8.67 shows the timing for setting of the tcfu flag in tsr on underflow, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt p figure 8.66 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt p figure 8.67 tciu interrupt setting timing
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 203 of 448 rej09b0394-0200 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc is activated, the flag is cleared automatically. figure 8.68 shows the timing for status flag clearing by the cpu. status flag write signal address tsr address interrupt request signal tsr write cycle t1 t2 p figure 8.68 timing for status flag clearing by the cpu
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 204 of 448 rej09b0394-0200 8.7 usage notes 8.7.1 module standby mode setting mtu operation can be disabled or enabled using the module standby register. the initial setting is for mtu operation to be halted. register access is enabled by clearing module standby mode. for details, refer to section 17, power-down modes. 8.7.2 input clock restrictions the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detec tion. the tpu will not operate properly at narrower pulse widths. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 8.69 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 8.69 phase differen ce, overlap, and pulse widt h in phase counting mode
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 205 of 448 rej09b0394-0200 8.7.3 caution on period setting when counter clearing on compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = p (n + 1) where f : counter frequency p : peripheral clock operating frequency n : tgr set value 8.7.4 contention between tcnt write and clear operations if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 8.70 shows the timing in this case. counter clear signal write signal address p tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 8.70 contention between tcnt write and clear operations
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 206 of 448 rej09b0394-0200 8.7.5 contention between tcnt write and increment operations if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 8.71 shows the timing in this case. tcnt input clock write signal address p tcnt address tcnt tcnt write cycle t1 t2 nm tcnt write data figure 8.71 contention between tc nt write and increment operations
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 207 of 448 rej09b0394-0200 8.7.6 contention between tg r write and compare match when a compare match occurs in the t2 state of a tgr write cycle, th e tgr write is executed and the compare match signal is generated. figure 8.72 shows the timing in this case. compare match signal write signal address p tgr address tcnt tgr write cycle t1 t2 nm tgr write data tgr n n + 1 figure 8.72 contention between tgr write and compare match
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 208 of 448 rej09b0394-0200 8.7.7 contention between buffer register write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the data that is transferred to tgr by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write. figures 8.73 and 8.74 show the timing in this case. compare match buffer signal compare match signal write signal address p buffer register address buffer register tgr write cycle t1 t2 m tgr nm buffer register write data figure 8.73 contention betw een buffer register write and compare match (channel 0)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 209 of 448 rej09b0394-0200 p address write signal compare match signal compare match buffer signal tgr write cycle t1 t2 buffer register address n n m buffer register write data buffer register tgr figure 8.74 contention between buff er register write and compare match (channels 3 and 4)
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 210 of 448 rej09b0394-0200 8.7.8 contention between tgr read and input capture if an input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be that in the buffer after input capture transfer. figure 8.75 shows the timing in this case. p address read signal input capture signal tgr read cycle t1 t2 tgr address m m tgr internal data bus x figure 8.75 contention between tgr read and input capture
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 211 of 448 rej09b0394-0200 8.7.9 contention between tgr write and input capture if an input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 8.76 shows the timing in this case. input capture signal write signal address p tcnt tgr write cycle t1 t2 m tgr m tgr address figure 8.76 contention between tgr write and input capture
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 212 of 448 rej09b0394-0200 8.7.10 contention between buffer register write and input capture if an input capture signal is generated in the t2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 8.77 shows the timing in this case. input capture signal write signal address p tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 8.77 contention between bu ffer register write and input capture 8.7.11 tcnt_2 write and overflow/underflo w contention in cascade connection with timer counters tcnt_1 and tcnt_2 in a cascade connection, when a contention occurs during tcnt_1 count (during a tcnt_2 overflow/underflow) in the t2 state of the tcnt_2 write cycle, the write to tcnt_2 is conducted, and the tcnt_1 count signal is disabled. at this point, if there is match with tgra_1 and the tcnt_1 value, a compare signal is issued. furthermore, when the tcnt_1 count clock is selected as the input capture source of channel 0, tgra_0 to d_0 carry out the input capture operati on. in addition, when the compare match/input capture is selected as the input capture source of tgrb_1, tgrb_1 carries out input capture operation. the timing is shown in figure 8.78. for cascade connections, be sure to synchronize settings for channels 1 and 2 when setting tcnt clearing.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 213 of 448 rej09b0394-0200 t1 t2 h'fffe h'ffff n n + 1 h'ffff m m n p qp m disabled tcnt_2 write data tcnt_2 address tcnt write cycle p address write signal tcnt_2 tgr2a_2 to tgr2b_2 ch2 compare- match signal a/b tcnt_1 input clock tcnt_1 tgra_1 ch1 compare- match signal a tgrb_1 ch1 input capture signal b tcnt_0 tgra_0 to tgrd_0 ch0 input capture signal a to d figure 8.78 tcnt_2 write and overflow/und erflow contention with cascade connection
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 214 of 448 rej09b0394-0200 8.7.12 counter value during complementary pwm mode stop when counting operation is stopped with tcnt_3 and tcnt_4 in complementary pwm mode, tcnt_3 has the timer dead time register (tddr) value, and tcnt_4 is set to h'0000. when restarting complementary pwm mode, counting begins automatically from the initialized state. this explanatory diagram is shown in figure 8.79. when counting begins in another operating mode , be sure that tcnt_3 and tcnt_4 are set to the initial values. tgra_3 tcdr tddr h'0000 tcnt_3 tcnt_4 complementary pwm mode operation complementary pwm mode operation counter operation stop complementary pmw restart figure 8.79 counter value during complementary pwm mode stop 8.7.13 buffer operation setting in complementary pwm mode in complementary pwm mode, conduct rewrites by buffer operation for the pwm cycle setting register (tgra_3), timer cycle data register (t cdr), and duty cycle setting registers (tgrb_3, trga_4, and tgrb_4). in complementary pwm mode, channel 3 and channel 4 buffers operate in accordance with bit settings bfa and bfb of tmdr_3. when tmdr_3's bfa bit is set to 1, tgrc_3 functions as a buffer register for tgra_3. at the same time, tgrc_4 functions as the buffer register for trga_4, while the tcbr functions as the tcdr's buffer register.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 215 of 448 rej09b0394-0200 8.7.14 reset sync pwm mode buffer operation and compare match flag when setting buffer operation for reset sync pwm mode, set the bfa and bfb bits of tmdr_4 to 0. the tioc4c pin will be unable to produce its waveform output if the bfa bit of tmdr_4 is set to 1. in reset sync pwm mode, the channel 3 and channe l 4 buffers operate in accordance with the bfa and bfb bit settings of tmdr_3. for example, if the bfa bit of tmdr_3 is set to 1, tgrc_3 functions as the buffer register for tgra_3. at the same time, tgrc_4 functions as the buffer register for trga_4. the tgfc bit and tgfd bit of tsr_3 and tsr_4 are not set when tgrc_3 and tgrd_3 are operating as buffer registers. figure 8.80 shows an example of operations for tgr_3, tgr_4, tioc3, and tioc4, with tmdr_3's bfa and bfb bits set to 1, and tmdr_4's bfa and bfb bits set to 0. tgra_3 tgrc_3 tgrb_3, tgra_4, tgrb_4 tgrd_3, tgrc_4, tgrd_4 h'0000 tioc3a tioc3b tioc3d tioc4a tioc4c tioc4b tioc4d tgfc tgfd tgra_3, tgrc_3 tgrb_3, tgrd_3, tgra_4, tgrc_4, tgrb_4, tgrd_4 buffer transfer with compare match a3 tcnt3 not set not set point a point b figure 8.80 buffer operation and compare-match flags in reset sync pwm mode
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 216 of 448 rej09b0394-0200 8.7.15 overflow flags in reset sync pwm mode when set to reset sync pwm mode, tcnt_3 and tcnt_4 start counting when the cst3 bit of tstr is set to 1. at this point, tcnt_4's count clock source and count edge obey the tcr_3 setting. in reset sync pwm mode, with cycle register tgra_3's set value at h'ffff, when specifying tgr3a compare-match for the counter clear s ource, tcnt_3 and tcnt_4 count up to h'ffff, then a compare-match occurs with tgra_3, and tcnt_3 and tcnt_4 are both cleared. at this point, tsr's overflow flag tcfv bit is not set. figure 8.81 shows a tcfv bit operation example in reset sync pwm mode with a set value for cycle register tgra_3 of h'ffff, when a tgra _3 compare-match has b een specified without synchronous setting for the counter clear source. tgra_3 (h'ffff) h'0000 tcfv_3 tcfv_4 tcnt_3 = tcnt_4 counter cleared by compare match 3a not set not set figure 8.81 reset sync pwm mode overflow flag
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 217 of 448 rej09b0394-0200 8.7.16 contention between overflo w/underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 8.82 shows the operation timing when a tg r compare match is specified as the clearing source, and when h'ffff is set in tgr. counter clear signal tcnt tcnt input clock p h'ffff h'0000 tgf tcfv disabled figure 8.82 contention between overflow and co unter clearing
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 218 of 448 rej09b0394-0200 8.7.17 contention between tcnt write and overf low/underflow if there is an up-count or down-count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/t cfu flag in tsr is not set. figure 8.83 shows the operation timing when there is contention between tcnt write and overflow. write signal address p tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag figure 8.83 contention betw een tcnt write and overflow 8.7.18 cautions on transition from normal operation or pwm mode 1 to reset- synchronous pwm mode when making a transition from channel 3 or 4 normal operation or pwm mode 1 to reset- synchronous pwm mode, if the counter is halted with the output pins (tioc3b, tioc3d, tioc4a, tioc4c, tioc4b, tioc4d) in the high-impedance state, followed by the transition to reset-synchronous pwm mode and operation in that mode, the initial pin output will not be correct. when making a transition from normal operation to reset-synchronous pwm mode, write h'11 to registers tior3_h, tior3_l, tior 4_h, and tior4_l to initialize the output pins to low level output, then set an initial register value of h'00 before making the mode transition. when making a transition from pwm mode 1 to reset-synchronous pwm mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of h'00 before making the transition to reset-synchronous pwm mode.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 219 of 448 rej09b0394-0200 8.7.19 output level in complementary pw m mode and reset-sy nchronous pwm mode when channels 3 and 4 are in complementary pwm mode or reset-synchronous pwm mode, the pwm waveform output level is set with the olsp and olsn bits in the timer output control register (tocr). in the case of complementary pwm mode or reset-synchronous pwm mode, tior should be set to h'00. 8.7.20 interrupts in module standby mode if module standby mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source. interrupts should therefore be disabled before entering module standby mode. 8.7.21 simultaneous input capture of tcnt_1 and tcnt_2 in cascade connection when timer counters 1 and 2 (tcnt_1 and tcnt_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be captured successfully even if input-capture input is simultaneously done to tioc1a and tioc2a or to tioc1b and tioc2b. this is because the input timing of tioc1a and tioc2a or of tioc1b and tioc2b may not be the same when external input-capture signals to be input into tcnt_1 and tcnt_2 are taken in synchronization with the internal clock. for example, tcnt_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from tcnt_2 (the counter for lower 16 bits) but captures the count value before the count-up. in this case, the values of tcnt_1 = h'fff1 and tcnt_2 = h'0000 should be transferred to tgra_1 and tgra_2 or to tgrb_1 and tgrb_2, but the values of tcnt_1 = h'fff0 and tcnt _2 = h'0000 are erroneously transferred.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 220 of 448 rej09b0394-0200 8.8 mtu output pi n initialization 8.8.1 operating modes the mtu has the following six operating modes. waveform output is possible in all of these modes. ? normal mode (channels 0 to 4) ? pwm mode 1 (channels 0 to 4) ? pwm mode 2 (channels 0 to 2) ? phase counting modes 1 to 4 (channels 1 and 2) ? complementary pwm mode (channels 3 and 4) ? reset-synchronous pwm mode (channels 3 and 4) the mtu output pin initialization method for each of these modes is described in this section. 8.8.2 reset start operation the mtu output pins (tioc*) are initialized low by a reset or in standby mode. since mtu pin function selection is performed by the pin function controller (pfc), when the pfc is set, the mtu pin states at that point are output to the ports. when mtu output is selected by the pfc immediately after a reset, the mtu output initial level, low, is output directly at the port. when the active level is low, the syst em will operate at this point, a nd therefore the pfc setting should be made after initialization of the mtu output pins is completed. note: channel number and port notation are substituted for *.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 221 of 448 rej09b0394-0200 8.8.3 operation in case of re-setting due to error duri ng operation, etc. if an error occurs during mtu operation, mtu output should be cut by the system. cutoff is performed by switching the pin output to port output with the pfc and outputting the inverse of the active level. for large-current pins, output can also be cut by hardware, using port output enable (poe). the pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. the mtu has six operating modes, as stated above. there are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. possible mode transition combinations are shown in table 8.43. table 8.43 mode transition combinations after before normal pwm1 pwm2 pcm cpwm rpwm normal (1) (2) (3) (4) (5) (6) pwm1 (7) (8) (9) (10) (11) (12) pwm2 (13) (14) (15) (16) none none pcm (17) (18) (19) (20) none none cpwm (21) (22) none none (23) (24) (25) rpwm (26) (27) none none (28) (29) legend: normal: normal mode pwm1: pwm mode 1 pwm2: pwm mode 2 pcm: phase counting modes 1 to 4 cpwm: complementary pwm mode rpwm: reset-synchronous pwm mode the above abbreviations are used in so me places in following descriptions.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 222 of 448 rej09b0394-0200 8.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ? when making a transition to a mode (normal, pwm1, pwm2, pcm) in which the pin output level is selected by the timer i/o control register (tior) setting, initialize the pins by means of a tior setting. ? in pwm mode 1, since a waveform is not output to the tioc*b (tioc *d) pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 1. ? in pwm mode 2, since a waveform is not output to the cycle register pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 2. ? in normal mode or pwm mode 2, if tgrc and tgrd operate as buffer registers, setting tior will not initialize the buffer register pins. if initialization is required, clear buffer mode, carry out initialization, and then set buffer mode again. ? in pwm mode 1, if either tgrc or tgrd operates as a buffer register, setting tior will not initialize the tgrc pin. to initialize the tgrc pin, clear buffer mode, carry out initialization, then set buffer mode again. ? when making a transition to a mode (cpwm, rpwm) in which the pin output level is selected by the timer output control register (tocr) setting, switch to normal mode and perform initialization with tior, then restore tior to its initial value, and temporarily disable channel 3 and 4 output with the timer output mast er enable register (t oer). then operate the unit in accordance with the mode setting procedure (tocr setting, tmdr setting, toer setting). note: channel number is substituted for * indicated in this article. pin initialization procedures are described below for the numbered combinations in table 8.43. the active level is assumed to be low.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 223 of 448 rej09b0394-0200 (1) operation when error o ccurs during normal mode op eration, and operation is restarted in normal mode: figure 8.84 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc*a tioc*b port output pen pen note: n = 0 to 15 hi-z hi-z figure 8.84 error occurren ce in normal mode, rec overy in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. after a reset, the tmdr setting is for normal mode. 3. for channels 3 and 4, enable output with toer before initializing the pins with tior. 4. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. output goes low on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. 11. not necessary when restarting in normal mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 224 of 448 rej09b0394-0200 (2) operation when error o ccurs during normal mode op eration, and operation is restarted in pwm mode 1: figure 8.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) note: n = 0 to 15 hi-z hi-z figure 8.85 error occurrence in norm al mode, recovery in pwm mode 1 1 to 10 are the same as in figure 8.84. 11. set pwm mode 1. 12. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 1.) 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 225 of 448 rej09b0394-0200 (3) operation when error o ccurs during normal mode op eration, and operation is restarted in pwm mode 2: figure 8.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm2) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (cycle register) note: n = 0 to 15 hi-z hi-z figure 8.86 error occurrence in norm al mode, recovery in pwm mode 2 1 to 10 are the same as in figure 8.84. 11. set pwm mode 2. 12. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 2.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: pwm mode 2 can only be set for channels 0 to 2, and therefore toer setting is not necessary.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 226 of 448 rej09b0394-0200 (4) operation when error o ccurs during normal mode op eration, and operation is restarted in phase counting mode: figure 8.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re- setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pcm) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen note: n = 0 to 15 hi-z hi-z figure 8.87 error occurrence in normal mode, recovery in phase counting mode 1 to 10 are the same as in figure 8.84. 11. set phase counting mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: phase counting mode can only be set for channels 1 and 2, and therefore toer setting is not necessary.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 227 of 448 rej09b0394-0200 (5) operation when error o ccurs during normal mode op eration, and operation is restarted in complementary pwm mode: figure 8.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary pwm mode after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tior (0 init 0 out) 12 tior ( disabled ) 13 toer (0) 14 tocr 15 tmdr (cpwm) (16) toer (1) (17) pfc (mtu) (18) tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.88 error occurrence in normal mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 8.84. 11. initialize the normal mode waveform generation section with tior. 12. disable operation of the normal mode waveform generation section with tior. 13. disable channel 3 and 4 output with toer. 14. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 15. set complementary pwm. 16. enable channel 3 and 4 output with toer. 17. set mtu output with the pfc. 18. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 228 of 448 rej09b0394-0200 (6) operation when error o ccurs during normal mode op eration, and operation is restarted in reset-synchronous pwm mode: figure 8.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous pwm mode after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tior (0 init 0 out) 12 tior ( disabled ) 13 toer (0) 14 tocr 15 tmdr (cpwm) 16 toer (1) 17 pfc (mtu) 18 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.89 error occurren ce in normal mode, recov ery in reset-synchronous pwm mode 1 to 13 are the same as in figure 8.88. 14. select the reset-synchronous pwm output level and cyclic output enabling/disabling with tocr. 15. set reset-synchronous pwm. 16. enable channel 3 and 4 output with toer. 17. set mtu output with the pfc. 18. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 229 of 448 rej09b0394-0200 (7) operation when error o ccurs during pwm mode 1 op eration, and operation is restarted in normal mode: figure 8.90 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) note: n = 0 to 15 hi-z hi-z figure 8.90 error occurren ce in pwm mode 1, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 1. 3. for channels 3 and 4, enable output with toer before initializing the pins with tior. 4. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 1, the tioc*b side is not initialized.) 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. output goes low on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. 11. set normal mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 230 of 448 rej09b0394-0200 (8) operation when error o ccurs during pwm mode 1 op eration, and operation is restarted in pwm mode 1: figure 8.91 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) ? not initialized (tioc * b) note: n = 0 to 15 hi-z hi-z figure 8.91 error occu rrence in pwm mode 1, recovery in pwm mode 1 1 to 10 are the same as in figure 8.90. 11. not necessary when restarting in pwm mode 1. 12. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 231 of 448 rej09b0394-0200 (9) operation when error o ccurs during pwm mode 1 op eration, and operation is restarted in pwm mode 2: figure 8.92 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm2) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) ? not initialized (cycle register) note: n = 0 to 15 hi-z hi-z figure 8.92 error occu rrence in pwm mode 1, recovery in pwm mode 2 1 to 10 are the same as in figure 8.90. 11. set pwm mode 2. 12. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: pwm mode 2 can only be set for channels 0 to 2, and therefore toer setting is not necessary.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 232 of 448 rej09b0394-0200 (10) operation when error occurs during pwm mode 1 op eration, and operation is restarted in phase counting mode: figure 8.93 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in phase counting mode after re- setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pcm) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) note: n = 0 to 15 hi-z hi-z figure 8.93 error occurrence in pwm mode 1, recovery in phase counting mode 1 to 10 are the same as in figure 8.90. 11. set phase counting mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: phase counting mode can only be set for channels 1 and 2, and therefore toer setting is not necessary.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 233 of 448 rej09b0394-0200 (11) operation when error occurs during pwm mode 1 op eration, and operation is restarted in complementary pwm mode: figure 8.94 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in complementary pwm mode after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (0 init 0 out) 13 tior ( disabled ) 14 toer (0) 15 tocr 16 tmdr (cpwm) 17 toer (1) 18 pfc (mtu) 19 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 ? not initialized (tioc3b) ? not initialized (tioc3d) hi-z hi-z hi-z figure 8.94 error occurrence in pwm mode 1, recovery in complementary pwm mode 1 to 10 are the same as in figure 8.90. 11. set normal mode for initialization of the normal mode waveform generation section. 12. initialize the pwm mode 1 waveform generation section with tior. 13. disable operation of the pwm mode 1 waveform generation section with tior. 14. disable channel 3 and 4 output with toer. 15. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 16. set complementary pwm. 17. enable channel 3 and 4 output with toer. 18. set mtu output with the pfc. 19. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 234 of 448 rej09b0394-0200 (12) operation when error occurs during pwm mode 1 op eration, and operation is restarted in reset-synchronous pwm mode: figure 8.95 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in reset-synchronous pwm mode after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (0 init 0 out) 13 tior ( disabled ) 14 toer (0) 15 tocr 16 tmdr (rpwm) 17 toer (1) 18 pfc (mtu) 19 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 ? not initialized (tioc3b) ? not initialized (tioc3d) hi-z hi-z hi-z figure 8.95 error occu rrence in pwm mode 1, recovery in reset-synchronous pwm mode 1 to 14 are the same as in figure 8.90. 15. select the reset-synchronous pwm output level and cyclic output enabling/disabling with tocr. 16. set reset-synchronous pwm. 17. enable channel 3 and 4 output with toer. 18. set mtu output with the pfc. 19. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 235 of 448 rej09b0394-0200 (13) operation when error occurs during pwm mode 2 op eration, and operation is restarted in normal mode: figure 8.96 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (cycle register) note: n = 0 to 15 hi-z hi-z figure 8.96 error occurren ce in pwm mode 2, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 2. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 2, the cycle register pins are not initialized. in the example, tioc *a is the cycle register.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 236 of 448 rej09b0394-0200 (14) operation when error occurs during pwm mode 2 op eration, and operation is restarted in pwm mode 1: figure 8.97 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) ? not initialized (cycle register) note: n = 0 to 15 hi-z hi-z figure 8.97 error occu rrence in pwm mode 2, recovery in pwm mode 1 1 to 9 are the same as in figure 8.96. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 237 of 448 rej09b0394-0200 (15) operation when error occurs during pwm mode 2 op eration, and operation is restarted in pwm mode 2: figure 8.98 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (cycle register) ? not initialized (cycle register) note: n = 0 to 15 hi-z hi-z figure 8.98 error occu rrence in pwm mode 2, recovery in pwm mode 2 1 to 9 are the same as in figure 8.96. 10. not necessary when restarting in pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 238 of 448 rej09b0394-0200 (16) operation when error occurs during pwm mode 2 op eration, and operation is restarted in phase counting mode: figure 8.99 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in phase counting mode after re- setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (cycle register) note: n = 0 to 15 hi-z hi-z figure 8.99 error occurrence in pwm mode 2, recovery in phase counting mode 1 to 9 are the same as in figure 8.96. 10. set phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 239 of 448 rej09b0394-0200 (17) operation when error occurs during phase countin g mode operation, and operation is restarted in normal mode: figure 8.100 shows an explanator y diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen note: n = 0 to 15 hi-z hi-z figure 8.100 error occurr ence in phase counting mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set phase counting mode. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set in normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 240 of 448 rej09b0394-0200 (18) operation when error occurs during phase countin g mode operation, and operation is restarted in pwm mode 1: figure 8.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen ? not initialized (tioc * b) note: n = 0 to 15 hi-z hi-z figure 8.101 error occurr ence in phase counting mode, recovery in pwm mode 1 1 to 9 are the same as in figure 8.100. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc *b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 241 of 448 rej09b0394-0200 (19) operation when error occurs during phase countin g mode operation, and operation is restarted in pwm mode 2: figure 8.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen note: n = 0 to 15 hi-z hi-z ? not initialized (cycle register) figure 8.102 error occurr ence in phase counting mode, recovery in pwm mode 2 1 to 9 are the same as in figure 8.100. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 242 of 448 rej09b0394-0200 (20) operation when error occurs during phase countin g mode operation, and operation is restarted in phase counting mode: figure 8.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen note: n = 0 to 15 hi-z hi-z figure 8.103 error occurren ce in phase counting mode, recovery in phase counting mode 1 to 9 are the same as in figure 8.100. 10. not necessary when restarting in phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 243 of 448 rej09b0394-0200 (21) operation when error occurs during complementary pwm mode operation, and operation is restarted in normal mode: figure 8.104 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in normal mode after re-setting. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.104 error occurren ce in complementary pwm mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 3. set complementary pwm. 4. enable channel 3 and 4 output with toer. 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. the complementary pwm waveform is output on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. (mtu output becomes the complementary pwm output initial value.) 11. set normal mode. (mtu output goes low.) 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 244 of 448 rej09b0394-0200 (22) operation when error occurs during complementary pwm mode operation, and operation is restarted in pwm mode 1: figure 8.105 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 ? not initialized (tioc3b) ? not initialized (tioc3d) hi-z hi-z hi-z figure 8.105 error occurren ce in complementary pwm mode, recovery in pwm mode 1 1 to 10 are the same as in figure 8.104. 11. set pwm mode 1. (mtu output goes low.) 12. initialize the pins with tior. (in pwm mode 1, the tioc *b side is not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 245 of 448 rej09b0394-0200 (23) operation when error occurs during complementary pwm mode operation, and operation is restarted in complementary pwm mode: figure 8.106 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in complementary pwm mode after re-setting (when operation is restarted using the cycle and duty cycle settings at the time the counter was stopped). 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 pfc (mtu) 12 tstr (1) 13 match mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.106 error occurrence in co mplementary pwm mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 8.104. 11. set mtu output with the pfc. 12. operation is restarted by tstr. 13. the complementary pwm waveform is output on compare-match occurrence.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 246 of 448 rej09b0394-0200 (24) operation when error occurs during complementary pwm mode operation, and operation is restarted in complementary pwm mode: figure 8.107 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in complementary pwm mode after re-setting (when operation is restarted using completely new cycle and duty cycle settings). 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 toer (0) 13 tocr 14 tmdr (cpwm) 15 toer (1) 16 pfc (mtu) 17 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.107 error occurrence in co mplementary pwm mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 8.104. 11. set normal mode and make new settings. (mtu output goes low.) 12. disable channel 3 and 4 output with toer. 13. select the complementary pwm mode output level and cyclic output enabling/disabling with tocr. 14. set complementary pwm. 15. enable channel 3 and 4 output with toer. 16. set mtu output with the pfc. 17. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 247 of 448 rej09b0394-0200 (25) operation when error occurs during complementary pwm mode operation, and operation is restarted in reset-synchronous pwm mode: figure 8.108 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in reset-synchronous pwm mode. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 toer (0) 13 tocr 14 tmdr (rpwm) 15 toer (1) 16 pfc (mtu) 17 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.108 error occurren ce in complementary pwm mode, recovery in reset-synchronous pwm mode 1 to 10 are the same as in figure 8.104. 11. set normal mode. (mtu output goes low.) 12. disable channel 3 and 4 output with toer. 13. select the reset-synchronous pwm mode output level and cyclic output enabling/disabling with tocr. 14. set reset-synchronous pwm. 15. enable channel 3 and 4 output with toer. 16. set mtu output with the pfc. 17. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 248 of 448 rej09b0394-0200 (26) operation when error occurs during reset-synchronous pwm mode operation, and operation is restarted in normal mode: figure 8.109 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in normal mode after re-setting. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.109 error occurrence in reset-synchronous pwm mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. select the reset-synchronous pwm output level and cyclic output enabling/disabling with tocr. 3. set reset-synchronous pwm. 4. enable channel 3 and 4 output with toer. 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. the reset-synchronous pwm waveform is output on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. (mtu output becomes the reset-synchronous pwm output initial value.) 11. set normal mode. (mtu positive phase output is low, and negative phase output is high.) 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 249 of 448 rej09b0394-0200 (27) operation when error occurs during reset-synchronous pwm mode operation, and operation is restarted in pwm mode 1: figure 8.110 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tocr 3 tmdr (rpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 ? not initialized (tioc3b) ? not initialized (tioc3d) hi-z hi-z hi-z figure 8.110 error occurrence in reset-synchronous pwm mode, recovery in pwm mode 1 1 to 10 are the same as in figure 8.109. 11. set pwm mode 1. (mtu positive phase output is low, and negative phase output is high.) 12. initialize the pins with tior. (in pwm mode 1, the tioc *b side is not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 250 of 448 rej09b0394-0200 (28) operation when error occurs during reset-synchronous pwm mode operation, and operation is restarted in complementary pwm mode: figure 8.111 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in complementary pwm mode after re-setting. 1 reset 2 tocr 3 tmdr (rpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 toer (0) 12 tocr 13 tmdr (cpwm) 14 toer (1) 15 pfc (mtu) 16 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 8.111 error occurrence in reset-synchronous pwm mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 8.109. 11. disable channel 3 and 4 output with toer. 12. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 13. set complementary pwm. (the mtu cyclic output pin goes low.) 14. enable channel 3 and 4 output with toer. 15. set mtu output with the pfc. 16. operation is restarted by tstr.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 251 of 448 rej09b0394-0200 (29) operation when error occurs during reset-synchronous pwm mode operation, and operation is restarted in reset-synchronous pwm mode: figure 8.112 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in reset-synchronous pwm mode after re-setting. 1 reset 2 tocr 3 tmdr (rpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 pfc (mtu) 12 tstr (1) 13 match mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z hi-z hi-z hi-z figure 8.112 error occurrence in reset-synchronous pwm mode, recovery in reset-synchronous pwm mode 1 to 10 are the same as in figure 8.109. 11. set mtu output with the pfc. 12. operation is restarted by tstr. 13. the reset-synchronous pwm waveform is output on compare-match occurrence.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 252 of 448 rej09b0394-0200 8.9 port output enable (poe) the port output enable (poe) can be used to esta blish a high-impedance state for high-current pins, by changing the poe0 to poe3 pin input, depending on the output status of the high-current pins (pe9/tioc3b, pe11/tioc3d, pe12/tioc4a, pe13/tioc4b/ mres , pe14/tioc4c, pe15/tioc4d/ irqout ). it can also simultaneously generate interrupt requests. the high-current pins also become high-impedance regardless of whether these pin functions are selected in cases such as when the oscillator stops or in standby mode. 8.9.1 features ? each of the poe0 to poe3 input pins can be set for falling edge, p /8 16, p /16 16, or p /128 16 low-level sampling. ? high-current pins can be set to high-impedance state by poe0 to poe3 pin falling-edge or low-level sampling. ? high-current pins can be set to high-impedance state when the high-current pin output levels are compared and simultaneous low-level output continues for one cycle or more. ? interrupts can be generated by input-level sampling or output-level comparison results.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 253 of 448 rej09b0394-0200 the poe has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of figure 8.113. tioc3b tioc3d tioc4a tioc4c tioc4b tioc4d poe3 poe2 poe1 poe0 output level detection circuit output level detection circuit output level detection circuit input level detection circuit falling-edge detection circuit low-level detection circuit ocsr icsr1 p /8 p /16 p /128 high- impedance request control signal interrupt request (mtupoe) legend: ocsr: output level control/status register icsr1: input level control/status register figure 8.113 poe block diagram
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 254 of 448 rej09b0394-0200 8.9.2 pin configuration table 8.44 pin configuration name abbreviation i/o description port output enable input pins poe0 to poe3 input input request signals to make high- current pins high-impedance state table 8.45 shows output-level comparisons with pin combinations. table 8.45 pin combinations pin combination i/o description pe9/tioc3b and pe11/tioc3d output all high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. pe12/tioc4a and pe14/tioc4c output all high- current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. pe13/tioc4b/ mres and pe15/tioc4d/ irqout output all high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. 8.9.3 register configuration the poe has the two registers. the input level control/status register 1 (icsr1) controls both poe0 to poe3 pin input signal detection and interrupts. the output level control/status register (ocsr) controls both the enable/disable of output comparison and interrupts. input level control/status register 1 (icsr1): the input level control/status register (icsr1) is a 16-bit readable/writable register that selects the poe0 to poe3 pin input modes, controls the enable/disable of interrupts, and indicates status.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 255 of 448 rej09b0394-0200 bit bit name initial value r/w description 15 poe3f 0 r/(w) * poe3 flag this flag indicates that a high impedance request has been input to the poe3 pin [clearing condition] ? by writing 0 to poe3f after reading a poe3f = 1 [setting condition] ? when the input set by icsr1 bits 7 and 6 occurs at the poe3 pin 14 poe2f 0 r/(w) * poe2 flag this flag indicates that a high impedance request has been input to the poe2 pin [clearing condition] ? by writing 0 to poe2f after reading a poe2f = 1 [setting condition] ? when the input set by icsr1 bits 5 and 4 occurs at the poe2 pin 13 poe1f 0 r/(w) * poe1 flag this flag indicates that a high impedance request has been input to the poe1 pin [clearing condition] ? by writing 0 to poe1f after reading a poe1f = 1 [setting condition] ? when the input set by icsr1 bits 3 and 2 occurs at the poe1 pin 12 poe0f 0 r/(w) * poe0 flag this flag indicates that a high impedance request has been input to the poe0 pin [clearing condition] ? by writing 0 to poe0f after reading a poe0f = 1 [setting condition] ? when the input set by icsr1 bits 1 and 0 occurs at the poe0 pin
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 256 of 448 rej09b0394-0200 bit bit name initial value r/w description 11 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 pie 0 r/w port interrupt enable this bit enables/disables interrupt requests when any of the poe0f to poe3f bits of the icsr1 are set to 1 0: interrupt requests disabled 1: interrupt requests enabled 7 6 poe3m1 poe3m0 0 0 r/w r/w poe3 mode 1, 0 these bits select the input mode of the poe3 pin 00: accept request on falling edge of poe3 input 01: accept request when poe3 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe3 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe3 input has been sampled for 16 p /128 clock pulses, and all are low level. 5 4 poe2m1 poe2m0 0 0 r/w r/w poe2 mode 1, 0 these bits select the input mode of the poe2 pin 00: accept request on falling edge of poe2 input 01: accept request when poe2 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe2 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe2 input has been sampled for 16 p /128 clock pulses, and all are low level. 3 2 poe1m1 poe1m0 0 0 r/w r/w poe1 mode 1, 0 these bits select the input mode of the poe1 pin 00: accept request on falling edge of poe1 input 01: accept request when poe1 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe1 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe1 input has been sampled for 16 p /128 clock pulses, and all are low level.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 257 of 448 rej09b0394-0200 bit bit name initial value r/w description 1 0 poe0m1 poe0m0 0 0 r/w r/w poe0 mode 1, 0 these bits select the input mode of the poe0 pin 00: accept request on falling edge of poe0 input 01: accept request when poe0 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe0 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe0 input has been sampled for 16 p /128 clock pulses, and all are low level. note: * the write value should always be 0. output level control/status register (ocsr): the output level control/status register (ocsr) is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. if the osf bit is set to 1, the high current pins become high impedance. bit bit name initial value r/w description 15 osf 0 r/(w) * output short flag this flag indicates that any one pair of the three pairs of 2 phase outputs compared have simultaneously become low level outputs. [clearing condition] ? by writing 0 to osf after reading an osf = 1 [setting condition] ? when any one pair of the three 2-phase outputs simultaneously become low level 14 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 258 of 448 rej09b0394-0200 bit bit name initial value r/w description 9 oce 0 r/w output level compare enable this bit enables the start of output level comparisons. when setting this bit to 1, pay attention to the output pin combinations shown in table 8.43, mode transition combinations. when 0 is output, the osf bit is set to 1 at the same time when this bit is set, and output goes to high impedance. accordingly, bits 15 to 11 and bit 9 of the port e data register (pedr) are set to 1. for the mtu output comparison, set the bit to 1 after setting the mtu's output pins with the pfc. set this bit only when using pins as outputs. when the oce bit is set to 1, if oie = 0 a high- impedance request will not be issued even if osf is set to 1. therefore, in order to have a high-impedance request issued according to the result of the output level comparison, the oie bit must be set to 1. when oce = 1 and oie = 1, an interrupt request will be generated at the same time as the high-impedance request: however, this interrupt can be masked by means of an interrupt controller (intc) setting. 0: output level compare disabled 1: output level compare enabled; makes an output high impedance request when osf = 1. 8 oie 0 r/w output short interrupt enable this bit makes interrupt requests when the osf bit of the ocsr is set. 0: interrupt requests disabled 1: interrupt request enabled 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * the write value should always be 0.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 259 of 448 rej09b0394-0200 8.9.4 operation input level detection operation if the input conditions set by the icsr1 occur on any of the poe pins, all high-current pins become high-impedance state. however, only when the general input/output function or mtu function is selected, the large-current pin is in the high-impedance state. falling edge detection: when a change from high to low level is input to the poe pins. low-level detection: figure 8.114 shows the low-level detection operation. sixteen continuous low levels are sampled with the sampling clock estab lished by the icsr1. if even one high level is detected during this interval, the low level is not accepted. furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection. p sampling clock 3 poe input pe9/ tioc3b when low level is sampled at all points when high level is sampled at least once flag set ( poe received) flag not set high-impedance state * note: * other large-current pins (pe11/tioc3d, pe12/tioc4a, pe13/tioc4b/ mres , pe14/tioc4c, pe15/tioc4d/ irqout ) also go to the high-impedance state at the same timing. 2 1 2 1 16 13 8/16/128 clock cycles figure 8.114 low-level detection operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 260 of 448 rej09b0394-0200 output-level co mpare operation figure 8.115 shows an example of the output-level compare operation for the combination of pe9/tioc3b and pe11/tioc3d. the operation is the same for the other pin combinations. p pe11/ tioc3d pe9/ tioc3b 0 level overlapping detected high impedance state figure 8.115 output-lev el detection operation release from high-impedance state high-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12 to 15 (poe0f to poe3f) flags of the icsr1. high-current pins that have become high- impedance due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (oce) of the ocsr to disable output-level compares, then clearing the bit 15 (osf) flag. however, when returning from high-impedance state by clearing the osf flag, always do so only after outputting a high level from the high- current pins (tioc3b, tioc3d, tioc4a, tioc4b, tioc4c, and tioc4d). high-level outputs can be achieved by setting the mtu internal registers.
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 261 of 448 rej09b0394-0200 poe timing figure 8.116 shows an example of timing from poe input to high impedance of pin. poe input ck falling p pe9/ tioc3b falling edge detected high impedance state note: other large-current pins (pe11/tico3d, pe12/tioc4a, pe13/tioc4b/ mres , pe14/tioc4c, pe15/tioc4d/ irqout ) also go to the high impedance state at the same timing figure 8.116 falling edge detection operation
8. multi-function timer pulse unit (mtu) rev.2.00 sep. 27, 2007 page 262 of 448 rej09b0394-0200 8.9.5 usage note to set the poe pin as a level detection pin, a high level signal must be firstly input to the poe pin. (1) symptom (a) regarding the poenf* 1 bits if setting of the poenf bits in the input level control/status registers (icsr1 and icsr2) by the hardware* 2 and reading from these bits occur simulta neously, ?0? will be read, where ?1? should be read. furthermore, if clearing of these bits is attempted subsequent to the above condition, the clearing should be ignored* 3 but it will be carried out. notes: *1 for the sh7046-series and sh7047-series, n = 0 to 6; for the sh7144-series, n = 0 to 3. *2 the poenf bits are set when the signals input to the respective poen pins satisfy the conditions that are specified by the poen m1 and poenm0 of the icsr1 and icsr2. *3 the correct operation is that clearing of the poenf bits is only possible after ?1? is read from them in order to prevent accidental clearing. (b) regarding the osf bit the same symptom applies to the osf bits of the output level control/status register (ocsr). (2) to avoid this problem please clear the poenf bits or the osf bit in these steps: firs t execute a read for icsr1, icsr2, or ocsr, then write ?0? to the bits that had a re ad value of ?1? to clear them while writing ?1? to other bits. if this procedure is not followed, the poenf bits and the osf bit may be cleared unexpectedly if their setting by hardware and reading occur simultaneously.
9. watchdog timer wdt0400a_010020030200 rev.2.00 sep. 27, 2007 page 263 of 448 rej09b0394-0200 section 9 watchdog timer the watchdog timer (wdt) is an 8-bit timer that can reset this lsi internally if the counter overflows without rewriting the counter value due to a system crash or the like. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. the block diagram of the wdt is shown in figure 9.1. 9.1 features ? selectable from eight counter input clocks. ? switchable between watchdog timer mode and interval timer mode ? clears software standby mode in watchdog timer mode ? output wdtovf signal ? if the counter overflows, it is possible to select whether this lsi is internally reset or not. in interval timer mode ? if the counter overflows, the wdt generates an interval timer interrupt (iti).
9. watchdog timer rev.2.00 sep. 27, 2007 page 264 of 448 rej09b0394-0200 overflow interrupt control iti (interrupt request signal) internal reset signal * reset control rstcsr tcnt tscr /2 /64 /128 /256 /512 /1024 /4096 /8192 clock clock select internal clock sources bus interface module bus internal bus wdt legend: tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register note: * the internal reset signal can be generated by making a register setting. power-on reset or manual reset can be selected. wdtovf figure 9.1 block diagram of wdt 9.2 input/output pin table 9.1 shows the pin configuration of the watchdog timer. table 9.1 pin configuration pin abbreviation i/o function watchdog timer overflow wdtovf o outputs the counter overflow signal in watchdog timer mode note: the wdtovf pin should not be pulled down. however, if it is necessary to pull this pin down, a resistance of 1 m or higher should be used.
9. watchdog timer rev.2.00 sep. 27, 2007 page 265 of 448 rej09b0394-0200 9.3 register descriptions the wdt has the following three registers. for details, refer to section 18, list of registers. to prevent accidental overwriting, tcsr, tcnt, and rstcsr have to be written to in a method different from normal registers. for details, re fer to section 9.6.1, notes on register access. ? timer control/status register (tcsr) ? timer counter (tcnt) ? reset control/status register (rstcsr) 9.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable upcounter. when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, tcnt starts counting pulses of an internal clock selected by clock select bits 2 to 0 (cks2 to cks0) in tcsr. when the value of tcnt overflows (changes from h'ff to h'00), a watchdog timer overflow signal ( wdtovf ) or interval timer interrupt (iti) is generated, depending on the mode selected in the wt/ it bit of tcsr.
9. watchdog timer rev.2.00 sep. 27, 2007 page 266 of 448 rej09b0394-0200 9.3.2 timer control/status register (tcsr) tcsr is an 8-bit readable/writable register. its functions include selecting the clock source to be input to tcnt, and the timer mode. bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcnt has overflowed in interval timer mode. only a write of 0 is permitted, to clear the flag. this flag is not set in watchdog timer mode. [setting condition] ? when tcnt overflows in interval timer mode. [clearing conditions] ? cleared by reading ovf ? when 0 is written to the tme bit in interval timer mode 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. when tcnt overflows, the wdt either generates an interval timer interrupt (iti) or generates a wdtovf signal, depending on the mode selected. 0: interval timer mode interval timer interrupt (iti) request to the cpu when tcnt overflows 1: watchdog timer mode wdtovf signal output externally when tcnt overflows * 2 . 5 tme 0 r/w timer enable enables or disables the timer. 0: timer disabled tcnt is initialized to h'00 and count-up stops 1: timer enabled tcnt starts counting. a wdtovf signal or interrupt is generated when tcnt overflows. 4, 3 ? all 1 r reserved this bit is always read as 1, and should only be written with 1.
9. watchdog timer rev.2.00 sep. 27, 2007 page 267 of 448 rej09b0394-0200 bit bit name initial value r/w description 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select one of eight internal clock sources for input to tcnt. the clock signals are obtained by dividing the frequency of the system clock ( ). the overflow frequency for = 40 mhz is enclosed in parentheses * 3 . 000: clock /2 (frequency: 12.8 s) 001: clock /64 (frequency: 409.6 s) 010: clock /128 (frequency: 0.8 ms) 011: clock /256 (frequency: 1.6 ms) 100: clock /512 (frequency: 3.3 ms) 101: clock /1024 (frequency: 6.6 ms) 110: clock /4096 (frequency: 26.2 ms) 111: clock /8192 (frequency: 52.4 ms) notes: 1. only a 0 can be written after reading 1. 2. section 9.3.3, reset control/status register (rstcsr), describes in detail what happens when tcnt overflows in watchdog timer mode. 3. the overflow interval listed is the time from when the tcnt begins counting at h'00 until an overflow occurs.
9. watchdog timer rev.2.00 sep. 27, 2007 page 268 of 448 rej09b0394-0200 9.3.3 reset control/status register (rstcsr) rstcsr is an 8-bit readable/writable register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode. [setting condition] ? set when tcnt overflows in watchdog timer mode [clearing condition] ? cleared by reading wovf, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not a reset signal is generated in the chip if tcnt overflows in watchdog timer mode. 0: reset signal is not generated even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: reset signal is generated if tcnt overflows 5 rsts 0 r/w reset select selects the type of internal reset generated if tcnt overflows in watchdog timer mode. 0: power-on reset 1: manual reset 4 to 0 ? all 1 r reserved these bits are always read as 1, and should only be written with 1. note: * only 0 can be written, for flag clearing.
9. watchdog timer rev.2.00 sep. 27, 2007 page 269 of 448 rej09b0394-0200 9.4 operation 9.4.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it and tme bits of tcsr to 1. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. no tcnt overflows will occur while the sy stem is operating normally, but if tcnt fails to be rewritten and overflows occur due to a system crash or the like, a wdtovf signal is output externally. the wdtovf signal can be used to reset the system. the wdtovf signal is output for 128 clock cycles. if the rste bit in rstcsr is set to 1, a signal to reset the chip will be generated internally simultaneous to the wdtovf signal when tcnt overflows. either a power-on reset or a manual reset can be selected by the rsts bit in rstcsr. the internal reset signal is output for 512 clock cycles. when a wdt overflow reset is generated simultaneously with a reset input at the res pin, the res reset takes priority, and the wovf bit in rstcsr is cleared to 0. the following are not initialized by a wdt reset signal: ? poe (port output enable) of mtu registers ? pfc (pin function controller) registers ? i/o port registers these registers are initialized only by an external power-on reset.
9. watchdog timer rev.2.00 sep. 27, 2007 page 270 of 448 rej09b0394-0200 tcnt value h'ff h'00 wdtovf signal internal reset signal * overflow h'00 written in tcnt wt/ it = 1 tme = 1 h'00 written in tcnt wt/ it = 1 tme = 1 wovf = 1 wdtovf and internal reset generated 128 clocks 512 clocks legend: wt/ it : timer mode select bit tme: timer enable bit note: * internal reset signal occurs only when the rste bit is set to 1. time figure 9.2 operation in watchdog timer mode
9. watchdog timer rev.2.00 sep. 27, 2007 page 271 of 448 rej09b0394-0200 9.4.2 interval timer mode to use the wdt as an in terval timer, clear wt/ it to 0 and set tme to 1 in tcsr. an interval timer interrupt (iti) is generate d each time the timer counter (tcn t) overflows. this function can be used to generate interval timer interrupts at regular intervals. tcnt value h'ff h'00 overflow wt/ it = 0 tme = 1 overflow overflow overflow iti iti iti iti time legend: iti: interval timer interrupt request generation figure 9.3 operation in interval timer mode 9.4.3 clearing software standby mode the watchdog timer has a special function to clear software standby mode with an nmi interrupt or irq0 to irq3 interrupts. when using software standby mode, set the wdt as described below. before transition to software standby mode: the tme bit in tcsr must be cleared to 0 to stop the watchdog timer counter before entering software standby mode. the chip cannot enter software standby mode while the tme bit is set to 1. set bits cks2 to cks0 in tcsr so that the counter overflow interval is equal to or longer than the oscillation settling time. see section 19.3, ac characteristics, for the oscillation settling time. recovery from software standby mode: when an nmi signal or irq0 to irq3 signals are received in software standby mode, the clock oscillator starts running and tcnt starts incrementing at the rate selected by bits cks2 to cks0 before software standby mode was entered. when tcnt overflows (changes from h'ff to h'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and software standby mode ends. for details on software standby mode, see section 17, power-down modes.
9. watchdog timer rev.2.00 sep. 27, 2007 page 272 of 448 rej09b0394-0200 9.4.4 timing of setting the overflow flag (ovf) in interval timer mode, when tcnt overflows, the ovf bit of tcsr is set to 1 and an interval timer interrupt (iti) is simultaneously requested. figure 9.4 shows this timing. tcnt overflow signal (internal signal) ovf h'ff h'00 figure 9.4 timing of setting ovf 9.4.5 timing of setting the watchdog timer overflow flag (wovf) when tcnt overflows in watchdog timer mode, the wovf bit of rstcsr is set to 1 and a wdtovf signal is output. when the rste bit in rstcsr is set to 1, tcnt overflow enables an internal reset signal to be generated for the entire chip. figure 9.5 shows this timing. tcnt overflow signal (internal signal) wovf h'ff h'00 figure 9.5 timing of setting wovf
9. watchdog timer rev.2.00 sep. 27, 2007 page 273 of 448 rej09b0394-0200 9.5 interrupt source during interval timer mode operation, an overflow generates an interval timer interrupt (iti). the interval timer interrupt is requested whenever th e ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. table 9.2 wdt interrupt source (in interval timer mode) name interrupt source interrupt flag iti tcnt overflow ovf 9.6 usage notes 9.6.1 notes on register access the watchdog timer's tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte transfer instructions. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must be h'5a (for tcnt) or h'a5 (for tcsr) (figure 9.6). this transfers the write data from the lower byte to tcnt or tcsr. 15 8 7 0 15 8 7 0 h'5a h'a5 write data write data ? writing to tcnt ? writing to tcsr address: h'ffff8610 address: h'ffff8610 figure 9.6 writing to tcnt and tcsr
9. watchdog timer rev.2.00 sep. 27, 2007 page 274 of 448 rej09b0394-0200 writing to rstcsr: rstcsr must be written by a word access to address h'ffff8612. it cannot be written by byte transfer instructions. procedures for writing 0 to wovf (bit 7) and for writing to rste (bit 6) and rsts (bit 5) are different, as shown in figure 9.7. to write 0 to the wovf bit, the write data must be h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0. the rste and rsts bits are not affected. to write to the rste and rsts bits, the upper byte must be h'5a and the lower byte must be the write data. the values of bits 6 and 5 of the lower byte are transferred to the rste and rsts bits, respectively. the wovf bit is not affected. 15 8 7 0 15 8 7 0 h'a5 h'5a write data ? writing 0 to the wovf bit ? writing to the rste and rsts bits address: h'ffff8612 address: h'ffff8612 h'00 figure 9.7 writing to rstcsr reading from tcnt, tcsr, and rstcsr: tcnt, tcsr, and rstcsr are read like other registers. use byte transfer instructions . the read addresses are h'ffff8610 for tcsr, h'ffff8611 for tcnt, and h'ffff8613 for rstcsr.
9. watchdog timer rev.2.00 sep. 27, 2007 page 275 of 448 rej09b0394-0200 9.6.2 tcnt write and increment contention if a timer counter increment clock pulse is generate d during the t3 state of a write cycle to tcnt, the write takes priority and the timer counter is not incremented. figure 9.8 shows this operation. address internal write signal tcnt input clock tcnt n m t 1 t 2 tcnt write cycle counter write data t 3 tcnt address figure 9.8 contention between tcnt write and increment 9.6.3 changing cks2 to cks0 bit values if the values of bits cks2 to cks0 in the timer control/status register (tcsr) are rewritten while the wdt is running, the count may not increment correctly. always stop the watchdog timer (by clearing the tme bit to 0) before rewriting the values of bits cks2 to cks0. 9.6.4 changing between watchdog timer/interval timer modes to prevent incorrect operation, always stop the watchdog timer (by clearing the tme bit to 0) before switching between interval timer mode and watchdog timer mode.
9. watchdog timer rev.2.00 sep. 27, 2007 page 276 of 448 rej09b0394-0200 9.6.5 system reset by wdtovf signal if a wdtovf output signal is input to the res pin, the chip cannot initialize correctly. avoid logical input of the wdtovf signal to the res input pin. to reset the entire system with the wdtovf signal, use the circuit shown in figure 9.9. reset input reset signal to entire system SH7101 res wdtovf figure 9.9 example of system reset circuit using wdtovf signal 9.6.6 internal reset in watchdog timer mode if the rste bit is cleared to 0 in watchdog timer mode , the chip will not be re set internally when a tcnt overflow occurs, but tcnt and tcsr in the wdt will be reset. 9.6.7 manual reset in watchdog timer mode when an internal reset is effected by tcnt overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. 9.6.8 notes on using wdtovf pin the wdtovf pin should not be pulled down. however, if it is necessary to pull this pin down, a resistance of 1 m or higher should be used.
10. serial communication interface (sci) scis200b_010020030200 rev.2.00 sep. 27, 2007 page 277 of 448 rej09b0394-0200 section 10 serial communication interface (sci) this lsi has two independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. in asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). 10.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually indepe ndent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the tran smitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected external clock can be selected as a transfer clock source. ? choice of lsb-first or msb-first transfer* (except in the case of asynchronous mode 7-bit data) ? four interrupt sources four interrupt sources ? transmit-end, transmit-data-empty , receive-data-full, and receive error ? that can issue requests. ? module standby mode can be set asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? multiprocessor bit: 1 or 0 ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by reading the rxd pin level directly in case of a framing error
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 278 of 448 rej09b0394-0200 clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected note: * the description in this section are based on lsb-first transfer. figure 10.1 shows a block diagram of the sci. rxd txd sck clock p p /8 p /32 p /128 tei txi rxi eri ssr scr smr sdcr transmission/ reception control baud rate generator brr module data bus rdr tsr rsr parity generation legend: rsr: receive shift register rdr: receive data register tsr: transmit shift register tdr: transmit data register smr: serial mode register scr: serial control register ssr: serial status register brr: bit rate register sdcr: serial direction control register tdr bus interface internal data bus parity check external clock figure 10.1 block diagram of sci
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 279 of 448 rej09b0394-0200 10.2 input/output pins table 10.1 shows the sci pin configuration. table 10.1 pin configuration channel pin name * i/o function sck2 i/o sci2 clock input/output rxd2 input sci2 receive data input 2 txd2 output sci2 transmit data output sck3 i/o sci3 clock input/output 3 rxd3 input sci3 receive data input txd3 output sci3 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 10.3 register descriptions the sci has the following register s for each channel. for details on register addresses and register states during each processing, refer to section 18, list of registers. channel 2 ? serial mode register_2 (smr_2) ? bit rate register_2 (brr_2) ? serial control register_2 (scr_2) ? transmit data register_2 (tdr_2) ? serial status register_2 (ssr_2) ? receive data register_2 (rdr_2) ? serial direction control register_2 (sdcr_2) channel 3 ? serial mode register_3 (smr_3) ? bit rate register_3 (brr_3) ? serial control register_3 (scr_3) ? transmit data register_3 (tdr_3) ? serial status register_3 (ssr_3)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 280 of 448 rej09b0394-0200 ? receive data register_3 (rdr_3) ? serial direction control register_3 (sdcr_3) 10.3.1 receive shift register (rsr) rsr is a shift register used to receive serial data that is input to the rxd pin and convert it into parallel data. when one byte of data has been r eceived, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 10.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive da ta. when the sci has received one byte of serial data, it transfers the received serial data from rs r to rdr where it is stor ed. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, enables continuous receive operations to be performed. after confirmi ng that the rdrf bit in ssr is set to 1, read rdr for only once. rdr cannot be written to by the cpu. the initial value of rdr is h'00. 10.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. 10.3.4 transmit data register (tdr) tdr is an 8-bit register that stores transmit data. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts transmission. the double-buffered structures of tdr and tsr enables continuous serial transmission. if the next transmit data has already been written to tdr during serial transmission, the sci transfers the written data to tsr to continue transmission. although tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. the initial value of tdr is h'ff.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 281 of 448 rej09b0394-0200 10.3.5 serial mode register (smr) smr is used to set the sci's serial transfer format and select the ba ud rate generator clock source. bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb (bit 7) of tdr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. for a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode (enabled only in asynchronous mode) when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 282 of 448 rej09b0394-0200 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock source for the baud rate generator. 00: p clock (n = 0) 01: p /8 clock (n = 1) 10: p /32 clock (n = 2) 11: p /128 clock (n = 3) for the relation between the bit rate register setting and the baud rate, see section 10.3.9, bit rate register (brr). n is the decimal display of the value of n in brr (see section 10.3.9, bit rate register (brr)).
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 283 of 448 rej09b0394-0200 10.3.6 serial control register (scr) scr is a register that performs enabling or disabling of sci transfer operations and interrupt requests, and selection of the transfer clock source. for details on interrupt requests, refer to section 10.7, interrupts sources. bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, txi interrupt request is enabled. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 10.5, multiprocessor communication function. 2 teie 0 r/w transmit end interrupt enable this bit is set to 1, tei interrupt request is enabled.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 284 of 448 rej09b0394-0200 bit bit name initial value r/w description 1 0 cke1 cke0 0 0 r/w r/w clock enable 1 and 0 selects the clock source and sck pin function. asynchronous mode: 00: internal clock, sck pin used for input pin (input signal is ignored) or output pin (output level is undefined) 01: internal clock, sck pin used for clock output (the output clock frequency is the same as the bit rate) 10: external clock, sck pin used for clock input (the input clock frequency is 16 times the bit rate) 11: external clock, sck pin used for clock input (the input clock frequency is 16 times the bit rate) clocked synchronous mode: 00: internal clock, sck pin used for synchronous clock output 01: internal clock, sck pin used for synchronous clock output 10: external clock, sck pin used for synchronous clock input 11: external clock, sck pin used for synchronous clock input
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 285 of 448 rej09b0394-0200 10.3.7 serial status register (ssr) ssr is a register containing stat us flags of the sci and multiproce ssor bits for transfer. 1 cannot be written to flags tdre, rdrf, orer, per, and fer; they can only be cleared. bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty displays whether tdr contains transmit data. [setting conditions] ? power-on reset or software standby mode ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing condition] ? when 0 is written to tdre after reading tdre = 1 6 rdrf 0 r/(w) * receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to rdrf after reading rdrf = 1 the rdrf flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 5 orer 0 r/(w) * overrun error [setting condition] ? when the next serial reception is completed while rdrf = 1 [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains their previous values when the re bit in scr is cleared to 0.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 286 of 448 rej09b0394-0200 bit bit name initial value r/w description 4 fer 0 r/(w) * framing error [setting condition] ? when the stop bit is 0 [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to fer after reading fer = 1 in 2-stop-bit mode, only the first stop bit is checked. the fer flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 3 per 0 r/(w) * parity error [setting condition] ? when a parity error is detected during reception [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to per after reading per = 1 the per flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2 tend 1 r transmit end [setting conditions] ? power-on reset or software standby mode ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1- byte serial transmit character [clearing condition] ? when 0 is written to tdre after reading tdre = 1 1 mpb 0 r multiprocessor bit mpb stores the multiprocessor bit in the receive data. when the re bit in scr is cleared to 0 its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer mpbt sets the multiprocessor bit value to be added to the transmit data. note: * only 0 can be written, for flag clearing.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 287 of 448 rej09b0394-0200 10.3.8 serial direction control register (sdcr) the dir bit in the serial direction control register (sdcr) sel ects lsb-first or msb-first transfer. with an 8-bit data length, lsb-first/msb-first selection is available regardless of the communication mode. with a 7-bit data length, lsb-first transfer must be selected. the description in this section assumes lsb-first transfer. bit bit name initial value r/w description 7 to 4 ? all 1 r reserved the write value must always be 1. operation cannot be guaranteed if 0 is written. 3 dir 0 r/w data transfer direction selects the serial/parallel conversion format. valid for an 8-bit transmit/receive format. 0: tdr contents are transmitted in lsb-first order receive data is stored in rdr in lsb-first 1: tdr contents are transmitted in msb-first order receive data is stored in rdr in msb-first 2 ? 0 r reserved the write value must always be 0. operation cannot be guaranteed if 1 is written. 1 ? 1 r reserved this bit is always read as 1, and cannot be modified. 0 ? 0 r reserved the write value must always be 0. operation cannot be guaranteed if 1 is written. 10.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rate s can be set for each channel. table 10.2 shows the relationships between the n setting in brr and the effective bit rate b 0 for asynchronous and clocked synchronous modes. the initial value of brr is h'ff, and it can be read or written to by the cpu at all times.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 288 of 448 rej09b0394-0200 table 10.2 relationships between n setting in brr and effective bit rate b 0 mode asynchronous mode (n = 0) asynchronous mode (n = 1 to 3) clocked synchronous mode (n = 0) clocked synchronous mode (n = 1 to 3) b 0 = p 10 6 32 2 2n (n + 1) bit rate error b 0 b 1 b 0 = p 10 6 32 2 2n+1 (n + 1) b 0 = p 10 6 4 2 2n (n + 1) b 0 = p 10 6 4 2 2n+1 (n + 1) error ( % ) = ? 1 100 ? ? ? ? b 0 b 1 error ( % ) = ? ? ? 1 100 ? ? ? ? notes: b 0 : effective bit rate (bit/s) actual transfer speed according to the register settings b 1 : logical bit rate (bit/s) specified transfer speed of the target system n: brr setting for baud rate generator (0 n 255) p : peripheral clock operating frequency (mhz) n : determined by the smr settings shown in the following tables. smr setting cks1 cks0 n 0 0 0 0 1 1 1 0 2 1 1 3 table 10.3 shows sample n settings in brr in normal asynchronous mode. table 10.4 shows the maximum bit rate for each frequency in normal asynchronous mode. table 10.6 shows sample n settings in brr in clocked synchronous mode. for details, refer to section 10.4.2, receive data sampling timing and reception margin in asynchron ous mode. tables 10.5 and 10.7 show the maximum bit rates with external clock input.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 289 of 448 rej09b0394-0200 table 10.3 brr settings for various bit rates (asynchronous mode) operating frequency p (mhz) 4 6 8 10 12 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 140 0.74 1 212 0.03 2 70 0.03 2 88 ?0.25 2 106 ?0.44 150 1 103 0.16 1 155 0.16 2 51 0.16 2 64 0.16 2 77 0.16 300 1 51 0.16 1 77 0.16 2 25 0.16 1 129 0.16 2 38 0.16 600 1 25 0.16 1 38 0.16 2 12 0.16 1 64 0.16 1 77 0.16 1200 1 12 0.16 0 155 0.16 1 25 0.16 1 32 ?1.36 1 38 0.16 2400 0 51 0.16 0 77 0.16 1 12 0.16 0 129 0.16 0 155 0.16 4800 0 25 0.16 0 38 0.16 0 51 0.16 0 64 0.16 0 77 0.16 9600 0 12 0.16 0 19 ?2.34 0 25 0.16 0 32 ?1.36 0 38 0.16 14400 0 8 ?3.55 0 12 0.16 0 16 2.12 0 21 ?1.36 0 25 0.16 19200 0 6 ?6.99 0 9 ?2.34 0 12 0.16 0 15 1.73 0 19 ?2.34 28800 0 3 8.51 0 6 ?6.99 0 8 ?3.55 0 10 ?1.36 0 12 0.16 31250 0 3 0.00 0 5 0.00 0 7 0.00 0 9 0.00 0 11 0.00 38400 0 2 8.51 0 4 ?2.34 0 6 ?6.99 0 7 1.73 0 9 ?2.34 operating frequency p (mhz) 14 16 18 20 22 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 123 0.23 2 141 0.03 2 159 ?0.12 2 177 ?0.25 2 194 0.16 150 2 90 0.16 2 103 0.16 2 116 0.16 2 129 0.16 2 142 0.16 300 2 45 ?0.93 2 51 0.16 2 58 ?0.69 2 64 0.16 2 71 ?0.54 600 2 22 ?0.93 1 103 0.16 1 116 0.16 1 129 0.16 1 142 0.16 1200 1 45 ?0.93 1 51 0.16 1 58 ?0.69 1 64 0.16 1 71 ?0.54 2400 1 22 ?0.93 0 207 0.16 0 233 0.16 1 32 ?1.36 1 35 ?0.54 4800 0 90 0.16 0 103 0.16 0 116 0.16 0 129 0.16 0 142 0.16 9600 0 45 ?0.93 0 51 0.16 0 58 ?0.69 0 64 0.16 0 71 ?0.54 14400 0 29 1.27 0 34 ?0.79 0 38 0.16 0 42 0.94 0 47 ?0.54 19200 0 22 ?0.93 0 25 0.16 0 28 1.02 0 32 ?1.36 0 35 ?0.54 28800 0 14 1.27 0 16 2.12 0 19 ?2.34 0 21 ?1.36 0 23 ?0.54 31250 0 13 0.00 0 15 0.00 0 17 0.00 0 19 0.00 0 21 0.00 38400 0 10 3.57 0 12 0.16 0 14 ?2.34 0 15 1.73 0 17 ?0.54
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 290 of 448 rej09b0394-0200 operating frequency p (mhz) 24 25 26 28 30 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 212 0.03 2 221 ?0.02 2 230 ?0.08 2 248 ?0.17 3 66 ?0.62 150 2 155 0.16 2 162 ?0.15 2 168 0.16 2 181 0.16 2 194 0.16 300 2 77 0.16 2 80 0.47 2 84 ?0.43 2 90 0.16 2 97 ?0.35 600 1 155 0.16 1 162 ?0.15 1 168 0.16 1 181 0.16 2 48 ?0.35 1200 1 77 0.16 1 80 0.47 1 84 ?0.43 1 90 0.16 1 97 ?0.35 2400 1 38 0.16 1 40 ?0.76 1 41 0.76 1 45 ?0.93 1 48 ?0.35 4800 0 155 0.16 0 162 ?0.15 0 168 0.16 0 181 0.16 0 194 0.16 9600 0 77 0.16 0 80 0.47 0 84 ?0.43 0 90 0.16 0 97 ?0.35 14400 0 51 0.16 0 53 0.47 0 55 0.76 0 60 ?0.39 0 64 0.16 19200 0 38 0.16 0 40 ?0.76 0 41 0.76 0 45 ?0.93 0 48 ?0.35 28800 0 25 0.16 0 26 0.47 0 27 0.76 0 29 1.27 0 32 ?1.36 31250 0 23 0.00 0 24 0.00 0 25 0.00 0 27 0.00 0 29 0.00 38400 0 19 ?2.34 0 19 1.73 0 20 0.76 0 22 ?0.93 0 23 1.73 operating frequency p (mhz) 32 34 36 38 40 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 70 0.03 3 74 0.62 3 79 ?0.12 3 83 0.40 3 88 ?0.25 150 2 207 0.16 2 220 0.16 2 233 0.16 2 246 0.16 3 64 0.16 300 2 103 0.16 2 110 ?0.29 2 116 0.16 2 123 ?0.24 2 129 0.16 600 2 51 0.16 2 54 0.62 2 58 ?0.69 2 61 ?0.24 2 64 0.16 1200 1 103 0.16 1 110 ?0.29 1 116 0.16 1 123 ?0.24 1 129 0.16 2400 1 51 0.16 1 51 6.42 1 58 ?0.69 1 61 ?0.24 1 64 0.16 4800 0 207 0.16 0 220 0.16 0 234 ?0.27 0 246 0.16 1 32 ?1.36 9600 0 103 0.16 0 110 ?0.29 0 116 0.16 0 123 ?0.24 0 129 0.16 14400 0 68 0.64 0 73 ?0.29 0 77 0.16 0 81 0.57 0 86 ?0.22 19200 0 51 0.16 0 54 0.62 0 58 ?0.69 0 61 ?0.24 0 64 0.16 28800 0 34 ?0.79 0 36 ?0.29 0 38 0.16 0 40 0.57 0 42 0.94 31250 0 31 0.00 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 38400 0 25 0.16 0 27 ?1.18 0 28 1.02 0 30 ?0.24 0 32 ?1.36
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 291 of 448 rej09b0394-0200 table 10.4 maximum bit rate for each fre quency when using baud rate generator (asynchronous mode) p (mhz) n n maximum bit rate (bit/s) 4 0 0 125000 8 0 0 250000 10 0 0 312500 12 0 0 375000 14 0 0 437500 16 0 0 500000 18 0 0 562500 20 0 0 625000 22 0 0 687500 24 0 0 750000 25 0 0 781250 26 0 0 812500 28 0 0 875000 30 0 0 937500 32 0 0 1000000 34 0 0 1062500 36 0 0 1125000 38 0 0 1187500 40 0 0 1250000
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 292 of 448 rej09b0394-0200 table 10.5 maximum bit rate with external clock input (asynchronous mode) p (mhz) external clock (mhz) maximum bit rate (bit/s) 4 1.0000 62500 6 1.5000 93750 8 2.0000 125000 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 25 6.2500 390625 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 293 of 448 rej09b0394-0200 table 10.6 brr settings for various bit rates (clocked synchronous mode) operating frequency p (mhz) 4 6 8 10 12 logical bit rate (bit/s) n n n n n n n n n n 250 2 124 2 187 2 249 ? ? ? ? ? ? 2 124 2 155 2 187 1000 1 124 1 187 1 249 ? ? ? ? 1 74 1 99 1 124 1 149 5000 1 24 ? ? 1 49 ? ? 1 74 10000 0 99 0 149 1 24 0 249 ? ? 0 59 1 9 0 99 1 14 50000 0 19 0 29 1 4 0 49 0 59 100000 0 9 0 14 0 19 0 24 0 29 250000 0 3 0 5 0 7 0 9 0 11 500000 0 1 0 2 0 3 0 4 0 5 1000000 0 0 ? ? 0 1 ? ? 0 2 2500000 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? ? operating frequency p (mhz) 14 16 18 20 22 logical bit rate (bit/s) n n n n n n n n n n 250 3 108 3 124 3 140 3 155 3 171 500 2 218 2 249 ? ? ? ? ? ? 2 124 2 140 2 155 3 42 2500 1 174 2 49 1 224 1 249 ? ? ? ? 2 24 1 112 1 124 1 137 10000 ? ? 1 49 ? ? ? ? ? ? 1 19 0 179 1 24 0 219 50000 0 69 1 9 0 89 0 99 0 109 100000 0 34 1 4 0 44 0 49 0 54 250000 0 13 1 1 0 17 0 19 0 21 500000 0 6 1 0 0 8 0 9 0 10 1000000 ? ? 0 3 ? ? 0 4 ? ? ? ? ? ? ? ? 0 1 ? ? ? ? ? ? ? ? 0 0 ? ?
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 294 of 448 rej09b0394-0200 operating frequency p (mhz) 24 25 26 28 30 logical bit rate (bit/s) n n n n n n n n n n 250 3 187 3 194 3 202 3 218 3 233 500 ? ? ? ? 3 101 3 108 3 116 1000 2 187 2 194 2 202 2 218 2 233 2500 2 74 ? ? ? ? ? ? ? ? 1 155 1 162 1 174 1 187 10000 1 74 ? ? ? ? ? ? ? ? 0 249 ? ? 1 34 ? ? 0 124 0 129 0 139 0 149 100000 0 59 ? ? 0 64 0 69 0 74 250000 0 23 0 24 0 25 0 27 0 29 500000 0 11 ? ? 0 12 0 13 0 14 1000000 0 5 ? ? ? ? 0 6 ? ? ? ? ? ? ? ? ? ? 0 2 5000000 ? ? ? ? ? ? ? ? ? ? operating frequency p (mhz) 32 34 36 38 40 logical bit rate (bit/s) n n n n n n n n n n 250 3 249 ? ? ? ? ? ? ? ? 3 132 3 140 3 147 3 155 1000 2 249 ? ? ? ? ? ? ? ? 2 105 2 112 2 118 2 124 5000 2 49 1 212 1 224 1 237 1 249 10000 2 24 1 105 1 112 1 118 1 124 25000 2 9 ? ? 1 44 ? ? 1 49 50000 2 4 0 169 0 179 0 189 1 24 100000 1 9 0 84 0 89 0 94 0 99 250000 1 3 0 33 0 35 0 37 0 39 500000 1 1 0 16 0 17 0 18 0 19 1000000 1 0 ? ? 0 8 ? ? 0 9 2500000 ? ? ? ? ? ? ? ? 0 3 5000000 ? ? ? ? ? ? ? ? 0 1
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 295 of 448 rej09b0394-0200 table 10.7 maximum bit rate with external clock input (clocked synchronous mode) p (mhz) external clock (mhz) maximum bit rate (bit/s) 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 25 4.1667 4166666.7 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7 legend: ? : can be set, but there will be a degree of error. * : continuous transfer is not possible. note: settings with an error of 1 % or less are recommended.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 296 of 448 rej09b0394-0200 10.4 operation in as ynchronous mode figure 10.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the co mmunication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. inside th e sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered struct ure, so that data can be read or written during transmission or reception, enabling continuous data transfer. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 10.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 10.4.1 data transfer format table 10.8 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, refer to section 10.5, multiprocessor communication function.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 297 of 448 rej09b0394-0200 table 10.8 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 x x x x s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 1234567 8 9 101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend: s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit x: don't care
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 298 of 448 rej09b0394-0200 10.4.2 receive data sampling timing and reception margin in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the bit rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 10.3. thus the reception margin in asynchronous mode is given by formula (1) below. m = 0.5 ? 1 2n (d ? 0.5) n ? ? (l ? 0.5) f 100 % ........................... formula (1) where m: reception margin ( % ) n: ratio of bit rate to clock (n = 16) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin is given by formula below. m = {0.5 ? 1/(2 16)} 100 [ % ] = 46.875 % however, this is only the computed value, and a margin of 20 % to 30 % should be allowed in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 0 7 figure 10.3 receive data samplin g timing in asynchronous mode
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 299 of 448 rej09b0394-0200 10.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci's serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 10.4. the clock must not be stopped during operation. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 sck txd figure 10.4 relation between output clock and transmit data phase (asynchronous mode)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 300 of 448 rej09b0394-0200 10.4.4 sci initialization (asynchronous mode) before transmitting and receiving data, you should firs t clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait yes [1] start transmission clear rie, tie, teie, mpie, te and re bits in scr to 0 * [2] no set value in brr [3] [4] [5] [6] 1-bit interval elapsed? < initialization completion> [1] set the clock selection in scr. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external colck is used. [4] set the rie, tie, teie, and mpie bits. [5] set pfc of the external pin used. set rxd input during receiving and txd output during transmitting. set sck input/output according to contents set by cke1 and cke0. when cke1 and cke0 are 0 in asynchronous mode, setting the sck pin is unnecessary. outputting clocks from the sck pin starts at synchronous clock output setting. [6] wait at least one bit interval, then set the te bit or re bit in scr to 1. * at this time, the txd, rxd, and sck pins can be used. the txd pin is in a mark state during transmitting, and rxd pin is in an idle state for waiting the start bit during receiving. set data transfer format in smr set the rie, tie, teie, and mpie bits in scr set pfc of the external pin used sck, txd, rxd set te and re bits of scr to 1 set cke1 and cke0 bits in scr (te and re bits are 0) note: * in simultaneous transmit/receive operation, the te and re bits must be cleared to 0 or set to 1 simultaneously. figure 10.5 sample sci initialization flowchart
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 301 of 448 rej09b0394-0200 10.4.5 data transmission (asynchronous mode) figure 10.6 shows an example of the operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. because the txi interrupt routine writes the next transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered in which 1 is output. if the tei e bit in scr is set to 1 at this time, a tei interrupt request is generated. figure 10.7 shows a sample flowchart for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit data written to tdr and tdre flag cleared to 0 in txi interrupt processing routine tei interrupt request generated idle state (mark state) txd txi interrupt request generated txi interrupt request generated figure 10.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 302 of 448 rej09b0394-0200 no [1] yes initialization start transmission read tdre flag in ssr [2] no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 clear te bit in scr to 0; select the txd pin as an output port with the pfc tdre = 1 all data transmitted? tend = 1 break output? [1] sci initialization: set the txd pin using the pfc. after the te bit is set to 1, 1 is output for one frame, and transmission is enabled. however, data is not transmitted. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. [4] break output at the end of serial transmission: to output a break in serial transmission, first clear the port data register (dr) to 0, then clear the te bit to 0 in scr and use the pfc to select the txd pin as an output port. write transmit data to tdr and clear tdre flag in ssr to 0 figure 10.7 sample serial transmission flowchart
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 303 of 448 rej09b0394-0200 10.4.6 serial data recepti on (asynchronous mode) figure 10.8 shows an example of the operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in rs r, and checks the parity bit and stop bit. 2. if an overrun error (when reception of the next data is completed while the rdrf flag is still set to 1) occurs, the oer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error (when the stop bit is 0) is detected, the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception finishes successfully, the rdrf b it in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interrupt processing routine reads the receive data transferred to rdr before reception of the next receive data has finished, conti nuous reception can be enabled. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine rxi interrupt request generated rxd figure 10.8 example of sc i operation in r eception (example wi th 8-bit data, parity, one stop bit)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 304 of 448 rej09b0394-0200 table 10.9 shows the states of the ssr status flag s and receive data handling when a receive error is detected. if a receive error is detected, the rd rf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 10.9 shows a sample flow chart for serial data reception. table 10.9 ssr status flags and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains its state before data reception.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 305 of 448 rej09b0394-0200 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error processing (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer = 1 rdrf = 1 all data received? [1] sci initialization: set the rxd pin using the pfc. [2] [3] receive error processing and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. [4] sci status check and receive data read: read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. [5] serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. figure 10.9 sample serial reception data flowchart (1)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 306 of 448 rej09b0394-0200 [3] error processing parity error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing orer = 1 fer = 1 break? per = 1 clear re bit in scr to 0 figure 10.9 sample serial reception data flowchart (2)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 307 of 448 rej09b0394-0200 10.5 multiprocessor comm unication function use of the multiprocessor communication function en ables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communicatio n is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, the cycle is an id transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. figure 10.10 shows an example of inter-processor communication using the multiprocessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receivi ng station compares that data with its own id. the station whose id matches then receives the da ta sent next. stations whose id does not match continue to skip data until data with a 1 multiprocessor bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer to 1 are inhibited until data with a 1 multiprocessor bit is received. on reception of receive character with a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is invalid. all other bit settings are the same as those in normal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 308 of 448 rej09b0394-0200 transmitting station receiving station a (id = 01) receiving station b (id = 02) receiving station c (id = 03) receiving station d (id = 04) serial transmission line serial data id transmission cycle = receiving station specification data transmission cycle = data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa legend: mpb: multiprocessor bit figure 10.10 example of communication using multiprocessor format (transmission of data h'aa to receiving station a)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 309 of 448 rej09b0394-0200 10.5.1 multiprocessor serial data transmission figure 10.11 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no [1] yes initialization start transmission read tdre flag in ssr [2] no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 clear te bit in scr to 0; select the txd pin as an output port with the pfc tdre = 1 all data transmitted? tend = 1 break output? clear tdre flag to 0 [1] sci initialization: set the txd pin using the pfc. after the te bit is set to 1, 1 is output for one frame, and transmission is enabled. however, data is not transmitted. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. [4] break output at the end of serial transmission: to output a break in serial transmission, first clear the port data register (dr) to 0, then clear the te bit to 0 in scr and use the pfc to select the txd pin as an output port. write transmit data to tdr and set mpbt bit in ssr figure 10.11 sample multiprocessor serial transmission flowchart
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 310 of 448 rej09b0394-0200 10.5.2 multiprocessor s erial data reception figure 10.13 shows a sample flowchart for multiprocessor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bit, the receive data is tr ansferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 10.12 shows an example of sci operation for multiprocessor format reception. mpie rxd rxd rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 01 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit data (id2) start bit stop bit start bit data (data2) stop bit rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine if not this station's id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station's id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 01 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) generated idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine matches this station's id, so reception continues, and data is received in rxi interrupt processing routine mpie bit is set to 1 again id2 (b) data matches station's id data2 id1 mpie = 0 mpie = 0 figure 10.12 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 311 of 448 rej09b0394-0200 yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error processing (continued on next page) [5] no yes fer orer = 1 rdrf = 1 all data received? set mpie bit in scr to 1 [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station's id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer orer = 1 read receive data in rdr rdrf = 1 [1] sci initialization: set the rxd pin using the pfc. [2] id reception cycle: set the mpie bit in scr to 1. [3] sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station's id. if the data is not this station's id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station's id, clear the rdrf flag to 0. [4] sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. [5] receive error processing and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. figure 10.13 sample multiprocesso r serial reception flowchart (1)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 312 of 448 rej09b0394-0200 error processing yes no clear orer and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing orer = 1 fer = 1 break? clear re bit in scr to 0 [5] figure 10.13 sample multiprocesso r serial reception flowchart (2)
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 313 of 448 rej09b0394-0200 10.6 operation in clocke d synchronous mode figure 10.14 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. data is transferred in 8-bit units. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sci receives data in synchronizati on with the rising edge of the seri al clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is added. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enab ling continuous data transfer. don't care don't care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * high except in continuous transfer figure 10.14 data format in clocked synchronous communication (for lsb-first) 10.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of cke1 and cke0 bits in scr. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the clock is fixed high.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 314 of 448 rej09b0394-0200 10.6.2 sci initialization (clocked synchronous mode) before transmitting and receiving data, you should firs t clear the te and re bits in scr to 0, then initialize the sci as described in a sample flowchart in figure 10.15. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te b it is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initia lize the rdrf, per, fer, and orer flags, or the contents of rdr. wait no yes start initialization set data transfer format in smr set value in brr clear rie, tie, teie, mpie, te and re bits in scr to 0 * [2] [3] set the rie, tie, teie, and mpie bits in scr [4] [5] [6] 1-bit interval elapsed? set pfc of the external pin used sck, txd, rxd set te and re bits of scr to 1 set cke1 and cke0 bits in scr (te and re bits are 0) [1] [1] set the clock selection in scr. [2] set the data transfer format in smr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] set the rie, tie teie, and mpie bits. [5] set pfc of the external pin used. set rxd input during receiving and txd output during transmitting. set sck input/output according to contents set by cke1 and cke0. [6] wait at least one bit interval, then set the te bit or re bit in scr to 1. * at this time, the txd, rxd, and sck pins can be used. the txd pin is in a mark state during transmitting. when synchronous clock output (clock master) is set during receiving in synchronous mode, outputting clocks from the sck pin starts. note: * in simultaneous transmit and receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. figure 10.15 sample sci initialization flowchart
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 315 of 448 rej09b0394-0200 10.6.3 serial data transmission (clocked synchronous mode) figure 10.16 shows an example of sci operation for transmission in clocked synchronous mode. in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if it is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty (txi) interrupt request is generated. because the tx i interrupt routine writes the next transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the txd pin maintains the output state of the last bit. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 10.17 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (orer, fer, or per) is set to 1. make sure to clear the receive error flags to 0 be fore starting transmission. note that clearing the re bit to 0 does not clear the receive error flags.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 316 of 448 rej09b0394-0200 transfer direction bit 0 serial data synchroniza- tion clock 1 frame tdre tend bit 1 bit 0 bit 4 bit 5 bit 6 bit 7 txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt processing routine tei interrupt request generated txi interrupt request generated figure 10.16 sample sci transmission operation in clocked synchronous mode
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 317 of 448 rej09b0394-0200 no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre = 1 all data transmitted? tend = 1 [1] sci initialization: set the txd pin using the pfc. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. figure 10.17 sample serial transmission flowchart
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 318 of 448 rej09b0394-0200 10.6.4 serial data reception (clocked synchronous mode) figure 10.18 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in rsr. 2. if an overrun error (when reception of the next data is completed while the rdrf flag is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive da ta is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if reception finishes successfully, the rdrf b it in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interrupt processing routine reads the receive data transferred to rdr before reception of the next receive data has finished, conti nuous reception can be enabled. bit 7 serial data synchroniza- tion clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt processing routine eri interrupt request generated by overrun error rxi interrupt request generated figure 10.18 example of sci operation in reception
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 319 of 448 rej09b0394-0200 reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 10.19 shows a sample flowchart for serial data reception. yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error processing (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer = 1 rdrf = 1 all data received? read orer flag in ssr error processing overrun error processing clear orer flag in ssr to 0 [3] [1] sci initialization: set the rxd pin using the pfc. [2] [3] receive error processing: if a receive error occurs, read the orer flag in ssr, and after performing the appropriate error processing, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. [4] sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. [5] serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0 should be finished. figure 10.19 sample s erial reception flowchart
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 320 of 448 rej09b0394-0200 10.6.5 simultaneous serial data transmission and reception (clocked synchronous mode) figure 10.20 shows a sample flowchart for simulta neous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations after the sci initialization. to switch from transmit mode to simultaneous transmit and receive mode, after checking that the sci has finished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneously set te and re to 1 with a single instruction. to switch from receive mode to simultaneous tran smit and receive mode, after checking that the sci has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (orer, fer, and per) are cleared to 0, simultaneously set te and re to 1 with a single instruction.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 321 of 448 rej09b0394-0200 yes [1] no initialization start transmission/reception [5] error processing [3] no yes orer = 1 all data received? [2] read tdre flag in ssr no yes tdre = 1 write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf = 1 read orer flag in ssr [4] read rdrf flag in ssr [1] sci initialization: set the txd and rxd pins using the pfc. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. [3] receive error processing: if a receive error occurs, read the orer flag in ssr, and after performing the appropriate error processing, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. [4] sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. [5] serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr and clear the tdre flag to 0. note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. clear te and re bits in scr to 0 read receive data in rdr, and clear rdrf flag in ssr to 0 figure 10.20 sample flowchar t of simultaneous serial tr ansmit and receive operations
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 322 of 448 rej09b0394-0200 10.7 interrupts sources 10.7.1 interrupts in normal serial communication interface mode table 10.10 shows the interrupt sources in no rmal serial communication interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. when the rdrf flag in ssr is se t to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. a tei interrupt is generated when the tend flag is set to 1 while the teie bit is set to 1. if a tei interrupt and a txi interrupt are generated simultaneously, the txi interrupt has priority for acceptance. however, note that if the tdre and tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot branch to the tei interrupt routine later. table 10.10 sci interrupt sources channel name interrupt source interrupt flag eri_2 receive error orer, fer, per rxi_2 receive data full rdrf txi_2 transmit data empty tdre 2 tei_2 transmission end tend 3 eri_3 receive error orer, fer, per rxi_3 receive data full rdrf txi_3 transmit data empty tdre tei_3 transmission end tend
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 323 of 448 rej09b0394-0200 10.8 usage notes 10.8.1 tdr write and tdre flag the tdre bit in the serial status register (ssr) is a status flag indicating transferring of transmit data from tdr into tsr. the sci sets the tdre bit to 1 when it transfers data from tdr to tsr. data can be written to tdr regardless of the tdre bit status. if new data is written in tdr when tdre is 0, however, the old data stored in tdr will be lost because the data has not yet been transferred to ts r. before writing transmit data to tdr, be sure to check that the tdre bit is set to 1. 10.8.2 module standby mode setting sci operation can be disabled or enabled using the module standby control register. the initial setting is for sci operation to be halted. regist er access is enabled by clearing module standby mode. for details, refer to section 17, power-down modes. 10.8.3 break detection and processing (asynchronous mode only) when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the per flag may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 10.8.4 sending a break signal (asynchronous mode only) the txd pin becomes of the i/o port general i/o pin with the i/o direction and level determined by the port data register (dr) and the port i/o register (ior) of the pin function controller (pfc). these conditions allow break signals to be sent. the dr value is substituted for the marking status until the pfc is set. consequently, the output port is set to initially output a 1. to send a break in serial transmission, first clear the dr to 0, then establish the txd pin as an output port using the pfc. when the te bit is cleared to 0, the transmission section is initialized regardless of the present transmission status.
10. serial communication interface (sci) rev.2.00 sep. 27, 2007 page 324 of 448 rej09b0394-0200 10.8.5 receive error flags and transmit op erations (clocked sync hronous mode only) transmission cannot be started when a receive error fl ag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that recei ve error flags cannot be cleared to 0 even if the re bit is cleared to 0. 10.8.6 cautions on clocked synchronous external clock mode 1. set te = re = 1 only when external clock sck is 1. 2. do not set te = re = 1 until at least four p clocks after external clock sck has changed from 0 to 1. 3. when receiving, rdrf is 1 when re is cleared to 0 after 2.5?3.5 p clocks from the rising edge of the rxd d7 bit sck input, but copying to rdr is not possible. 10.8.7 caution on clocked synchronous internal clock mode when receiving, rdrf is 1 when re is cleared to 0 after 1.5 p clocks from the rising edge of the rxd d7 bit sck output, but copying to rdr is not possible.
11. a/d converter adcms20b_010020030200 rev.2.00 sep. 27, 2007 page 325 of 448 rej09b0394-0200 section 11 a/d converter this lsi includes a successive approximation type 10-bit a/d converter. the block diagram of the a/d converter is shown in figure 11.1. 11.1 features ? 10-bit resolution ? input channels ? 8 channels (two independent a/d conversion modules) ? conversion time: 6.7 s per channel (at p = 20-mhz operation) 5.4 s per channel (at p = 25-mhz operation) ? three operating modes ? single mode: single-channel a/d conversion ? continuous scan mode: 1 to 4 channels ? single-cycle scan mode: 1 to 4 channels ? data registers ? conversion results are held in a 16-bit data register for each channel ? sample and hold function ? three methods for conversion start ? software ? conversion start trigger from mu ltifunction timer pulse unit (mtu) ? external trigger signal ? interrupt source ? an a/d conversion end interrupt request (adi) can be generated ? module standby mode can be set
11. a/d converter rev.2.00 sep. 27, 2007 page 326 of 448 rej09b0394-0200 module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit adi interrupt signal bus interface successive approximations register multiplexer addr8 ? ? ? addr15 adcsr adcr adtsr an8 ? ? ? ? ? ? an15 legend: adcr: a/d control register adcsr: a/d control/status register adtsr: a/d trigger select register addr8?addr15: a/d data register 8 to 15 note: the register number corresponds to the channel number of the module. adtrg conversion start trigger from mtu p /4 p /8 p /16 p /32 av cc av ss figure 11.1 block diagram of a/d converter (for one module)
11. a/d converter rev.2.00 sep. 27, 2007 page 327 of 448 rej09b0394-0200 11.2 input/output pins table 11.1 summarizes the input pins used by the a/d converter. this lsi has two a/d conversion modules, each of which can be operate d independently. the input channels are divided into four channel sets. table 11.1 pin configuration module type pin name i/o function common av cc input analog block power supply and reference voltage av ss input analog block ground and reference voltage adtrg input a/d external trigger input pin an8 input analog input pin 8 group 1 a/d module 0 (a/d0) an9 input analog input pin 9 an10 input analog input pin 10 an11 input analog input pin 11 an12 input analog input pin 12 group 1 a/d module 1 (a/d1) an13 input analog input pin 13 an14 input analog input pin 14 an15 input analog input pin 15 note: the connected a/d module differs for each pin. the control registers of each module must be set.
11. a/d converter rev.2.00 sep. 27, 2007 page 328 of 448 rej09b0394-0200 11.3 register descriptions the a/d converter has the following registers. for details on register addresses and register states in each operating mode, refer to s ection 18, list of registers. ? a/d data register 8 (h/l) (addr8) ? a/d data register 9 (h/l) (addr9) ? a/d data register 10 (h/l) (addr10) ? a/d data register 11 (h/l) (addr11) ? a/d data register 12 (h/l) (addr12) ? a/d data register 13 (h/l) (addr13) ? a/d data register 14 (h/l) (addr14) ? a/d data register 15 (h/l) (addr15) ? a/d control/status register_0 (adcsr_0) ? a/d control/status register_1 (adcsr_1) ? a/d control register_0 (adcr_0) ? a/d control register_1 (adcr_1) ? a/d trigger select register (adtsr) 11.3.1 a/d data registers 8 to 15 (addr8 to addr15) addr are 16-bit read-only registers. the conversi on result for each analog input channel is stored in addr with the corresponding number. (for exampl e, the conversion result of an8 is stored in addr8.) the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converte r is 8 bits wide. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register contents are transferred from the addr when the upper byte data is read. when reading addr, read only the upper byte, or read in word unit. addr are initialized to h'0000.
11. a/d converter rev.2.00 sep. 27, 2007 page 329 of 448 rej09b0394-0200 11.3.2 a/d control/status registers_0 and _1 (adcsr_0 and adcsr_1) adcsr for each module controls a/d conversion operations. bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends on all specified channels in scan mode [clearing condition] ? when 0 is written after reading adf = 1 6 adie 0 r/w a/d interrupt enable the a/d conversion end interrupt (adi) request is enabled when 1 is set. when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. 5 4 adm1 adm0 0 0 r/w r/w a/d mode 1 and 0 select the a/d conversion mode. 00: single mode 01: 4-channel scan mode 10: setting prohibited 11: setting prohibited when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. 3 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 2 1 0 ch2 ch1 ch0 0 0 0 r/w r/w r/w channel select 2 to 0 select analog input channels. see table 11.2. when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. note: * only 0 can be written to clear the flag.
11. a/d converter rev.2.00 sep. 27, 2007 page 330 of 448 rej09b0394-0200 table 11.2 channel select list analog input channels bit 2 bit 1 bit 0 single mode 4-channel scan mode * ch2 ch1 ch0 a/d0 a/d1 a/d0 a/d1 1 0 0 an8 an12 an8 an12 1 an9 an13 an8, an9 an12, an13 1 0 an10 an14 an8 to an10 an12 to an14 1 an11 an15 an8 to an11 an12 to an15 note: * continuous scan mode or single-cycle scan mode can be selected with the adcs bit. 11.3.3 a/d control registers_0 and _1 (adcr_0 and adcr_1) adcr for each module controls a/d conversion starte d by an external trigger signal and selects the operating clock. bit bit name initial value r/w description 7 trge 0 r/w trigger enable enables or disables triggering of a/d conversion by adtrg or an mtu trigger. 0: a/d conversion triggering is disabled 1: a/d conversion triggering is enabled 6 5 cks1 cks0 0 0 r/w r/w clock select 0 and 1 select the a/d conversion time. 00: p /32 01: p /16 10: p /8 11: p /4 when changing the a/d conversion time, first clear the adst bit in the a/d control registers (adcr) to 0. cks [1,0] = b'11 can be set while p 25 mhz.
11. a/d converter rev.2.00 sep. 27, 2007 page 331 of 448 rej09b0394-0200 bit bit name initial value r/w description 4 adst 0 r/w a/d start starts or stops a/d conversion. when this bit is set to 1, a/d conversion is started. when this bit is cleared to 0, a/d conversion is stopped and the a/d converter enters the idle state. in single or single-cycle scan mode, this bit is automatically cleared to 0 when a/d conversion ends on the selected single channel. in continuous scan mode, a/d conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode, or module standby mode. 3 adcs 0 r/w a/d continuous scan selects either single-cycle scan or continuous scan in scan mode. this bit is valid only when scan mode is selected. 0: single-cycle scan 1: continuous scan when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. 2 to 0 ? all 1 r reserved these bits are always read as 1. the write value should always be 1.
11. a/d converter rev.2.00 sep. 27, 2007 page 332 of 448 rej09b0394-0200 11.3.4 a/d trigger select register (adtsr) adtsr enables an a/d conversion started by an external trigger signal. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 trg1s1 trg1s0 0 0 r/w r/w ad trigger 1 select 1 and 0 enable the start of a/d conversion by a/d1 with a trigger signal. 00: a/d conversion start by external trigger pin ( adtrg ) or mtu trigger is enabled 01: a/d conversion start by external trigger pin ( adtrg ) is enabled 10: a/d conversion start by mtu trigger is enabled 11: setting prohibited when changing the operating mode, first clear the trge and adst bits in the a/d control registers (adcr) to 0. 1 0 trg0s1 trg0s0 0 0 r/w r/w ad trigger 0 select 1 and 0 enable the start of a/d conversion by a/d0 with a trigger signal. 00: a/d conversion start by external trigger pin ( adtrg ) or mtu trigger is enabled 01: a/d conversion start by external trigger pin ( adtrg ) is enabled 10: a/d conversion start by mtu trigger is enabled 11: setting prohibited when changing the operating mode, first clear the trge and adst bits in the a/d control registers (adcr) to 0.
11. a/d converter rev.2.00 sep. 27, 2007 page 333 of 448 rej09b0394-0200 11.4 operation the a/d converter operates by successive approxi mation with 10-bit resolution. it has two operating modes; single mode and scan mode. there are two kinds of scan mode: continuous mode and single-cycle mode. when changing the oper ating mode or analog input channel, in order to prevent incorrect operation, first clear the adst bit to 0 in adcr. the adst bit can be set at the same time when the operating mode or analog input channel is changed. 11.4.1 single mode in single mode, a/d conversion is to be performed only once on the specified single channel. the operations are as follows. 1. a/d conversion is started when the adst bit in adcr is set to 1, according to software, mtu, or external trigger input. 2. when a/d conversion is completed, the result is transferred to the a/d data register corresponding to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the idle state. when the adst bit is cleared to 0 during a/d conversion, a/d conversion stops and the a/d converter enters the idle state. 11.4.2 continuous scan mode in continuous scan mode, a/d conversion is to be performed sequentially on the specified channels (four channels maximum). the operations are as follows. 1. when the adst bit in adcr is set to 1 by software, mtu, or external trigger input, a/d conversion starts on the channel with the lowest number in the group (an8, an9, ..., an11). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. conversion of the first channel in the group starts again. 4. steps 2 to 3 are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and the a/d converter enters the idle state.
11. a/d converter rev.2.00 sep. 27, 2007 page 334 of 448 rej09b0394-0200 adst set * 1 clear * 1 clear * 1 a/d continuous conversion channel 8 (an8) operation condition channel 9 (an9) operation condition channel 10 (an10) operation condition channel 11 (an11) operation condition adf addr8 addr9 addr10 addr11 notes: indicates command execution by the software 1. 2. data is ignored during conversion * 2 a/d conversion time conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby a/d conversion (1) a/d conversion (2) conversion standby conversion standby transfer a/d conversion result (1) a/d conversion result (4) a/d conversion result (2) a/d conversion result (3) a/d conversion (3) a/d conversion (5) a/d conversion (4) figure 11.2 operation exampl e in continuous scan mode (three channels selected) (an8 to an10)
11. a/d converter rev.2.00 sep. 27, 2007 page 335 of 448 rej09b0394-0200 11.4.3 single-cycle scan mode in single-cycle scan mode, a/d conversion is to be performed once on the specified channels (four channels maximum). operations are as follows. 1. when the adst bit in adcr is set to 1 by a software, mtu, or external trigger input, a/d conversion starts on the channel with the lowest number in the group (an8, an9, ..., an11). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. 4. after a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the idle state. when the adst bit is cleared to 0 during a/d conversion, a/d conversion stops and the a/d converter enters the idle state. 11.4.4 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit for each module. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit in adcr is set to 1, then starts conversion. figure 11.3 shows the a/d conversion timing. table 11.3 shows the a/d conversion time. as indicated in figure 11.3, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcr. the total conversion time therefore varies within the ranges indicated in table 11.3. in scan mode, the values given in table 11.3 apply to the first conversion time. the values given in table 11.4 apply to the second and subsequent conversions.
11. a/d converter rev.2.00 sep. 27, 2007 page 336 of 448 rej09b0394-0200 p a/d converter a/d conversion a/d conversion start delay time(t d ) a/d conversion time (t conv ) analog input sampling time(t spl ) adst write timing end of a/d conversion adf address write cycle a/d synchronization time (3 states) (up to 59 states) internal write signal analog input sampling signal idle state sample-and-hold figure 11.3 a/d conversion timing table 11.3 a/d conversion time (single mode) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min typ max min typ max mi n typ max min typ max a/d conversion start delay time t d 31 ? 62 15 ? 30 7 ? 14 3 ? 6 input sampling time t spl ? 256 ? ? 128 ? ? 64 ? ? 32 ? a/d conversion time t conv 1024 ? 1055 515 ? 530 259 ? 266 131 ? 134 note: all values represent the number of states for p .
11. a/d converter rev.2.00 sep. 27, 2007 page 337 of 448 rej09b0394-0200 table 11.4 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 1024 (fixed) 0 1 512 (fixed) 0 256 (fixed) 1 1 128 (fixed) 11.4.5 a/d converter activation by mtu the a/d converter can be independently activated by an a/d conversion request from the interval timer of the mtu. to activate the a/d converter by th e mtu, set the a/d trigger select register (adtsr). when the trgs1 and trgs0 bits in adtsr are set to 00 or 01, if an a/d conversion request from the interval timer of the mtu occurs, the adst bit in adcr is automatically set to 1. the timing from setting of the adst bit until the start of a/d conversion is the same as when 1 is written to the adst bit by software. 11.4.6 external trigger input timing a/d conversion can be externally triggered. when the trgs0 and trgs1 bits are set to 00 or 01 in adtsr, external trigger input is enabled at the adtrg pin. a falling edge of the adtrg pin sets the adst bit to 1 in adcr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the adst bit has been set to 1 by software. figure 11.4 shows the timing. ck adtrg external trigger signal adst a/d conversion figure 11.4 external trigger input timing
11. a/d converter rev.2.00 sep. 27, 2007 page 338 of 448 rej09b0394-0200 11.5 interrupt sources the a/d converter generates an a/d conversion end interrupt (adi) upon the completion of a/d conversion. adi interrupt requests are enabled when the adie bit is set to 1 while the adf bit in adcsr is set to 1 after a/d conversion is completed. the a/d converter can generate an a/d conversion end interrupt request. the adi interrupt can be enabled by setting the adie bit in the a/d control/status register (adcsr) to 1, or disabled by clearing the adie bit to 0. table 11.5 a/d converter interrupt source name interrupt source interrupt source flag adi a/d conversion completed adf 11.6 definitions of a/d conversion accuracy this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 11.5). ? offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'00) to b'0000000001 (h'01) (see figure 11.6). ? full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 11.6). ? nonlinearity error the error with respect to the ideal a/d conversion characteristic between zero voltage and full- scale voltage. does not include offset error, full-scale error, or quantization error (see figure 11.6). ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error.
11. a/d converter rev.2.00 sep. 27, 2007 page 339 of 448 rej09b0394-0200 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error digital output ideal a/d conversion characteristic analog input voltage figure 11.5 definitions of a/d conversio n accuracy fs digital output ideal a/d conversion characteristic nonlinearity error analog input voltage offset error actual a/d conversion characteristic full-scale error figure 11.6 definitions of a/d conversio n accuracy
11. a/d converter rev.2.00 sep. 27, 2007 page 340 of 448 rej09b0394-0200 11.7 usage notes 11.7.1 module standby mode setting operation of the a/d converter can be disabled or enabled using the module standby control register. the initial setting is for operation of the a/d converter to be halted. register access is enabled by clearing module standby mode. for details, refer to section 17, power-down modes. 11.7.2 permissible sign al source impedance this lsi's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less, or 3 k or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k or 3 k , charging may be insufficient and it may not be possible to guara ntee a/d conversion accuracy. however, for a/d conversion in single mode with a large capac itance provided externally , the input load will essentially comprise only the internal input resistance of 10 k , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ s or greater) (see figure 11.7). when converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 11.7.3 influences on absolute accuracy adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute accuracy. be su re to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circuits do not communicate with digital signals on the mounting board (i.e., acting as antennas). 20 pf 10 k c in = 15 pf sensor output impedance of up to 3 k or up to 1 k this lsi low-pass filter c to 0.1 f sensor input a/d converter equivalent circuit figure 11.7 example of analog input circuit
11. a/d converter rev.2.00 sep. 27, 2007 page 341 of 448 rej09b0394-0200 11.7.4 range of analog power supply and other pin settings if the conditions below are not met, the reliability of the device may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss van avcc. ? relationship between avcc, avss and vcc, vss set avss = vss for the relationship between av cc, avss and vcc, vss. if the a/d converter is not used, the avcc and avss pins must not be left open. 11.7.5 notes on board design in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an8 to an15), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable ground (vss) on the board. 11.7.6 notes on noise countermeasures a protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (an8 to an15), between avcc and avss, as shown in figure 11.8. also, the bypass capacitors connect ed to avcc and the filte r capacitor connected to an8 to an15 must be connected to avss. if a filter capacitor is connected, th e input currents at the analog input pins (an8 to an15) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the curre nt input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding circuit constants.
11. a/d converter rev.2.00 sep. 27, 2007 page 342 of 448 rej09b0394-0200 avcc * 1 an8 to an15 avss r in * 2 100 0.1 f 0.01 f 10 f notes: values are reference values. 1. 2. r in : input impedance figure 11.8 example of analog input protection circuit table 11.6 analog pin specifications item min max unit measurement condition analog input capacitance ? 20 pf permissible signal source impedance ? 3 k p 20 mhz ? 1 k 20 mhz < p 25 mhz 20 pf an8 to an15 note: values are reference values. 10 k to a/d converter figure 11.9 analog input pin equivalent circuit
12. compare match timer (cmt) timcmt0a_010020030200 rev.2.00 sep. 27, 2007 page 343 of 448 rej09b0394-0200 section 12 compare match timer (cmt) this lsi has an on-chip compare match timer (cmt) comprising two 16-bit timer channels. the cmt has 16-bit counters and can generate interrupts at set intervals. 12.1 features ? four types of counter input clock can be selected ? one of four internal clocks (p /8, p /32, p /128, p /512) can be selected independently for each channel. ? interrupt sources ? a compare match interrupt can be reque sted independently for each channel. ? module standby mode can be set figure 12.1 shows a block diagram of the cmt. control circuit clock selection module bus control circuit clock selection cmi0 cmi1 p /8 p /32 p /128 p /512 p /8 p /32 p /128 p /512 bus interface internal bus legend: cmstr: compare match timer start register cmcsr: compare match timer control/status register cmcor: compare match timer constant register cmcnt: compare match timer counter cmi: compare match interrupt comparator cmstr cmt cmcsr0 cmcor0 comparator cmcnt0 cmcsr1 cmcor1 cmcnt1 figure 12.1 cmt block diagram
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 344 of 448 rej09b0394-0200 12.2 register descriptions the cmt has the following registers. for details on register addresses and register states during each processing, refer to section 18, list of registers. ? compare match timer start register (cmstr) ? compare match timer control/status register_0 (cmcsr_0) ? compare match timer counter_0 (cmcnt_0) ? compare match timer constant register_0 (cmcor_0) ? compare match timer control/status register_1 (cmcsr_1) ? compare match timer counter_1 (cmcnt_1) ? compare match timer constant register_1 (cmcor_1) 12.2.1 compare match timer start register (cmstr) cmstr is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (cmcnt). bit bit name initial value r/w description 15 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 str1 0 r/w count start 1 this bit selects whether to operate or halt compare match timer counter_1. 0: cmcnt_1 count operation halted 1: cmcnt_1 count operation 0 str0 0 r/w count start 0 this bit selects whether to operate or halt compare match timer counter_0. 0: cmcnt_0 count operation halted 1: cmcnt_0 count operation
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 345 of 448 rej09b0394-0200 12.2.2 compare match timer control/status register_0 and _1 (cmcsr_0, cmcsr_1) cmcsr is a 16-bit register that indicates th e occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 cmf 0 r/(w) * compare match flag this flag indicates whether or not the cmcnt and cmcor values have matched. 0: cmcnt and cmcor values have not matched [clearing condition] ? write 0 to cmf after reading 1 from it 1: cmcnt and cmcor values have matched 6 cmie 0 r/w compare match interrupt enable this bit selects whether to enable or disable a compare match interrupt (cmi) when the cmcnt and cmcor values have matched (cmf = 1). 0: compare match interrupt (cmi) disabled 1: compare match interrupt (cmi) enabled 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w these bits select the clock input to cmcnt among the four internal clocks obtained by dividing the peripheral clock (p ). when the str bit in cmstr is set to 1, cmcnt begins incrementing with the clock selected by cks1 and cks0. 00: p /8 01: p /32 10: p /128 11: p /512 note: * only 0 can be written, for flag clearing.
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 346 of 448 rej09b0394-0200 12.2.3 compare match timer counter_0 and _1 (cmcnt_0, cmcnt_1) cmcnt is a 16-bit register used as an up-counter for generating interrupt requests. cmcnt is initialized to h'0000. 12.2.4 compare match timer constant register_0 and _1 (cmcor_0, cmcor_1) cmcor is a 16-bit register that sets the period for compare match with cmcnt. cmcor is initialized to h'ffff. 12.3 operation 12.3.1 cyclic count operation when an internal clock is selected with the cks1, cks0 bits in cmcsr and the str bit in cmstr is set to 1, cmcnt begins incrementing with the selected clock. when the cmcnt counter value matches that of the compare match constant register (cmcor), the cmcnt counter is cleared to h'0000 and the cmf flag in cmcsr is set to 1. if the cmie bit in cmcsr is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt counter begins counting up again from h'0000. figure 12.2 shows the compare match counter operation. cmcnt value cmcor h'0000 counter cleared by cmcor compare match time figure 12.2 counter operation
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 347 of 448 rej09b0394-0200 12.3.2 cmcnt count timing one of four internal clocks (p /8, p /32, p /128, p /512) obtained by dividing the peripheral clock (p ) can be selected by the cks1 and cks0 bits in cmcsr. figure 12.3 shows the timing. p internal clock cmcnt input clock cmcnt n-1 n n+1 figure 12.3 count timing 12.4 interrupts 12.4.1 interrupt sources the cmt has a compare match inte rrupt for each channel, with independent vector addresses allocated to each of them . the corresponding interrupt reques t is output when interrupt request flag cmf is set to 1 and interrupt enable bit cmie has also been set to 1. when activating cpu interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. see section 6, interrupt controller (intc), for details. 12.4.2 compare match flag set timing the cmf bit in cmcsr is set to 1 by the compare match signal generated when the cmcor register and the cmcnt counter match. the comp are match signal is generated upon the final state of the match (timing at which the cmcnt counter matching count value is updated). consequently, after the cmcor register and the cmcnt counter match, a compare match signal will not be generated until a cmcnt counter input clock occurs. figure 12.4 shows the cmf bit set timing.
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 348 of 448 rej09b0394-0200 p cmcnt input clock cmcnt cmcor n0 n compare match signal cmf cmi figure 12.4 cmf set timing 12.4.3 compare match flag clear timing the cmf bit in cmcsr is cleared by writing 0 to it after reading 1. figure 12.5 shows the timing when the cmf bit is cleared by the cpu. t1 t2 cmcsr write cycle p cmf figure 12.5 timing of cmf clear by cpu
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 349 of 448 rej09b0394-0200 12.5 usage notes 12.5.1 contention between cm cnt write and compare match if a compare match signal is generated during the t2 state of the cmcnt counter write cycle, the cmcnt counter clear has priority, so the write to the cmcnt counter is not performed. figure 12.6 shows the timing. p t1 t2 address cmcnt internal write signal cmcnt n h'0000 compare match signal cmcnt write cycle figure 12.6 cmcnt write and compare match contention
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 350 of 448 rej09b0394-0200 12.5.2 contention between cmcnt word write and incrementation if an increment occurs during the t2 state of th e cmcnt counter word write cycle, the counter write has priority, so no increment occurs. figure 12.7 shows the timing. p t1 t2 address cmcnt internal write signal cmcnt nm cmcnt write data cmcnt input clock cmcnt write cycle figure 12.7 cmcnt word wr ite and increment contention
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 351 of 448 rej09b0394-0200 12.5.3 contention between cmcnt byte write and incrementation if an increment occurs during the t2 state of th e cmcnt byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. the byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. figure 12.8 shows the timing when an increment occurs during the t2 state of the cmcnth write cycle. p t1 t2 address cmcnth internal write signal cmcnth n m cmcntl xx cmcnth write data cmcnt input clock cmcnt write cycle figure 12.8 cmcnt byte wr ite and increment contention
12. compare match timer (cmt) rev.2.00 sep. 27, 2007 page 352 of 448 rej09b0394-0200
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 353 of 448 rej09b0394-0200 section 13 pin function controller (pfc) the pin function controller (pfc) is composed of those registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. tables 13.1 to 13.5 list the multiplexed pins of this lsi. tables 13.6 lists the pin functions in each operating mode. table 13.1 multiplexed pins (port a) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (related module) function 6 (related module) function 7 (related module) function 8 (related module) a pa0 i/o (port) ? ? ? ? poe0 input (port) rxd2 input (sci) ? pa1 i/o (port) ? ? ? ? poe1 input (port) txd2 output (sci) ? pa2 i/o (port) ? ? irq0 input (intc) ? ? sck2 i/o (sci) ? pa3 i/o (port) ? ? ? ? ? rxd3 input (sci) ? pa4 i/o (port) ? ? ? ? ? txd3 output (sci) ? pa5 i/o (port) ? ? irq1 input (intc) ? ? sck3 i/o (sci) ? pa6 i/o (port) tclka input (mtu) ? ? ? rxd2 input (sci) ? ? pa7 i/o (port) tclkb input (mtu) ? ? ? txd2 output (sci) ? ? pa8 i/o (port) tclkc input (mtu) ? ? ? rxd3 input (sci) ? ? pa9 i/o (port) tclkd input (mtu) ? ? ? txd3 output (sci) ? ? pa10 i/o (port) ? ? ? ? sck2 i/o (sci) ? ? pa11 i/o (port) ? adtrg input (a/d) ? ? sck3 i/o (sci) ? ? pa12 i/o (port) ? ? ? ? ? ? ? pa13 i/o (port) ? ? ? ? ? ? ?
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 354 of 448 rej09b0394-0200 port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (related module) function 6 (related module) function 7 (related module) function 8 (related module) a pa14 i/o (port) ? ? ? ? ? ? ? pa15 i/o (port) ? ? ? ? ? ? ? table 13.2 multiplexed pins (port b) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) b pb2 i/o (port) irq0 input (intc) poe0 input (port) ? pb3 i/o (port) irq1 input (intc) poe1 input (port) ? pb4 i/o (port) irq2 input (intc) poe2 input (port) ? pb5 i/o (port) irq3 input (intc) poe3 input (port) ?
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 355 of 448 rej09b0394-0200 table 13.3 multiplexed pins (port e) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) e pe0 i/o (port) tioc0a i/o (mtu) ? ? pe1 i/o (port) tioc0b i/o (mtu) ? ? pe2 i/o (port) tioc0c i/o (mtu) ? ? pe3 i/o (port) tioc0d i/o (mtu) ? ? pe4 i/o (port) tioc1a i/o (mtu) rxd3 input (sci) ? pe5 i/o (port) tioc1b i/o (mtu) txd3 output (sci) ? pe6 i/o (port) tioc2a i/o (mtu) sck3 i/o (sci) ? pe7 i/o (port) tioc2b i/o (mtu) ? ? pe8 i/o (port) tioc3a i/o (mtu) ? ? pe9 i/o (port) tioc3b i/o (mtu) ? ? pe10 i/o (port) tioc3c i/o (mtu) ? ? pe11 i/o (port) tioc3d i/o (mtu) ? ? pe12 i/o (port) tioc4a i/o (mtu) ? ? pe13 i/o (port) tioc4b i/o (mtu) mres input (intc) ? pe14 i/o (port) tioc4c i/o (mtu) ? ? pe15 i/o (port) tioc4d i/o (mtu) ? irqout output (intc) pe16 i/o (port) ? ? ? pe17 i/o (port) ? ? ? pe18 i/o (port) ? ? ? pe19 i/o (port) ? ? ? pe20 i/o (port) ? ? ? pe21 i/o (port) ? ? ?
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 356 of 448 rej09b0394-0200 table 13.4 multiplexed pins (port f) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) f pf8 input (port) an8 input (a/d0) ? ? pf9 input (port) an9 input (a/d0) ? ? pf10 input (port) an10 input (a/d0) ? ? pf11 input (port) an11 input (a/d0) ? ? pf12 input (port) an12 input (a/d1) ? ? pf13 input (port) an13 input (a/d1) ? ? pf14 input (port) an14 input (a/d1) ? ? pf15 input (port) an15 input (a/d1) ? ? table 13.5 multiplexed pins (port g) port function 1 (related module) g pg0 input (port) pg1 input (port) pg2 input (port) pg3 input (port)
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 357 of 448 rej09b0394-0200 table 13.6 pin functions in each operating mode pin name single chip mode pin no. initial function pfc selected function possibilities 11, 43, 66 vcc vcc 9, 24, 41, 64 vss vss 22, 62 vcl vcl 27, 38 avcc avcc 25, 40 avss avss 1 pe2 pe2/tioc0c 2 pe3 pe3/tioc0d 3 pe4 pe4/tioc1a/rxd3 4 pe5 pe5/tioc1b/txd3 5 pe6 pe6/tioc2a/sck3 6 pe7 pe7/tioc2b 7 pe8 pe8/tioc3a 8 pe9 pe9/tioc3b 10 pe10 pe10/tioc3c 12 pe11 pe11/tioc3d 13 pe12 pe12/tioc4a 14 pe13 pe13/tioc4b/ mres 15 pe14 pe14/tioc4c 16 pe15 pe15/tioc4d/ irqout 17 pe16 pe16 18 pe17 pe17 19 pe18 pe18 20 pe19 pe19 21 pe20 pe20 23 pe21 pe21 26 pf15/an15 pf15/an15 28 pf14/an14 pf14/an14 29 pf13/an13 pf13/an13 30 pf12/an12 pf12/an12 31 pg3 pg3
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 358 of 448 rej09b0394-0200 pin name single chip mode pin no. initial function pfc selected function possibilities 32 pg2 pg2 33 pg1 pg1 34 pg0 pg0 35 pf11/an11 pf11/an11 36 pf10/an10 pf10/an10 37 pf9/an9 pf9/an9 39 pf8/an8 pf8/an8 42 pb5 pb5/ irq3 / poe3 44 pb4 pb4/ irq2 / poe2 45 pb3 pb3/ irq1 / poe1 46 pb2 pb2/ irq0 / poe0 47 pa15 pa15 48 pa14 pa14 49 pa13 pa13 50 pa12 pa12 51 pa11 pa11/ adtrg /sck3 52 pa10 pa10/sck2 53 pa9 pa9/tclkd/txd3 54 pa8 pa8/tclkc/rxd3 55 pa7 pa7/tclkb/txd2 56 pa6 pa6/tclka/rxd2 57 pa5 pa5/ irq1 /sck3 58 pa4 pa4/txd3 59 pa3 pa3/rxd3 60 pa2 pa2/ irq0 /sck2 61 pa1 pa1/ poe1 /txd2 63 pa0 pa0/ poe0 /rxd2 65 fwp fwp 67 res res 68 nmi nmi 69 md3 md3
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 359 of 448 rej09b0394-0200 pin name single chip mode pin no. initial function pfc selected function possibilities 70 md2 md2 71 md1 md1 72 md0 md0 73 extal extal 74 xtal xtal 75 pllvcl pllvcl 76 pllcap pllcap 77 pllvss pllvss 78 wdtovf wdtovf 79 pe0 pe0/tioc0a 80 pe1 pe1/tioc0b note: in single chip mode, do not set functions other than those that can be set by pfc listed in this table.
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 360 of 448 rej09b0394-0200 13.1 register descriptions the pfc has the following registers. for details on the addresses of the registers and their states during each process, see section 18, list of registers. ? port a i/o register l (paiorl) ? port a control register l3 (pacrl3) ? port a control register l2 (pacrl2) ? port a control register l1 (pacrl1) ? port b i/o register (pbior) ? port b control register 1 (pbcr1) ? port b control register 2 (pbcr2) ? port e i/o register h (peiorh) ? port e i/o register l (peiorl) ? port e control register h (pecrh) ? port e control register l1 (pecrl1) ? port e control register l2 (pecrl2) 13.1.1 port a i/o register l (paiorl) paiorl is a 16-bit readable/writable register that is used to set the pins on port a as inputs or outputs. bits pa15ior to pa0ior correspond to pins pa15 to pa0 (names of multiplexed pins are here given as port names and pin numbers alone). paiorl is enabled when the port a pins are functioning as general-purpose inputs/outputs (pa15 to pa0), and sck2 and sck3 pins are functioning as inputs/outputs of sci. in other states, paiorl is disabled. a given pin on port a will be an output pin if the corresponding bit in paiorl is set to 1, and an input pin if the bit is cleared to 0. paiorl is initialized to h'0000.
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 361 of 448 rej09b0394-0200 13.1.2 port a control registers l3 to l1 (pacrl3 to pacrl1) pacrl3 to pacrl1 are 16-bit readable/writable regi sters that are used to select the functions of the multiplexed pins on port a. port a control registers l3 to l1 (pacrl3 to pacrl1) register bit bit name initial value r/w description pacrl3 pacrl1 pacrl1 15 15 14 pa15md2 pa15md1 pa15md0 0 0 0 r/w r/w r/w pa15 mode select the function of the pa15 pin. 000: pa15 i/o (port) 011: setting prohibited 001: setting prohibited 1xx: setting prohibited 010: setting prohibited pacrl3 pacrl1 pacrl1 14 13 12 pa14md2 pa14md1 pa14md0 0 0 0 r/w r/w r/w pa14 mode select the function of the pa14 pin. 000: pa14 i/o (port) 011: setting prohibited 001: setting prohibited 1xx: setting prohibited 010: setting prohibited pacrl3 pacrl1 pacrl1 13 11 10 pa13md2 pa13md1 pa13md0 0 0 0 r/w r/w r/w pa13 mode select the function of the pa13 pin. 000: pa13 i/o (port) 011: setting prohibited 001: setting prohibited 1xx: setting prohibited 010: setting prohibited pacrl3 pacrl1 pacrl1 12 9 8 pa12md2 pa12md1 pa12md0 0 0 0 r/w r/w r/w pa12 mode select the function of the pa12 pin. 000: pa12 i/o (port) 011: setting prohibited 001: setting prohibited 1xx: setting prohibited 010: setting prohibited pacrl3 pacrl1 pacrl1 11 7 6 pa11md2 pa11md1 pa11md0 0 0 0 r/w r/w r/w pa11 mode select the function of the pa11/ adtrg /sck3 pin. 000: pa11 i/o (port) 100: setting prohibited 001: setting prohibited 101: sck3 i/o (sci) 010: adtrg input (a/d) 110: setting prohibited 011: setting prohibited 111: setting prohibited
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 362 of 448 rej09b0394-0200 register bit bit name initial value r/w description pacrl3 pacrl1 pacrl1 10 5 4 pa10md2 pa10md1 pa10md0 0 0 0 r/w r/w r/w pa10 mode select the function of the pa10/sck2 pin. 000: pa10 i/o (port) 100: setting prohibited 001: setting prohibited 101: sck2 i/o (sci) 010: setting prohibited 110: setting prohibited 011: setting prohibited 111: setting prohibited pacrl3 pacrl1 pacrl1 9 3 2 pa9md2 pa9md1 pa9md0 0 0 0 r/w r/w r/w pa9 mode select the function of the pa9/tclkd/txd3 pin. 000: pa9 i/o (port) 100: setting prohibited 001: tclkd input (mtu) 101: txd3 output (sci) 010: setting prohibited 110: setting prohibited 011: setting prohibited 111: setting prohibited pacrl3 pacrl1 pacrl1 8 1 0 pa8md2 pa8md1 pa8md0 0 0 0 r/w r/w r/w pa8 mode select the function of the pa8/tclkc/rxd3 pin. 000: pa8 i/o (port) 100: setting prohibited 001: tclkc input (mtu) 101: rxd3 input (sci) 010: setting prohibited 110: setting prohibited 011: setting prohibited 111: setting prohibited pacrl3 pacrl2 pacrl2 7 15 14 pa7md2 pa7md1 pa7md0 0 0 0 r/w r/w r/w pa7 mode select the function of the pa7/tclkb/txd2 pin. 000: pa7 i/o (port) 100: setting prohibited 001: tclkb input (mtu) 101: txd2 output (sci) 010: setting prohibited 110: setting prohibited 011: setting prohibited 111: setting prohibited pacrl3 pacrl2 pacrl2 6 13 12 pa6md2 pa6md1 pa6md0 0 0 0 r/w r/w r/w pa6 mode select the function of the pa6/tclka/rxd2 pin. 000: pa6 i/o (port) 100: setting prohibited 001: tclka input (mtu) 101: rxd2 input (sci) 010: setting prohibited 110: setting prohibited 011: setting prohibited 111: setting prohibited pacrl3 pacrl2 pacrl2 5 11 10 pa5md2 pa5md1 pa5md0 0 0 0 r/w r/w r/w pa5 mode select the function of the pa5/ irq1 /sck3 pin. 000: pa5 i/o (port) 100: setting prohibited 001: setting prohibited 101: setting prohibited 010: setting prohibited 110: sck3 i/o (sci) 011: irq1 input (intc) 111: setting prohibited
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 363 of 448 rej09b0394-0200 register bit bit name initial value r/w description pacrl3 pacrl2 pacrl2 4 9 8 pa4md2 pa4md1 pa4md0 0 0 0 r/w r/w r/w pa4 mode select the function of the pa4/txd3 pin. 000: pa4 i/o (port) 100: setting prohibited 001: setting prohibited 101: setting prohibited 010: setting prohibited 110: txd3 output (sci) 011: setting prohibited 111: setting prohibited pacrl3 pacrl2 pacrl2 3 7 6 pa3md2 pa3md1 pa3md0 0 0 0 r/w r/w r/w pa3 mode select the function of the pa3/rxd3 pin. 000: pa3 i/o (port) 100: setting prohibited 001: setting prohibited 101: setting prohibited 010: setting prohibited 110: rxd3 input (sci) 011: setting prohibited 111: setting prohibited pacrl3 pacrl2 pacrl2 2 5 4 pa2md2 pa2md1 pa2md0 0 0 0 r/w r/w r/w pa2 mode select the function of the pa2/ irq0 /sck2 pin. 000: pa2 i/o (port) 100: setting prohibited 001: setting prohibited 101: setting prohibited 010: setting prohibited 110: sck2 i/o (sci) 011: irq0 input (intc) 111: setting prohibited pacrl3 pacrl2 pacrl2 1 3 2 pa1md2 pa1md1 pa1md0 0 0 0 r/w r/w r/w pa1 mode select the function of the pa1/ poe1 /txd2 pin. 000: pa1 i/o (port) 100: setting prohibited 001: setting prohibited 101: poe1 input (port) 010: setting prohibited 110: txd2 output (sci) 011: setting prohibited 111: setting prohibited pacrl3 pacrl2 pacrl2 0 1 0 pa0md2 pa0md1 pa0md0 0 0 0 r/w r/w r/w pa0 mode select the function of the pa0/ poe0 /rxd2 pin. 000: pa0 i/o (port) 100: setting prohibited 001: setting prohibited 101: poe0 input (port) 010: setting prohibited 110: rxd2 input (sci) 011: setting prohibited 111: setting prohibited note: x means ?don't care?.
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 364 of 448 rej09b0394-0200 13.1.3 port b i/o register (pbior) pbior is a 16-bit readable/writable register that is used to set the pins on port b as inputs or outputs. bits pb5ior to pb2ior correspond to pi ns pb5 to pb2 (names of multiplexed pins are here given as port names and pin numbers alone). pbior is enabled when port b pins are functioning as general-purpose inputs/outputs (pb5 to pb2). in other states, pbior is disabled. a given pin on port b will be an output pin if the corresponding bit in pbior is set to 1, and an input pin if the bit is cleared to 0. bits 15 to 6, 1, and 0 are reserved. these bits are always read as 0. the write value should always be 0. pbior is initialized to h'0000.
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 365 of 448 rej09b0394-0200 13.1.4 port b control registers 1 and 2 (pbcr1 and pbcr2) pbcr1 and pbcr2 are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port b. port b control registers 1 and 2 (pbcr1 and pbcr2) register bit bit name initial value r/w description pbcr1 pbcr1 pbcr2 pbcr2 15, 14 9 to 0 15 to 12 3 to 0 ? ? ? ? all 0 all 0 all 0 all 0 r r r r reserved these bits are always read as 0. the write value should always be 0. pbcr1 pbcr2 pbcr2 13 11 10 pb5md2 pb5md1 pb5md0 0 0 0 r/w r/w r/w pb5 mode select the function of the pb5/ irq3 / poe3 pin. 000: pb5 i/o (port) 011: setting prohibited 001: irq3 input (intc) 1xx: setting prohibited 010: poe3 input (port) pbcr1 pbcr2 pbcr2 12 9 8 pb4md2 pb4md1 pb4md0 0 0 0 r/w r/w r/w pb4 mode select the function of the pb4/ irq2 / poe2 pin. 000: pb4 i/o (port) 011: setting prohibited 001: irq2 input (intc) 1xx: setting prohibited 010: poe2 input (port) pbcr1 pbcr2 pbcr2 11 7 6 pb3md2 pb3md1 pb3md0 0 0 0 r/w r/w r/w pb3 mode select the function of the pb3/ irq1 / poe1 pin. 000: pb3 i/o (port) 011: setting prohibited 001: irq1 input (intc) 1xx: setting prohibited 010: poe1 input (port) pbcr1 pbcr2 pbcr2 10 5 4 pb2md2 pb2md1 pb2md0 0 0 0 r/w r/w r/w pb2 mode select the function of the pb2/ irq0 / poe0 pin. 000: pb2 i/o (port) 011: setting prohibited 001: irq0 input (intc) 1xx: setting prohibited 010: poe0 input (port) note: x means ?don't care?.
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 366 of 448 rej09b0394-0200 13.1.5 port e i/o registers l and h (peiorl and peiorh) peiorl and peiorh are 16-bit readable/writable regi sters that are used to set the pins on port e as inputs or outputs. bits pe21ior to pe0ior correspond to pins pe21 to pe0 (names of multiplexed pins are here given as port names and pin numbers alone). peiorl is enabled when the port e pins are functioning as general-purpose inputs/outputs (pe15 to pe0), tioc pins are functioning as inputs/outputs of mtu, and sck3 pins are functioning as inputs/outputs of sci. in other states, peiorl is disabled. peiorh is enabled when the port e pins are functioning as general-purpose inputs/outputs (pe21 to pe16). in other states, peiorh is disabled. a given pin on port e will be an output pin if the corresponding peiorl or peiorh bit is set to 1, and an input pin if the bit is cleared to 0. bits 15 to 6 in peiorh are rese rved. these bits are always read as 0. the write value should always be 0. peiorl and peiorh are initialized to h'0000. 13.1.6 port e control registers l1, l2, and h (pecrl1, pecrl2, and pecrh) pecrl1, pecrl2 and pecrh are 16- bit readable/writable registers that are used to select the multiplexed pin function of the pins on port e.
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 367 of 448 rej09b0394-0200 port e control registers l1, l2, and h (pecrl1, pecrl2, and pecrh) register bit bit name initial value r/w description pecrh 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. pecrh pecrh 11 10 pe21md1 pe21md0 0 0 r/w r/w pe21 mode select the function of the pe21 pin. 00: pe21 i/o (port) 10: setting prohibited 01: setting prohibited 11: setting prohibited pecrh pecrh 9 8 pe20md1 pe20md0 0 0 r/w r/w pe20 mode select the function of the pe20 pin. 00: pe20 i/o (port) 10: setting prohibited 01: setting prohibited 11: setting prohibited pecrh pecrh 7 6 pe19md1 pe19md0 0 0 r/w r/w pe19 mode select the function of the pe19 pin. 00: pe19 i/o (port) 10: setting prohibited 01: setting prohibited 11: setting prohibited pecrh pecrh 5 4 pe18md1 pe18md0 0 0 r/w r/w pe18 mode select the function of the pe18 pin. 00: pe18 i/o (port) 10: setting prohibited 01: setting prohibited 11: setting prohibited pecrh pecrh 3 2 pe17md1 pe17md0 0 0 r/w r/w pe17 mode select the function of the pe17 pin. 00: pe17 i/o (port) 10: setting prohibited 01: setting prohibited 11: setting prohibited pecrh pecrh 1 0 pe16md1 pe16md0 0 0 r/w r/w pe16 mode select the function of the pe16 pin. 00: pe16 i/o (port) 10: setting prohibited 01: setting prohibited 11: setting prohibited pecrl1 pecrl1 15 14 pe15md1 pe15md0 0 0 r/w r/w pe15 mode select the function of the pe15/tioc4d/ irqout pin. 00: pe15 i/o (port) 10: setting prohibited 01: tioc4d i/o (mtu) 11: irqout output (intc)
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 368 of 448 rej09b0394-0200 register bit bit name initial value r/w description pecrl1 pecrl1 13 12 pe14md1 pe14md0 0 0 r/w r/w pe14 mode select the function of the pe14/tioc4c pin. 00: pe14 i/o (port) 10: setting prohibited 01: tioc4c i/o (mtu) 11: setting prohibited pecrl1 pecrl1 11 10 pe13md1 pe13md0 0 0 r/w r/w pe13 mode select the function of the pe13/tioc4b/ mres pin. 00: pe13 i/o (port) 10: mres input (intc) 01: tioc4b i/o (mtu) 11: setting prohibited pecrl1 pecrl1 9 8 pe12md1 pe12md0 0 0 r/w r/w pe12 mode select the function of the pe12/tioc4a pin. 00: pe12 i/o (port) 10: setting prohibited 01: tioc4a i/o (mtu) 11: setting prohibited pecrl1 pecrl1 7 6 pe11md1 pe11md0 0 0 r/w r/w pe11 mode select the function of the pe11/tioc3d pin. 00: pe11 i/o (port) 10: setting prohibited 01: tioc3d i/o (mtu) 11: setting prohibited pecrl1 pecrl1 5 4 pe10md1 pe10md0 0 0 r/w r/w pe10 mode select the function of the pe10/tioc3c pin. 00: pe10 i/o (port) 10: setting prohibited 01: tioc3c i/o (mtu) 11: setting prohibited pecrl1 pecrl1 3 2 pe9md1 pe9md0 0 0 r/w r/w pe9 mode select the function of the pe9/tioc3b pin. 00: pe9 i/o (port) 10: setting prohibited 01: tioc3b i/o (mtu) 11: setting prohibited pecrl1 pecrl1 1 0 pe8md1 pe8md0 0 0 r/w r/w pe8 mode select the function of the pe8/tioc3a pin. 00: pe8 i/o (port) 10: setting prohibited 01: tioc3a i/o (mtu) 11: setting prohibited pecrl2 pecrl2 15 14 pe7md1 pe7md0 0 0 r/w r/w pe7 mode select the function of the pe7/tioc2b pin. 00: pe7 i/o (port) 10: setting prohibited 01: tioc2b i/o (mtu) 11: setting prohibited
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 369 of 448 rej09b0394-0200 register bit bit name initial value r/w description pecrl2 pecrl2 13 12 pe6md1 pe6md0 0 0 r/w r/w pe6 mode select the function of the pe6/tioc2a/sck3 pin. 00: pe6 i/o (port) 10: sck3 i/o (sci) 01: tioc2a i/o (mtu) 11: setting prohibited pecrl2 pecrl2 11 10 pe5md1 pe5md0 0 0 r/w r/w pe5 mode select the function of the pe5/tioc1b/txd3 pin. 00: pe5 i/o (port) 10: txd3 output (sci) 01: tioc1b i/o (mtu) 11: setting prohibited pecrl2 pecrl2 9 8 pe4md1 pe4md0 0 0 r/w r/w pe4 mode select the function of the pe4/tioc1a/rxd3 pin. 00: pe4 i/o (port) 10: rxd3 input (sci) 01: tioc1a i/o (mtu) 11: setting prohibited pecrl2 pecrl2 7 6 pe3md1 pe3md0 0 0 r/w r/w pe3 mode select the function of the pe3/tioc0d pin. 00: pe3 i/o (port) 10: setting prohibited 01: tioc0d i/o (mtu) 11: setting prohibited pecrl2 pecrl2 5 4 pe2md1 pe2md0 0 0 r/w r/w pe2 mode select the function of the pe2/tioc0c pin. 00: pe2 i/o (port) 10: setting prohibited 01: tioc0c i/o (mtu) 11: setting prohibited pecrl2 pecrl2 3 2 pe1md1 pe1md0 0 0 r/w r/w pe1 mode select the function of the pe1/tioc0b pin. 00: pe1 i/o (port) 10: setting prohibited 01: tioc0b i/o (mtu) 11: setting prohibited pecrl2 pecrl2 1 0 pe0md1 pe0md0 0 0 r/w r/w pe0 mode select the function of the pe0/tioc0a pin. 00: pe0 i/o (port) 10: setting prohibited 01: tioc0a i/o (mtu) 11: setting prohibited
13. pin function controller (pfc) rev.2.00 sep. 27, 2007 page 370 of 448 rej09b0394-0200 13.2 usage notes 13.2.1 note on pfc setting in this lsi, individual functions are available as multiplexed functions on multiple pins. this approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. when the pin function controller (pfc) is used to select a function, only a single pin can be specified for each function. if one function is specified for two or more pins, the function will not work properly. 13.2.2 note on pfc setting order when a pin function is selected, the port i/o registers (paiorl and pbiorl) must be set after setting the port control registers (pacrl3, pacrl2, pacrl1, pbcr2, and pbcr1. when a pin function which is multiplexed with the port e is selected, do not care about the setting order of the port control registers (pecrh, pecrl1, and pecrl2) and the port i/o registers (peiorh and peiorl).
14. i/o ports rev.2.00 sep. 27, 2007 page 371 of 448 rej09b0394-0200 section 14 i/o ports this lsi has five ports: a, b, e, f, and g. port a is a 16-bit port, port b is a 4-bit port, and port e is a 22-bit port, all supporting both input and output. port f is an 8-bit port and port g is a 4-bit port, both for input-only. all the port pins are multiplexed as general input/output pins and special function pins. the functions of the multiplex pins are selected by means of the pin function controller (pfc). each port is provided with a data register for storing the pin data. 14.1 port a port a is an input/output port with the 16 pins shown in figure 14.1. pa15 to pa12 have an input-pull up mos. pa15 (i/o) pa14 (i/o) pa13 (i/o) pa12 (i/o) pa11 (i/o) / adtrg (input) / sck3 (i/o) pa10 (i/o) / sck2 (i/o) pa9 (i/o) / tclkd (input) / txd3 (output) pa8 (i/o) / tclkc (input) / rxd3 (input) pa7 (i/o) / tclkb (input) / txd2 (output) pa6 (i/o) / tclka (input) / rxd2 (input) pa5 (i/o) / irq1 (input) / sck3 (i/o) pa4 (i/o) / txd3 (output) pa3 (i/o) / rxd3 (input) pa2 (i/o) / irq0 (input) / sck2 (i/o) pa1 (i/o) / poe1 (input) / txd2 (output) pa0 (i/o) / poe0 (input) / rxd2 (input) port a figure 14.1 port a
14. i/o ports rev.2.00 sep. 27, 2007 page 372 of 448 rej09b0394-0200 14.1.1 register description port a is a 16-bit input/output port. port a has the following register. for details on register addresses and register states during each processi ng, refer to section 18, list of registers. ? port a data register l (padrl) 14.1.2 port a data register l (padrl) padrl is a 16-bit readable/writable register th at stores port a data. bits pa15dr to pa0dr correspond to pins pa15 to pa0 (multiplexed functions omitted here). when a pin functions is a general output, if a va lue is written to padrl, that value is output directly from the pin, and if padrl is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if padrl is read, the pin state, not the register value, is returned directly. if a value is written to padrl, a lthough that valu e is written into padrl, it does not affect the pin state. table 14.1 summarizes port a data register l read/write operations.
14. i/o ports rev.2.00 sep. 27, 2007 page 373 of 448 rej09b0394-0200 bit bit name initial value r/w description 15 pa15dr 0 r/w see table 14.1 14 pa14dr 0 r/w 13 pa13dr 0 r/w 12 pa12dr 0 r/w 11 pa11dr 0 r/w 10 pa10dr 0 r/w 9 pa9dr 0 r/w 8 pa8dr 0 r/w 7 pa7dr 0 r/w 6 pa6dr 0 r/w 5 pa5dr 0 r/w 4 pa4dr 0 r/w 3 pa3dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w 0 pa0dr 0 r/w table 14.1 port a data register l (padrl) read/write operations bits 15 to 0: paiorl pin function read write 0 general input pin state can write to padrl, but it has no effect on pin state other than general input pin state can write to padrl, but it has no effect on pin state 1 general output padrl value value written is output from pin other than general output padrl value can write to padrl, but it has no effect on pin state
14. i/o ports rev.2.00 sep. 27, 2007 page 374 of 448 rej09b0394-0200 14.2 port b port b is an input/output port with the four pins shown in figure 14.2. pb5 (i/o) / irq3 (input) / poe3 (input) pb4 (i/o) / irq2 (input) / poe2 (input) pb3 (i/o) / irq1 (input) / poe1 (input) pb2 (i/o) / irq0 (input) / poe0 (input) port b figure 14.2 port b 14.2.1 register description port b is a 4-bit input/output port. port b has the following register. for details on register addresses and register states during each processi ng, refer to section 18, list of registers. ? port b data register (pbdr) 14.2.2 port b data register (pbdr) pbdr is a 16-bit readable/writable register th at stores port b data. bits pb5dr to pb2dr correspond to pins pb5 to pb2 (multiplexed functions omitted here). when a pin functions is a general output, if a value is written to pbdr, that value is output directly from the pin, and if pbdr is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if pbdr is read, the pin state, not the register value, is returned directly. if a value is written to pbdr, alt hough that value is written into pbdr, it does not affect the pin state. table 14.2 summarizes port b data register read/write operations.
14. i/o ports rev.2.00 sep. 27, 2007 page 375 of 448 rej09b0394-0200 bit bit name initial value r/w description 15 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 4 3 2 pb5dr pb4dr pb3dr pb2dr 0 0 0 0 r/w r/w r/w r/w see table 14.2 1, 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. table 14.2 port b data register (pbdr) read/write operations bits 5 to 2: pbior pin function read write 0 general input pin state can write to pbdr, but it has no effect on pin state other than general input pin state can write to pbdr, but it has no effect on pin state 1 general output pbdr value value written is output from pin other than general output pbdr value can write to pbdr, but it has no effect on pin state
14. i/o ports rev.2.00 sep. 27, 2007 page 376 of 448 rej09b0394-0200 14.3 port e port e is an input/output port with the 22 pins shown in figure 14.3. pe21 to pe16 have an input-pull up mos. port e pe15 (i/o) / tioc4d (i/o) / irqout (output) pe14 (i/o) / tioc4c (i/o) pe13 (i/o) / tioc4b (i/o) / mres (input) pe12 (i/o) / tioc4a (i/o) pe11 (i/o) / tioc3d (i/o) pe10 (i/o) / tioc3c (i/o) pe9 (i/o) / tioc3b (i/o) pe21 (i/o) pe20 (i/o) pe19 (i/o) pe18 (i/o) pe17 (i/o) pe16 (i/o) pe8 (i/o) / tioc3a (i/o) pe7 (i/o) / tioc2b (i/o) pe6 (i/o) / tioc2a (i/o) / sck3 (i/o) pe5 (i/o) / tioc1b (i/o) / txd3 (output) pe4 (i/o) / tioc1a (i/o) / rxd3 (input) pe3 (i/o) / tioc0d (i/o) pe2 (i/o) / tioc0c (i/o) pe1 (i/o) / tioc0b (i/o) pe0 (i/o) / tioc0a (i/o) figure 14.3 port e
14. i/o ports rev.2.00 sep. 27, 2007 page 377 of 448 rej09b0394-0200 14.3.1 register descriptions port e has the following registers. for details on register addresses and re gister states during each processing, refer to section 18, list of registers. ? port e data register h (pedrh) ? port e data register l (pedrl) 14.3.2 port e data registers h and l (pedrh and pedrl) pedrh and pedrl are 16-bit readable/writable registers that store port e data. bits pe21dr to pe0dr correspond to pins pe21 to pe0 (multiplexed functions omitted here). when a pin functions is a general output, if a valu e is written to pedrh or pedrl, that value is output directly from the pin, and if pedrh or pedrl is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if pedrh or pedrl is read, the pin state, not the register value, is returned directly. if a value is written to pedrh or pedrl, although that value is written into pedrh or pedrl it does not affect the pin state. table 14.3 summarizes port e data register read/write operations. pedrh: bit bit name initial value r/w description 15 to 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 pe21dr 0 r/w see table 14.3. 4 pe20dr 0 r/w 3 pe19dr 0 r/w 2 pe18dr 0 r/w 1 pe17dr 0 r/w 0 pe16dr 0 r/w
14. i/o ports rev.2.00 sep. 27, 2007 page 378 of 448 rej09b0394-0200 pedrl: bit bit name initial value r/w description 15 pe15dr 0 r/w see table 14.3. 14 pe14dr 0 r/w 13 pe13dr 0 r/w 12 pe12dr 0 r/w 11 pe11dr 0 r/w 10 pe10dr 0 r/w 9 pe9dr 0 r/w 8 pe8dr 0 r/w 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w 0 pe0dr 0 r/w table 14.3 port e data registers h and l (pedrh and pedrl) read/write operations bits 5 to 0 in pedrh and bits 15 to 0 in pedrl: peior pin function read write 0 general input pin state can write to pedrh or pedrl, but it has no effect on pin state other than general input pin state can write to pedrh or pedrl, but it has no effect on pin state 1 general output value written is output from pin ( poe pin = high) * pedrh or pedrl value high impedance regardless of pedrh or pedrl value ( poe pin = low) * other than general output pedrh or pedrl value can write to pedrh or pedrl, but it has no effect on pin state note: * control by the poe pin is only available for large current-output pins (pe9 and pe11 to pe15).
14. i/o ports rev.2.00 sep. 27, 2007 page 379 of 448 rej09b0394-0200 14.4 port f port f is an input-only port with the eight pins shown in figure 14.4. port f pf15 (input) / an15 (input) pf14 (input) / an14 (input) pf13 (input) / an13 (input) pf12 (input) / an12 (input) pf11 (input) / an11 (input) pf10 (input) / an10 (input) pf9 (input) / an9 (input) pf8 (input) / an8 (input) figure 14.4 port f 14.4.1 register description port f is an 8-bit input-only port. port f has the following register. for details on register addresses and register states during each processi ng, refer to section 18, list of registers. ? port f data register (pfdr) 14.4.2 port f data register (pfdr) pfdr is a 16-bit read-only register that stores port f data. bits pf15dr to pf8dr correspond to pins pf15 to pf8 (multiplexed functions omitted here). any value written into these bits is ignored, and there is no effect on the state of the pins. when any of the bits are read, the pin st ate rather than the bit value is read directly. however, when an a/d converter analog input is being sampled, values of 1 are read out. table 14.4 summarizes port f data register read operation.
14. i/o ports rev.2.00 sep. 27, 2007 page 380 of 448 rej09b0394-0200 bit bit name initial value r/w description 15 pf15dr 0/1 * r see table 14.4. 14 pf14dr 0/1 * r 13 pf13dr 0/1 * r 12 pf12dr 0/1 * r 11 pf11dr 0/1 * r 10 pf10dr 0/1 * r 9 pf9dr 0/1 * r 8 pf8dr 0/1 * r 7 to 0 ? all 0 r reserved these bits are always read as 0. note: * initial values are dependent on the state of the external pins. table 14.4 port f data register (pfdr) read/wri te operations bits 15 to 8: pin function read write general input pin state ignored (no effect on pin state) ann input 1 ignored (no effect on pin state)
14. i/o ports rev.2.00 sep. 27, 2007 page 381 of 448 rej09b0394-0200 14.5 port g port g is an input-only port with the four pins shown in figure 14.5. port g pg3 (input) pg2 (input) pg1 (input) pg0 (input) figure 14.5 port g 14.5.1 register description port g is a 4-bit input-only port. port g has the following register. for details on register addresses and register states during each processing, refer to section 18, list of registers. ? port g data register (pgdr) 14.5.2 port g data register (pgdr) pgdr is an 8-bit read-only register that stores port g data. bits pg3dr to pg0dr correspond to pins pg3 to pg0. any value written into these bits is ignored, and there is no effect on the state of the pins. when any of the bits are read, the pin state rather than the bit value is r ead directly. table 14.5 summarizes port g data register read operation. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. 3 pg3dr 0/1 * r see table 14.5. 2 pg2dr 0/1 * r 1 pg1dr 0/1 * r 0 pg0dr 0/1 * r note: * initial values are dependent on the state of the external pins.
14. i/o ports rev.2.00 sep. 27, 2007 page 382 of 448 rej09b0394-0200 table 14.5 port g data register (pgdr) read/write operations bits 3 to 0: pin function read write general input pin state ignored (no effect on pin state)
15. mask rom rev.2.00 sep. 27, 2007 page 383 of 448 rej09b0394-0200 section 15 mask rom this lsi is available with 32 kbytes of on-chip mask rom. the on-chip rom is connected to the cpu through a 32-bit data bus (figure 15.1). the cpu can access the on-chip rom in 8, 16 and 32-bit widths. data in the on-chip rom can always be accessed in one cycle. h'00000000 h'00000004 h'00000001 h'00000005 h'00000002 h'00000006 h'00000003 h'00000007 h'00007ffc h'00007ffd h'00007ffe h'00007fff internal data bus (32 bits) on-chip rom figure 15.1 mask rom block diagram the on-chip rom is allocated to addresses h'0000000 0 to h' 00007fff. 15.1 usage note ? setting module standby mode for mask rom, this module can be disabled/enabled by the module standby control register. mask rom operation is enabled for the initial value. accessing mask rom is disabled by setting module standby mode. for details, see section 17, power-down modes.
15. mask rom rev.2.00 sep. 27, 2007 page 384 of 448 rej09b0394-0200
16. ram ram0200a_000020030200 rev.2.00 sep. 27, 2007 page 385 of 448 rej09b0394-0200 section 16 ram this lsi has an on-chip high-speed static ram. the on-chip ram is connected to the cpu by a 32-bit data bus, enabling 8, 16, or 32-bit width acce ss to data in the on-chip ram. data in the on- chip ram can always be accessed in one cycle, providing high-speed access that makes this ram ideal for use as a program area, stack area, or data area. the contents of the on-chip ram are retained in both sleep and standby modes. the on-chip ram can be enabled or disabled by means of the rame bit in the system control register (syscr). for details on the system control register (syscr), refer to section 17.2.2, system control register (syscr). product type type of rom ram capacity ram address SH7101 mask rom 2 kbytes h'fffff800 to h'ffffffff 16.1 usage note ? module standby mode setting ram can be enabled/disabled by the module stan dby control register. the initial value enables ram operation. ram access is disabled by setti ng the module standby mode. for details, see section 17, power-down modes.
16. ram rev.2.00 sep. 27, 2007 page 386 of 448 rej09b0394-0200
17. power-down modes lpwsh20a_010020030200 rev.2.00 sep. 27, 2007 page 387 of 448 rej09b0394-0200 section 17 power-down modes in addition to the normal program execution state, this lsi has three power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip peripheral functions, and so on. this lsi's power-down modes are as follows: (1) sleep mode (2) software standby mode (3) module standby mode sleep mode indicates the state of the cpu, and module standby mode indicates the state of the on- chip peripheral function. some of these states can be combined. after a reset, the lsi is in normal-operation mode. table 17.1 lists internal operation states in each mode.
17. power-down modes rev.2.00 sep. 27, 2007 page 388 of 448 rej09b0394-0200 table 17.1 internal operation states in each mode function normal operation sleep module standby software standby system clock pulse generator functioning functioning functioning halted cpu instructions registers functioning halted (retained) functioning halted (retained) nmi functioning functioning functioning functioning external interrupts irq3 to irq0 i/o port functioning functioning functioning retained wdt functioning functioning functioning halted (retained) sci a/d mtu cmt peripheral functions rom functioning functioning halted (reset) halted (reset) ram functioning functioning retained retained notes: 1. "halted (retained)" means that the operation of the internal state is suspended, although internal register values are retained. 2. "halted (reset)" means that internal register values and internal state are initialized. 3. in module standby mode, only modules for which a stop setting has been made are halted (reset or retained). 4. there are two types of on-chip peripheral m odule registers; ones which are initialized in software standby mode and module standby mode, and those not initialized those modes. for details, refer to section 18.3, register states in each operating mode. 5. the port high-impedance bit (hiz) in sbycr sets the state of the i/o port in software standby mode. for details on the setting, refer to section 17.2.1, standby control register (sbycr). for the state of pins, refer to appendix a, pin states.
17. power-down modes rev.2.00 sep. 27, 2007 page 389 of 448 rej09b0394-0200 program-halted state program execution state sleep instruction sleep instruction external interrupt * ssby = 0 ssby = 1 res pin = high : transition after exception processing : power-down mode reset state normal-operation mode (main clock) software standby mode sleep mode (main clock) notes: * nmi and irq ? when a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. ? in any state, a transition to the reset state occurs when res is driven low. figure 17.1 mode transition diagram 17.1 input/output pins table 17.2 lists the pins relating to power-down mode. table 17.2 pin configuration pin name i/o function res input power-on reset input pin mres input manual reset input pin
17. power-down modes rev.2.00 sep. 27, 2007 page 390 of 448 rej09b0394-0200 17.2 register descriptions registers related to power down modes are shown below. for details on register addresses and register states during each process, refe r to section 18, list of registers. ? standby control register (sbycr) ? system control register (syscr) ? module standby control register 1 (mstcr1) ? module standby control register 2 (mstcr2) 17.2.1 standby control register (sbycr) sbycr is an 8-bit readable/writable register that performs software standby mode control. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit specifies the transition mode after executing the sleep instruction. 0: shifts to sleep mode after the sleep instruction has been executed 1: shifts to software standby mode after the sleep instruction has been executed this bit cannot be set to 1 when the watchdog timer (wdt) is operating (when the tme bit in tcsr of the wdt is set to 1). when transferring to software standby mode, clear the tme bit to 0, stop the wdt, then set the ssby bit to 1. 6 hiz 0 r/w port high-impedance in software standby mode, this bit selects whether the pin state of the i/o port is retained or changed to high- impedance. 0: in software standby mode, the pin state is retained. 1: in software standby mode, the pin state is changed to high-impedance. the hiz bit cannot be set to 1 when the tme bit in tcsr of the wdt is set to 1. when changing the pin state of the i/o port to high- impedance, clear the tme bit to 0, then set the hiz bit to 1.
17. power-down modes rev.2.00 sep. 27, 2007 page 391 of 448 rej09b0394-0200 bit bit name initial value r/w description 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 to 1 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 0 irqel 1 r/w irq3 to irq0 enable irq interrupts are enabled to clear software standby mode. 0: software standby mode is cleared. 1: software standby mode is not cleared.
17. power-down modes rev.2.00 sep. 27, 2007 page 392 of 448 rej09b0394-0200 17.2.2 system control register (syscr) syscr is an 8-bit readab le/writable register that enables/di sables the access to the on-chip ram. bit bit name initial value r/w description 7, 6 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 5 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 rame 1 r/w ram enable this bit enables/disables the on-chip ram. 0: on-chip ram disabled 1: on-chip ram enabled when this bit is cleared to 0, the access to the on-chip ram is disabled. in this case, an undefined value is returned when reading or fetching the data or instruction from the on- chip ram, and writing to the on-chip ram is ignored. when rame is cleared to 0 to disable the on-chip ram, an instruction to access the on-chip ram should not be set next to the instruction to write to syscr. if such an instruction is set, normal access is not guaranteed. when rame is set to 1 to enable the on-chip ram, an instruction to read syscr should be set next to the instruction to write to syscr. if an instruction to access the on-chip ram is set next to the instruction to write to syscr, normal access is not guaranteed.
17. power-down modes rev.2.00 sep. 27, 2007 page 393 of 448 rej09b0394-0200 17.2.3 module standby control register 1 and 2 (mstcr1 and mstcr2) mstcr, comprising two 16-bit readable/writable registers, performs module standby mode control. setting a bit to 1, the corresponding module enters module standby mode, while clearing the bit to 0 clears the module standby mode. mstcr1 bit bit name initial value r/w description 15 to 12 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 11 mstp27 0 r/w on-chip ram 10 mstp26 0 r/w on-chip rom 9, 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 4 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 3 mstp19 1 r/w serial communication interface 3 (sci_3) 2 mstp18 1 r/w serial communication interface 2 (sci_2) 1, 0 ? all 1 r reserved these bits are always read as 1. the write value should always be 1.
17. power-down modes rev.2.00 sep. 27, 2007 page 394 of 448 rej09b0394-0200 mstcr2 bit bit name initial value r/w description 15 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 14 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 13 mstp13 1 r/w multi-function timer pulse unit (mtu) 12 mstp12 1 r/w compare match timer (cmt) 11, 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 8 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 7 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 6 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 5 mstp5 1 r/w a/d converter (a/d1) 4 mstp4 1 r/w a/d converter (a/d0) 3 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0.
17. power-down modes rev.2.00 sep. 27, 2007 page 395 of 448 rej09b0394-0200 17.3 operation 17.3.1 sleep mode transition to sleep mode: if sleep instruction is executed wh ile the ssby bit in sbycr = 0, the cpu enters sleep mode. in sleep mode, cpu operation stops, however the contents of the cpu's internal registers are retained. peripheral functions except the cpu do not stop. clearing sleep mode: sleep mode is cleared by the conditions below. ? clearing by the power on reset when the res pin is driven low, the cpu enters the reset state. when the res pin is driven high after the elapse of the specified reset input period, the cpu starts the reset exception handling. also, when the internal power on reset is occurred, sl eep mode is cleared. ? clearing by the manual reset when the mres pin is driven low while the res pin is high, the cpu shifts to the manual reset state and thus sleep mode is cleared. also , when the internal manual reset is occurred, sleep mode is cleared. notes on using sleep mode ? there are 4 conditions to clear sleep mode. (1) clearing by an interrupt (2) clearing by dtc address error (3) clearing by the power-on reset (4) clearing by the manual reset when clearing sleep mode by (1) or (2), cpu ma y run out of control. please clear sleep mode by (3) or (4), don't use (1) or (2). ? do not use dtc module or aud module during sleep mode.
17. power-down modes rev.2.00 sep. 27, 2007 page 396 of 448 rej09b0394-0200 17.3.2 software standby mode transition to software standby mode: a transition is made to software standby mode if the sleep instruction is executed while the ssby bit in sbycr is set to 1. in this mode, the cpu, on-chip peripheral functions, and the oscillator, all stop. however, the contents of the cpu's internal registers and on-chip ram data (when the rame bit in syscr is 0) are retained as long as the specified voltage is supplied. there are two types of on- chip peripheral module registers; ones which are initialized by software standby mode, and those not initialized by that mode. for details, refer to s ection 18.3, register states in each operating mode. the port high-impedance bit (hiz) in sbycr sets the state of the i/o port either to "retained" or "high-impedance". for the state of pins, refer to appendix a, pin states. in software standby mode, the oscillator stops and thus power consumption is significantly reduced. clearing software standby mode: software standby mode is cleared by the condition below. ? clearing by the nmi interrupt input when the falling edge or rising edge of the nmi pin (selected by the nmi edge select bit (nmie) in icr1 of the interrupt controller (intc)) is detected, clock oscillation is started. this clock pulse is supplied only to the watchdog timer (wdt). after the elapse of the time set in the clock select bits (cks2 to cks0) in tcsr of the wdt before the transition to software standby mode, the wdt overflow occurs. since this overflow indicates that the clock has been stabilized, clock pulse will be s upplied to the entire chip after this overflow. software standby mode is thus cleared and the nmi exception handling is started. when clearing software standby mode by the nmi interrupt, set cks2 to cks0 bits so that the wdt overflow period will be longer th an the oscillation stabilization time. when software standby mode is cleared by th e falling edge of the nmi pin, the nmi pin should be high when the cpu enters software standby mode (when the clock pulse stops) and should be low when the cpu returns from standby mode (when the clock is initiated after the oscillation stabilization). when software standby mode is cleared by the rising edge of the nmi pin, the nmi pin should be low when the cpu enters software standby mode (when the clock pulse stops) and should be high when the cpu returns from software standby mode (when the clock is initiated after the oscillation stabilization). ? clearing by the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation is started, clock pulse is supp lied to the entire chip . ensure that the res pin is held low until clock oscillation stabilizes. when the res pin is driven high, the cpu starts the reset exception handling.
17. power-down modes rev.2.00 sep. 27, 2007 page 397 of 448 rej09b0394-0200 ? clearing by the irq interrupt input when the irqel bit in the standby control register (sbycr) is set to 1 and when the falling edge or rising edge of the irq pin (selected by the irq3s to irq0s bits in icr1 of the interrupt controller (intc) and the irq3es [1:0] to irq0es [1:0] bits in icr2) is detected, clock oscillation is started.* this clock pulse is supplied only to the watchdog timer (wdt). the irq interrupt priority level should be higher than the interrupt mask level set in the status register (sr) of the cpu before the transition to software standby mode. after the elapse of the time set in the clock select bits (cks2 to cks0) in tcsr of the wdt before the transition to software standby mode, the wdt overflow occurs. since this overflow indicates that the clock has been stabilized, clock pulse will be s upplied to the entire chip after this overflow. software standby mode is thus cleared and the irq exception handling is started. when clearing software standby mode by the irq interrupt, set cks2 to cks0 bits so that the wdt overflow period will be longer th an the oscillation stabilization time. when software standby mode is cleared by the falling edge or both edges of the irq pin, the irq pin should be high when the cpu enters software standby mode (when the clock pulse stops) and should be low when the cpu returns from software standby mode (when the clock is initiated after the oscillation stabilization). when software standby mode is cleared by the rising edge of the irq pin, the irq pin should be low when the cpu enters software standby mode (when the clock pulse stops) and should be high when the cpu returns from software standby mode (when the clock is initiate d after the oscillation stabilization). note: * when the irq pin is set to falling-edge detection or both-edge detection, clock oscillation starts at falling-edge detection. when the irq pin is set to rising-edge detection, clock oscillation starts at rising-edge detection. do not set the irq pin to low-level detection. software standby mode application example: figure 17.2 shows an example in which a transition is made to software standby mode at the falling edge of the nmi pin, and software standby mode is cleared at a rising edge of the nmi pin. in this example, when the nmi pin is driven low while the nmi edge select bit (nmie) in icr1 is 0 (falling edge detection), an nmi interrupt is accepte d. then, the nmie bit is set to 1 (rising edge detection) in the nmi exception se rvice routine, the ssb y bit in sbycr is set to 1, and a sleep instruction is executed to transfer to software standby mode. software standby mode is cleared by driving the nmi pin from low to high.
17. power-down modes rev.2.00 sep. 27, 2007 page 398 of 448 rej09b0394-0200 oscillator ck nmi input nmie bit ssby bit lsi state oscillation start time program execution state exception service routine software standby mode wdt setting time nmi exception handling nmi exception handling oscillation stabilization time figure 17.2 nmi timing in software standby mode 17.3.3 module standby mode module standby mode can be set for indi vidual on-chip peripheral functions. when the corresponding mstp bit in mstcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module standby mode. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, module standby mode is cleared and the module starts operating at the end of the bus cycle. in module standby mode, the internal states of modules are initialized. after reset clearing, the sci, mtu, cmt, and a/d converter are in module standby mode. when an on-chip peripheral module is in module standby mode, read/write access to its registers is disabled.
17. power-down modes rev.2.00 sep. 27, 2007 page 399 of 448 rej09b0394-0200 17.4 usage notes 17.4.1 i/o port status when a transition is mode to software standby mode while the port high-impedance bit (hiz) in sbycr is 0, i/o port states are retained. therefor e, there is no reduction in current consumption for the output current when a high-level signal is output. 17.4.2 current consumption during oscillation stabilization wait period current consumption increases during the oscillation stabilization wait period. 17.4.3 on-chip peripheral module interrupt relevant interrupt operations cannot be perfor med in module standby mode. consequently, if the cpu enters module standby mode while an interrupt has been requested, it will not be possible to clear the cpu interrupt source. interrupts should therefore be disabled before entering module standby mode. 17.4.4 writing to mstcr1 and mstcr2 mstcr1 and mstcr2 should onl y be written to by the cpu.
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18. list of registers rev.2.00 sep. 27, 2007 page 401 of 448 rej09b0394-0200 section 18 list of registers the column ?access size? shows the number of bits. the column ?access states? shows the number of access states, in units of cy cles, of the specified reference clock. b, w, and l in the column repr esent 8-bit, 16-bit, and 32-bit access, respectively. 18.1 register addresses (order of address) register name abbreviation bits address module access size access states ? ? ? h'ffff8000 to h'ffff81bf ? ? ? serial mode register_2 smr_2 8 h'ffff81c0 8, 16 bit rate register_2 brr_2 8 h'ffff81c1 sci (channel 2) 8 serial control register_2 scr_2 8 h'ffff81c2 8, 16 in p cycles b: 2 w: 4 transmit data register_2 tdr_2 8 h'ffff81c3 8 serial status register_2 ssr_2 8 h'ffff81c4 8, 16 receive data register_2 rdr_2 8 h'ffff81c5 8 serial direction control register_2 sdcr_2 8 h'ffff81c6 8 ? ? ? h'ffff81c7 to h'ffff81cf ? serial mode register_3 sm r_3 8 h'ffff81d0 8, 16 bit rate register_3 brr_3 8 h'ffff81d1 sci (channel 3) 8 serial control register_3 scr_3 8 h'ffff81d2 8, 16 transmit data register_3 tdr_3 8 h'ffff81d3 8 serial status register_3 ssr_3 8 h'ffff81d4 8, 16 receive data register_3 rdr_3 8 h'ffff81d5 8 serial direction control register_3 sdcr_3 8 h'ffff81d6 8 ? ? ? h'ffff81d7 to h'ffff81ff ? timer control register_3 tcr_3 8 h'ffff8200 8, 16, 32 timer control regist er_4 tcr_4 8 h'ffff8201 8 timer mode register _3 tmdr_3 8 h'ffff8202 mtu (channels 3 and 4) 8, 16 in p cycles b: 2 w: 2 l: 4 timer mode register_4 tmdr_4 8 h'ffff8203 8 timer i/o control register h_3 tiorh_3 8 h'ffff8204 8, 16, 32 timer i/o control register l_3 tiorl_3 8 h'ffff8205 8
18. list of registers rev.2.00 sep. 27, 2007 page 402 of 448 rej09b0394-0200 register name abbreviation bits address module access size access states timer i/o control register h_4 tiorh_4 8 h'ffff8206 8, 16 timer i/o control register l_4 tiorl_4 8 h'ffff8207 8 timer interrupt enable register_3 tier_3 8 h'ffff8208 8, 16, 32 timer interrupt enable register_4 tier_4 8 h'ffff8209 mtu (channels 3 and 4) 8 in p cycles b: 2 w: 2 l: 4 timer output master enable register toer 8 h'ffff820a 8, 16 timer output control register tocr 8 h'ffff820b 8 ? ? ? h'ffff820c timer gate control register tgcr 8 h'ffff820d 8 ? ? ? h'ffff820e ? ? ? h'ffff820f timer counter_3 tcnt_3 16 h'ffff8210 16, 32 timer counter_4 tcnt _4 16 h'ffff8212 16 timer period data register tcdr 16 h'ffff8214 16, 32 timer dead time data register tddr 16 h'ffff8216 16 timer general register a_3 tgra_3 16 h'ffff8218 16, 32 timer general register b_3 tgrb_3 16 h'ffff821a 16 timer general register a_4 tgra_4 16 h'ffff821c 16, 32 timer general register b_4 tgrb_4 16 h'ffff821e 16 timer sub-counter tcnt s 16 h'ffff8220 16, 32 timer period buffer register tcbr 16 h'ffff8222 16 timer general register c_3 tgrc_3 16 h'ffff8224 16, 32 timer general register d _3 tgrd_3 16 h'ffff8226 16 timer general register c_4 tgrc_4 16 h'ffff8228 16, 32 timer general register d_4 tgrd_4 16 h'ffff822a 16 timer status register_3 tsr_3 8 h'ffff822c 8, 16 timer status register_4 tsr_4 8 h'ffff822d 8 ? ? ? h'ffff822e to h'ffff823f timer start register tstr 8 h'ffff8240 8, 16 timer synchro register tsyr 8 h'ffff8241 mtu (common) 8 ? ? ? h'ffff8242 to h'ffff825f in p cycles b: 2 w: 2
18. list of registers rev.2.00 sep. 27, 2007 page 403 of 448 rej09b0394-0200 register name abbreviation bits address module access size access states timer control register_0 tcr_0 8 h'ffff8260 8, 16, 32 timer mode register _0 tmdr_0 8 h'ffff8261 mtu (channel 0) 8 timer i/o control register h_0 tiorh_0 8 h'ffff8262 8, 16 in p cycles b: 2 w: 2 l: 4 timer i/o control register l_0 tiorl_0 8 h'ffff8263 8 timer interrupt enable register_0 tier_0 8 h'ffff8264 8, 16, 32 timer status register_0 tsr_0 8 h'ffff8265 8 timer counter_0 t cnt_0 16 h'ffff8266 16 timer general register a_0 tgra_0 16 h'ffff8268 16, 32 timer general register b_0 tgrb_0 16 h'ffff826a 16 timer general register c_0 tgrc_0 16 h'ffff826c 16, 32 timer general register d_0 tgrd_0 16 h'ffff826e 16 ? ? ? h'ffff8270 to h'ffff827f ? timer control register_1 tcr_1 8 h'ffff8280 8, 16 timer mode register _1 tmdr_1 8 h'ffff8281 mtu (channel 1) 8 timer i/o control register_1 tior_1 8 h'ffff8282 8 ? ? ? h'ffff8283 ? timer interrupt enable register_1 tier_1 8 h'ffff8284 8, 16, 32 timer status register_1 tsr_1 8 h'ffff8285 8 timer counter_1 tcnt _1 16 h'ffff8286 16 timer general register a_1 tgra_1 16 h'ffff8288 16, 32 timer general register b_1 tgrb_1 16 h'ffff828a 16 ? ? ? h'ffff828c to h'ffff829f ? timer control register_2 tcr_2 8 h'ffff82a0 8, 16 timer mode register _2 tmdr_2 8 h'ffff82a1 mtu (channel 2) 8 timer i/o control register_2 tior_2 8 h'ffff82a2 8 ? ? ? h'ffff82a3 ? timer interrupt enable register_2 tier_2 8 h'ffff82a4 8, 16, 32 timer status register_2 tsr_2 8 h'ffff82a5 8 timer counter_2 tcnt_2 16 h'ffff82a6 16
18. list of registers rev.2.00 sep. 27, 2007 page 404 of 448 rej09b0394-0200 register name abbreviation bits address module access size access states timer general register a_2 tgra_2 16 h'ffff82a8 16, 32 timer general register b_2 tgrb_2 16 h'ffff82aa mtu (channel 2) 16 ? ? ? h'ffff82ac to h'ffff833f ? in p cycles b: 2 w: 2 l: 4 ? ? ? h'ffff8340 to h'ffff8347 intc ? interrupt priority register a ipra 16 h'ffff8348 8, 16 ? ? ? h'ffff834a to h'ffff834d ? interrupt priority register d iprd 16 h'ffff834e 8, 16 in cycles b: 2 w: 2 l: 4 interrupt priority register e ipre 16 h'ffff8350 8, 16, 32 interrupt priority register f iprf 16 h'ffff8352 8, 16 interrupt priority register g iprg 16 h'ffff8354 8, 16, 32 interrupt priority register h iprh 16 h'ffff8356 8, 16 interrupt control register 1 icr1 16 h'ffff8358 8, 16, 32 irq status register isr 16 h'ffff835a 8, 16 interrupt priority register i ipri 16 h'ffff835c 8, 16, 32 ? ? ? h'ffff835e to h'ffff8365 ? interrupt control register 2 icr2 8 h'ffff8366 8, 16 ? ? ? h'ffff8368 to h'ffff837f ? ? ? ? h'ffff8380 to h'ffff8381 ? ? ? port a data register l padrl 16 h'ffff8382 i/o 8, 16 ? ? ? h'ffff8384 to h'ffff8385 ? ? port a i/o register l paiorl 16 h'ffff8386 pfc 8, 16 in cycles b: 2 w: 2 l: 4 ? ? ? h'ffff8388 to h'ffff8389 ? ? port a control register l3 pacrl3 16 h'ffff838a pfc 8, 16 port a control register l1 pacrl1 16 h'ffff838c 8, 16, 32 port a control register l2 pacrl2 16 h'ffff838e 8, 16 port b data register pbdr 16 h'ffff8390 i/o 8, 16 ? ? ? h'ffff8392 to h'ffff8393 ? ?
18. list of registers rev.2.00 sep. 27, 2007 page 405 of 448 rej09b0394-0200 register name abbreviation bits address module access size access states port b i/o register pbior 16 h'ffff8394 pfc 8, 16, 32 ? ? ? h'ffff8396 to h'ffff8397 ? ? port b control register 1 pbcr1 16 h'ffff8398 pfc 8, 16, 32 port b control register 2 pbcr2 16 h'ffff839a 8, 16 ? ? ? h'ffff839c to h'ffff83ae ? ? port e data register l pedrl 16 h'ffff83b0 i/o 8, 16, 32 port f data register pfdr 16 h'ffff83b2 8, 16 port e i/o register l peiorl 16 h'ffff83b4 pfc 8, 16, 32 port e i/o register h peiorh 16 h'ffff83b6 8, 16 port e control register l1 pecrl1 16 h'ffff83b8 8, 16, 32 in cycles b: 2 w: 2 l: 4 port e control register l2 pecrl2 16 h'ffff83ba 8, 16 port e control register h pecrh 16 h'ffff8 3bc 8, 16, 32 port e data register h pedrh 16 h'ffff8 3be i/o 8, 16 input control/status register 1 icsr1 16 h'ffff83c0 mtu 8, 16, 32 output control/ status register ocsr 16 h'ffff83c2 8, 16 in cycles b: 2 w: 2 l: 4 ? ? ? h'ffff83c4 to h'ffff83cc ? ? port g data register pgdr 8 h'ffff83cd i/o 8 in p cycles b: 2 w: 2 l: 4 ? ? ? h'ffff83ce to h'ffff83cf ? ? ? compare match timer start register cmstr 16 h'ffff83d0 cmt 8, 16, 32 compare match timer control/status register_0 cmcsr_0 16 h'ffff83d2 8, 16 in cycles b: 2 w: 2 l: 4 compare match timer counter_0 cm cnt_0 16 h'ffff83d4 8, 16, 32 compare match timer constant register_0 cmcor_0 16 h'ffff83d6 8, 16
18. list of registers rev.2.00 sep. 27, 2007 page 406 of 448 rej09b0394-0200 register name abbreviation bits address module access size access states compare match timer control/status register_1 cmcsr_1 16 h'ffff83d8 cmt 8, 16, 32 compare match timer counter_1 cmcnt_1 16 h'ffff83da 8, 16 in cycles b: 2 w: 2 l: 4 compare match timer constant register_1 cmcor_1 16 h'ffff83dc 8, 16 ? ? ? h'ffff83de ? ? ? h'ffff83e0 to h'ffff842e ? ? ? a/d data register 8 addr8 16 h'ffff8430 8, 16 in p cycles b: 3 w: 6 a/d data register 9 addr9 16 h'ffff8432 a/d (channel 0) 8, 16 a/d data register 10 addr10 16 h'ffff8434 8, 16 a/d data register 11 addr11 16 h'ffff8436 8, 16 a/d data register 12 addr12 16 h'ffff8438 8, 16 a/d data register 13 addr13 16 h'ffff843a a/d (channel 1) 8, 16 a/d data register 14 addr14 16 h'ffff843c 8, 16 a/d data register 15 a ddr15 16 h'ffff843e 8, 16 ? ? ? h'ffff8440 to h'ffff847f ? ? a/d control/status register_0 adcsr_0 8 h'ffff8480 a/d 8, 16 a/d control/status register_1 adcsr_1 8 h'ffff8481 8 ? ? ? h'ffff8482 to h'ffff8487 ? a/d control register_0 adcr_0 8 h'ffff8488 8, 16 a/d control register_1 adcr_1 8 h'ffff8489 8 ? ? ? h'ffff848a to h'ffff860f ? ? timer control/status register tcsr 8 h'ffff8610 8 * 2 /16 * 1 timer counter tcnt * 1 8 h'ffff8610 16 timer counter tcnt * 2 8 h'ffff8611 8 in cycles b: 3 w: 3 reset control/status register rstcsr * 1 8 h'ffff8612 16 reset control/status register rstcsr * 2 8 h'ffff8613 wdt * 1: write cycle * 2: read cycle 8 standby control register sbycr 8 h'ffff8614 power- down state 8 in cycles b: 3
18. list of registers rev.2.00 sep. 27, 2007 page 407 of 448 rej09b0394-0200 register name abbreviation bits address module access size access states ? ? ? h'ffff8615 to h'ffff8617 ? ? ? system control register syscr 8 h'ffff8618 8 ? ? ? h'ffff8619 to h'ffff861b power- down state ? module standby control register 1 mstcr1 16 h'ffff861c 8, 16, 32 module standby control register 2 mstcr2 16 h'ffff861e 8, 16 in p cycles b: 3 w: 3 l: 6 bus control register 1 bcr1 16 h'ffff8620 bsc 8, 16, 32 ? ? ? h'ffff8622 to h'ffff8626 ? in cycles b: 3 w: 3 l: 6 ? ? h'ffff8628 to h'ffff87f3 ? ad trigger select regist er adtsr 8 h'ffff87f4 a/d 8 ? ? h'ffff87f5 to h'ffff89ff ? in p cycles b: 3 ? ? h'ffff8a00 to h'ffffb4f3 ?
18. list of registers rev.2.00 sep. 27, 2007 page 408 of 448 rej09b0394-0200 18.2 register bits on-chip peripheral module register addresses and bit names are shown in the following table. 16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively. register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module smr_2 c/ a chr pe o/ e stop mp cks1 cks0 brr_2 scr_2 tie rie te re mpie teie cke1 cke0 tdr_2 ssr_2 tdre rdrf orer fer per tend mpb mpbt sci (channel 2) rdr_2 sdcr_2 ? ? ? ? dir ? ? ? smr_3 c/ a chr pe o/ e stop mp cks1 cks0 brr_3 scr_3 tie rie te re mpie teie cke1 cke0 tdr_3 ssr_3 tdre rdrf orer fer per tend mpb mpbt sci (channel 3) rdr_3 sdcr_3 ? ? ? ? dir ? ? ? ? ? ? ? ? ? ? ? ? ? tcr_3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcr_4 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_3 ? ? bfb bfa md3 md2 md1 md0 tmdr_4 ? ? bfb bfa md3 md2 md1 md0 tiorh_3 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_3 iod3 iod2 iod1 iod0 ioc3 ioc 2 ioc1 ioc0 tiorh_4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_4 iod3 iod2 iod1 iod0 ioc3 ioc 2 ioc1 ioc0 tier_3 ttge ? ? tciev tgied tgiec tgieb tgiea tier_4 ttge ? ? tciev tgied tgiec tgieb tgiea mtu (channels 3 and 4) toer ? ? oe4d oe4c oe3d oe4b oe4a oe3b tocr ? psye ? ? ? ? olsn olsp tgcr ? bdc n p fb wf vf uf tcnt_3
18. list of registers rev.2.00 sep. 27, 2007 page 409 of 448 rej09b0394-0200 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcnt_4 tcdr tddr tgra_3 tgrb_3 tgra_4 tgrb_4 mtu (channels 3 and 4) tcnts tcbr tgrc_3 tgrd_3 tgrc_4 tgrd_4 tsr_3 tcfd ? ? tcfv tgfd tgfc tgfb tgfa tsr_4 tcfd ? ? tcfv tgfd tgfc tgfb tgfa tstr cst4 cst3 ? ? ? cst2 cst1 cst0 tsyr sync4 sync3 ? ? ? sync2 sync1 sync0 tcr_0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ? ? bfb bfa md3 md2 md1 md0 mtu (channel 0) tiorh_0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 iod3 iod2 iod1 iod0 ioc3 ioc 2 ioc1 ioc0 tier_0 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 ? ? ? tcfv tgfd tgfc tgfb tgfa
18. list of registers rev.2.00 sep. 27, 2007 page 410 of 448 rej09b0394-0200 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcnt_0 tgra_0 tgrb_0 tgrc_0 tgrd_0 mtu (channel 0) tcr_1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu tciev ? ? tgieb tgiea tsr_1 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_1 tgra_1 tgrb_1 mtu (channel 1) tcr_2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu tciev ? ? tgieb tgiea tsr_2 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_2 tgra_2 tgrb_2 mtu (channel 2) ? ? ? ? ? ? ? ? ? ?
18. list of registers rev.2.00 sep. 27, 2007 page 411 of 448 rej09b0394-0200 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module irq0 irq0 irq0 irq0 irq1 irq1 irq1 irq1 ipra irq2 irq2 irq2 irq2 irq3 irq3 irq3 irq3 mtu0 mtu0 mtu0 mtu0 mtu0 mtu0 mtu0 mtu0 iprd mtu1 mtu1 mtu1 mtu1 mtu1 mtu1 mtu1 mtu1 mtu2 mtu2 mtu2 mtu2 mtu2 mtu2 mtu2 mtu2 ipre mtu3 mtu3 mtu3 mtu3 mtu3 mtu3 mtu3 mtu3 mtu4 mtu4 mtu4 mtu4 mtu4 mtu4 mtu4 mtu4 iprf ? ? ? ? ? ? ? ? a/d0,1 a/d0,1 a/d0,1 a/d0,1 ? ? ? ? iprg cmt0 cmt0 cmt0 cmt0 cmt1 cmt1 cmt1 cmt1 wdt wdt wdt wdt i/o(mtu) i/o(mtu) i/o(mtu) i/o(mtu) iprh ? ? ? ? ? ? ? ? nmil ? ? ? ? ? ? nmie icr1 irq0s irq1s irq2s irq3s ? ? ? ? ? ? ? ? ? ? ? ? isr irq0f irq1f irq2f irq3f ? ? ? ? sci2 sci2 sci2 sci2 sci3 sci3 sci3 sci3 ipri ? ? ? ? ? ? ? ? irq0es1 irq0es0 irq1es1 irq1es0 irq2es1 irq2es0 irq3es1 irq3es0 icr2 ? ? ? ? ? ? ? ? intc ? ? ? ? ? ? ? ? ? ? pa15dr pa14dr pa13dr pa12dr pa11dr pa10dr pa9dr pa8dr port a padrl pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr paiorl pa15ior pa14ior pa13ior pa12 ior pa11ior pa10ior pa9ior pa8ior pa7ior pa6ior pa5ior pa4ior pa3ior pa2ior pa1ior pa0ior pa15md2 pa14md2 pa13md2 pa12md2 pa11md2 pa10md2 pa9md2 pa8md2 pacrl3 pa7md2 pa6md2 pa5md2 pa4md2 pa3md2 pa2md2 pa1md2 pa0md2 pa15md1 pa15md0 pa14md1 pa14md0 pa13md1 pa13md0 pa12md1 pa12md0 pacrl1 pa11md1 pa11md0 pa10md1 pa10md0 pa9md1 pa9md0 pa8md1 pa8md0 pacrl2 pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 pa4md1 pa4md0 pa3md1 pa3md0 pa2md1 pa2md0 pa1md1 pa1md0 pa0md1 pa0md0
18. list of registers rev.2.00 sep. 27, 2007 page 412 of 448 rej09b0394-0200 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ? ? ? ? ? ? ? ? port b pbdr ? ? pb5dr pb4dr pb3dr pb2dr ? ? ? ? ? ? ? ? ? ? pbior ? ? pb5ior pb4 ior pb3 ior pb2 ior ? ? ? ? pb5md2 pb4md2 pb3md2 pb2md2 ? ? pbcr1 ? ? ? ? ? ? ? ? ? ? ? ? pb5md1 pb5md0 pb4md1 pb4md0 pbcr2 pb3md1 pb3md0 pb2md1 pb2md0 ? ? ? ? pe15dr pe14dr pe13dr pe12dr pe11dr pe10dr pe9dr pe8dr pedrl pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr port e pf15dr pf14dr pf13dr pf12dr pf11dr pf10dr pf9dr pf8dr port f pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr pe15ior pe14 ior pe13 ior pe12 ior pe11 ior pe10 ior pe9 ior pe8 ior peiorl pe7ior pe6ior pe5ior pe4ior pe3ior pe2ior pe1ior pe0ior ? ? ? ? ? ? ? ? peiorh ? ? pe21ior pe20ior pe19ior pe18ior pe17ior pe16ior port e pe15md1 pe15md0 pe14md1 pe14md0 pe13md1 pe13md0 pe12md1 pe12md0 pecrl1 pe11md1 pe11md0 pe10md1 pe10md0 pe9md1 pe9md0 pe8md1 pe8md0 pe7md1 pe7md0 pe6md1 pe6md0 pe5md1 pe5md0 pe4md1 pe4md0 pecrl2 pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 ? ? ? ? pe21md1 pe21md0 pe20md1 pe20md0 pecrh pe19md1 pe19md0 pe18md1 pe18md0 pe17md1 pe17md0 pe16md1 pe16md0 ? ? ? ? ? ? ? ? pedrh ? ? pe21dr pe20dr pe19dr pe18dr pe17dr pe16dr ? ? ? ? ? ? ? ? ? ? poe3f poe2f poe1f poe0f ? ? ? pie mtu icsr1 poe3m1 poe3m0 poe2m1 poe2m0 poe1m1 poe1m0 poe0m1 poe0m0 osf ? ? ? ? ? oce oie ocsr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pgdr ? ? ? ? pg3dr pg2dr pg1dr pg0dr port g ? ? ? ? ? ? ? ? ? ?
18. list of registers rev.2.00 sep. 27, 2007 page 413 of 448 rej09b0394-0200 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module ? ? ? ? ? ? ? ? cmstr ? ? ? ? ? ? str1 str0 ? ? ? ? ? ? ? ? cmcsr_0 cmf cmie ? ? ? ? cks1 cks0 cmcnt_0 cmcor_0 ? ? ? ? ? ? ? ? cmcsr_1 cmf cmie ? ? ? ? cks1 cks0 cmcnt_1 cmt cmcor_1 ? ? ? ? ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d addr8 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr9 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr10 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr11 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr12 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr13 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr14 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr15 ad1 ad0 ? ? ? ? ? ? adcsr_0 adf adie adm1 adm0 ? ch2 ch1 ch0 adcsr_1 adf adie adm1 adm0 ? ch2 ch1 ch0 adcr_0 trge cks1 cks0 adst adcs ? ? ? adcr_1 trge cks1 cks0 adst adcs ? ? ? ? ? ? ? ? ? ? ? ? ?
18. list of registers rev.2.00 sep. 27, 2007 page 414 of 448 rej09b0394-0200 register abbreviation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module tcsr ovf wt/ it tme ? ? cks2 cks1 cks0 wdt tcnt rstcsr wovf rste rsts ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sbycr ssby hiz ? ? ? ? ? irqel syscr ? ? ? ? ? ? ? rame ? ? ? ? mstp27 mstp26 ? ? mstcr1 ? ? ? ? mstp19 mstp18 ? ? power-down state ? ? mstp13 mstp12 ? ? ? ? mstcr2 ? ? mstp5 mstp4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mturwe ? ? ? ? ? bsc bcr1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? adtsr ? ? ? ? trg1s1 trg1s0 trg0s1 trg0s0 a/d ? ? ? ? ? ? ? ? ? ?
18. list of registers rev.2.00 sep. 27, 2007 page 415 of 448 rej09b0394-0200 18.3 register states in each operating mode register abbreviation power-on reset manual reset software standby module standby sleep module smr_2 initialized held initialized initialized held brr_2 initialized held initialized initialized held scr_2 initialized held initialized initialized held tdr_2 initialized held initialized initialized held ssr_2 initialized held initialized initialized held rdr_2 initialized held initialized initialized held sdcr_2 initialized held initialized initialized held sci (channel 2) smr_3 initialized held initialized initialized held brr_3 initialized held initialized initialized held scr_3 initialized held initialized initialized held tdr_3 initialized held initialized initialized held ssr_3 initialized held initialized initialized held rdr_3 initialized held initialized initialized held sdcr_3 initialized held initialized initialized held sci (channel 3) tcr_3 initialized held initialized initialized held tcr_4 initialized held initialized initialized held tmdr_3 initialized held initialized initialized held tmdr_4 initialized held initialized initialized held tiorh_3 initialized held initialized initialized held tiorl_3 initialized held initialized initialized held tiorh_4 initialized held initialized initialized held mtu (channels 3 and 4) tiorl_4 initialized held initialized initialized held tier_3 initialized held initialized initialized held tier_4 initialized held initialized initialized held toer initialized held initialized initialized held tocr initialized held initialized initialized held tgcr initialized held initialized initialized held tcnt_3 initialized held initialized initialized held tcnt_4 initialized held initialized initialized held tcdr initialized held initialized initialized held tddr initialized held initialized initialized held
18. list of registers rev.2.00 sep. 27, 2007 page 416 of 448 rej09b0394-0200 register abbreviation power-on reset manual reset software standby module standby sleep module tgra_3 initialized held initialized initialized held tgrb_3 initialized held initialized initialized held tgra_4 initialized held initialized initialized held tgrb_4 initialized held initialized initialized held tcnts initialized held initialized initialized held tcbr initialized held initialized initialized held tgrc_3 initialized held initialized initialized held tgrd_3 initialized held initialized initialized held tgrc_4 initialized held initialized initialized held tgrd_4 initialized held initialized initialized held tsr_3 initialized held initialized initialized held tsr_4 initialized held initialized initialized held tstr initialized held initialized initialized held tsyr initialized held initialized initialized held mtu (channels 3 and 4) tcr_0 initialized held initialized initialized held tmdr_0 initialized held initialized initialized held tiorh_0 initialized held initialized initialized held tiorl_0 initialized held initialized initialized held tier_0 initialized held initialized initialized held tsr_0 initialized held initialized initialized held tcnt_0 initialized held initialized initialized held tgra_0 initialized held initialized initialized held tgrb_0 initialized held initialized initialized held tgrc_0 initialized held initialized initialized held tgrd_0 initialized held initialized initialized held tcr_1 initialized held initialized initialized held tmdr_1 initialized held initialized initialized held tior_1 initialized held initialized initialized held tier_1 initialized held initialized initialized held tsr_1 initialized held initialized initialized held mtu (channel 0) tcnt_1 initialized held initialized initialized held
18. list of registers rev.2.00 sep. 27, 2007 page 417 of 448 rej09b0394-0200 register abbreviation power-on reset manual reset software standby module standby sleep module tgra_1 initialized held initialized initialized held tgrb_1 initialized held initialized initialized held tcr_2 initialized held initialized initialized held tmdr_2 initialized held initialized initialized held tior_2 initialized held initialized initialized held tier_2 initialized held initialized initialized held tsr_2 initialized held initialized initialized held tcnt_2 initialized held initialized initialized held mtu (channel 2) tgra_2 initialized held initialized initialized held tgrb_2 initialized held initialized initialized held ipra initialized initialized held ? held iprd initialized initialized held ? held ipre initialized initialized held ? held iprf initialized initialized held ? held iprg initialized initialized held ? held iprh initialized initialized held ? held icr1 initialized initialized held ? held isr initialized initialized held ? held ipri initialized initialized held ? held icr2 initialized initialized held ? held intc padrl initialized held held ? held port a paiorl initialized held held ? held pacrl3 initialized held held ? held pacrl1 initialized held held ? held pacrl2 initialized held held ? held pbdr initialized held held ? held port b pbior initialized held held ? held pbcr1 initialized held held ? held pbcr2 initialized held held ? held pedrl initialized held held ? held port e pfdr held held held ? held port f
18. list of registers rev.2.00 sep. 27, 2007 page 418 of 448 rej09b0394-0200 register abbreviation power-on reset manual reset software standby module standby sleep module peiorl initialized held held ? held port e peiorh initialized held held ? held pecrl1 initialized held held ? held pecrl2 initialized held held ? held pecrh initialized held held ? held pedrh initialized held held ? held icsr1 initialized held held held held ocsr initialized held held held held mtu pgdr held held held ? held port g cmstr initialized held initialized initialized held cmcsr_0 initialized held initialized initialized held cmcnt_0 initialized held initialized initialized held cmcor_0 initialized held initialized initialized held cmcsr_1 initialized held initialized initialized held cmcnt_1 initialized held initialized initialized held cmt cmcor_1 initialized held initialized initialized held addr8 initialized held initialized initialized held a/d addr9 initialized held initialized initialized held addr10 initialized held initialized initialized held addr11 initialized held initialized initialized held addr12 initialized held initialized initialized held addr13 initialized held initialized initialized held addr14 initialized held initialized initialized held addr15 initialized held initialized initialized held adcsr_0 initialized held initialized initialized held adcsr_1 initialized held initialized initialized held adcr_0 initialized held initialized initialized held adcr_1 initialized held initialized initialized held tcsr initialized initialized held ? held wdt tcnt initialized initialized held ? held rstcsr initialized held initialized ? held
18. list of registers rev.2.00 sep. 27, 2007 page 419 of 448 rej09b0394-0200 register abbreviation power-on reset manual reset software standby module standby sleep module sbycr initialized initialized held ? held syscr initialized held held ? held power-down state mstcr1 initialized held held ? held mstcr2 initialized held held ? held bcr1 initialized held held ? held bsc adtsr initialized held held ? held a/d
18. list of registers rev.2.00 sep. 27, 2007 page 420 of 448 rej09b0394-0200
19. electrical characteristics rev.2.00 sep. 27, 2007 page 421 of 448 rej09b0394-0200 section 19 electrical characteristics 19.1 absolute maximum ratings table 19.1 shows the absolute maximum ratings. table 19.1 absolute maximum ratings item symbol rating unit power supply voltage v cc ?0.3 to +7.0 v extal pin vin ?0.3 to v cc +0.3 v input voltage all pins other than analog input and extal pins vin ?0.3 to v cc +0.3 v analog supply voltage av cc ?0.3 to +7.0 v analog input voltage v an ?0.3 to av cc +0.3 v standard product * ?20 to +75 operating temperature wide temperature-range product * t opr ?40 to +85 c storage temperature t stg ?55 to +125 c [operating precautions] operating the lsi in excess of the absolute maximum ratings may result in permanent damage. note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 422 of 448 rej09b0394-0200 19.2 dc characteristics table 19.2 dc characteristics conditions: v cc = 4.0 to 5.5 v, av cc = 4.0 to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)*, t a = ?40 c to +85 c (wide temperature-range product)* item symbol min typ max unit measurement conditions res , mres , nmi, fwp, md3 to md0 v cc ?0.7 ? v cc +0.3 v extal v ih v cc ?0.7 ? v cc +0.3 v a/d port 2.2 ? av cc +0.3 v input high-level voltage (except schmitt trigger input voltage) other input pins 2.2 ? v cc +0.3 v res , mres , nmi, fwp, md3 to md0, extal ?0.3 ? 0.5 v input low-level voltage (except schmitt trigger input voltage) other input pins v il ?0.3 ? 0.8 v v t+ v cc ?0.5 ? v cc +0.3 v v t? ?0.3 ? 1.0 v schmitt trigger input voltage irq3 to irq0 , poe3 to poe0 , tclka to tclkd, tioc0a to tioc0d, tioc1a, tioc1b, tioc2a, tioc2b, tioc3a to tioc3d, tioc4a to tioc4d v t+ ?v t? 0.4 ? ? v res , mres , nmi, fwp, md3 to md0 ? ? 1.0 a vin = 0.5 to v cc ?0.5 v ports f and g ? ? 1.0 a vin = 0.5 to av cc ?0.5 v input leak current other input pins | i in | ? ? 1.0 a vin = 0.5 to v cc ?0.5 v three-state leak current (while off) port a, b, e | i tsi | ? ? 1.0 a vin = 0.5 to v cc ?0.5 v v cc ?0.5 ? ? v i oh = ?200 a output high- level voltage all output pins v oh v cc ?0.5 ? ? v i oh = ?1 ma all output pins ? ? 0.4 v i ol = 1.6 ma output low- level voltage pe9, pe11 to pe15 v ol ? ? 1.5 v i ol = 15 ma pull-up resistor pa15 to pa12, pe21 to pe16 r pull 20 50 80 k
19. electrical characteristics rev.2.00 sep. 27, 2007 page 423 of 448 rej09b0394-0200 item symbol min typ max unit measurement conditions res ? ? 80 pf nmi ? ? 50 pf input capacitance all other input pins c in ? ? 20 pf vin = 0 v = 1 mhz ta = 25 c clock 1:1 ? 110 130 ma = 40 mhz normal operation clock 1:1/2 ? 100 120 ma = 40 mhz clock 1:1 ? 70 90 ma = 40 mhz sleep clock 1:1/2 ? 60 80 ma = 40 mhz ? 1 10 a t a 50 c current consumption standby i cc ? ? 50 a 50 c < t a during a/d conversion, a/d converter idle state ? 3 5 ma analog supply current during standby ai cc ? ? 5 a ram standby voltage v ram 2.0 ? ? v v cc [operating precautions] 1. when the a/d converter is not used, the av cc , and av ss pins should not be open. 2. the current consumption is measured when v ih min = v cc ?0.5 v, v il = 0.5 v, with all output pins unloaded. note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 424 of 448 rej09b0394-0200 table 19.3 permitted output current values conditions: v cc = 4.0 v to 0.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)* 1 , t a = ?40 c to +85 c (wide temperature-range product)* 1 item symbol min typ max unit output low-level permissible current (per pin) i ol ? ? 2.0 * 2 ma output low-level permissible current (total) i ol ? ? 110 ma output high-level permissible current (per pin) ?i oh ? ? 2.0 ma output high-level permissible current (total) ?i oh ? ? 25 ma [operating precautions] to assure lsi reliability, do not exceed the output values listed in this table. note: 1. see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. i ol = 15 ma (max) about the pins pe9, pe11 to pe15. however, three pins at most are permitted to have simultaneously i ol > 2.0 ma among these pins.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 425 of 448 rej09b0394-0200 19.3 ac characteristics 19.3.1 test conditions for the ac characteristics input reference levels high level: v ih minimum value, low level: v il maximum value output reference levels high level: 2.0 v, low level: 0.8 v i ol i oh c l v ref v dut output lsi output pin c l is a total value that includes the capacitance of measurement equipment, and is set as follows: 30 pf: irqout 30 pf: port output pins and peripheral module output pins other than the above it is assumed that i ol = 1.6 ma, i oh = 200 a in the test conditions. 30 pf figure 19.1 output load circuit
19. electrical characteristics rev.2.00 sep. 27, 2007 page 426 of 448 rej09b0394-0200 19.3.2 clock timing table 19.4 shows the clock timing. table 19.4 clock timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)*, t a = ?40 c to +85 c (wide temperature-range product)* item symbol min max unit figures operating frequency f op 10 40 mhz figure 19.2 clock cycle time t cyc 25 250 ns clock low-level pulse width t cl 4 ? ns clock high-level pulse width t ch 4 ? ns clock rise time t cr ? 5 ns clock fall time t cf ? 5 ns extal clock input frequency f ex 4 10.0 mhz figure 19.3 extal clock input cycle time t excyc 100 250 ns extal clock input low-level pulse width t exl 45 ? ns extal clock input high-level pulse width t exh 45 ? ns extal clock input rise time t exr ? 5 ns extal clock input fall time t exf ? 5 ns reset oscillation settling time t osc1 10 ? ms figure 19.4 standby return oscillation settling time t osc2 10 ? ms clock cycle time for on-chip peripheral modules t pcyc 25 100 ns ? note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 427 of 448 rej09b0394-0200 t cyc t ch t cf t cr v oh ck v oh 1/2v cc 1/2v cc v oh v ol v ol t cl figure 19.2 system clock timing t excyc t exh t exf t exr v ih extal v ih 1/2v cc 1/2v cc v ih v il v il t exl figure 19.3 extal clock input timing ck v cc v cc min t osc1 res figure 19.4 oscillation settling time
19. electrical characteristics rev.2.00 sep. 27, 2007 page 428 of 448 rej09b0394-0200 19.3.3 control signal timing table 19.5 shows control signal timing. table 19.5 control signal timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)* 1 , t a = ?40 c to +85 c (wide temperature-range product)* 1 item symbol min max unit figures res rise time, fall time t resr , t resf ? 200 ns figure 19.5 res pulse width t resw 25 ? t cyc figure 19.6 res setup time t ress 19 ? ns mres pulse width t mresw 20 ? t cyc mres setup time t mress 19 ? ns md3 to md0, fwp setup time t mds 20 ? t cyc nmi rise time, fall time t nmir , t nmiif ? 200 ns nmi setup time t nmis 19 ? ns figure 19.7 irq3 to irq0 setup time * 2 (edge detection) t irqes 19 ? ns irq3 to irq0 setup time * 2 (level detection) t irqls 19 ? ns nmi hold time t nmih 19 ? ns irq3 to irq0 hold time t irqeh 19 ? ns irqout output delay time t irqod ? 100 ns figure 19.8 [operating precautions] notes: 1. see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. the res , mres , nmi and irq3 to irq0 signals are asynchronous inputs, but when the setup times shown here are observed, the signals are considered to have been changed at clock rise ( res , mres ) or fall (nmi and irq3 to irq0 ). if the setup times are not observed, detection of these signals may be delayed until the next clock rise or fall.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 429 of 448 rej09b0394-0200 t ress t mds v oh v ih v ih v ih v il v il v il t ress t resw ck md3 to md0 fwp res figure 19.5 reset input timing ck mres t mresw t mress t mress v ih v il v il figure 19.6 reset input timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 430 of 448 rej09b0394-0200 v ih v ih v il v il t nmis t nmih v ih v ol v ol v il v il t irqes t irqeh t irqls ck nmi irq edge irq level figure 19.7 interrupt signal input timing t irqod v oh v ol t irqod ck irqout v oh figure 19.8 interrupt signal output timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 431 of 448 rej09b0394-0200 19.3.4 multi-function timer pulse unit (mpu) timing table 19.6 shows multi-function timer pulse unit timing. table 19.6 multi-function timer pulse unit timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product*), t a = ?40 c to +85 c (wide temperature-range product*) item symbol min max unit figures output compare output delay time t tocd ? 100 ns figure 19.9 input capture input setup time t tics 19 ? ns timer input setup time t tcks 20 ? ns figure 19.10 timer clock pulse width (single edge specified) t tckwh/l 1.5 ? t pcyc timer clock pulse width (both edges specified) t tckwh/l 2.5 ? t pcyc timer clock pulse width (phase count mode) t tckwh/l 2.5 ? t pcyc note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. ck output compare output input capture input t tocd t tics figure 19.9 mtu input/output timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 432 of 448 rej09b0394-0200 ck tclka to tclkd t tcks t tcks t tckwh t tckwl figure 19.10 mtu clock input timing 19.3.5 i/o port timing table 19.7 shows i/o port timing. table 19.7 i/o port timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product*), t a = ?40 c to +85 c (wide temperature-range product*) item symbol min max unit figures port output data delay time t pwd ? 100 ns figure 19.11 port input hold time t prh 19 ? ns port input setup time t prs 19 ? ns [operating precautions] the port input signals are asynchronous. they are, however, considered to have been changed at ck clock fall with two-state intervals shown in figure 19.11. if the setup times shown here are not observed, detection may be delayed until the clock fall two states after that timing. note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 433 of 448 rej09b0394-0200 t prs t prh t pwd ck port (read) port (write) figure 19.11 i/o port input/output timing 19.3.6 watchdog timer (wdt) timing table 19.8 shows watchdog timer timing. table 19.8 watchdog timer timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)*, t a = ?40 c to +85 c (wide temperature-range product)* item symbol min max unit figures wdtovf delay time t wovd ? 100 ns figure 19.12 note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. t wovd t wovd v oh v oh ck wdtovf figure 19.12 wdt timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 434 of 448 rej09b0394-0200 19.3.7 serial communication interface (sci) timing table 19.9 shows serial communication interface timing. table 19.9 serial communica tion interface timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)*, t a = ?40 c to +85 c (wide temperature-range product)* item symbol min max unit figures input clock cycle t scyc 4 ? t pcyc figure 19.13 input clock cycle (clock sync) t scyc 6 ? t pcyc input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t pcyc input clock fall time t sckf ? 1.5 t pcyc transmit data delay time t txd ? 100 ns figure 19.14 received data setup time t rxs 100 ? ns received data hold time t rxh 100 ? ns [operating precautions] the inputs and outputs are asynchronous in asynchronous mode, but as shown in figure 19.14, the received data is considered to have been changed at ck clock rise (two-clock intervals). the transmit signals change with a reference of ck clock rise (two-clock intervals). note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. t sckw v ih v ih v ih v ih v il v il v il sck2, sck3 t sckr t sckf t scyc figure 19.13 input clock timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 435 of 448 rej09b0394-0200 t scyc sck2, sck3 (input/output) txd2, txd3 (transmit data) rxd2, rxd3 (receive data) sci input/output timing (clock synchronous mode) t txd t rxs t rxh v oh v oh t 1 ck txd2, txd3 (transmit data) rxd2, rxd3 (receive data) sci input/output timing (asynchronous mode) t n t txd t rxs t rxh figure 19.14 sci input/output timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 436 of 448 rej09b0394-0200 19.3.8 output enable (poe) timing table 19.10 output enable timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product*), t a = ?40 c to +85 c (wide temperature-range product*) item symbol min max unit figures poe input setup time t poes 100 ? ns figure 19.15 poe input pulse width t poew 1.5 ? t cyc note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. ck poe input t poes t poew figure 19.15 poe input/output timing 19.3.9 a/d converter timing table 19.11 shows a/d converter timing. table 19.11 a/d converter timing conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product*), t a = ?40 c to +85 c (wide temperature-range product*) item symbol min typ max unit figure external trigger input start delay time t trgs 50 ? ? ns figure 19.16 note: * see page 2 for correspondence of the standard product, wide temperature-range product, and product model name.
19. electrical characteristics rev.2.00 sep. 27, 2007 page 437 of 448 rej09b0394-0200 ck adtrg input adcr (adst = 1 set) 3 to 5 states t trgs v oh figure 19.16 external trigger input timing
19. electrical characteristics rev.2.00 sep. 27, 2007 page 438 of 448 rej09b0394-0200 19.4 a/d converter characteristics table 19.12 shows a/d converter characteristics. table 19.12 a/d converter characteristics conditions: v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (standard product)* 1 , t a = ?40 c to +85 c (wide temperature-range product)* item min typ max unit resolution 10 10 10/5.4 bit a/d conversion time ? ? 6.7 * 2 /5.4 * 3 s analog input capacitance ? ? 20 pf permitted analog signal source impedance ? ? 3/1 * 3 k non-linear error ? ? 3.0 * 2 / 5.0 * 3 lsb offset error ? ? 3.0 * 2 / 5.0 * 3 lsb full-scale error ? ? 3.0 * 2 / 5.0 * 3 lsb quantization error ? ? 0.5 lsb absolute error ? ? 4.0 * 2 / 6.0 * 3 lsb notes: 1. see page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. value when (cks1, 0) = (1, 1) and t pcyc = 50 ns 3. value when (cks1, 0) = (1, 1) and t pcyc = 40 ns
appendix a pin states rev.2.00 sep. 27, 2007 page 439 of 448 rej09b0394-0200 appendix a pin states the initial values differ in each mcu operating mode. for details, refer to section 13, pin function controller (pfc). table a.1 pin states pin function pin state reset state power-down state type pin name power-on manual software standby sleep clock xtal o o l o extal i i i i pllcap i i i i system control res i i i i mres z i z * 2 i wdtovf o * 3 o o o operation mode control md0 to md3 i i i i fwp i i i i interrupt nmi i i i i irq0 to irq3 z i z * 4 i irqout z o k * 1 o mtu tclka to tclkd z i z i tioc0a to tioc0d tioc1a, tioc1b tioc2a, tioc2b tioc3a, tioc3c z i/o k * 1 i/o tioc3b, tioc3d tioc4a to tioc4d z i/o z * 2 i/o port control poe0 to poe3 z i z i sci sck2, sck3 z i/o z i/o rxd2, rxd3 z i z i txd2, txd3 z o o * 1 o
appendix a pin states rev.2.00 sep. 27, 2007 page 440 of 448 rej09b0394-0200 pin function pin state reset state power-down state type pin name power-on manual software standby sleep an8 to an15 z i z i a/d converter adtrg z i z i i/o port pa0 to pa15 pb2 to pb5 pe0 to pe8, pe10, pe16 to pe21 z i/o k * 1 i/o pe9, pe11 to pe15 z i/o z * 2 i/o pf8 to pf15 z i z i pg0 to pg3 z i z i legend: i: input o: output h: high-level output l: low-level output z: high impedance k: input pins become high-impedance, and output pins retain their state. notes: 1. when the hiz bit in sbycr is set to 1, the output pins enter their high-impedance state. 2. those pins multiplexed with large-curr ent pins (pe9, pe11 to pe15) unconditionally enter their high-impedance state. 3. this pin operates as an input pin during a power-on reset. this pin should be pulled up to avoid malfunction. 4. this pin operates as an input pin when the irqel bit in sbycr is cleared to 0.
appendix b product lineup rev.2.00 sep. 27, 2007 page 441 of 448 rej09b0394-0200 appendix b product lineup product type part no. package (package code) SH7101 mask rom version standard product hd6437101 qfp-80 (fp-80q)
appendix b product lineup rev.2.00 sep. 27, 2007 page 442 of 448 rej09b0394-0200
appendix c package dimensions rev.2.00 sep. 27, 2007 page 443 of 448 rej09b0394-0200 appendix c package dimensions the package dimension that is shown in the renesas semiconductor package data book has priority. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 0.83 14 1.6 0.10 0 8 0.65 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.10 0.25 3.05 17.0 17.2 17.4 2.70 14 0.30 0.15 0.6 0.8 1.0 0.12 17.4 17.2 17.0 0.83 reference symbol dimension in millimeters min nom max l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l h e * 1 * 2 * 3 m x y 40 41 60 61 21 20 f 1 80 d e d e p z z b h d h e detail f 1 1 2 c l a l a a p 1 1 terminal cross section b c b c p-qfp80-14x14-0.65 1.2g mass[typ.] fp-80q/fp-80qv prqp0080jd-a renesas code jeita package code previous code figure c.1 fp-80q
appendix c package dimensions rev.2.00 sep. 27, 2007 page 444 of 448 rej09b0394-0200
index rev.2.00 sep. 27, 2007 page 445 of 448 rej09b0394-0200 index a/d conversion time............................... 335 a/d converter ......................................... 325 absolute maximum ratings..................... 421 address error exception processing .......... 60 address map ............................................. 45 addressing modes..................................... 20 buffer operation...................................... 145 bus state controller ................................... 87 byte........................................................... 15 cascaded operation................................. 149 clock m ode............................................... 43 clock pulse generator ............................... 47 clocked synchronous communication .... 313 compare match....................................... 139 compare match timer.............................. 343 continuous s can mode ............................ 333 control registers........................................ 13 crystal resonator...................................... 47 data formats............................................. 15 delayed branch instructions...................... 17 exception processing ................................ 53 exception processing state........................ 42 exception processing vector table ............ 55 external clock ........................................... 49 free-running co unters ............................. 138 general illegal instruction exception processing ................................................. 63 general registers ....................................... 13 global base register (gbr)..................... 14 high-impedance state ............................. 252 i/o ports ..................................................371 illegal slot exception processing ...............63 input capt ure ...........................................141 interrupt controller ....................................67 interrupt exception processing ..................61 interrupt response time..............................84 interval timer mode ...............................271 irq interrupts ...........................................75 longword..................................................15 manual reset..............................................58 mask rom..............................................383 module standb y mode .............................398 multi-function timer pulse unit .................91 multiply-and-accumulate registers (mac) ..................................................................14 multiprocessor communication function.307 nmi interrupt ............................................75 on-chip peripheral module interrupts .......77 operating modes .......................................43 overrun er ror...........................................303 periodic counter ......................................137 phase counti ng mode ..............................156 pin function c ontroller ............................353 pin functions in each operating mode .....353 power-down modes.................................387 power-down state......................................42 power-on reset...........................................57 procedure register (pr)............................14 processing states .......................................41 program counter (pc) ..............................14 program execution state ............................42 pwm mode .............................................150
index rev.2.00 sep. 27, 2007 page 446 of 448 rej09b0394-0200 ram ....................................................... 385 reading from tcnt, tcsr, and rstcsr ................................................................ 274 registers adcr ......................... 330, 406, 413, 418 adcsr....................... 329, 406, 413, 418 addr................................................. 328 adtsr ....................... 332, 407, 414, 419 bcr1 ............................ 89, 4 07, 414, 419 brr ............................ 287, 401, 408, 415 cmcnt ...................... 346, 405, 413, 418 cmcor...................... 346, 405, 413, 418 cmcsr ...................... 345, 405, 413, 418 cmstr....................... 344, 405, 413, 418 icr1 ............................. 69, 4 04, 411, 417 icr2 ............................. 70, 4 04, 411, 417 icsr1 ......................... 254, 405, 412, 418 ipr ................................ 73, 4 04, 411, 417 isr ................................ 72, 4 04, 411, 417 mstcr....................... 393, 407, 414, 419 ocsr.......................... 257, 405, 412, 418 pacrl ....................... 361, 404, 411, 417 padrl ....................... 372, 404, 411, 417 paiorl...................... 360, 404, 411, 417 pbcr .......................... 365, 405, 412, 417 pbdr.......................... 374, 404, 412, 417 pbior ........................ 364, 405, 412, 417 pecrh ....................... 366, 405, 412, 418 pecrl........................ 366, 405, 412, 418 pedrh ....................... 377, 405, 412, 418 pedrl........................ 377, 405, 412, 417 peiorh...................... 366, 405, 412, 418 peiorl ...................... 366, 405, 412, 418 pfdr .......................... 379, 405, 412, 417 pgdr.......................... 381, 405, 412, 418 rdr ............................ 280, 401, 408, 415 rsr..................................................... 280 rstcsr ............................. 268, 406, 418 sbycr ....................... 390, 406, 414, 419 scr............................. 283, 401, 408, 415 sdcr .......................... 287, 401, 408, 415 smr ............................ 281, 401, 408, 415 ssr ............................. 285, 401, 408, 415 syscr........................ 392, 407, 414, 419 tcbr .......................... 135, 402, 409, 416 tcdr.......................... 135, 402, 409, 415 tcnt ......................... 126, 265, 402, 406, ................................ 408, 414, 415, 418 tcnts........................ 135, 402, 409, 416 tcr............................... 98, 4 01, 408, 415 tcsr .......................... 266, 406, 414, 418 tddr.......................... 135, 402, 409, 415 tdr ............................ 280, 401, 408, 415 tgcr.......................... 133, 402, 408, 415 tgr ............................ 127, 402, 409, 416 tier............................ 122, 402, 408, 415 tior ........................... 104, 401, 408, 415 tmdr ......................... 102, 401, 408, 415 tocr.......................... 131, 402, 408, 415 toer .......................... 130, 402, 408, 415 tsr ..................... 124, 280, 402, 409, 416 tstr........................... 127, 402, 409, 416 tsyr .......................... 128, 402, 409, 416 reset state ................................................. 42 reset-synchronized pwm mode............. 163 risc.......................................................... 17 serial communication interface............... 277 single m ode ............................................ 333 single-cycle scan .................................... 335 sleep mode.............................................. 395 software standby mode........................... 396 status register (sr) .................................. 13 synchronous operation............................ 142 system registers ........................................ 14 the functions of multiplexed pins........... 353 trap instruction exception processing....... 62
index rev.2.00 sep. 27, 2007 page 447 of 448 rej09b0394-0200 vector base register (vbr)..................... 14 vector numbers......................................... 77 vector table............................................... 77 watchdog timer ...................................... 263 watchdog time r mode ...........................269 word .........................................................15 writing to rstcsr ................................274 writing to tcnt and tcsr ...................273
index rev.2.00 sep. 27, 2007 page 448 of 448 rej09b0394-0200
renesas 32-bit risc microcomputer hardware manual SH7101 publication date: 1st edition, february, 2003 rev.2.00, september 27, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan.
sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0

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