1/4 rev. a structure silicon monolithic integrated circuit product series strobe charge control ic type ?fvm functions 1. built-in low vth dmos 45v 2. adjustable transformer primary- side peak current by radj pin 3. standby mode switching with the start pin. 4. includes charge complete s ignal output (full) pin. includes charge voltage detectio n (vc) pin (can be set external ly). 5. built-in thermal shutdown circuit (tsd). built-in under voltage looked out (uvlo). 6. built-in transformer secondary-side open, short protection . 7. sop 10pin package msop10 (2.9mm4.0mm0.9mm) absolute maximum ratings(ta=25) reduced by 5.70 mw/ over ta = 25. (when mounted on 74.2 mm ? 74.2 mm ? 1.6 mm, glass epoxy) recommended operating ranges parameter symbol limit unit vcc pin vcc -0.3 to 7 v sw pin vsw 45 v vc pin vc -0.3 to 7 v start pin start -0.3 t o7 v full pin full -0.3 t o7 v igbt_in pin igbt_in -0.3 to 7 v operating temperature topr ?35 to 85 storage temperature range tstg ?55 to 150 junction temperature tjmax 150 power dissipation pd 712 mw parameter symbol limit unit vcc power supply input voltage range vcc 2.5 to 5.5 v vc pin input voltage range vc -0.3 to vcc v start pin input voltage range vstart 0 to vcc v igbt_in pin input voltage range vigbt_in 0 to vcc v full pin input voltage range vfull 0 to 5.5 v sw pin current isw 0 to 2 a
2/4 rev. a electrical characteristics (ta =25vcc=v(start)=3.4 v, v(igbt _in)=0v) parameter symbol limit unit conditions min. typ. max. [overall device] vcc circuit current icc 1.6 3.2 ma circuit current standby operation istb 1 a start=0v [standby control start pin] start pin high voltage vsth 2.0 v start pin low voltage vstl 0.6 v input bias current istart 12 24 36 a start=3.4v [transformer primary -side driver block] sw pin leak current iswl D D 1 a sw=45v sw pin peak current ipeak 0.4 0.5 0.6 a radj=100k sw saturation voltage vsat 0.175 0.35 v isw=0.5a radj adjustable range radj 33 D 100 k [charging control block] max on time tonmax 25 50 100 sec max off time toffmax 12 25 50 sec [transformer secondary-side detection block] vc pin input current ivc D D 1 a vc=vcc full charge detection voltage vfullth 0.9875 1 1.0125 v full pin on resistor rfulll 0. 5 1 2 k vc=vcc,full=0.5v full pin leak current ifullh 1 a full=3.4v [protection circuit block] uvlo detect voltage vuvloth 1.95 2.1 2.25 v vcc detection uvlo hysteresis vuvlohys 120 200 280 mv [igbt driver block] output short high current ioso 90 140 200 ma igbt_in=3.4v,start=0v, igbt_out =0v output short low current iosi 30 60 90 ma igbt_in=0v,start=0v, igbt_out=3.4v igbt_in response time rise trise1 15 80 nsec igbt_in response time fall tfall1 120 200 nsec igbt_in input high voltage range1 vigbth1 2.0 D v start=0v igbt_in input high voltage range2 vigbth2 1.4 D v start=0v,vcc=3.0vto3.6v, ta=-25 to 85 igbt_in input high voltage range vigbtl D 0.6 v start=0v igbt_in sink current iigbt_in 12 24 36 a start=0v this product is not designed for normal operation within a rad ioactive environment.
3/4 rev. a block diagram logic stb uvlo tsd s r vcc uvlo q tsd tsd + - + - sdp enable max_on vcc stb s r q os full stb s r full os q 5 vref uvlo 6 start max off time 8 7 9 sdp sdp off vcc pgnd driver max on time max_on igbt_out 10 pgnd 4 2 1 vc full radj sw start igbt_in i/v 3 gnd + - off vcc stb fig.1 block diagram package (unit:mm) pin no. pin no. pin name function 1 pgnd power gnd 2 igbt_out igbt driver output 3 gnd ground pin 4 vc secondaryCside voltage detection pin 5 vcc vcc supply pin 6 start standby pin 7 igbt_in nput terminal of trigger signal for starting output of igbt driver 8 radj primary-side current control pin 9 full full charge detection flag pin 10 sw switching pin fig. 2 marking specification
4/4 rev. a cautions on use 1. absolute maximum ratings an excess in the absolute maximum ratings, such as supply volta ge, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. if any over rated value s will expect to exceed the absolute maximum ra tings, consider adding circuit protection devices, such as fuses. 2. gnd and pgnd potential ensure a minimum gnd and pgnd(except for sw pin and vc pin) pin potential in all operating conditions. in addition, ensure tha t no pins other than the gnd and pgnd pin carry a voltage less th an or equal to the gnd and pgnd pin, including during actual transient phenomena. dont use vc pin under absolute maximum rating. 3. thermal design use a thermal design that allows for a sufficient margin in lig ht of the power dissipation (pd) i n actual operating conditions . 4. protect circuit the ic does not incorporate buil t-in malfunction protection suc h as overcurrent protection, short detection, or thermal shutdo wn circuitry. for this reason, the ic may be damaged if it is shor ted or subjected to a load that exceeds the package power. the design of peripheral application circuits should reflect these potential risks. 5. inter-pin shorts and mounting errors use caution when positioning the ic for mounting on printed cir cuit boards. the ic may be damaged if there is any connection error or if positive and ground power supply terminals are reve rsed. the ic may also be damaged if pins are shorted together o r are shorted to other circuits power lines. 6. common impedance the power supply and ground lines must be as short and thick as possible to reduce line impedance. fluctuating voltage on the power ground line m ay damage the device. 7. ic pin input this is the monolithic ic and has p + isolation and p substrate for e lement isolation between each e lement. by the p layer and n layer of each element, a p-n ju nction is formed and various par asitic elements are configured. for example, in the case of a res istor and transistor being con nected to a pin as shown in fig.-3; p-n junction operates as a parasitic diode when gnd > (pin a) i n the case of the resistor, and when gnd > (pin b) in the case of the transistor (npn) also, a parasitic npn transistor operates by the n layer of ano ther element adjacent to the previous diode in the case of a transistor (npn) when gnd > (pin b). the parasitic element consequent ly emerges through the potentia l relationship because of ics structure. the parasitic element pulls interference out of the circuit which may be the cause of malfunction or destruction. therefore, excessive caution is required to avoid operation of the parasitic element which is c aused by applying voltage to an input pin lower than gnd (p boa rd), etc pin ? gnd parasitic element p substrate n p n p p pin a parasitic element fig.3 other adjacent elements parasitic element transistor (npn) gnd p substrate n p n p p pin b b n e c gnd n
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