View ML5012_5887326.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

p1/29 rev. m, may 2010 ML5012 ML5012 C 12 bit sar a/d converter features 4-pins serial control interface cs, din, dout, sck operates with 3.3v or analog adjusted voltage reference differential input programmable gain amplifier (pga) : 0 ~40.25db channel selectable differential & single end input mode 0v to vdd input range with single 2.2v to 5.0v power supply 4 mosfet switch for external loads on/off mcu programmalbe ad clock frequency from 1m to 7.8khz and ad startup time. successive ad conversion mode applications general metering application general description the ML5012 is cmos 12-bit sar a/d converter, differ ential input programmable gain amplifier and four m osfet on/off switches. a 4-pin serial control interface is easy to communicate with mcu. key specification resolution 12 bits total unadjusted error +/- 6 lsb single voltage supply 2.2v ~ 5.0v a/d conversion time 15 adclk comparison time 15 adclk mosfet current 5ma ordering information item package shipping ML5012 dice form absolute maximum ratings parameter symbol ratings units supply voltage vdd -0.3 ~ 5.5 v input voltage at any pin vin -0.3 ~ vdd + 0.3 v output voltage vio vss-0.3 ~ vin+0.3 v operation ambient temperature topr -20 ~ +70 ?c storage temperature tstg -40 ~ +90 ?c
p2/29 rev. m, may 2010 ML5012 pin function pin name i/o description vdd p positive power supply vr p reference voltage for analog input signal ce i chip enable control signal padeoc o a pulse signal of eoc (end of conversion) out1 ~ 4 o mosfet on/off switch output cs i chip select for serial interface sck i clock for serial interface din i data input for serial interface dout o data output for serial interface, tri-state o utput vss p negative supply voltage cha1 ~ cha4 i analog input channels for positive di fferential input of pga chb1 ~ chb4 i analog input channels for positive/ne gative differential input of pga agnd p analog gnd block diagram
p3/29 rev. m, may 2010 ML5012 bonding diagram pin function pin (x,y) description pin (x,y) description 1 cha1 (85,1110) analog input channel 14 dout (1660,290) data output 2 cha2 (85,980) analog input channel 15 out4 (1660,465) mosfet switch 3 cha3 (85,855) analog input channel 16 out3 (1660,620) mosfet switch 4 cha4 (85,725) analog input channel 17 out2 (1660,780) mosfet switch 5 chb1 (85,600) analog input channel 18 out1 (1660,935) mosfet switch 6 chb2 (85,470) analog input channel 19 agnd (1660,1090) analog gnd 7 chb3 (85,345) analog input channel 20 agnd (1660,1200) analog gnd 8 chb4 (85,215) analog input channel 21 vr (1415,1270) reference voltage 9 ce (85,85) chip enable 22 vr (1300,1270) reference voltage 10 cs (1095,85) chip select 23 vdd (1115,1270) positive supply voltage 11 din (1225,85) data input for serial interface 24 vdd (1000,1270) positive supply voltage 12 sck (1355,85) clock for serial interface 25 vss (855,1270) negative supply voltage 13 padeoc (1660,115) end of conversion 26 vss (740,1270) negative supply voltage note: dice size : 1.72 x 1.34 mm 2
p4/29 rev. m, may 2010 ML5012 allowable operating conditions ta = 0 o c to 70 o c unless otherwise specified ta=25 c parameter symbol conditions min typ max units supply voltage vdd 2.2 5.5 v analog input voltage vin 0 5.5 v oscillator frequency fosc 100 khz electrical characteristics 1. a/d converter & pga digital levels and dc specif ication vdd = 3.0v, vr = 3.0v dc, ta = 25 o c unless otherwise specified ta=25 c parameter symbol conditions min typ max units ivdd 0.60 0.70 ma isb vdd = 2.0v ~ 3.3v, a/d inactive 1 ua ad active 0.05 ma operating current ivr osc. active, a/d inactive 0.15 ma ioff(+) analog multiplexer vdd = 3.0v, vin = 3.0v 0 ua off channel leakage current ioff(-) analog multiplexer vdd = 3.0v, vin = 0v 0 ua pga input offset voff vdd = 3.0v, vcha = vchb = 1.5v differential input mode -5 5 mv 2. digital levels and dc specification vdd = 3.0v, vr = 3.0v dc, ta = 25 o c unless otherwise specified ta=25 c parameter symbol conditions min typ max units logical 1 input voltage vih 2.2 3.0 v logical 0 input voltage vil 0 0.7 v logical 1 output voltage voh ioh = 1ma 2.2 v logical 0 output voltage vol iol = -1ma 0.7 v
p5/29 rev. m, may 2010 ML5012 3. a/d converter and comparator timing specificatio n vdd = 3.0v, vr = 3.0v dc, ta = 25 o c unless otherwise specified ta=25 c parameter symbol conditions min typ max units a/d conversion time tadc fosc = 100khz 150 us comparator conversion time tcomp fosc = 100khz 150 us 4. a/d conversion specification vdd = 3.0v, vr = 3.0v dc, ta = 25 o c unless otherwise specified ta=25 c parameter symbol conditions min typ max units resolution res pga gain = 0db 10 bit a/d error err pga gain = 0db, fosc = 2mhz, vdd = vr = 3.3v +/- 4 +/- 6 lsb 5. mosfet switch specification vdd = 3.0v, vr = 3.0v dc, ta = 25 o c unless otherwise specified ta=25 c parameter symbol conditions min typ max units high output voltage voh vr = 3.0v, ioh = -5ma 2.9 v
p6/29 rev. m, may 2010 ML5012 block diagram of pga and a/d converter
p7/29 rev. m, may 2010 ML5012 function description 1. serial interface command there are 5 commands for serial interface, stch, pga_ ac, wr_ad, wr_osc, rr_ac and rr_ad as shown the below command code map. command code map command code r/w c1 c2 c3 c4 interface command function description w 0 0 0 0 wr_stch stch register. enable oscillator for a/d, select pga input channel, enable mosfet and select a/d range w 0 0 0 1 wr_pga_ac set pga gain & write a/d confi guration w 0 0 1 0 wr_ad write data to a/d register w 0 0 1 1 wr_sys sys register. set ad conversion frequency , adc startup time, successive ad mode, reference voltage to agnd or (vr-agnd)/2 r 1 0 0 0 rr_stch read stch register value r 1 0 0 1 rr_pga_ac read pga gain & a/d configurati on r 1 0 1 0 rr_ad read data from a/d register r 1 0 1 1 rr_sys read sys register value
p8/29 rev. m, may 2010 ML5012 1-1. wr_stch command. select pga input channel (chab_sel & chb_sel), enable oscillator (enosc) for a/d, ad range selection (ad_range) and mosfet enable contr ol (m1_en, m2_en, m3_en & m4_en). the following diagram shows the timing of sending w r_stch command. the din data in c1~c4 cycle is wr_stch command code. the din data in c5 cycle is oscillator enable bit, d1 1 = enosc. the din data in c6 cycle is ad range selection bit, d10 = ad_range the din data in c7~c9 cycle is channel ab selection, d [9:7] = chab_sel[2:0]. the din data in c10~c12 cycle is channel b selection, d[6:4] = chb_sel[2:0]. the din data in c13 cycle is mosfet 1 enable, d3= m1 _en. the din data in c14 cycle is mosfet 2 enable, d2= m2 _en. the din data in c15 cycle is mosfet 3 enable, d1= m3 _en. the din data in c16 cycle is mosfet 4 enable, d0= m4 _en.
p9/29 rev. m, may 2010 ML5012 stch register operations table control function d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 operations 0 rc oscillator disable oscillator enable (enosc) 1 rc oscillator enable 0 ad range : 0 ~ 4,095 ad range select (ad_range) 1 ad range : -2,047 ~ 2,047 0 0 0 chab = cha1 0 0 1 chab = cha2 0 1 0 chab = cha3 0 1 1 chab = cha4 1 0 0 chab = chb1 1 0 1 chab = chb2 1 1 0 chab = chb3 channel ab select chab_sel[2:0] 1 1 1 chab = chb4 0 0 0 chb = chb1 0 0 1 chb = chb2 0 1 0 chb = chb3 0 1 1 chb = chb4 channel b select chb_sel[2:0] 1 x x chb = agnd 0 mosfet 1 disable mosfet 1 enable (m1_en) 1 mosfet 1 enable 0 mosfet 2 disable mosfet 2 enable (m2_en) 1 mosfet 2 enable 0 mosfet 3 disable mosfet 3 enable (m3_en) 1 mosfet 3 enable 0 mosfet 4 disable mosfet 4 enable (m4_en) 1 mosfet 4 enable note : x = dont care
p10/29 rev. m, may 2010 ML5012 1-2. wr_pga_ac command. write data into pga gain registe r & set a/d configuration register the following diagram shows the timing diagram of w riting data into pga gain register & setting a/d con figuration register. the din data in c1~c4 cycle is pga_ac gain command code . the din data in c5 cycle is a/d converter enable bit, d11 = en. the din data in c6 cycle is storage of comparison resu lt bit, d10 = rslt. the din data in c7 cycle is start/stop bit of a/d con verter, d9 = s/s. the din data in c8 cycle is operation mode bit of a/d converter, d8 = md. the din data in c9~c16 cycles are setting the pga ga in for pga gain register, d[7:0] = pga[7:0]. a/d converter configuration register table control function d11 d10 d9 d8 operations 0 a/d converter disable a/d converter enable (en) 1 a/d converter enable 0 input voltage * pga gain < internal reference volta ge storage of comparison result (rslt) 1 input voltage * pga gain > internal reference volta ge 0 stop a/d conversion or comparison operation start/stop of a/d converter (s/s) 1 start a/d conversion or comparison operation 0 a/d conversion mode operation mode of a/d converter (md) 1 comparison mode
p11/29 rev. m, may 2010 ML5012 pga gain register table control gain code function d7 d6 d5 d4 d3 d2 d1 d0 decimal hex pga gain factor 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1.4 0 0 0 0 0 0 1 0 2 2 1.8 0 0 0 0 0 0 1 1 3 3 2.2 0 0 0 0 0 1 0 0 4 4 2.6 . . . 0 0 0 0 0 1 1 1 7 7 3.8 0 0 0 0 1 0 0 0 8 8 4.2 0 0 0 0 1 0 0 1 9 9 4.6 . . . 0 0 0 0 1 1 1 1 15 f 7 0 0 0 1 0 0 0 0 16 10 7.4 0 0 0 1 0 0 0 1 17 11 7.8 . . . 0 0 0 1 1 1 1 1 31 1f 13.4 0 0 1 0 0 0 0 0 32 20 13.8 0 0 1 0 0 0 0 1 33 21 14.2 . . . 0 0 1 1 1 1 1 1 63 3f 26.2 0 1 0 0 0 0 0 0 64 40 26.6 0 1 0 0 0 0 0 1 65 41 27 . . . 0 1 1 1 1 1 1 1 127 7f 51.8 1 0 0 0 0 0 0 0 128 80 52.2 1 0 0 0 0 0 0 1 129 81 52.6 . . . 1 1 1 1 1 1 1 0 254 fe 102.6 pga gain 1 1 1 1 1 1 1 1 255 ff 103 note: pga gain = 1 + gain code * 0.4 eg. if gain code = 100, pga gain = 1 + 0.4*100 = 41.
p12/29 rev. m, may 2010 ML5012 1-3. wr_ad command. write data into a/d register the following diagram shows the timing diagram of w riting data into a/d register. the din data in c1~c4 cycle is wr_ad command code. the din data in c5~c16 cycles are input data for a/ d register, d[11:0] = a/d[11:0].
p13/29 rev. m, may 2010 ML5012 1-4. wr_sys command. set ad conversion clock frequency, ad startup time, successive ad conversion mode, pga reference voltage to agnd or (vr-agnd)/2 the following diagram shows the timing diagram of w riting data to control the ad conversion frequency. the din data in c1~c4 cycle is wr_sys command code. the din data in c5~c7 cycles are output data of adc c lock, d[11:9] = ad_clock[2:0]. the din data in c8~c9 cycles are output data of start time, d[8:7] = sta_opt[1:0]. the din data in c10~c13 are reserved. the din data in c14 is successive ad mode enable, d[ 2] = smode. the din data in c15 is reference agnd connection enab le, d[1] = vgnd_en. the din data in c16 is reference (vr-agnd)/2 connecti on enable, d[0] = vmid_en. control function d11 d10 d9 d8 d7 d2 d1 d0 operations 0 0 0 ad clock frequency = 1mhz 0 0 1 ad clock frequency = 500khz (default) 0 1 0 ad clock frequency = 250khz 0 1 1 ad clock frequency = 125khz 1 0 0 ad clock frequency = 62.5khz 1 0 1 ad clock frequency = 31.25khz 1 1 0 ad clock frequency = 15.625khz set ad clock frequency (ad_clock[2:0]) 1 1 1 ad clock frequency = 7.8125khz 0 0 startup time = 1000us (default) 0 1 startup time = 800us 1 0 startup time = 600us set ad converter startup time (sta_opt[1:0]) 1 1 startup time = 400us 0 successive ad conversion mode disable set successive ad conversion mode (smode) 1 successive ad conversion mode enable 0 pga reference connect to agnd enable pga reference connect to vmin (vmin_en) 1 pga reference connect to vmin - reserved -
p14/29 rev. m, may 2010 ML5012 1-5 rr_stch command. read stch register value the following diagram shows the timing diagram of r eading data from the stch register. the din data in c1~c4 cycle is rr_stch command code. the dout data in c5 cycle is rc oscillator enable bit , d11 = enosc. the dout data in c6 cycle is ad range select, d10 = a d_range. the dout data in c7~c9 cycle is channel ab select, d9 C d7 = chab_sel[2:0]. the dout data in c10~c12 cycle is channel b select, d6 C d4 = chb_sel[2:0]. the dout data in c13~c16 cycles are mosfet enable, d 3 = m1_enb, d2 = m2_enb, d1 = m3_enb, d0 = m4_enb.
p15/29 rev. m, may 2010 ML5012 1-6 rr_pga_ac command. read data from a/d configuration register the following diagram shows the timing diagram of r ead data from a/d configuration register. the din data in c1~c4 cycle is rr_ac command code. the din data in c5 cycle is a/d converter enable bit, d11 = en. the din data in c6 cycle is storage of comparison resu lt bit, d10 = rslt. the din data in c7 cycle is start/stop bit of a/d con verter, d9 = s/s. the din data in c8 cycle is operation mode bit of a/d converter, d8 = md. the din data in c9~c16 cycles are pga gain setting, d[7:0] = pga[7:0]. a/d converter configuration register table control function d11 d10 d9 d8 operations 0 a/d converter disable a/d converter enable (en) 1 a/d converter enable 0 input voltage * pga gain < internal reference volta ge storage of comparison result (rslt) 1 input voltage * pga gain > internal reference volta ge 0 stop a/d conversion or comparison operation start/stop of a/d converter (s/s) 1 start a/d conversion or comparison operation 0 a/d conversion mode operation mode of a/d converter (md) 1 comparison mode
p16/29 rev. m, may 2010 ML5012 1-7 rr_ad command. read data from a/d register. the following diagram shows the timing diagram of r ead data from a/d register. the din data in c1~c4 cycle is rr_ad command code. the dout data in c5~c16 cycles are output data from a /d register, d[11:0] = a/d[11:0]. 1-8 rr_sys command. read data from sys register. the following diagram shows the timing diagram of r ead data from a/d register. the din data in c1~c4 cycle is rr_sys command code. the dout data in c5~c7 cycles are output data of adc clock, d[11:9] = ad_clock[2:0]. the dout data in c8~c9 cycles are output data of sta rt time, d[8:7] = sta_opt[1:0]. the dout data in c10~c13 are reserved. the dout data in c14 is successive ad mode enable, d [2] = smode. the dout data in c15 is reference agnd connection enab le, d[1] = vgnd_en. the dout data in c16 is reference (vr-agnd)/2 connecti on enable, d[0] = vmid_en.
p17/29 rev. m, may 2010 ML5012 2. chip enable and chip reset the ce input pin is an input for chip enabled contro lled and chip reset controlled. when ce=0, the chip will enter reset condition. in this time, all functions stops op erating and the dout pin becomes tri-state output, and padeoc becomes low output. for reducing the power consumpti on, it is recommended to reset ce pin as 0 when adc function is inactive. when ce=1, the chip will wake up from reset condition . all functions have ready to operate and the dout pin becomes output data. the chip will get into waiting s tate to receive the command from serial interface. since no power on reset circuitry is built in this chi p, it is necessary to set ce pin to 0 after power on state to initiate this chip. 3. pga offset initialization after system power up, ML5012 will initialize the p ga offset register automatically. 4. system register control the ad_clock controls the ad conversion clock frequency ; slower clock can save power, but longer conversion t ime. the sta_opt, is the startup time option, the shorte r the startup time, the sooner will get the result, but the ad result may not be stable. smode is the successive ad conversion mode, when ena bled, the adc will not be automatically disabled aft er each ad conversion, otherwise, the adc will be disabled a fter each ad conversion to save power, when enabled , and the sta_opt will not have effect after the first convers ion, as the adc is always enabled. vgnd_en, vref = agnd and vmid_en, vref = (vr-agn d)/2 are selecting the vref voltage to the pga, fro m the below output voltage equation of the pga. vref gain pga v v out pga chb cha + ? = _ ) ( _ then the pga_out will input to the adc directly.
p18/29 rev. m, may 2010 ML5012 when selecting the ad_range, its actually selecting the reference zero point. for ad_range is 0 C 4096, the reference zero point is agnd, when ad_range is -2047 ~+2046, the reference zero point is (vr-agnd)/2, so users can select your target ad_range based on the above c alculation. if ad_range = 0 ( ) [ ] vref gain pga v v agnd vr out ad chb cha + ? ? = _ 4096 _ if ad_range = 1 ( ) [ ] 2048 _ 4096 _ ? + ? ? = vref gain pga v v agnd vr out ad chb cha
p19/29 rev. m, may 2010 ML5012 5. a/d conversion mode the a/d conversion mode converts the analog voltage o n the a/d pin into the digital value. the input ana log voltage is successively compared with weighted voltages from the capacitor array. digitized conversion data (12-bi t) are stored into 12 bits a/d register a/d[11:0]. the time required for the converter to complete conve rsion is as follows: conversion duration = oscillator clock period x 15 example: (a). 150us (oscillator clock at 100khz) (b). 75us (oscillator clock at 200khz) caution: while in the a/d conversion mode, do not use a/d re gister a/d[11:0] to store other data. 5-1. selecting pga input channel ab & b, pga gain & a/d enable control executing stch command to enable oscillator and then select one of pga input channel ab (ie. cha1~4 or chb1~4) & input channel b (ie. chb1~4 or agnd) fo r differential or single end analog input. setting of oscillator enable pins before using a/d conversion, enosc bit must be set t o 1 to start-up the oscillator in order to provide the clock for a/d conversion mode. it is recommended to turn off the oscillator when a /d conversion mode is completed in order to reduce the power consumption. setting of ad output range setting of ad output range output range ad_range = 0 0 ~ 4,095 ad_range = 1 -2,047 ~ 2,047 please refer to section 3-4 for more details.
p20/29 rev. m, may 2010 ML5012 setting of pga input channel a and b case 1 : differential analog input chab_sel[2:0] chb_sel[2:0] bit 2 bit 1 bit 0 channel ab bit 2 bit 1 bit 0 channel b 0 0 0 cha1 0 0 0 chb1 0 0 1 cha2 0 0 1 chb2 0 1 0 cha3 0 1 0 chb3 0 1 1 cha4 0 1 1 chb4 case 2 : single end analog input chab_sel[2:0] chb_sel[2:0] bit 2 bit 1 bit 0 channel ab bit 2 bit 1 bit 0 channel b 0 0 0 cha1 0 0 1 cha2 0 1 0 cha3 0 1 1 cha4 1 0 0 chb1 1 0 1 chb2 1 1 0 chb3 1 1 1 chb4 1 0 0 agnd setting of pga gain executing pga_ac command to set pga gain from 0db to 40.25db. please refer to section 1-2 for more details.
p21/29 rev. m, may 2010 ML5012 5-2. starting a/d conversion a/d conversion starts according to the bit setting of the a/d configuration register. all settings specifi ed by the contents of the a/d configuration register wh ich shall set at the same time when a/d conversion starts. execute pga_ac command and delivers the desir ed value into a/d configuration register. please refer to section 1-2. for the execution of pga_ac co mmand. setting to start a/d conversion setting of a/d configuration register operation en, s/s = 1 start of a/d conversion md = 0 set operation mode to a/d conversion when setting a/d configuration register for a/d conv ersion start, the bits of a/d configuration register other than bits shown in the table above ca n be any value. these bits will not affect a/d conversion. in contrast, do not modify contents of the a/d config uration register, the ad output range and pga gain value while the a/d converter is running. 5-3. indication of end of a/d conversion at the end of a/d conversion the bit s/s and bit en are cleared. monitoring one of these bits detects the end of a/d conversion. there is an external pin (pad eoc) to indicate the end of conversion. when the conversion is completed, an h pulse signal will b e outputted to this pin. 5-4. storing digitized data the digital equivalent of analog input voltage (a/d ed data) consisting of 12 bits is stored into a/d register : a/d[11:0]. a/ded data stored in a/d register : a/d[11:0] input voltage and a/ded data at ad_range = 0 (ie. a /d data = 0 ~ 4,095) input voltage = a/d[11:0] / 4,096 *vr (v) / pga gai n note: a/ded data (unsigned 12 bits) = converts into decimal value
p22/29 rev. m, may 2010 ML5012 input voltage and a/ded data at ad_range = 1 (ie. a /d data = -2,047 ~ 2,047) a/ded data is a 12 bits signed data which a/d[11] sh ows the sign of a/ded data as follow : case 1 : if a/d[11] = 0, input voltage = + a/d[10:0] / 2048 *vr (v) / pga gain case 2 : if a/d[11] = 1, input voltage = - a/d[10:0] / 2048 *vr (v) / pga gain note: a/ded data (signed 12 bits) = converts into d ecimal value executing rr_ad command could read out the contents o f a/d register to dout pin. please refer to section 1-5. for the operation of rr_ad command.
p23/29 rev. m, may 2010 ML5012 6. comparison mode the comparison mode compares the level of analog vol tage coming from channel ab and b with internal volt age set by the a/d configuration register, storing the resul t into the bit rslt of a/d configuration register. the time required for the converter to complete conve rsion is as follows: conversion duration = oscillator clock period x 15 example: (a). 150us (oscillator clock at 100khz) (b). 75us (oscillator clock at 200khz) 6-1. selecting pga channel ab & b input pin, pga ga in & a/d enable control executing stch command to enable oscillator and then s elect one of pga input channel ab & b for differential analog input or single end input. setting of oscillator enable pins before using a/d conversion, enosc bit must be set t o 1 to start-up the oscillator in order to provide the clock for a/d conversion mode. it is recommended to turn off the oscillator when a /d conversion mode is completed in order to reduce the power consumption. setting of ad output range setting of ad output range output range ad_range = 0 0 ~ 4,095 ad_range = 1 -2,047 ~ 2,047 please refer to section 4-2 for more details.
p24/29 rev. m, may 2010 ML5012 setting of pga input channel a and b case 1 : differential analog input chab_sel[2:0] chb_sel[2:0] bit 2 bit 1 bit 0 channel ab bit 2 bit 1 bit 0 channel b 0 0 0 cha1 0 0 0 chb1 0 0 1 cha2 0 0 1 chb2 0 1 0 cha3 0 1 0 chb3 0 1 1 cha4 0 1 1 chb4 case 2 : single end analog input chab_sel[2:0] chb_sel[2:0] bit 2 bit 1 bit 0 channel ab bit 2 bit 1 bit 0 channel b 0 0 0 cha1 0 0 1 cha2 0 1 0 cha3 0 1 1 cha4 1 0 0 chb1 1 0 1 chb2 1 1 0 chb3 1 1 1 chb4 1 0 0 agnd setting of pga gain executing pga gain command to set pga gain from 0db t o 40.8db. please refer to section 1-2 for more details. 6-2. setting internal comparison voltage the internal voltage data to be compared with the an alog a/d input is stored into the a/d register a/d[11:0], the same location as for storing a/ded da ta. the same register are used for storing a/ded data and internal voltage data.
p25/29 rev. m, may 2010 ML5012 executing wr_ad command to deliver the internal volt age data and store the data into a/d register. internal reference voltage data stored in a/d regist er: a/d[11:0] internal reference voltage at ad output range = 0 (a /d data : 0 ~ 4,095) comparison reference voltage = a/d[11:0] / 4096 * vr (v) note: a/d register value (unsigned 12 bits) = conve rt register value into decimal number internal reference voltage at ad output range = 1 (a /d data : -2,047 ~ 2,047) register value is a 12 bits signed data which a/d[11 ] shows the sign of a/d register value as follow : case 1 : if a/d[11] = 0, comparison reference voltage = + a/d[10:0] / 2048 *vr (v) case 2 : if a/d[11] = 1, comparison reference voltage = - a/d[10:0] / 2048 *vr (v) note: a/d register value (signed 12 bits) = convert register value into decimal number. 6-3. starting comparison the comparison starts when the bit s/s of a/d configu ration register is set. the operation mode should be set upon starting of the comparison. all a/d confi guration register settings are made at the same time. setting to start comparison setting of a/d configuration register operation en, s/s = 1 start of a/d conversion md = 1 set operation mode to comparison mode settings of bits other than those necessary to start comparison will not affect the comparison operation. please do not modify a/d configuration re gister, ad output range and pga gain value while the a/d converter is running.
p26/29 rev. m, may 2010 ML5012 6-4. indication of end of comparison at the end of a/d conversion the bit s/s and bit en are cleared. monitoring one of these bits detects the end of comparison. there is an external pin (padeoc) to indicate the en d of conversion. when the conversion is completed, an h pulse signal will be outputted to this pin. 6-5. storing comparison result the result of comparison sets the bit rslt of a/d con figuration register to either 1 or 0 depending on the level of the input voltages as shown below. rslt result rslt=0 input voltage * pga gain < internal reference voltage rslt=1 input voltage * pga gain > internal reference voltage when the input voltage * pga gain is equal to the i nternal reference voltage, the level of bit rslt is undefined. 7. setting mosfet enable when ce pin set to 1, all of the mosfets are disabl e. executing stch command to enable the mosfet accordi ngly. each of these mosfets could be enabled or disable ind ividually. m1_en m2_en m3_en m4_en mosfet 0 0 0 0 all mosfets turn off 1 0 0 0 mosfet 1 turn on 0 1 0 0 mosfet 2 turn on 0 0 1 0 mosfet 3 turn on 0 0 0 1 mosfet 4 turn on 1 1 1 1 all mosfets turn on
p27/29 rev. m, may 2010 ML5012 8. summary of a/d converter operations typical operation procedure of a/d converter is summa rized as below the bit represented by [x] is user s ettable. 8-1. general procedure of using a/d conversion mode the procedure below is to use the a/d converter in th e a/d conversion mode. steps below are to convert the analog voltage between input channel cha1 and c hb1 in differential input mode to digital value at pga gain = 0db with a/d output range from -2,047 to 2,047, and vref = (vr C agnd)/2 operation setting 1 start-up oscillator enosc = 1 2 set a/d output range : -2,047 to 2,047 ad_range = 1 3 set vref = (vr C agnd)/2 vmid_en = 1 4 select differential analog input cha1 and chb1 chab_sel[2:0] = 000 and chb_sel[2:0] = 000 5 set pga gain = 0 db pga_gain register = 0000 000 0 6 specify operation mode and start a/d converter a/d configuration register = 1010 this procedure starts the a/d converter. when a/d con version time has elapsed, the a/d converter stops and stores the result in a/d register a/d[11:0]. en d of the operation can be verified by reading bits s /s or en that should be 0.
p28/29 rev. m, may 2010 ML5012 8-2. general procedure of using comparison mode this procedure below is to compare the analog voltage from the analog voltage between cha2 and agnd in single end input mode at pga gain = 20.48db with internal reference digital value at a/d output range from 0 to 4,095, and vref = agnd operation setting 1 start-up oscillator enosc = 1 2 set a/d output range : 0 to 4,095 ad_range = 0 3 set vref = agnd vgnd = 1 3 select single end analog input cha2 and agnd chab_sel[2:0] = 001 and chb_sel[2:0] = 100 4 set pga gain = 20.48 db pga_gain register = 1000 0000 5 store 12 bits of comparison data at a/d register a /d[11:0] = xxxx xxxx xxxx 6 specify operation mode and start a/d converter a/d configuration register =1011 this procedure starts the a/d converter. when the con version time has elapsed, the converter stops and stores the result of comparison into bit rslt of a/ d configuration register as follow: rslt = 1 when the analog input is higher than the reference voltage rslt = 0 when the analog input is lower than the reference voltage
p29/29 rev. m, may 2010 ML5012 typical application circuit disclaimer: minilogic reserves the rights to change the informa tion and specifications without prior notice. the i nformation presented in this document does not form part of any quotatio n or contract, is believed to be accurate and relia ble and may be changed without notice. no liability will be accepted by th e publisher for any consequence of its use.

▲Up To Search▲

Price & Availability of ML5012

	To Download ML5012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .