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the powerpc name, the powerpc logotype, and powerpc 603 are trademarks of international business machines corporation, used by motorola under license from international business machines corporation. flotherm is a registered trademark of flomerics ltd., uk. this document contains information on a new product under development by motorola and ibm. motorola and ibm reserve the right to motorola inc., 1997. all rights reserved. portions hereof international business machines corporation, 1991?997. all rights reserved. 603 hardware speci?ations change or discontinue this product without notice.
2 603 hardware specifications 1.1 overview this section describes the features of the 603 and describes brie? how those units interact. the 603 is the ?st low-power implementation of the powerpc microprocessor family of risc microprocessors. the 603 implements the powerpc architecture as it is speci?d for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and ?ating- point data types of 32 and 64 bits (single-precision and double-precision). for 64-bit powerpc implementations, the powerpc architecture provides additional 64-bit integer data types, 64-bit addressing, and related features. the 603 provides four software controllable power-saving modes. three of the modes (the doze, nap, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603 to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. the 603 is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance; however, the 603 makes completion appear sequential. the 603 integrates ?e execution units?n integer unit (iu), a ?ating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu), and a system register unit (sru). the ability to execute ?e instructions in parallel and the use of simple instructions with rapid execution times yield high ef?iency and throughput for 603-based systems. most integer instructions execute in one clock cycle. the fpu is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. the 603 provides independent on-chip, 8-kbyte, two-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and caches use a least recently used (lru) replacement algorithm. the 603 also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array during block translation. in accordance with the powerpc architecture, if an effective address hits in both the tlb and bat array, the bat translation takes priority. the 603 has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603 interface protocol allows multiple masters to compete for system resources through a central external arbiter. the 603 provides a three-state coherency protocol that supports the exclusive, modi?d, and invalid cache states. this protocol is a compatible subset of the mesi (modi?d/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. the 603 supports single-beat and burst data transfers for memory accesses; it also supports both memory-mapped i/o and direct-store addressing. the 603 uses an advanced, 3.3-v cmos process technology and maintains full interface compatibility with ttl devices.
603 hardware specifications 3 1.2 features this section summarizes features of the 603s implementation of the powerpc architecture. major features of the 603 are as follows: high-performance, superscalar microprocessor as many as three instructions issued and retired per clock as many as ?e instructions in execution per clock single-cycle execution for most instructions pipelined fpu for all single-precision and most double-precision operations five independent execution units and two register ?es bpu featuring static branch prediction a 32-bit iu fully ieee 754-compliant fpu for both single- and double-precision operations lsu for data transfer between data cache and gprs and fprs sru that executes condition register (cr) and special-purpose register (spr) instructions thirty-two gprs for integer operands thirty-two fprs for single- or double-precision operands high instruction and data throughput zero-cycle branch capability (branch folding) programmable static branch prediction on unresolved conditional branches instruction fetch unit capable of fetching two instructions per clock from the instruction cache a six-entry instruction queue that provides lookahead capability independent pipelines with feed-forwarding that reduces data dependencies in hardware 8-kbyte data cache?wo-way set-associative, physically addressed; lru replacement algorithm 8-kbyte instruction cache?wo-way set-associative, physically addressed; lru replacement algorithm cache write-back or write-through operation programmable on a per page or per block basis bpu that performs cr lookahead operations address translation facilities for 4-kbyte page size, variable block size, and 256-mbyte segment size a 64-entry, two-way set-associative itlb a 64-entry, two-way set-associative dtlb four-entry data and instruction bat arrays providing 128-kbyte to 256-mbyte blocks software table search operations and updates supported through fast trap mechanism 52-bit virtual address; 32-bit physical address facilities for enhanced system performance a 32- or 64-bit split-transaction external data bus with burst transfers support for one-level address pipelining and out-of-order bus transactions bus extensions for direct-store operations
4 603 hardware specifications integrated power management low-power 3.3 volt design internal processor/bus clock multiplier that provides 1/1, 2/1, 3/1 and 4/1 ratios three power saving modes?oze, nap, and sleep automatic dynamic power reduction when internal functional units are idle in-system testability and debugging features through jtag boundary-scan capability 1.3 general parameters the following list provides a summary of the general parameters of the 603. technology 0.5 m cmos (four-layer metal) die size 11.5 mm x 7.4 mm (85 mm 2 ) transistor count 1.6 million logic design fully-static package surface mount, 240-pin cqfp power supply 3.3 5% v dc 1.4 electrical and thermal characteristics this section provides the ac and dc electrical speci?ations and thermal characteristics for the 603. 1.4.1 dc electrical characteristics the tables in this section describe the 603 dc electrical characteristics. table 1 provides the absolute maximum ratings. table 1. absolute maximum ratings characteristic symbol value unit core supply voltage vdd ?.3 to 4.0 v pll supply voltage avdd ?.3 to 4.0 v input voltage v in ?.3 to 5.5 v storage temperature range t stg ?5 to 150 c notes: 1. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed vdd by more than 2.5 v at anytime including during power-on reset.
603 hardware specifications 5 table 2 provides the recommended operating conditions for the 603. table 3 provides the package thermal characteristics for the 603. table 4 provides the dc electrical characteristics for the 603. table 2. recommended operating conditions characteristic symbol value unit core supply voltage vdd 3.135 to 3.465 v pll supply voltage avdd 3.135 to 3.465 v input voltage v in ?.3 to 5.5 v die-junction temperature t j 0 to 105 c notes : these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. table 3. package thermal characteristics characteristic symbol value rating motorola wire-bond cqfp package die junction-to-case thermal resistance (typical) q jc 2.2 c/w ibm c4-cqfp package die junction-to-heat sink base thermal resistance (typical) q js 1.1 c/w note: refer to section 1.8, ?ystem design information, for more details about thermal management. table 4. dc electrical specifications vdd = 3.3 5% v dc, gnd = 0 v dc, 0 t j 105 c characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 2.2 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current, v in = 3.465 v v in = 5.5 v i in ?0 m a1 i in tbd m a1 hi-z (off-state) leakage current, v in = 3.465 v v in = 5.5 v i tsi ?0 m a1 i tsi tbd m a1 output high voltage, i oh = ? ma v oh 2.4 v
6 603 hardware specifications table 5 provides the power consumption for the 603. output low voltage, i ol = 14 ma v ol 0.4 v capacitance, v in = 0 v, f = 1 mhz (excludes ts , abb , dbb , and ar tr y )c in 10.0 pf 2 capacitance, v in = 0 v, f = 1 mhz (for ts , abb , dbb , and ar tr y )c in 15.0 pf 2 notes : 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk), and jtag signals. 2. capacitance is periodically sampled rather than 100% tested. table 5. power consumption vdd = 3.3 5% v dc, gnd = 0 v dc, 0 t j 105 c cpu clock: sysclk processor core frequency unit 66.67 mhz 80 mhz full-on mode typical maximum 1.8 2.0 w 2.5 2.9 w doze mode * typical 740 800 mw nap mode * typical 160 160 mw sleep mode * typical 125 130 mw sleep mode?ll disabled * typical 70 40 mw sleep mode?ll and sysclk disabled * typical 2 2 mw note: these values apply for all valid pll_cfg[0?] settings and do not include output driver power (ovdd) or analog supply power (avdd). ovdd power is system dependent but is typically 10% of vdd. worst-case avdd = 15 mw. table 4. dc electrical specifications (continued) vdd = 3.3 5% v dc, gnd = 0 v dc, 0 t j 105 c characteristic symbol min max unit notes
603 hardware specifications 7 1.4.2 ac electrical characteristics this section provides the ac electrical characteristics for the 603. after fabrication, parts are sorted by maximum processor core frequency as shown in section 1.4.2.1, ?lock ac speci?ations?and tested for conformance to the ac speci?ations for that frequency. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0?] signals. pll_cfg signals should be set prior to power up and not altered afterwards. these speci?ations are for 66 mhz core frequency with 33 mhz bus (66c?:1 bus mode), 66 mhz bus (66a?:1 bus mode), and 80 mhz core frequency with 40 mhz bus (80c?:1 bus mode). parts are sold by maximum processor core frequency and bus mode; see section 1.9, ?rdering information. 1.4.2.1 clock ac speci?ations table 6 provides the clock ac timing speci?ations as de?ed in figure 1. table 6. clock ac timing specifications vdd = 3.3 5% v dc, gnd = 0 v dc , 0 t j 105 c num characteristic 66c 66a 80c unit notes min max min max min max processor frequency 16.67 66.0 16.67 66.0 16.67 80.0 mhz 1 vco frequency 120 240 120 240 120 240 mhz sysclk (bus) frequency 16.67 33.0 16.67 66.0 16.67 40.0 mhz 1 sysclk cycle time 40.0 60.0 30.0 60.0 25.0 60.0 ns 2,3 sysclk rise and fall time 2.0 2.0 2.0 ns 2 4 sysclk duty cycle measured at 1.4 v 40.0 60.0 40.0 60.0 40.0 60.0 % 3 sysclk jitter 150 150 150 ps 4 603 internal pll-relock time 100 100 100 m s 3, 5 notes: 1. caution : the sysclk frequency and pll_cfg[0?] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?] signal description in section 1.8, ?ystem design information, for valid pll_cfg[0?] settings, and to section 1.9, ?rdering information, for available frequencies and part numbers. 2. rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 3. timing is guaranteed by design and characterization, and is not tested. 4. the total input jitter (short term and long term combined) must be under 150 ps. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum amount of time required for pll lock after a stable vdd and sysclk are reached during the power-on reset sequence. this speci?ation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 m s) during the power-on reset sequence.
8 603 hardware specifications figure 1 provides the sysclk input timing diagram. figure 1. sysclk input timing diagram 1.4.2.2 input ac speci?ations table 7 provides the input ac timing speci?ations for the 603 as de?ed in figure 2 and figure 3. table 7. input ac timing specifications vdd = 3.3 5% v dc, gnd = 0 v dc , 0 t j 105 c num characteristic 66c 66a 80c unit notes min max min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 4.0 2.5 3.5 ns 2 10b all other inputs valid to sysclk (input setup) 6.0 4.5 5.5 ns 3 10c mode select inputs valid to hreset (input setup) (for dr tr y , qa ck and tlbisync ) 8 * t sysclk 8 * t sysclk 8 * t sysclk ns 4, 5, 6 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 1.0 1.0 ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 1.0 1.0 ns 3 11c hreset to mode select inputs invalid (input hold) (for dr tr y , qa ck , and tlbisync ) 0??ns4, 6 notes: 1. all input speci?ations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk. both input and output timings are measured at the pin (see figure 2). 2. address/data/transfer attribute input signals are composed of the following?[0?1], ap[0?], tt[0?], tc[0?], tbst , tsiz[0?], gbl , dh[0?1], dl[0?1], dp[0?]. 3. all other input signals are composed of the following?s , xa ts , abb , dbb , ar tr y , bg , aa ck , dbg , dbw o , t a , dr tr y , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qa ck , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 3). this speci?ation is for con?uration-mode only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 m s) during the power-on reset sequence. 5. t sysclk is the period of the external clock (sysclk) in nanoseconds. 6. these values are guaranteed by design, and are not tested. vm cvil cvih sysclk 2 3 1 4 vm = midpoint voltage (1.4 v) 4
603 hardware specifications 9 figure 2 provides the input timing diagram for the 603. figure 2. input timing diagram figure 3 provides the mode select input timing diagram for the 603. figure 3. mode select input timing diagram vm sysclk all inputs vm = midpoint voltage (1.4 v) 10a 10b 11a 11b mode pins hreset vm vm = midpoint voltage (1.4 v) 10c 11c
10 603 hardware specifications 1.4.2.3 output ac speci?ations table 8 provides the output ac timing speci?ations for the 603 as de?ed in figure 4. table 8. output ac timing specifications 1 vdd = 3.3 5% v dc, gnd = 0 v dc, cl = 50 pf, 0 t j 105 c num characteristic 66c 66a 80c unit notes min max min max min max 12 sysclk to output driven (output enable time) 1.0 1.0 1.0 ns 13a sysclk to output valid (5.5 v to 0.8 v?ts , abb , ar tr y , dbb ) 13.0 10.0 12.0 ns 4 13b sysclk to output valid (ts , abb , ar tr y , dbb ) 12.0 9.0 11.0 ns 6 14a sysclk to output valid (5.5 v to 0.8 v?all except ts , abb , ar tr y , dbb ) 15.0 12.0 14.0 ns 4 14b sysclk to output valid (all except ts , abb , ar tr y , dbb ) 13.0 10.0 12.0 ns 6 15 sysclk to output invalid (output hold) 1.5 1.5 1.5 ns 3 16 sysclk to output high impedance (all except ar tr y , abb , dbb ) 11.5 8.5 10.5 ns 17 sysclk to abb , dbb , high impedance after precharge 1.0 1.2 1.0 t sysclk 5,7 18 sysclk to ar tr y high impedance before precharge 11.0 8.0 10.0 ns 19 sysclk to ar tr y precharge enable 0.2 * t sysclk + 1.0 0.2 * t sysclk + 1.0 0.2 * t sysclk + 1.0 ns 3,5,8 20 maximum delay to ar tr y precharge 1.0 1.2 1.0 t sysclk 5,8 21 sysclk to ar tr y high impedance after precharge 2.0 2.25 2.0 t sysclk 5,8 notes: 1. all output speci?ations are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin 2. all maximum timing speci?ations assume c l = 50 pf. 3. this minimum parameter assumes c l = 0 pf. 4. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with discharging the external voltage from 5.5 v to 0.8 v instead of from vdd to 0.8 v (5 v cmos levels instead of 3.3 v cmos levels). 5. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. output signal transitions from gnd to 2.0 v or vdd to 0.8 v. 7. nominal precharge width for abb and dbb is 0.5 t sysclk . 8. nominal precharge width for ar tr y is 1.0 t sysclk .
603 hardware specifications 11 figure 4 provides the output timing diagram for the 603. figure 4. output timing diagram 1.4.3 jtag ac timing speci?ations table 9 provides the jtag ac timing speci?ations as de?ed in figure 5 through figure 8. table 9. jtag ac timing specifications (independent of sysclk) vdd = 3.3 5% v dc, gnd = 0 v dc, c l = 50 pf, 0 t j 105 c num characteristic min max unit notes tck frequency of operation 0 16 mhz 1 tck cycle time 62.5 ns 2 tck clock pulse width measured at 1.4 v 25 ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck rising edge 13 ns 1 5 trst assert time 40 ns 6 boundary-scan input data setup time 6 ns 2 sysclk 12 14 13 15 16 16 ts ar tr y abb , dbb vm vm vm = midpoint voltage (1.4 v) 15 vm 13 20 18 17 21 19 all outputs (except ts , abb , dbb , artry
12 603 hardware specifications figure 5 provides the jtag clock input timing diagram. figure 5. clock input timing diagram figure 6 provides the trst timing diagram . figure 6. trst timing diagram 7 boundary-scan input data hold time 27 ns 2 8 tck to output data valid 4 25 ns 3 9 tck to output high impedance 3 24 ns 3 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 25 ns 12 tck to tdo data valid 4 24 ns 13 tck to tdo high impedance 3 15 ns notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test signal input timing with respect to tck. 3. non-test signal output timing with respect to tck. table 9. jtag ac timing specifications (independent of sysclk) (continued) vdd = 3.3 5% v dc, gnd = 0 v dc, c l = 50 pf, 0 t j 105 c num characteristic min max unit notes tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage (1.4 v) 4 5 trst tck vm
603 hardware specifications 13 figure 7 provides the boundary-scan timing diagram. figure 7. boundary-scan timing diagram figure 8 provides the test access port timing diagram. figure 8. test access port timing diagram 6 7 input data valid 8 9 8 output data valid output data valid tck data inputs data outputs data outputs data outputs vm vm 10 11 input data valid 12 13 12 output data valid output data valid tck tdi, tms tdo tdo tdo vm vm
14 603 hardware specifications 1.5 powerpc 603 microprocessor pin assignments this section contains the pinout diagram for the 603 ceramic quad ?t pack (cqfp) package as shown in figure 9. figure 9. pinout diagram of the cqfp package gbl a1 a3 vdd a5 a7 a9 ognd gnd ovdd a11 a13 a15 vdd a17 a19 a21 ognd gnd ovdd a23 a25 a27 vdd dbw o dbg bg aa ck gnd a29 qreq ar tr y ognd vdd ovdd abb a31 dp0 gnd dp1 dp2 dp3 ognd vdd ovdd dp4 dp5 dp6 gnd dp7 dl23 dl24 ognd ovdd dl25 dl26 dl27 dl28 vdd ognd tt4 a0 a2 vdd a4 a6 a8 ovdd gnd ognd a10 a12 a14 vdd a16 a18 a20 ovdd gnd ognd a22 a24 a26 vdd dr tr y t a tea dbdis gnd a28 xa ts ts ovdd vdd ognd dbb a30 dl0 gnd dl1 dl2 dl3 ovdd vdd ognd dl4 dl5 dl6 gnd dl7 dl8 dl9 ovdd ognd dl10 dl11 dl12 dl13 vdd ovdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 ovdd gnd ognd ci wt qa ck tben tlbisync rsr v ap0 ap1 ovdd ognd ap2 ap3 cse tc0 tc1 ovdd clk_out ognd br ape dpe ckstp_out ckstp_in hreset pll_cfg0 sysclk pll_cfg1 pll_cfg2 avdd pll_cfg3 vdd gnd lssd_mode l1_tstclk l2 _tstclk trst tck tms tdi tdo tsiz0 tsiz1 tsiz2 ovdd ognd tbst tt0 tt1 sreset int smi mcp tt2 tt3 ovdd gnd ognd 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 ovdd dl29 dl30 dl31 gnd dh31 dh30 dh29 ognd ovdd dh28 dh27 dh26 dh25 dh24 dh23 ognd dh22 ovdd dh21 dh20 dh19 dh18 dh17 dh16 ognd dh15 ovdd dh14 dh13 dh12 dh11 dh10 dh9 ognd ovdd dh8 dh7 dh6 dl22 dl21 dl20 ognd ovdd dl19 dl18 dl17 dh5 dh4 dh3 ognd ovdd dh2 dh1 dh0 gnd dl16 dl15 dl14 ognd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 top view
603 hardware specifications 15 1.6 powerpc 603 microprocessor pinout listing table 10 provides the pinout listing for the 603 cqfp package. table 10. powerpc 603 microprocessor pinout listing signal name pin number active i/o a[0?1] 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 high i/o aa ck 28 low input abb 36 low i/o ap[0?] 231, 230, 227, 226 high i/o ape 218 low output ar tr y 32 low i/o avdd 209 high input bg 27 low input br 219 low output ci 237 low output clk_out 221 output ckstp_in 215 low input ckstp_out 216 low output cse 225 high output dbb 145 low i/o dbdis 153 low input dbg 26 low input dbw o 25 low input dh[0?1] 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 high i/o dl[0?1] 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 high i/o dp[0?] 38, 40, 41, 42, 46, 47, 48, 50 high i/o dpe 217 low output dr tr y 156 low input gbl 1 low i/o
16 603 hardware specifications gnd 9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 low input hreset 214 low input int 188 low input lssd_mode 1 205 low input l1_tstclk 1 204 input l2_tstclk 1 203 input mcp 186 low input ognd 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 low input ovdd 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 high input pll_cfg[0?] 213, 211, 210, 208 high input qa ck 235 low input qreq 31 low output rsr v 232 low output smi 187 low input sreset 189 low input sysclk 212 input t a 155 low input tben 234 high input tbst 192 low i/o tc[0?] 224, 223 high output tck 201 input tdi 199 high input tdo 198 high output tea 154 low input tlbisync 233 low input tms 200 high input trst 202 low input tsiz[0?] 197, 196, 195 high i/o table 10. powerpc 603 microprocessor pinout listing (continued) signal name pin number active i/o
603 hardware specifications 17 1.7 powerpc 603 microprocessor package description the following sections provide the package parameters and the mechanical dimensions for the 603. note that the 603 is currently offered in two types of cqfp packages?he motorola wire-bond cqfp and the ibm c4-cqfp. 1.7.1 motorola wire-bond cqfp package description the following sections provide the package parameters and mechanical dimensions for the motorola wire- bond cqfp package. 1.7.1.1 package parameters the package parameters for the motorola wire-bond cqfp are as provided in the following list. the package type is 32 mm x 32 mm, 240-pin ceramic quad ?t pack. package outline 32 mm x 32 mm interconnects 240 pitch 0.5 mm (20 mil) maximum module height 4.15 mm ts 149 low i/o tt[0?] 191, 190, 185, 184, 180 high i/o vdd 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 high input wt 236 low output xa ts 150 low i/o notes: 1. these are test signals for factory use only and must be pulled up to vdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. future members of the 603 family may use different ovdd and vdd input levels; for example, ovdd = 3.3 v or 5.0 v, with vdd = 2.5 v. table 10. powerpc 603 microprocessor pinout listing (continued) signal name pin number active i/o
18 603 hardware specifications 1.7.1.2 mechanical dimensions of the motorola wire-bond cqfp package figure 10 shows the mechanical dimensions for the motorola wire-bond cqfp package. figure 10. mechanical dimensions of the motorola wire-bond cqfp package *reduced pin count shown for clarity. 60 pins per side min. max. a 30.86 31.75 b 34.6 bsc c 3.75 4.15 d 0.5 bsc e 0.18 0.30 f 3.10 3.90 g 0.13 0.175 h 0.45 0.55 j 0.25 aa 1.80 ref ab 0.95 ref q 12 6 q 21 7 r 0.15 ref ? ab q i r r aa q 2 h pin 240 c a b pin 1 de *not to scale g f j die wire bonds ceramic body alloy 42 leads notes : 1. bsc?etween standard centers. 2. all measurements in mm.
603 hardware specifications 19 1.7.2 ibm c4-cqfp package description the following sections provide the package parameters and mechanical dimensions for the ibm c4-cqfp package. 1.7.2.1 package parameters the package parameters for the ibm c4-cqfp are as provided in the following list. the package type is 32 mm x 32 mm, 240-pin ceramic quad ?t pack. package outline 32 mm x 32 mm interconnects 240 pitch 0.5 mm lead plating ni au solder joint sn/pb (10/90) lead encapsulation epoxy solder-bump encapsulation epoxy maximum module height 3.1 mm co-planarity speci?ation 0.08 mm note : no solvent can be used with the c4-cqfp package. see appendix a, ?eneral handling recommendations for the c4-cqfp package,?for details.
20 603 hardware specifications 1.7.2.2 mechanical dimensions of the ibm c4-cqfp package figure 11 shows the mechanical dimensions for the ibm c4-cqfp package. figure 11. mechanical dimensions of the ibm c4-cqfp package *reduced pin count shown for clarity. 60 pins per side min max a 31.8 32.2 b 34.4 34.8 c 2.33 2.93 d 0.45 0.55 e 0.18 0.28 f 0.585 0.685 g 0.12 0.20 h 0.40 0.60 jmin 0.30 0.40 ang 0.0 5.0 rad 0.25 clip leadframe chip tape cast ceramic epoxy dam urethane solder-bump encapsulant h jmin radius 0.08 f g a b e 0.13 total s a-b -c- 0.13 total s a-b 0.08 total m a-b d -a- pin 240 pin 1 * not to scale all measurements in mm ang -b- c
603 hardware specifications 21 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the 603. 1.8.1 pll con?uration the 603 pll is con?ured by the pll_cfg[0?] signals. for a given sysclk (bus) frequency, the pll con?uration signals set the internal cpu and vco frequency of operation. the pll con?uration for the 603 is shown in table 11 for nominal frequencies. table 11. powerpc 603 microprocessor pll configuration pll_cfg[0?] cpu frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to- vco multiplier bus 16.6 mhz bus 20 mhz bus 25 mhz bus 33.3 mhz bus 40 mhz bus 50 mhz bus 66.6 mhz 0000 1x 2x 66.6 (133) 0001 1x 4x 33.3 (133) 40 (160) 50 (200) 0010 1x 8x 16.6 (133) 20 (160) 25 (200) 0100 2x 2x 66.6 (133) 80 (160) 0101 2x 4x 33.3 (133) 40 (160) 50 (200) 1000 3x 2x 60 (120) 75 (150) 1001 3x 4x 50 (200) 60 (240) 1100 4x 2x 66.6 (133) 80 (160) 0011 pll bypass 1111 clock off notes: 1. the sample bus-to-core frequencies shown are for reference only. 2. some pll con?urations may select bus, cpu, or pll frequencies which are not supported by the 603; see section 1.4.2.2, ?nput ac speci?ations, for valid sysclk frequencies. 3. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note: the ac timing speci?ations given in this document do not apply in pll-bypass mode. 4. in clock-off mode, no clocking occurs inside the 603 regardless of the sysclk input. 5. pll_cfg[0?] signals select the cpu-to-bus ratio (1:1, 2:1, 3:1, 4:1), pll_cfg[2?] signals select the cpu-to-pll multiplier (x2, x4, x8).
22 603 hardware specifications 1.8.2 pll power supply filtering the avdd power signal is provided on the 603 to provide power to the clock generation phased-lock loop. to ensure stability of the internal clock, the power supplied to the avdd input signal should be ?tered using a circuit similar to the one shown in figure 12. the circuit should be placed as close as possible to the avdd signal to ensure it ?ters out as much noise as possible. figure 12. pll power supply filter circuit 1.8.3 decoupling recommendations due to the 603s dynamic power management feature, large address and data buses, and high operating frequencies, the 603 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 603 system, and the 603 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd and ovdd pin of the 603. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 m f to provide both high- and low-frequency ?tering, and should be placed as close as possible to their associated vdd or ovdd pin. suggested values for the vdd pins?20 pf (ceramic), 0.01 m f (ceramic), and 0.1 m f (ceramic). suggested values for the ovdd pins?.01 m f (ceramic), 0.1 m f (ceramic), and 10 m f (tantalum). only smt (surface mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ovdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?00 m f (avx tps tantalum) or 330 m f (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be connected to vdd. unused active high inputs should be connected to gnd. 1.8.5 pull-up resistor requirements the 603 requires high-resistive (weak: 10 k w ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603 or other bus master. these signals are?s , abb , dbb , ar tr y . in addition, the 603 has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 k w ?0 k w ) if they are used by the system. these signals are?pe , dpe , and ckstp_out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master vdd avdd 10 w 10 m f 0 . 1 m f gnd
603 hardware specifications 23 and may ?at in the high-impedance state for relatively long periods of time. since the 603 must continually monitor these signals for snooping, this ?at condition may cause excessive power draw by the input receivers on the 603. it is recommended that these signals be pulled up through weak (10 k w ) pull-up resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are a[0?1], ap[0?], tt[0?], tbst , tsiz[0?], and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 1.8.6 thermal management information this section provides thermal management information for the ceramic quad-?t package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design?he heat sink, air?w and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods?dhesive or spring clip to holes in the printed-circuit board; see figure 13. this spring force should not exceed 5.5 pounds of force. figure 13. package exploded cross-sectional view with several heat sink options the board designer can choose between several types of heat sinks to place on the 603. there are several commercially-available heat sinks for the 603 provided by the following vendors: chip coolers inc. 800-227-0254 (usa/canada) 333 strawberry field rd. 401-739-7600 warwick, ri 02887-6979 international electronic research corporation (ierc) 818-842-7277 135 w. magnolia blvd. burbank, ca 91502 thermalloy 214-243-4321 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 adhesive wb/cqfp package or thermal interface material heat sink heat sink clip printed-circuit board
24 603 hardware specifications wake?ld engineering 617-245-5900 60 audubon rd. wake?ld, ma 01880 aavid engineering 603-528-3400 one kool path laconia, nh 03247-0440 ultimately, the ?al selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 1.8.6.1 internal package conduction resistance for this packaging technology the intrinsic thermal conduction resistance (shown in table 3) versus the external thermal resistance paths are shown in figure 14 for a package with an attached heat sink mounted to a printed-circuit board. figure 14. package with heat sink mounted to a printed-circuit board 1.8.6.2 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 15 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/ oil, ?roether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease signi?antly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the thermal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see figure 13). this spring force should not exceed 5.5 pounds of force. therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors?hermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. external resistance external resistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
603 hardware specifications 25 figure 15. thermal performance of select thermal interface material the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: dow-corning corporation 517-496-4000 dow-corning electronic materials p.o. box 0997 midland, mi 48686-0997 chomerics, inc. 617-935-4850 77 dragon court woburn, ma 01888-4850 thermagon inc. 216-741-7659 3256 west 25th street cleveland, oh 44109-1668 0 0.5 1 1.5 2 0 1020 304050607080 graphite/oil sheet (0.005 inch) silicone sheet (0.006 inch) floroether oil sheet (0.007 inch) synthetic grease bare joint specific thermal resistance (kin 2 /w) contact pressure (psi) contact pressure (psi) speci? thermal resistance (kin 2 /w)
26 603 hardware specifications loctite corporation 860-571-5100 1001 trout brook crossing rocky hill, ct 06067 ai technology (e.g., eg7655) 609-882-2332 1425 lower ferry rd trent, nj 08618 the following section provides a heat sink selection example using one of the commercially available heat sinks. 1.8.6.3 heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j = t a + t r + ( q jc + q int + q sa ) * p d where : t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet q jc is the die junction-to-case thermal resistance q int is the adhesive or interface material thermal resistance q sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device during operation the die-junction temperatures (t j ) should be maintained less than the value speci?d in table 2. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material ( q int ) is typically about 1 c/w. assuming a t a of 30 c, a t r of 5 c a cqfp package q jc = 2.2 c/w, and a power consumption (p d ) of 3.0 w, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (2.2 c/w + 1.0 c/w + r sa ) * 3.0 w for a thermalloy heat sink #2328b, the heat sink-to-ambient thermal resistance (r sa ) versus air?w velocity is shown in figure 16.
603 hardware specifications 27 figure 16. thermalloy #2328b heat sink-to-ambient thermal resistance versus airflow velocity assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 c/w, thus t j = 30 c + 5 c + (2.2 c/w +1.0 c/w + 7 c/w) * 3.0 w, resulting in a die-junction temperature of approximately 66 c which is well within the maximum operating temperature of the component. other heat sinks offered by chip coolers, ierc, thermalloy, wake?ld engineering, and aavid engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air ?w. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common ?ure- of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat ?w. the ?al die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. in addition to the component's power consumption, a number of factors affect the ?al operating die-junction temperature?ir?w, board population (local heat ?x of adjacent components), heat sink ef?iency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. to expedite system-level thermal analysis, several ?ompact thermal-package models are available within flotherm? these are available upon request. 1 2 3 4 5 6 7 8 0 0.5 1 1.5 2 2.5 3 3.5 thermalloy #2328b pin-fin heat sink (25 x 28 x 15 mm) heat sink thermal resistance ( c/w) approach airflow velocity (m/s) approach air?w velocity (m/s) heat sink thermal resistance ( c/w)
28 603 hardware specifications 1.9 ordering information this section provides the ordering information for the 603. note that the individual part numbers correspond to a speci? combination of 603 internal/bus frequencies, which must be observed to ensure proper operation of the device. for other frequency combinations, temperature ranges, power-supply tolerances package types, etc., contact your local motorola or ibm sales of?e. 1.9.1 motorola part number key figure 17 provides a detailed description of the motorola part number for the 603. figure 17. motorola part number key 1.9.2 ibm part number key figure 18 provides a detailed description of the ibm part number for the 603. figure 18. ibm part number key table 12. ordering information for the powerpc 603 microprocessor package type maximum internal frequency maximum bus frequency required pll_cfg[0?] setting part numbers motorola ibm motorola ibm wire-bond cqfp c4-cqfp 80 mhz 40 mhz 0100 mpc603afe80cc ppc603-fx-080-2 66.67 mhz 33.33 mhz 0100 mpc603afe66cc ppc603-fx-066-2 66.67 mhz 0000 mpc603afe66ac ppc603-fx-066-1 mpc 603 a fe xx x c product code part identifier part modifier application modifier processor speed package (a = alpha?riginal design) (fe = wire-bond cqfp) (a = 1:1 processor to bus, c = 2:1 processor to bus) revision level (contact motorola sales office) (f = c4-cqfp) part identifier ppc 603 ?f x?0xx?x package revision level bus speed internal speed (contact ibm sales office) (1 = internal speed, 2 = half internal) product code
603 hardware specifications 29 appendix a general handling recommendations for the c4-cqfp package the following list provides a few guidelines for package handling: handle the electrostatic discharge sensitive (esd) package with care before, during, and after processing. do not apply any load to exceed 3 kg after assembly. components should not be hot-dip tinned. the package encapsulation is an acrylated urethane. use adequate ventilation (local exhaust) for all elevated temperature processes. the package parameters are as follows: heat sink adhesive aieg-7655 ibm reference drawing 99f4869 test socket yamaichi qfp-po 0.5-240p signal 165 power/ground 75 total 240 a.1 package environmental, operation, shipment, and storage requirements the environmental, operation, shipment, and storage requirements are as follows: make sure that the package is suitable for continuous operation under business of?e environments. operating environment: 10 c to 40 c, 8% to 80% relative humidity storage environment: 1 c to 60 c, up to 80% relative humidity shipping environment: 40 c to 60 c, 5% to 100% relative humidity this component is quali?d to meet jedec moisture class 2. after expiration of shelf life, packages may be baked at 120 c (+10/? c) for 4 hours minimum and then be used or repackaged. shelf life is as speci?d by jedec for moisture class 2 components. a.2 card assembly recommendations this section provides recommendations for card assembly process. follow these guidelines for card assembly. this component is supported for aqueous, ir, convection re?w, and vapor phase card assembly processes. the temperature of packages should not exceed 220 c for longer than 5 minutes. the package entering a cleaning cycle must not be exposed to temperature greater than that occurring during solder re?w or hot air exposure. it is not recommended to re-attach a package that is removed after card assembly.
30 603 hardware specifications during the card assembly process, no solvent can be used with the c4fp, and no more than 3 kg of force must be applied normal to the top of the package prior to, during, or after card assembly. other details of the card assembly process follow: solder paste either water soluble (for example, alpha 1208) or no clean solder stencil thickness 0.152 mm solder stencil aperature width reduced to 0.03 mm from the board pad width placement tool panasonic mpa3 or equivalent solder re?w infrared, convection, or vapor phase solder re?w pro?e infrared and/or convection average ramp-up?.48 to 1.8 c/second time above 183 c?5 to 145 seconds minimum lead temperature?00 c maximum lead temperature?40 c maximum c4fp temperature?45 c vapor phase preheat (board)?0 c to 150 c time above 183 c?0 to 145 seconds minimum lead temperature?00 c maximum c4fp temperature?20 c egress temperature?elow 150 c clean after re?w de-ionized (d.i.) water if water-soluble paste is used cleaner requirements?onveyorized, in-line minimum of four washing chambers ?pre-clean chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 70 c minimum, dwell time of 24 seconds minimum, water is not re-used, water ?w rate of 30 liters/minute. ?wash chamber #1: top and bottom sprays, minimum top-side pressure of 48 psig, minimum bottom-side pressure of 44 psig, water temperature of 62.5 c ( 2.5 c), dwell time of 48 seconds minimum, water ?w rate of 350 liters/minute. ?wash chamber #2: top and bottom sprays, minimum top-side pressure of 32 psig, minimum bottom-side pressure of 28 psig, water temperature of 72.5 c ( 2.5 c), dwell time of 48 seconds minimum, water ?w rate of 325 liters/minute. ?final rinse chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 72.5 c minimum, dwell time of 24 seconds minimum, water ?w rate of 30 liters/minute. no cleaning required if ?o clean solder paste?is used touch-up and repair water soluble (for example, kester 450) or no clean flux c4fp removal hot air rework c4fp replace hand solder
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. there are no express or implied copyright or patent licenses granted hereunder by motorola or ibm to design, modify the design of, or fabricate circuits based on the information in this document. the powerpc 603 microprocessor embodies the intellectual property of motorola and of ibm. however, neither motorola nor ibm assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. neither motorola nor ibm is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. both motorola and ibm reserve the right to modify this document and/or any of the products as described herein without further notice. nothing in this document, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as the conveyance by motorola or ibm of an express warranty of any kind or implied warranty, representation, or guarantee regarding the merchantability or fitness of the products for any particular purpose . neither motorola nor ibm assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. in the absence of such an agreement, no liability is assumed by motorola, ibm, or the marketing party for any damages, actual or otherwise. ?ypical parameters can and do vary in different applications. all operating parameters, including ?ypicals, must be validated for each customer application by customers technical experts. neither motorola nor ibm convey any license under their respective intellectual property rights nor the rights of others. neither motorola nor ibm makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold motorola and ibm and their respective of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorneys fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola or ibm was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. ibm, the ibm logo, and ibm microelectronics are trademarks of international business machines corporation. the powerpc name, the powerpc logotype, and powerpc 603 are trademarks of international business machines corporation, used by motorola under license from international business machines corporation. international business machines corporation is an equal opportunity/af?mative action employer.

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