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s3c9004/p9004/c9014/p9014 product overview 1 - 1 1 product overview sam87ri product family samsung's sam87ri family of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. a dual address/data bus architecture and a large number of bit- or nibble-configurable i/o ports provide a flexible programming environment for applications with varied memory and i/o requirements. timer/counters with selectable operating modes are included to support real-time operations. many sam87ri microcontrollers have an external interface that provides access to external memory and other peripheral devices. s3c9004/p9004/c9014/p9014 microcontroller the s3c9004/p9004/c9014/p9014 single-chip 8-bit microcontroller is fabricated using an advanced cmos process. it is built around the powerful sam87ri cpu core. stop and idle power-down modes were implemented to reduce power consumption. to increase on-chip register space, the size of the internal register file was logically expanded. the s3c9004/p9004/c9014/p9014 has 4 k bytes of program memory on-chip. using the sam87ri design approach, the following peripherals were integrated with the sam87ri core: ? five configurable i/o ports (32 pins) ? 12 bit-programmable pins for external interrupts ? 8-bit timer/counter with three operating modes the s3c9004/p9004/c9014/p9014 is a versatile microcontroller that can be used in a wide range of general purpose applications. it is especially suitable for use as a keyboard controller and is available in a 40 -pin dip and a 44-pin qfp package. otp the s3c9004/c9014 microcontroller is also available in otp (one time programmable) version, s3p9004/p9014. s3p9004/p9014 microcontroller has an on-chip 8-kbyte one-time-programmable eprom instead of masked rom. the s3p9004/p9014 is comparable to s3c9004/c9014, both in function and in pin configuration.
product overview s3c9004/p9004/c9014 /p9014 1 - 2 features cpu ? sam87ri cpu core memory ? 4-kbyte internal program memory (rom) ? 208-byte internal register file ? 8-kbyte external program memory ? 8-kbyte external data memory instruction set ? 41 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 1. 5 m s at 4 mhz f osc interrupts ? 14 interrupt sources with one vector, each source has its pending bit ? one level, one vector interrupt structure oscillation circuit options ? 4 mhz rc oscillator with on chip capacitor for s3c9004/p9004 ( ? 10% rc accuracy at v dd 5% and ta = 0 c?70 c, u sing 1% external precision resistor) ? rc oscillator for s3c9004/p9004 ? crystal/ceramic oscillator for S3C9014/p9014 general i/o ? five ports (32 pins total) ? three bit-programmable ports (20 pins total) ? two bit-programmable ports with external interrupts (12 pins total) timer/counter ? one 8-bit basic timer for watchdog function and programmable oscillation stabilization interval generation function ? one 8-bit timer/counter with pwm mode operating temperature range ? ? 4 0 c to + 85 c operating voltage range ? 4. 5 v to 5.5 v for s3c9004/p9004 ? 2.7 v to 5.5 v for S3C9014/p9014 package types ? 40-pin dip
s3c9004/p9004/c9014/p9014 product overview 1 - 3 block diagram port port sam87ri cpu p0.0-p0.4/a8-a12, p0.5-p0.7 4-kb rom reset p3.0 p3.1 p3.2 p3.3/clo ea (test) main osc 208-byte register file port p4.0/int p4.1/int/t0clk p4.2/int p4.3/int/t0out timer 0 port port p2.0-p2.7/int, as, ds , r/ w , dm p1.0-p1.7/ ad0-ad7 x in x out sam87ri bus basic timer i/o port and interrupt control v dd v ss1 v dd v ss1 figure 1-1 . block diagram
product overview s3c9004/p9004/c9014 /p9014 1 - 4 pin assignments p3.0 int/p4.0 t0clk/int/p4.1 int/p4.2 t0out/int/p4.3 as /int/p2.0 ds /int/p2.1 r/ w /int/p2.4 dm /int/p2.3 int/p2.4 int/p2.5 int/p2.6 int/p2.7 nc v ss1 ad7/p1.7 ad6/p1.6 ad5/p1.5 ad4/p1.4 ad3/p1.3 40-dip (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p3.1 p3.2 p3.3/clo v dd p0.0/a8 p0.1/a9 p0.2/a10 p0.3/a11 p0.4/a12 p0.5 p0.6 p0.7 x in reset ea p1.0/ad0 p1.1/ad1 p1.2/ad2 x out v ss2 s3c9004/p9004 S3C9014/p9014 figure 1-2 . pin assignment diagram (40-pin dip package)
s3c9004/p9004/c9014/p9014 product overview 1 - 5 pin descriptions table 1- 1. s3c9004/p9004/c9014/p9014 pin descriptions pin names pin type pin description circuit number pin numbers share pins p0.0 - p0.7 i/o bit-programmable i/o port for schmitt trigger input or open-drain output. port0 can also be configured as external interface address lines a8 - a12. c 36-29 a8 - a12 p1.0 - p1.7 i/o bit-programmable i/o port for schmitt trigger input , push-pull , or open-drain output. port1 can alternatively be used as external interface address/data lines ad0 - ad7. c 23-16 ad0 - ad7 p2.0 - p2.7 i/o bit-programmable i/o port for schmitt trigger input or push-pull output. port2 can be individually configured as external interrupt inputs. especially, p2.0 - 2.3 can be configured for external bus control signal. d 6-13 int, as , ds , r/ w , dm p3.0 - p3.3 i/o same general characteristics as port1. port3 are designed for to drive led directly. p3.3 can be used to system clock output (c l o) port. c 1, 40-38 p3.3/ c l o p4.0 - p4.3 i/o bit-programmable i/o port. input mode or n- channel open-drain output mode is software assignable. port4 can be individually configured as external interrupt inputs. pull-up resistors are also software assignable. especially, p4.1 can be used t0clk input and p4.3 also t0out for timer 0. d 2-5 int, t0clk, t0out x in , x out ? system clock input and output pin (for rc oscillator, crystal/ceramic oscillator, or external clock source) ? 27, 28 ? int i external interrupt for bit-programmable port2 and port4 pins when set to input mode. ? 2-13 port2/ port4 reset i reset signal input pin. schmitt trigger input with internal pull-up resistor. a 26 ? ea i external memory access (ea) pin with 2 modes: 0v = normal operation mode 5v = romless operation mode (must be connected to v ss during normal operation mode) b 24 ? v dd ? power input pin ? 37 ? v ss1 , v ss2 ? vss1 is a ground power for cpu core. vss2 is a ground power for i/o and osc block ? 15, 25 ? nc ? no connection (this pin would be better connecting to v ss ) ? 14 ?
product overview s3c9004/p9004/c9014 /p9014 1 - 6 pin circuits table 1- 2. pin circuit assignments for the s3c9004/p9004/c9014/p9014 circuit number circuit type s3c9004/p9004/c9014/p9014 assignments a i reset signal input b i ea input c i/o port s 0 , 1 , and 3 d i/o port s 2 and 4 v dd pull-up resistor in noise filter figure 1-3 . pin circuit type a ( reset reset ) in 0 v = internal rom access 5 v = external rom access figure 1-4 . pin circuit type b (ea) v dd open drain output disable in put data mux d0 d1 mode in put data in put out put d0 d1 i/o output data v ss figure 1-5 . pin circuit type c (port s 0, 1 , and 3)
s3c9004/p9004/c9014/p9014 product overview 1 - 7 v dd open drain output disable in put data mode in put data in put out put d0 d1 i/o output data v ss pull-up enable v dd pull-up resistor mux d0 d1 figure 1-6 . pin circuit type d (port s 2 and 4 )
product overview s3c9004/p9004/c9014 /p9014 1 - 8 application circuit keyboard matrix 0 1 2 3 15 0 1 2 3 7 5v h o s t 5v clk data x in x out v ss1 v ss2 v dd port 3 port 0 port 1 port 2 ea reset s3c9004 s3p9004 port 4 r osc figure 1-7 . keyboard control application circuit diagram
s3c9004/p9004/c9014/p9014 electrical data 12- 1 12 electrical data overview in this section, the following s3c9004/p9004/c9014/p9014 electrical characteristics are presented in tables and graphs: ? absolute maximum ratings ? d.c. electrical characte ristics ? i/o capacitance ? a.c. electrical characteristics ? input timing for reset ? input timing for external interrupts (ports 2 and 4, reset , and ea) ? oscillator characteristics ? oscillation stabilization time ? clock timing measurement points at x in ? data retention supply voltage in stop mode ? stop mode release timing when initiated by a reset ? stop mode release timing when initiated by an external interrupt ? exte r nal memory timing characteristics (8 mhz) ? exte r nal memory read and write timing ? characteristic curves
electrical data s3c9004/p9004/c9014 /p9014 12- 2 table 12- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v in all input ports ? 0.3 to v dd + 0.3 v output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current i oh one i/o pin active ? 18 ma high all i/o pins active ? 60 output current i ol one i/o pin active + 25 ma low total pin current for ports 3 + 100 total pin current for ports 0, 1, 2, 4 + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 12- 2. d.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 4. 5 v to 5.5 v (1) ) parameter symbol conditions min typ max unit input high voltage v ih1 all inputs except v ih2 0.8 v dd ? v dd v v ih2 x in v dd ? 0.5 v dd input low voltage v il1 all inputs except v il2 ? 0.2 v dd v v il2 x in 0.4 output high voltage v oh i oh = ? 200 a all output s except p4.1, p4.3, and port0 v dd ? 1.0 ? ? v output low voltage v ol i ol = 2 ma all output s except port3 ? ? 0.4 v output low current i ol v ol = 3 v port3 only 8 15 23 ma input high leakage current i lih1 v in = v dd all inputs except i lih2 , p4.0 and p4.1 ? ? 3 a i lih2 v in = v dd x in , x out 20
s3c9004/p9004/c9014/p9014 electrical data 12- 3 table 12- 2. d.c. electrical characteristics (continued) (t a = ? 4 0 c to + 85 c, v dd = 4. 5 v to 5.5 v (1) ) parameter symbol conditions min typ max unit input low leakage current i lil1 v in = 0 v all inputs except i lil2 , p4.0 and p4.1 ? ? ? 3 a i lil2 v in = 0 v x out , x in ? 20 output high leakage current i loh v out = v dd all outputs ? ? 3 a output low leakage current i lol v out = 0 v all outputs ? ? ? 3 a pull-up resistors r l1 v in = 0 v ; port 2 only 30 60 90 k w r l2 v in = 0 v ; port 4 only 1. 8 2.8 4.0 r l3 v in = 0 v ; reset only 50 90 150 supply current (2) i dd1 normal operation mode 4 mhz cpu clock ? 4.5 10 ma i dd2 idle mode ; 4 m hz oscillator 0.9 3 ma i dd3 stop mode 0.5 5 a note s : 1. the operating voltage range of S3C9014/p9014 is from 2.7 v to 5.5 v according to oscillation frequency. 2 . supply current does not include current drawn through internal pull-up resistors or external output current loads.

s3c9004/p9004/c9014/p9014 electrical data 12- 5 table 12- 3. input/output capacitance (t a = ? 4 0 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 12- 4. a.c. electrical characteristics (t a = ? 4 0 c to + 85 c, v dd = 4. 5 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width t inth , t intl p2 and p4 ? 200 ? ns reset input low width t rsl reset ? 1,000 ? reset t rsl 0.2 v dd figure 12- 1. input timing for reset reset
electrical data s3c9004/p9004/c9014 /p9014 12- 6 t intl t inth 0.8 v dd 0.2 v dd figure 12- 2. input timing measurement points for port 2, port 4, and reset reset table 12- 5. oscillator characteristics (t a = ? 4 0 c + 85 c, v dd = 4. 5 v to 5.5 v) oscillator clock circuit test condition min typ max unit rc oscillator (with internal capacitor ; for s3c9004/p9004 ) r x in x out v dd = 4.75 to 5.25 v ta = 0 c + 70 c tolerance: 10% ( note ) ? 4 ? mhz crystal/ceramic oscillator ( for S3C9014/p9014 ) c2 x in x out c1 crystal/ceramic oscillation frequency 1.0 ? 8.0 note : the s3c9004/p9004 provides an internal capacitor to accommodate an rc oscillator configuration. a 1% precision resistor must be used to achieve an oscillation frequency with an acceptable tolerance.
s3c9004/p9004/c9014/p9014 electrical data 12- 7 cpu clock 1 mhz supply voltage (v) 2 mhz 3 mhz 4 mhz 6 mhz 8 mhz 2 3 4 5 6 7 1 2.7 3.5 5.5 figure 12- 3. operating voltage range (S3C9014/p9014)

s3c9004/p9004/c9014/p9014 electrical data 12- 9 table 12- 6. oscillation stabilization time (t a = ? 4 0 c + 85 c, v dd = 4. 5 v to 5.5 v) oscillator test condition min typ max unit main crystal f osc = 4 mhz ? ? 10 ms main ceramic (oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range.) oscillator stabilization wait time t wait stop mode release time by a reset ? 2 1 6 / f osc ? t wait stop mode release time by an interrupt ? (note) ? note : the oscillator stabilization wait time, t wait , is determined by the setting in the basic timer control register, btcon. x in t xl t xh 1 / f osc v dd ? 0.5 v 0.4 v figure 12-4 . clock timing measurement points at x in table 12- 7. data retention supply voltage in stop mode (t a = ? 4 0 c + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2.0 ? 6 v data retention supply current i dddr stop mode; v dddr = 2.0 v ? ? 5 a
electrical data s3c9004/p9004/c9014 /p9014 12- 10 t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset oper a tion idle mode (basic timer active) 0.8 v dd 0.2 v dd normal operating mode ~ ~ ~ ~ figure 12-5 . stop mode release timing when initiated by a reset t wait v dd external interrupt execution of stop instruction v dddr data retention mode stop mode idle mode (basic timer active) 0.8 v dd 0.2 v dd normal operating mode ~ ~ ~ ~ figure 12-6 . stop mode release timing when initiated by an external interrupt
s3c9004/p9004/c9014/p9014 electrical data 12- 11 table 12- 8. external memory timing characteristics ( 4 mhz) (t a = ? 4 0 c to + 85 c, v dd = 4. 5 v to 5.5 v) number symbol parameter normal timing (ns) min max 1 t da (as) address valid to as - delay 10 ? 2 t das (a) as - to address float delay 35 ? 3 t das (dr) as - to read data required valid ? 140 4 t was as low width 88 ? 5 t da (ds) address float to ds 0 ? 6a t wds (read) ds (read) low width 314 ? 6b t wds (write) ds (write) low width 164 ? 7 t dds (dr) ds to read data required valid ? 80 8 t hds (dr) read data to ds - hold time 0 ? 9 t dds (a) ds - to address active delay 20 ? 10 t dds (as) ds - to as delay 30 ? 11 t ddo (ds) write data valid to ds (write) delay 10 ? 12 t drw (as) r/ w valid to as - delay 20 ? 13 t dds (dw) ds - to write data not valid delay 20 ? notes: 1. all times are in nano seconds (ns) and assume an 4 mhz input frequency. 2. wait states add 100 ns to the time of numbers 3, 6a, 6b, and 7.
electrical data s3c9004/p9004/c9014 /p9014 12- 12 port0 (p2.3) port1 (p2.0) (p2.1) 12 3 1 2 11 4 5 7 6 8 10 9 13 a0 - a7 d 0 - d 7 out d 0 - d 7 in out r/ (p2.2) w dm as ds a8 - a12, dm figure 12-7. external memory read and write timing (see table 12- 8 for a description of each timing point.)
s3c9004/p9004/c9014/p9014 electrical data 12- 13 characteristic curves note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. i dd1 (ma) 1 0 v dd (v) 2 3 4 5 6 7 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f osc = 10 mhz ~ ~ 2.5 f osc = 8 mhz f osc = 5 mhz f osc = 2 mhz f osc = 1 mhz (t a = 25 c) figure 12-8. i dd1 vs. v dd
electrical data s3c9004/p9004/c9014 /p9014 12- 14 i dd2 ( m a) 200 0 v dd (v) 400 600 800 1000 1200 1400 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ~ ~ 2.5 f osc = 10 mhz f osc = 5,8 mhz f osc = 2 mhz f osc = 1 mhz (t a = 25 c) figure 12-9 . i dd2 vs. v dd
s3c9004/p9004/c9014/p9014 electrical data 12- 15 i dd3 ( n a) 400 0 v dd (v) 450 5 00 55 0 6 00 65 0 7 5 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 ~ ~ 2.5 f osc = 5 mhz (t a = 25 c) 7 00 figure 12-10 . i dd3 vs. v dd voh (v) 0 -1 ioh (ma) 1 2 3 4 5 2 3 4 5 6 7 8 1 6 0 9 10 11 12 v dd = 5.0v v dd = 4.5v v dd = 5.5v figure 12-11 . i oh vs. v oh
electrical data s3c9004/p9004/c9014 /p9014 12- 16 vol (v) iol (ma) 1 2 3 4 5 2 3 4 5 6 7 8 1 6 0 10 12 14 17 v dd = 4.5v 7 9 11 13 15 16 v dd = 5.5v v dd = 5.0v figure 12-12 . v o l vs. i o l (port 0, 1, 2, and 4) vol (v) iol (ma) 1 2 3 4 5 2 3 4 5 6 7 8 1 6 0 10 12 14 17 v dd = 4.5v 7 9 11 13 15 16 v dd = 5.5v v dd = 5.0v figure 12-13 . v o l vs. i o l (port 3)
s3c9004/p9004/c9014/p9014 mechanical data 13 - 1 13 mechanical data overview the s3c9004/p9004/c9014/p9014 is currently available in a 40-pin dip package. note : dimensions are in millimeters. 0-15 15.24 0.25 +0.1 ? 0.05 0.51min 3.95 0.2 3.30 0.3 5.08max 5 2 .42 0.2 52.82 max 1.27 0.1 0.46 0.1 (2.00) 2.54 13.85 0.2 #1 #20 #40 #21 40-dip-600b figure 13 - 1. 40-pin dip package mechanical data (40-dip-600b)
mechanical data s3c9004/p9004/c9014/p9014 13 - 2 notes

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