View W83627THF_5915969.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

winbond lpc i/o W83627THF date: august 7, 2003 revision: 0.8
W83627THF publication release date: august 7, 2003 - 1 - revision 0.8 W83627THF data sheet revision history pages dates version web version main contents 1 n.a. 01/16/2003 0.50 first published preliminary version. 2 p.104 p.117~120 03/25/2003 0.60 susled data correction. add item 7.8.9 3 p.116~122 04/10/2003 0.70 update appendix a to demo circuit 4 p.7 p.18 08/07/2003 0.80 add block diagram add description for gp26(pin93) please note that all data and specific ations are subject to change without notice. all the trademarks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages re sulting from such improper use or sales.
W83627THF publication release date: august 7, 2003 - ii - revision 0.8 table of contents- 1. general des cription ......................................................................................................... 1 2. features ....................................................................................................................... .......... 3 3. block diagram .................................................................................................................. .... 7 4. pin config uration .............................................................................................................. .8 5. pin descri ption................................................................................................................ ..... 9 5.1 lpc interf ace ................................................................................................................ 10 5.2 fdc interf ace................................................................................................................ 11 5.3 multi-mode para llel port ............................................................................................... 12 5.4 serial port interface ...................................................................................................... 14 5.5 kbc interf ace................................................................................................................ 15 5.6 hardware monito r interface .......................................................................................... 16 5.7 game port..................................................................................................................... 1 7 5.8 general purpos e i/o po rt ............................................................................................. 18 5.8.1 general purpose i/o port 1 (p ower source is vcc) ........................................................18 5.8.2 general purpose i/o port 2 (p ower source is vcc) ........................................................18 5.8.3 general purpose i/o port 3, 4 (power sour ce is vsb) ................................................... 19 5.8.4 general purpose i/o port 5 (p ower source is vcc) ........................................................20 5.9 power pi ns.................................................................................................................... 2 0 5.10 gpio pin powe r source .............................................................................................. 20 6. general purp ose i/o......................................................................................................... 21 7. hardware mo nitor ........................................................................................................... 24 7.1 general desc riptio n ...................................................................................................... 24 7.2 access inte rface ........................................................................................................... 24 7.3 analog in puts ................................................................................................................ 26 7.3.1 monitor over 4. 096v volt age:.......................................................................................... 26 7.3.2 cpuvcore voltage det ection me thod: .........................................................................27 7.3.3 temperature measur ement mach ine..............................................................................28 7.4 fan speed count and fa n speed cont rol ................................................................. 29 7.4.1 fan speed count .............................................................................................................29 7.4.2 fan speed co ntrol...........................................................................................................31 7.5 smartfan tm contro l ...................................................................................................... 32 7.5.1 thermal crui se m ode ..................................................................................................... 32 7.5.2 fan speed crui se mode.................................................................................................33 7.5.3 manual cont rol m ode ..................................................................................................... 34
W83627THF publication release date: august 7, 2003 - iii - revision 0.8 7.6 smi# interru pt mode ..................................................................................................... 34 7.6.1 voltage smi# mode: .......................................................................................................34 7.6.2 fan smi# mode: .............................................................................................................34 7.6.3 the W83627THF temperature s ensor 1(systin) smi# in terrupt has 3 modes : ............35 7.6.4 the W83627THF temperature sensor 2(cputin ) and sensor 3(auxtin) smi# interrupt has two modes and it is progr ammed at cr[4c h] bit 6...................................................36 7.7 ovt# interr upt mode .................................................................................................... 37 7.8 registers and ram....................................................................................................... 38 7.8.1 address port (port x5h) ..................................................................................................38 7.8.2 data port (p ort x 6h)........................................................................................................ 38 7.8.3 configuration register ? index 40h...............................................................................39 7.8.4 interrupt status register 1 ? index 41h .........................................................................39 7.8.5 interrupt status register 2 ? index 42h ........................................................................ 40 7.8.6 smi# mask register 1 ? index 43h ...............................................................................41 7.8.7 smi# mask register 2 ? index 44h ...............................................................................41 7.8.8 reserved register ? index 4 5h?46h ...........................................................................41 7.8.9 fan divisor register i ? index 47h................................................................................42 7.8.10 value ram ? index 20h- 3fh......................................................................................42 7.8.11 device id regist er - index 49h.....................................................................................44 7.8.12 reserved register ? index 4ah ..................................................................................44 7.8.13 fan divisor register ii - index 4bh...............................................................................44 7.8.14 smi#/ovt# control regi ster- inde x 4ch .....................................................................45 7.8.15 fan in/out and beep control register- in dex 4dh ..................................................46 7.8.16 register 50h ~ 5fh bank select register - index 4e h .................................................47 7.8.17 winbond vendor id regist er - inde x 4fh.....................................................................47 7.8.18 winbond test register -- in dex 50h - 55h (bank 0) ..................................................... 48 7.8.19 beep control register 1-- index 56h ( bank 0 ) ............................................................48 7.8.20 beep control register 2-- index 57h ( bank 0 ) ............................................................49 7.8.21 chip id -- index 58h ( bank 0 ) .......................................................................................49 7.8.22 diode selection register -- index 59h ( bank 0 ) .........................................................50 7.8.23 reserved -- index 5ah ( bank 0 ) ...................................................................................50 7.8.24 reserved -- index 5bh ( bank 0 ) ...................................................................................50 7.8.25 reserved -- index 5ch ( bank 0 ) ...................................................................................50 7.8.26 vbat monitor control register -- index 5dh ( bank 0 ) .................................................51 7.8.27 reserved register --5eh ( bank 0 )................................................................................51 7.8.28 reserved register --5fh ( bank 0 )................................................................................51 7.8.29 cputin temperature sensor temperatur e (high byte) register - index 50h ( bank 1 ).. .............................................................................................................................. .......52 7.8.30 cputin temperature sensor temperatur e (low byte) register - index 51h ( bank 1 )52 7.8.31 cputin temperature sensor config uration register - index 52h ( bank 1 ) ................53
W83627THF publication release date: august 7, 2003 - iv - revision 0.8 7.8.32 cputin temperature sensor hysteresis (high byte) register - index 53h ( bank 1 )..53 7.8.33 cputin temperature sensor hysteresis (low byte) register - index 54h ( bank 1 ) ...54 7.8.34 cputin temperature sensor over-temper ature (high byte) register - index 55h ( bank1 ) .........................................................................................................................54 7.8.35 cputin temperature sensor over-temperat ure (low byte) register - index 56h ( bank 1 ) .............................................................................................................................. ....55 7.8.36 auxtin temperature sensor temperature (high byte) register - index 50h ( bank 2 )... .............................................................................................................................. .......55 7.8.37 auxtin temperature sensor temperature (low byte) register - index 51h ( bank 2 )56 7.8.38 auxtin temperature sensor config uration register - index 52h ( bank 2 ).................56 7.8.39 auxtin temperature sensor hysteresis (high byte) register - index 53h ( bank 2 )..57 7.8.40 auxtin temperature sensor hysteresis (low byte) register - index 54h ( bank 2 ) ...57 7.8.41 auxtin temperature sensor over-temper ature (high byte) register - index 55h ( bank 2 ) ........................................................................................................................58 7.8.42 auxtin temperature sensor over-temperat ure (low byte) register - index 56h ( bank 2 ) .............................................................................................................................. ....58 7.8.43 interrupt status register 3 -- index 50h (bank4 ).........................................................59 7.8.44 smi# mask register 3 -- index 51h (bank 4)............................................................59 7.8.45 reserved register -- index 52h ( bank 4 ) .....................................................................60 7.8.46 beep control register 3-- index 53h ( bank 4 ) ............................................................60 7.8.47 systin temperature sensor offs et register -- index 54h ( bank 4 ) ...........................60 7.8.48 cputin temperature sensor offs et register -- index 55h ( bank 4 ) ...........................61 7.8.49 auxtin temperature sensor offs et register -- index 56h ( bank 4 ) ...........................61 7.8.50 reserved register -- index 57h--58h ( bank4) ..............................................................61 7.8.51 real time hardware status register i -- index 59h ( bank 4 ).......................................62 7.8.52 real time hardware status register ii -- index 5ah ( bank 4 ) .....................................63 7.8.53 real time hardware status register iii -- index 5bh ( bank 4 ) ....................................64 7.8.54 reserved register -- index 5ch ( bank 4 ).....................................................................64 7.8.55 reserved register -- index 5dh ( bank 4 ).....................................................................64 7.8.56 value ram 2 ? index 50h - 5ah (bank 5) ..................................................................64 7.8.57 winbond test register -- index 50h ( bank 6 ) ..............................................................65 7.8.58 reserved register--index00h ( bank 0 ) ........................................................................65 7.8.59 sysfanout output value control register-- 01h ( bank 0 ) .......................................65 7.8.60 reserved register?index02h ( bank 0 ) .......................................................................66 7.8.61 cpufanout output value control register-- 03h ( bank 0 ).......................................66 7.8.62 fan configuration register i -- index 04h ( bank 0 ) .....................................................66 7.8.63 systin target temperature register/ sysf anin target speed register -- index 05h ( bank 0 ) ........................................................................................................................67 7.8.64 cputin target temperature register/ cp ufanin target speed register -- index 06h ( bank 0 ) ........................................................................................................................68 7.8.65 tolerance of target temperature or target speed register -- index 07h ( bank 0 ) ........68 7.8.66 sysfanout stop value register -- index 08h ( bank 0 ) ............................................69
W83627THF publication release date: august 7, 2003 - v - revision 0.8 7.8.67 cpufanout stop value register -- 09h ( bank 0 )......................................................69 7.8.68 sysfanout start-up value register -- index 0ah ( bank 0 ) ......................................69 7.8.69 cpufanout start-up value register -- index 0bh ( bank 0 ) ......................................70 7.8.70 sysfanout stop time register -- index 0ch ( bank 0 ).............................................70 7.8.71 cpufanout stop time register -- index 0dh ( bank 0 ) ............................................71 7.8.72 fan output step down time register -- index 0eh ( bank 0 ).......................................71 7.8.73 fan output step up time register -- index 0fh ( bank 0 )............................................72 7.8.74 reserved register?index10h ( bank 0 ) .......................................................................72 7.8.75 auxfanout output value control register-- 11h ( bank 0 ).......................................72 7.8.76 fan configuration register ii -- index 12h ( bank 0 ) ....................................................73 7.8.77 auxtin target temperature register/ au xfanin target speed register -- index 13h ( bank 0 ) ........................................................................................................................74 7.8.78 tolerance of target temperature or target speed register -- index 14h ( bank 0 ) .....74 7.8.79 auxfanout stop value register -- index 15h ( bank 0 ) ............................................75 7.8.80 auxfanout start-up value register -- index 16h ( bank 0 ).......................................75 7.8.81 auxfanout stop time register -- index 17h ( bank 0 ) .............................................76 7.8.82 vrm & ovt configuration register -- index 18h ( bank 0 )...........................................76 7.8.83 reserved -- index 19h ( bank 0 )....................................................................................77 7.8.84 user defined register -- index 1a- 1bh ( bank 0 ).........................................................77 7.8.85 reserved registe r-- index 1ch-1fh ( bank 0 ) ..............................................................77 8. plug and play co nfiguration ...................................................................................... 78 8.1 compatible pnp ............................................................................................................ 78 8.1.1 extended function register s .........................................................................................78 8.1.2 extended functions enable registers (efers).............................................................79 8.1.3 extended function index registers (efirs), extended function data registers(efdrs) .............................................................................................................................. .........79 8.2 configuratio n sequence ............................................................................................... 79 8.2.1 enter the extended function mode ..................................................................................79 8.2.2 configuration t he configuration register s ........................................................................80 8.2.3 exit the extended function mode ....................................................................................80 8.2.4 software progra mming exam ple.....................................................................................80 9. configuration register................................................................................................. 81 9.1 chip (global) cont rol register...................................................................................... 81 9.1.1 logical device 0 (f dc) ..................................................................................................87 9.1.2 logical device 1 (p arallel po rt) ......................................................................................91 9.1.3 logical device 2 (uart a).............................................................................................92 9.1.4 logical device 3 (uart b).............................................................................................93 9.1.5 logical device 5 (kbc ) ..................................................................................................95 9.1.6 logical device 7 (game port and mi di port and gpio port 1 and 5) ............................96
W83627THF publication release date: august 7, 2003 - vi - revision 0.8 9.1.7 logical device 8 (gpio port 2 this po wer of the port is vcc sour ce)...........................97 9.1.8 logical device 9 (gpio port 3, 4. t hese two ports are powered by vsb) .....................99 9.2 logical device a (acpi) ............................................................................................. 100 9.3 logical device b (har dware moni tor) ......................................................................... 109 10. electrical chara cteristics....................................................................................... 110 10.1 absolute maximu m ratings ........................................................................................ 110 10.2 dc characteri stics ...................................................................................................... 110 11. application ci rcuits ...................................................................................................... 115 11.1 parallel port ex tension fdd ....................................................................................... 115 11.2 parallel port ex tension 2fdd ..................................................................................... 116 11.3 four fdd mode .......................................................................................................... 116 12. how to read the top mark ing.................................................................................... 117 13. package dime nsions ....................................................................................................... 118 14. appendix a : demo circuit ............................................................................................. 119
W83627THF publication release date: august 7, 2003 - 1 - revision 0.8 1. general description W83627THF is a winbond lpc i/o product. it integrates the following major peripheral functions in a chip: the disk driver adapter (fdc), serial port (uart), parallel por t (spp/epp/ecp), keyboard controller (kbc), sir, game port, midi port, hard ware monitor, acpi, on now wake-up features. the disk drive adapter functions of W83627THF include a floppy disk drive controller compatible with the industry standard 82077/765, data separator, wr ite pre-compensation ci rcuit, decode logic, data rate selection, clock generator, drive interface co ntrol logic, and interrupt and dma logic. the wide range of functions integrated onto the w83627t hf greatly reduces the number of components required for interfacing with floppy disk drives. the W83627THF supports four 360k, 720k, 1.2m, 1.44m, or 2.88m disk drives and data transfer ra tes of 250 kb/s, 300 kb/s, 500 kb/s, 1 mb/s, and 2 mb/s. the W83627THF provides two high-speed serial communication ports (uarts), one of which supports serial infrared communication. each uart includes a 16-byte send/receive fifo, a programmable baud rate generator, complete modem control capability, and a processor interrupts system. both uarts provide legacy speed with baud rate up to 115.2k bps and also advanced speed with baud rates of 230k, 460k, or 921k bps, whic h support higher speed modems. in addition, the W83627THF provides ir functions: irda 1.0 (sir for 1.152k bps) the W83627THF supports one pc-com patible printer port (spp), bi-dir ectional printer port (bpp) and also enhanced parallel port (epp) and extended capabilities port (ecp). through the printer port interface pins, also available are: extensi on fdd mode and extension 2fdd mode allowing one or two external floppy disk drives to be connected. the configuration registers suppor t mode selection, function enable/disable, and power down function selection. furthermore, the configurable pnp feat ures are compatible with the plug-and-play feature demand of windows 95/98 tm , which makes system resource allocation more efficient than ever. the W83627THF provides functions that complies with acpi ( advanced configuration and power interface ), which includes support of legacy and acpi power management through pme# or psout# function pins. for onnow keyboard wake-up, onnow mouse wake-up. the W83627THF also has auto power management to r educe the power consumption. the keyboard controller is based on 8042 compatible instruction set with a 2k byte programmable rom and a 256-byte ram bank. keyboard bios firmware are available with optional amikey tm - 2, phoenix multikey/42 tm , or customer code. the W83627THF provides a set of flexible i/o contro l functions to the system designer through a set of general purpose i/o ports. these gpio ports may serve as simple i/o or may be individually configured to provide a pr edefined alternate function.
W83627THF publication release date: august 7, 2003 - 2 - revision 0.8 the W83627THF is made to fully comply with microsoft pc98 and pc99 hardware design guide. moreover, W83627THF is made to meet the specif ication of pc2001's requirement in the power management: acpi 1.0/1.0b/2.0 and dpm (device power management). the W83627THF contains a game port and a midi port. the game port is designed to support 2 joysticks and can be applied to all standard pc game control devices. they are very important for an entertainment or consumer computer. the W83627THF supports hardware status monitori ng for personal computers. it can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and properly. moreover, W83627THF support the smart fan control system, including the ?thermal cruise tm ? and ?speed cruise tm ? functions. smart fan can make system more stable and user friendly. the special characteristic of super i/o product line is to avoid power rails short. this is especially true to a multi-power system where power partition is much more complex than a single-power one. special care might be appl ied during layout stage or the ic will fail even though its in tended function is ok.
W83627THF publication release date: august 7, 2003 - 3 - revision 0.8 2. features general meet lpc spec. 1.1 support ldrq#(lpc dma), serirq (serial irq) compliant with microsoft pc98/pc2001 hardware design guide support dpm (device power management), acpi programmable configuration settings single 24 or 48 mhz clock input fdc compatible with ibm pc at disk drive systems variable write pre-compensation with track selectable capability support vertical recording format dma enable logic 16-byte data fifos support floppy disk drives and tape drives detects all overrun and underrun conditions built-in address mark detection circuit to simplify the read electronics fdd anti-virus functions with software write protect and fdd write enable signal (write data signal was forced to be inactive) support up to four 3.5-inch or 5.25-inch floppy disk drives completely compatible with industry standard 82077 360k/720k/1.2m/1.44m/2.88m format; 250k, 300k , 500k, 1m, 2m bps data transfer rate support 3-mode fdd, and its win95/98/nt/2k/xp driver uart two high-speed 16550 compatible uarts with 16-byte send/receive fifos midi compatible fully programmable serial-interface characteristics: --- 5, 6, 7 or 8-bit characters --- even, odd or no parity bit generation/detection --- 1, 1.5 or 2 stop bits generation
W83627THF publication release date: august 7, 2003 - 4 - revision 0.8 internal diagnostic capabilities: --- loop-back controls for communications link fault isolation --- break, parity, overrun, framing error simulation programmable baud generator allows division of 1.8461 mhz and 24 mhz by 1 to (2 16 -1) maximum baud rate up to 921k bps for 14.769 mhz and 1.5m bps for 24 mhz infrared support irda version 1.0 sir protocol with maximum baud rate up to 115.2k bps support sharp ask-ir protocol with maximum baud rate up to 57,600 bps parallel port compatible with ibm parallel port support ps/2 compatible bi-directional parallel port support enhanced parallel port (epp) ? compatible with ieee 1284 specification support extended capabilities port (ecp) ? compatible with ieee 1284 specification extension fdd mode supports disk drive b; and extension 2fdd mode supports disk drives a and b through parallel port enhanced printer port back-drive current protection keyboard controller asynchronous access to two data registers and one status register software compatibility with the 8042 support ps/2 mouse support port 92 support both interrupt and polling modes fast gate a20 and hardware keyboard reset 8 bit timer/ counter support binary and bcd arithmetic 6 mhz, 8 mhz, 12 mhz, or 16 mhz operating frequency
W83627THF publication release date: august 7, 2003 - 5 - revision 0.8 game port support two separate joysticks support every joystick two axis (x, y) and two button (a, b) controllers midi port the baud rate is 31.25 k baud rate 16-byte input fifo 16-byte output fifo general purpose i/o ports 6 sets programmable general purpose i/o ports general purpose i/o ports can serve as simple i/o ports, interrupt steering inputs, watching dog timer output, power led output, infrared i/o pins, kbc control i/o pins, suspend led output, rsmrst# signal, pwrok signal, str (suspend to dram) function, vid control function, onnow functions keyboard wake-up by programmable keys mouse wake-up by programmable buttons on now wake-up from all of the acpi sleeping states (s1-s5)
W83627THF publication release date: august 7, 2003 - 6 - revision 0.8 hardware monitor functions smart fan control system, support ?thermal cruise tm ? and ?speed cruise tm ? 3 thermal inputs from optionally remote t hermistors or 2n3904 transistors or pentium tm ii/iii/4 thermal diode output 4 external voltage detect inputs. 3 intrinsic voltage monitoring (typical for vbat, +5vsb , +5vcc) 3 fan speed monitoring inputs 3 fan speed control (dc analog output) build in case open detection circuit watchdog comparison of all monitored values programmable hysteresis and setting points for all monitored items over temperature indicate output issue smi#, irq, ovt# to activate system protection winbond hardware doctor tm support intel ldcm tm compatible package 128-pin pqfp
W83627THF publication release date: august 7, 2003 - 7 - revision 0.8 3. block diagram lreset#, lclk, lframe#, lad[3:0], ldrq#, serirq lpc interface fdc ura, b prt hm game port midi gpio ir floppy drive interface signals serial port a, b interface signals printer port interface signals irrx irtx acpi joystick interface signals general-purpose i/o pins msi mso hardware monitor channel and vref kbc keyboard/mouse data and clock
W83627THF publication release date: august 7, 2003 - 8 - revision 0.8 4. pin configuration susled/gp37 kdat kclk 5vsb kbrst ga20m beep ria# dcda# gnd penkbc/souta sina pnpcsv/dtra# hefras/rtsa# dsra# ctsa# vcc stb# afd# err# init# slin# pd0 pd1 pd2 pd3 auxtin vref cpuvcore vin0 vin1 vin2 gp23 gp24 gp25 gp26 gp30/pwrgd gp31/3vsbsw# gp32/pled gp33/wdto irrx/gp34 irtx gp35 rib# dcdb# pen48/soutb sinb dtrb# rtsb# dsrb# ctsb# gp36 caseopen# gp40 vbat slp_sx#/gp41 pwrctl#/gp42 pwrok/gp43 rsmrst#/gp44 gp45 psin/gp46 psout#/gp47 mdat mclk cputin systin gp55 gp54 gp53 gp52 gp51 gp50 auxfanin cpufanin sysfanin avcc cpufanout sysfanout agnd gp22 gp21/msi irqin0/gp20/mso gp17/gpsa2 gp16/gpsb2 gp15/gpy1 gp14/gpy2 gp13/gpx2 gp12/gpx1 gp11/gpsb1 gp10/gpsa1 drvden0 irqin1/smi# index# moa# ovt# dsa# auxfanout dir# step# wd# we# vcc trak0# wp# rdata# head# dskchg# clkin pme# gnd pciclk ldrq# serirq lad3 lad2 lad1 lad0 3vcc lframe# lreset# slct pe busy ack# pd7 pd6 pd5 pd4 W83627THF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
W83627THF publication release date: august 7, 2003 - 9 - revision 0.8 5. pin description note: please refer to section 6.2 dc characteristics for details. aout - analog output pin ain - analog input pin in cs - cmos level schmitt-triggered input pin in t - ttl level input pin in td - ttl level input pin with internal pull down resistor in ts - ttl level schmitt-triggered input pin in tsp3 - 3.3v ttl level schmitt-triggered input pin in tu - ttl level input pin with internal pull up resistor i/o 8t - ttl level bi-directional pin with 8 ma source-sink capability i/o 12t - ttl level bi-directional pin with 12 ma source-sink capability i/o 12tp3 - 3.3 v ttl level bi-directional pi n with 12 ma source-sink capabilities i/od 12ts - ttl level bi-directional sc hmitt-triggered pin. open-drain output with 12 ma sink capability i/od 12tp3 - 3.3 v ttl level bi-directional pin. open-drain output with 12 ma sink capability i/od 16cs - cmos level schmitt-triggered bi-directional pin. open-drain output with 16 ma sink capability i/od 24t - ttl level bi-directional pin. o pen-drain output with 24 ma sink capability out 12tp3 - 3.3v ttl level output pin with 12 ma source-sink capability out 8 - ttl level output pin with 8 ma source-sink capability out 12 - ttl level output pin with 12 ma source-sink capability out 24 - ttl level output pin with 24 ma source-sink capability od 8 - open-drain output pin with 8 ma sink capability od 12 - open-drain output pin with 12 ma sink capability od 24 - open-drain output pin with 24 ma sink capability
W83627THF publication release date: august 7, 2003 - 10 - revision 0.8 5.1 lpc interface symbol pin i/o function clkin 18 in t system clock input. according to the input frequency 24mhz or 48mhz, it is selectable through regi ster. default is 24mhz input. pme# 19 od 8 generated pme event. pciclk 21 in tsp3 pci 33 mhz clock input. ldrq# 22 out 12tp3 encoded dma request signal. serirq 23 i/od 12tp3 serial irq input/output. lad[3:0] 24-27 i/o 12tp3 these signal lines communicate address, control, and data information over the lpc bus between a host and a peripheral. lframe# 29 in tsp3 indicates start of a new cycle or termination of a broken cycle. lreset# 30 in tsp3 reset signal. it can connect to pcirst# signal on the host.
W83627THF publication release date: august 7, 2003 - 11 - revision 0.8 5.2 fdc interface symbol pin i/o function drvden0 1 od 24 drive density select bit 0. index# 3 in cs this schmitt-triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. this input pin is pulled up internally by a 1 k ? resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). moa# 4 od 24 motor a on. when set to 0, this pin enables disk drive 0. this is an open drain output. dsa# 6 od 24 drive select a. when set to 0, this pin enables disk drive a. this is an open drain output. dir# 8 od 24 direction of the head step motor. an open drain output. logic 1 = outward motion logic 0 = inward motion step# 9 od 24 step output pulses. this active low open drain output produces a pulse to move the head to another track. wd# 10 od 24 write data. this logic low open drain writes pre-compensation serial data to the selected fdd. an open drain output. we# 11 od 24 write enable. an open drain output. trak0# 13 in cs track 0. this schmitt-triggered input from the disk drive is active low when the head is positioned over the outermost track. this input pin is pulled up internally by a 1 k ? resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). wp# 14 in cs write protected. this active low schmitt input from the disk drive indicates that the diskette is wr ite-protected. this input pin is pulled up internally by a 1 k ? resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). rdata# 15 in cs the read data input signal from the fdd. this input pin is pulled up internally by a 1 k ? resistor. the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn). head# 16 od 24 head select. this open drain output determines which disk drive head is active. logic 1 = side 0 logic 0 = side 1 dskchg# 17 in cs diskette change. this signal is active low at power on and whenever the diskette is remov ed. this input pin is pulled up internally by a 1 k ? . the resistor can be disabled by bit 7 of l0-crf0 (fipurdwn).
W83627THF publication release date: august 7, 2003 - 12 - revision 0.8 5.3 multi-mode parallel port the following pins have alternate functions , which are controlled by cr28 and l3-crf0. symbol pin i/o function slct 31 in t printer mode: an active high input on this pin indicates that the printer is selected. refer to the description of the parallel port for definition of this pin in ecp and epp mode. pe 32 in t printer mode: an active high input on this pin indicates that the printer has detected the end of the paper. refe r to the description of the parallel port for the definition of this pin in ecp and epp mode. busy 33 in t printer mode: an active high input indicates that the printer is not ready to receive data. refer to the description of the parallel port for definition of this pin in ecp and epp mode. ack# 34 in t printer mode: ack# an active low input on this pin indicates that the printer has received data and is ready to accept more data. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. err# 45 in t printer mode: err# an active low input on this pin indicates that the printer has encountered an error condition. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. slin# 43 od 12 printer mode: slin# output line for detection of printer selection. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. init# 44 od 12 printer mode: init# output line for the printer initialization. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. afd# 46 od 12 printer mode: afd# an active low output from this pin causes the printer to auto feed a line after a line is printed. refer to the description of the parallel port for the definition of this pin in ecp and epp mode.
W83627THF publication release date: august 7, 2003 - 13 - revision 0.8 3.3 multi-mode parallel port, continued symbol pin i/o function stb# 47 od 12 printer mode: stb# an active low output is used to latch the parallel data into the printer. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd0 42 i/o 12t printer mode: pd0 parallel port data bus bit 0. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd1 41 i/o 12t printer mode: pd1 parallel port data bus bit 1. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd2 40 i/o 12t printer mode: pd2 parallel port data bus bit 2. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. extension fdd mode: wp2# pd3 39 i/o 12t printer mode: pd3 parallel port data bus bit 3. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd4 38 i/o 12t printer mode: pd4 parallel port data bus bit 4. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd5 37 i/o 12t printer mode: pd5 parallel port data bus bit 5. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd6 36 i/o 12t printer mode: pd6 parallel port data bus bit 6. refer to the description of the parallel port for the definition of this pin in ecp and epp mode. pd7 35 i/o 12t printer mode: pd7 parallel port data bus bit 7. refer to the description of the parallel port for the definition of this pin in ecp and epp mode.
W83627THF publication release date: august 7, 2003 - 14 - revision 0.8 5.4 serial port interface symbol pin i/o function ctsa# 49 in t clear to send. it is the modem control input. the function of these pins can be tested by reading bit 4 of the handshake status register. ctsb# 78 in t i/o 12t clear to send. it is the modem control input. the function of these pins can be tested by reading bit 4 of the handshake status register. dsra# 50 in t data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. dsrb# 79 in t data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. rtsa# hefras 51 i/o 8t uart a request to send. an active low signal informs the modem or data set that the cont roller is ready to send data. during power-on reset, this pin is pulled down internally and is defined as hefras, which provides the power-on value for cr26 bit 6 (hefras). a 4.7 k ? is recommended if intends to pull up. (select 4eh as configuration i/o port s address) rtsb# 80 i/o 8t uart b request to send. an active low signal informs the modem or data set that the cont roller is ready to send data. dtra# pnpcsv# 52 i/o 8t uart a data terminal ready. an active low signal informs the modem or data set that the controller is ready to communicate. during power-on reset, this pin is pulled down internally and is defined as pnpcsv# , which provides the power-on value for cr24 bit 0 ( pnpcsv# ). a 4.7 k ? is recommended if intends to pull up. (clear the default value of fdc, uarts, prt, game port and midi port) dtrb# 81 i/o 8t uart b data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate. sina 53 in t serial input. it is used to re ceive serial data through the communication link. sinb 82 in tt serial input. it is used to re ceive serial data through the communication link.
W83627THF publication release date: august 7, 2003 - 15 - revision 0.8 3.4 serial port interface, continued symbol pin i/o function souta penkbc 54 i/o 8t uart a serial output. it is used to transmit serial data out to the communication link. during power-on reset, this pin is pulled down internally and is defined as penkbc, which provides the power-on value for cr24 bit 2 (enkbc). a 4.7 k ? resistor is recommended if intends to pull up. (enable kbc) soutb pen48 83 i/o 8t uart b serial output. during power-on reset, this pin is pulled down internally and is defined as pen48, which provides the power-on value for cr24 bit 6 (en48). a 4.7 k ? resistor is recommended if intends to pull up. dcda# 56 in t data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. dcdb# 84 in t data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. ria# 57 in t ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. rib# 85 in t ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 5.5 kbc interface symbol pin i/o function ga20m 59 out 12 gate a20 output. this pin is high after system reset. (kbc p21) kbrst 60 out 12 keyboard reset. this pin is high after system reset. (kbc p20) kdat 63 i/od 16cs keyboard data. mclk 65 i/od 16cs ps2 mouse clock. mdat 66 i/od 16cs ps2 mouse data.
W83627THF publication release date: august 7, 2003 - 16 - revision 0.8 5.6 hardware monitor interface symbol pin i/o function beep 58 od 8 beep function for hardware monitor. this pin is low after system reset. caseopen# 76 in t case open. an active low input from an external device when case is opened. this sig nal can be latched if pin vbat is connect to battery, ev en W83627THF is power off. vin0 99 ain 0v to 4.096v fsr analog inputs. vin1 98 ain 0v to 4.096v fsr analog inputs. vin2 97 ain 0v to 4.096v fsr analog inputs. cpuvcore 100 ain 0v to 4.096v fsr analog inputs. vref 101 aout reference voltage for temperature maturation. auxtin 102 ain temperature sensor 3 inputs. it is used for temperature maturation. cputin 103 ain temperature sensor 2 inputs. it is used for cpu1 temperature maturation. systin 104 ain temperature sensor 1 input. it is used for system temperature maturation. ovt# 111 od 12 over temperature shutdown output. it indicated the temperature is over temperature limit. auxfanin cpufanin sysfanin 5 112 113 i/o 12ts 0v to +5v amplitude fan tachometer input. sysfanout cpufanout auxfanout 116 115 7 aout fan speed control. output analog voltage level to control the fan's speed.
W83627THF publication release date: august 7, 2003 - 17 - revision 0.8 5.7 game port symbol pin i/o function gpsa1 gp10 128 in cs i/od 12cs active-low, joystick i switch input 1. (default) general purpose i/o port 1 bit 0. gpsb1 gp11 127 in cs i/od 12cs active-low, joystick ii switch input 1. (default) general purpose i/o port 1 bit 1. gpx1 gp12 126 i/od 12cs joystick i timer pin. this pin connects to x positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 2. gpx2 gp13 125 i/od 12cs i/od 12cs joystick ii timer pin. this pin connects to x positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 3. gpy2 gp14 124 i/od 12cs i/od 12cs joystick ii timer pin. this pin connects to y positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 4. gpy1 gp15 123 i/od 12cs i/od 12cs joystick i timer pin. this pin connects to y positioning variable resistors for the joystick. (default) general purpose i/o port 1 bit 5. gpsb2 gp16 122 in cs i/od 12cs active-low, joystick ii switch input 2. this pin has an internal pull- up resistor. (default) general purpose i/o port 1 bit 6. gpsa2 gp17 121 in cs i/od 12cs active-low, joystick i switch input 2. this pin has an internal pull- up resistor. (default) general purpose i/o port 1 bit 7.
W83627THF publication release date: august 7, 2003 - 18 - revision 0.8 5.8 general purpose i/o port 5.8.1 general purpose i/o port 1 (power source is vcc) see 3.7 game port 5.8.2 general purpose i/o port 2 (power source is vcc) symbol pin i/o function gp20 mso irqin0 120 i/od 12t out 12 in t general purpose i/o port 2 bit 0. midi serial data output. (default) irq channel input 0. gp21 msi 119 i/od 12t in tu general purpose i/o port 2 bit 1. midi serial data input. it is internally pulled up by a 40 k ohms resistor. (default) gp22 118 i/od 12t general purpose i/o port 2 bit 2. (default) gp23 96 i/od 12t general purpose i/o port 2 bit 3. (default) gp24 95 i/od 12t general purpose i/o port 2 bit 4. (default) gp25 94 i/od 12t general purpose i/o port 2 bit 5. (default) gp26 93 i/od 12t general purpose i/o port 2 bit 6. (default) smi# irqin1 2 od 24 in t system management interrupt channel output. irq channel input 1.
W83627THF publication release date: august 7, 2003 - 19 - revision 0.8 5.8.3 general purpose i/o port 3, 4 (power source is vsb) symbol pin i/o function gp30 92 i/od 12t general purpose i/o port 3 bit 0. gp31 91 i/od 12t general purpose i/o port 3 bit 1. gp32 pled 90 i/od 24t out 24 general purpose i/o port 3 bit 2. power led output. gp33 wdto 89 i/od 12t out 12 general purpose i/o port 3 bit 3. (default) watchdog time out output. gp34 irrx 88 i/od 12ts in ts general purpose i/o port 3 bit 4. irrx input. (default) irtx 87 out 12 infrared transmitter output. (default) gp35 86 i/od 12t general purpose i/o port 3 bit 5. (default) gp37 susled/ 64 i/od 24t out 24 general purpose i/o port 3 bit 7. suspend led output, it can program to flash when suspend state. this function can wo rk without vcc. (default) gp40 75 i/od 8t general purpose i/o port 4 bit 0. gp41 slp_sx# 73 i/od 12t in t general purpose i/o port 4 bit 1. slp_s3# input. (default) gp42 pwrctl# 72 i/od 12t od 12 general purpose i/o port 4 bit 2. this pin generates the pwrctl# signal while the power failure. (default) gp43 pwrok 71 i/od 12t od 12 general purpose i/o port 4 bit 3. this pin generates the pwrok signal while the vcc come in. (default) gp44 rsmrst# 70 i/od 12t od 12 general purpose i/o port 4 bit 4. this pin generates the rsmrst signal while the vsb come in. (default) gp45 69 i/od 12t general purpose i/o port 4 bit 5. gp46 psin 68 i/od 12t in td general purpose i/o port 4 bit 6. panel switch input. this pin is high active with an internal pull down resistor. (default) gp47 psout# 67 i/od 12t od 12 general purpose i/o port 4 bit 7. panel switch output. this signal is used for wake-up system from s5 cold state. this pin is pulse output, active low. (default)
W83627THF publication release date: august 7, 2003 - 20 - revision 0.8 5.8.4 general purpose i/o port 5 (power source is vcc) symbol pin i/o function gp50 110 i/o 12tp3 general purpose i/o port 5 bit 0. gp51 109 i/o 12tp3 general purpose i/o port 5 bit 1. gp52 108 i/o 12tp3 general purpose i/o port 5 bit 2. gp53 107 i/o 12tp3 general purpose i/o port 5 bit 3. gp54 106 i/o 12tp3 general purpose i/o port 5 bit 4. gp55 105 i/o 12tp3 general purpose i/o port 5 bit 5. note. the gpio port 5 could be used as vid input / output function for vrd10. 5.9 power pins symbol pin function vcc 12, 48 +5v power supply for the digital circuitry. 5vsb 61 +5v stand-by power supply for the digital circuitry. 3vcc 28 +3.3v power supply for driving 3v on host interface. avcc 114 analog vcc input. internally supplier to all analog circuitry. vbat 74 battery voltage input. agnd 117 analog ground. gnd 20, 55 ground. 5.10 gpio pin power source symbol power source gpio port 1 vcc gpio port 2 vcc gpio port 3 v sb gpio port 4 v sb gpio port 5 vcc
W83627THF publication release date: august 7, 2003 - 21 - revision 0.8 6. general purpose i/o W83627THF provides 36 input/output ports that can be individually configured to perform a simple basic i/o function or a pre-defined alternate function. those 36 gp i/o ports are divided into five groups . the first and fifth groups are configured through control registers in logical device 7, the second group in logical device 8, and the third and forth groups in logical device 9. users can configure each individual port to be an input or output port by programming respective bit in selection register (crf0/f3: 0 = output, 1 = input). invert por t value by setting inversion register (crf2/f5: 0 = non-inverse, 1 = inverse). port value is read/wr itten through data register (crf1/crf4). table 4-1 and 4-2 give more details on gpio's assignment. fi gure 4-1 shows the gp i/o port's structure. after power-on reset those ports default to perform basic in put function which maintains its previous settings until a battery loss condition. selection bit 0 = output 1 = input inversion bit 0 = non inverse 1 = inverse basic i/o operations 0 0 basic non-inverting output 0 1 basic inverting output 1 0 basic non-inverting input 1 1 basic inverting input table 4-1
W83627THF publication release date: august 7, 2003 - 22 - revision 0.8 table 4-2 gp i/o port data register register bit assignment gp i/o port bit 0 gp10 bit 1 gp11 bit 2 gp12 bit 3 gp13 bit 4 gp14 bit 5 gp15 bit 6 gp16 gp1(vcc power) bit 7 gp17 bit 0 gp20 bit 1 gp21 bit 2 gp22 bit 3 gp23 bit 4 gp24 bit 5 gp25 gp2(vcc power) bit 6 gp26 bit 0 gp30 bit 1 gp31 bit 2 gp32 bit 3 gp33 bit 4 gp34 bit 5 gp35 bit 6 gp36 gp3(vsb power) bit 7 gp37 bit 0 gp40 bit 1 gp41 bit 2 gp42 bit 3 gp43 bit 4 gp44 bit 5 gp45 bit 6 gp46 gp4(vsb power) bit 7 gp47 bit 0 gp50 bit 1 gp51 bit 2 gp52 bit 3 gp53 bit 4 gp54 gp5(vcc power) bit 5 gp55
W83627THF publication release date: august 7, 2003 - 23 - revision 0.8 figure 4-1
W83627THF publication release date: august 7, 2003 - 24 - revision 0.8 7. hardware monitor 7.1 general description the W83627THF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatur es, which are very important for a high-end computer system to work stable and properly . W83627THF provides lpc interface to access hardware . an 8-bit analog-to-digital converter (adc) was built inside W83627THF. the W83627THF can simultaneously monitor 3 analog voltage inputs (addition monitor v bat, 5vsb & 5vcc power), 3 fan tachometer inputs, 3 remote temperature inputs and one case-open detection signal. the remote temperature sensing can be performed by thermistors, 2n3904 npn-type tr ansistors, or directly from intel tm cpu thermal diode output. also the w83627th f provides: 3 analog outputs for fan speed control. beep tone output for warning; smi#(c an through serirq pin), ovt# signals for system protection events. through the application software or bios, the users c an read all the monitored parameters of system from time to time. and a pop-up warning can be also activated when the monitored item was out of the proper/preset range. the application software could be winbond's hardware doctor tm , or intel tm ldcm (landesk client management), or other m anagement application software. also the users can set up the upper and lower limits (alarm thresholds ) of these monitored parameters and to activate one programmable and maskable interrupts. an opti onal beep tone could be used as warning signal when the monitored parameters ar e out of the preset range. 7.2 access interface W83627THF uses lpc bus to access which the ports address of low byte (bit2~bit0) are defined in the port 5h and 6h. the other higher bits of these ports are set by W83627THF itself. the general decoded address is set to port 295h and port 296h. t hese two ports are described as following: port 295h: index port. port 296h: data port. the register structure is showed as the figure 5-1
W83627THF publication release date: august 7, 2003 - 25 - revision 0.8 configuration register 40h interrupt status registers 41h, 42h smi# mask registers 43h-44h fan divisor register i 47h serial bus address 48h monitor value registers 20h~3fh device id 49h temperature 2, 3 serial bus address 4ah 4bh smi#/ovt# control register 4ch fan in/out and beep/gpo# control register 4dh bank select for 50h~5fh registers. 4eh winbond vendor id 4fh bank 0 beep control registers 56h~57h bank 0 chip id register 58h bank 0 temperature sensor type configuration & fan divisor bit2 registers 59h,5dh data register port 6h port 5h index register lpc bus smart fan configuration registers 00h-1fh bank 4 interrupt status & smi mask registers 50h~51h bank 4 beep control registers 53h bank 4 temperature offset registers 54h~56h bank 4 read time status registers 59h~5bh bank 5 59h~5bh monitor value registers fan divisor register i bank 0 winbond test registers 50h~55h bank 1 cputin temperature control/staus registers 50h~56h bank 2 vtin temperature control/staus registers 50h~56h figure 5-1 : lpc interface access diagram
W83627THF publication release date: august 7, 2003 - 26 - revision 0.8 7.3 analog inputs the maximum input voltage of the analog pin is 4.096v because the 8-bit adc has a 16mv lsb. really, the application of the pc monitoring would most often be connected to power suppliers. the cpu vcore voltage, +3.3v, battery(pin 74), avcc( pin 114) and 5vsb voltage c an directly connected to these analog inputs. the +12v voltage inputs should be reduced a factor with external resistors so as to obtain the input range. as figure 3.2 shows. figure. 5-2 7.3.1 monitor over 4.096v voltage: the +12v input voltage can be expressed as following equation. 2 1 2 1 0 r r r v vin + = the value of r1 and r2 can be selected to 28k ohms and 10k ohms, respectively, when the input voltage v1 is 12v. the node voltage of vin0 can be subject to less than 4.096v for the maximum input range of the 8-bit adc. pin 100 cpuvcore vin1(+3.3v) pin 98 pin 99 vin0 vbat pin 74 r1 v1 positive voltage input 8-bit adc with 16mv lsb 10k, 1% r thm vref pin 101 auxtin cputin systin pin 102 pin 103 pin 104 5vsb pin 61 10k@25 c, beta=3435k r2 r avcc pin 114 power inputs 30k, 1% r cap,3300p cpud+ cpud- vin2 pin 97 negative voltage input r3 r5 v2 r4
W83627THF publication release date: august 7, 2003 - 27 - revision 0.8 the -12v input voltage can be expressed as following equation. 12 , 6 . 3 4 3 ) 6 . 3 ( 2 2 4 2 ? = + + ? = wherev r r r v vin the value of r3 and r4 can be selected to 232k ohms and 56k ohms, respectively, when the input voltage v2 is -12v. the node voltage of vin2 ca n be subject to less than 4.096v for the maximum input range of the 8-bit adc. the pin 114 is connected to the power supply vcc wi th +5v. there are two functions in this pin with 5v. the first function is to supply internal analog power in the W83627THF and the second function is that this voltage with 5v is connected to internal serial resistors to monitor the +5v voltage. the W83627THF internal two serial resistors are 34k ohms and 51k ohms so that input voltage to adc is 3v which is less than 4.096v of adc maximum i nput voltage. the express equation can represent as follows. v k k k vcc v in 3 34 51 51 ? ? + ? ? = where vcc is set to 5v. the pin 61 is connected to 5vsb voltage. W83627THF monitors this voltage and the internal two serial resistors are 34k ? and 51k ? so that input voltage to adc is 3v which less than 4.096v of adc maximum input voltage. 7.3.2 cpuvcore voltage detection method: W83627THF provides two detection methods for cpuvcore(pin100). (1). vrm8 method: the lsb of this mode is 16mv. this means that the detected voltage equals to the reading of this voltage register multiplies 16mv. the formula is as the following: detected voltage = 016 . 0 re ? ading v (2). vrm9 method: (default) the lsb of this mode is 4.88mv which is especially designed for the low voltage cpu. the formula is as the following: detected voltage = 69 . 0 00488 . 0 re + ? ading v
W83627THF publication release date: august 7, 2003 - 28 - revision 0.8 7.3.3 temperature measurement machine the temperature data format is 8-bit two's-c omplement for sensor systin and 9-bit two's- complement for sensor cputin and auxtin. the 8-bit temperature data can be obtained by reading the cr[27h]. the 9-bit temperature data can be obtained by reading the 8 msbs from the bank1/bank2 cr[50h] and the lsb from the bank1/bank2 cr[51h] bit 7. the format of the temperature data is show in table 5-1. temperature 8-bit digital ou tput 9-bit digital output 8-bit binary 8-bit hex 9-bit binary 9-bit hex +125 c 0111,1101 7dh 0,1111,1010 0fah +25 c 0001,1001 19h 0,0011,0010 032h +1 c 0000,0001 01h 0,0000,0010 002h +0.5 c - - 0,0000,0001 001h +0 c 0000,0000 00h 0,0000,0000 000h -0.5 c - - 1,1111,1111 1ffh -1 c 1111,1111 ffh 1,1111,1110 1ffh -25 c 1110,0111 e7h 1,1100,1110 1ceh -55 c 1100,1001 c9h 1,1001,0010 192h table 5-1 7.3.3.1 monitor temperature from thermistor: the W83627THF can connect three thermistors to measure three different environment temperature. the specification of thermistor should be considered to (1) value is 3435k, (2) resistor value is 10k ohms at 25 c. in the figure 5-2, the themistor is connect ed by a serial resistor with 10k ohms, then connect to vref (pin 101). 7.3.3.2 monitor temperature from pentium ii tm /pentium iii tm thermal diode or bipolar transistor 2n3904 the W83627THF can alternate the thermistor to pentium ii tm /pentium iii tm thermal diode interface or transistor 2n3904 and the circuit connection is shown as figure 5-3. the pin of pentium ii tm /pentium iii tm d- is connected to agnd and the pin d+ is connected to temperature sensor pin in the W83627THF. the resistor r = 30k ohms should be connected to vref to supply the diode bias current and the bypass capacitor c = 3300pf should be added to filter the high frequency noise. the transistor 2n3904 should be connected to a form with a diode, that is, the base (b) and collector (c) in the 2n3904 should be tied together to act as a thermal diode.
W83627THF publication release date: august 7, 2003 - 29 - revision 0.8 2n3904 c e b r=30k,1% c=3300pf bipolar transistor temperature sensor pentium ii/iii cpu d+ d- therminal diode c=3300pf r=30k,1% vref vtin cputin or W83627THF agnd figure 5-3 7.4 fan speed count and fan speed control 7.4.1 fan speed count inputs are provides for signals from fans equipped wi th tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage can?t be over vcc. if the input signals from the tachometer outputs are over the vcc, the external trimming circuit should be added to reduce the voltage to obtain the input specific ation. the normal circuit and trimming circuits are shown as figure 5-4 ~ 5-7. determine the fan counter according to: diviso r r pm count = 6 10 35 . 1 in other words, the fan speed counter has been read from register cr28 or cr29 or cr2a, the fan speed can be evaluated by the following equation. rpm count divisor = 135 10 6 . the default divisor is 2 and defined at cr47.bit7 ~4, cr4b.bit7~6, and bank0 cr5d.bit5~7 which are three bits for divisor. that provides very low speed fan counter such as power supply fan. the followed table is an example for the relation of divisor, rpm, and count .
W83627THF publication release date: august 7, 2003 - 30 - revision 0.8 divisor nominal rpm time per revolution counts 70% rpm time for 70% 1 8800 6.82 ms 153 6160 9.84 ms 2 (default) 4400 13.64 ms 153 3080 19.48 ms 4 2200 27.27 ms 153 1540 38.96 ms 8 1100 54.54 ms 153 770 77.92 ms 16 550 109.08 ms 153 385 155.84 ms 32 275 218.16 ms 153 192 311.68 ms 64 137 436.32 ms 153 96 623.36 ms 128 68 872.64 ms 153 48 1246.72 ms table 5-2 fan connecto r fan ou t +12 v gnd pull-up resiste r 4.7k ohms +5v +12 v fan inpu t pin112 -113,5 W83627THFd fan connecto r fan ou t +12 v gnd pull-up resiste r 4.7k ohms +12 v fan inpu t 14k~39 k 10 k figure 5-5. fan with tach pull-up to +12v, or totem-pole output and register attenuator figure 5-4. fan with tach pull-up to +5v fan connecto r fan ou t +12 v gnd pull-up resiste r > 1 k +12 v fan inpu t pin 112-113,5 fan connecto r fan ou t +12 v gnd pull-up resister < 1 k or totem-pole outpu t +12 v fan inpu t pin 112-113,5 > 1 k figure 5-7. fan with tach pull-up to +12v, or totem-pole putput and zener clamp figure 5-6. fan with tach pull-up to +12v and zener clamp 3.9v zene r 3.9v zene r W83627THFd pin 112-113,5 W83627THFd W83627THFd
W83627THF publication release date: august 7, 2003 - 31 - revision 0.8 7.4.2 fan speed control the W83627THF has a 4 bit dac which produces 0 to 5 volts dc output that provides maximum 3 sets for fan speed control. the analog output can be programmed in the bank0 index 01h, index 03h and index 11h. the default value is 0xfy,y is reserv ed nibble, that is default output value is 5 v. the expression of output voltage can be represented as follow , output voltage 16 value register bit - 4 programmed = avcc the application circuit is shown as follow, + - lm358 3 2 1 4 11 20k fanout fan 3 2 1 0 io-12v 28k npn 0.1u io+12v io+12v r1 c1 tachometer output r3 r4 q1 figure 5-8 must be take care when choosing the op-amp and the transistor. the op-amp is used for amplify the 5v range of the dc output up to 12v . the transistor should has a suitable value to avoid its base current pulling down the op-amp ?s output and gain t he common current to operate the fan at fully speed.
W83627THF publication release date: august 7, 2003 - 32 - revision 0.8 7.5 smartfan tm control smartfan tm control provides two mechanisms. one is thermal cruise mode and the other is fan speed cruise mode. no matter which mode you use, the fan will full speed run at beginning. 7.5.1 thermal cruise mode there are maximum 3 pairs of temperature/fanout control at this mode: systin with sysfanout, cputin with cpufanout, auxtin with auxfanout. at this mode, W83627THF provides the smart fan system which can cont rol the fan speed automat ically depend on current temperature to keep it with in a specific range. at first a wanted temperature and interval must be set (ex. 55 c 3 c) by bios, as long as the real temperat ure remains below the setting value, the fan will be off. once the temperature exceeds the setting high limit temperature ( 58 c), the fan will be turned on with a specific speed set by bios (ex: 3.75 v) and automatically controlled its dc voltage output with the temperature varying. three conditions may occur : (1) if the temperature still ex ceeds the high limit (ex: 58 c), dc fan output voltage will increase slowly. if the fan has been operating in its fully speed but the temperatur e still exceeds the high limit(ex: 58 c) after 3 minutes, a warning message will be issued to protect the system. (2) if the temperature goes below the high limit (ex: 58 c), but above the low limit (ex: 52 c), the fan speed will be fixed at the current speed because the temperature is in the target area(ex: 52 c ~ 58 c). (3) if the temperature goes below the low limit (ex: 52 c), dc fan output voltage will decrease slowly to 0 until the temperature exceeds the low limit. figure 5-9 and 5-10 give the illustration for thermal cruise mode . 55`c 58`c 52`c dc output voltage 5 0 2.5 fan start = 1.875 v a b c d target temperature tolerance tolerance figure 5-9
W83627THF publication release date: august 7, 2003 - 33 - revision 0.8 55`c 58`c 52`c dc output voltage 5 0 2.5 fan start = 1.875v fan stop = 1.25v fan start = 1.875v abc d target temperature tolerance tolerance figure 5-10 one more protection is provided t hat dc fan output voltage will not be decreased to 0 in the above (3) situation in order to keep the fans running with a minimum speed. by setting cr[12h] bit3-5 to 1, fan output voltage will be decreased to the ? st op value ? which are defined at cr[08h],cr[09h] and cr[15h]. 7.5.2 fan speed cruise mode there are 3 pairs of fanin/fano ut control at this mode: sysfan in with sysfanout, cpufanin with cpufanout, auxfanin with auxfanout. at this mode, W83627THF provides the smart fan system which can control the fan speed automa tically depend on current fan speeds to keep it with in a specific range. a wanted fan speed count and interval must be set (ex. 160 10 ) by bios. as long as the fan speed count is the specific ra nge, output voltage will keep the current value. if current fan speed count is higher than the high limit (ex. 160+10), output voltage will be increased to keep the count less than the high limit. otherwise, if current fan speed is less than the low limit(ex. 160-10), output voltage will be decreased to keep th e count higher than the low limit. see figure 5-11 example. 160 170 150 dc output voltage 5 0 2.5 a c count figure 5-11
W83627THF publication release date: august 7, 2003 - 34 - revision 0.8 7.5.3 manual control mode smart fan control system can be disabled and the fan speed control algorithmic can be programmed by bios or application software. the progr amming method is just as section 5.4.2. 7.6 smi# interrupt mode the smi#/irqin1 pin(pin2) is a multi-function pin. the smi# function is selected at configuration register cr[2ah] bit 2. 7.6.1 voltage smi# mode: smi# interrupt for voltage is two-times interrupt mode. voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by re ading all the interrupt status register. (figure 5-12) 7.6.2 fan smi# mode: smi# interrupt for fan is two-times interrupt mode . fan count exceeding the limit, or exceeding and then going below the limit, will causes an interrupt if the previous interrupt has been reset by reading all the interrupt status register. (figure 5-13) *** *interrupt reset when interrupt status registers are read smi# * high limit low limit * smi# * fan count limit figure 5-12 figure 5-13
W83627THF publication release date: august 7, 2003 - 35 - revision 0.8 7.6.3 the W83627THF temperature sensor 1(systin) smi# interrupt has 3 modes: (1) comparator interrupt mode setting the t hyst (temperature hysteresis) limit to 127 c will set temperature sensor 1 smi# to the comparator interrupt mode. temperature exceeds t o (over temperature) limit causes an interrupt and this interrupt will be reset by reading all the inte rrupt status register. on ce an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t o , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t o . (figure 5-14) . setting the t hyst lower than t o will set temperature sensor 1 sm i# to the interrupt mode. the following are two kinds of interrupt modes, which are selected by index 4ch bit5 : (2) two-times interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 5-15 ) (3) one-time interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will not cause an interrupt. once an interrupt event has occurred by exceeding t o , then going below t hyst, an interrupt will not occur again until the temperature exceeding t o . (figure 5-16 ) t oi t hyst ** *interrupt reset when interrupt status registers are read t oi t hyst smi# smi# ** * * * 127'c figure 5-14 figure 5-15
W83627THF publication release date: august 7, 2003 - 36 - revision 0.8 *interrupt reset when interrupt status registers are read t oi t hyst smi# * * figure 5-16 7.6.4 the W83627THF temperature sensor 2(cputin) and sensor 3(auxtin) smi# interrupt has two modes and it is programmed at cr[4ch] bit 6. (1) comparator interrupt mode temperature exceeding t o causes an interrupt and this inte rrupt will be reset by reading all the interrupt status register. once an interru pt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will occur again when the next conversion has completed. if an interrupt event has occurred by exceeding t o and not reset, the interrupts will not occur again. the interrupts will continue to occur in this manner until the temperature goes below t hyst . ( figure 5-17 ) (2) two-times interrupt mode temperature exceeding t o causes an interrupt and then temperature going below t hyst will also cause an interrupt if the previous interrupt has been reset by reading all the interrupt status register. once an interrupt event has occurred by exceeding t o , then reset, if the temperature remains above the t hyst , the interrupt will not occur. (figure 5-18 ) t oi t hyst *** *interrupt reset when interrupt status registers are read t oi t hyst smi# smi# ** * * * figure 5-17 figure 5-18
W83627THF publication release date: august 7, 2003 - 37 - revision 0.8 7.7 ovt# interrupt mode the ovt# mode selection bits are at bank0 i ndex18h bit4, bank1 index52h bit1 and bank2 index52h bit1. (1) comparator mode: temperature exceeding t o causes the ovt# output activated until the temperature is less than t hyst . ( figure 5-19) (2) interrupt mode: temperature exceeding t o causes the ovt# output activat ed indefinitely until reset by reading temperature sensor register s. temperature exceeding t o , then ovt# reset, and then temperature going below t hyst will also cause the ovt# activated inde finitely until reset by reading temperature sensor registers. once the ovt# is activated by exceeding t o , then reset, if the temperature remains above t hyst , the ovt# will not be activated again.( figure 5-19) t hyst ** *interrupt reset when temperature sensor registers are read ovt# ovt# * (comparator mode; default) (interrupt mode) to figure 5-19
W83627THF publication release date: august 7, 2003 - 38 - revision 0.8 7.8 registers and ram address port and data port are set in the register cr60 and cr61 of logical device b which is hardware monitor device. the value in cr60 is high byte and that in cr61 is low byte. for example, setting cr60 to 02 and cr61 to 90 cause the address port to be 0x295 and data port to be 0x296. 7.8.1 address port (port x5h) address port: port x5h power on default value 00h attribute: bit 6:0 read/write , bit 7: reserved size: 8 bits 7 6 5 4 3 2 1 0 data bit7: reserved bit 6-0: read/write bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved address pointer (power on default 00h) (power on default 0) a6 a5 a4 a3 a2 a1 a0 7.8.2 data port (port x6h) data port: port x6h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 data bit 7-0: data to be read from or to be written to ram and register.
W83627THF publication release date: august 7, 2003 - 39 - revision 0.8 7.8.3 configuration register ? index 40h register location: 40h power on default value 03h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 start smi#enable reserved int_clear reserved reserved reserved initialization bit 7: a one restores power on default value to some r egisters. this bit clears it self since the power on default is zero. bit 6: reserved bit 5: reserved bit 4: reserved bit 3: a one disables the smi# output without affect ing the contents of interrupt status registers. the device will stop monitoring. it will resume upon clearing of this bit. bit 2: reserved bit 1: a one enables the smi# interrupt output. bit 0: a one enables startup of monitoring oper ations, a zero puts the part in standby mode. note: the outputs of interrupt pins will not be cleared if the user writes a zero to this location after an interrupt has occurred unlike "int_clear'' bit. 7.8.4 interrupt status register 1 ? index 41h register location: 41h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 cpuvcore vin0 vin1 avcc(pin 114) systin cputin sysfanin cpufanin
W83627THF publication release date: august 7, 2003 - 40 - revision 0.8 bit 7: a one indicates the fan count limit of cpufanin has been exceeded. bit 6: a one indicates the fan count limit of sysfanin has been exceeded. bit 5: a one indicates a high limit of cputin temperature has been exceeded. bit 4: a one indicates a high limit of systin temperature has been exceeded . bit 3: a one indicates a high or low limit of avcc(pin 114) has been exceeded. bit 2: a one indicates a high or low limit of vin1 has been exceeded. bit 1: a one indicates a high or low limit of vin0 has been exceeded. bit 0: a one indicates a high or low limit of cpuvcore has been exceeded. 7.8.5 interrupt status register 2 ? index 42h register location: 42h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vin2 reserved reserved auxfanin caseopen auxtin tar1 tar2 bit 7: a one indicates that the cputin temperatur e has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of smartfan tm . bit 6: a one indicates that t he systin temperature ha s been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of smartfan tm . bit 5: a one indicates a high or low limit of auxtin temperature has been exceeded. bit 4: a one indicates case has been opened. bit 3: a one indicates the fan count limit of auxfanin has been exceeded . bit 2: reserved. bit 1: reserved. bit 0: a one indicates a high or low limit of vin2 has been exceeded.
W83627THF publication release date: august 7, 2003 - 41 - revision 0.8 7.8.6 smi# mask register 1 ? index 43h register location: 43h power on default value feh attribute: read/write size: 8 bits cpuvcore 7 6 5 4 3 2 1 0 vin0 vin1 avcc (pin 114) systin cputin sysfanin cpufanin bit 7-0: a one disables the corresponding interrupt status bit for smi interrupt. 7.8.7 smi# mask register 2 ? index 44h register location: 44h power on default value ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vin2 reserved reserved auxfanin caseopen auxtin tar1 tar2 bit 7-0: a one disables the corresponding interrupt status bit for smi interrupt. 7.8.8 reserved register ? index 45h?46h
W83627THF publication release date: august 7, 2003 - 42 - revision 0.8 7.8.9 fan divisor register i ? index 47h register location: 47h power on default value: 5fh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved sysfanindiv_b0 sysfanindiv_b1 cpufanindiv_b0 cpufanindiv_b1 bit 7-6: cpufanin divisor bit1:0 . bit 5-4: sysfanin divisor bit1:0. note : please refer to bank0 cr[5dh] , fan divisor table. 7.8.10 value ram ? index 20h- 3fh address a6-a0 description 20h cpuvcore reading 21h vin0 reading 22h vin1 reading 23h avcc(pin 114)reading 24h vin2 reading 25h reserved 26h reserved 27h systin temperature sensor reading 28h sysfanin reading note: this location stores the number of counts of the internal clock per revolution. 29h cpufanin reading note: this location stores the number of counts of the internal clock per revolution.
W83627THF publication release date: august 7, 2003 - 43 - revision 0.8 5.8.10 value ram ? index 20h- 3fh, continued address a6-a0 description 2bh cpuvcore high limit (pow er on default value is 1.75v) 2ch cpuvcore low limit (power on default value is 0v) 2dh vin0 high limit 2eh vin0 low limit 2fh vin1 high limit 30h vin1 low limit 31h avcc(pin 114) high limit 32h avcc(pin 114) low limit 33h vin2 high limit 34h vin2 low limit 35h reserved 36h reserved 37h reserved 38h reserved 39h systin temperature sensor high limit 3ah systin temperature sensor hysteresis limit 3bh sysfanin fan count limit note: it is the number of counts of the intern al clock for the low limit of the fan speed. 3ch cpufanin fan count limit note: it is the number of counts of the intern al clock for the low limit of the fan speed. 3dh auxfanin fan count limit note: it is the number of counts of the intern al clock for the low limit of the fan speed. 3e- 3fh reserved setting all ones to the high limits for voltages an d fans (0111 1111 binary for temperature) means interrupts will never be generated except the ca se when voltages go below the low limits.
W83627THF publication release date: august 7, 2003 - 44 - revision 0.8 7.8.11 device id register - index 49h register location: 49h power on default value 03h attribute: bit<7: 1> read only; bit<0> read/write size: 8 bits 7 6 5 4 3 2 1 0 did<6:0 > reserved bit 7-1: read only - device id<6:0> bit 0 :reserved. 7.8.12 reserved register ? index 4ah 7.8.13 fan divisor register ii - index 4bh register location: 4bh power on default value <7:0> 44h. attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved adcovsel adcovsel auxfanindiv_b0 auxfanindiv_b1 bit 7-6:auxfanin speed divisor. please refer to bank0 cr[5dh] , fan divisor table.
W83627THF publication release date: august 7, 2003 - 45 - revision 0.8 bit 5-4: select a/d converter clock input. <5:4> = 00 - default. adc clock select 22.5 khz. <5:4> = 01- adc clock select 5.6 khz. (22.5k/4) <5:4> = 10 - adc clock sele ct 1.4khz. (22.5k/16) <5:4> = 11 - adc clock sele ct 0.35 khz. (22.5k/64) bit 3-2: these two bits should be set to 01h. the default value is 01h. bit 1-0: reserved. 7.8.14 smi#/ovt# control register- index 4ch register location: 4ch power on default value 18h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved ovtpol dis_ovt2 dis_ovt3 en_t1_one t2t3_intmode reserved bit 7: reserved. user defined. bit 6: set to 1, the smi# output type of temperat ure cputin/auxtin is set to comparator interrupt mode. set to 0, the smi# output type is se t to two-times interrupt mode. (default 0) bit 5: set to 1, the smi# output type of temperatur e systin is one-time interrupt mode. set to 0, the smi# output type is two-times interrupt mode. bit 4: disable temperature sensor auxtin over-tem perature (ovt) output if set to 1. set 0, enable auxtin ovt output through pin ovt#. bit 3: disable temperature sensor cputin over-t emperature (ovt) output if set to 1. set 0, enable cputin ovt output through pin ovt#. bit 2: over-temperature polarity. write 1, ovt# acti ve high. write 0, ovt# active low. default 0. bit 1: reserved. bit 0: reserved.
W83627THF publication release date: august 7, 2003 - 46 - revision 0.8 7.8.15 fan in/out and beep control register- index 4dh register location: 4dh power on default value 15h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 faninc1 fanopv1 faninc2 fanopv2 faninc3 fanopv3 reserved reserved bit 7~6: reserved. bit 5: auxfanin output value if faninc3 sets to 0. write 1, pin 5 generates a logic high signal. write 0, pin 5 generates a logic low signal. this bit is default 0. bit 4: auxfanin input control. set to 1, pin 5 ac ts as fan tachometer input, which is default value. set to 0, this pin 5 acts as fan control signal and the output value of fan control is set by this register bit 5. bit 3: cpufanin output value if faninc2 sets to 0. write 1, then pin 112 always generate logic high signal. write 0, pin 112 always generates logic low signal. this bit default 0. bit 2: cpufanin input control. set to 1, pin 112 acts as fan tachometer input, which is default value. set to 0, this pin 112 acts as fan control signal and the output value of fan control is set by this register bit 3. bit 1: sysfanin output value if faninc1 sets to 0. write 1, then pin 113 al ways generate logic high signal. write 0, pin 113 always generates logic low signal. this bit default 0. bit 0: sysfanin input control. set to 1, pin 113 acts as fan tachometer input, which is default value. set to 0, this pin 113 acts as fan control signal and the output value of fan control is set by this register bit 1.
W83627THF publication release date: august 7, 2003 - 47 - revision 0.8 7.8.16 register 50h ~ 5fh bank select register - index 4eh register location: 4eh power on default value 80h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 banksel0 banksel1 banksel2 reserved reserved reserved reserved hbacs bit 7: hbacs- high byte access. set to 1, access register 4fh high byte register. set to 0, access register 4fh low byte register. default 1. bit 6-3: reserved. this bit should be set to 0. bit 2-0: index ports 0x 50~0x5f bank select. set to 0, select bank0. set to 1, select bank1. set to 2, select bank2. 7.8.17 winbond vendor id register - index 4fh register location: 4fh power on default value <15:0> = 5ca3h attribute: read only size: 16 bits 15 8 7 0 vidh vidl bit 15-8: vendor id high byte if cr4e.bit7=1.default 5ch. bit 7-0: vendor id low byte if cr4e.bit7=0. default a3h.
W83627THF publication release date: august 7, 2003 - 48 - revision 0.8 7.8.18 winbond test register -- index 50h - 55h (bank 0) 7.8.19 beep control register 1-- index 56h ( bank 0 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vcore_bp en_vin0_bp en_vin1_bp en_avcc_bp en_systin_bp en_cputin_bp en_sysfanin_b p en_cpufanin_b p bit 7: beep output control for cpuf anin if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 6: beep output control for sysfanin if the moni tor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 5: beep output control for temperature cputin if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 4: beep output control for temperature systin if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 3: beep output control for av cc(pin 114) if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 2: beep output control for vin1 if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 1: beep output control for vin0 if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 0: beep output control for cpuvco re if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value.
W83627THF publication release date: august 7, 2003 - 49 - revision 0.8 7.8.20 beep control register 2-- index 57h ( bank 0 ) register location: 57h power on default value 80h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vin2_bp reserved reserved en_auxfanin_b p en_caso_bp en_auxtin_bp reserved en_gbp bit 7: global beep control. write 1, enable global beep output. default 1. write 0, disable all beep output. bit 6: reserved. bit 5: beep output control for temperature auxtin if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 4: beep output control for case open if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 3: beep output control for auxfanin if the moni tor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 2-1: reserved. bit 0: beep output control for vin1 if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. 7.8.21 chip id -- index 58h ( bank 0 ) register location: 58h power on default value 90h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 chipid bit 7-0: winbond chip id number. read this register will return 90h.
W83627THF publication release date: august 7, 2003 - 50 - revision 0.8 7.8.22 diode selection re gister -- index 59h ( bank 0 ) register location: 59h power on default value 70h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved reserved reserved selpiiv1 selpiiv2 selpiiv3 reserved bit 7 : reserved bit 6: diode mode selection of temperature auxtin if index 5dh bit3 is 1. set this bit to 1, select pentium ii cpu compatible thermal diode. set this bit to 0, select 2n3904 bipolar diode. bit 5: diode mode selection of temperature cputin if index 5dh bit2 is 1. set this bit to 1, select pentium ii cpu compatible thermal diode. set this bit to 0, select 2n3904 bipolar diode. bit 4: diode mode selection of temperature systin if i ndex 5dh bit1 is 1. set this bit to 1, select pentium ii cpu compatible thermal diode. set this bit to 0, select 2n3904 bipolar diode. bit 3-0: reserved 7.8.23 reserved -- index 5ah ( bank 0 ) 7.8.24 reserved -- index 5bh ( bank 0 ) 7.8.25 reserved -- index 5ch ( bank 0 )
W83627THF publication release date: august 7, 2003 - 51 - revision 0.8 7.8.26 vbat monitor control register -- index 5dh ( bank 0 ) register location: 5dh power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_vbat_mn t diodes1 diodes2 diodes3 reserved fandiv1_b2 fandiv2_b2 fandiv3_b2 bit 7: auxfanin divisor bit2. bit 6: cpufanin divisor bit2. bit 5: sysfanin divisor bit2. bit 4: reserved. bit 3: sensor type selection of auxtin. set to 1, select diode sensor. set to 0, select thermistor sensor. bit 2: sensor type selection of cputin. set to 1, select diode sensor. set to 0, select thermistor sensor. bit 1: sensor type selection of systin. set to 1, se lect diode sensor. set to 0, select thermistor sensor. bit 0: set to 1, enable battery voltage monitor. set to 0, disable battery voltage monitor. after set this bit from 0 to 1, the monitored value will be updated to the vbat r eading value register after one monitor cycle time. fan divisor table: bit 2 bit 1 bit 0 fan divisor bit 2 bit 1 bit 0 fan divisor 0 0 0 1 1 0 0 16 0 0 1 2 1 0 1 32 0 1 0 4 1 1 0 64 0 1 1 8 1 1 1 128 table 5-3 7.8.27 reserved register --5eh ( bank 0 ) 7.8.28 reserved register --5fh ( bank 0 )
W83627THF publication release date: august 7, 2003 - 52 - revision 0.8 7.8.29 cputin temperature sensor temperature (high byte) register - index 50h ( bank 1 ) register location: 50h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp<8:1> bit 7: temperature <8:1> of cputin sensor, which is high byte, means 1 c. 7.8.30 cputin temperature sensor temper ature (low byte) register - index 51h ( bank 1 ) register location: 51h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp<0> reserved bit 7: temperature <0> of cputin s ensor, which is low byte, means 0.5 c. bit 6-0: reserved.
W83627THF publication release date: august 7, 2003 - 53 - revision 0.8 7.8.31 cputin temperature sensor c onfiguration register - index 52h ( bank 1 ) register location: 52h power on default value 00h size: 8 bits 7 6 5 4 3 2 1 0 stop ovtmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting ovt# output to avoid false tripping due to noise. bit 2: read - reserved. this bit should be set to 0. bit 1: read/write - ovt# mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitor. 7.8.32 cputin temperature sensor hyster esis (high byte) register - index 53h ( bank 1 ) register location: 53h power on default value 4bh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst<8:1> bit 7-0: temperature hysteresis bit 8-1, which is high byte. the temperature default 75 degree c.
W83627THF publication release date: august 7, 2003 - 54 - revision 0.8 7.8.33 cputin temperature sensor hyster esis (low byte) register - index 54h ( bank 1 ) register location: 54h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst<0> reserved bit 7: hysteresis temperatur e bit 0, which is low byte. bit 6-0: reserved. 7.8.34 cputin temperature sensor over-te mperature (high byte) register - index 55h ( bank1 ) register location: 55h power on default value 50h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf<8:1> bit 7-0: over-temperature bit 8-1, which is high byte. the temperature default 80 degree c.
W83627THF publication release date: august 7, 2003 - 55 - revision 0.8 7.8.35 cputin temperature sensor over-te mperature (low byte) register - index 56h ( bank 1 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf<0> reserved bit 7: over-temperature bit 0, which is low byte. bit 6-0: reserved. 7.8.36 auxtin temperature sensor temperat ure (high byte) register - index 50h ( bank 2 ) register location: 50h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp<8:1 > bit 7: temperature <8:1> of sensor 2, which is high byte, means 1 c.
W83627THF publication release date: august 7, 2003 - 56 - revision 0.8 7.8.37 auxtin temperature sensor temperat ure (low byte) register - index 51h ( bank 2 ) register location: 51h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 temp<0> reserved bit 7: temperature <0> of sensor 3, which is low byte, means 0.5 c. bit 6-0: reserved. 7.8.38 auxtin temperature sensor conf iguration register - index 52h ( bank 2 ) register location: 52h power on default value 00h size: 8 bits 7 6 5 4 3 2 1 0 stop ovtmod reserved fault fault reserved reserved reserved bit 7-5: read - reserved. this bit should be set to 0. bit 4-3: read/write - number of faults to detect before setting ovt# output to avoid false tripping due to noise. bit 2: read - reserved. this bit should be set to 0. bit 1: read/write - ovt# mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 0: read/write - when set to 1 the sensor will stop monitor.
W83627THF publication release date: august 7, 2003 - 57 - revision 0.8 7.8.39 auxtin temperature sensor hyster esis (high byte) register - index 53h ( bank 2 ) register location: 53h power on default value 4bh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst<8:1> bit 7-0: temperature hysteresis bit 8-1, which is high byte. the temperature default 75 degree c. 7.8.40 auxtin temperature sensor hysteresi s (low byte) register - index 54h ( bank 2 ) register location: 54h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 thyst<0> reserved bit 7: hysteresis temperatur e bit 0, which is low byte. bit 6-0: reserved.
W83627THF publication release date: august 7, 2003 - 58 - revision 0.8 7.8.41 auxtin temperature sensor over-temp erature (high byte) register - index 55h ( bank 2 ) register location: 55h power on default value 50h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf<8:1> bit 7-0: over-temperature bit 8-1, which is high byte. the temperature default 80 degree c. 7.8.42 auxtin temperature sensor over-temp erature (low byte) register - index 56h ( bank 2 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 tovf<0> reserved bit 7: over-temperature bit 0, which is low byte. bit 6-0: reserved.
W83627THF publication release date: august 7, 2003 - 59 - revision 0.8 7.8.43 interrupt status register 3 -- index 50h (bank4) register location: 50h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 5vsb vbat tar3 reserved reserved reserved reserved reserved bit 7-3: reserved. bit 2: a one indicates that the auxtin temperatur e has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of smartfan tm . bit 1: a one indicates a high or low limit of vbat has been exceeded. bit 0: a one indicates a high or low limit of 5vsb has been exceeded. 7.8.44 smi# mask register 3 -- index 51h (bank 4) register location: 51h power on default value ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 5vsb vbat reserved reserved tar3 reserved reserved reserved bit 7-5: reserved. bit 4: a one disables the corresponding interrupt status bit for smi interrupt. bit 2-3: reserved. bit 1: a one disables the corresponding interrupt status bit for smi interrupt. bit 0: a one disables the corresponding interrupt status bit for smi interrupt.
W83627THF publication release date: august 7, 2003 - 60 - revision 0.8 7.8.45 reserved register -- index 52h ( bank 4 ) 7.8.46 beep control register 3-- index 53h ( bank 4 ) register location: 53h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 en_5vsb_bp en_vbat_bp reserved reserved reserved en_user_bp reserved reserved bit 7-6: reserved. bit 5: user define beep output function. write 1, the beep is always active. write 0, this function is inactive. (default 0) bit 4-2: reserved. bit 1: beep output control for vbat if the monitor value exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. bit 0: beep output control for 5vsb if the monitor va lue exceed the limit value. write 1, enable beep output. write 0, disable beep output, which is default value. 7.8.47 systin temperature sensor offset register -- index 54h ( bank 4 ) register location: 54h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 offset<7:0> bit 7-0: systin temperature offset value. the val ue in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value.
W83627THF publication release date: august 7, 2003 - 61 - revision 0.8 7.8.48 cputin temperature sensor offset register -- index 55h ( bank 4 ) register location: 55h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 offset<7:0> bit 7-0: cputin temperature offset value. the va lue in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 7.8.49 auxtin temperature sensor offset register -- index 56h ( bank 4 ) register location: 56h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 offset<7:0 > bit 7-0: auxtin temperature offset value. the va lue in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. 7.8.50 reserved register -- index 57h--58h ( bank4)
W83627THF publication release date: august 7, 2003 - 62 - revision 0.8 7.8.51 real time hardware status register i -- index 59h ( bank 4 ) register location: 59h power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vcore_sts vin0_sts vin1_sts avcc_sts systin_sts cputin_sts sysfanin_sts cpufanin_sts bit 7: cpufanin status. set 1, t he fan speed counter is over the lim it value. set 0, the fan speed counter is in the limit range. bit 6: sysfanin status. set 1, the fan speed counte r is over the limit value. set 0, the fan speed counter is in the limit range. bit 5: cputin temperature sensor status. set 1, the temperature exceeds th e over-temperature limit value. set 0, the temperature is in under the hysteresis value. bit 4: systin temperature sensor status. set 1, the temperature exceeds th e over-temperature limit value. set 0, the temperature is in under the hysteresis value. bit 3: avcc voltage status. set 1, the voltage of avcc is over the limit value. set 0, the voltage of avcc is in the limit range. bit 2: vin1 voltage status. set 1, the voltage of vin1 is over the limit value. set 0, the voltage of vin1 is in the limit range. bit 1: vin0 voltage status. set 1, the voltage of vin0 is over the limit value. set 0, the voltage of vin0 is in the limit range. bit 0: vcore voltage status. set 1, the voltage of vcore is over the limit value. set 0, the voltage of vcore is in the limit range.
W83627THF publication release date: august 7, 2003 - 63 - revision 0.8 7.8.52 real time hardware status register ii -- index 5ah ( bank 4 ) register location: 5ah power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 vin2_sts reserved reserved auxfanin_st s case_sts auxtin_sts tar1_sts tar2_sts bit 7: smart cpufanin warning status. set 1, the cputin temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of smartfan tm . set 0, the temperature does not reach the warning range yet. bit 6: smart sysfanin warning status. set 1, t he systin temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of smartfan tm . set 0, the temperature does not reach the warning range yet. bit 5: auxtin temperature sensor status. set 1, the temperature exceeds t he over-temperature limit value. set 0, the temperature is in under the hysteresis value. bit 4: case open status. set 1, the case open is detected and latched. set 0, the case is not latched open. bit 3: cpufanin status. set 1, t he fan speed counter is over the lim it value. set 0, the fan speed counter is in the limit range. bit 2-1: reserved. bit 0: vin2 voltage status. set 1, the voltage of vin2 is over the limit value. set 0, the voltage of vin2 is in the limit range.
W83627THF publication release date: august 7, 2003 - 64 - revision 0.8 7.8.53 real time hardware status register iii -- index 5bh ( bank 4 ) register location: 5bh power on default value 00h attribute: read only size: 8 bits 7 6 5 4 3 2 1 0 5vsb_sts vbat_sts tar3 reserved reserved reserved reserved reserved bit 7-2: reserved. bit 2: smart auxfanin warning status. set 1, th e auxtin temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of smartfan tm . set 0, the temperature does not reach the warning range yet. bit 1: vbat voltage status. set 1, the voltage of vbat is over the lim it value. set 0, the voltage of vbat is during the limit range. bit 0: 5vsb voltage status. set 1, the voltage of 5v sb is over the limit value. set 0, the voltage of 5vsb is in the limit range. 7.8.54 reserved register -- index 5ch ( bank 4 ) 7.8.55 reserved register -- index 5dh ( bank 4 ) 7.8.56 value ram 2 ? index 50h - 5ah (bank 5) address a6-a0 description 50h 5vsb reading 51h vbat reading. the reading is meanin gless if en_vbat_mnt bit(cr5d bit0) is not set. 52h reserved 53h reserved 54h 5vsb high limit 55h 5vsb low limit. 56h vbat high limit 57h vbat low limit
W83627THF publication release date: august 7, 2003 - 65 - revision 0.8 7.8.57 winbond test register -- index 50h ( bank 6 ) 7.8.58 reserved register--index00h ( bank 0 ) 7.8.59 sysfanout output value control register-- 01h ( bank 0 ) register location: 01h power on default value ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 sysfanout value reserved reserved reserved reserved bit 7-4: sysfanout voltage control. output voltage = 16 * fanout avcc if avcc= 5v , output voltage table is bit 7 bit 6 bit 5 bit 4 output voltage bit 7 bit 6 bit 5 bit 4 output voltage 0 0 0 0 0 1 0 0 0 2.50 0 0 0 1 0.31 1 0 0 1 2.81 0 0 1 0 0.63 1 0 1 0 3.13 0 0 1 1 0.97 1 0 1 1 3.44 0 1 0 0 1.25 1 1 0 0 3.75 0 1 0 1 1.56 1 1 0 1 4.06 0 1 1 0 1.88 1 1 1 0 4.38 0 1 1 1 2.19 1 1 1 1 4.69 table 5-4 . note. the accuracy of fanout voltage is +/- 0.16 v.
W83627THF publication release date: august 7, 2003 - 66 - revision 0.8 7.8.60 reserved register?index02h ( bank 0 ) 7.8.61 cpufanout output value control register-- 03h ( bank 0 ) register location: 03h power on default value ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 cpufanout value reserved reserved reserved reserved bit 7-4: cpufanout voltage control. output voltage = 16 * fanout avcc note: see the table 5-4 7.8.62 fan configuration register i -- index 04h ( bank 0 ) register location: 04h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved reserved sysfan_mod e sysfan_mod e cpufan_mod e cpufan_mod e reserved reserved bit7-6: reserved bit5-4: cpufanout mode control. set 00, cpufanout is as manual mode. (default).
W83627THF publication release date: august 7, 2003 - 67 - revision 0.8 set 01, cpufanout is as thermal cruise mode. set 10, cpufanout is as fan speed cruise mode. set 11, reserved and no function. bit3-2: sysfanout mode control. set 00, sysfanout is as manual mode. (default). set 01, sysfanout is as thermal cruise mode. set 10, sysfanout is as fan speed cruise mode. set 11, reserved and no function. bit 1-0:reserved. 7.8.63 systin target temperature register/ sysfanin target speed register -- index 05h ( bank 0 ) register location: 05h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 target temperature / target speed (1).when at thermal cruise mode: bit7: reserved. bit6-0: systin target temperature. (2).when at fan speed cruise mode: bit7-0: sysfanin target speed.
W83627THF publication release date: august 7, 2003 - 68 - revision 0.8 7.8.64 cputin target temperature regist er/ cpufanin target speed register -- index 06h ( bank 0 ) register location: 06h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 target temperature / target speed (1).when at thermal cruise mode: bit7: reserved. bit6-0: cputin target temperature. (2).when at fan speed cruise mode: bit7-0: cpufanin target speed. 7.8.65 tolerance of target temperature or target speed register -- index 07h ( bank 0 ) register location: 07h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 systin target temperature tolerance / sysfanin target speed tolerance cputin target temperature toleranc e / cpufanin target speed tolerance (1).when at thermal cruise mode: bit7-4: tolerance of cputin target temperature. bit3-0: tolerance of systin target temperature. (2).when at fan speed cruise mode: bit7-4: tolerance of cpufanin target speed. bit3-0: tolerance of sysfanin target speed.
W83627THF publication release date: august 7, 2003 - 69 - revision 0.8 7.8.66 sysfanout stop value register -- index 08h ( bank 0 ) register location: 08h power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 sysfanout stop value reserved reserved reserved reserved when at thermal cruise mode, sysfanout voltage will decrease to this register value. this register should be written a non-zero minimum output value. 7.8.67 cpufanout stop value register -- 09h ( bank 0 ) register location: 09h power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 cpufanout stop valu e reserved reserved reserved reserved when at thermal cruise mode, cpufanout voltag e will decrease to this register value. this register should be written a non-zero minimum output value. 7.8.68 sysfanout start-up value register -- index 0ah ( bank 0 ) register location: 0ah power on default value 01h attribute: read/write size: 8 bits
W83627THF publication release date: august 7, 2003 - 70 - revision 0.8 7 6 5 4 3 2 1 0 sysfanout start-up value reserved reserved reserved reserved when at thermal cruise mode, sysfanout voltage will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.8.69 cpufanout start-up value register -- index 0bh ( bank 0 ) register location: 0bh power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 cpufanout start-up valu e reserved reserved reserved reserved when at thermal cruise mode, cpufanout voltage will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.8.70 sysfanout stop time register -- index 0ch ( bank 0 ) register location: 0ch power on default value 3ch attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 sysfanout stop tim e when at thermal cruise mode, this register det ermines the time of which sysfanout voltage is from stop value to 0. the unit of this register is 0.1 second. the default time is 6 seconds.
W83627THF publication release date: august 7, 2003 - 71 - revision 0.8 7.8.71 cpufanout stop time register -- index 0dh ( bank 0 ) register location: 0dh power on default value 3ch attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 cpufanout stop tim e when at thermal cruise mode, this register determines the time of which cpufanout voltage is from stop value to 0. the unit of this register is 0.1 second. the default time is 6 seconds. 7.8.72 fan output step down time register -- index 0eh ( bank 0 ) register location: 0eh power on default value 0ah attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 fanout value step down time this register determines the speed of fanout decreasing the voltage in smart fan control mode. the unit is 1.6 second.
W83627THF publication release date: august 7, 2003 - 72 - revision 0.8 7.8.73 fan output step up time register -- index 0fh ( bank 0 ) register location: 0fh power on default value 0ah attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 fanout value step up time this register determines the speed of fanout in creasing the voltage in smart fan control mode. the unit is 1.6 second 7.8.74 reserved register?index10h ( bank 0 ) 7.8.75 auxfanout output value control register-- 11h ( bank 0 ) register location: 11h power on default value ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 auxfanout value reserved reserved reserved reserved bit 7-4: auxfanout voltage control. output voltage = 16 * fanout avcc note: see the table 5-4
W83627THF publication release date: august 7, 2003 - 73 - revision 0.8 7.8.76 fan configuration register ii -- index 12h ( bank 0 ) register location: 12h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 reserved auxfanout_mode auxfanout_mode auxfanout_min_volt cpufanout_min_volt sysfanout_min_volt reserved reserved bit7-6: reserved bit 5: set 1, sysfanout voltage will decrease to and keep the value set in index 08h when temperature goes below target r ange. this is to maintain the fan speed in a minimum value. set 0, sysfanout duty cycle will decrease to 0 when temperature goes below target range. bit 4: set 1, cpufanout duty cycle will decrease to and keep the value set in index 09h when temperature goes below target r ange. this is to maintain the fan speed in a minimum value. set 0, cpufanout duty cycle will decrease to 0 when temperature goes below target range. bit 3: set 1, auxfanout duty cycle will decrease to and keep the value set in index 15h when temperature goes below target r ange. this is to maintain the fan speed in a minimum value. set 0, auxfanout duty cycle will decrease to 0 when temperature goes below target range. bit2-1: auxfanout mode control. set 00, auxfanout is as manual mode. (default). set 01, auxfanout is as thermal cruise mode. set 10, auxfanout is as fan speed cruise mode. set 11, reserved and no function. bit 0:reserved.
W83627THF publication release date: august 7, 2003 - 74 - revision 0.8 7.8.77 auxtin target temperature regist er/ auxfanin target speed register -- index 13h ( bank 0 ) register location: 13h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 target temperature / target speed (1).when at thermal cruise mode: bit7: reserved. bit6-0: auxtin target temperature. (2).when at fan speed cruise mode: bit7-0: auxfanin target speed. 7.8.78 tolerance of target temperature or target speed register -- index 14h ( bank 0 ) register location: 14h power on default value 00h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 auxtin target temperature tolerance / auxfanin target speed tolerance reserved (1).when at thermal cruise mode: bit3-0: tolerance of auxt in target temperature. (2).when at fan speed cruise mode: bit3-0: tolerance of au xfanin target speed.
W83627THF publication release date: august 7, 2003 - 75 - revision 0.8 7.8.79 auxfanout stop value register -- index 15h ( bank 0 ) register location: 15h power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 auxfanout stop value reserved reserved reserved reserved when at thermal cruise mode, auxfanout value will decrease to register value. this register should be written a non-zero minimum output value. 7.8.80 auxfanout start-up value register -- index 16h ( bank 0 ) register location: 16h power on default value 01h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 auxfanout start-up value reserved reserved reserved reserved when at thermal cruise mode, auxfanout value w ill increase from 0 to this register value to provide a minimum voltage to turn on the fan.
W83627THF publication release date: august 7, 2003 - 76 - revision 0.8 7.8.81 auxfanout stop time register -- index 17h ( bank 0 ) register location: 17h power on default value 3ch attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 auxfanout stop tim e when at thermal cruise mode, this register det ermines the time of which auxfanout voltage is from stop value to 0. the unit of this register is 0.1 second. the default time is 6 seconds. 7.8.82 vrm & ovt configuration register -- index 18h ( bank 0 ) register location: 18h power on default value 43h attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 vcore_ad_se l reserved reserved reserved ovt1_mode reserved dis_ovt1 reserved bit 7: reserved. bit 6: set to 1, disable temperature sensor systin over-temperature (ovt#) output. set to 0, enable the systin ovt# output. bit 5: reserved. bit 4: systin ovt# mode select. this bit default is set to 0, which is compared mode. when set to 1, interrupt mode will be selected. bit 3-1: reserved. bit 0: cpuvcore pin voltage detection method selecti on. set to 1, vrm9 formula is selected. set to 0, vrm8 formula is selected. this bit default value is 1.
W83627THF publication release date: august 7, 2003 - 77 - revision 0.8 7.8.83 reserved -- index 19h ( bank 0 ) 7.8.84 user defined register -- index 1a- 1bh ( bank 0 ) register location: 1a-1bh power on default value ffh attribute: read/write size: 8 bits 7 6 5 4 3 2 1 0 user-defined user-defined user-defined user-defined user-defined user-defined user-defined user-defined bit 7-0: user can write any va lue into these bits and read. 7.8.85 reserved register-- index 1ch-1fh ( bank 0 )
W83627THF publication release date: august 7, 2003 - 78 - revision 0.8 8. plug and play configuration the W83627THF uses compatible pnp protocol to access configuration registers for setting up different types of configurations. in w83627t hf, there are eleven logical devices (from logical device 0 to logical device b with the exception of logical device 4 for back ward compatibility) which correspond to eleven individual functions: fdc (log ical device 0), prt (logical device 1), uart1 (logical device 2), uart2 (logical device 3), kbc (logical device 5), gpio, 5 (logical device 7), gpio2 (logical device 8), gpio3,4 (logical device 9), acpi ((logical device a), and hardware monitor (logical device b). each logical device has its own configur ation registers (above cr30). host can access those registers by writing an appropr iate logical device number into logical device select register at cr7. 8.1 compatible pnp 8.1.1 extended function registers in compatible pnp, there are two ways to enter ex tended function and read or write the configuration registers. hefras (cr26 bit 6) can be used to se lect one out of these two methods of entering the extended function mode as follows: hefras address and value 0 write 87h to the location 2eh twice 1 write 87h to the location 4eh twice after power-on reset, the value on rtsa# (pin 43) is latched by hefras of cr26. in compatible pnp, a specific value (87h) must be written twice to the extended functions enable register (i/o port address 2eh or 4eh). secondly, an index value (02h, 07h-ffh) must be written to the extended functions index register (i/o port address 2eh or 4eh same as extended functions enable register) to identify which configuration register is to be accessed. the designer can then access the desired configuration register through the extended functi ons data register (i/o port address 2fh or 4fh). after programming of the configurati on register is finished, an additional value (aah) should be written to efers to exit the extended function mode to prevent unintentional access to those configuration
W83627THF publication release date: august 7, 2003 - 79 - revision 0.8 registers. the designer can also set bit 5 of cr 26 (lockreg) to high to protect the configuration registers against accidental accesses. the configuration registers can be reset to their defaul t or hardware settings only by a cold reset (pin mr = 1). a warm reset will not affect the configuration registers. 8.1.2 extended functions enable registers (efers) after a power-on reset, the W83627THF enters the default operating mode. before the W83627THF enters the extended function mode, a specific value must be programmed into the extended function enable register (efer) so that the extended function register can be accessed. the extended function enable registers are writ e-only registers. on a pc/at system, their port addresses are 2eh or 4eh (as described in previous section). 8.1.3 extended function index register s (efirs), extended function data registers(efdrs) after the extended function mode is entered, t he extended function index register (efir) must be loaded with an index value (02h, 07h-feh) to access configuration register 0 (cr0), configuration register 7 (cr07) to configurat ion register fe (crfe), and so forth through the extended function data register (efdr). the efirs are write-only r egisters with port address 2eh or 4eh (as described in section 12.2.1) on pc/at systems, the efdrs are read/write registers with port address 2fh or 4fh (as described in section 9. 2.1) on pc/at systems. 8.2 configuration sequence to program W83627THF configuration registers, the following configuration sequence must be followed: (1). enter the extended function mode (2). configure the c onfiguration registers (3). exit the extended function mode 8.2.1 enter the extended function mode to place the chip into the extended function mode, tw o successive writes of 0x87 must be applied to extended function enable registers( efers, i.e. 2eh or 4eh).
W83627THF publication release date: august 7, 2003 - 80 - revision 0.8 8.2.2 configuration the configuration registers the chip selects the logical device and activates the desired logical devices through extended function index register(efir) and extended function data register(efdr). efir is located at the same address as efer, and efdr is located at address (efir+1). first, write the logical device number (i.e.,0x07) to the efir and then write the number of the desired logical device to the efdr. if accessing the chip(global ) control registers, this step is not required. secondly, write the address of the de sired configuration register within the logical device to the efir and then write (or read) the desired c onfiguration register through efdr. 8.2.3 exit the extended function mode to exit the extended function mode, one write of 0xaa to efer is required. once the chip exits the extended function mode, it is in the normal running m ode and is ready to enter the configuration mode. 8.2.4 software programming example the following example is written in intel 8086 assemb ly language. it assumes that the efer is located at 2eh, so efir is located at 2eh and efdr is lo cated at 2fh. if hefras (cr26 bit 6) is set, 4eh can be directly replaced by 4eh and 2fh replaced by 4fh. ;----------------------------------------------------------------------------------- ; enter the extended function mode, interruptible double-write | ;----------------------------------------------------------------------------------- mov dx,2eh mov al,87h out dx,al out dx,al ;----------------------------------------------------------------------------- ; configuration logical device 1, configuration register crf0 | ;----------------------------------------------------------------------------- mov dx,2eh mov al,07h out dx,al ; point to logical device number reg. mov dx,2fh mov al,01h out dx,al ; select logical device 1 ; mov dx,2eh mov al,f0h out dx,al ; select crf0 mov dx,2fh mov al,3ch out dx,al ; update crf0 with value 3ch ;------------------------------------------ ; exit extended function mode | ;------------------------------------------ mov dx,2eh mov al,aah out dx,al
W83627THF publication release date: august 7, 2003 - 81 - revision 0.8 9. configuration register 9.1 chip (global) control register cr02 (default 0x00) bit 7 - 1 : reserved. bit 0 : swrst --> soft reset. cr07 bit 7 - 0 : ldnb7 - ldnb0 --> logical device number bit 7 - 0 cr20 bit 7 - 0 : devidb7 - debidb0 --> device id bit 7 - bit 0 = 0x82(read only). cr21 bit 7 - 0 : devrevb7 - debrevb0 --> device rev bit 7 - bit 0 = 0x83 (read only, 1 is version no.). cr22 (default 0xff) bit 7 : r eserved . bit 6 : hmpwd = 0 power down = 1 no power down bit 5 : urbpwd = 0 power down = 1 no power down bit 4 : urapwd = 0 power down = 1 no power down bit 3 : prtpwd = 0 power down = 1 no power down bit 2 - 1 : reserved. bit 0 : fdcpwd = 0 power down = 1 no power down
W83627THF publication release date: august 7, 2003 - 82 - revision 0.8 cr23 (default 0x00) bit 7 - 1 : r eserved . bit 0 : ipd (immediate power do wn). when set to 1, it will put the whole chip into power down mode immediately. cr24 (default 0s110s1sb) bit 7 : reserved bit 6 : clksel = 0 the clock input on pin 18 should be 24 mhz. = 1 the clock input on pin 18 should be 48 mhz. the corresponding power-on setting pin is soutb (pin 83). bit 5 - 3 : reserved bit 2 : enkbc = 0 kbc is disabled after hardware reset. = 1 kbc is enabled after hardware reset. this bit is read only, and set/reset by power -on setting pin. the corresponding power- on setting pin is souta (pin 54). bit 1 : reserved. must be 1. bit 0 : pnpcsv = 0 the compatible pnp address select registers have default values. = 1 the compatible pnp address se lect registers have no default value. when trying to make a change to this bit, new value of pnpcvs must be complementary to the old one to make an effective change. for example, the user must set pnpcsv to 0 first and then reset it to 1 to reset these pnp registers if t he present value of pnpcsv is 1. the corresponding power-on setting pin is ndtra (pin 52). cr25 (default 0x00) bit 7 - 6 : reserved bit 5 : urbtri bit 4 : uratri bit 3 : prttri bit 2 - 1 : reserved bit 0 : fdctri.
W83627THF publication release date: august 7, 2003 - 83 - revision 0.8 cr26 (default 0s000000b) bit 7 : sel4fdd = 0 select two fdd mode. = 1 select four fdd mode. bit 6 : hefras these two bits define how to enable confi guration mode. the corresponding power-on setting pin is nrtsa (pin 51). hefras address and value = 0 write 87h to the location 2eh twice. = 1 write 87h to the location 4eh twice. bit 5 : lockreg = 0 enable r/w confi guration registers = 1 disable r/w confi guration registers. bit 4 : reserved bit 3 : dsfdlgrq = 0 enable fdc legacy mode on irq and drq selection, then do register bit 3 is effective on selecting irq = 1 disable fdc legacy mode on irq and drq se lection, then do register bit 3 is not effective on selecting irq bit 2 : dsprlgrq = 0 enable prt legacy mode on irq and drq se lection, then dcr bit 4 is effective on selecting irq = 1 disable prt legacy mode on irq and drq se lection, then dcr bit 4 is not effective on electing irq. bit 1 : dsualgrq = 0 enable uart a legacy mode irq selecting, then mcr bit 3 is effective on selecting irq. = 1 disable uart a legacy mode irq select ing, then mcr bit 3 is not effective on selecting irq. bit 0 : dsublgrq = 0 enable uart b legacy mode irq selecting, then mcr bit 3 is effective on selecting irq = 1 disable uart b legacy mode irq select ing, then mcr bit 3 is not effective on selecting irq
W83627THF publication release date: august 7, 2003 - 84 - revision 0.8 cr28 (default 0x00) bit 7 - 3 : reserved. bit 2 - 0 : prtmods2 - prtmods0 = 0xx parallel port mode = 100 reserved = 101 external fdc mode = 110 reserved = 111 external two fdc mode cr29 (gpio group 1 multiplexed pin selection register 1. vcc powered. default 0x00) bit 7, 6 port select (select pin 121 ~ 128 as game port, general purpose i/o port 1 decoding feature. = 00 game port. = 01 general purpose i/o port 1. = 10 reserved. = 11 reserved. bit 5 pin105s. = 0 gp55 = 1 winbond test mode bit 4 xur_sel. it selects the function of pin 78 ~ 85. = 0 pin 78 ~ 85 serve as urb function. = 1 winbond test mode bit 3 - 2 reserved. bit 1, 0 pin120s1, pin120s0 = 00 mso (midi serial output). = 01 gp20 = 10 reserved = 11 irqin0 (select irq resource thr ough crf4 bit 7-4 of logical device 8). cr2a (gpio2 multiplexed pin selection register. vcc powered. default 0x00) bit 7, 6 pin119s1, pin119s0. = 00 msi. = 01 gp21. = 10 winbond test mode = 11 reserved.
W83627THF publication release date: august 7, 2003 - 85 - revision 0.8 bit 5 pin118s. = 0 gp22. = 1 winbond test mode bit 4 pin96s. = 0 gp23. = 1 winbond test mode . bit 3 pin95s. = 0 gp24. = 1 winbond test mode bit 2 pin94s. = 0 gp25. = 1 winbond test mode. bit 1 pin93s. = 0 gp26. = 1 winbond test mode bit 0 pin2s = 0 smi#. = 1 irqin1 (select irq resource th rough crf4 bit 7-4 of logical device8). cr2b (gpio3 multiplexed pin selection regi ster 3. vsb powered. default 0x00ssssssb) bit 7 reserved bit 6 pin86s. = 0 gp35. = 1 winbond test mode bit 5, 4 pin88s1, pin88s0. = 00 irrx. = 01 gp34. = 10 winbond test mode = 11 reserved bit 3, 2 pin89s1, pin89s0. = 00 gp33. = 01 wdto. = 10 reserved = 11 reserved
W83627THF publication release date: august 7, 2003 - 86 - revision 0.8 bit 1, 0 pin90s1, pin90s0. = 00 gp32. = 01 pled. = 10 reserved. = 11 reserved. cr2c (gpio3 multiplexed pin selection regi ster 2. vsb powered. default 0xssssss00b) bit 7, 6 : pin91s1, pin91s0. = 00 gp31. = 01 reserved. = 10 reserved. = 11 reserved bit 5, 4 : pin92s1, pin92s0. = 00 gp30. = 01 reserved. = 10 reserved. = 11 reserved bit 3, 2 : pin64s1, pin64s0. = 00 susled. = 01 gp37. = 10 reserved. = 11 reserved. bit 1 : pin87s. = 0 irtx. = 1 winbond test mode. bit 0 : reserved. cr2d (gpio4 multiplexed pin selection register. vsb powered. default 0x00s00000b) bit 7 : pin67s. = 0 psout#. = 1 gp47. bit 6 : pin68s. = 0 psin. = 1 gp46.
W83627THF publication release date: august 7, 2003 - 87 - revision 0.8 bit 5 : pin69s. = 0 gp45. = 1 reserved. bit 4 : pin70s. = 0 rsmrst#. = 1 gp44. bit 3 : pin71s. = 0 pwrok. = 1 gp43. bit 2 : pin72s. = 0 pwrctl#. = 1 gp42. bit 1 : pin73s. = 0 slp_sx#. = 1 gp41. bit 0 : pin75s. = 0 gp40 = 1 winbond test mode cr2e (default 0x00) test modes: reserved for winbond. cr2f (default 0x00) test modes: reserved for winbond. 9.1.1 logical device 0 (fdc) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0xf0 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select fdc i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x06 if pnpcsv = 0 during por, default 0x00 otherwise)
W83627THF publication release date: august 7, 2003 - 88 - revision 0.8 bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resource for fdc. cr74 (default 0x02 if pnpcsv = 0 during por, default 0x04 otherwise) bit 7 - 3 : reserved. bit 2 - 0 : these bits select drq resource for fdc. = 0x00 dma0 = 0x01 dma1 = 0x02 dma2 = 0x03 dma3 = 0x04 - 0x07 no dma active crf0 (default 0x0e) fdd mode register bit 7 : fipurdwn this bit controls the internal pull-up resistor s of the fdc input pins rdata, index, trak0, dskchg, and wp. = 0 the internal pull-up resistors of fdc are turned on. (default) = 1 the internal pull-up resistors of fdc are turned off. bit 6 : intvertz this bit determines the polarity of all fdd interface signals. = 0 fdd interface signals are active low. = 1 fdd interface signals are active high. bit 5 : drv2en (ps2 mode only) when this bit is a logic 0, indicates a second drive is installed and is reflected in status register a. bit 4 : swap drive 0, 1 mode = 0 no swap (default) = 1 drive and motor select 0 and 1 are swapped. bit 3 - 2 :interface mode = 11 at mode (default) = 10 (reserved) = 01 ps/2 = 00 model 30
W83627THF publication release date: august 7, 2003 - 89 - revision 0.8 bit 1 : fdc dma mode = 0 burst mode is enabled = 1 non-burst mode (default) bit 0 : floppy mode = 0 normal floppy mode (default) = 1 enhanced 3-mode fdd crf1 (default 0x00) bit 7 - 6 : boot floppy = 00 fdd a = 01 fdd b = 10 fdd c = 11 fdd d bit 5, 4 : media id1, media id0. these bits wi ll be reflected on fdc's ta pe drive register bit 7, 6. bit 3 - 2 : density select = 00 normal (default) = 01 normal = 10 1 (forced to logic 1) = 11 0 (forced to logic 0) bit 1 : disfddwr = 0 enable fdd write. = 1 disable fdd write(forces pins we, wd stay high). bit 0 : swwp = 0 normal, use wp to determine whether the fdd is write protected or not. = 1 fdd is always write-protected. crf2 (default 0xff) bit 7 - 6 : fdd d drive type bit 5 - 4 : fdd c drive type bit 3 - 2 : fdd b drive type bit 1 - 0 : fdd a drive type
W83627THF publication release date: august 7, 2003 - 90 - revision 0.8 crf4 (default 0x00) fdd0 selection: bit 7 : reserved. bit 6 : pre-comp. disable. = 1 disable fdc pre-compensation. = 0 enable fdc pre-compensation. bit 5 : reserved. bit 4 - 3 : drts1, drts0: data rate table select (refer to table a). = 00 select regular drives and 2.88 format = 01 3-mode drive = 10 2 meg tape = 11 reserved bit 2 : reserved. bit 1:0 : dtype0, dtype1: drive ty pe select (refer to table b). crf5 (default 0x00) fdd1 selection: same as fdd0 of crf4. table a drive rate table select data rate selected data rate selden drts1 drts0 drate1 drate0 mfm fm 1 1 1meg --- 1 0 0 0 0 500k 250k 1 0 1 300k 150k 0 1 0 250k 125k 0 1 1 1meg --- 1 0 1 0 0 500k 250k 1 0 1 500k 250k 0 1 0 250k 125k 0 1 1 1meg --- 1 1 0 0 0 500k 250k 1 0 1 2meg --- 0 1 0 250k 125k 0
W83627THF publication release date: august 7, 2003 - 91 - revision 0.8 table b dtype0 dtype1 drvden0(pin 2) drvden1(pin 3) drive type 0 0 selden drate0 4/2/1 mb 3.5?? 2/1 mb 5.25? 2/1.6/1 mb 3.5? (3-mode) 0 1 drate1 drate0 1 0 selden drate0 1 1 drate0 drate1 9.1.2 logical device 1 (parallel port) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0x78 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select parallel port i/o base address. [0x100:0xffc] on 4 byte boundar y (epp not supported) or [0x100:0xff8] on 8 byte boundary (all modes su pported, epp is only ava ilable when the base address is on 8 byte boundary). cr70 (default 0x07 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for parallel port. cr74 (default 0x04) bit 7 - 3 : reserved. bit 2 - 0 : these bits select drq resource for parallel port. 0x00 = dma0 0x01 = dma1 0x02 = dma2 0x03 = dma3 0x04 - 0x07 = no dma active
W83627THF publication release date: august 7, 2003 - 92 - revision 0.8 crf0 (default 0x3f) bit 7 : reserved. bit 6 - 3 : ecp fifo threshold. bit 2 - 0 : parallel port mode (cr28 prtmods2 = 0) = 100 printer mode (default) = 000 standard and bi-direction (spp) mode = 001 epp - 1.9 and spp mode = 101 epp - 1.7 and spp mode = 010 ecp mode = 011 ecp and epp - 1.9 mode = 111 ecp and epp - 1.7 mode. 9.1.3 logical device 2 (uart a) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x03, 0xf8 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select serial port 1 i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x04 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resource for serial port 1. crf0 (default 0x00) bit 7 - 2 : reserved. bit 1 - 0 : suaclkb1, suaclkb0 = 00 uart a clock source is 1.8462 mhz (24mhz/13) = 01 uart a clock source is 2 mhz (24mhz/12) = 10 uart a clock source is 24 mhz (24mhz/1) = 11 uart a clock source is 14.769 mhz (24mhz/1.625)
W83627THF publication release date: august 7, 2003 - 93 - revision 0.8 9.1.4 logical device 3 (uart b) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x02, 0xf8 if pnpcsv = 0 during por, default 0x00, 0x00 otherwise) these two registers select serial port 2 i/o base address [0x100:0xff8] on 8 byte boundary. cr70 (default 0x03 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for serial port 2. crf0 (default 0x00) bit 7 - 4 : reserved. bit 3 : rxw4c = 0 no reception delay when sir is changed from tx mode to rx mode. = 1 reception delays 4 characters - time ( 40 bit-time) when sir is changed from tx mode to rx mode. bit 2 : txw4c = 0 no transmission delay when sir is changed from rx mode to tx mode. = 1transmission delays 4 characters-time (40 bit-time) when sir is changed from rx mode to tx mode. bit 1 - 0 : subclkb1, subclkb0 = 00 uart b clock source is 1.8462 mhz (24 mhz/ 13) = 01 uart b clock source is 2 mhz (24 mhz/ 12) = 10 uart b clock source is 24 mhz (24 mhz/ 1) = 11 uart b clock source is 14.769 mhz (24 mhz/ 1.625)
W83627THF publication release date: august 7, 2003 - 94 - revision 0.8 crf1 (default 0x00) bit 7 : reserved. bit 6 : irlocsel. ir i/o pins' location select. = 0 through sinb/soutb. = 1 through irrx/irtx. bit 5 : irmode2. ir function mode selection bit 2. bit 4 : irmode1. ir function mode selection bit 1. bit 3 : irmode0. ir function mode selection bit 0. ir mode ir function irtx irrx 00x disable tri-state high 010* irda active pulse 1.6 s demodulation into sinb/irrx 011* irda active pulse 3/16 bit time demodulation into sinb/irrx 100 ask-ir inverting irtx/soutb pin routed to sinb/irrx 101 ask-ir inverting irtx/soutb & 500 khz clock routed to sinb/irrx 110 ask-ir inverting irtx/soutb demodulation into sinb/irrx 111* ask-ir inverting irtx/soutb & 500 khz clock demodulation into sinb/irrx note: the notation is normal mode in the ir function. bit 2 : hduplx. ir half/full duplex function select. = 0 the ir function is full duplex. = 1 the ir function is half duplex. bit 1 : tx2inv = 0 the soutb pin of uart b function or ir tx pin of ir function in normal condition. = 1 inverse the soutb pin of uart b function or irtx pin of ir function. bit 0 : rx2inv. = 0 the sinb pin of uart b function or i rrx pin of ir function in normal condition. = 1 inverse the sinb pin of uart b function or irrx pin of ir function
W83627THF publication release date: august 7, 2003 - 95 - revision 0.8 9.1.5 logical device 5 (kbc) cr30 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x60 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the first kbc i/o base address [0x100:0xfff] on 1 byte boundary. cr62, cr 63 (default 0x00, 0x64 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the second kbc i/o base address [0x100:0xfff] on 1 byte boundary. cr70 (default 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for kint (keyboard). cr72 (default 0x0c if pnpcsv = 0 dur ing por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for mint (ps2 mouse) crf0 (default 0x80) bit 7 - 6 : kbc clock rate selection = 00 select 6mhz as kbc clock input. = 01 select 8mhz as kbc clock input. = 10 select 12mhz as kbc clock input. = 11 select 16mhz as kbc clock input. bit 5 - 3 : reserved. bit 2 = 0 port 92 disable. = 1 port 92 enable. bit 1 = 0 gate20 software control. = 1 gate20 hardware speed up. bit 0 = 0 kbrst software control. = 1 kbrst hardware speed up.
W83627THF publication release date: august 7, 2003 - 96 - revision 0.8 9.1.6 logical device 7 (game port and mi di port and gpio port 1 and 5) cr30 (default 0x00) bit 7 - 4 : reserved. bit 3 = 1 enable gpio port 5. = 0 disable gpio port 5. bit 2 = 1 enable midi port. = 0 midi port is disabled if bit 0 of this register is also 0. bit 1 = 1 enable game port. = 0 game port is disabled if bit 0 of this register is also 0. bit 0 = 1 enable gpio port 1, game port and midi port. = 0 disable gpio port 1. game port and midi port are enabled/disabled by bit 1 and 2 of this register respectively. cr60, cr 61 (default 0x02, 0x01 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the game port base address [0x100:0xfff] on 1 byte boundary. cr62, cr 63 (default 0x03, 0x30 if pnpcsv = 0 during por, default 0x00 otherwise) these two registers select the midi port base address [0x100:0xfff] on 2 byte boundary. cr70 (default 0x09 if pnpcsv = 0 during por, default 0x00 otherwise) bit 7 - 4 : reserved. bit [3:0] : these bits select irq resource for midi port . crf0 (gp1[7:0] i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp1[7:0] data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, t hen its respective bit can only be read. crf2 (gp1[7:0] inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register.
W83627THF publication release date: august 7, 2003 - 97 - revision 0.8 crf3 (gp5[5:0] i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf4 (gp5[5:0] data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, t hen its respective bit can only be read. crf5 (gp5[5:0] inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. 9.1.7 logical device 8 (gpio port 2 this power of the port is vcc source) cr30 (gp2[7:0] default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activate gpio2. = 0 gpio2 is inactive. crf0 (gp2[7:0] i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp2[7:0] data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, t hen its respective bit can only be read. crf2 (gp2[7:0] inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. crf3 (default 0x00) bit 7 - 4 : these bits select irq resource for irqin1. bit 3 - 0 : these bits select irq resource for irqin0.
W83627THF publication release date: august 7, 2003 - 98 - revision 0.8 crf4 (reserved) crf5 (pled mode register. default 0x00) bit 7-6 : select pled mode = 00 power led pin is tri-stated. = 01 power led pin is driven low. = 10 power led pin is a 1hz toggle pulse with 50 duty cycle = 11 power led pin is a 1/4hz t oggle pulse with 50 duty cycle. bit 5-4 : reserved bit 3 : select wdto counter type. = 0 by second = 1 by minute bit 2 : enable the rising edge of keyboard reset (p20) to force time-out event. = 0 disable = 1 enable bit 1-0 : reserved crf6 (default 0x00) watch dog timer time-out value. writing a non-zer o value to this register causes the counter to load the value to watch dog counter and start count ing down. if the bit 7 and bit 6 are set, any mouse interrupt or keyboard interrupt event will al so cause the reload of pr eviously-loaded non-zero value to watch dog counter and start counting down. reading this register returns current value in watch dog counter instead of watch dog timer time-out value. bit 7 - 0 = 0x00 time-out disable = 0x01 time-out occurs after 1 second/minute = 0x02 time-out occurs after 2 second/minutes = 0x03 time-out occurs after 3 second/minutes ................................................ = 0xff time-out occurs after 255 second/minutes
W83627THF publication release date: august 7, 2003 - 99 - revision 0.8 crf7 (default 0x00) bit 7 : mouse interrupt reset enable or disable = 1 watch dog timer is reset upon a mouse interrupt = 0 watch dog timer is not affected by mouse interrupt bit 6 : keyboard interrupt reset enable or disable = 1 watch dog timer is reset upon a keyboard interrupt = 0 watch dog timer is not affected by keyboard interrupt bit 5 : force watch dog timer time-out, write only* = 1 force watch dog timer time-out ev ent; this bit is self-clearing. bit 4 : watch dog timer status, r/w = 1 watch dog timer time-out occurred = 0 watch dog timer counting bit 3 -0 : these bits select irq resour ce for watch dog. setting of 2 selects smi. 9.1.8 logical device 9 (gpio port 3, 4. these two ports are powered by vsb) cr30 (default 0x00) bit 7 - 2 : reserved bit 1 = 1 activate gpio4. = 0 gpio4 is inactive. bit 0 = 1 activate gpio3. = 0 gpio3 is inactive. crf0 (gp3[7:0] i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf1 (gp3[7:0] data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, t hen its respective bit can only be read. crf2 (gp3[7:0] inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register.
W83627THF publication release date: august 7, 2003 - 100 - revision 0.8 crf3 (susled mode register. default 0x00) bit 7-6 : select suspend led mode = 00 suspend led pin is drove low. = 01 suspend led pin is tri-stated. = 10 suspend led pin is a 1hz toggle pulse with 50 duty cycle. = 11 suspend led pin is a 1/4hz t oggle pulse with 50 duty cycle. this mode selection bit 7-6 keep its settings until vsb power loss. bit 5 - 0 : reserved. crf4 (gp4[7:0] i/o selection register. default 0xff) when set to a '1', respective gpio port is programmed as an input port. when set to a '0', respective gpio port is programmed as an output port. crf5 (gp4[7:0] data register. default 0x00) if a port is programmed to be an output port, then its respective bit can be read/written. if a port is programmed to be an input port, t hen its respective bit can only be read. crf6 (gp4[7:0] inversion register. default 0x00) when set to a '1', the incoming/outgoing port value is inverted. when set to a '0', the incoming/outgoing port value is the same as in data register. 9.2 logical device a (acpi) (the cr30, 70, f0~f9 are vcc power sour ce; cr e0~e7 are vrtc power source) cr30 (default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr70 (default 0x00) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq resources for pme .
W83627THF publication release date: august 7, 2003 - 101 - revision 0.8 cre0 (default 0x00) bit 7 : dis-pansw_in. disable panel switch input to turn system power supply on. = 0 pansw_in is wire-anded and connected to pansw_out. = 1 pansw_in is blocked and can not affect pansw_out. bit 6 : enkbwakeup. enable keyboard to wake-up system via pansw_out. = 0 disable keyboard wake-up function. = 1 enable keyboard wake-up function. bit 5 : enmswakeup. enable mouse to wake-up system via pansw_out. = 0 disable mouse wake-up function. = 1 enable mouse wake-up function. bit 4 : msrkey. this bit combining with msxkey (bit 1 of cre0 of logical device a) and enmdat_up (bit 7 of cre6 of logical device a) define w hat kind of mouse wake-up event can trigger an active low pulse on psout#. their combi nation is described in the following table. enmdat_up msrkey msxkey wake up event 1 x 1 any button click or any movement 1 x 0 one click of left/right button 0 0 1 one click of left button 0 1 1 one click of right button 0 0 0 two times click of left button 0 1 0 two times click of right button bit 3 reserved bit 2 : kb/ms swap. enable keyboard/mouse port-swap. = 0 keyboard/mouse ports are not swapped. = 1 keyboard/mouse ports are swapped. bit 1 : msxkey. this bit combining with msrkey (bit 4 of cre0 of logical device a) and enmdat_up (bit 7 of cre6 of logical device a) define w hat kind of mouse wake-up event can trigger an active low pulse on psout#. their combination is described in the following table. enmdat_up msrkey msxkey wake up event 1 x 1 any button click or any movement 1 x 0 one click of left/right button 0 0 1 one click of left button 0 1 1 one click of right button 0 0 0 two times click of left button 0 1 0 two times click of right button bit 0 : kbxkey. enable any character received fr om keyboard to wake-up the system = 0 only predetermined specific key co mbination can wake up the system. = 1 any character received from keyboard can wake up the system.
W83627THF publication release date: august 7, 2003 - 102 - revision 0.8 cre1 (default 0x00) keyboard wake-up index register this register is used to indicate which ke yboard wake-up shift register or predetermined key register is to be read/written via cre2. the first set of wake up key combination is in the range of 0x00 - 0x0e, the second set 0x30 ? 0x3e, and the th ird set 0x40 ? 0x4e. incoming key combination can be read through 0x10 ? 0x1e. cre2 keyboard wake-up data register this register holds the value of wake-up key regi ster indicated by cre1. this register can be read/written. cre3 (read only) keyboard/mouse wake-up status register bit 7-5 : reserved. bit 4 : pwrloss_sts: this bi t is set when power loss occurs. bit 3 reserved bit 2 : pansw_sts. the panel switch event is caused by pansw_in. this bit is cleared by reading this register. bit 1 : mouse_sts. the panel switch event is caused by mouse wake-up event. this bit is cleared by reading this register. bit 0 : keyboard_sts. the panel switch event is caused by keyboard wake-up event. this bit is cleared by reading this register. cre4 (default 0x00) bit 7 : power loss control bit 2. = 0 disable acpi resume = 1 enable acpi resume bit 6-5 : power loss control bit <1:0> = 00 system always turn off when come back from power loss state. = 01 system always turn on when come back from power loss state. = 10 system turn on/off when come back from power loss state depend on the state before power loss. = 11 reserved. bit 4 : reserved bit 3 : keyboard wake-up type select for wake-up the system from s1/s2. = 0 la.cre0.bit0 determines how system wake up from s1/s2. = 1 any key. bit 2 : enable all wake-up event set in cre0 ca n wake-up the system from s1/s2 state. this bit is cleared when wake-up event occurs. = 0 disable. = 1 enable. bit 1 - 0 : reserved. must be 00b.
W83627THF publication release date: august 7, 2003 - 103 - revision 0.8 cre5 (default 0x00) bit 7 : reserved. bit 6 - 0 : compared code length. when the compared codes are storied in the data register, these data length should be written to this register. cre6 (default 0x00) bit 7 enmdat_up. this bit combining with ms rkey (bit 4 of cre0 of logical device a) and msxkey (bit 1 of cre0 of logical device a) define what kind of mouse wake-up event can trigger an active low pulse on psout#. their combination is described in the following table. enmdat_up msrkey msxkey wake up event 1 x 1 any button click or any movement 1 x 0 one click of left/right button 0 0 1 one click of left button 0 1 1 one click of right button 0 0 0 two times click of left button 0 1 0 two times click of right button bit6 chassis status clear = 1 clear caseopen# (pin76) event. = 0 disable clear function. bit 5 - 0 reserved
W83627THF publication release date: august 7, 2003 - 104 - revision 0.8 cre7 (default 0x00) bit 7 enkd3. enable the third set of keyboa rd wake-up key combinations. its values are accessed through keyboard wake -up index register (cre1 of logical device a) and keyboard wake-up data register (cre2 of l ogical device a) at index from 40h to 4eh. = 0 disable wake-up function of the third set of key combinations. = 1 enable wake-up function of the third set of key combinations. bit 6 enkd2. enable the second set of key board wake-up key combinations. its values are accessed through keyboard wake -up index register (cre1 of logical device a) and keyboard wake-up data register (cre2 of l ogical device a) at index from 30h to 3eh. = 0 disable wake-up function of the second set of key combinations. = 1 enable wake-up function of the second set of key combinations. bit 5 enwin98key. enable win98 keyboard dedicated key to wake up system through pansw_out if keyboard wake up function is enabled. = 0 disable win98 keyboard wake up. = 1 enable win98 keyboard wake up. bit 4 en_onpsout. enable to issue a 0.5s long psout# pulse when system returns from power loss state and is supposed to be on as desc ribed in cre4 bit 6, 5 of logical device a. = 0 disable this function for intel?s chipset. = 1 enable this function for clone?s chipset. bit 3 selwdtorst: select whether watch do g timer function is reset by lreset_l signal or pwrok signal. =0 watch dog timer function is reset by lreset_l signal. =1 watch dog timer function is reset by pwrok signal. bit 2 reserved bit 1 reserved bit 0 reserved
W83627THF publication release date: august 7, 2003 - 105 - revision 0.8 crf0 (default 0x00) bit 7 : chippme. chip level auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 6 reserved bit 5 : midipme. midi port auto power management enable. = 0 disable the auto power management functions = 1 enable the auto power management functions. bit 4 : reserved. return zero when read. bit 3 : prtpme. printer port auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 2 : fdcpme. fdc auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 1 : urapme. uart a auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions. bit 0 : urbpme. uart b auto power management enable. = 0 disable the auto power management functions. = 1 enable the auto power management functions.
W83627THF publication release date: august 7, 2003 - 106 - revision 0.8 crf1 (default 0x00) bit 7 : wak_sts. this bit is set when the chip is in the sleeping state and an enabled resume event occurs. upon setting this bit, the sl eeping/working state machine will transition the system to the working state. this bit is onl y set by hardware and is cleared by writing a 1 to this bit position or by the sleeping/worki ng state machine automatically when the global standby timer expires. = 0 the chip is in the sleeping state. = 1 the chip is in the working state. bit 6 - 5 : devices' trap status. bit 4 : reserved. return zero when read. bit 3 - 0 : devices' trap status. crf3 (default 0x00) bit 7 - 0 : device's irq status. these bits indicate the irq status of the individual device respectively. the device's irq status bit is set by their source device an d is cleared by writing a 1. writing a 0 has no effect. bit 7 : reserved. bit 6 : reserved. bit 5 : mouirqsts. mouse irq status. bit 4 : kbcirqsts. kbc irq status. bit 3 : prtirqsts. printer port irq status. bit 2 : fdcirqsts. fdc irq status. bit 1 : urairqsts. uart a irq status. bit 0 : urbirqsts. uart b irq status. crf4 (default 0x00) bit 7 : reserved. return zero when read. bit 6 - 0 : these bits indicate the irq status of the individual gpio function or logical device respectively. the status bit is set by thei r source function or device and is cleared by writing a1. writing a 0 has no effect. bit 6 :reserved bit 5 : hmirqsts. hardware monitor irq status. bit 4 : wdtirqsts. watch dog timer irq status. bit 3 reserved bit 1 : irqin1sts. irqin1 status. bit 0 : irqin0sts. irqin0 status.
W83627THF publication release date: august 7, 2003 - 107 - revision 0.8 crf6 (default 0x00) bit 7 - 0 : enable bits of the smi / pme generation due to the device's irq. these bits enable the generation of an smi / pme interrupt due to any irq of the devices. smi / pme logic output = (mouirqen and mouirqsts) or (kbcirqen and kbcirqsts) or (prtirqen and prtirqsts) or (fdcirqen and fdcirqsts) or (urairqen and urairqsts) or (urbirqen and urbirqsts) or (hmirqen and hmirqsts) or (wdtirqen and wdtirqsts) or (irqin3en and irqin3sts) or (irqin2en and irqin2sts) or (irqin1en and irqin1sts) or (irqin0en and irqin0sts) bit 7 reserved. bit 6 reserved bit 5 : mouirqen. = 0 disable the generation of an smi / pme interrupt due to mouse's irq. = 1 enable the generation of an smi / pme interrupt due to mouse's irq. bit 4 : kbcirqen. = 0 disable the generation of an smi / pme interrupt due to kbc's irq. = 1 enable the generation of an smi / pme interrupt due to kbc's irq. bit 3 : prtirqen. = 0 disable the generation of an smi / pme interrupt due to printer port's irq. = 1 enable the generation of an smi / pme interrupt due to printer port's irq. bit 2 : fdcirqen. = 0 disable the generation of an smi / pme interrupt due to fdc's irq. = 1 enable the generation of an smi / pme interrupt due to fdc's irq. bit 1 : urairqen. = 0 disable the generation of an smi / pme interrupt due to uart a's irq. = 1 enable the generation of an smi / pme interrupt due to uart a's irq. bit 0 : urbirqen. = 0 disable the generation of an smi / pme interrupt due to uart b's irq. = 1 enable the generation of an smi / pme interrupt due to uart b's irq.
W83627THF publication release date: august 7, 2003 - 108 - revision 0.8 crf7 (default 0x00) bit 7 : reserved. return zero when read bit 6 - 0 : enable bits of the smi / pme generation due to the gpio irq function or device's irq. bit 6 reserved bit 5 : hmirqen. = 0 disable the generation of an smi / pme interrupt due to hardware monitor's irq. = 1 enable the generation of an smi / pme interrupt due to hardware monitor's irq. bit 4 : wdtirqen. = 0 disable the generation of an smi / pme interrupt due to watch dog timer's irq. = 1 enable the generation of an smi / pme interrupt due to watch dog timer's irq. bit 3 reserved bit 2 : midiirqen. = 0 disable the generation of an smi / pme interrupt due to midi's irq. = 1 enable the generation of an smi / pme interrupt due to midi's irq. bit 1 : irqin1en. = 0 disable the generation of an smi / pme interrupt due to irqin1's irq. = 1 enable the generation of an smi / pme interrupt due to irqin1's irq. bit 0 : irqin0en. = 0 disable the generation of an smi / pme interrupt due to irqin0's irq. = 1 enable the generation of an smi / pme interrupt due to irqin0's irq. crf9 (default 0x00) bit 7 - 3 : reserved. return zero when read. bit 2 : pme_en: select the power management events to be either an pme or smi interrupt for the irq events. note that: this bi t is valid only when smipme_oe = 1. = 0 the power management events will generate an smi event = 1 the power management events will generate an pme event. bit 1 : fsleep: this bit selects the fast expiry time of individual devices. = 0 1 second. = 1 8 ms bit 0 : smipme_oe: this is the smi and pme output enable bit. = 0 neither smi nor pme will be generated. only the irq status bit is set. = 1 an smi or pme event will be generated.
W83627THF publication release date: august 7, 2003 - 109 - revision 0.8 crfe, ff (default 0x00) reserved for winbond test. 9.3 logical device b (hardware monitor) cr30 (default 0x00) bit 7 - 1 : reserved. bit 0 = 1 activates the logical device. = 0 logical device is inactive. cr60, cr 61 (default 0x00, 0x00) these two registers select hardware moni tor base address [0x 100:0xfff] on 8-byte boundary. cr70 (default 0x00) bit 7 - 4 : reserved. bit 3 - 0 : these bits select irq channel for hardware monitor.
W83627THF publication release date: august 7, 2003 - 110 - revision 0.8 10. electrical characteristics 10.1 absolute maximum ratings parameter rating unit power supply voltage (5v) -0.5 to 7.0 v input voltage -0.5 to v dd +0.5 v rtc battery voltage v bat 2.2 to 4.0 v operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions be yond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 10.2 dc characteristics (t a = 0 c to 70 c, v dd = 5v 10%, v ss = 0v) parameter sym. min. typ max. unit conditions rtc battery quiescent current i bat 2.4 ua v bat = 2.5 v acpi stand-by power supply quiescent current i bat 2.0 ma v sb = 5.0 v, all acpi pins are not connected. in cs - cmos level schmitt-triggered input pin input low threshold voltage v t- 1.3 1.5 1.7 v v dd = 5 v input high threshold voltage v t+ 3.2 3.5 3.8 v v dd = 5 v hystersis v th 1.5 2 v v dd = 5 v input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v in t - ttl level input pin input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v
W83627THF publication release date: august 7, 2003 - 111 - revision 0.8 dc characteristics, continued parameter sym. min. typ max. unit conditions in td - ttl level input pin with internal pull down resistor input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v pull down resistor r 47 k ? in ts - ttl level schmitt-triggered input pin input low threshold voltage v t- 0.8 0.9 1.0 v v dd = 5 v input high threshold voltage v t+ 1.8 1.9 2.0 v v dd = 5 v hystersis v th 0.8 1.0 v v dd = 5 v input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v in tsp3 - 3.3 v ttl level schmitt-triggered input pin input low threshold voltage v t- 0.5 0.8 1.1 v v dd = 3.3 v input high threshold voltage v t+ 1.6 2.0 2.4 v v dd = 3.3 v hystersis v th 0.5 1.2 v v dd = 3.3 v input high leakage i lih +10 a v in = 3.3 v input low leakage i lil -10 a v in = 0 v in tu - ttl level input pin with internal pull up resistor input low voltage v il 0.8 v input high voltage v ih 2.0 v input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v pull up resistor r 40 k ?
W83627THF publication release date: august 7, 2003 - 112 - revision 0.8 dc characteristics, continued parameter sym. min. typ max. unit conditions i/o 8t - ttl level bi-directional pin with source-sink capability of 8 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 8 ma output high voltage v oh 2.4 v i oh = - 8 ma input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v i/o 12t - ttl level bi-directional pin with source-sink capability of 12 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v i/o 12tp3 - 3.3 v ttl level bi-directional pin with source-sink capability of 12 ma input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma input high leakage i lih +10 a v in = 3.3 v input low leakage i lil -10 a v in = 0 v i/od 12ts - ttl level bi-directional schmitt-triggered pin. open-drain output with 12 ma sink capability input low threshold voltage v t- 0.8 0.9 1.0 v v dd = 5 v input high threshold voltage v t+ 1.8 1.9 2.0 v v dd = 5 v hystersis v th 0.8 1.0 v v dd = 5 v output low voltage v ol 0.4 v i ol = 12 ma input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v
W83627THF publication release date: august 7, 2003 - 113 - revision 0.8 dc characteristics, continued parameter sym. min. typ max. unit conditions i/od 12tp3 ? 3.3 v ttl level bi-directional pin. op en-drain output with 12 ma sink capability input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 12 ma input high leakage i lih +10 a v in = 3.3v input low leakage i lil -10 a v in = 0v i/od 16cs - cmos level schmitt-triggered bi-directional pin. open-drain output with 16 ma sink capability input low threshold voltage v t- 1.3 1.5 1.7 v v dd = 5 v input high threshold voltage v t+ 3.2 3.5 3.8 v v dd = 5 v hystersis v th 1.5 2 v v dd = 5 v input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 16 ma input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v i/od 24t - ttl level bi-directional pin. open-drain output with 24 ma sink capability input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.4 v i ol = 24 ma input high leakage i lih +10 a v in = 5 v input low leakage i lil -10 a v in = 0 v od 8 - open-drain output pin with sink capability of 8 ma output low voltage v ol 0.4 v i ol = 8 ma od 12 - open-drain output pin with sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma
W83627THF publication release date: august 7, 2003 - 114 - revision 0.8 dc characteristics, continued parameter sym. min. typ max. unit conditions od 24 - open-drain output pin with sink capability of 24 ma output low voltage v ol 0.4 v i ol = 24 ma out 8 - ttl level output pin with source-sink capability of 8 ma output low voltage v ol 0.4 v i ol = 8 ma output high voltage v oh 2.4 v i oh = -8 ma out 12 - ttl level output pin with source-sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma out 24 - ttl level output pin with source-sink capability of 24 ma output low voltage v ol 0.4 v i ol = 24 ma output high voltage v oh 2.4 v i oh = -24 ma out 12tp3 - 3.3 v ttl level output pin with source-sink capability of 12 ma output low voltage v ol 0.4 v i ol = 12 ma output high voltage v oh 2.4 v i oh = -12 ma
W83627THF publication release date: august 7, 2003 - 115 - revision 0.8 11. application circuits 11.1 parallel port extension fdd 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 we2/slct wd2/pe mob2/busy dsb2/ack pd7 pd6 pd5 dch2/pd4 rdd2/pd3 step2/slin wp2/pd2 dir2/init trk02/pd1 head2/err idx2/pd0 rwc2/afd stb jp 13a ext fdc dch2 trk02 rdd2 dir2 wp2 mob2 rwc2 dsb2 head2 step2 wd2 we2 idx2 parallel port extension fdd mode connection diagram
W83627THF publication release date: august 7, 2003 - 116 - revision 0.8 11.2 parallel port extension 2fdd 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 printer port 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 jp13 we2/slct wd2/pe mob2/busy dsb2/ack pd5 dch2/pd4 rdd2/pd3 step2/slin wp2/pd2 dir2/init trk02/pd1 head2/err idx2/pd0 rwc2/afd stb jp 13a ext fdc dch2 trk02 rdd2 dir2 wp2 mob2 rwc2 dsb2 head2 step2 wd2 we2 idx2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 dsa2 moa2 parallel port extension 2fdd connection diagram dsa2/pd7 moa2/pd6 11.3 four fdd mode g1 a1 b1 g2 a2 b2 1y0 1y1 1y2 1y3 2y0 2y1 2y2 2y3 dsa moa dsa dsb moa mob w83977f 74ls139 7407(2) mod moc mob dsc dsd dsb
W83627THF publication release date: august 7, 2003 - 117 - revision 0.8 12. how to read the top marking example: the top marking of W83627THF 1st line: winbond logo 2nd line: the type number: W83627THF 3rd line: the tracking code 030a7c282012345ua 030 : packages made in '00, week 30 a : assembly house id; a means ase, s means spil.... etc. 7 : code version; 7 means code 007 c : ic revision; a means version a, b means version b 282012345 : wafer production series lot number ua : winbond internal use. inbond W83627THF 030a7c282012345ua
W83627THF publication release date: august 7, 2003 - 118 - revision 0.8 13. package dimensions (128-pin qfp) l l 1 detail f c e b 1 38 h d d 39 64 h e e 102 65 1.dimension d & e do not include interlead flash. 2.dimension b does not include dambar protrusion/intrusion 3.controlling dimension : millimeter 4.general appearance spec. should be based on final visual inspection spec. . note: seating plane see detail f y a a 1 a 2 128 103 5. pcb layout please use the "mm". symbol b c d e h d h e l y 0 a a l 1 1 2 e 7 0 0.08 1.60 0.95 17.40 0.80 17.20 0.65 17.00 14.10 0.20 0.30 2.87 14.00 2.72 0.50 13.90 0.10 0.10 2.57 0.25 min nom max dimension in mm 0.20 0.15 19.90 20.00 20.10 23.00 23.20 23.40 0.35 0.45 0.003 0 0.063 0.037 0.685 0.031 0.677 0.025 0.669 0.020 0.555 0.008 0.012 0.113 0.551 0.107 0.547 0.004 0.004 0.101 0.010 max nom min dimension in inch 0.006 0.008 7 0.783 0.787 0.791 0.905 0.913 0.921 0.014 0.018 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.
W83627THF publication release date: august 7, 2003 - 119 - revision 0.8 14. appendix a : demo circuit gp26 |627thf_6.sch sinb 3 pd1 ps2 mouse. fanout1 6 pciclk jp1 header 17x2 12 34 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 afd# 4 rsmrst# 5 msi 2 pd3 gpy2 2 gpsb1 2 pd2 io5v lad[0..3] game port ga20m |link trak0# indicated the vcc is ok. ctsb# 3 irtx 3 dtra# 3,5 gp52 gp50 avcc ack# 4 |627thf_4.sch wp# to power supply for turn on vcc. vin1 7 gp24 r1 4.7k avcc gp40 kdat 2 caseopen# 7 gpx1 2 printer we# h/w monitor err# 4 cputin 7 slin# 4 slct 4 gpsa2 2 gp51 fanout2 rtsa# 3,5 susled 5 stb# 4 io5v fanin2 6 gp23 head# lad3 io5v gp22 souta 3,5 mdat 2 |627thf_3.sch rtsb# 3 ria# 3 |627thf_1.sch gp25 c4 .1uf c1 0.1uf dcdb# 3 vtin 7 vin2 7 lad2 ctsa# 3 wdto fanout3 6 pd0 l1 fb don't need pull-up resistor gp53 pd7 gpx2 2 lad0 pwrok gpsa1 2 lad[0..3] pd5 rib# 3 gp55 busy 4 rwc# init# 4 dsrb# 3 fanin1 6 kclk 2 lreset# smi# dsa# r2 4.7k for vrd10's vid control lpc interface io5v wd# io5v mclk 2 kbrst gp31 systin 7 u2 osc 24m/48m hz 4 3 2 vcc o/p gnd |627thf_5.sch sina 3 soutb 3,5 for wake up function iovsb pwrctl# 5 gp30 pd4 rdata# cpuvcore 7 c3 0.1uf dsra# 3 index# comb & ir dtrb# 3 ovt# midi port gp36 W83627THF + fdc 0.1 W83627THF application circuit winbond electronic corp. b 17 wednesday, april 09, 2003 title size document number rev date: sheet of gp54 u1 W83627THF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 drvden0 smi#/irqin1 index# moa# fanin3 dsa# fanout3 dir# step# wd# we# vcc trak0# wp# rdata# head# dskchg# clkin pme# vss pciclk ldrq# serirq lad3 lad2 lad1 lad0 vcc3v lframe# lreset# slct pe busy ack# pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 slin# init# err# afd# stb# vcc ctsa# dsra# hefras/rtsa# pnpcsv/dtra# sina penkbc/souta vss dcda# ria# beep ga20m kbrst vsb kclk kdat susled/gp37 mclk mdat psout#/gp47 psin/gp46 gp45 rsmrst#/gp44 pwrok/gp43 pwrctl#/gp42 slp_sx#/gp41 vbat gp40 caseopen# gp36 ctsb# dsrb# rtsb# dtrb# sinb pen48/soutb dcdb# rib# gp35 irtx irrx/gp34 wdto/gp33 pled/gp32 gp31 gp30 gp26 gp25 gp24 gp23 vin3 vin2 vin1 cpuvcore vref vtin cputin systin gp55 gp54 gp53 gp52 gp51 gp50 ovt# fanin2 fanin1 avcc fanout2 fanout1 agnd gp22 msi/gp21 mso/irqin0/gp20 gpsa2/gp17 gpsb2/gp16 gpy1/gp15 gpy2/gp14 gpx2/gp13 gpx1//gp12 gpsb1/gp11 gpsa1/gp10 gp45 slp_sx# lframe# 5 pme# 5 serirq 5 psin 5 gpy1 2 mso 2 gp35 keyboard & io5v ldrq# 5 |627thf_2.sch fanin3 6 beep dir# dskchg# c2 .1uf coma iobat panswout# 5 moa# dcda# 3 pd6 step# lad1 |627thf_7.sch irrx 3 gpsb2 2 pled 5 vin3 7 pe 4 pd[0..7] 4 vref 7 io3v
W83627THF publication release date: august 7, 2003 - 120 - revision 0.8 c6 47p jp3:1-2 clear cmos vwake r9 2.2k gpsa1 1 r16 2.2k c5 10u io5v vwake gpy1 1 vwake circuit c13 0.01u c12 0.01u d2 1n4148 r5 4.7k bt1 battery 3v io5v io5v c17 0.01u l2 fb r6 4.7k io5v r4 4.7k c11 0.1u r19 1m r8 2.2k io5v mdat 1 onnow or wake_up function power battery circuit gpsb2 1 c18 0.01u mclk 1 2-3 enable onnow functions j1 header 6 1 2 3 4 5 6 c16 0.01u msi 1 l4 fb io5v gpsb1 1 d3 1n4148 gpsa2 1 c9 47p d1 1n4148 r17 2.2k iovsb game & midi port circuit l5 fb c7 47p r15 2.2k c20 0.01u kclk 1 jp3 head3 1 2 3 r10 2.2k r11 2.2k j2 header 6 1 2 3 4 5 6 r7 1k mso 1 p1 prt 8 15 7 14 6 13 5 12 4 11 3 10 2 9 1 r18 1m r13 2.2k jp2 kb/ms 1 2 12 r12 2.2k io5v c15 0.01u c19 0.01u vwake l6 fb game & midi & kbc 0.1 W83627THF application circuit winbond electronic corp. b 27 wednesday, april 09, 2003 title size document number rev date: sheet of gpx2 1 r14 2.2k r20 1m c10 47p gpx1 1 c14 0.01u iobat kdat 1 keyboard f1 fuse l3 fb c8 0.1u gpy2 1 r3 4.7k r21 1m ps2 mouse
W83627THF publication release date: august 7, 2003 - 121 - revision 0.8 dcdb# 1 gnd io-12v ndsrb p2 connector db9 5 9 4 8 3 7 2 6 1 nria dsrb# 1 uart+ir 0.1 W83627THF application circuit winbond electronic corp. b 37 wednesday, april 09, 2003 title size document number rev date: sheet of nrtsa io-12v rtsb# 1 nrib io+12v souta 1,5 (uartb) nrib nsoutb u4 w83778 20 16 15 13 19 18 17 14 12 11 1 5 6 8 2 3 4 7 9 10 vcc da1 da2 da3 ry1 ry2 ry3 ry4 ry5 gnd +12v dy1 dy2 dy3 ra1 ra2 ra3 ra4 ra9 -12v (sop20) ria# dtrb# 1 ndsrb io+12v nrtsa soutb 1,5 nctsa nria ndtra ir connector sina nrtsb ctsb# 1 ndsra ndcdb irtx 1 dsra# nsina nctsb jp4 header 5x2 12 34 56 78 910 dsra# 1 ndcda dtra# 1,5 nsinb io5v (sop20) ria# 1 io5v rib# 1 dtra# dcda# 1 rtsa# 1,5 ndcda nsoutb nsinb com port nctsa nctsb nsina j3 cn2x5 6 7 8 9 10 1 2 3 4 5 ndtra nsouta gnd sinb 1 ctsa# souta ndtrb sina 1 coma comb ndtrb irrx 1 ndcdb io5v nsouta rtsa# ndsra ctsa# 1 nrtsb u3 w83778 20 16 15 13 19 18 17 14 12 11 1 5 6 8 2 3 4 7 9 10 vcc da1 da2 da3 ry1 ry2 ry3 ry4 ry5 gnd +12v dy1 dy2 dy3 ra1 ra2 ra3 ra4 ra9 -12v (uarta) dcda#
W83627THF publication release date: august 7, 2003 - 122 - revision 0.8 c29 180p pd6 ndp15 pd[0..7] 1 err# 1 prt port pd2 pd[0..7] print port 0.1 W83627THF application circuit winbond electronic corp. b 47 wednesday, april 09, 2003 title size document number rev date: sheet of rp2 2.7k 1 8 2 7 3 6 4 5 afd# 1 pd7 c32 180p c37 180p j4 db25 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 c34 180p c30 180p slin# 1 pd1 ndp5 c24 180p c28 180p c26 180p d4 diode pe 1 c21 180p ack# 1 pd5 ndp2 c35 180p ndp10 r22 2.7k ndp13 ndp3 busy 1 init# 1 c23 180p ndp6 ndp11 c31 180p slct 1 rp1 2.7k 1 8 2 7 3 6 4 5 pd0 c25 180p io5v rp7 22 1 8 2 7 3 6 4 5 ndp12 rp6 22 1 8 2 7 3 6 4 5 pd3 c22 180p c36 180p ndp4 c33 180p rp5 22 1 8 2 7 3 6 4 5 rp4 2.7k 1 8 2 7 3 6 4 5 c27 180p rp3 2.7k 1 8 2 7 3 6 4 5 stb# 1 pd4
W83627THF publication release date: august 7, 2003 - 123 - revision 0.8 power setting 0.1 W83627THF application circuit winbond electronic corp. b 57 wednesday, april 09, 2003 title size document number rev date: sheet of io3v panswout# 1 pnpcsv soutb 1,3 ldrq# 1 suspend led circuit rsmrst# 1 r27 4.7k all 0 jp5 header 2 1 2 kbc enable 4e d5 susled pen48 r?(8p4ra1 4.7k 1 8 2 7 3 6 4 5 r23 4.7k psin 1 serirq 1 default kbc disable pwrctl# 1 i/o configuration address q2 2n3904 pen48 io3v io5v dtra# 1,3 r25 4.7k gp42 i/o port base default value clk 24m iovsb r29 10k rtsa# 1,3 c38 0.1u io3vsb lframe# 1 signal pullhigh stren pme# 1 rtsa# dtra# iovsb io5v q1 2n3904 souta 1,3 io5v soutb 1,3 panel switch 1 iovsb rp9 4.7k 1 8 2 7 3 6 4 5 rtsa# 1,3 pnpcsv soutb pled 1 rp11 4.7k 1 8 2 7 3 6 4 5 rp10 4.7k 1 8 2 7 3 6 4 5 lad[0..3] 1 s1 sw dip-5 1 2 3 4 5 10 9 8 7 6 r26 150 susled 1 d6 led power led circuit iovsb dtra# 1,3 penkbc souta 1,3 power on setting pin rp8 4.7k 1 8 2 7 3 6 4 5 souta r24 150 2e power on setting pin pin18 input clk value penkbc r28 1k clk 48m hefras hefras 0
W83627THF publication release date: august 7, 2003 - 124 - revision 0.8 fanout2 1 note : r36 20k r41 27k fanin1 1 + - u5b lm358 5 6 7 8 4 3. use ceb05p03, max. fanvcc is 12v r43 28k r32 4.7k fanin3 1 fan control 0.1 W83627THF application circuit winbond electronic corp. b 67 wednesday, april 09, 2003 title size document number rev date: sheet of fanin2 1 u6 lm1117 3 1 2 out adj in io+12v io+12v r38 28k d7 1n4148 + - u5a lm358 3 2 1 8 4 q3 npn 2sc5706 r39 20k r57 470k type 1 : transistor 2sc5706 type 2 : pmos ceb05p03 r34 28k 4. use lm1117, max. fanvcc max is 10.8v d8 1n4148 r40 4.7k q4 ceb05p03 d g s jp8 header 3 3 2 1 io+12v r35 27k r42 10k jp7 header 3 3 2 1 1. transistor,mosfet,ldo fanout3 1 r44 20k r37 10k circuit for dc fan speed control 2. use 2sc5706, max. fanvcc is 10.2v r30 4.7k we suggest to-252 or to-262 type of package r33 10k io+12v io+12v io+12v io+12v d9 1n4148 fanout1 1 type 3 : ldo lm1117 io+12v jp6 header 3 3 2 1 + - u7a lm358 3 2 1 8 4 r31 27k io+12v
W83627THF publication release date: august 7, 2003 - 125 - revision 0.8 r45 10k 1% ls1 speaker r52 28k 1% r54 10k 1% r46 10k 1% r49 30k r48 4.7k vin2 1 temperature sensing q5 npn t rt1 thermistor io3v vref c39 3300p io+12v io-12v voltage sensing s2 sw spst cpuvco r51 10k vref 1 vtin 1 cpud- r47 100 temperature+voltage sensing 0.1 W83627THF application circuit winbond electronic corp. b 77 wednesday, april 09, 2003 title size document number rev date: sheet of r55 56k 1% beep cpud+ 1 cpuvcore 1 io5v r53 10k 1% r50 2m r56 232k 1% vin3 1 iobat vin1 1 t rt2 thermistor systin 1 caseopen# 1 from cpu's therm diode cputin 1

▲Up To Search▲

Price & Availability of W83627THF

	To Download W83627THF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .