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sbas306a ? november 2004 ? revised december 2004 features 105ksps data rate ac performance: 51khz bandwidth 109db snr (high-resolution mode) ?105db thd dc accuracy: 1.8 v/ c offset drift 2ppm/ c gain drift selectable operating modes: high-speed: 105ksps data rate high-resolution: 109db snr low-power: 35mw dissipation power-down control digital filter: linear phase response passband ripple: 0.005db stop band attenuation: 100db internal offset calibration on command selectable spi or frame sync serial interface designed for multichannel systems: daisy-chainable serial interface easy synchronization simple pin-driven control specified from ?40 c to +105 c analog supply: 5v digital supply: 1.8v to 3.3v applications vibration/modal analysis acoustics dynamic strain gauges pressure sensors test and measurement description the ads1271 is a 24-bit, delta-sigma analog-to-digital converter (adc) with a data rate up to 105ksps. it offers a unique combination of excellent dc accuracy and outstanding ac performance. the high-order, chopper-stabilized modulator achieves very low drift with low in-band noise. the onboard decimation filter suppresses modulator and signal out-of-band noise. the ads1271 provides a usable signal bandwidth up to 90% of the nyquist rate with less than 0.005db of ripple. traditionally, industrial delta-sigma adcs offering good drift performance use digital filters with large passband droop. as a result, they have limited signal bandwidth and are mostly suited for dc measurements. high-resolution adcs in audio applications of fer larger usable bandwidths, but the offset and drift specification are significantly weaker than their industrial counterparts. the ads1271 combines these converters, allowing high-precision industrial measurement with excellent dc and ac specifications ensured over an extended industrial temperature range. three operating modes allow for optimization of speed, resolution, and power. a selectable spi or a frame-sync serial interface provides for convenient interfacing to microcontrollers or dsps. all operations, including internal offset calibration, are controlled directly by pins; there are no registers to program. ? modulator digital filter vrefp vrefn avdd dvdd drdy/fsync sclk dout din format ainp ainn serial interface control logic dgnd agnd sync/pdwn mode clk www.ti.com copyright ? 2004, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. all trademarks are the property of their respective owners.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 2 absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) ads1271 unit avdd to agnd ?0.3 to +6.0 v dvdd to dgnd ?0.3 to +3.6 v agnd to dgnd ?0.3 to +0.3 v input current 100, momentary ma input current 10, continuous ma analog input to agnd ?0.3 to avdd + 0.3 v digital input or output to dgnd ?0.3 to dvdd + 0.3 v maximum junction temperature +150 c operating temperature range ?40 to +105 c storage temperature range ?60 to +150 c lead temperature (soldering, 10s) +300 c (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. ordering information for the most current package and ordering information, see the package option addendum located at the end of this data sheet, or refer to our web site at www.ti.com. this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 3 electrical characteristics all specifications at t a = ?40 c to +105 c, avdd = +5v, dvdd = +1.8v, f clk = 27mhz, and v ref = +2.5v, unless otherwise noted. ads1271 parameter test conditions min typ max units analog inputs full-scale input voltage (fsr) (1) v in = (ainp ? ainn) v ref v absolute input voltage ainp or ainn to agnd agnd ? 0.1 avdd + 0.1 v common-mode input voltage v cm = (ainp + ainn)/2 2.5 v differential input high-speed mode 16.4 k ? differential input impedance high-resolution mode 16.4 k ? impedance low-power mode 32.8 k ? dc performance resolution no missing codes 24 bits high-speed mode 105,469 sps data rate (f data ) high-resolution mode 52,734 sps data rate (f data ) low-power mode 52,734 sps integral nonlinearity (inl) differential input, v cm = 2.5v 0.0006 0.0015 % of fsr (1) offset error high-speed mode without calibration 0.150 1 mv offset error with calibration on the level of the noise offset drift 1.8 v/ c gain error 0.1 0.5 % gain error drift 2 ppm/ c high-speed mode shorted input 9.0 20 v, rms noise high-resolution mode 6.5 v, rms noise low-power mode 9.0 v, rms common-mode rejection f cm = 60hz 90 100 db power-supply avdd f = 60hz 80 db power-supply rejection dvdd f = 60hz 80 db ac performance signal-to-noise ratio high-speed mode 99 106 db signal-to-noise ratio (snr) (2) (unweighted) high-resolution mode 109 db (snr) (2) (unweighted) low-power mode 106 db total harmonic distortion (thd) (3) v in = 1khz, ?0.5dbfs ?105 ?95 db spurious free dynamic range ?108 db passband ripple 0.005 db passband 0.453 f data hz ?3db bandwidth 0.49 f data hz stop band attenuation 100 db high-speed mode 0.547 f data 63.453 f data hz stop band high-resolution mode 0.547 f data 127.453 f data hz stop band low-power mode 0.547 f data 63.453 f data hz group delay high-speed and low-power modes 38/f data s group delay high-resolution mode 39/f data s settling time (latency) high-speed and low-power modes complete settling 76/f data s settling time (latency) high-resolution mode complete settling 78/f data s (1) fsr = full-scale range = 2v ref . (2) minimum snr is ensured by the limit of the dc noise specification. (3) thd includes the first nine harmonics of the input signals. (4) mode and format pins excluded. (5) see the text for more details on sclk.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 4 electrical characteristics (continued) all specifications at t a = ?40 c to +105 c, avdd = +5v, dvdd = +1.8v, f clk = 27mhz, and v ref = +2.5v, unless otherwise noted. units ads1271 parameter units max typ min test conditions voltage reference inputs reference input voltage (v ref ) v ref = vrefp ? vrefn 0.5 2.5 2.65 v negative reference input (vrefn) agnd ? 0.1 vrefp ? 0.5 v positive reference input (vrefp) vrefn + 0.5 avdd + 0.1 v reference input high-speed mode 4.2 k ? reference input impedance high-resolution mode 4.2 k ? impedance low-power mode 8.4 k ? digital input/output v ih 0.7 dvdd dvdd v v il dgnd 0.3 dvdd v v oh i oh = 5ma 0.8 dvdd dvdd v v ol i ol = 5ma dgnd 0.2 dvdd v input leakage (4) 0 < v in digital < dvdd 10 a master clock rate (f clk ) 1 27 mhz spi format 24 f data f clk mhz serial clock rate (f ) (5) high-speed mode 64 f data 64 f data mhz serial clock rate (f sclk ) (5) frame-sync format high-resolution mode 128 f data 128 f data mhz sclk frame-sync format low-power mode 64 f data 64 f data mhz power supply avdd 4.75 5 5.25 v dvdd 1.65 3.6 v high-speed mode 17 25 ma high-resolution mode 17 25 ma avdd current low-power mode 6.3 9.5 ma avdd current power-down mode t 105 c 1 70 a power-down mode t 85 c 1 10 a high-speed mode 3.5 6 ma high-resolution mode 2.5 5 ma dvdd current low-power mode 1.8 3.5 ma dvdd current power-down mode t 105 c, dvdd = 3.3v 1 70 a power-down mode t 85 c, dvdd = 3.3v 1 20 a high-speed mode 92 136 mw power dissipation high-resolution mode 90 134 mw power dissipation low-power mode 35 54 mw temperature range specified ?40 +105 c operating ?40 +105 c storage ?60 +150 c (1) fsr = full-scale range = 2v ref . (2) minimum snr is ensured by the limit of the dc noise specification. (3) thd includes the first nine harmonics of the input signals. (4) mode and format pins excluded. (5) see the text for more details on sclk.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 5 pin assignments tssop (pw) package (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vrefp vrefn dgnd dvdd clk sclk drdy/fsync dout ainp ainn agnd avdd mode format sync/pdwn din ads1271 terminal functions pin name no. function description ainp 1 analog input positive analog input ainn 2 analog input negative analog input agnd 3 analog input analog ground avdd 4 analog input analog supply mode 5 digital input mode = 0: high-speed mode mode 5 digital input mode = float: high-resolution mode mode = 1: low-power mode format 6 digital input format = 0: spi format = 1: frame-sync sync /pdwn 7 digital input synchronize/power-down input, active low din 8 digital input data input for daisy-chain operation dout 9 digital output data output drdy /fsync 10 digital input/output if format = 0 (spi), then pin 10 = drdy output if format = 1 (frame-sync), then pin 10 = fsync input sclk 11 digital input serial clock for data retrieval clk 12 digital input master clock dvdd 13 digital input digital supply dgnd 14 digital input digital ground vrefn 15 analog input negative reference input vrefp 16 analog input positive reference input
sbas306a ? november 2004 ? revised december 2004 www.ti.com 6 timing characteristics: spi format clk t cpw t clk t cpw t sd t s t dist t dohd t spw bit 23 (msb) bit 22 bit 21 t spw t dopd t cd t ds t ddo t dihd ??? t conv drdy sclk dout din timing requirements: spi format for t a = ?40 c to +105 c and dvdd = 1.65v to 3.6v. symbol parameter min typ max unit t clk clk period (1/f clk ) 37 1000 ns t cpw clk positive or negative pulse width 15 ns high-speed mode 256 clk periods t conv conversion period (1/f data ) high-resolution mode 512 clk periods t conv conversion period (1/f data ) low-power mode 512 clk periods t cd (1) falling edge of clk to falling edge of drdy 8 ns t ds (1) falling edge of drdy to rising edge of first sclk to retrieve data 5 ns t ddo (1) valid dout to falling edge of drdy 0 ns t sd (1) falling edge of sclk to rising edge of drdy 8 ns t s sclk period t clk ns t spw sclk positive or negative pulse width 12 ns t dohd (1) sclk falling edge to old dout invalid (hold time) 5 ns t dopd (1) sclk falling edge to new dout valid (propagation delay) 12 ns t dist new din valid to falling edge of sclk (setup time) 6 ns t dihd old din valid to falling edge of sclk (hold time) 6 ns (1) load on drdy and dout = 20pf.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 7 timing characteristics: frame-sync format sclk fsync dout din t dohd t fpw t s t sf t spw t spw t frame t fpw t fs t spw t dihd t ddo t dist bit 23 (msb) bit 22 bit 21 t dopd clk t cpw t cpw t cf ??? c timing requirements: frame-sync format for t a = ?40 c to +105 c and dvdd = 1.65v to 3.6v. symbol parameter min typ max unit t clk clk period (1/f clk ) 37 1000 ns t cpw clk positive or negative pulse width 15 ns t cs rising edge of clk to falling edge of sclk ?2 8 ns high-speed mode 256 clk periods t frame frame period (1/f data ) high-resolution mode 256 or 512 (1) clk periods t frame frame period (1/f data ) low-power mode 256 or 512 (1) clk periods t fpw fsync positive or negative pulse width 1 sclk periods t fs rising edge of fsync to rising edge of sclk 5 ns t sf rising edge of sclk to rising edge of fsync 5 ns sclk period (sclk must high-speed mode frame /64 frame periods s sclk period (sclk must be continuously running) high-resolution mode frame /128 frame periods s be continuously running) low-power mode frame /64 frame periods t spw sclk positive or negative pulse width 0.4 sclk 0.6 sclk ns t dohd (2) sclk falling edge to old dout invalid (hold time) 5 ns t dopd (2) sclk falling edge to new dout valid (propagation delay) 12 ns t ddo (2) valid dout to falling edge of fsync 0 ns t dist new din valid to falling edge of sclk (setup time) 6 ns t dihd old din valid to falling edge of sclk (hold time) 6 ns (1) the ads1271 automatically detects either frame period. (2) load on dout = 20pf.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 8 typical characteristics t a = 25 c, avdd = 5v, dvdd = 1.8v, f clk = 27mhz, and v ref = 2.5v, unless otherwise noted. figure 1 output spectrum 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 amplitude (db) 10k 100k high?speed mode f in = 1khz, ? 0.5dbfs 32,768 points figure 2 output spectrum 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 amplitude (db) 10k 100k high?speed mode f in =1khz, ? 20dbfs 32,768 points figure 3 output spectrum 0.1 1 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 ? 180 amplitude (db) 10k 100k high?speed mode shorted input 2,097,152 points figure 4 noise histogram ? 50 ? 45 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 15 20 25 30 35 40 45 50 output ( v) 420k 360k 300k 240k 180k 120k 60k 0 number of occurrences high?speed mode shorted input 2,097,152 points figure 5 output spectrum 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 amplitude (db) 10k 100k high?resolution mode f in =1khz, ? 0.5dbfs 32,768 points figure 6 output spectrum 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 amplitude (db) 10k 100k high?resolution mode f in = 1khz, ? 20dbfs 32,768 points
sbas306a ? november 2004 ? revised december 2004 www.ti.com 9 typical characteristics (continued) t a = 25 c, avdd = 5v, dvdd = 1.8v, f clk = 27mhz, and v ref = 2.5v, unless otherwise noted. figure 7 output spectrum 0.1 1 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 ? 180 amplitude (db) 10k 100k high?resolution mode shorted input 1,048,576 points figure 8 noise histogram ? 30 ? 28 ? 26 ? 24 ? 22 ? 20 ? 18 ? 16 ? 14 ? 12 ? 10 ? 8 ? 6 ? 4 ? 2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 output ( v) 210k 180k 150k 120k 90k 60k 30k 0 number of occurrences high?resolution mode shorted input 1,048,576 points figure 9 output spectrum 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 amplitude (db) 10k 100k low?power mode f in =1khz, ? 0.5dbfs 32,768 points figure 10 output spectrum 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 amplitude (db) 10k 100k low?power mode f in =1khz, ? 20dbfs 32,768 points figure 11 output spectrum 0.1 1 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 ? 180 amplitude (db) 10k 100k low?power mode shorted input 1,048,576 points figure 12 noise histogram ? 50 ? 45 ? 40 ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 5 10 15 20 25 30 35 40 45 50 output ( v) 200k 180k 160k 140k 120k 100k 80k 60k 40k 20k 0 number of occurrences low?power mode shorted input 1,048,576 points
sbas306a ? november 2004 ? revised december 2004 www.ti.com 10 typical characteristics (continued) t a = 25 c, avdd = 5v, dvdd = 1.8v, f clk = 27mhz, and v ref = 2.5v, unless otherwise noted. figure 13 total harmonic distortion vs frequency 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 thd, thd+n amplitude (db) 10k 100k high?speed mode v in = ? 0.5dbfs thd+n thd figure 14 total harmonic distortion vs input level ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 input amplitude (dbfs) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 thd, thd+n amplitude (db) high?speed mode f in =1khz thd+n thd figure 15 total harmonic distortion vs frequency 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 thd, thd+n amplitude (db) 10k 100k high?resolution mode v in = ? 0.5dbfs thd+n thd figure 16 total harmonic distortion vs input level ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 input amplitude (dbfs) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 thd, thd+n amplitude (db) high?resolution mode f in =1khz thd+n thd figure 17 total harmonic distortion vs frequency 10 100 1k frequency (hz) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 thd, thd+n amplitude (db) 10k 100k low?power mode v in = ? 0.5dbfs thd+n thd figure 18 total harmonic distortion vs input level ? 120 ? 100 ? 80 ? 60 ? 40 ? 20 0 input amplitude (dbfs) 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 thd, thd+n amplitude (db) low?power mode f in =1khz thd+n thd
sbas306a ? november 2004 ? revised december 2004 www.ti.com 11 typical characteristics (continued) t a = 25 c, avdd = 5v, dvdd = 1.8v, f clk = 27mhz, and v ref = 2.5v, unless otherwise noted. figure 19 absolute offset drift histogram 1 3 5 7 9 111315171921 absolute offset drift ( v/ c) 60 50 40 30 20 10 0 occurrences (%) 30 units, based on 20 cintervals figure 20 gain drift histogram ? 6.0 ? 5.5 ? 5.0 ? 4.5 ? 4.0 ? 3.5 ? 3.0 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 gain drift (ppm/ c) 15 10 5 0 occurrences (%) 30 units, based on 20 c intervals figure 21 offset power?on warmup 0 102030405060 time after power?on (s) 40 30 20 10 0 ? 10 ? 20 ? 30 ? 40 normalized offset ( v) high?speed mode dvdd = 3.3v response band figure 22 gain error power?on warmup 0 10203040 5060 time after power?on (s) 10 8 6 4 2 0 ? 2 ? 4 ? 6 ? 8 ? 10 normalized gain error (ppm) high?speed mode dvdd = 3.3v response band figure 23 uncalibrated offset histogram ? 500 ? 450 ? 400 ? 350 ? 300 ? 250 ? 200 ? 150 ? 100 ? 50 0 50 100 150 200 250 300 uncalibrated offset ( v) 30 20 10 0 units (%) high?speed mode 30 units figure 24 gain error histogram ? 2350 ? 2300 ? 2250 ? 2200 ? 2150 ? 2100 ? 2050 ? 2000 ? 1950 ? 1900 ? 1850 ? 1800 ? 1750 ? 1700 ? 1650 ? 1600 gain error (ppm) 50 40 30 20 10 0 units (%) high?speed mode 30 units
sbas306a ? november 2004 ? revised december 2004 www.ti.com 12 typical characteristics (continued) t a = 25 c, avdd = 5v, dvdd = 1.8v, f clk = 27mhz, and v ref = 2.5v, unless otherwise noted. figure 25 reference input differential impedance vs temperature ? 40 ? 20 0 20 40 60 80 100 temp er a ture ( c) 4280 4260 4240 4220 4200 4180 4160 4140 4120 4100 reference input impedance ( ? ) 120 125 high?speed and high?resolution modes figure 26 reference input differential impedance vs temperature ? 40 ? 20 0 20 40 60 80 100 temperature ( c) 8900 8800 8700 8600 8500 8400 8300 8200 reference input impedance ( ? ) 120 125 low?power mode figure 27 analog input differential impedance vs temperature ? 40 ? 20 0 20 40 60 80 100 temp er a ture ( c) 16550 16500 16450 16400 16350 16300 16250 16200 16150 analog input impedance ( ? ) 120 125 high?speed and high?resolution modes figure 28 analog input differential impedance vs temperature ? 40 ? 20 0 20 40 60 80 100 temp er a ture ( c) 33200 33000 32800 32600 32400 32200 32000 analog input impedance ( ? ) 120 125 low?power mode figure 29 integral nonlinearity vs temperature ? 40 ? 20 0 20 40 60 80 100 temperature ( c) 14 12 10 8 6 4 2 0 inl (ppm) 120 125 high? resolution high?speed low?power figure 30 linearity error vs input level ? 2.5 ? 2.0 2.0 ? 1.5 1.5 ? 1.0 1.0 ? 0.5 0.5 0 v in (v) 10 8 6 4 2 0 ? 2 ? 4 ? 6 ? 8 ? 10 linearity error (ppm) 2.5 high?speed mode t=+25 c t=+125 c t=+105 c t= ? 40 c
sbas306a ? november 2004 ? revised december 2004 www.ti.com 13 typical characteristics (continued) t a = 25 c, avdd = 5v, dvdd = 1.8v, f clk = 27mhz, and v ref = 2.5v, unless otherwise noted. figure 31 noise vs avdd 4.75 4.85 5.15 4.95 5.05 av dd (v) 20 18 16 14 12 10 8 6 4 2 0 rms noise ( v) 5.25 high?resolution high?speed low?power figure 32 noise vs dvdd 1.6 2.0 2.2 1.8 3.2 3.4 2.4 2.6 2.8 3.0 dvdd (v) 20 18 16 14 12 10 8 6 4 2 0 rms noise ( v) 3.6 high?resolution high?speed low?power figure 33 noise vs temperature ? 40 ? 20 0 20 40 60 80 100 temperature ( c) 12 10 8 6 4 2 0 rms noise ( v) 120 125 high?resolution high?speed low?power figure 34 noise vs input level ? 2.5 ? 2.0 ? 1.5 ? 1.0 1.5 1.0 ? 0.5 0.5 0 v in (v) 20 18 16 14 12 10 8 6 4 2 0 rms noise ( v) 2.5 2.0 high?resolution high?speed low?power figure 35 avdd current vs temperature ? 40 ? 20 0 20 40 60 80 100 temp er a ture ( c) 22 20 18 16 14 12 10 8 6 4 2 0 avdd current (ma) 120 125 high?speed and high?resolution low?power figure 36 dvdd current vs temperature ? 40 ? 20 0 20 40 60 80 100 temperature ( c) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 dvdd current (ma) 120 125 low?power high?resolution high?speed
sbas306a ? november 2004 ? revised december 2004 www.ti.com 14 overview the ads1271 is a 24-bit, delta-sigma adc. it offers the combination of outstanding dc accuracy and superior ac performance. figure 37 shows the block diagram for the ads1271. the ads1271 converter is comprised of an advanced, 6th-order, chopper-stabilized, delta-sigma modulator followed by a low-ripple, linear phase fir filter. the modulator measures the differential input signal, v in = (ainp ? ainn), against the differential reference, v ref = (vrefp ? vrefn). the digital filter receives the modulator signal and provides a low-noise digital output. to allow tradeoffs among speed, resolution, and power, three modes of operation are supported on the ads1271: high-speed, high-resolution, and low-power. table 1 summarizes the performance of each mode. in high-speed mode, the data rate is 105ksps; in high-resolution mode, the snr = 109db; and in low-power mode, the power dissipation is only 35mw. the ads1271 is configured by simply setting the appropriate io pins?there are no registers to program. data is retrieved over a serial interface that supports both spi and frame-sync formats. the ads1271 has a daisy-chainable output and the ability to synchronize externally, so it can be used conveniently in multichannel systems. ? modulator digital filter vrefp v ref v in vrefn drdy/fsync sclk dout din format sync/pdwn mode clk spi or frame? sync serial interface ainp ainn figure 37. block diagram table 1. operating mode performance summary mode data rate (sps) passband (hz) snr (db) noise ( v rms ) power (mw) high-speed 105,469 47,777 106 9.0 92 high-resolution 52,734 23,889 109 6.5 90 low-power 52,734 23,889 106 9.0 35
sbas306a ? november 2004 ? revised december 2004 www.ti.com 15 analog inputs (ainp, ainn) the ads1271 measures the differential input signal v in = (ainp ? ainn) against the differential reference v ref = (vrefp ? vrefn). the most positive measurable differential input is +v ref , which produces the most positive digital output code of 7fffffh. likewise, the most negative measurable differential input is ?v ref , which produces the most negative digital output code of 800000h. while the ads1271 measures the differential input signal, the absolute input voltage is also important. this is the voltage on either input (ainp or ainn) with respect to agnd. the range for this voltage is: ?0.1v < (ainn or ainp) < avdd +0.1v if either input is taken below ?0.1v or above (avdd + 0.1), esd protection diodes on the inputs may turn on. the ads1271 uses switched-capacitor circuitry to measure the input voltage. internal capacitors are charged by the inputs and then discharged. figure 38 shows a conceptual diagram of these circuits. switch s2 represents the net effect of the modulator circuitry in discharging the sampling capacitor; the actual implementation is dif ferent. the timing for switches s1 and s2 is shown in figure 39. the sampling time (t sample ) is the inverse of modulator sampling frequency (f mod ) and is a function of the mode, format, and frequency of clk, as shown in t able 2. when using the frame-sync format with high-resolution or low-power modes, the ratio between f mod and f clk depends on the frame period that is set by the fsync input. esd protection avdd agnd avdd ainp 9pf ainn agnd s 1 s 1 s 2 figure 38. equivalent analog input circuitry on off s1 on off s2 t sample =1/f mod figure 39. s1 and s2 switch timing for figure 38 table 2. modulator frequency for the different mode and format settings mode interface format f mod high-speed spi or frame-sync f clk /4 high-resolution spi f clk /4 high-resolution frame-sync f clk /4 or f clk /2 low-power spi f clk /8 low-power frame-sync f clk /8 or f clk /4 the average load presented by the switched capacitor input can be modeled with an effective differential impedance, as shown in figure 40. note that the effective impedance is a function of f mod . ainp ainn zeff = 16.4k ? (6.75mhz/f mod ) figure 40. effective input impedances the ads1271 is a very high-performance adc. for optimum performance, it is critical that the appropriate circuitry be used to drive the ads1271 inputs. see the application information section for the recommended circuits.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 16 voltage reference inputs (vrefp, vrefn) the voltage reference for the ads1271 adc is the differential voltage between vrefp and vrefn: v ref = (vrefp?vrefn). the reference inputs use a structure similar to that of the analog inputs with the equivalent circuitry on the reference inputs shown in figure 41. as with the analog inputs, the load presented by the switched capacitor can be modeled with an effective impedance, as shown in figure 42. esd protection avdd avdd vrefn vrefp figure 41. equivalent reference input circuitry vrefp vrefn zeff = 4.2k ? (6.75mhz/f mod ) figure 42. effective reference impedance esd diodes protect the reference inputs. to keep these diodes from turning on, make sure the voltages on the reference pins do not go below agnd by more than 0.1v, and likewise do not exceed avdd by 0.1v: ?0.1v < (vrefp or vrefn) < avdd + 0.1v a high-quality reference voltage with the appropriate drive strength is essential for achieving the best performance from the ads1271. noise and drift on the reference degrade overall system performance. see the application information section for example reference circuits. clock input (clk) the ads1271 requires an external clock signal to be applied to the clk input pin. as with any high-speed data converter, a high-quality, low-jitter clock is essential for optimum performance. crystal clock oscillators are the recommended clock source. make sure to avoid excess ringing on the clock input; keeping the clock trace as short as possible using a 47 ? series resistor will help. the ratio between the clock frequency and output data rate is a function of the mode and format. table 3 shows the ratios when the spi format is selected. also included in this table is the typical clk frequency and the corresponding data rate. when high-speed mode is used, each conversion takes 256 clk periods. when high-resolution or low-power modes are selected, the conversions take 512 clk periods. table 4 shows the ratios when the frame-sync format is selected. when using the frame-sync format in either high-resolution or low-power mode, the f clk /f data ratio can be 256 or 512. the ads1271 automatically detects which ratio is being used. using a ratio of 512 allows the clk frequency to be reduced by a factor of two while maintaining the same data rate. the output data rate scales with the clock frequency. see the serial interface section for more details on the frame-sync operation. table 3. clock ratios for spi format mode selection f clk /f data typical f clk (mhz) corresponding data rate (sps) high-speed 256 27 105,469 high-resolution 512 27 52,734 low-power 512 27 52,734 table 4. clock ratios for frame-sync format mode selection f clk /f frame typical f clk (mhz) corresponding data rate (sps) high-speed 256 27 105,469 high-resolution 256 13.5 52,734 high-resolution 512 27 52,734 low-power 256 13.5 52,734 low-power 512 27 52,734
sbas306a ? november 2004 ? revised december 2004 www.ti.com 17 mode selection (mode) the ads1271 supports three modes of operation: high-speed, high-resolution, and low-power. the mode selection is determined by the status of the digital input mode pin, as shown in table 5. a high impedance, or floating, condition allows the mode pin to support a third state. the ads1271 constantly monitors the status of the mode pin during operation and responds to a change in status after 12,288 clk periods. when floating the mode pin, keep the total capacitance on the pin less than 100pf and the resistive loading greater than 10m ? to ensure proper operation. changing the mode clears the internal offset calibration value. if onboard offset calibration is being used, be sure to recalibrate after a mode change. when daisy-chaining multiple ads1271s together and operating in high-resolution mode (mode pin floating), the mode pin of each device must be isolated from one another; this ensures proper device operation. the mode pins can be tied together for high-speed and low-power modes. table 5. mode selection mode pin status mode selection logic low (dgnd) high-speed floating (1) high-resolution logic high (dvdd) low-power (1) load on mode: c < 100pf, r > 10m ? when using the spi format, drdy is held high after a mode change occurs until settled (or valid) data is ready, as shown in figure 43. in frame-sync format, the dout pin is held low after a mode change occurs until settled data is ready, as shown in figure 43. data can be read from the device to detect when dout changes to logic 1, indicating valid data. format selection (format) to help connect easily to either microcontrollers or dsps, the ads1271 supports two formats for the serial interface: an spi-compatible interface and a frame-sync interface. the format is selected by the format pin, as shown in table 6. it is recommended that the format pin be directly tied to the appropriate voltage. if the status of this pin changes, perform a sync operation afterwards to ensure proper operation. table 6. format selection format pin status serial interface format logic low (dgnd) spi logic high (dvdd) frame-sync mode pin ads1271 mode high?speed symbol t md time to register mode changes clk periods t ndr time for new data to be ready 128 conversions (1/f data ) min typ max units description low?power low?power mode valid data ready drdy spi format frame?sync format clk t md dout low?power mode validdataondout t ndr t ndr 12,288 figure 43. mode change timing
sbas306a ? november 2004 ? revised december 2004 www.ti.com 18 synchronization the sync /pdwn pin has two functions. when pulsed, it synchronizes the start of conversions and, if held low for more than 2 19 clk cycles (t syn ), places the ads1271 in power-down mode. see the power-down and offset calibration section for more details. the ads1271 can be synchronized by taking sync /pdwn low. this stops the conversion process and resets the internal counters used by the digital filter. return sync /pdwn high on the rising edge of clk to begin the conversion process. synchronization allows the conversions to be aligned with an external event; for example, the changing of an external multiplexer on the analog inputs. it can also be used to synchronize the conversions of multiple ads1271s. in the spi format, drdy goes high as soon as sync /pdwn is taken low, as shown in figure 44. after sync /pdwn is returned high, drdy stays high while the digital filter is settling. once valid data is ready for retrieval, drdy goes low. in the frame-sync format, dout goes low as soon as sync /pdwn is taken low, as shown in figure 45. after sync /pdwn is returned high, dout stays low while the digital filter is settling. once valid data is ready for retrieval, dout begins to output valid data. the device detects the state of the sync /pdwn pin on the falling edge. when synchronizing multiple devices, set the sync /pdwn pin high on the rising edge of sclk to ensure all devices are restarted on the same sclk period. it is recommended to leave fsync and sclk running during a synchronization. clk drdy sync/pdwn t ndr t syn ??? ??? symbol t syn synchronize pulse width 2 18 1 clk periods t ndr time for new data to be ready 128 conversions (1/f data ) min typ max units description figure 44. synchronization timing for spi format clk fsync val id da ta dout sync/pdwn t ndr t syn ??? ??? symbol t syn synchronize pulse width 2 18 1 clk periods t ndr time for new data to be ready 128 conversions (1/f data ) min typ max units description 129 figure 45. synchronization timing for frame-sync format
sbas306a ? november 2004 ? revised december 2004 www.ti.com 19 power-down and offset calibration in addition to controlling synchronization, the sync /pdwn pin also serves as the control for power-down mode and offset calibration. to enter this mode, hold the sync /pdwn pin low for at least 2 19 clk periods. while in power-down mode, both the analog and digital circuitry are completely deactivated. the digital inputs are internally disabled so that is not necessary to shut down clk and sclk. to exit power-down mode, return sync /pdwn high on the rising edge of clk. the ads1271 uses a chopper-stabilized modulator to provide inherently very low offset drift. to further minimize offset, the ads1271 automatically performs an offset self-calibration when exiting power-down mode. when power down completes, the offset self-calibration begins with the inputs ainp and ainn automatically disconnected from the signal source and internally shorted together. there is no need to modify the signal source applied to the analog inputs during this calibration. it is critical for the reference voltage to be stable when exiting power-down mode; otherwise, the calibration will be corrupted. the offset self-calibration only removes offset errors internal to the device, not offset errors due to external sources. note: when an offset self-calibration is performed, the resulting offset value will vary each time within the peak-to-peak noise range of the converter. in high-speed mode, this is typically 178 lsbs. the offset calibration value is cleared whenever the device mode is changed (for example, from high-speed mode to high-resolution mode). when using the spi format, drdy will stay high after exiting power-down mode while the digital filter settles, as shown in figure 46. when using the frame-sync format, dout will stay low after exiting power-down mode while the digital filter settles, as shown in figure 47. status clk converting sync power down converting post?calibration data ready offset cal and filter settling drdy ??? ??? sync/pdwn t pdwn t ofs symbol t pdwn pulse width to enter power?down mode 2 19 clk periods t ofs time for offset calibration and filter settling 256 conversions (1/f data ) min typ max units description sync /pdwn figure 46. power-down timing for spi format symbol t pdwn pulse width to enter power?down mode 2 19 clk periods t ofs time for offset calibration and filter settling 257 256 conversions (1/f data ) min typ max units description status clk fsync dout ??? ??? sync/pdwn t ofs t pdwn converting sync power down converting post?calibration data offset cal and filter settling sync /pdwn figure 47. power-down timing for frame-sync format
sbas306a ? november 2004 ? revised december 2004 www.ti.com 20 power-up sequence the analog and digital supplies should be applied before any analog or digital input is driven. the power supplies may be sequenced in any order. once the supplies and the voltage reference inputs have stabilized, data can be read from the device. frequency response the digital filter sets the overall frequency response. the filter uses a multi-stage fir topology to provide linear phase with minimal passband ripple and high stopband attenuation. the oversampling ratio of the digital filter (that is, the ratio of the modulator sampling to the output data rate: f mod /f data ) is a function of the selected mode, as shown in table 7. f mod is clk/2 or clk/4, depending on the mode. table 7. oversampling ratio versus mode mode oversampling ratio (f mod /f data ) high-speed 64 high-resolution 128 low-power 64 high-speed and low-power modes the digital filter configuration is the same in both high-speed and low-power modes with the oversampling ratio set to 64. figure 48 shows the frequency response in high-speed and low-power modes normalized to f data . figure 49 shows the passband ripple. the transition from passband to stop band is illustrated in figure 50. the overall frequency response repeats at 64x multiples of the modulator frequency f mod , as shown in figure 51. these image frequencies, if present in the signal and not externally filtered, will fold back (or alias) into the passband, causing errors. however, with such a wide stopband, only a simple low-order, antialias filter is typically required in front of the ads1271 inputs to limit out-of-band noise. see table 8 for more detail. 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 0.4 normalized input frequency (f in /f data ) amplitude (db) 0 0.2 0.6 0.8 1.0 figure 48. frequency response for high-speed and low-power modes 0.02 0 ? 0.02 ? 0.04 ? 0.06 ? 0.08 ? 0.10 0.2 normalized input frequency (f in /f data ) amplitude (db) 0 0.1 0.3 0.4 0.5 0.6 figure 49. passband response for high-speed and low-power modes 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 normalized input frequency (f in /f data ) amplitude (db) 0.45 0.47 0.49 0.51 0.53 0.55 figure 50. transition band response for high-speed and low-power modes 20 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 input frequency (f in /f data ) gain (db) 016324864 figure 51. frequency response out to f mod for high-speed and low-power modes
sbas306a ? november 2004 ? revised december 2004 www.ti.com 21 high-resolution mode the oversampling ratio is 128 in high-resolution mode. figure 52 shows the frequency response in high-resolution mode normalized to f data . figure 53 shows the passband ripple, and the transition from passband to stop band is illustrated in figure 54. the overall frequency response repeats at multiples of the modulator frequency f mod , (128 f data ), as shown in figure 55. with such an extremely wide stop band, only a simple antialias filter is typically required in front of the ads1271 inputs to limit out-of-band noise. see table 8 for more detail. 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 0.50 normalized input frequency (f in /f data ) amplitude (db) 00.25 0.75 1 figure 52. frequency response for high-resolution mode 0.02 0 ? 0.02 ? 0.04 ? 0.06 ? 0.08 ? 0.10 0.2 normalized input frequency (f in /f data ) amplitude (db) 0 0.1 0.3 0.4 0.5 0.6 figure 53. passband response for high-resolution mode 0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 normalized input frequency (f in /f data ) amplitude (db) 0.45 0.47 0.49 0.51 0.53 0.55 figure 54. transition band response for high-resolution mode 20 0 ? 20 ? 40 ? 60 ? 80 ? 100 ? 120 ? 140 ? 160 gain (db) normalized input frequency (f in /f data ) 0 32 64 96 128 figure 55. frequency response out to f mod for high-resolution mode table 8. antialias filter order image rejection antialias image rejection (db) (f ?3db at f data ) antialias filter order hs, lp hr 1 39 45 2 75 87 3 111 129
sbas306a ? november 2004 ? revised december 2004 www.ti.com 22 phase response the ads1271 incorporates a multiple stage, linear phase digital filter. linear phase filters exhibit constant delay time versus input frequency (constant group delay). this means the time delay from any instant of the input signal to the same instant of the output data is constant and is independent of input signal frequency. this behavior results in essentially zero phase errors when analyzing multi-tone signals. settling time as with frequency and phase response, the digital filter also determines settling time. figure 56 shows the output settling behavior after a step change on the analog inputs normalized to conversion periods. the x axis is given in units of conversion. note that after the step change on the input occurs, the output data changes very little prior to 30 conversion periods. the output data is fully settled after 76 conversion periods for high-speed and low-power modes, and 78 conversions for high-resolution mode. 100 0 % settling conversions (1/f data ) 020 10 40 30 60 50 80 70 fully settled data at 76 conversions (78 conversions for high?resolution mode) initial value final value figure 56. settling time for all power modes data format the ads1271 outputs 24 bits of data in two?s complement format. a positive full-scale input produces an output code of 7fffffh, and the negative full-scale input produces an output code of 800000h. the output clips at these codes for signals exceeding full-scale. table 9 summarizes the ideal output codes for different input signals. table 9. ideal output code versus input signal input signal v in (ainp ? ainn) ideal output code (1) +v ref 7fffffh +v ref 2 23 1 000001h 0 000000h ?v ref 2 23 1 ffffffh ?v ref 2 23 2 23 1 800000h (1) excludes effects of noise, inl, offset and gain errors. serial interface data is retrieved from the ads1271 using the serial interface. to provide easy connection to either microcontrollers or dsps, two formats are available for the interface: spi and frame-sync. the format pin selects the interface. the same pins are used for both interfaces (sclk, drdy /fsync, dout and din), though their respective functionality depends on the particular interface selected. spi serial interface the spi-compatible format is a simple read-only interface. data ready for retrieval is indicated by the drdy output and is shifted out on the falling edge of sclk, msb first. the interface can be daisy-chained using the din input when using multiple ads1271s. see the daisy-chaining section for more information. sclk (spi format) the serial clock (sclk) features a schmitt-triggered input and shifts out data on dout on the falling edge. it also shifts in data on the falling edge on din when this pin is being used for daisy-chaining. the device shifts data out on the falling edge and the user shifts this data in on the rising edge. even though the sclk input has hysteresis, it is recommended to keep sclk as clean as possible to prevent glitches from accidentally shifting the data. sclk should be held low after data retrieval. sclk may be run as fast as the clk frequency. sclk may be either in free-running or stop-clock operation between conversions. to maximize the converter performance, the ratio of clk to sclk should be held to: sclk clk 2 n n 0, 1, 2 .
sbas306a ? november 2004 ? revised december 2004 www.ti.com 23 drdy /fsync in the spi format, this pin functions as the drdy output. it goes low when data is ready for retrieval and then returns high on the rising edge of the first subsequent sclk. if data is not retrieved (that is, sclk is held low), drdy will pulse high just before the next conversion data is ready, as shown in figure 57. the new data is loaded within the ads1271 one clk cycle before drdy goes low. all data must be shifted out before this time to avoid being overwritten. drdy sclk 1/f data 1/f clk figure 57. drdy timing with no readback dout the conversion data is shifted out on dout. the msb data is valid on dout when drdy goes low. the subsequent bits are shifted out with each falling edge of sclk. if daisy-chaining, the data shifted in using din will appear on dout after all 24 bits have been shifted out. din this input is used when multiple ads1271s are to be daisy-chained together. the dout pin of the first device connects to the din pin of the next, etc. it can be used with either the spi or frame-sync formats. data is shifted in on the falling edge of sclk. when using only one ads1271, tie din low. see the daisy-chaining section for more information. frame-sync serial interface frame-sync format is similar to the interface often used on audio adcs. it operates in slave fashion?the user must supply framing signal fsync (similar to the left/right clock on stereo audio adcs) and the serial clock sclk (similar to the bit clock on audio adcs). the data is output msb first or left-justified . when using frame-sync format, the clk, fsync and sclk inputs must be synchronized together, as described in the following sub-sections. sclk (frame-sync format) the serial clock (sclk) features a schmitt-triggered input and shifts out data on dout on the falling edge. it also shifts in data on the falling edge on din when this pin is being used for daisy-chaining. even though sclk has hysteresis, it is recommended to keep sclk as clean as possible to prevent glitches from accidentally shifting the data. when using frame-sync format, sclk must run continuously. if it is shut down, the data readback will be corrupted. frame-sync format requires a specific relationship between sclk and fsync, determined by the mode shown in table 10. table 10. sclk period when using frame-sync format mode required sclk period high-speed frame /64 high-resolution frame /128 low-power frame /64 drdy /fsync in frame-sync format, this pin is used as the fsync input. the frame-sync input (fsync) sets the frame period. the required fsync periods are shown in table 11. for high-speed mode, the fsync period must be 256 clk periods. for both high-resolution and low-power modes, the fsync period can be either 512 or 256 clk periods; the ads1271 will automatically detect which is being used. if the fsync period is not the proper value, data readback will be corrupted. it is recommended that fsync be aligned with the falling edge of sclk. table 11. fsync period mode required fsync period high-speed 256 clk periods high-resolution 256 or 512 clk periods low-power 256 or 512 clk periods dout the conversion data is shifted out on dout. the msb data becomes valid on dout on the sclk rising edge prior to fsync going high. the subsequent bits are shifted out with each falling edge of sclk. if daisy-chaining, the data shifted in using din will appear on dout after all 24 bits have been shifted out. din this input is used when multiple ads1271s are to be daisy-chained together. it can be used with either spi or frame-sync formats. data is shifted in on the falling edge of sclk. when using only one ads1271, tie din low .see the daisy-chaining section for more information.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 24 daisy-chaining multiple ads1271s can be daisy-chained together to simplify the serial interface connections. the dout of one ads1271 is connected to the din of the next ads1271. the first dout provides the output data and the last din in the chain is connected to ground. a common sclk is used for all the devices in the daisy chain. figure 58 shows an example of a daisy chain with four ads1271s. figure 59 shows the timing diagram when reading back in the spi format. it takes 96 sclks to shift out all the data. in spi format, it is recommended to tie all the sync /pdwn inputs together, which forces synchronization of all the devices. it is only necessary to monitor the drdy output of one device when multiple devices are configured this way. in frame-sync format, all of the devices are driven to synchronization by the fsync and sclk inputs. however, to ensure synchronization to the same f clk cycle, it is recommended to tie all sync /pdwn inputs together. the device clocks the sync /pdwn pin on the falling edge of f clk . to ensure exact synchronization, the sync /pdwn pin should transition on the rising edge of f clk since dout and din are both shifted on the falling edge of sclk, the propagation delay on dout creates the setup time on din. minimize the skew in sclk to avoid timing violations. see mode selection section for mode pin use when daisy-chaining. the spi format offers the most flexibility when daisy-chaining because there is more freedom in setting the sclk frequency. the maximum number of ads1271s that can be daisy-chained is determined by dividing the conversion time (1/f data ) by the time needed to read back all 24 bits (24 1/f sclk ). consider the case where: f clk = 27mhz mode = high-resolution (52,734sps) format = spi f sclk = 27mhz the maximum length of the daisy-chain is: 27mhz/(24 52,734sps) = 21.3 rounding down gives 21 as the maximum number of ads1271s that can be daisy-chained. daisy-chaining also works in frame-sync format, but the maximum number of devices that can be daisy-chained is less than when using the spi format. the ratio between the frame period and sclk period is fixed, as shown in table 10. using these values, the maximum number of devices is two for high-speed and low-power modes, and four for high-resolution mode. ads1271 4 din sclk sclk sync dout ads1271 3 dout ads1271 2 dout ads1271 1 dout sync din sclk sync din sclk sync din sclk sync drdy figure 58. example of spi-format, daisy-chain connection for multiple ads1271s drdy sclk 1 ads1271 1 bit 23 (msb) ads1271 1 bit 0 (lsb) ads1271 4 bit 0 (lsb) ads1271 2 bit 23 (msb) ads1271 4 bit 23 (msb) 24 25 73 96 dout figure 59. timing diagram for example in figure 58 (spi format)
sbas306a ? november 2004 ? revised december 2004 www.ti.com 25 application information to obtain the specified performance from the ads1271, the following layout and component guidelines should be considered. 1. power supplies: the device requires two power supplies for operation: dvdd and av dd. the allowed range for dvdd is 1.65v to 3.6v, and avdd is restricted to 4.75v to 5.25v. best performance is achieved when dvdd = 1.8v. for both supplies, use a 10 f tantalum capacitor, bypassed with a 0.1 f ceramic capacitor, placed close to the device pins. alternatively, a single 10 f ceramic capacitor can be used. the supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, led display drivers, etc.). if a switching power supply source is used, the voltage ripple should be low (< 2mv). the power supplies may be sequenced in any order. 2. ground plane: a single ground plane connecting both agnd and dgnd pins can be used. if separate digital and analog grounds are used, connect the grounds together at the converter. 3. digital inputs: it is recommended to source terminate the digital inputs to the device with 50 ? series resistors. the resistors should be placed close to the driving end of digital source (oscillator, logic gates, dsp, etc.) this helps to reduce ringing on the digital lines, which may lead to degraded adc performance. 4. analog/digital circuits: place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (dsp, microcontroller, logic). avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk. 5. reference inputs: it is recommended to use a minimum 10 f tantalum with a 0.1 f ceramic capacitor directly across the reference inputs, refp and refn. the reference input should be driven by a low-impedance source. for best performance, the reference should have less than 3 v rms broadband noise. for references with noise higher than this, external reference filtering may be necessary. 6. analog inputs: the analog input pins must be driven differentially to achieve specified performance. a true differential driver or transformer (ac applications) can be used for this purpose. route the analog inputs tracks (ainp, ainn) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. a 1nf to 10nf capacitor should be used directly across the analog input pins, ainp and ainn. a low-k dielectric (such as cog or film type) should be used to maintain low thd. capacitors from each analog input to ground should be used. they should be no larger than 1/10 the size of the dif ference capacitor (typically 100pf) to preserve the ac common-mode performance. 7. component placement: place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. this is particularly important for the small-value ceramic capacitors. surface-mount components are recommended to avoid the higher inductance of leaded components. figure 60 to figure 62 illustrate basic connections and interfaces that can be used with the ads1271.
sbas306a ? november 2004 ? revised december 2004 www.ti.com 26 tie to either dvdd or gnd +5v differential inputs 50 ? 50 ? 50 ? 50 ? 50 ? 100 ? +5v + + 50 ? 10 f 10 f0.1 f 0.1 f 0.1 f + 0.1 f 100pf 100pf 10 f +5v 1nf 100 f 0.1 f 0.1 f 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 vrefp vrefn dgnd dvdd clk sclk drdy/ fsync dout ainp ainn agnd avdd mode format sync/ pdwn din ads1271 27mhz clock source ref3125 100 ? 1k ? 1k ? 10nf opa350 1.8v to 3.3v (1) note: (1) 1.8v recommended. figure 60. basic connection drawing +15v (1) note: (1) bypass with 10 f and 0.1 f capacitors. ? 15v (1) v ref v in 49.9 ? ainp opa1632 ainn v ocm 0.1 f 1k ? 1k ? 1k ? 1k ? 49.9 ? 1000pf 1000pf figure 61. basic differential signal interface +15v (1) note: (1) bypass with 10 fand0.1 f capacitors. ? 15v (1) v ref v in opa1632 49.9 ? ainp ainn v odiff =10 v in v ocomm =v ref v ocm 0.1 f 10k ? 1k ? 10k ? 1k ? 49.9 ? 1000pf 1000pf figure 62. basic single-ended signal interface
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ADS1271IPW active tssop pw 16 94 none cu level-2-240c-1 year ADS1271IPWr active tssop pw 16 2500 none cu level-2-240c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - may not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. none: not yet available lead (pb-free). pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean "pb-free" and in addition, uses package materials that do not contain halogens, including bromine (br) or antimony (sb) above 0.1% of total product weight. (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedecindustry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 27-dec-2004 addendum-page 1
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2004, texas instruments incorporated

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