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EM42CM1684RTA jan. 2012 www.eorex.com 1/22 revision history revision 0.1 (jan. 2012) - first release.
EM42CM1684RTA jan. 2012 www.eorex.com 2/22 1gb (16m 4bank 16) double data rate sdram features ? internal double-date-rate architecture with twice accesses per clock cycle. ? single 2.5v 0.2v power supply ? 2.5v sstl-2 compatible i/o ? burst length (b/l) of 2, 4, 8 ? cas latency: 3 ? bi-directional data strobe (dqs) for input and output data, active by both edges ? data mask (dm) for write data ? sequential & interleaved burst type available ? auto precharge option for each burst accesses ? dqs edge-aligned with data for read cycles ? dqs center-aligned with data for write cycles ? dll aligns dq & dqs transitions with clk transition ? auto refresh and self refresh ? 8,192 refresh cycles / 64ms description the EM42CM1684RTA is high speed synchronous graphic ram fabricated with ultra high performance cmos process containing 1,073,741,824 bits which organized as 16meg words x 4 banks by 16 bits. the 1gb ddr sdram uses double data rate architecture to accomplish high-speed operation. the data path internally prefetches multiple bits and transfers the data for both rising and falling edges of the system clock. it means the doubled data bandwidth can be achieved at the i/o pins. available package: tsopii 66p 400mil. ordering information part no organization max. freq package grade pb EM42CM1684RTA-75f 64m x 16 133mhz @cl3-3-3 66pin tsop(ll) commercial free EM42CM1684RTA-6f 64m x 16 166mhz @cl3-3-3 66pin tsop(ll) commercial free * eorex reserves the right to change products or specification without notice.
EM42CM1684RTA jan. 2012 www.eorex.com 3/22 pin assignment 66pin tsop-ii
EM42CM1684RTA jan. 2012 www.eorex.com 4/22 pin description (simplified) pin name function 45,46 clk,/clk (system clock) clock input active on the positive rising edge except for dq and dm are active on both edge of the dqs. clk and /clk are differential clock inputs. 24 /cs (chip select) /cs enables the command decoder when?l? and disable the command decoder when ?h?. the new command are over- looked when the command decoder is disabled but previous operation will still continue. 44 cke (clock enable) activates the clk when ?h? and deactivates when ?l?. when deactivate the clock, cke low signifies the power down or self refresh mode. 29~32,35~40 ,28,41,42,17 a0~a13 (address) row address (a0 to a13) and column address (ca0 to ca9) are multiplexed on the same pin. ca10 defines auto prechar ge at column address. 26, 27 ba0, ba1 (bank address) selects which bank is to be active. 23 /ras (row address strobe) latches row addresses on the posit ive rising edge of the clk with /ras ?l?. enables row access & pre-charge. 22 /cas (column address strobe) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 21 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. 16/51 ldqs/udqs (data input/output) data inputs and outputs are synchronized with both edge of dqs. 20/47 ldm/udm (data input/output mask) dm controls data inputs. ldm corresponds to the data on dq0~dq7.udm corresponds to the data on dq8~dq15. 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 dq0~dq15 (data input/output) data inputs and outputs are multiplexed on the same pin. 1,18,33/ 34,48,66 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for internal circuits. 3, 9, 15, 55.61/ 6, 12, 52, 58,64 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. 14,19,25,43, 50,53 nc/rfu (no connection/reserved for future use) this pin is recommended to be left no connection on the device. 49 v ref (input) sstl-2 reference voltage for input buffer.
EM42CM1684RTA jan. 2012 www.eorex.com 5/22 absolute maximum rating symbol item rating units v in , v out input, output (i/o) voltage -0.5 ~ v ddq + 0.5 v v in input voltage -1.0 ~ +3.6 v dd , v ddq power supply voltage -1.0 ~ +3.6 v t op operating temperature range commercial 0 ~ +70 c t stg storage temperature range -55 ~ +150 c p d power dissipation 1.6 w i os short circuit current 50 ma note: caution exposing the device to stress above th ose listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a =-0c ~+70c) symbol parameter min. typ. max. units v dd power supply voltage 2.3 2.5 2.7 v v ddq power supply voltage (for i/o buffer) 2.3 2.5 2.7 v v ref i/o logic high voltage 0.49*v ddq 0.5*v ddq 0.51*v ddq v v tt i/o termination voltage v ref -0.04 - v ref +0.04 v v ih input logic high voltage v ref +0.15 - v ddq +0.3 v v il input logic low voltage -0.3 - v ref -0.15 v
EM42CM1684RTA jan. 2012 www.eorex.com 6/22 recommended dc operating conditions (v dd =2.5v 0.2v) max. symbol parameter test conditions -6 -75 units i dd1 operating current (note 1) burst length=2, t rc t rc (min.), i ol =0ma, one bank active 195 180 ma i dd2p precharge standby current in power down mode cke v il (max.), t ck =min 15 15 ma i dd2n precharge standby current in non-power down mode (all banks idle) cke v ih (min.), t ck =min, /cs v ih (min.), v in =v ref input signals are changed once per clock cycle 65 60 ma i dd3p active standby current in power down mode cke v il (max.), t ck =min one bank active, v in =v ref 35 30 ma i dd3n active standby current in non-power down mode cke v ih (min.), t ck =min, /cs v ih (min.) input signals are changed once per clock cycle 65 65 ma read 220 200 i dd4 operating current (note 2) t ck t ck (min.), i ol =0ma, one banks active, bl=2 write 230 210 ma i dd5 refresh current (note 3) t rc t rfc (min.), all banks active 340 330 ma i dd6 self refresh current cke 0.2v 9 9 ma i dd7 operating current (four banks) four banks interleaving, bl=4 525 485 ma *all voltages referenced to v ss . note 1: i dd1 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 2: i dd4 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 3: min. of t rfc (auto refresh row cycle times) is shown at ac characteristics. recommended dc operating conditions (continued) symbol parameter test conditions min. max. units i il input leakage current 0 v i v ddq , v ddq =v dd all other pins not under test=0v -2 +2 ua i ol output leakage current 0 v o v ddq , d out is disabled -5 +5 ua v oh high level output voltage i out = -16.8ma 1.95 - ma v ol low level output voltage i out = +16.8ma - 0.35 ma
EM42CM1684RTA jan. 2012 www.eorex.com 7/22 block diagram row add. buffer row decoder address register auto/ self refresh counter memory array s/ a & i/ o gating col. decoder col. add. buffer mode register set col add. counter burst counter write dqm control data in data out doi a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 timing register ck cke /cs / ras / cas /we dm dm /ck dqs
EM42CM1684RTA jan. 2012 www.eorex.com 8/22 ac operating test conditions 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specif ications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. refer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of t he signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (b elow) the dc input low (high) level. ac input operating conditions symbol parameter min. typ. max. units v ih (ac) input (dq,dqs &dm) high voltage v ref +0.31 - - v v il (ac) input (dq,dqs &dm) low voltage - - v ref- 0.31 v v id (ac) input differential (ck & /ck) voltage 0.7 - v ddq +0.6 v v ix (ac) input crossing point (ck & /ck) 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v
EM42CM1684RTA jan. 2012 www.eorex.com 9/22 ac operating test characteristics (v dd =2.5v 0.2v) -6 -75 symbol parameter min. max. min. max. units t dqck dq output access from clk,/c lk -0.7 0.7 -0.75 0.75 ns t dqsck dqs output access from clk,/clk -0.6 0.6 -0.75 0.75 ns t cl ,t ch cl low/high level width 0.45 0.55 0.45 0.55 t ck t ck clock cycle time cl=3 6 12 7.5 12 ns t dh ,t ds dq and dm hold/setup time 0.45 - 0.5 - ns t dipw dq and dm input pulse width for each input 1.75 - 1.75 - ns t hz ,t lz data out high/low impedance time from clk,/clk -0.7 0.7 -0.75 0.75 ns t dqsq dqs-dq skew for associated dq signal - 0.4 - 0.5 ns t dqss write command to first latching dqs transition 0.75 1.25 0.75 1.25 t ck t dsl ,t dsh dqs input valid window 0.35 - 0.35 - t ck t mrd mode register set command cycle time 2 - 2 - t ck t wpres write preamble setup time 0 - 0 - ns t wpst write postamble 0.4 0.6 0.4 0.6 t ck address/control input hold/set up time (slow) 0.8 - 1 - ns t ih ,t is address/control input hold/set up time (fast) 0.75 - 0.9 - ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck t dsh dqs falling edge from clk rising, hold time 0.2 - 0.2 - t ck t dss dqs falling edge to clk rising, setup time 0.2 - 0.2 - t ck
EM42CM1684RTA jan. 2012 www.eorex.com 10/22 ac operating test characteristics (continued) (v dd =2.5v 0.2v) -6 -75 symbol parameter min. max. min. max. units t rpst read postamble 0.4 0.6 0.4 0.6 t ck t ras active to precharge command period 42 70k 45 120k ns t rc active to active command period 60 - 65 - ns t rfc auto refresh row cycle time 72 - 75 - ns t rcd active to read or write delay 18 - 20 - ns t rp precharge command period 18 - 20 - ns t rrd active bank a to b command period 12 - 15 - ns t rap active to read with auto precharge command 18 - 20 - ns t wpre dqs write preamble 0.25 - 0.25 - t ck t wr write recovery time 15 - 15 - ns t wtr internal write to read command delay 1 - 1 - t ck t xsnr exit self refresh to non-read command 75 - 75 - ns t xsrd exit self refresh to read command 200 - 200 - t ck t refi average periodic refresh interval - 7.8 - 7.8 us
EM42CM1684RTA jan. 2012 www.eorex.com 11/22 simplified state diagram
EM42CM1684RTA jan. 2012 www.eorex.com 12/22 1. command truth table cke command symbol n- 1 n /cs /ras /cas /we ba0, ba1 a10 a12~a0 ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre-charge read a h x l h l h v h v write writ h x l h l l v l v write with auto pre-charge writa h x l h l l v h v bank activate act h x l l h h v v v pre-charge select bank pre h x l l h l v l x pre-charge all banks pall h x l l h l x h x mode register set mrs h x l l l l op code extended mrs emrs h x l l l l op code h = high level, l = low level, x = high or low level (don't care), v = valid data input 2. cke truth table cke item command symbol n-1 n /cs /ras /cas /we addr. idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x - l h l h h h x self refresh self refresh exit - l h h x x x x idle power down entry - h l x x x x x power down power down exit - l h x x x x x h = high level, l = low level, x = high or low level (don't care)
EM42CM1684RTA jan. 2012 www.eorex.com 13/22 3. operative command table current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h h l x term nop l h l x ba/ca/a10 read/writ/bw illegal (note 1) idle l l h h ba/ra act bank active,latch ra l l h l ba, a10 pre/prea nop (note 3) l l l h x refa auto refresh (note 4) l l l l op-code, mode-add mrs mode register h x x x x desl nop l h h h x nop nop l h h l ba/ca/a10 read/reada begin read,latch ca, determine auto-precharge l h l l ba/ca/a10 writ/writa begin write,latch ca, determine auto-precharge row active l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea precharge/precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop no p(continue burst to end) l h h l x term terminal burst read l h l h ba/ca/a10 read/reada terminate burst,latch ca, begin new read, determine auto-precharge l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea terminate burst, prechare l l l h x refa illegal l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop no p(continue burst to end) l h h l x term illegal l h l h ba/ca/a10 read/reada terminate burst with dm=?h?,latch ca,begin read,determine auto-precharge (note 2) l h l l ba/ca/a10 writ/writa terminate burst,latch ca,begin new write, determine auto-precharge (note 2) l l h h ba/ra act illegal (note 1) l l h l ba, a10 pre/prea terminate burst with dm=?h?, precharge l l l h x refa illegal write l l l l op-code, mrs illegal
EM42CM1684RTA jan. 2012 www.eorex.com 14/22 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba/ca/a10 term illegal l h l x ba/ra read/write illegal (note 1) l l h h ba/a10 act illegal (note 1) l l h l x pre/prea illegal (note 1) l l l h x refa illegal read with ap l l l l op-code, mode-add mrs illegal h x x x x desl nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x term illegal l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal write with ap l l l l op-code, mode-add mrs illegal h x x x x desl nop(idle after t rp ) l h h h x nop nop(idle after t rp ) l h h l x term nop l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea nop(idle after t rp ) (note 3) l l l h x refa illegal pre-charging l l l l op-code, mode-add mrs illegal h x x x x desl nop(row active after t rcd ) l h h h x nop nop(row active after t rcd ) l h h l x term nop l h l x ba/ca/a10 read/write illegal (note 1) l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal row activating l l l l op-code, mode-add mrs illegal h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge
EM42CM1684RTA jan. 2012 www.eorex.com 15/22 3. operative command table (continued) current state /cs /r /c /w addr. command action h x x x x desl nop l h h h x nop nop l h h l x term nop l h l h ba/ca/a10 read illegal (note 1) write l h l l ba/ca/a10 writ/writa new write, determine ap l l h h ba/ra act illegal (note 1) l l h l ba/a10 pre/prea illegal (note 1) l l l h x refa illegal recovering l l l l op-code, mode-add mrs illegal h x x x x desl nop(idle after t rp ) l h h h x nop nop(idle after t rp ) l h h l x term nop l h l x ba/ca/a10 read/writ illegal l l h h ba/ra act illegal l l h l ba/a10 pre/prea nop(idle after t rp ) l l l h x refa illegal refreshing l l l l op-code, mode-add mrs illegal h = high level, l = low level, x = high or low level (don't care), ap = auto pre-charge note 1: illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. note 2: must satisfy bus contention, bus turn ar ound, and/or write recovery requirements. note 3: nop to bank precharging or in idle state.may precharge bank indicated by ba. note 4: illegal of any bank is not idle.
EM42CM1684RTA jan. 2012 www.eorex.com 16/22 4. command truth table for cke cke current state n-1 n /cs /r /c /w addr. action h x x x x x x invalid l h h x x x x exist self-refresh l h l h h h x exist self-refresh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop(maintain self refresh) h x x x x x x invalid l h h x x x x exist power down l h l h h h x exist power down l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal both bank precharge power down l l x x x x x nop(maintain power down) h h x x x x x refer to function true table h l h x x x x enter power down mode (note 3) h l l h h h x enter power down mode (note 3) h l l h h l x illegal h l l h l x x illegal h l l l h h ra row active/bank active h l l l l h x enter self-refresh (note 3) h l l l l l op-code mode register access h l l l l l op-code special mode register access all banks idle l x x x x x x refer to current state any state other than listed above h h x x x x x refer to command truth table h = high level, l = low level, x = high or low level (don't care) notes 1: after cke?s low to high transition to exist self refresh mode. and a time of t rc (min) has to be elapse after cke?s low to high transition to issue a new command. notes 2: cke low to high transition is asynchronous as if restarts internal clock. notes 3: power down and self refresh can be enter ed only from the idle state of all banks.
EM42CM1684RTA jan. 2012 www.eorex.com 17/22 the sequence of power-up and initialization the following sequence is required for power-up and initialization. 1. apply power and attempt to maintain cke at a low state (all other inputs may be undefined.) - apply vdd before or at the same time as vddq. - apply vddq before or at the same time as vtt & vref. 2. start clock and maintain stable condition for a minimum of 200us. 3. the minimum of 200us after stable power and clock (clk, clk), apply nop & take cke high. 4. precharge all banks. 5. issue emrs to enable dll.(to issue ?dll enabl e? command, provide ?low? to a0, ?high? to ba0 and ?low? to all of the rest address pins, a1~a11 and ba1) 6. issue a mode register set command for ?dll reset?. the additional 200 cycles of clock input is required to lock the dll. (to issue dll reset command, provide ?high? to a8 and ?low? to ba0) 7. issue precharge commands for all banks of the device. 8. issue 2 or more auto-refresh commands. 9. issue a mode register set command to initialize device operation. note1 every ?dll enable? command resets d ll. therefore sequence 6 can be skipped during power up. instead of it, the additional 200 cycles of clock input is required to lock the dll after enabling dll.
EM42CM1684RTA jan. 2012 www.eorex.com 18/22 mode register definition mode register set the mode register stores the data for controlling the various operating m odes of ddr sdram which contains addressing mode, burst length, /cas latency, test mode, dll reset and various vendor?s specific opinions. the defaults value of the register is not def ined, so the mode register must be written after emrs setting for proper ddr sdram operation. the mode regist er is written by asserting low on /cs, /ras, /cas, /we and ba0 ( the ddr sdram should be in all bank precharge with cke already high prior to writing into the mode register. ) the state of the addr ess pins a0-a12 in the same cycle as /cs, /ras, /cas, /we and ba0 going low is written in the mode regi ster. two clock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. the mode register is divided into various fields dependi ng on functionality. the burst length uses a0-a2, addressing mode uses a3, /cas latency (read latency fr om column address) uses a4-a6. a7 is used for test mode. a8 is used for ddr reset. a7 mu st be set to low for normal mrs operation.
EM42CM1684RTA jan. 2012 www.eorex.com 19/22 address input for mode register set bust length bt cas latency tm dll rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 1 1 reserve 0 1 1 reserve 1 0 1 reserve 0 0 1 reserve 1 1 0 3 0 1 0 reserved 1 0 0 reserved 0 0 0 reserved a4 a5 a6 cas latency 1 interleave 0 sequential a3 burst type 1 1 1 reserve 0 1 1 reserve 1 0 1 reserve 0 0 1 reserve 1 1 0 8 0 1 0 4 1 0 0 2 0 0 0 reserve a0 a1 a2 burst latency 1 yes 0 no a8 dll rest 1 test 0 normal a7 mode 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use bust length bt cas latency tm dll rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 1 1 reserve 0 1 1 reserve 1 0 1 reserve 0 0 1 reserve 1 1 0 3 0 1 0 reserved 1 0 0 reserved 0 0 0 reserved a4 a5 a6 cas latency 1 interleave 0 sequential a3 burst type 1 1 1 reserve 0 1 1 reserve 1 0 1 reserve 0 0 1 reserve 1 1 0 8 0 1 0 4 1 0 0 2 0 0 0 reserve a0 a1 a2 burst latency 1 yes 0 no a8 dll rest 1 test 0 normal a7 mode 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use
EM42CM1684RTA jan. 2012 www.eorex.com 20/22 burst type (a3) burst length a2 a1 a0 sequential addressing interleave addressing x x 0 0 1 0 1 2 x x 0 1 0 1 0 x 0 0 0 1 2 3 0 1 2 3 x 0 1 1 2 3 0 1 0 3 2 x 1 0 2 3 0 1 2 3 0 1 4 x 1 1 3 0 1 2 3 2 1 0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 *page length is a function of i/o organization and column addressing dll enable / disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disable the dll for the purpose of debug or evaluation ( upon existing self refresh mode, the dll is enable automatically. ) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. output drive strength the normal drive strength got all outputs is specified to be sstl-2, class ii. some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments.
EM42CM1684RTA jan. 2012 www.eorex.com 21/22 extended mode register set ( emrs ) the extended mode register stores the data enabling or disabling dll. the value of the extended mode register is not defined, so the extended mode regist er must be written after power up for enabling or disabling dll. the extended mode register is writt en by asserting low on /cs, /ras, /cas, /we and high on ba0 ( the ddr sdram should be in all bank prechar ge with cke already prior to writing into the extended mode register. ) the state of address pins a0 -a10 and ba1 in the same cycle as /cs, /ras, /cas, and /we going low is written in the extended m ode register. the mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll enable or disa ble. high on ba0 is used for emrs. all the other address pins except a0 and ba0 must be set to low for proper emrs operation. dll i/o 0 rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 half 0 full a1 i/o strength 1 disable 0 enable a0 dll enable 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use must be set to ?0? dll i/o 0 rfu* mrs 0 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 ba0 ba1 1 half 0 full a1 i/o strength 1 disable 0 enable a0 dll enable 1 emrs 0 mrs cycle ba0 an ~ a0 *rfu: reserved for future use must be set to ?0?
EM42CM1684RTA jan. 2012 www.eorex.com 22/22 package description 66-pin plastic tsop-ii (400mil) 0.010 - 0.005 0.25 - 0.12 r2 - - 0.005 - - 0.12 r1 0.026bsc 0.65bsc 0.031ref 0.80ref l1 0.024 0.020 0.016 0.60 0.50 0.40 l 0.400bsc 10.16bsc e1 0.463bsc 11.76bsc e 0.028ref 0.71ref zd 0.875bsc 22.22bsc d 0.006 0.005 0.004 0.16 0.127 0.10 c1 0.008 - 0.005 0.21 - 0.12 c 0.013 0.012 0.009 0.33 0.30 0.22 b1 0.015 - 0.009 0.38 - 0.22 b 0.041 0.039 0.037 1.05 1.00 0.95 a2 0.006 0.004 0.002 0.15 0.10 0.05 a1 0.047 - - 1.2 - - a max nom min max nom min dimension(inch) dimension(mm) symbol 20 15 10 3 20 15 10 2 - - 0 1 8 - 0 max nom min symbol 0.010 - 0.005 0.25 - 0.12 r2 - - 0.005 - - 0.12 r1 0.026bsc 0.65bsc 0.031ref 0.80ref l1 0.024 0.020 0.016 0.60 0.50 0.40 l 0.400bsc 10.16bsc e1 0.463bsc 11.76bsc e 0.028ref 0.71ref zd 0.875bsc 22.22bsc d 0.006 0.005 0.004 0.16 0.127 0.10 c1 0.008 - 0.005 0.21 - 0.12 c 0.013 0.012 0.009 0.33 0.30 0.22 b1 0.015 - 0.009 0.38 - 0.22 b 0.041 0.039 0.037 1.05 1.00 0.95 a2 0.006 0.004 0.002 0.15 0.10 0.05 a1 0.047 - - 1.2 - - a max nom min max nom min dimension(inch) dimension(mm) symbol 20 15 10 3 20 15 10 2 - - 0 1 8 - 0 max nom min symbol

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