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s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 1 / 1 1 v e r 1 . 0 ( m a r . 1 9 9 9 ) no responsibility is assumed by sec for its use nor for any infringements of patents or other rights of third parties that may result from its use. the content of this datasheet is subject to change without any notice. g e n e r a l d e s c r i p t i o n the bw1221l_3clk is a cmos triple 10bit d/a converter for general & video applications. its typical conversion rate is 30msps (maximum 50msps) and supply voltage is 3.3v single. an external 1.0v voltage reference(vref) and a single resistor (rset) control the full_scale output current. f e a t u r e s . 30msps 1clk pipeline delay operation . +3.3v cmos monolothic construction . 1.0lsb differential linearity error(max) . 2.5lsb integral linearity error(max) . external voltage reference . triple channel dac . 10-bit voltage parallel input per channel . high impedance single current output . bineary coding input . high impedance analog output current source f u n c t i o n a l b l o c k d i a g r a m t y p i c a l a p p l i c a t i o n s . high definition television(dtv,hdtv) . high resolution color graphics . hard disk driver(hdd) . cae/cad/cam . image processing . instrumentation . conventional digital to analog conversion clkgen opa cm d2[9:0] clk1 vref iref pd io2 io3 f i r s t l a t c h 2 f i r s t l a t c h 3 d e c o e d e r 2 d e c o e d e r 3 s e c o n d l a t c h 3 s e c o n d l a t c h 2 s w i t c h 2 comp d3[9:0] s w i t c h 3 f i r s t l a t c h 1 d e c o e d e r 1 s e c o n d l a t c h 1 s w i t c h 1 io1 d1[9:0] clk2 clk3
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 2 / 1 1 n a m e i / o t y p e i / o p a d p i n d e s c r i p t i o n d1[9:0] di picc_bb 1st channel digital input d2[9:0] di picc_bb 2nd channel digital input d3[9:0] di picc_bb 3rd channel digital input io1 ao poa_bb 1st channel current output io2 ao poa_bb 2nd channel current output io3 ao poa_bb 3rd channel current output clk1 di picc_bb clock input for first channel clk2 di picc_bb clock input for second channel clk3 di picc_bb clock input for third channel vref ai pia_bb reference voltage input comp ai pia_bb external capacitance connection pd di picc_bb power-down high enable iref ai pia_bb external resistor connection vdda ap vdda analog power vddd dp vddd digital power vssa ag vssa analog ground vssd dg vssd digital ground vbb ag vbba bulk bias i / o t y p e a b b r . - ai : analog input - di : digital input - ao : analog output - do : analog output - ap : analog power - dp : digital power - ag : analog ground - dg : digital ground - ab : analog bidirection - db : digital bidirection c o r e c o n f i g u r a t i o n b w 1 2 2 1 l _ 3 c l k io2 io1 vdda vddd vssa vssd vbb clk3 pd iref vref comp d 2 [ 9 : 0 ] d 1 [ 9 : 0 ] d 3 [ 9 : 0 ] io3 clk2 clk1 external pad when it's been embedded interrnal pad when it's been embedded note
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 3 / 1 1 c h a r a c t e r i s t i c s s y m b o l v a l u e s u n i t supply voltage vdda vddd 5 v voltage on any digital voltage vin vssd-0.3 to vddd+0.3 v storage temperature range tstg -45 to 125 c c h a r a c t e r i s t i c s s y m b o l m i n t y p m a x u n i t operating supply voltage vdda,vddd 3.15 3.3 3.45 v digital input voltage high low v i h v i l 0.7vddd - 3.3 0.0 - 0.3vddd v operating temperature range t o p r 0 25 70 c output load(effective) r l - 249 - w data input setup time t s - 2 - ns data input hold time t h - 2 - ns clock cycle time t c l k 20 33 - ns clock pulse width high t p w h 10 16 - ns clock pulse width low t p w l 10 16 - ns iref current i r e f - 0.33 - ma zero_level voltage v o z -5.0 -1.2 5.0 mv external reference voltage v r e f - 1.0 - v note: * it is strongly recommended that to avoid power latch-up all the supply p i n s ( v d d a , v d d d ) be driven from the same source, and all ground pins( v s s a , v s s d , v b b ) be driven from the same source. * absolute maximum rating values should be applied individually while all other parameters are within specified operating conditions. function operation under any of these conditions is not implied. * applied voltage must be limited to specified range. * absolute maximum ratings are values beyond which the device may be damaged permanently. normal operation is not guaranteed. a b s o l u t e m a x i m u m r a t i n g s r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s note: - it is strongly recommended that all the supply p i n s ( v d d a , v d d d ) should be driven from the same source to avoid power latch-up. - all data above could be available with less than 10pf parasitic load capacitance at io1,io2 and io3 node.
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 4 / 1 1 c h a r a c t e r i s t i c s s y m b o l m i n t y p m a x u n i t resolution - - 10 - bits differential linearity error dle - 0.6 1.0 lsb integral linearity error ile - 1.8 2.5 lsb full scale current per channel i f s - 4.9 - ma monotonicity - - guaranteed - - lsb size - - 4.9 - ua maximum output compliance v o c -0.5 0.0 0.0 v exteranl refence voltage - - 1.0 - v power supply current i s - 16 - ma c h a r a c t e r i s t i c s s y m b o l m i n t y p m a x u n i t conversion speed f m a x - 30 50 mhz analog output delay t d - 11 20 ns analog output rising time t r - - 2 ns analog output falling time t f - - 2 ns analog output settling time t s e t - 100 150 ns glitch impulse gi - 120 200 pvsec pipeline delay t o p - 1 - clock power supply rejection ratio (f=5.8khz, comp=0.1uf) pss - 0.0 0.5 % feedthrough fdth - -33 -28 db power_down on time t p n - 4 6 ms power_down off time t p f - 0.1 0.3 ms d c e l e c t r i c a l c h a r a c t e r i s t i c s notes * converter specifications (unless otherwise specified) vdda=3.3v vddd=3.3v v s s a = v s s d = v b b = g n d ta=25 c r l 1 =r l 2 =r l 3 =249 w , v r e f =1.0v, r s e t = 3k w *. tbd : to be determined a c e l e c t r i c a l c h a r a c t e r i s t i c s note: - the above pararameters are not tested through the temperature range. - clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs .settling time does not include clock and data feedthrough . glitch impulse include clock and data feedthrough.
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 5 / 1 1 f u n c t i o n a l d e s c r i p t i o n this is triple 10bit 30msps digital to analog data converter and uses segment architecture for 5bits of msb sides and binerary-weighted architecture for 5 bits of lsb side. it contains of 1st latch block, decoder block, 2nd latch block, opa block, cm( current mirror)block and analog switch block. this core uses reference current to decide the 1lsb current size by dividing the reference current by 68times. so the reference current must be constant and the reference curretn of cm can be constant by using opa block with high dc gain. the most significant block of this core is analog switch block and it must maintain the uniformity at each switch, so layout designer must care of the matching characteristic on analog switch and cm block. and more than 80% of supply current is dissipated at analog switch block and opa block. and it uses samsung(sec) standard cell as all digital cell of latch,decoder and buffer. and to adjust full current output, you must decide the "rset" resistor value(connected to iref pin) and " vbias" voltage value(connected to vref pin). its voltage output can be obtained by connecting r l 1 ( connected to io1 pin), r l 2 (connected to io2 pin) and r l 3 (connected to io3 pin). its maximum output voltage limit is 1.2v. so you must decide the r l 1 , r l 2 . and r l 3 , vbias and rset carefully not vout(p-p) to exceed 1.2v. it contains pd pin for power-save but regretfuly it isn't complete. if you want more complete power-save mode, call back us(sec). we can provide you more complete power-save mode control scheme.
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 6 / 1 1 t i m i n g d i a g r a m notes: - the behavioral modeling is provided by verilog hdl modeling file which includes the spec of pipeline delay, setup_time, hold_time, rising time, falling time, and clock frequency, and so on. - output delay(t d ) measured from the 50% point of the rising edge of clk to the full scale trasition - settling time(t s e t ) measured from the 50% point of full scale transition to the output remaining within 1lsb. - output rising(t r )/falling(t f ) time measured between the 10% and 90% points of full scale transition. - power_down doesn't need clock signal. io clk d[9:0] 1 clocks pipeline delay d a t a ( 1 1 1 1 1 1 1 1 1 1 ) 0 0 0 0 0 0 0 0 0 0 t r t s t p w h t p w l 0 0 0 0 0 0 0 0 0 0 t c l k t s e t t f t d high low vout(p-p) 0v clk t s t h t d d[9:0] data[2] data[3] data[1] io vout[2] vout[1] clk d[9:0] d a t a 1 ( 1 1 1 1 1 1 1 1 1 1 ) io pd t p n t p f 0v vout(pp)
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 7 / 1 1 c o r e e v a l u a t i o n g u i d e l o c a t i o n d e s c r i p t i o n c c o m p ,cc 0.1 m f ceramic capacitor ct 10 m ftantalum capacitor r s e t 3k w r l 1 249 w r l 2 249 w r l 3 249 w v r e f 1.0v dc voltage supply path select b w 1 2 2 1 l _ 3 c l k test path h o s t d s p c o r e 1 0 io2 io3 r l 3 channel select r l 2 v d d d v s s d v d d a v s s a v b b 3 . 3 v c t + l 1 c t + 3 . 3 v l 2 c c c c 1.0v v r e f clk1 input c l k 1 p d r s e t i r e f c o m p c c o m p vdda c l k 2 clk2 input c l k 3 clk3 input d 1 [ 9 ] d 1 [ 8 ] d 1 [ 7 ] d 1 [ 6 ] d 1 [ 5 ] d 1 [ 4 ] d 1 [ 3 ] d 1 [ 2 ] d 1 [ 1 ] d 1 [ 0 ] d 2 [ 9 ] d 2 [ 8 ] d 2 [ 7 ] d 2 [ 6 ] d 2 [ 5 ] d 2 [ 4 ] d 2 [ 3 ] d 2 [ 2 ] d 2 [ 1 ] d 2 [ 0 ] d 3 [ 9 ] d 3 [ 8 ] d 3 [ 7 ] d 3 [ 6 ] d 3 [ 5 ] d 3 [ 4 ] d 3 [ 3 ] d 3 [ 2 ] d 3 [ 1 ] d 3 [ 0 ] io1 r l 1 1 0 1 0 1 0 2
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 8 / 1 1 * h o w t o c h a n g e t h e r e s o l u t i o n if it is needed to change the resolution, you can use as many as more significant bits, and the rest (less significant bits) can be grounded or supplied by vddd power. that is, if you need only 8bits, you have to use msb 8bit digital input pin, and the lsb 2 digital input pin have to be grounded or supplied by vddd power. * h o w t o c h a n g e t h e o u t p u t r a n g e you can change the output swing using the following equation: v o u t = { v r e f / ( r s e t * 6 8 ) } * 1 0 2 3 * r l this equation implies that you can determine the output swing by changing the value of vref, r s e t , and r l where the output swing is limited up to 1.2v. 1. about t e s t a b i l i t y if you want to test it over full spec via all channel in main chip(that is, when it is used as a block of main chip) you must add many pins(for 30pins of digital inputs, 3pins of analog outputs, etc) at the main chip to test this dac block. but usually it is nearly impossble 'cause the total number of pins at main chip is limited. so more efficient method for testing this dac block is needed. we offer two ways of testing efficiently here as a reference. but remember this is not the best way. you can test it by your own testing method. 2. first method of t e s t a b i l i t y the first way is adding only extra 10pads for 10bit parallel digital inputs and 2pads for channel selecting and path selecting. you can check three channels one by one, that is you can test only one channel at one time. therefore you can test all three channels by turn but cannot check all channel at one time. and this method needs extra mux and switch blocks for testing. furthermore we can confirm all channels by testing only one channel because the three channels have same architecture and share the same analog reference block(opamp, cm, bgr). this characteristic makes it simple to test this dac block(when it is embedded in main chip) by adding another 10pads for parallel digital inputs and 2pads for selecting one channel analog switch block of dac out of three channels. 3. second method of t e s t a b i l i t y if above extra 12pads are burden on you, then you can test it by this second method to reduce the extra pads for testing. what is different from above method is that this way needs only 2 extra pads(one for 1bit serial digital input and the other for clock signal), but you must insert extra serial to parallel converter block for converting 1bit 10times high speed digital input to 10bit parallel digital inputs. and this block needs considerable area. further this method also needs extra 2pads for channel selecting and path selecting. 4 analysis the voltage applied to vref is measured at iref node . and the voltage value is proportioned to the reference current value of resistor which is connected to iref node. so you can estimate the full scale current value by measuring the voltage, and check the dc characteristics of the opamp. for reference, as v r e f voltage applied to vref pin is given at iref node, the current flowing through r s e t resistor(connected to iref pin) is given as v r e f /r s e t . if the voltage applied to vref pin is not same with iref node, you can say "this dac chip does not work p r o p e r l y " , because the internal opamp block makes the two node voltage(ifef pin, vref pin) equal. and you have to check the comp node to see the desired voltage on it. if the desired voltage is not measured, you can check the dac output by appling a desired voltage to the comp pin instead of compensation capacitor directly. if you use internal reference voltage(bgr's output voltage) instead of external vbias by setting the bgrsw low, you can check the bgr's output by checking the vref pin voltage.
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 9 / 1 1 c o r e l a y o u t g u i d e l a y o u t d a c c o r e r e p l a c e m e n t it is recommended that you use thick analog power metal. when connecting to pad, the path should be kept as short as possible, and use branch metal to connect to the center of analog switch block. it is recommended that you use thick analog output metal(at least more than 50um) when connecting to pad, and also the path length should be kept as short as possible. if the metal width is less than 50um, you should use double or triple pads. digital power and analog power are separately used. when it is connected to other blocks, it must be double shielded using n-well and p+ active to remove the substrate and coupling noise. in that case, the power metal should be connected to pad directly. bulk power is used to reduce the influence of substrate noise. you must use more than two pins for vdda because it requires much current dissipation.
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 10 / 1 1 - do you want to power down mode? - do you want to interal reference voltage(bgr)? - which do you want to serial input type or parallel input type? - do you need 3.3v and 5v power supply in your system? - how many channels do you n e e d ( b w 1 2 2 1 l _ 3 c l k is triple channel dac)? d c / a c e l e c t r i c a l c h a r a c t e r i s t i c c h a r a c t e r i s t i c s m i n t y p m a x u n i t r e m a r k s supply voltage v power dissipation mw resolution bits analog output voltage v operating temperature c output load capacitor mf output load resistor w integral non-linearity error lsb differential non-linearity error lsb maximum conversion rate mhz v o l t a g e o u t p u t d a c reference voltage top bottom v analog output voltage range v digital input format binary code or 2's complement code c u r r e n t o u t p u t d a c analog output maximum current ma analog output maximum signal frequency mhz reference voltage v external resistor for current setting(rset) w pipeline delay sec f e e d b a c k r e q u e s t we appreciate your interest in our products. if you have further questions, please specify in the attached form. thank you very much.
s e c a s i c b w 1 2 2 1 l _ 3 c l k 1 0 b i t 3 0 m s p s t r i p l e d a c a n a l o g 11 / 1 1 a n a l o g s i g n a l i n t e r c o n n e c t to minimized noise pickup and reflections due to impedance mismatch, the bw1221l_3clk should be located as close as possible to the output connector. the line between dac output and monitor input should also be regarded as a transmission line. due to the fact, it can cause problems in transmission line mismatch. as a solution to these problems, the double-termination methods used. by using this, both ends of the termination lines are matched, providing an ideal, non-reflective system. p c b o a r d l a y o u t c o n s i d e r a t i o n s p c b o a r d c o n s i d e r a t i o n s to minimize noise on the power lines and the ground lines, the digital inputs need to be shielded and decoupled. this trace length between groups of vdd ( v d d a , v d d d ) pins short as possible so as to minimize inductive ringing. s u p p l y d e c o u p l i n g a n d p l a n e s for the decoupling capacitor between the power line and the ground line, 0.1 m f ceramic capacitor is used in parallel with a 10 m f tantalum capacitor. the digital power plane(vddd) and analog power plane(vdda) are connected through a ferrite bead, and also the digital ground plane(vssd) and the analog ground plane(vssa). this ferrite bead should be located within 3inches of the bw1221l_3clk. the analog power plane supplies power to the bw1221l_3clk of the analog output pin and related devices.

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