preliminary ? 2001 fairchild semiconductor corporation ds500506 www.fairchildsemi.com november 2000 revised january 2001 fin1019 3.3v lvds high speed differential driver/receiver (preliminary) fin1019 3.3v lvds high speed differential driver/receiver (preliminary) general description this driver and receiver pair are designed for high speed interconnects utilizing low voltage differential signaling (lvds) technology. the driver translates lvttl signals to lvds levels with a typical differential output swing of 350mv and the receiver translates lvds signals, with a typical differential input threshold of 100mv, into lvttl levels. lvds technology provides low emi at ultra low power dissipation even at high frequencies. this device is ideal for high speed clock or data transfer. features greater than 400mbs data rate 3.3v power supply operation 0.5ns maximum differential pulse skew 2.5ns maximum propagation delay low power dissipation power off protection 100mv receiver input sensitivity fail safe protection open-circuit, shorted and terminated conditions meets or exceeds the tia/eia-644 lvds standard flow-through pinout simplifies pcb layout 14-lead soic and tssop packages save space ordering code: devices also available in tape and reel. specify by appending the suffix letter ?x? to the ordering code. function table h = high logic level l = low logic level x = don?t care z = high impedance fail safe = open, shorted, terminated connection diagram pin descriptions order number package number package description fin1019m m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow FIN1019MTC mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide inputs outputs ri + ri ? re ro lhl l hll h xxh z fail safe condition l h di de do + do ? lhlh hhhl xlzz open ? circuit or z h l h pin name description di lvttl data input do + non-inverting lvds output do ? inverting lvds output de driver enable (lvttl, active high) ri + non-inverting lvds input ri ? inverting lvds input ro lvttl receiver output re receiver enable (lvttl, active low) v cc power supply gnd ground
preliminary www.fairchildsemi.com 2 fin1019 absolute maximum ratings (note 1) recommended operating conditions note 1: the ? absolute maximum ratings ? : are those values beyond which damage to the device may occur. the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. fairchild does not recommend operation of circuits outside databook specification. dc electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified supply voltage (v cc ) ? 0.5v to + 4.6v lvttl dc input voltage (di, de, re ) ? 0.5v to + 6v lvds dc input voltage (ri + , ri ? ) ? 0.5v to 4.7v lvttl dc output voltage (ro) ? 0.5v to + 6v lvds dc output voltage (do + , do ? ) ? 0.5v to 4.7v lvds driver short circuit current (i osd ) continuous lvttl dc output current (i o )16 ma storage temperature range (t stg ) ? 65 c to + 150 c max junction temperature (t j ) 150 c lead temperature (t l ) (soldering, 10 seconds) 260 c esd (human body model) 2000v esd (machine model) 200v supply voltage (v cc ) 3.0v to 3.6v input voltage (v in ) 0 to v cc magnitude of differential voltage (|v id |) 100 mv to v cc common-mode input voltage (v ic ) 0.05v to 2.35v operating temperature (t a ) ? 40 c to + 85 c symbol parameter test conditions min typ max units (note 2) lvds differential driver characteristics v od output differential voltage 250 350 450 mv ? v od v od magnitude change from 25 mv differential low-to-high r l = 100 ? , see figure 1 v os offset voltage 1.125 1.25 1.375 v ? v os offset magnitude change from 25 mv differential low-to-high i ozd disabled output leakage current v out = v cc or gnd, de = 0v 20 a i off power off output current v cc = 0v, v out = 0v or 3.6v 20 a i os short circuit output current v out = 0v, de = v cc ? 8 ma v od = 0v, de = v cc 6 lvttl driver characteristics v oh output high voltage i oh = ? 100 a, re = 0v, v cc ? 0.2 v see figure 6 and table 1 i oh = ? 8 ma, re = 0v, v id = 400 mv 2.4 v id = 400 mv, v ic = 1.2v, see figure 6 v ol output low voltage i ol = 100 a, re = 0v, v id = ? 400 mv 0.2 v see figure 6 and table 1 i ol = ? 8 ma, re = 0v, v id = ? 400 mv 0.5 v id = ? 400 mv, v ic = 1.2v, see figure 6 i oz disabled output leakage current v out = v cc or gnd, re = v cc 20 a lvds receiver characteristics v th differential input threshold high see figure 6 and table 1 100 mv v tl differential input threshold low see figure 6 and table 1 ? 100 mv i in input current v in = 0v or v cc 20 a i i(off) power-off input current v cc = 0v, v in = 0v or 3.6v 20 a lvttl driver and control signals characteristics v ih input high voltage 2.0 v cc v v il input low voltage gnd 0.8 v i in input current v in = 0v or v cc 20 a i i(off) power-off input current v cc = 0v, v in = 0v or 3.6v 20 a v ik input clamp voltage i ik = ? 18 ma ? 1.5 v
preliminary 3 www.fairchildsemi.com fin1019 dc electrical characteristics (continued) note 2: all typical values are at t a = 25 c and with v cc = 3.3v. ac electrical characteristics over supply voltage and operating temperature ranges, unless otherwise specified note 3: all typical values are at t a = 25 c and with v cc = 5v. note 4: t sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either low-to-high or high-to-low) when both devices operate with the same supply voltage, same temperature, and have identica l test circuits. device characteristics i cc power supply current driver enabled, driver load: r l = 100 ? 14 ma receiver disabled, no receiver load driver enabled, driver load: rl = 100 ? , 20 ma receiver enabled, (ri + = 1v and ri ? = 1.4v) or (ri + = 1.4v and ro ? = 1v) driver disabled, receiver enabled, 13.5 ma (ri + = 1v and ri ? = 1.4v) or (ri + = 1.4v and ri ? = 1v) driver disabled, receiver disabled 9 ma c in input capacitance any lvttl or lvds input 3 pf c out output capacitance any lvttl or lvds output 5 pf symbol parameter test conditions min typ max units (note 3) driver timing characteristics t plhd differential propagation delay 0.5 1.5 ns low-to-high t phld differential propagation delay 0.5 1.5 ns high-to-low r l = 100 ? , c l = 10 pf, t tlhd differential output rise time (20% to 80%) see figure 2 and figure 3 0.4 1.0 ns t thld differential output fall time (80% to 20%) 0.4 1.0 ns t sk(p) pulse skew |t plh - t phl | 0.5 ns t sk(pp) part-to-part skew (note 4) 1.0 ns t zhd differential output enable time from z to high r l = 100 ? , c l = 10 pf, 5.0 ns t zld differential output enable time from z to low see figure 4 and figure 5 5.0 ns t hzd differential output disable time from high to z 5.0 ns t lzd differential output disable time from low to z 5.0 ns receiver timing characteristics t plh propagation delay low-to-high 1.0 2.5 ns t phl propagation delay high-to-low 1.0 2.5 ns t tlh output rise time (20% to 80%) |v id | = 400 mv, c l = 10 pf, 0.5 ns t thl output fall time (80% to 20%) see figure 6 and figure 7 0.5 ns t sk(p) pulse skew | t plh - t phl | 0.5 ns t sk(pp) part-to-part skew (note 4) 1.0 ns t zh lvttl output enable time from z to high 5.0 ns t zl lvttl output enable time from z to low r l = 500 ? , c l = 10 pf, 5.0 ns t hz lvttl output disable time from high to z see figure 8 5.0 ns t lz lvttl output disable time from low to z 5.0 ns
preliminary www.fairchildsemi.com 4 fin1019 figure 1. differential driver dc test circuit note a: input pulses have frequency = 10 mhz, t r or t f = 1 ns note b: c l includes all probe and jig capacitances figure 2. differential driver propagation delay and transition time test circuit figure 3. ac waveforms for differential driver note b: input pulses have the frequency = 10 mhz, t r or t f = 1 ns note a: c l includes all probe and jig capacitances figure 4. differential driver enable and disable test circuit figure 5. enable and disable ac waveforms
preliminary 5 www.fairchildsemi.com fin1019 note a: input pulses have frequency = 10 mhz, t r or t f = 1ns note b: c l includes all probe and jig capacitance figure 6. differential receiver voltage definitions and propagation delay and transition time test circuit table 1. receiver minimum and maximum input threshold test voltages applied voltages (v) resulting differential resulting common mode input voltage (mv) input voltage (v) v ia v ib v id v ic 1.25 1.15 100 1.2 1.15 1.25 ? 100 1.2 2.4 2.3 100 2.35 2.3 2.4 ? 100 2.35 0.1 0 100 0.05 00.1 ? 100 0.05 1.5 0.9 600 1.2 0.9 1.5 ? 600 1.2 2.4 1.8 600 2.1 1.8 2.4 ? 600 2.1 0.6 0 600 0.3 00.6 ? 600 0.3
preliminary www.fairchildsemi.com 6 fin1019 figure 7. lvds input to lvttl output ac waveforms test circuit for lvttl outputs voltage waveforms enable and disable times figure 8. lvttl outputs test circuit and ac waveforms
preliminary 7 www.fairchildsemi.com fin1019 physical dimensions inches (millimeters) unless otherwise noted 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150 narrow package number m14a
preliminary www.fairchildsemi.com 8 fin1019 3.3v lvds high speed differential driver/receiver (preliminary) physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc14 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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