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avago confidential afbr-810bxxxz and afbr-820bxxxz twelve-channel transmitter and receiver pluggable, parallel-fiber-optic modules data sheet description the afbr-810b twelve-channel, pluggable, parallel-fiber- optic transmitter and afbr-820b twelve-channel, pluggable, parallel-fiber-optic receiver are high per - formance fber optic modules for short-range parallel multi-lane data communication and interconnect ap - plications. these 12-channel devices are capable of 10.0 gbps per channel, 120 gbps raw aggregate operation. the modules are designed to operate over multimode fber systems using a nominal wavelength of 850 nm. the electrical interface uses a 10x10 meg-array ? low-profle mezzanine connector. the optical interface uses a mtp ? (mpo) 1x12 ribbon cable connector. the thermal interface can be a factory installed heatsink for air-cooled systems or thermal seating plane for user fexibility. the modules incorporate high performance, highly reliable, short wavelength optical devices coupled with proven circuit technology to provide long life and consistent service. applications ? high performance and high productivity computer interconnects ? infniband qdr sx interconnects ? datacom switch and router backplane connections ? telecom switch and router backplane connections part number ordering options transmitter part numbers afbr-810bz with fin heat sink / no emi nose clip afbr-810bez with fin heat sink / emi nose clip afbr-810bpz with pin heat sink / no emi nose clip AFBR-810BEPZ with pin heat sink / emi nose clip afbr-810bhz with no heat sink / no emi nose clip afbr-810behz with no heat sink/ emi nose clip receiver part numbers afbr-820bz with fin heat sink / no emi nose clip afbr-820bez with fin heat sink / emi nose clip afbr-820bpz with pin heat sink / no emi nose clip afbr-820bepz with pin heat sink / emi nose clip afbr-820bhz with no heat sink / no emi nose clip afbr-820behz with no heat sink/ emi nose clip features ? high channel capacity: 120 gbps per module ? high port density: 19 mm lateral port pitch; < 0.51 mm/ gbps for txCrx pair ? low power consumption per gbps: < 42 mw/gb/s for txCrx pair ? based on industry-standard, pluggable, snap12 form factor with upgraded pinout for improved signal integrity and keyed to prevent mis-plugging with frst generation snap12 devices ? twelve independent channels per module ? separate transmitter and receiver modules ? 850 nm vcsel array in transmitter; pin array in receiver ? operates up to 10 gbps with 8b/10b compatible coded data ? links up to 50 m at 10 gbps with 2000 mhz?km 50 um mmf ? two power supplies, 2.5 v and 3.3 v, for low power consumption ? dedicated signals for module address, module reset and host interrupt. ? two wire serial (tws) interface with maskable interrupt for expanded functionality including: C individual channel functions: disable, squelch disable, lane polarity inversion, margin C programmable equalization integrated with dc blocking caps at transmitter data input C programmable receiver output swing and de- emphasis level C a/d readback: module temperature and supply voltages, per channel laser current and laser power, or received power C status: per channel tx fault, electrical (transmitter) or optical (receiver) los, and alarm fags ? 0 to 70 c case temperature operating range patent - www.avagotech.com/patents
2 transmitter module the optical transmitter module (see figure 1) incorporates a 12-channel vcsel (vertical cavity surface emitting laser) array, a 12-channel input bufer and laser driver, diagnos - tic monitors, control and bias blocks. the transmitter is designed for iec-60825 and cdrh eye safety compliance; class 1m out of the module. the tx input bufer provides cml compatible diferential inputs (presenting a nominal diferential input impedance of 100 ohms and a nominal common mode impedance to signal ground of 25 ohms) for the high speed electrical interface that can operate over a wide common mode range without requiring dc blocking capacitors. for module control and interroga - tion, the control interface (lvttl compatible) incorpo - rates a two wire serial (tws) interface of clock and data signals and dedicated signals for host interrupt, module address setting and module reset. diagnostic monitors for vcsel bias, light output (lop), temperature, both supply voltages and elapsed operating time are implemented and results are available through the tws interface. over the tws interface, the user can, for individual channels, control (fip) polarity of the diferential inputs, de-activate channels, place channels into margin mode, figure 1. transmitter block diagram electrical interface optical interface din[11:0][p/n] (24) intl sda scl adr[2:0] (3) resetl vcc33 (4) vcc25 (2) gnd tx input bu?er 12 channels laser driver 12 channels control diagnostic monitors 1 x 12 vcsel array bias disable the squelch function and program input equaliza - tion levels to reduce the efect of long pcb traces. a reset for the control registers is available. serial id information and alarm thresholds are provided. to reduce the need for polling, the tws interface is augmented with an interrupt signal for the host. alarm thresholds are established for the monitored attributes. flags are set and interrupts generated when the attributes are outside the thresholds. flags are also set and interrupts generated for loss of input signal (los) and transmitter fault conditions. all fags are latched and will remain set even if the condition initiating the latch clears and operation resumes. all interrupts can be masked and fags are reset by reading the appropriate fag register. the optical output will squelch for loss of input signal unless squelch is disabled. fault detection or channel deactiva - tion through the tws interface will disable the channel. status, alarm and fault information are available via the tws interface. the interrupt signal (selectable via the tws interface as a pulse or static level) is provided to inform hosts of an assertion of an alarm, los and/or tx fault. avago confidential
3 receiver module the optical receiver module (see figure 2) incorporates a 12-channel pin photodiode array, a 12-channel pre- amplifer and output bufer, diagnostic monitors, control and bias blocks. the rx output bufer provides cml compatible diferential outputs for the high speed elec - trical interface presenting nominal single-ended output impedances of 50 ohms to ac ground and 100 ohms diferentially that should be diferentially terminated with 100 ohms. dc blocking capacitors may be required. for module control and interrogation, the control interface (lvttl compatible) incorporates a two wire serial (tws) interface of clock and data signals and dedicated signals for host interrupt, module address setting and module reset. diagnostic monitors for optical input power, tem - perature, both supply voltages and elapsed operating time are implemented and results are available through the tws interface. over the tws interface, the user can, for individual channels, control (fip) polarity of the diferential outputs, de-activate channels, disable the squelch function, program output signal amplitude and de-emphasis and change receiver bandwidth. a reset for the control registers is available. serial id information and alarm thresholds are provided. to reduce the need for polling, the tws interface is augmented with an interrupt signal for the host. alarm thresholds are established for the monitored at - tributes. flags are set and interrupts generated when the attributes are outside the thresholds. flags are also set and interrupts generated for loss of optical input signal (los). all fags are latched and will remain set even if the condition initiating the latch clears and operation resumes. all interrupts can be masked and fags are reset upon reading the appropriate fag register. the electri - cal output will squelch for loss of input signal (unless squelch is disabled) and channel de-activation through tws interface. status and alarm information are available via the tws interface. the interrupt signal (selectable via the tws interface as a pulse or static level) is provided to inform hosts of an assertion of an alarm and/or los. electrical interface optical interface dout[11:0][p/n] (24) intl sda scl adr[2:0] (3) resetl vcc33 (4) vcc25 (2) gnd rx output bu?er 12 channels preamp 12 channels control diagnostic monitors 1 x 12 pin array bias figure 2. receiver block diagram avago confidential
4 figure 3. application reference diagram asic/serdes fo tx (1 of 12 lanes) host board electrical interface - compliance points - fo rx electrical interface fo rx (1 of 12 lanes) fo tx electrical interface sdd22 scc22 scc11 sdd11 scd11 sdc22 cac cac 100 ? 50 ? 50 ? 100 ? 50 ? 50 ? high speed signal interface figure 3 shows the interface between an asic/serdes and the fber optic modules. for simplicity, only one channel is shown. as shown in the figure 3, the compliance points are on the host board side of the electrical connectors.sets of s-parameters are defned for the transmitter and receiver interfaces. the transmitter and receiver are designed, when operating within recommended operating con - ditions, to provide a robust eye-opening at the receiver outputs. see the recommended operating conditions and the receiver electrical characteristics for details. unused inputs and outputs should be terminated with 100 : diferential loads. the transmitter inputs support a wide common mode range and dc blocking capacitors may not be needed C none are shown in figure 3. depending on the common mode range tolerance of the asic/serdes inputs, dc blocking capacitors may be required in series with the receiver. diferential impedances are nominally 100 : . the common mode output impedance for the receiver is nominally 25 : while the nominal common mode input impedance of the transmitter is 25 : . figure 4. input equalization frequency gain no equalization maximum equalization transmitter input equalization transmitter inputs can be programmed for one of several levels of equalization. see figure 4. diferent levels of compensation can be selected to equalize skin-efect losses across the host circuit board. see tx memory map 01h upper page section addresses 228 - 233 for program - ming details. avago confidential
5 receiver output amplitude and de-emphasis receiver outputs can be programmed to provide several levels of amplitude and de-emphasis. see figure 5 for de-emphasis defnition. the user can program for peak- to-peak amplitude and then a de-emphasis level. if zero de-emphasis is selected, then the signal steady state equals the peak-to-peak level. for other levels of de-emphasis the selected de-emphasis reduces the steady-state from the peak-to-peak level. the change from peak-to-peak level to steady-state occurs within a bit time. see rx memory map 01h upper page section addresses 228 - 233 for amplitude programming details and addresses 234 C 239 for de-emphasis programming details. for optimal performance at 10 gb/s, lowering the de-emphasis setting below the default value of 4 is not recommended. 1 bit data 1 0 0 0 0 0 1 1 1 1 output voltage de-emphasis (de) steady-state (ss) de-emphasis % = (de/ss)(100%) figure 5. defnition of de-emphasis and steady state control signal interface the control interface includes dedicated signals for address inputs, interrupt output and reset input and bidi - rectional clock and data lines for a two-wire serial access (tws interface) to control and status and information registers. the tws interface is compatible with industry standard two-wire serial protocol scaled for 3.3 volt lvttl. it is implemented as a slave device. signal and timing characteristics are further defned in the control charac - teristics and control interface & memory map sections. the registers of the serial interface memory are defned in the control interface & memory map section. regulatory & compliance issues various standard and regulations apply to the modules. these include eye-safety, emc, esd and rohs. see the reg - ulatory section for details regarding these and component recognition. please note the transmitter module is a class 1m laser product C do not view radiation directly with optical instruments. see regulatory compliance table for details. when released, the afbr- will support this table. package outline the module is designed to meet the package outline defned in the ppod msa. this msa follows the outline of the snap12 msa except for the position of the meg- array ? connector and pin assignments. see the package outline and host board footprint fgures (figures 23 -26) for details. handling and cleaning the transmitter and receiver modules can be damaged by exposure to current surges and over voltage events. care should be taken to restrict exposure to the condi - tions defned in the absolute maximum ratings. wave soldering, refow soldering and/or aqueous wash process with the modules on board are not recommended. normal handling precautions for electrostatic discharge sensitive devices should be observed. each module is supplied with an inserted port plug for protection of the optical ports. this plug should always be in place whenever a fber cable is not inserted. the optical connector includes recessed elements that are exposed whenever a cable or port plug is not inserted. prior to insertion of a fber optic cable, it is recommended that the cable end be cleaned to avoid contamination from the cable plug. the port plug ensures the optic remain clean and no addition cleaning should be needed. in the event of contamination, dry nitrogen or clean dry air at less than 20 psi can be used to dislodge the contami - nation. the optical port features (e.g. guide pins) preclude use of a solid instrument. liquids are also not advised. avago confidential
6 link model and reference channel performance specifcations for the afbr-810 transmitter and afbr-820 receiver are based on a reference channel model. a reference channel model provides the basis for inter-operability between independently produced trans - mitter and receiver modules. the reference model used for the afbr-810 transmitter and afbr-820 receiver is based on the industry standard 10gbe link model (10gepbud3_ 1_16a.xls available at the ieee p802.3ae 10gb/s ethernet task force serial pmd documents website http://www. ieee802.org/3/ae/public/adhoc/serial_pmd/documents/). as shown in figure 6, a channel for a fber optic link comprises a transmitter, receiver and cable plant with inputs at test point tp1 and outputs at test point tp4. the test points tp1 and tp4 coincide with the compliance points defned in figure 3. the cable plant here assumes a point to point link and does not include any inline connectors. a reference channel permits the efect of various channel attributes to be referred to diferent points in the channel and accumulated. for example, in the gbe (all_1250. xls available at the ieee website http: //grouper.ieee. org/groups/802/3/10g_study/public/email_attach/all_ 1250.xls) and 10 gbe models all signal impairments are captured and translated into power penalties. also, the efect of transmitter and fber attributes are also captured and referred to tp3 to defne stressed receiver test criteria. similarly, all efects upstream of tp4 can be captured and referred to tp4 and combined at this point into a fgure of merit. since the signal at tp4 is electrical and not optical there are advantages for this. to ensure inter-operability among independently pro- duced transmitters and receivers, defnition of acceptable devices is required. this can be accomplished on an indi - vidual parameter basis by setting min/max limits or with aggregates of attributes by establishing a fgure of merit. referring again to the 10gbe link model, the entity margin at target distance is an aggregate fgure of merit of all link attributes. there a set of link attributes will yield a specifc link margin and a worst case set of link attributes can be defned for a minimum level of performance. instead of placing a maximum or minimum limit on each attribute, it is possible to allow elements in the set to shift (i.e. tradeof with others within the set) as long as the desired margin is achieved. further, if margin at target distance can be translated into eye opening at tp4, the aggregate fgure of merit is directly measurable. to preserve independence for transmitter, receiver and fbers, it is required that trans - mitter attributes only trade-of with other transmitter at - tributes and, similarly, receiver attributes can only trade- of with other receiver attributes. in this data sheet, a minimum eye width at tp4 for a specifed maximum ber is the fgure of merit used to defne acceptable link performance. additional inputs and calculations have been added to the 10gbe link model to calculate eye closure and the efects of all impairments are referred to tp4 and combined as elements of eye closure. the minimum eye width at tp4 is included in tables, transmitter optical characteristics and receiver electri - cal characteristics, as minimum reference link output eye width. the recommended operating conditions table and those for transmitter and receiver characteristics provide the necessary attributes to defne the worst case set for the reference channel. various elements of this worst case set are labeled informative and are allowed to range outside the maximum or minimum limit for the individual element when there is a compensating improvement in others of the worst case subset. transmitter attribute tradeofs are limited to the transmitter subset and receiver tradeofs are limited to the receiver subset. the following two tables summarizes the practical trade- ofs between diferent informative transmitter param - eters, as well as diferent informative receiver parameters, respectively. although the wavelength and spectral width can also trade of with each other, they are not included here for interoperability reason. asic a asic b fo rx tp4 tp3 fiber optic link fo tx tp2 tp1 fiber figure 6. fiber optic link avago confidential
7 informative tx parameters trading of each other while guaranteeing tp2 & tp4 performance parameter symbol extinction ratio er output optical modulation amplitude oma output rise/fall time relative intensity noise oma rin 12 oma contributed portion of accumulated deterministic jitter contributed portion of accumulated total jitter informative rx parameters trading of each other while guaranteeing tp4 performance parameter symbol receiver bandwidth (bw) input optical power sensitivity (oma) contributed portion of accumulated deterministic jitter contributed portion of accumulated total jitter the reference model for testing transmitters consists of a pattern generator, fber optic test cable, attenuator, test receiver and bert. see figure 7 for the evolution of a reference channel to a transmitter test channel. dif - ferences between the worst case values for attributes in the reference model and those in the test equipment set can be compensated by an added attenuator (note that the 10gbe model translates all impairments into power penalties) and adjustments in tj criteria at tp4. diferences in the tp1 input jitter between the defned conditions, tj r and dj r, for the reference channel and actually provided in the test channel, tj t and dj t, can also be accommodat - ed by adjustments to tp4 test criteria (tj r becomes tj t). the extended 10gbe link model is used to determine the compensating attenuation and tp4 criteria adjustments. the reference for testing receivers consists of a pattern generator, test transmitter, fber optic test cable, attenua - tor and bert. see figure 8 for the evolution of a reference channel to a receiver test channel. in a similar manner as with the transmitter, all diferences between the test equipment and worst case channel are compensated with an attenuator and adjustments in the tp4 criteria. r e f e r e n ce c h a n n e l p a t t e r n g e n e r a t o r b e r t t p 1 t j r d j r w o r st c a se t r a n sm i t t e r m i n o m a m i n c e n t e r w a v e l e n g t h m a x s p e ct r a l r m s w i d t h m a x r i n 12 o m a m a x r i se & fa l l t i m e s w o r st c a se c a b l e p l a n t fi b e r t y p e m a x l e n g t h m a x c o n n e ct o r l o ss m a x m o d a l n o i se p e n a l t y w o r st c a se r e ce i v e r m a x s e n si t i v i t y m i n b a n d w i d t h t p 4 t j r r e f e r e n ce c h a n n e l f o r t x d u t ( t x t e st c h a n n e l ) p a t t e r n g e n e r a t o r b e r t t p 1 t j t d j t t r a n sm i t t e r u n d e r t e st t e st c a b l e p l a n t t e st fi b e r t y p e t e st l e n g t h a t t e n u a t o r t e st r e ce i v e r t e st s e n si t i v i t y t e st b a n d w i d t h t p 4 t j t r e f e r e n ce c h a n n e l p a t t e r n g e n e r a t o r b e r t t p 1 t j r d j r w o r st c a se t r a n sm i t t e r m i n o m a m i n c e n t e r w a v e l e n g t h m a x s p e ct r a l r m s w i d t h m a x r i n 12 o m a m a x r i se & fa l l t i m e s w o r st c a se c a b l e p l a n t fi b e r t y p e m a x l e n g t h m a x c o n n e ct o r l o ss m a x m o d a l n o i se p e n a l t y w o r st c a se r e ce i v e r m a x s e n si t i v i t y m i n b a n d w i d t h t p 4 t j r p a t t e r n g e n e r a t o r b e r t r e f e r e n ce c h a n n e l f o r rx d u t ( t x t e st c h a n n e l ) t p 1 t j t d j t t r a n sm i t t e r u n d e r t e st t e st c a b l e p l a n t t e st fi b e r t y p e t e st l e n g t h a t t e n u a t o r r e ce i v e r under test t p 4 t j t t e st o m a t e st c e n t e r w a v e l e n g t h t e st s p e ct r a l r m s w i d t h t e st r i n 12 o m a t e st r i se & fa l l t i m e s figure 7. reference and test channels for transmitter figure 8. reference and test channels for receiver avago confidential
8 absolute maximum ratings stress in excess of any of the individual absolute maximum ratings can cause immediate catastrophic damage to the module even if all other parameters are within recommended operation conditions. it should not be assumed that limiting values of more than one parameter can be applied to the module concurrently. exposure to any of the absolute maximum ratings for extended periods can adversely afect reliability. parameter symbol min max units notes storage temperature t s -40 100 c case temperature C operating t c amr -20 90 c 1 2.5 v power supply voltage v cc 25 -0.5 3.0 v 3.3 v power supply voltage v cc 33 -0.5 3.6 v data input voltage C single ended -0.5 v cc 33+0.5, v cc 25+0.5 v 2 data input voltage C diferential | v dip - v din | 1.0 v 3 control input voltage vi -0.5 v cc 33+0.5, 3.6 v 4 control output current io -20 20 ma relative humidity rh 5 95 % notes: 1. the position for case temperature measurement is shown in figure 11. operation at or above the maximum absolute maximum case temperature for extended periods may adversely afect reliability. optical and electrical characteristics are not defned for operation outside the recommended operating conditions. 2. the maximum limit is the lesser of vcc33 + 0.5 v or vcc25+ 0.5 v. 3. this is the maximum voltage that can be applied across the diferential inputs without damaging the input circuitry. 4. the maximum limit is the lesser of vcc33 + 0.5 v or 3.6 v. avago confidential
9 recommended operating conditions recommended operating conditions specify parameters for which the optical and electrical characteristics hold unless otherwise noted. optical and electrical characteristics are not defned for operation outside the recommended operating conditions, reliability is not implied and damage to the module may occur for such operation over an extended period of time. parameter symbol min typ max units reference case temperature t c 0 40 70 c 1 2.5 v power supply voltage v cc 25 2.375 2.5 2.625 v figures 12, 13 3.3 v power supply voltage v cc 33 3.135 3.3 3.465 v figures 12, 13 signal rate per channel 2.5 10 gbd 2 data input diferential peak-to-peak voltage swing v di pp 175 1400 mvpp 3, figure 14 data input common mode voltage v di cm 0.35 v cc 33-0.35 v 4 data input rise & fall times (20% - 80%) 30 48 ps data input deterministic jitter 15 ps 5 data input total jitter 30 ps 6 control* input voltage high vih 2 vcc33 v control* input voltage low vil gnd 0.8 v two wire serial interface clock rate 400 khz figure 17 two wire serial interface write cycle time t wr 40 ms reset pulse width t rstl pw 10 s figure 19 power supply noise 100 mvpp 7, 500 hz to 2.7 ghz receiver diferential data output load 100 ohms figure 3 ac coupling capacitors C receiver data outputs cac 0.1 f 8, figure 3 fiber length: 2000 mhz?km 50 m mmf 0.5 50 m 9 notes: * control signals, lvttl (3.3 v) compatible, include adr[2:0], intl, resetl, scl and sda. 1. the position for case temperature measurement is shown in figure 11. continuous operation at the maximum recommended operating case temperature should be avoided in order not to degrade reliability. modules will function (degraded performance may result) where operated with case temperatures below the minimum recommended operating case temperature. 2. while operation for various codes, e.g. 8b10b and 64b66b, are supported, certain parameters, jitter and sensitivity, are defned for specifc operating conditions of 10 gbd and 8b/10b equivalent test patterns. the receiver has a low frequency -3db (electrical) corner near 100 khz. 3. data inputs are cml compatible. minimum input requirement holds for default input equalization settings. data input diferential peak to peak voltage swing is defned as follows: v di pp = v dih C v dil where v dih = high state diferential data input voltage and v dil = low state diferential data input voltage. 4. data input common mode voltage is defned as follows: v di cm = (v dinp + v dinn )/2. 5. deterministic jitter, dj, conforms to the dual-dirac model where tj(ber) = dj + 2q(ber)rjrms and rjrms is the width of the gaussian component. here ber = 10 -12 . dj is measured with the same conditions as tj. efects of impairments in the test signal due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns. 6. total jitter, tj, defned for a ber of 10 -12 , is measured at the 50% signal level using test pattern 2 defned in ieee p802.3ae clause 52.9.1, or equivalent, operating at 10 gbd. efects of impairments in the test signals due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns. 7. power supply noise is defned as the peak-to-peak noise amplitude over the frequency range at the host supply side of the recommended power supply flter with the module and recommended flter in place. voltage levels including peak-to-peak noise are limited to the recommended operating range of the associated power supply. see figures 12 and 13 for recommended power supply flters. 8. for data patterns with restricted run lengths and disparity, e.g. 8b10b, smaller value capacitors may provide acceptable results. 9. channel insertion loss includes 3.5 db/km attenuation, 0 db connector loss and 0.3 db modal noise penalty allocations. avago confidential
10 transmitter electrical characteristics* the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc33 = 3.3 v and vcc25 = 2.5 v. parameter symbols min typ max units reference power consumption 2.4 w power supply current C vcc25 380 ma 1 power supply current C vcc33 425 ma 12 diferential input impedance 80 120 informative diferential input refection coefcient s dd11 -8 db 3, figure 3 common mode input refection coefcient s cc11 -6 db 4, figure 3 diferential to cm input refection coefcient s cd11 -35 db 5, figure 3 los assert threshold: tx data input diferential peak-to-peak voltage swing v di pp los 58 120 156 mvpp los hysteresis: tx data input 1 4 db 6 power on initialization time t pwr init 500 ms 7, figure 18 notes: * for control signal timing including adr[2:0], intl, resetl, scl and sda see control characteristics: transmitter/receiver. 1. supply current includes that of all vcc25 contacts. 2. supply current includes that of all vcc33 contacts. 3. measured over the range 100 mhz to 3.75 ghz with reference diferential impedance of 100 4. measured over the range 100 mhz to 3.75 ghz with reference common mode impedance of 25 5. measured over the range 100 mhz to 3.75 ghz with reference diferential impedance of 100 6. los hysteresis is defned as 20 log(los de-assert level / los assert level). 7. power on initialization time is the time from when the supply voltages reach and remain above the minimum recommended operating conditions to the time when the module enables tws access. the module at that point is fully functional. avago confidential
11 receiver electrical characteristics* the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc33 = 3.3 v and vcc25 = 2.5 v. parameter symbol min typ max units reference power consumption 2 w 1 power supply current (vcc25) 670 ma 2 power supply current (vcc33) 200 ma 3 data output diferential peak-to-peak voltage swing (zero de-emphasis) v do pp 775 850 925 mvpp 4, figure 14, 100 load full scale setting 415 490 565 default ampli - tude setting data output common mode voltage v do cm 1.785 2.540 v 5, figure 14, over amplitude setting range data output of state diferential voltage v do off 20 mvpp data output of common mode voltage v do off cm vcc25 v output rise/fall time (20-80%) 80 ps 6 los to data output squelch assert time t sq on 80 s 7, figure 22 data output squelch de-assert time t sq off 300 s 8, figure 22 reference link output deterministic jitter 35 ps 9, informative reference link output total jitter 70 ps 10 reference link output eye width t eye link 30 ps 11 diferential output impedance 80 120 informative diferential output refection coefcient s dd22 -10 db 12, figure 3 common mode output refection coefcient s cc22 -8 db 13, figure 3 cm to diferential output refection coefcient s dc22 -35 db 14, figure 3 power on initialization time t pwr init 500 ms 15, figure 18 inter-channel skew 150 ps 16 rx input-output latency 600 ps informative notes: * for control signal timing including adr[2:0], intl, resetl, scl and sda see control characteristics: transmitter/receiver. 1. max conditions include default output amplitude and de-emphasis programming. 2. supply current includes that of all vcc25 contacts. max conditions include maximum output amplitude and de-emphasis programming. 3. supply current includes that of all vcc33 contacts. max conditions include maximum output amplitude and de-emphasis programming. 4. data outputs are cml compatible. data output diferential peak to peak voltage swing is defned as follows: v do pp = v doh - v dol where v doh = high state diferential data output voltage and v dol = low state diferential data output voltage. impairments in measurements due to the test system are removed. 5. data output common mode voltage is defned as follows: v do cm = (v doutp + v doutn )/2. 6. these are unfltered rise and fall times without de-emphasis measured between the 20% and 80% levels using a 500 mhz square wave test pattern. impairments in measurements due to the test system are removed. 7. this is the module response time from fall of rx input to less than rx input los threshold to squelch of rx outputs. 8. this is the module response time from rise of rx input to greater than rx input los threshold to resumption of rx outputs. 9. deterministic jitter, dj, conforms to the dual-dirac model where tj(ber) = dj + 2q(ber)rjrms and rjrms is the width of the gaussian component. here ber = 10 -12 . dj is measured with the same conditions as tj. the receiver output is measured with default de-emphasis. efects of impairments in the test signals due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns at an input signal 6 db above maximum receiver sensitivity. 10. total jitter, tj, defned for ber of 10 -12 , is measured at the 50% signal level using test pattern 2 defned in ieee p802.3ae clause 52.9.1, or equivalent, operating at 10 gbd with characteristics that are equivalent to that of an afbr 810b transmitter module and maximum cable length operating per the recommended operation conditions as the test source. efects of impairments in the test signals due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns. 11. eye opening is defned as the unit interval less tj for the same test pattern and conditions as tj. 12. measured over the range 100 mhz to 3.75 ghz with reference diferential impedance of 100 13. measured over the range 100 mhz to 3.75 ghz with reference common mode impedance 25 14. measured over the range 100 mhz to 3.75 ghz with reference diferential impedance 100 15. power on initialization time is the time from when the supply voltages reach and remain within recommended operating conditions to the time when the module enables tws access. the module at that point is fully functional. 16. inter-channel skew is defned for the condition of equal amplitude, zero ps skew input signals. avago confidential
12 control characteristics: transmitter/receiver the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc33 = 3.3 v and vcc25 = 2.5 v. parameter symbol min typ max units reference control* input voltage hysteresis lvttl vhys 0.4 v control* input current lvttl iin -125 125 a 0 v < vin < vcc33 control* output voltage low lvttl vol 0.4 v iol = 2ma control* output current high-z ioh -10 10 a 0 v < vin < vcc33 address assert time 100 ms 1 interrupt assert time t intl on 200 ms 2, figure 20 interrupt pulse width t intl pw 5 s 3, figure 20 interrupt de-assert time t intl off 500 s 4, figure 20 reset assert time t rstl on 100 s 5, figure 19 reset de-assert time t rstl off 500 ms 6, figure 19 initialization time tws interfaces 500 ms figure 18 tws data in set up time t su:sda 0.10 s 7, figure 17 tws data in hold time t hd:sda 0 s 8, figure 17 tws clock low to data out valid t aa 0.10 0.90 s 9, figure 17 tws data out hold time t dh 50 ns 10, figure 17 tws data output rise time tr sda 0.30 s figure 17, measured between 0.8v and 2.0v tws data output fall time tf sda 0.30 s tws interface timing see atmel two-wire serial eeprom, e.g. at24c01a tws write cycle time t wr 40ms notes: * control signals include adr[2:0], intl, resetl, scl and sda. 1. this is the module response time from a change in module address, adr[2:0], to response to tws communication using the new address. 2. this is the module response time from occurrence of interrupt generating event to intl assertion, vout:intl = vol. 3. pulse or static level can be selected for intl. pulse mode is default. see memory map. 4. this is the module response time from clear on read operation, measured from falling scl edge after stop bit of read transaction, until vout:intl = voh where intl is in static mode. 5. assertion of resetl activates a complete module reset, i.e. module returns to factory default and non-volatile control settings. while resetl is low, tx and rx outputs are disabled and the module does not respond to the tws interface. 6. this is the response time from resetl de-assertion to resumption of operation. 7. data in set up time is measured from vil(max)sda or vih(min)sda to vil(max)scl. 8. data in hold time is measured from vil(max)scl to vil(max)sda or vih(min)sda. 9. clock low to data out time is measured from vil(max)scl to vol(max)sda or voh(min)sda. 10. data out hold time is measured from vil(max)scl to vol(max)sda or voh(min)sda. avago confidential
13 transmitter optical characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc33 = 3.3 v and vcc25 = 2.5 v. parameter symbol min typ max units reference output optical power: average p o ave -1.5 dbm output optical power: disabled p o off -30 dbm extinction ratio er 3 db informative output optical modulation amplitude oma -5.25 dbm informative output oma: squelched -27 dbm encircled flux 1 center wavelength 830 860 nm spectral width - rms 0.85 nm output rise/fall time 50 ps 2, informative power on initialization time tx outputs t pwr init 500 ms figure 18 reset assert time tx outputs t rstl on 500 ms figure 19 reset de-assert re-initialization time tx outputs t rstl off 500 ms figure 19 output disable assert time for fault t dis on 100 ms figure 21 output squelch assert time for los t sq on 80 s figure 22 output squelch de-assert time for los t sq off 80 s figure 22 inter-channel skew 150 ps 3 channel latency 400 ps informative relative intensity noise oma rin 12 oma -124 db/hz informative accumulated deterministic jitter 30 ps 4, informative accumulated total jitter 60 ps 5, informative reference link output eye width t eye ref 40 ps 6 notes: 1. the transmitter launch condition meets the requirements of 10 gigabit ethernet multimode fber as detailed in tia 492aac. 2. these are unfltered rise and fall times measured between the 20% and 80% levels using a 500 mhz square wave test pattern. impairments in measurements due to the test system are removed. 3. inter-channel skew is defned for the condition of equal amplitude, zero ps skew input signals. 4. deterministic jitter, dj, conforms to the dual-dirac model where tj(ber) = dj + 2q(ber)rjrms and rjrms is the width of the gaussian component. here ber = 10 -12 . dj is measured with the same conditions as tj. efects of impairments in the test signals due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns. 5. total jitter, tj, defned for ber of 10 -12 , is measured at the 50% signal level using test pattern 2 defned in ieee p802.3ae clause 52.9.1, or equivalent, operating at 10 gbd with test source characteristics per the recommended operation conditions. efects of impairments in the test signals due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns. 6. eye opening is defned as the unit interval less tj for the same test pattern and conditions as tj. measurement is made at the output, tp4, of the reference channel. see link model and reference channel section and receiver electrical characteristics. avago confidential
14 receiver optical characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = c, vcc33 = 3.3 v and vcc25 = 2.5 v. parameter symbol min typ max units reference input optical power sensitivity (oma) -11 dbm 1, informative, default signal rate input optical power saturation p sat ave -1.0 dbm 2 operating center wavelength 830 860 nm return loss 12 db los asserted threshold C oma p los oma -26 -19 dbm los de-asserted C oma -17 -12 dbm los hysteresis 0.5 2 db 3 notes: 1. sensitivity is defned as the input oma needed to produce a ber 10 -12 at the center of the signal period using test pattern 2 defned in ieee p802.3ae clause 52.9.1, or equivalent, operating at 10 gbd. efects of impairments in the test signal due to the test system are removed from the measurement. all channels not under test are operating with similar test patterns and input signals 6 db above p in min . 2. saturation is defned as the average input power (er = 6 db) that at the receiver output produces an eye width less than the reference link output eye width minimum (t eye link ) for a ber 10 -12 using test pattern 2 defned in ieee p802.3ae clause 52.9.1, or equivalent, operating at 10 gbd. efects of impairments in the test signal due to the test system are removed from the measurement. 3. signal detect hysteresis is defned as 10 log(los de-assert level / los assert level). regulatory compliance table (when released, the afbr-810bxxz and afbr-820xxxz will support this table.) feature test method performance electrostatic discharge (esd) to the electrical contacts jedec human body model (hbm) (jesd22-a114-b) jedec machine model (mm) (jesd22-a115-a) transmitter module withstands minimum 2000 v receiver module withstands minimum 2000 v transmitter module withstands minimum 100 v receiver module withstands minimum 100 v electrostatic discharge (esd) to optical connector receptacle variation of iec 61000-4-2 typically withstands at least 6 kv air discharge with module biased electromagnetic interference (emi) fcc part 15 cenelec en55022 (cispr 22a) vcci class 1 typically passes with 10 db margin. actual performance dependent on enclosure design. immunity variation of iec 61000-4-3 typically minimal efect from a 10 v/m feld swept from 80 mhz to 1 ghz applied to the module without a chassis enclosure. laser eye safety and equipment type testing iec 60825-1 amendment 2 cfr 21 section 1040 pout: iec ael & us fda cdrh class 1m cdrh accession number: 9720151-074 tuv certifcate number: 72060862 component recognition underwriters laboratories and canadian standards association joint component recognition for information technology equipment including electrical business equipment ul file number: e173874 rohs compliance less than 100 ppm of cadmium, lead, mercury, hexavalent chromium, polybrominated biphenyls, and polybrominated biphenyl esters. avago confidential
15 transmitter module contact assignment and signal description optical connector side 1 2 3 4 5 6 7 8 9 10 a adr2 gnd gnd gnd gnd gnd gnd gnd gnd intl b adr1 gnd din1p gnd din4p gnd din8n gnd din11n gnd c adr0 gnd din1n gnd din4n gnd din8p gnd din11p gnd d gnd din0p gnd din3p gnd din6n gnd din10n gnd sda e gnd din0n gnd din3n gnd din6p gnd din10p gnd scl f resetl gnd din2p gnd din5n gnd din7n gnd din9p gnd g dnc gnd din2n gnd din5p gnd din7p gnd din9n gnd h dnc dnc gnd dnc gnd dnc gnd dnc gnd dnc j gnd gnd gnd dnc dnc dnc dnc gnd gnd gnd k vcc25 vcc33 vcc33 dnc dnc dnc dnc vcc33 vcc33 vcc25 figure 9. host board pattern for transmitter connector C top view signal name signal description i/o type adr[2:0] tws module bus address bits: address has the form 0101hjkx where adr2, adr1 & adr0 correspond to h, j & k respectively and x corresponds to the r/w command. i 3.3v lvttl din[11:0]p transmitter data non-inverting input for channels 11 through 0 i cml din[11:0]n transmitter data inverting input for channels 11 through 0 i cml dnc reserved C do not connect to any electrical potential on host pcb gnd signal common: all module voltages are referenced to this potential unless otherwise stated. connect these pins directly to the host board signal ground plane. intl interrupt signal to host, asserted low: an interrupt is generated in response to any tx fault condition, loss of input signal or assertion of any monitor flag. it may be programmed through the tws interface to generate either a pulse or static level with static mode as default. this output presents a high-z condition when intl is de-asserted and requires a pull-up on the host board. pull-up to the host 3.3 v supply is recommended. o 3.3v lvttl, high-z or driven to 0 level resetl reset signal to module, asserted low: when asserted the optical outputs are disabled, tws interface commands are inhibited, and the module returns to default and non-volatile settings. an internal pullup biases the input high if the input is open. i 3.3v lvttl sda tws interface data signal: pull-up with a 2.0 k? to 8.0 k resistor to the host 3.3 v supply is recommended. i/o 3.3v lvttl/ open-drain scl tws interface clock signal l: pull-up with a 2.0 k to 8.0 k resistor to the host 3.3 v supply is recommended. i 3.3v lvttl vcc25 2.5v power supply, external common connection of pins required C not common internally vcc33 3.3 v power supply, external common connection of pins required C not common internally case common not accessible in connector. case common incorporates exposed conductive surfaces including threaded bosses and is electrically isolated from signal common, i.e. gnd. connect as appropriate for emi shield integrity. see emi clip and bezel cutout recommendation. avago confidential
16 receiver module contact assignment and signal description figure 10. host board pattern for receiver connector C top view optical connector side adr2 gnd gnd gnd gnd gnd gnd gnd gnd intl k adr1 gnd dout1p gnd dout4p gnd dout8n gnd dout11n gnd j adr0 gnd dout1n gnd dout4n gnd dout8p gnd dout11p gnd h gnd dout0p gnd dout3p gnd dout6n gnd dout10n gnd sda g gnd dout0n gnd dout3n gnd dout6p gnd dout10p gnd scl f resetl gnd dout2p gnd dout5n gnd dout7n gnd dout9p gnd e dnc gnd dout2n gnd dout5p gnd dout7p gnd dout9n gnd d dnc dnc gnd dnc gnd dnc gnd dnc gnd dnc c gnd gnd gnd dnc dnc dnc dnc gnd gnd gnd b vcc25 vcc33 vcc33 dnc dnc dnc dnc vcc33 vcc33 vcc25 a 10 9 8 7 6 5 4 3 2 1 pin name functional descriptions i/o type adr[2:0] tws module bus address bits: address has the form 0101hjkx where adr2, adr1 & adr0 correspond to h, j & k respectively and x corresponds to the r/w command. i 3.3v lvttl dout[11:0]p receiver data non-inverting output for channels 11 through 0 o cml dout[11:0]n receiver data inverting output for channels 11 through 0 o cml dnc reserved C do not connect to any electrical potential on host pcb gnd signal common: all module voltages are referenced to this potential unless otherwise stated. connect these pins directly to the host board signal ground plane. intl interrupt signal to host, asserted low: an interrupt is generated in response to loss of input signal or assertion of any monitor flag. it may be programmed through the tws interface to generate either a pulse or static level with static mode as default. this output presents a high-z condition when intl is de-asserted and requires a pull-up on the host board. pull-up to the host 3.3 v supply is recommended. o 3.3v lvttl, high-z or driven to 0 level resetl reset signal to module, asserted low: when asserted the data outputs, dout[11:0]p/n are squelched, tws interface commands are inhibited, and the module returns to default and non-volatile settings. an internal pullup biases the input high if the input is open. i 3.3v lvttl sda tws interface data signal: pull-up with a 2.0 k? to 8.0 k resistor to the host 3.3 v supply is recommended. i/o 3.3v lvttl/ open-drain scl tws interface clock signal: pull-up with a 2.0 k? to 8.0 k resistor to the host 3.3 v supply is recommended. i 3.3v lvttl vcc25 2.5v power supply, external common connection of pins required C not common internally p vcc33 3.3 v power supply, external common connection of pins required C not common internally p case common not accessible in connector. case common incorporates exposed conductive surfaces including threaded bosses and is electrically isolated from signal common, i.e. gnd. connect as appropriate for emi shield integrity. see emi clip and bezel cutout recommendation. avago confidential
17 figure 11. case temperature measurement point host supply module vcc 10 f 0.1 f 68 h host supply module vcc 10 f 0.1 f 68 h figure 12. recommended tx power supply filter figure 13. recommended rx power supply filter figure 14. diferential signal defnitions figure 15. transmitter data input equivalent circuit receiver doutp doutn ?v do + - ?v di/oh ?v di/ol ?v di/opp - + + - transmitter dinp dinn ?v di v di/o refers to either v di or v do as appropriate. ?v di/ol v di/op v di/on ?v di/oh din p 150 k? v cc 33 din n v cc 33 gnd gnd 150 k? 100 k? gnd 100 k? 50 ? 50 ? 35 pf 35 pf 70 pf v cc 25 v cc 25 figure 16. receiver data output equivalent circuit figure 17. tws interface bus timing dout p gnd 50 ohms dout n 50 ohms v cc 25 t su:sda t hd:sda scl t fsda sda in sda out t rsda t rscl t fscl t aa t dh case temperature measurement point avago confidential
18 figure 18. power-up sequence t pwrinit v cc 33 v cc 25 v cc 25 > 2.375 v tws signals normal operation inhibited tx outputs normal operation disabled ... rx outputs normal operation disabled figure 19. resetl sequence t rstl off reset l t rstl pw t rstl on tx outputs normal operation disabled normal operation t rstl on ... rx outputs normal operation disabled normal operation t rstl on tws signals normal operation inhibited normal operation figure 20. interrupt sequence interrupt event scl flag bit t flag on t intl pw t intl on intl sda normal operation normal operation t flag off t intl off tws read transaction stop bit intl pulse mode intl static mode tws write transaction stop bit t dis on scl sda tx output normal operation disabled rx output normal operation disabled t dis on tws write transaction stop bit normal operation normal operation t dis off t dis off figure 21. channel disable sequence avago confidential
19 figure 22. los squelch sequence input los event tx output rx output normal operation normal operation normal operation squelched normal operation squelched flag bit intl t flag on t intl pw t intl on intl pulse mode intl static mode t sq on t sq on t sq off t sq off avago confidential
20 package outline, host pcb footprint and panel cutout figure 23. package outline afbr-810bhz and afbr-820bhz package outline dimensions are nominal expressed in mm unless otherwise stated. the mating host pcb mounted electrical connector is a 100 position fci meg-array ? plug (fci pn: 84512-102) or equivalent. 14.34 17.50 41.07 r ef . 8.95 32.12 24.4 7.56 12.90 thr eaded #2-56 3.8mm deep 3 plc ? s pin a1 l oc a tion pin a1 l oc a tion bott om vie w t x channel 0 channel 11 4.1 2.0 bott om vie w rx 8.63 t o ocl avago confidential
21 figure 24. package outline AFBR-810BEPZ and afbr-820bepz package outline dimensions are nominal expressed in mm unless otherwise stated. the mating host pcb mounted electrical connector is a 100 position fci meg-array ? plug (fci pn: 84512-102) or equivalent. 2.7 1.8 sq . t yp . 2.7 t yp . 4.7 12.90 avago confidential
22 figure 25. host board module footprint (top view) and module (side view) C mid-plane mount dimensions are nominal expressed in mm unless otherwise stated. the mating host pcb mounted electrical connector is a 100 position fci meg-array ? plug (fci pn: 84512-102) or equivalent. (3x) (3x) ? 4.17 keep out ? 2.69 (# 2 screw) (2x) ? 2.54 keep out (2x) ? 1.70 end of module ref. 8.95 end of module ref. 32.12 30.23 10.80 100 pin fci meg-array? receptacle foot print pin a1 5.715 5.715 13.72 18.70 ref note: orientation of receptacle is rotated between tx and rx 50 keep out far connector 4.06 ref. 12.90 ref. shown without heat sink avago confidential
23 figure 26. host board module footprint (top and side views) C panel mount dimensions are nominal expressed in mm unless otherwise stated. the mating host pcb mounted electrical connector is a 100 position fci meg-array ? plug (fci pn: 84512-102) or equivalent. (3x) ?2.69 (#2 scr e w s) (3x) ?4.2 k eep out 13.72.20 30.23.20 10.80 5.08.20 lo inside fr on t panel 5.71 pin a1 19.0min. 16.0.10 11.6.10 1.93.10 avago confidential
24 control interface & memory map the control interface combines dedicated signal lines for address inputs, adr[2:0], interrupt output, intl, and reset input, resetl, with two-wire serial, tws, interface clock, scl, and data, sda, signals to provide users rich function - ality over an efcient and easily used interface. the tws interface is implemented as a slave device and compatible with industry standard two-wire serial protocol. it is scaled for 3.3 volt lvttl. outputs are high-z in the high state to support busing of these signals. signal and timing char - acteristics are further defned in the control i/o charac - teristics section. in general, tws bus timing and protocols follow the implementation popularized in atmel two- wire serial eeproms. for additional details see, e.g., atmel at24c01a. the address signals, adr2, adr1 and adr0, provide the ability to program the tws bus address of the module. the module address has the binary form 0101hjkx, where h, j and k correspond to adr2, adr1 and adr0, respec - tively and x corresponds to the read/write command bit. modules will respond to tws bus addresses in the range of 50h 1 to 5fh (hereafter 5ih) depending upon the state of adr2, adr1 and adr0. the address b0(h) should be avoided on the tws bus where these modules are used. an interrupt signal, intl, is used to alert the host of a loss of input signal (los), transmitter fault conditions and/or assertion of any monitor fag. this reduces the need for dedicated status signal lines and polling the status and monitor registers while maintaining timely alerts to sig - nifcant events. intl can be programmed (page 01h byte 225 bit 0) to either pulse or static mode with pulse as the default mode. a dedicated module reset signal, resetl, is provided in case the tws interface becomes dysfunctional. when resetl is asserted, the outputs are disabled, tws interface commands are inhibited and the module returns to factory default settings except non-volatile read-write (rwn) registers which retain the last write. a module register (memory map except the non-volatile registers) reset can also be initiated over the tws interface (page 5ih byte 91, bit 0). a tws reset can be initiated by nine sla clock cycles with sda high in each cycle and creating a start condition. with the tws interface the user can read a status register (page 5ih byte 2) to see if data is available in the monitor registers, if the module has generated an intl that has not been cleared and global status reports for loss of signal and fault conditions los, tx fault and/or monitor fag registers can be accessed to check the status of individual channels or which channel may have generated a recent intl. los, tx fault and fag bits remain set (latched) after assertion even in the event the condition changes and operation resumes until cleared by the read operation of the associated registers or reset by resetl or the tws module reset function. the user can read the present value of the various monitors. for transmitters and receivers, internal module temperature and supply voltages are reported. for transmitters, monitors provide for each channel laser bias current and laser light output power (lop) information. for receivers, input power (pave) is monitored for each channel. in addition, elapsed operating time is reported. all monitor items are two-byte felds and to maintain coherency, the host must access these with single two-byte read sequences. for each monitored item, alarm thresholds are established. if an item moves past a threshold, a fag is set, and, provided the item is not masked, intl is asserted. the threshold settings are available in the upper memory page, 01h. the user can select either a pulse or static mode for the interrupt signal intl and initiate a module register reset. the user is provided the ability to disable individual channels. for transmitters, equalization levels can be independently set for individual channels. for receivers, output signal amplitude, de-emphasis levels and rate select can be inde - pendently set for individual channels. in the upper page, 01h, control feld the user can invert the truth of the dif - ferential inputs for individual transmitter channel and for the diferential outputs of individual receiver channels. in addition, the user can disable the output squelch function on an individual channel basis for both transmitters and receivers. for transmitters the user can, on an individual channel basis, activate a margin mode that reduces the output optical modulation amplitude for the channel. all non-volatile control registers are located in the upper page 01(h). non-volatile functions include the intl mode selection bit, input and output polarity fip bits, transmit - ter equalization control bits, receiver output amplitude control and receiver output de-emphasis control. entries into these registers will retain the last write for supply voltage cycles and for resetl and module register resets. volatile functions include module register reset, channel disable, squelch disable and margin activation. a mask bit that can be set to prevent assertion of intl for the individual item exists for every los, tx fault and monitor fag. mask felds for los, tx fault and module monitors are in the lower memory page, 5ih, and the mask feld for the channel monitors are in the upper page 01h. entries in the mask felds are volatile. page 00h, based on the serial id pages of xfp and qsfp, provides module identity and information regarding the capabilities of the module. 1. in terms ##h, the h indicates that ## is hexadecimal, if ##b, b indicates binary and if ##, then decimal. avago confidential
25 1. memory map overview the memory is structured as a single address, multiple page approach after that in the xfp msa and adapted by qsfp msa for multi-channel transceivers. figure 27 presents an overview of the memory structure showing a lower page (5ih) and two upper pages (00h and 01h). as with xfp and qsfp, time sensitive, dynamic and/or high interest information are contained in the base, i.e. lower, page. here the upper page 00h contains the serial id byte type lower memory page 5ih 0 ro identi?er 1-2 ro status 3-27 ro interrupt flags: los, fault, monitor 28-39 ro module monitors 40-87 ro channel monitors 88-89 ro elapsed operating time 90-105 rw controls (volatile) 106-118 rw masks: los, fault, module flags 119-126 rw reserved 127 rw upper page select byte byte type upper memory page 00h byte type upper memory page 01h 128-129 ro identi?ers 128-175 ro module thresholds 130 ro description: power supplies 176-223 ro channel thresholds 131 ro description: max case temp 224 ro checksum 132-133 ro description: min/max signal rate 225-243 rw controls (non-volatile) 134-137 ro description: wavelength 244-255 rw masks: channel monitor flags 138-143 ro description: supported functions 144-151 ro reserved 152-170 ro vendor information: name & oui 171-188 ro vendor information: pn & pn rev 189-204 ro vendor information: sn 205-212 ro vendor information: date code 213-222 ro vendor information: clei code 223 ro checksum 224-255 ro vendor speci?c figure 27. two-wire serial address 5ih page structure information, again following the style of xfp and qsfp. the 01h upper table contains static threshold information, confguration controls and fag masks. unless otherwise stated all reserved bytes are coded 00h and all reserved bits are coded 0b. non-volatile read- write bits are labeled rwn and volatile read-write bits are labeled rwv. avago confidential
26 2. memory map timing characteristics the following characteristics are defned over the recommended operating conditions unless otherwise noted. typical values are for tc = 40c, vcc33 = 3.3 v and vcc25 = 2.5 v. parameter symbol min typ max 1 units reference flag (including tx fault & los) assert time 2 t flag on 100 ms figure 20, time from occurrence of condition to intl assertion, vout:intl = vol flag (including tx fault & los) clear time 2 t flag off 100 ms figure 20, time for clear on read operation, measured from falling scl edge after stop bit of read transaction, until vout:intl = voh, where intl is in static mode channel disable assert time t dis on 100 ms figure 21, time from write operation, measured from falling edge of scl after stop bit of write transaction, until channel output falls below 10% of nominal channel disable de-assert time t dis off 300 ms figure 21, time from write operation, measured from falling edge of scl after stop bit of write transaction, until channel output rises above 90% of nominal mask assert time 100 ms time from write operation, measured from falling edge of scl after stop bit of write transaction, until associated intl is inhibited mask de-assert time 100 ms time from write operation, measured from falling edge of scl after stop bit of write transaction, until associated intl resumes volatile control assert time (except channel disable) t cntl on 100 ms time from write operation, measured from falling edge of scl after stop bit of write transaction, until associated control is activated volatile control de-assert time (except channel disable) 100 ms time from write operation, measured from falling edge of scl after stop bit of write transaction, until associated control is de-activated control transition period t cntl xp 10 s time during the control assert time when signal integrity may be impaired non-volatile control assert time 150 ms time from up to two byte write operation, measured from falling edge of scl after stop bit of write transaction, until associated control is activated non-volatile control de-assert time 150 ms time from up to two byte write operation, measured from falling edge of scl after stop bit of write transaction, until associated control is de-activated non-volatile control assert time 300 ms time from up to six byte write operation, measured from falling edge of scl after stop bit of write transaction, until associated control is activated non-volatile control de-assert time 300 ms time from up to six byte write operation, measured from falling edge of scl after stop bit of write transaction, until associated control is de-activated module reset assert time 100 ms time from write operation, measured from falling edge of scl after stop bit of write transaction, until associated reset begins module reset de-assert time 500 ms time from write operation, measured from falling edge of scl after stop bit of write transaction, until associated reset is completed and normal operation resumes notes: 1. max values are valid where competing tws trafc is absent. 2. the outputs of afected channels are disabled for incidences of tx fault and squelched for tx los and/or rx los. timing for output fault and squelch assertion and de-assertion are found in the receiver electrical and transmitter optical characteristics sections. avago confidential
27 3. tx memory map 5ih lower page details of the base or lower page of the memory map for a transmitter follow. address type field name/description byte bit 0 all ro type identifer: coded 00h for unspecifed 1 all ro reserved: coded 00h 2 7-4 ro reserved: coded 0000b 2 3 ro fault status: coded 1 when a fault fag (bytes 11 and 12 of this page) is asserted for any channel, else 0. clears when fault fags are cleared. 2 2 ro los status: coded 1 when a los fag (bytes 9 and 10 of this page) is asserted for any channel, else 0. clears when los fags are cleared. 2 1 ro intl status: coded 1 for asserted intl. clears to 0 when all fags including los and fault are cleared. 2 0 ro data not ready: coded 1 until data is available in monitor registers. coded 0 in normal operation. 3 - 7 all ro reserved: coded 00h 8 0 module ready interrupt. coded 1 when asserted and module is ready to respond to tws commands, latched, clears on read. 9 7-4 ro reserved: coded 0000b 9 3 ro los latched tx channel 11: coded 1 when asserted, latched, clears on read. 9 2 ro los latched tx channel 10: coded 1 when asserted, latched, clears on read. 9 1 ro los latched tx channel 9: coded 1 when asserted, latched, clears on read. 9 0 ro los latched tx channel 8: coded 1 when asserted, latched, clears on read. 10 7 ro los latched tx channel 7: coded 1 when asserted, latched, clears on read. 10 6 ro los latched tx channel 6: coded 1 when asserted, latched, clears on read. 10 5 ro los latched tx channel 5: coded 1 when asserted, latched, clears on read. 10 4 ro los latched tx channel 4: coded 1 when asserted, latched, clears on read. 10 3 ro los latched tx channel 3: coded 1 when asserted, latched, clears on read. 10 2 ro los latched tx channel 2: coded 1 when asserted, latched, clears on read. 10 1 ro los latched tx channel 1: coded 1 when asserted, latched, clears on read. 10 0 ro los latched tx channel 0: coded 1 when asserted, latched, clears on read. 11 7-4 ro reserved: coded 0000b 11 3 ro fault latched tx channel 11: coded 1 when asserted, latched, clears on read. 11 2 ro fault latched tx channel 10: coded 1 when asserted, latched, clears on read. 11 1 ro fault latched tx channel 9: coded 1 when asserted, latched, clears on read. 11 0 ro fault latched tx channel 8: coded 1 when asserted, latched, clears on read. 12 7 ro fault latched tx channel 7: coded 1 when asserted, latched, clears on read. 12 6 ro fault latched tx channel 6: coded 1 when asserted, latched, clears on read. 12 5 ro fault latched tx channel 5: coded 1 when asserted, latched, clears on read. 12 4 ro fault latched tx channel 4: coded 1 when asserted, latched, clears on read. 12 3 ro fault latched tx channel 2: coded 1 when asserted, latched, clears on read. 12 2 ro fault latched tx channel 2: coded 1 when asserted, latched, clears on read. 12 1 ro fault latched tx channel 1: coded 1 when asserted, latched, clears on read. 12 0 ro fault latched tx channel 0: coded 1 when asserted, latched, clears on read. 13 7 ro high internal temperature alarm latched: coded 1 when asserted, latched, clears on read. 13 6 ro low internal temperature alarm latched: coded 1 when asserted, latched, clears on read. 13 5-0 ro reserved 14 7 ro high internal 3.3 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 6 ro low internal 3.3 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 5-4 ro reserved 14 3 ro high internal 2.5 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 2 ro low internal 2.5 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 1-0 ro reserved avago confidential
28 address type field name/description byte bit 15 all ro reserved: coded 00h 16 7 ro high tx bias current alarm latched channel 11: coded 1 when asserted, latched, clears on read. 16 6 ro low tx bias current alarm latched channel 11: coded 1 when asserted, latched, clears on read. 16 5-4 ro reserved 16 3 ro high tx bias current alarm latched channel 10: coded 1 when asserted, latched, clears on read. 16 2 ro low tx bias current alarm latched channel 10: coded 1 when asserted, latched, clears on read. 16 1-0 ro reserved 17 7 ro high tx bias current alarm latched channel 9: coded 1 when asserted, latched, clears on read. 17 6 ro low tx bias current alarm latched channel 9: coded 1 when asserted, latched, clears on read. 17 5-4 ro reserved 17 3 ro high tx bias current alarm latched channel 8: coded 1 when asserted, latched, clears on read. 17 2 ro low tx bias current alarm latched channel 8: coded 1 when asserted, latched, clears on read. 17 1-0 ro reserved 18 7 ro high tx bias current alarm latched channel 7: coded 1 when asserted, latched, clears on read. 18 6 ro low tx bias current alarm latched channel 7: coded 1 when asserted, latched, clears on read. 18 5-4 ro reserved 18 3 ro high tx bias current alarm latched channel 6: coded 1 when asserted, latched, clears on read. 18 2 ro low tx bias current alarm latched channel 6: coded 1 when asserted, latched, clears on read. 18 1-0 ro reserved 19 7 ro high tx bias current alarm latched channel 5: coded 1 when asserted, latched, clears on read. 19 6 ro low tx bias current alarm latched channel 5: coded 1 when asserted, latched, clears on read. 19 5-4 ro reserved 19 3 ro high tx bias current alarm latched channel 4: coded 1 when asserted, latched, clears on read. 19 2 ro low tx bias current alarm latched channel 4: coded 1 when asserted, latched, clears on read. 19 1-0 ro reserved 20 7 ro high tx bias current alarm latched channel 3: coded 1 when asserted, latched, clears on read. 20 6 ro low tx bias current alarm latched channel 3: coded 1 when asserted, latched, clears on read. 20 5-4 ro reserved 20 3 ro high tx bias current alarm latched channel 2: coded 1 when asserted, latched, clears on read. 20 2 ro low tx bias current alarm latched channel 2: coded 1 when asserted, latched, clears on read. 20 1-0 ro reserved 21 7 ro high tx bias current alarm latched channel 1: coded 1 when asserted, latched, clears on read. 21 6 ro low tx bias current alarm latched channel 1: coded 1 when asserted, latched, clears on read. 21 5-4 ro reserved 21 3 ro high tx bias current alarm latched channel 0: coded 1 when asserted, latched, clears on read. 21 2 ro low tx bias current alarm latched channel 0: coded 1 when asserted, latched, clears on read. 21 1-0 ro reserved 22 7 ro high tx power alarm latched channel 11: coded 1 when asserted, latched, clears on read. 22 6 ro low tx power alarm latched channel 11: coded 1 when asserted, latched, clears on read. 22 5-4 ro reserved 22 3 ro high tx power alarm latched channel 10: coded 1 when asserted, latched, clears on read. 22 2 ro low tx power alarm latched channel 10: coded 1 when asserted, latched, clears on read. 22 1-0 ro reserved 23 7 ro high tx power alarm latched channel 9: coded 1 when asserted, latched, clears on read. 23 6 ro low tx power alarm latched channel 9: coded 1 when asserted, latched, clears on read. 23 5-4 ro reserved 23 3 ro high tx power alarm latched channel 8: coded 1 when asserted, latched, clears on read. 23 2 ro low tx power alarm latched channel 8: coded 1 when asserted, latched, clears on read. 23 1-0 ro reserved avago confidential
29 address type field name/description byte bit 24 7 ro high tx power alarm latched channel 7: coded 1 when asserted, latched, clears on read. 24 6 ro low tx power alarm latched channel 7: coded 1 when asserted, latched, clears on read. 24 5-4 ro reserved 24 3 ro high tx power alarm latched channel 6: coded 1 when asserted, latched, clears on read. 24 2 ro low tx power alarm latched channel 6: coded 1 when asserted, latched, clears on read. 24 1-0 ro reserved 25 7 ro high tx power alarm latched channel 5: coded 1 when asserted, latched, clears on read. 25 6 ro low tx power alarm latched channel 5: coded 1 when asserted, latched, clears on read. 25 5-4 ro reserved 25 3 ro high tx power alarm latched channel 4: coded 1 when asserted, latched, clears on read. 25 2 ro low tx power alarm latched channel 4: coded 1 when asserted, latched, clears on read. 25 1-0 ro reserved 26 7 ro high tx power alarm latched channel 3: coded 1 when asserted, latched, clears on read. 26 6 ro low tx power alarm latched channel 3: coded 1 when asserted, latched, clears on read. 26 5-4 ro reserved 26 3 ro high tx power alarm latched channel 2: coded 1 when asserted, latched, clears on read. 26 2 ro low tx power alarm latched channel 2: coded 1 when asserted, latched, clears on read. 26 1-0 ro reserved 27 7 ro high tx power alarm latched channel 1: coded 1 when asserted, latched, clears on read. 27 6 ro low tx power alarm latched channel 1: coded 1 when asserted, latched, clears on read. 27 5-4 ro reserved 27 3 ro high tx power alarm latched channel 0: coded 1 when asserted, latched, clears on read. 27 2 ro low tx power alarm latched channel 0: coded 1 when asserted, latched, clears on read. 27 1-0 ro reserved 28 all ro internal temperature monitor msb: integer part coded in signed 2s complement. tolerance is 3c. 29 all ro internal temperature monitor lsb: fractional part in units of 1/256 coded in binary. 30-31 all ro reserved: coded 00h 32-33 all ro internal 3.3 vcc monitor: voltage in 100 v units coded as 16 bit unsigned integer, byte 32 is msb. tolerance is 0.150v. 34-35 all ro internal 2.5 vcc monitor: voltage in 100 v units coded as 16 bit unsigned integer, byte 34 is msb. tolerance is 0.150v. 36-39 all ro reserved: coded 00h 40-41 all ro tx bias current monitor channel 11: bias current in 2 a units coded as 16 bit unsigned integer, byte 40 is msb. tolerance is 0.50 ma. 42-43 all ro tx bias current monitor channel 10: bias current in 2 a units coded as 16 bit unsigned integer, byte 42 is msb. tolerance is 0.50 ma. 44-45 all ro tx bias current monitor channel 9: bias current in 2 a units coded as 16 bit unsigned integer, byte 44 is msb. tolerance is 0.50 ma. 46-47 all ro tx bias current monitor channel 8: bias current in 2 a units coded as 16 bit unsigned integer, byte 46 is msb. tolerance is 0.50 ma. 48-49 all ro tx bias current monitor channel 7: bias current in 2 a units coded as 16 bit unsigned integer, byte 48 is msb. tolerance is 0.50 ma. 50-51 all ro tx bias current monitor channel 6: bias current in 2 a units coded as 16 bit unsigned integer, byte 50 is msb. tolerance is 0.50 ma. 52-53 all ro tx bias current monitor channel 5: bias current in 2 a units coded as 16 bit unsigned integer, byte 52 is msb. tolerance is 0.50 ma. 54-55 all ro tx bias current monitor channel 4: bias current in 2 a units coded as 16 bit unsigned integer, byte 54 is msb. tolerance is 0.50 ma. 56-57 all ro tx bias current monitor channel 3: bias current in 2 a units coded as 16 bit unsigned integer, byte 56 is msb. tolerance is 0.50 ma. 58-59 all ro tx bias current monitor channel 2: bias current in 2 a units coded as 16 bit unsigned integer, byte 58 is msb. tolerance is 0.50 ma. avago confidential
30 address type field name/description byte bit 60-61 all ro tx bias current monitor channel 1: bias current in 2 a units coded as 16 bit unsigned integer, byte 60 is msb. tolerance is 0.50 ma. 62-63 all ro tx bias current monitor channel 0: bias current in 2 a units coded as 16 bit unsigned integer, byte 62 is msb. tolerance is 0.50 ma. 64-65 all ro tx light output monitor channel 11: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 64 is msb. tolerance is 3db. 66-67 all ro tx light output monitor channel 10: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 66 is msb. tolerance is 3db. 68-69 all ro tx light output monitor channel 9: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 68 is msb. tolerance is 3db. 70-71 all ro tx light output monitor channel 8: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 70 is msb. tolerance is 3db. 72-73 all ro tx light output monitor channel 7: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 72 is msb. tolerance is 3db. 74-75 all ro tx light output monitor channel 6: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 74 is msb. tolerance is 3db. 76-77 all ro tx light output monitor channel 5: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 76 is msb. tolerance is 3db. 78-79 all ro tx light output monitor channel 4: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 78 is msb. tolerance is 3db. 80-81 all ro tx light output monitor channel 3: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 80 is msb. tolerance is 3db. 82-83 all ro tx light output monitor channel 2: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 82 is msb. tolerance is 3db. 84-85 all ro tx light output monitor channel 1: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 84 is msb. tolerance is 3db. 86-87 all ro tx light output monitor channel 0: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 86 is msb. tolerance is 3db. 88-89 all ro elapsed (power-on) operating time: elapsed time in 2 hour units coded as 16 bit unsigned integer, byte 88 is msb, tolerance is 10% 90 all rwv reserved: coded 00h 91 7-1 rwv reserved: coded 0000000b 91 0 rwv transmitter reset: writing 1 return all registers except non-volatile rw to factory default values. reads 0 after operation. 92 7-4 rwv reserved: coded 0000b 92 3 rwv tx channel 11 disable: writing 1 deactivates the optical output, default is 0. 92 2 rwv tx channel 10 disable: writing 1 deactivates the optical output, default is 0. 92 1 rwv tx channel 9 disable: writing 1 deactivates the optical output, default is 0. 92 0 rwv tx channel 8 disable: writing 1 deactivates the optical output, default is 0. 93 7 rwv tx channel 7 disable: writing 1 deactivates the optical output, default is 0. 93 6 rwv tx channel 6 disable: writing 1 deactivates the optical output, default is 0. 93 5 rwv tx channel 5 disable: writing 1 deactivates the optical output, default is 0. 93 4 rwv tx channel 4 disable: writing 1 deactivates the optical output, default is 0. 93 3 rwv tx channel 3 disable: writing 1 deactivates the optical output, default is 0. 93 2 rwv tx channel 2 disable: writing 1 deactivates the optical output, default is 0. 93 1 rwv tx channel 1 disable: writing 1 deactivates the optical output, default is 0. 93 0 rwv tx channel 0 disable: writing 1 deactivates the optical output, default is 0. 94 7-4 rwv reserved: coded 0000b 94 3 rwv squelch disable channel 11: writing 1 inhibits squelch for the channel, default is 0. 94 2 rwv squelch disable channel 10: writing 1 inhibits squelch for the channel, default is 0. 94 1 rwv squelch disable channel 9: writing 1 inhibits squelch for the channel, default is 0. 94 0 rwv squelch disable channel 8: writing 1 inhibits squelch for the channel, default is 0. avago confidential
31 address type field name/description byte bit 95 7 rwv squelch disable channel 7: writing 1 inhibits squelch for the channel, default is 0. 95 6 rwv squelch disable channel 6: writing 1 inhibits squelch for the channel, default is 0. 95 5 rwv squelch disable channel 5: writing 1 inhibits squelch for the channel, default is 0. 95 4 rwv squelch disable channel 4: writing 1 inhibits squelch for the channel, default is 0. 95 3 rwv squelch disable channel 3: writing 1 inhibits squelch for the channel, default is 0. 95 2 rwv squelch disable channel 2: writing 1 inhibits squelch for the channel, default is 0. 95 1 rwv squelch disable channel 1: writing 1 inhibits squelch for the channel, default is 0. 95 0 rwv squelch disable channel 0: writing 1 inhibits squelch for the channel, default is 0. 96-98 all rwv reserved: coded 00h 99 7-4 rwv reserved: coded 0000b 99 3 rwv margin activation channel 11: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 99 2 rwv margin activation channel 10: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 99 1 rwv margin activation channel 9: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 0 rwv margin activation channel 8: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 7 rwv margin activation channel 7: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 6 rwv margin activation channel 6: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 5 rwv margin activation channel 5: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 4 rwv margin activation channel 4: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 3 rwv margin activation channel 3: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 2 rwv margin activation channel 2: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 1 rwv margin activation channel 1: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 100 0 rwv margin activation channel 0: writing 1places channel into margin mode (reduces oma by 1 db), default is 0. 101-105 all rwv reserved: coded 00h 106-111 all rwv reserved: coded 00h 112 7-4 rwv reserved: coded 0000b 112 3 rwv mask los tx channel 11: writing 1 prevents intl generation, default = 0 112 2 rwv mask los tx channel 10: writing 1 prevents intl generation, default = 0 112 1 rwv mask los tx channel 9: writing 1 prevents intl generation, default = 0 112 0 rwv mask los tx channel 8: writing 1 prevents intl generation, default = 0 113 7 rwv mask los tx channel 7: writing 1 prevents intl generation, default = 0 113 6 rwv mask los tx channel 6: writing 1 prevents intl generation, default = 0 113 5 rwv mask los tx channel 5: writing 1 prevents intl generation, default = 0 113 4 rwv mask los tx channel 4: writing 1 prevents intl generation, default = 0 113 3 rwv mask los tx channel 3: writing 1 prevents intl generation, default = 0 113 2 rwv mask los tx channel 2: writing 1 prevents intl generation, default = 0 113 1 rwv mask los tx channel 1: writing 1 prevents intl generation, default = 0 113 0 rwv mask los tx channel 0: writing 1 prevents intl generation, default = 0 114 7-4 rwv reserved: coded 0000b 114 3 rwv mask fault tx channel 11: writing 1 prevents intl generation, default = 0 114 2 rwv mask fault tx channel 10: writing 1 prevents intl generation, default = 0 114 1 rwv mask fault tx channel 9: writing 1 prevents intl generation, default = 0 114 0 rwv mask fault tx channel 8: writing 1 prevents intl generation, default = 0 115 7 rwv mask fault tx channel 7: writing 1 prevents intl generation, default = 0 115 6 rwv mask fault tx channel 6: writing 1 prevents intl generation, default = 0 115 5 rwv mask fault tx channel 5: writing 1 prevents intl generation, default = 0 115 4 rwv mask fault tx channel 4: writing 1 prevents intl generation, default = 0 115 3 rwv mask fault tx channel 3: writing 1 prevents intl generation, default = 0 115 2 rwv mask fault tx channel 2: writing 1 prevents intl generation, default = 0 115 1 rwv mask fault tx channel 1: writing 1 prevents intl generation, default = 0 115 0 rwv mask fault tx channel 0: writing 1 prevents intl generation, default = 0 avago confidential
32 address type field name/description byte bit 116 7 rwv mask high internal temperature alarm: writing 1 prevents intl generation, default = 0 116 6 rwv mask low internal temperature alarm: writing 1 prevents intl generation, default = 0 116 5-0 rwv reserved 117 7 rwv mask high internal 3.3 vcc alarm: writing 1 prevents intl generation, default = 0 117 6 rwv mask low internal 3.3 vcc alarm: writing 1 prevents intl generation, default = 0 117 5-4 rwv reserved 117 3 rwv mask high internal 2.5 vcc alarm: writing 1 prevents intl generation, default = 0 117 2 rwv mask low internal 2.5 vcc alarm: writing 1 prevents intl generation, default = 0 117 1-0 rwv reserved 118 all rwv tx output power alarm level select. custom=01h, factory default=0 119-120 all rw tx optical power all channels custom high alarm threshold: optical power in 0.1 uw units coded as 16 bit un - signed integer, low address is msb 121-122 all rw tx optical power all channels custom low alarm threshold: optical power in 0.1 uw units coded as 16 bit un - signed integer, low address is msb 123-126 all rw reserved: coded 00h 127 all rwv page select byte avago confidential
33 4. tx memory map 00h upper page transmitter serial id page 00h entries follow. description of the registers can be found in section 9 below. address contents type field name/description byte bit code 128 all 00h ro type identifer: coded 00h for unspecifed. see sff-8472 for reference 129 all 10000010b ro module description: coded for < 2.5 w max, controlled launch 130 all 11000000b ro required power supplies: coded for 3.3v & 2.5v supplies 131 all 01010000b ro max recommended operating case temperature in degrees c: coded for 80c 132 all 00011001b ro min bit rate in 100 mb/s units: coded for 2500 mb/s 133 all 01100100b ro max bit rate in 100 mb/s units: coded for 10000 mb/s 134-135 all 42h 04h ro nominal laser wavelength (wavelength in nm = value / 20): coded for 845 nm 136-137 all 0bh bbh ro wavelength deviation from nominal (wavelength tolerance in nm = +/- value / 200): coded for 15 nm 138 all 11001000b ro supported flags/actions: coded for tx fault, tx los, output squelch for los, alarm flags 139 all 11000101b ro supported monitors: coded for tx bias, tx lop, internal temp, elapsed time 140 all 01100000b ro supported monitors: coded for 3.3v, 2.5v 141 all 10100010b ro supported controls: coded for ch disable, squelch disable, input equalization 142 all 00001011b ro supported controls: coded for margin mode, ch polarity flip, module addressing 143 all 00h ro supported functions: 144-151 all 00h ro reserved 152-167 all 41h 56h 41h 47h 4fh 20h 20h x10 ro vendor name in ascii: coded avago for avago technologies, spaces (20h) for unused characters 168-170 all 00h 17h 6ah ro vendor oui (ieee id): coded 00h 17h 6ah for avago technologies 171-186 all 41h 46h 42h 52h 2dh 37h 37h 36h 42h ro vendor part number in ascii: afbr-810b where bytes 180 through 186 vary with selected option, spaces (20h) for unused characters 187-188 all 30h 32h ro vendor revision number in ascii: coded 02 189-204 all ro vendor serial number (ascii): varies by unit 205-212 all ro vendor date code yyyymmdd (ascii):spaces (20h) for unused characters 213-222 all ro clei code in ascii: all spaces (20h) if unused 223 all ro check sum addresses 128 through 222 224-255 all ro vendor specifc: all zeroes if unused avago confidential
34 5. tx memory map 01h upper page details of transmitter upper page 01h follow. address type field name/description byte bit 128 all ro internal temperature high alarm threshold msb: integer part coded in signed 2s complement 129 all ro internal temperature high alarm threshold lsb: fractional part in units of 1/256 coded in binary. 130 all ro internal temperature low alarm threshold msb: integer part coded in signed 2s complement 131 all ro internal temperature low alarm threshold lsb: fractional part in units of 1/256 coded in binary. 132-143 all ro reserved: coded 00h 144-145 all ro internal 3.3 vcc high alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 146-147 all ro internal 3.3 vcc low alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 148-151 all ro reserved 152-153 all ro internal 2.5 vcc high alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 154-155 all ro internal 2.5 vcc low alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 156-159 all ro reserved 160-175 all ro thresholds reserved: coded 00h 176-177 all ro tx bias current all channels high alarm threshold: current in 2 a units coded as 16 bit unsigned integer, low address is msb. 178-179 all ro tx bias current all channels low alarm threshold: current in 2 a units coded as 16 bit unsigned integer, low address is msb. 180-183 all ro reserved 184-185 all ro tx optical power all channels high alarm threshold: optical power in 0.1 w units coded as 16 bit unsigned integer, low address is msb. 186-187 all ro tx optical power all channels low alarm threshold: optical power in 0.1 w units coded as 16 bit unsigned integer, low address is msb. 188-223 all ro thresholds reserved: coded 00h 224 all ro check sum: low order 8 bits of the sum of all bytes from 128 through 223 inclusive 225 7-1 rwn reserved: coded 0000000b 225 0 rwn intl pulse/static option: writing 1 sets intl to static mode, default is 0 for pulse mode 226 7-4 rwn reserved: coded 0000b 226 3 rwn input polarity flip channel 11: writing 1 inverts truth of the diferential input pair, default is 0. 226 2 rwn input polarity flip channel 10: writing 1 inverts truth of the diferential input pair, default is 0. 226 1 rwn input polarity flip channel 9: writing 1 inverts truth of the diferential input pair, default is 0. 226 0 rwn input polarity flip channel 8: writing 1 inverts truth of the diferential input pair, default is 0. 227 7 rwn input polarity flip channel 7: writing 1 inverts truth of the diferential input pair, default is 0. 227 6 rwn input polarity flip channel 6: writing 1 inverts truth of the diferential input pair, default is 0. 227 5 rwn input polarity flip channel 5: writing 1 inverts truth of the diferential input pair, default is 0. 227 4 rwn input polarity flip channel 4: writing 1 inverts truth of the diferential input pair, default is 0. 227 3 rwn input polarity flip channel 3: writing 1 inverts truth of the diferential input pair, default is 0. 227 2 rwn input polarity flip channel 2: writing 1 inverts truth of the diferential input pair, default is 0. 227 1 rwn input polarity flip channel 1: writing 1 inverts truth of the diferential input pair, default is 0. 227 0 rwn input polarity flip channel 0: writing 1 inverts truth of the diferential input pair, default is 0. 228 7-4 rwn tx input equalization control channel 11: see below for code description. default = 7 228 3-0 rwn tx input equalization control channel 10: see below for code description. default = 7 229 7-4 rwn tx input equalization control channel 9: see below for code description. default = 7 229 3-0 rwn tx input equalization control channel 8: see below for code description. default = 7 230 7-4 rwn tx input equalization control channel 7: see below for code description. default = 7 230 3-0 rwn tx input equalization control channel 6: see below for code description. default = 7 231 7-4 rwn tx input equalization control channel 5: see below for code description. default = 7 231 3-0 rwn tx input equalization control channel 4: see below for code description. default = 7 232 7-4 rwn tx input equalization control channel 3: see below for code description. default = 7 232 3-0 rwn tx input equalization control channel 2: see below for code description. default = 7 avago confidential
35 address type field name/description byte bit 233 7-4 rwn tx input equalization control channel 1: see below for code description. default = 7 233 3-0 rwn tx input equalization control channel 0: see below for code description. default = 7 234-243 all rwn reserved: coded 00h 244 7 rwv mask high tx bias current alarm channel 11: writing 1 prevents intl generation, default = 0 244 6 rwv mask low tx bias current alarm channel 11: writing 1 prevents intl generation, default = 0 244 5-4 rwv reserved 244 3 rwv mask high tx bias current alarm channel 10: writing 1 prevents intl generation, default = 0 244 2 rwv mask low tx bias current alarm channel 10: writing 1 prevents intl generation, default = 0 244 1-0 rwv reserved 245 7 rwv mask high tx bias current alarm channel 9: writing 1 prevents intl generation, default = 0 245 6 rwv mask low tx bias current alarm channel 9: writing 1 prevents intl generation, default = 0 245 5-4 rwv reserved 245 3 rwv mask high tx bias current alarm channel 8: writing 1 prevents intl generation, default = 0 245 2 rwv mask low tx bias current alarm channel 8: writing 1 prevents intl generation, default = 0 245 1-0 rwv reserved 246 7 rwv mask high tx bias current alarm channel 7: writing 1 prevents intl generation, default = 0 246 6 rwv mask low tx bias current alarm channel 7: writing 1 prevents intl generation, default = 0 246 5-4 rwv reserved 246 3 rwv mask high tx bias current alarm channel 6: writing 1 prevents intl generation, default = 0 246 2 rwv mask low tx bias current alarm channel 6: writing 1 prevents intl generation, default = 0 246 1-0 rwv reserved 247 7 rwv mask high tx bias current alarm channel 5: writing 1 prevents intl generation, default = 0 247 6 rwv mask low tx bias current alarm channel 5: writing 1 prevents intl generation, default = 0 247 5-4 rwv reserved 247 3 rwv mask high tx bias current alarm channel 4: writing 1 prevents intl generation, default = 0 247 2 rwv mask low tx bias current alarm channel 4: writing 1 prevents intl generation, default = 0 247 1-0 rwv reserved 248 7 rwv mask high tx bias current alarm channel 3: writing 1 prevents intl generation, default = 0 248 6 rwv mask low tx bias current alarm channel 3: writing 1 prevents intl generation, default = 0 248 5-4 rwv reserved 248 3 rwv mask high tx bias current alarm channel 2: writing 1 prevents intl generation, default = 0 248 2 rwv mask low tx bias current alarm channel 2: writing 1 prevents intl generation, default = 0 248 1-0 rwv reserved 249 7 rwv mask high tx bias current alarm channel 1: writing 1 prevents intl generation, default = 0 249 6 rwv mask low tx bias current alarm channel 1: writing 1 prevents intl generation, default = 0 249 5-4 rwv reserved 249 3 rwv mask high tx bias current alarm channel 0: writing 1 prevents intl generation, default = 0 249 2 rwv mask low tx bias current alarm channel 0: writing 1 prevents intl generation, default = 0 249 1-0 rwv reserved 250 7 rwv mask high tx power alarm channel 11: writing 1 prevents intl generation, default = 0 250 6 rwv mask low tx power alarm channel 11: writing 1 prevents intl generation, default = 0 250 5-4 rwv reserved 250 3 rwv mask high tx power alarm channel 10: writing 1 prevents intl generation, default = 0 250 2 rwv mask low tx power alarm channel 10: writing 1 prevents intl generation, default = 0 250 1-0 rwv reserved avago confidential
36 address type field name/description byte bit 251 5-4 rwv reserved 251 3 rwv mask high tx power alarm channel 8: writing 1 prevents intl generation, default = 0 251 2 rwv mask low tx power alarm channel 8: writing 1 prevents intl generation, default = 0 251 1-0 rwv reserved 252 7 rwv mask high tx power alarm channel 7: writing 1 prevents intl generation, default = 0 252 6 rwv mask low tx power alarm channel 7: writing 1 prevents intl generation, default = 0 252 5-4 rwv reserved 252 3 rwv mask high tx power alarm channel 6: writing 1 prevents intl generation, default = 0 252 2 rwv mask low tx power alarm channel 6: writing 1 prevents intl generation, default = 0 252 1-0 rwv reserved 253 7 rwv mask high tx power alarm channel 5: writing 1 prevents intl generation, default = 0 253 6 rwv mask low tx power alarm channel 5: writing 1 prevents intl generation, default = 0 253 5-4 rwv reserved 253 3 rwv mask high tx power alarm channel 4: writing 1 prevents intl generation, default = 0 253 2 rwv mask low tx power alarm channel 4: writing 1 prevents intl generation, default = 0 253 1-0 rwv reserved 254 7 rwv mask high tx power alarm channel 3: writing 1 prevents intl generation, default = 0 254 6 rwv mask low tx power alarm channel 3: writing 1 prevents intl generation, default = 0 254 5-4 rwv reserved 254 3 rwv mask high tx power alarm channel 2: writing 1 prevents intl generation, default = 0 254 2 rwv mask low tx power alarm channel 2: writing 1 prevents intl generation, default = 0 254 1-0 rwv reserved 255 7 rwv mask high tx power alarm channel 1: writing 1 prevents intl generation, default = 0 255 6 rwv mask low tx power alarm channel 1: writing 1 prevents intl generation, default = 0 255 5-4 rwv reserved 255 3 rwv mask high tx power alarm channel 0: writing 1 prevents intl generation, default = 0 255 2 rwv mask low tx power alarm channel 0: writing 1 prevents intl generation, default = 0 255 1-0 rwv reserved transmitter input equalization control code description control registers 228 through 233 permit input equalization control. four bit code blocks (either bits 7 through 4 or 3 through 0 where bit 7 or 3 is the msb) are assigned to each channel. codes 1xxx are reserved. code 0111 calls for full scale equalization and code 0000 calls for no equalization. intermediate code values provide intermediate levels of compensation. avago confidential
37 6. rx memory map 5ih lower page details of the base or lower page of the memory map for a receiver follow. address type field name/description byte bit 0 all ro type identifer: coded 00h for unspecifed 1 all ro reserved: coded 00h 2 7-3 ro reserved: coded 000000b 2 2 ro los status: coded 1 when a los fag (bytes 9 and 10 of this page) is asserted for any channel, else 0. clears when los fags are cleared. 2 1 ro intl status: coded 1 for asserted intl. clears to 0 when all fags including los are cleared. 2 0 ro data not ready: coded 1 until data is available in monitor registers. coded 0 in normal operation. 3 - 7 all ro reserved: coded 00h 8 0 module ready interrupt. coded 1 when asserted and module is ready to respond to tws commands, latched, clears on read. 9 7-4 ro reserved: coded 0000b 9 3 ro los latched rx channel 11: coded 1 when asserted, latched, clears on read. 9 2 ro los latched rx channel 10: coded 1 when asserted, latched, clears on read. 9 1 ro los latched rx channel 9: coded 1 when asserted, latched, clears on read. 9 0 ro los latched rx channel 8: coded 1 when asserted, latched, clears on read. 10 7 ro los latched rx channel 7: coded 1 when asserted, latched, clears on read. 10 6 ro los latched rx channel 6: coded 1 when asserted, latched, clears on read. 10 5 ro los latched rx channel 5: coded 1 when asserted, latched, clears on read. 10 4 ro los latched rx channel 4: coded 1 when asserted, latched, clears on read. 10 3 ro los latched rx channel 3: coded 1 when asserted, latched, clears on read. 10 2 ro los latched rx channel 2: coded 1 when asserted, latched, clears on read. 10 1 ro los latched rx channel 1: coded 1 when asserted, latched, clears on read. 10 0 ro los latched rx channel 0: coded 1 when asserted, latched, clears on read. 11-12 all ro reserved: coded 00h 13 7 ro high internal temperature alarm latched: coded 1 when asserted, latched, clears on read. 13 6 ro low internal temperature alarm latched: coded 1 when asserted, latched, clears on read. 13 5-0 ro reserved 14 7 ro high internal 3.3 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 6 ro low internal 3.3 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 5-4 ro reserved 14 3 ro high internal 2.5 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 2 ro low internal 2.5 vcc alarm latched: coded 1 when asserted, latched, clears on read. 14 1-0 ro reserved 15-21 all ro reserved: coded 00h 22 7 ro high rx power alarm latched channel 11: coded 1 when asserted, latched, clears on read. 22 6 ro low rx power alarm latched channel 11: coded 1 when asserted, latched, clears on read. 22 5-4 ro reserved 22 3 ro high rx power alarm latched channel 10: coded 1 when asserted, latched, clears on read. 22 2 ro low rx power alarm latched channel 10: coded 1 when asserted, latched, clears on read. 22 1-0 ro reserved 23 7 ro high rx power alarm latched channel 9: coded 1 when asserted, latched, clears on read. 23 6 ro low rx power alarm latched channel 9: coded 1 when asserted, latched, clears on read. 23 5-4 ro reserved 23 3 ro high rx power alarm latched channel 8: coded 1 when asserted, latched, clears on read. 23 2 ro low rx power alarm latched channel 8: coded 1 when asserted, latched, clears on read. 23 1-0 ro reserved avago confidential
38 address type field name/description byte bit 24 7 ro high rx power alarm latched channel 7: coded 1 when asserted, latched, clears on read. 24 6 ro low rx power alarm latched channel 7: coded 1 when asserted, latched, clears on read. 24 5-4 ro reserved 24 3 ro high rx power alarm latched channel 6: coded 1 when asserted, latched, clears on read. 24 2 ro low rx power alarm latched channel 6: coded 1 when asserted, latched, clears on read. 24 1-0 ro reserved 25 7 ro high rx power alarm latched channel 5: coded 1 when asserted, latched, clears on read. 25 6 ro low rx power alarm latched channel 5: coded 1 when asserted, latched, clears on read. 25 5-4 ro reserved 25 3 ro high rx power alarm latched channel 4: coded 1 when asserted, latched, clears on read. 25 2 ro low rx power alarm latched channel 4: coded 1 when asserted, latched, clears on read. 25 1-0 ro reserved 26 7 ro high rx power alarm latched channel 3: coded 1 when asserted, latched, clears on read. 26 6 ro low rx power alarm latched channel 3: coded 1 when asserted, latched, clears on read. 26 5-4 ro reserved 26 3 ro high rx power alarm latched channel 2: coded 1 when asserted, latched, clears on read. 26 2 ro low rx power alarm latched channel 2: coded 1 when asserted, latched, clears on read. 26 1-0 ro reserved 27 7 ro high rx power alarm latched channel 1: coded 1 when asserted, latched, clears on read. 27 6 ro low rx power alarm latched channel 1: coded 1 when asserted, latched, clears on read. 27 5-4 ro reserved 27 3 ro high rx power alarm latched channel 0: coded 1 when asserted, latched, clears on read. 27 2 ro low rx power alarm latched channel 01: coded 1 when asserted, latched, clears on read. 27 1-0 ro reserved 28 all ro internal temperature monitor msb: integer part coded in signed 2s complement. tolerance is 3c. 29 all ro internal temperature monitor lsb: fractional part in units of 1/256 coded in binary. 30-31 all ro reserved: coded 00h 32-33 all ro internal 3.3 vcc monitor: voltage in 100 v units coded as 16 bit unsigned integer, byte 32 is msb. tolerance is 0.150v. 34-35 all ro internal 2.5 vcc monitor: voltage in 100 v units coded as 16 bit unsigned integer, byte 34 is msb. tolerance is 0.150v. 36-63 all ro reserved: coded 00h 64-65 all ro rx optical input, pave, monitor channel 11: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 64 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 66-67 all ro rx optical input, pave, monitor channel 10: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 66 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 68-69 all ro rx optical input, pave, monitor channel 9: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 68 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 70-71 all ro rx optical input, pave, monitor channel 8: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 70 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 72-73 all ro rx optical input, pave, monitor channel 7: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 72 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 74-75 all ro rx optical input, pave, monitor channel 6: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 74 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 76-77 all ro rx optical input, pave, monitor channel 5: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 76 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 78-79 all ro rx optical input, pave, monitor channel 4: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 78 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. avago confidential
39 address type field name/description byte bit 80-81 all ro rx optical input, pave, monitor channel 3: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 80 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 82-83 all ro rx optical input, pave, monitor channel 2: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 82 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 84-85 all ro rx optical input, pave, monitor channel 1: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 84 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 86-87 all ro rx optical input, pave, monitor channel 0: optical power in 0.1 w units coded as 16 bit unsigned integer, byte 86 is msb. tolerance is 3db for -10 dbm to -1.0 dbm range. 88-89 all ro elapsed (power-on) operating time: elapsed time in 2 hour units coded as 16 bit unsigned integer, byte 88 is msb, tolerance is 10% 90 all rwv reserved: coded 00h 91 7-1 rwv reserved: coded 0000000b 91 0 rwv receiver reset: writing 1 return all registers except non-volatile rw to factory default values. reads 0 after operation. 92 7-4 rwv reserved: coded 0000b 92 3 rwv rx channel 11 disable: writing 1 deactivates the electrical output, default is 0. 92 2 rwv rx channel 10 disable: writing 1 deactivates the electrical output, default is 0. 92 1 rwv rx channel 9 disable: writing 1 deactivates the electrical output, default is 0. 92 0 rwv rx channel 8 disable: writing 1 deactivates the electrical output, default is 0. 93 7 rwv rx channel 7 disable: writing 1 deactivates the electrical output, default is 0. 93 6 rwv rx channel 6 disable: writing 1 deactivates the electrical output, default is 0. 93 5 rwv rx channel 5 disable: writing 1 deactivates the electrical output, default is 0. 93 4 rwv rx channel 4 disable: writing 1 deactivates the electrical output, default is 0. 93 3 rwv rx channel 3 disable: writing 1 deactivates the electrical output, default is 0. 93 2 rwv rx channel 2 disable: writing 1 deactivates the electrical output, default is 0. 93 1 rwv rx channel 1 disable: writing 1 deactivates the electrical output, default is 0. 93 0 rwv rx channel 0 disable: writing 1 deactivates the electrical output, default is 0. 94 7-4 rwv reserved: coded 0000b 94 3 rwv squelch disable channel 11: writing 1 inhibits squelch for the channel, default is 0. 94 2 rwv squelch disable channel 10: writing 1 inhibits squelch for the channel, default is 0. 94 1 rwv squelch disable channel 9: writing 1 inhibits squelch for the channel, default is 0. 94 0 rwv squelch disable channel 8: writing 1 inhibits squelch for the channel, default is 0. 95 7 rwv squelch disable channel 7: writing 1 inhibits squelch for the channel, default is 0. 95 6 rwv squelch disable channel 6: writing 1 inhibits squelch for the channel, default is 0. 95 5 rwv squelch disable channel 5: writing 1 inhibits squelch for the channel, default is 0. 95 4 rwv squelch disable channel 4: writing 1 inhibits squelch for the channel, default is 0. 95 3 rwv squelch disable channel 3: writing 1 inhibits squelch for the channel, default is 0. 95 2 rwv squelch disable channel 2: writing 1 inhibits squelch for the channel, default is 0. 95 1 rwv squelch disable channel 1: writing 1 inhibits squelch for the channel, default is 0. 95 0 rwv squelch disable channel 0: writing 1 inhibits squelch for the channel, default is 0. 96 7-6 rwv rate select channel 11: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 96 5-4 rwv rate select channel 10: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 96 3-2 rwv rate select channel 9: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 96 1-0 rwv rate select channel 8: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 97 7-6 rwv rate select channel 7: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 97 5-4 rwv rate select channel 6: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 97 3-2 rwv rate select channel 5: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 97 1-0 rwv rate select channel 4: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 avago confidential
40 address type field name/description byte bit 98 7-6 rwv rate select channel 3: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 98 5-4 rwv rate select channel 2: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 98 3-2 rwv rate select channel 1: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 98 1-0 rwv rate select channel 0: write 00 for max. bw, 01 for sdr bw, rest reserved. default is 00 99-105 all rwv reserved: coded 00h 106-111 all rwv reserved: coded 00h 112 7-4 rwv reserved: coded 0000b 112 3 rwv mask los rx channel 11: writing 1 prevents intl generation, default = 0 112 2 rwv mask los rx channel 10: writing 1 prevents intl generation, default = 0 112 1 rwv mask los rx channel 9: writing 1 prevents intl generation, default = 0 112 0 rwv mask los rx channel 8: writing 1 prevents intl generation, default = 0 113 7 rwv mask los rx channel 7: writing 1 prevents intl generation, default = 0 113 6 rwv mask los rx channel 6: writing 1 prevents intl generation, default = 0 113 5 rwv mask los rx channel 5: writing 1 prevents intl generation, default = 0 113 4 rwv mask los rx channel 4: writing 1 prevents intl generation, default = 0 113 3 rwv mask los rx channel 3: writing 1 prevents intl generation, default = 0 113 2 rwv mask los rx channel 2: writing 1 prevents intl generation, default = 0 113 1 rwv mask los rx channel 1: writing 1 prevents intl generation, default = 0 113 0 rwv mask los rx channel 0: writing 1 prevents intl generation, default = 0 114-115 all rwv reserved: coded 00h 116 7 rwv mask internal high temperature alarm: writing 1 prevents intl generation, default = 0 116 6 rwv mask internal low temperature alarm: writing 1 prevents intl generation, default = 0 116 5-0 rwv reserved 117 7 rwv mask internal high 3.3 vcc alarm: writing 1 prevents intl generation, default = 0 117 6 rwv mask internal low 3.3 vcc alarm: writing 1 prevents intl generation, default = 0 117 5-4 rwv reserved 117 3 rwv mask internal high 2.5 vcc alarm: writing 1 prevents intl generation, default = 0 117 2 rwv mask internal low 2.5 vcc alarm: writing 1 prevents intl generation, default = 0 117 1-0 rwv reserved 118 all rw rx input power alarm level select. custom=01h, factory default=00h 119-120 all rw rx optical power all channels custom high alarm threshold: optical power in 0.1 uw units coded as 16 bit unsigned integer, low address is msb 121-122 all rw rx optical power all channels custom low alarm threshold: optical power in 0.1 uw units coded as 16 bit unsigned integer, low address is msb 123-126 all rw reserved: coded 00h 127 all rwv page select byte avago confidential
41 7. rx memory map 00h upper page receiver serial id page 00h entries follow. description of the registers can be found in section 9 below. address contents type field name/description byte bit code 128 all 00h ro type identifer: coded 00h for unspecifed. see sff-8472 for reference 129 all 01000000b ro module description: coded for < 2.0 w 130 all 11000000b ro required power supplies: coded for 3.3v & 2.5v supplies 131 all 01010000b ro max recommended operating case temperature in degrees c: coded for 80c 132 all 00011001b ro min bit rate in 100 mb/s units: coded for 2500 mb/s 133 all 01100100b ro max bit rate in 100 mb/s units: coded for 10000 mb/s 134-135 all 00h ro nominal laser wavelength (wavelength in nm = value / 20): coded 00h for rx 136-137 all 00h ro wavelength deviation from nominal (tolerance in nm = +/- value / 200): coded 00h for rx 138 all 00101000b ro supported flags/actions: coded for rx los, output squelch for los, alarm flags 139 all 00110101b ro supported monitors: coded for rx input, pave, internal temp, elapsed time 140 all 01100000b ro supported monitors: coded for 3.3v, 2.5v 141 all 10101000b ro supported controls: coded for ch disable, squelch disable, rate select 142 all 10100011b ro supported controls: coded for rx amplitude, rx de-emphasis, ch polarity flip, addressing 143 all 00h ro supported functions 144-151 all 00h ro reserved 152-167 all 41h 56h 41h 47h 4fh 20h 20h x10 ro vendor name in ascii: coded avago for avago technologies, spaces (20h) for unused characters 168-170 all 00h 17h 6ah ro vendor oui (ieee id): coded 00h 17h 6ah for avago technologies 171-186 all 41h 46h 42h 52h 2dh 37h 38h 36h 42h ro vendor part number in ascii: afbr-820b where bytes 180 through 186 vary with selected option, spaces (20h) for unused characters 187-188 all 30h 32h ro vendor revision number in ascii: coded 02 189-204 all ro vendor serial number (ascii): varies by unit 205-212 all ro vendor date code yyyymmdd (ascii): spaces (20h) for unused characters 213-222 all ro clei code in ascii: all spaces (20h) if unused 223 all ro check sum addresses 128 through 222 224-255 all ro vendor specifc: all zeroes if unused avago confidential
42 8. rx memory map 01h upper page details of receiver upper page 01h follow. address type field name/description byte bit 128 all ro internal temperature high alarm threshold msb: integer part coded in signed 2s complement 129 all ro internal temperature high alarm threshold lsb: fractional part in units of 1/256 coded in binary. 130 all ro internal temperature low alarm threshold msb: integer part coded in signed 2s complement 131 all ro internal temperature low alarm threshold lsb: fractional part in units of 1/256 coded in binary. 132-143 all ro reserved 144-145 all ro internal 3.3 vcc high alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 146-147 all ro internal 3.3 vcc low alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 148-151 all ro reserved 152-153 all ro internal 2.5 vcc high alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 154-155 all ro internal 2.5 vcc low alarm threshold: voltage in 100 v units coded as 16 bit unsigned integer, low address is msb. 156-159 all ro reserved 160-183 all ro thresholds reserved: coded 00h 184-185 all ro rx optical power all channels high alarm threshold: optical power in 0.1 w units coded as 16 bit unsigned integer, low address is msb. 186-187 all ro rx optical power all channels low alarm threshold: optical power in 0.1 w units coded as 16 bit unsigned integer, low address is msb. 188-223 all ro thresholds reserved: coded 00h 224 all ro check sum: low order 8 bits of the sum of all bytes from 128 through 223 inclusive 225 7-1 rwn reserved: coded 0000000b 225 0 rwn intl pulse/static option: writing 1 sets intl to static mode, default is 0 for pulse mode 226 7-4 rwn reserved: coded 0000b 226 3 rwn output polarity flip channel 11: writing 1 inverts truth of the diferential output pair, default is 0. 226 2 rwn output polarity flip channel 10: writing 1 inverts truth of the diferential output pair, default is 0. 226 1 rwn output polarity flip channel 9: writing 1 inverts truth of the diferential output pair, default is 0. 226 0 rwn output polarity flip channel 8: writing 1 inverts truth of the diferential output pair, default is 0. 227 7 rwn output polarity flip channel 4: writing 1 inverts truth of the diferential output pair, default is 0. 227 6 rwn output polarity flip channel 6: writing 1 inverts truth of the diferential output pair, default is 0. 227 5 rwn output polarity flip channel 5: writing 1 inverts truth of the diferential output pair, default is 0. 227 4 rwn output polarity flip channel 4: writing 1 inverts truth of the diferential output pair, default is 0. 227 3 rwn output polarity flip channel 3: writing 1 inverts truth of the diferential output pair, default is 0. 227 2 rwn output polarity flip channel 2: writing 1 inverts truth of the diferential output pair, default is 0. 227 1 rwn output polarity flip channel 1: writing 1 inverts truth of the diferential output pair, default is 0. 227 0 rwn output polarity flip channel 0: writing 1 inverts truth of the diferential output pair, default is 0. 228 7-4 rwn rx output amplitude control: channel 11. see below for code description. default = 5 228 3-0 rwn rx output amplitude control: channel 10. see below for code description. default = 5 229 7-4 rwn rx output amplitude control: channel 9. see below for code description. default = 5 229 3-0 rwn rx output amplitude control: channel 8. see below for code description. default = 5 230 7-4 rwn rx output amplitude control: channel 7. see below for code description. default = 5 230 3-0 rwn rx output amplitude control: channel 6. see below for code description. default = 5 231 7-4 rwn rx output amplitude control: channel 5. see below for code description. default = 5 231 3-0 rwn rx output amplitude control: channel 4. see below for code description. default = 5 232 7-4 rwn rx output amplitude control: channel 3. see below for code description. default = 5 232 3-0 rwn rx output amplitude control: channel 2. see below for code description. default = 5 233 7-4 rwn rx output amplitude control: channel 1. see below for code description. default = 5 233 3-0 rwn rx output amplitude control: channel 0. see below for code description. default = 5 avago confidential
43 address type field name/description byte bit 234 7-4 rwn rx output de-emphasis control: channel 11. see below for code description. default = 4 234 3-0 rwn rx output de-emphasis control: channel 10. see below for code description. default = 4 235 7-4 rwn rx output de-emphasis control: channel 9. see below for code description. default = 4 235 3-0 rwn rx output de-emphasis control: channel 8. see below for code description. default = 4 236 7-4 rwn rx output de-emphasis control: channel 7. see below for code description. default = 4 236 3-0 rwn rx output de-emphasis control: channel 6. see below for code description. default = 4 237 7-4 rwn rx output de-emphasis control: channel 5. see below for code description. default = 4 237 3-0 rwn rx output de-emphasis control: channel 4. see below for code description. default = 4 238 7-4 rwn rx output de-emphasis control: channel 3. see below for code description. default = 4 238 3-0 rwn rx output de-emphasis control: channel 2. see below for code description. default = 4 239 7-4 rwn rx output de-emphasis control: channel 1. see below for code description. default = 4 239 3-0 rwn rx output de-emphasis control: channel 0. see below for code description. default = 4 240-243 all rwn reserved: coded 00h 244-249 all rwv reserved: coded 00h 250 7 rwv mask high rx power alarm channel 11: writing 1 prevents intl generation, default = 0 250 6 rwv mask low rx power alarm channel 11: writing 1 prevents intl generation, default = 0 250 5-4 rwv reserved 250 3 rwv mask high rx power alarm channel 10: writing 1 prevents intl generation, default = 0 250 2 rwv mask low rx power alarm channel 10: writing 1 prevents intl generation, default = 0 250 1-0 rwv reserved 251 7 rwv mask bt high rx power alarm channel 9: writing 1 prevents intl generation, default = 0 251 6 rwv mask low rx power alarm channel 9: writing 1 prevents intl generation, default = 0 251 5-4 rwv reserved 251 3 rwv mask high rx power alarm channel 8: writing 1 prevents intl generation, default = 0 251 2 rwv mask low rx power alarm channel 8: writing 1 prevents intl generation, default = 0 251 1-0 rwv reserved 252 7 rwv mask high rx power alarm channel 7: writing 1 prevents intl generation, default = 0 252 6 rwv mask low rx power alarm channel 7: writing 1 prevents intl generation, default = 0 252 5-4 rwv reserved 252 3 rwv mask high rx power alarm channel 6: writing 1 prevents intl generation, default = 0 252 2 rwv mask low rx power alarm channel 6: writing 1 prevents intl generation, default = 0 252 1-0 rwv reserved 253 7 rwv mask high rx power alarm channel 5: writing 1 prevents intl generation, default = 0 253 6 rwv mask low rx power alarm channel 5: writing 1 prevents intl generation, default = 0 253 5-4 rwv reserved 253 3 rwv mask high rx power alarm channel 4: writing 1 prevents intl generation, default = 0 253 2 rwv mask low rx power alarm channel 4: writing 1 prevents intl generation, default = 0 253 1-0 rwv reserved 254 7 rwv mask high rx power alarm channel 3: writing 1 prevents intl generation, default = 0 254 6 rwv mask low rx power alarm channel 3: writing 1 prevents intl generation, default = 0 254 5-4 rwv reserved 254 3 rwv mask high rx power alarm channel 2: writing 1 prevents intl generation, default = 0 254 2 rwv mask low rx power alarm channel 2: writing 1 prevents intl generation, default = 0 254 1-0 rwv reserved 255 7 rwv mask high rx power alarm channel 1: writing 1 prevents intl generation, default = 0 255 6 rwv mask low rx power alarm channel 1: writing 1 prevents intl generation, default = 0 255 5-4 rwv reserved 255 3 rwv mask high rx power alarm channel 0: writing 1 prevents intl generation, default = 0 255 2 rwv mask low rx power alarm channel 0: writing 1 prevents intl generation, default = 0 255 1-0 rwv reserved avago confidential
44 receiver output amplitude control code description control registers 228 through 233 permit output signal amplitude selection. four bit code blocks (either bits 7 through 4 or 3 through 0 where bit 7 or 3 is the msb) are assigned to each channel. codes 1xxx are reserved. code 0111 calls for full scale signal amplitude and code 0000 calls for minimum signal amplitude. see table below. code receiver output amplitude C no de-emphasis reference min nominal max units 1xxxb reserved 0111b 850 mvpp full scale 0110b 760 mvpp 0101b 670 mvpp 0100b 580 mvpp 0011b 490 mvpp 0010b 400 mvpp 0001b 310 mvpp 0000b 220 mvpp receiver output de-emphasis control code description control registers 234 through 239 permit output de-emphasis selection. four bit code blocks (either bits 7 through 4 or 3 through 0 where bit 7 or 3 is the msb) are assigned to each channel. codes 1xxx are reserved. code 0111 calls for full scale, 6 db, de-emphasis and code 0000 calls for no de-emphasis. intermediate code values yield intermediate de-emphasis levels. avago confidential
45 9. serial id 00h upper page description description of serial id page 00h codes follows. byte 128 module type address field name/description byte code module type 128 type identifer: see sff-8472 for reference, also sfp & xfp msa, coded 00h if unspecifed. byte 129 module description address field name/description byte bit code 129 7-6 00b power class 1: module power consumption < 1.5 w 7-6 01b power class 2: module power consumption < 2.0 w 7-6 10b power class 3: module power consumption < 2.5 w 7-6 11b power class 4: module power consumption < 3.5 w 5 coded 1 for tx cdr provided; else coded 0 4 coded 1 for rx cdr provided; else coded 0 3 coded 1 for required reference clock; else coded 0 2 coded 1 for page 02 provided; else coded 0 1 coded 1 for controlled launch transmitter (tia 492aaac); else coded 0 0 reserved byte 130 module description: required power supplies address field name/description byte bit code 130 7 3.3 v, coded 1 if required, else coded 0. 6 2.5 v, coded 1 if required, else coded 0. 5 1.8 v, coded 1 if required, else coded 0. 4 vo supply, coded 1 if required, else coded 0. 3 variable supply, coded 1 if required, else coded 0. 2-0 reserved byte 131 module description: max recommended operating case temperature address field name/description byte bit code 131 max tc = binary value x 1.0c byte 132 module description min signal rate per channel address field name/description byte code 132 00h unknown/unspecifed rest min signal rate = binary value x 100 mb/s avago confidential
46 byte 133 module description max signal rate per channel address field name/description byte code 133 00h unknown/unspecifed max signal rate = binary value x 100 mb/s byte 134 - 137 module description wavelength & tolerance address field name/description byte code 134-135 nominal center wavelength: wavelength in nm = binary value / 20, coded 00b if unspecifed/unused. 136-137 wavelength tolerance: tolerance in nm = binary value / 200, coded 00b if unspecifed/unused. byte 138 supported functions C flags/actions address field name/description byte bit code 138 7 coded 1 for tx fault flag provided, else coded 0 6 coded 1 for tx los flag provided, else coded 0 5 coded 1 for rx los flag provided, else coded 0 4 coded 1 for cdr lol flag provided, else coded 0 3 coded 1 for output squelch for los provided, else coded 0 2 coded 1 for monitor alarm & warning flags provided, coded 0 for monitor alarm flags provided 1-0 reserved byte 139 - 140 supported functions - monitors address field name/description byte bit code 139 7 coded 1 for tx bias monitor, else coded 0 139 6 coded 1 for tx lop monitor, else coded 0 139 5 coded 1 for individual rx input power monitors, coded 0 for single-channel or group monitor 139 4 coded 1 for rx input power reported as pave, coded 0 for reported as oma 139 3 coded 1 for case temperature monitor, else coded 0 139 2 coded 1 for internal temperature monitor, else coded 0 139 1 coded 1 for peak temperature monitor, else coded 0 139 0 coded 1 for elapsed time monitor, else coded 0 140 7 coded 1 for ber monitor, else coded 0 140 6 coded 1 for internal 3.3 v vcc monitor, else coded 0 140 5 coded 1 for internal 2.5 v vcc monitor, else coded 0 140 4 coded 1 for internal 1.8 v vcc monitor, else coded 0 140 3 coded 1 for internal vo vcc monitor, else coded 0 140 2 coded 1 for tec current monitor, else coded 0 140 1-0 reserved avago confidential
47 byte 141 supported functions C controls address field name/description byte bit code 141 7-6 00 channel disable control not provided/unspecifed 7-6 01 global channel disable control implemented 7-6 10 individual and independent channel disable control implemented 7-6 11 reserved 5-4 00 squelch disable control not provided/unspecifed 5-4 01 global squelch disable control implemented 5-4 10 individual and independent channel squelch control implemented 5-4 11 reserved 3-2 00 rate select control not provided/unspecifed 3-2 01 global rate select control implemented 3-2 10 individual and independent rate select control implemented 3-2 11 reserved 1-0 00 tx input equalization control not provided/unspecifed 1-0 01 global tx input equalization control implemented 1-0 10 individual and independent tx input equalization control implemented 1-0 11 reserved byte 142 supported functions C controls address field name/description byte bit code 142 7-6 00 rx output amplitude control not provided/unspecifed 7-6 01 global rx output amplitude control implemented 7-6 10 individual and independent rx output amplitude control implemented 7-6 11 reserved 5-4 00 rx output de-emphasis control not provided/unspecifed 5-4 01 global rx output de-emphasis control implemented 5-4 10 individual and independent rx output de-emphasis control implemented 5-4 11 reserved 3 coded 1 for tx margin mode provided, else coded 0 2 coded 1 for channel reset control provided, else coded 0 1 coded 1 for channel polarity flip control provided, else coded 0 0 coded 1 for module addressing control provided, else coded 0 avago confidential
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2013 avago technologies. all rights reserved. av02-1955en - january 28, 2013 byte 143 supported functions address field name/description byte bit code 143 7 coded 1 for fec control, else coded 0 6 coded 1 for pec control, else coded 0 5 coded 1 for jtag control, else coded 0 4 coded 1 for ac-jtag control, else coded 0 3 coded 1 for bist, else coded 0 2 coded 1 for tec temperature control, else coded 0 1 coded 1 for sleep mode set control provided, else coded 0 0 coded 1 for cdr bypass control provided, else coded 0 byte144 - 151 reserved address field name/description byte bit code 144-151 reserved: coded 00h byte 152 - 221 vendor information address field name/description byte bit code 152-167 vendor name ascii C 16 bytes 168-170 vendor oui C 3 bytes; unspecifed where coded all zeroes 171-186 vendor part number ascii C 16 bytes 187-188 vendor revision number ascii C 2 bytes 189-204 vendor serial number ascii C 16 bytes 205-212 vendor date code ascii C 8 bytes; coded yyyymmdd with spaces (20h) for unused characters 213-222 clei code C 10 bytes; unspecifed where coded all zeroes byte 223 check sum for bytes 128 through 222 address field name/description byte bit code 223 check code C 1 byte: low order 8 bits of the sum of all bytes from 128 through 222 inclusive. byte 224 - 255 vendor specifc address field name/description byte bit code 224-255 vendor specifc C 32 bytes avago confidential

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