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data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 1 general description the AUR9717 is a high efficiency step-down dc-dc voltage converter. the chip operation is optimized using constant frequency, peak-current mode architecture with built-in synchronous power mosfet switchers and internal compensators to reduce external part counts. it is automatically switching between the normal pwm mode and ldo mode to offer improved system power efficiency covering a wide range of loading conditions. the oscillator and timing capacitors are all built-in providing an internal switching frequency of 1.5mhz that allows the use of small surface mount inductors and capacitors for portable product implementations. additional features including soft start (ss), under voltage lock out (uvlo), input over voltage protection (iovp) and thermal shutdown detection (tsd) are integrated to provide reliable product applications. the device is available in adjustable output voltage versions ranging from 1v to 3.3v, and is able to deliver up to 1a. the AUR9717 is available in wdfn-33-10 package. features ? dual channel high efficiency buck power converter ? low quiescent current ? output current: 1a ? adjustable output voltage from 1v to 3.3v ? wide operating voltage range: 2.5v to 5.5v ? built-in power switchers for synchronous rectification with high efficiency ? feedback voltage: 600mv ? 1.5mhz constant frequency operation ? automatic pwm/ldo mode switching control ? thermal shutdown protection ? low drop-out operation at 100% duty cycle ? no schottky diode required ? internal input over voltage protection applications ? mobile phone, digital camera and mp3 player ? headset, radio and other hand-held instruments ? post dc-dc voltage regulation ? pda and notebook computer figure 1. package type of AUR9717 wdfn-33-10
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 2 pin configuration d package (wdfn-33-10) 1 2 3 4 56 7 8 9 10 pin 1 mark en1 fb1 vin2 gnd lx2 en2 fb2 vin1 gnd lx1 figure 2. pin configuration of AUR9717 (top view) pin description pin number pin name function 1 en1 enable signal input of channel 1, active high 2 fb1 feedback voltage of channel 1 3 vin2 power supply input of channel 2 4, 9 gnd this pin is the gnd reference for the nmosfet power stage. it must be connected to the system ground 5 lx2 connection from power mosfet of channel 2 to inductor 6 en2 enable signal input of channel 2, active high 7 fb2 feedback voltage of channel 2 8 vin1 power supply input of channel 1 10 lx1 connection from power mosfet of channel 1 to inductor
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 3 functional block diagram figure 3. functional block diagram of AUR9717 ordering information AUR9717 a circuit type a: adjustable output package temperature range part number marking id packing type wdfn-3 3-10 -40 to 80c AUR9717agd 9717a tape & reel bcd semiconductor's pb-free products, as designated with "g" in the part number, are rohs compliant and green. package d: wdfn-33-10 g: green
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 4 absolute maximum ratings (note 1) parameter symbol value unit supply input voltage v in1, v in2 0 to 6.5 v enable input voltage v en1, v en2 -0.3 to v in1 (v in2 )+0.3 v switch output voltage v lx1, v lx2 -0.3 to v in1 (v in2 )+0.3 v v in1 -v in2 voltage (note 2) v df -0.3 to 0.3 v power dissipation (on pcb, t a =25c) p d 2.22 w thermal resistance (junction to ambient, simulation) ja 45.13 c/w thermal resistance (junction to case, simulation) jc 6.97 c/w operating junction temperature t j 160 c operating temperature t op -40 to 85 c storage temperature t stg -55 to 150 c esd (human body model) v hbm 2000 v esd (machine model) v mm 200 v note 1: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating co nditions? is not implied. exposure to ?absolute maximum ratings? for extended periods may affect device reliability. note 2: the absolute voltage difference between v in1 and v in2 can not exceed 0.3v. recommended operating conditions parameter symbol min max unit supply input voltage v in1, v in2 2.5 5.5 v junction temperature range t j -20 125 c ambient temperature range t a -40 80 c
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 5 electrical characteristics v in =v en1 =v en2 =5v, v fb1 =v fb2 =0.6v, l1=l2=2.2 h, c in1 =c in2 =4.7 f, c out1 =c out2 =10 f, t a =25c, unless otherwise specified. parameter symbol conditions min typ max unit input voltage range v in v in =v in1 =v in2 2.5 5.5 v shutdown current i off v en1 =v en2 =0v 0.1 1 a regulated feedback voltage v fb for adjustable output voltage 0.585 0.6 0.615 v regulated output voltage accuracy v out1 /v out1, v out2 /v out2 v in =2.5v to 5.5v, i out1 =i out2 =0 to 1a -3 3 % peak inductor current i pk v fb1 =v fb2 =0.5v 1.5 a oscillator frequency f osc 1.2 1.5 1.8 mhz pmosfet r on r on(p) i out1 =i out2 =200ma 0.28 nmosfet r on r on(n) i out1 =i out2 =200ma 0.25 lx leakage current i lx v en1 =v en2 =0v, v lx1 =v lx2 =0v or 5v 0.01 0.1 a feedback current i fb1, i fb2 30 na input over voltage protection v iovp 6 v en leakage current i en1, i en2 0.01 0.1 a en high-level input voltage v en_h1, v en_h2 v in =2.5v to 5.5v 1.5 v en low-level input voltage v en_l1, v en_l2 v in =2.5v to 5.5v 0.6 v under voltage lock out v uvlo rising 1.8 v hysteresis hysteresis 0.1 v thermal shutdown t sd 160 c
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 6 typical performance characteristics figure 4. efficiency vs. output current figure 5. efficiency vs. load current figure 6. efficiency vs. load current figure 7. uvlo threshold vs. temperature
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 7 typical performance characteristics (continued) figure 8. output voltage vs. output current figure 9. output current limit vs. input voltage figure 10. output voltage vs. temperature figure 11. frequency vs. input voltage
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 8 typical performance characteristics (continued) figure 12. output current limit vs. temperature figure 13. frequency vs. temperature figure 14. temperature vs. load current figure 15. waveform of v in =4.5v, v out =1.5v, l=2.2 h v out 200mv/div v lx 2v/div v en 2v/div time 400ns/div
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 9 typical performance characteristics (continued) figure 16. soft start v en 2v/div v out 1v/div v lx 2v/div time 200 s/div
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 10 application information the basic AUR9717 application circuit is shown in figure 18. 1. inductor selection for most applications, the value of inductor is chosen based on the required ripple current with the range of 2.2 h to 4.7 h. the largest ripple current occurs at the highest input voltage. having a small ripple current reduces the esr loss in the output capacitor and improves the efficiency. the highest efficiency is realized at low operating frequency with small ripple current. however, larger value inductors will be required. a reasonable starting point for ripple current setting is i l =40%i max ? . for a maximum ripple current stays below a specified value, the inductor should be chosen according to the following equation: the dc current rating of the inductor should be at least equal to the maximum output current plus half the highest ripple current to prevent inductor core saturation. for better efficiency, a lower dc-resistance inductor should be selected. 2. capacitor selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current must be used. the maximum rm s capacitor current is given by: it indicates a maximum value at v in =2v out , where i rms =i out /2. this simple wors e-case condition is commonly used for design because even significant deviations do not much relieve. the selection of c out is determined by the effective series resistance (esr) that is required to minimize output voltage ripple and load step transients, as well as the amount of bulk capacitor that is necessary to ensure that the control loop is stable. loop stability can be also checked by viewing the load step transient response as described in the following section. the output ripple, v out , is determined by: the output ripple is the highest at the maximum input voltage since i l increases with input voltage. 3. load transient a switching regulator typically takes several cycles to respond to the load curren t step. when a load step occurs, v out immediately shifts by an amount equal to i load esr, where esr is the effective series resistance of output capacitor. i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during the recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. 4. output voltage setting the output voltage of AUR9717 can be adjusted by a resistive divider according to the following formula: the resistive divider senses the fraction of the output voltage as shown in figure 17. figure 17. setting the output voltage in out in out omax rms v v v v i i 2 1 )] ( [ ? = ) 1 ( 1 in out out l v v v l f i ? = ] ) ( 1 ][ ) ( [ max v v max i f v l in out l out ? = ] 8 1 [ out l out c f esr i v + ) 1 ( 6 . 0 ) 1 ( 2 1 2 1 fb r r v r r v v out + = + = fb gnd vout r1 r2 aur 9717
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 11 application information (continued) 5. efficiency considerations the efficiency of switching regulator is equal to the output power divided by the input power times 100%. it is usually useful to analyze the individual losses to determine what is limiting efficiency and which change could produce the largest improvement. efficiency can be expressed as: efficiency=100%-l1-l2-?.. where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the regulator produce losses, two major sources usually account for most of the power losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very light load currents and the i 2 r loss dominates the efficiency loss at medium to heavy load currents. 5.1 the v in quiescent current loss comprises two parts: the dc bias current as given in the electrical characteristics and the internal mosfet switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each cycle the gate is switched from high to low, then to high again, and the packet of charge, dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the internal dc bias current. in continuous mode, where q p and q n are the gate charge of power pmosfet and nmosfet switches. both the dc bias current and gate charge losses are proportional to the v in and this effect will be more serious at higher input voltages. 5.2 i 2 r losses are calculated from internal switch resistance, r sw and external inductor resistance r l . in continuous mode, the average output current flowing through the inductor is chopped between power pmosfet switch and nmosfet switch. then, the series resistance looking into the lx pin is a function of both pmosfet r ds(on)p and nmosfet r ds(on)n resistance and the duty cycle (d): therefore, to obtain the i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of total additional loss. 6. thermal characteristics in most applications, the part does not dissipate much heat due to its high efficiency. however, in some conditions when the part is operating in high ambient temperature with high r ds(on) resistance and high duty cycles, such as in ldo mode, the heat dissipated may exceed the maximum junction temperature. to avoid the part from exceeding maximum junction temperature, the user should do some thermal analysis. the maximum power dissipation depends on the layout of pcb, the thermal resistance of ic package, the rate of surrounding airflow and the temperat ure difference between junction and ambient. 7. pc board layout considerations when laying out the printed circuit board, the following checklist should be used to optimize the performance of AUR9717. 1. the power traces, including the gnd trace, the lx trace and the vin trace should be kept direct, short and wide. 2. put the input capacitor as close as possible to the vin and gnd pins. 3. the fb pin should be connected directly to the feedback resistor divider. 4. keep the switching node lx away from the sensitive fb pin and the node should be kept small area. ) ( n p gate q q f i + = () () ) ( d r d r r n on ds p on ds sw ? + = 1
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 12 typical application v in = 2.5v to 5.5v c in2 4.7f r1 r2 c out 1 10f l1 2.2h c1 v out1 AUR9717 gnd fb 1 lx1 en1 vin2 lx2 en2 gnd fb2 vin1 110 9 8 7 4 56 2 3 connected to v in c in1 4.7f r3 r4 c out2 10f l 2 2.2h c2 v out2 i r2 i r4 note 3: ) 1 ( 2 1 fb1 1 r r v v out + = ; ) 1 ( 4 3 fb2 2 r r v v out + = when r2 or r4=300k to 60k , the i r2 or i r4 =2 a to 10 a , and r 1 c1 or r3c2 should be in the range between 310 -6 and 610 -6 for component selection. . figure 18. typical application circuit of AUR9717 (note 3) table 1. component guide v out1 or v out2 (v) r1 or r3 (k ) r2 or r4 (k ) c1 or c2 (pf) l1 or l2 ( h) 3.3 453 100 13 2.2 2.5 320 100 18 2.2 1.8 200 100 30 2.2 1.2 100 100 56 2.2 1.0 68 100 82 2.2
data sheet dual 1a, 1.5mhz pwm step-down dc-dc co nverter with ovp AUR9717 oct. 2011 rev. 1.0 bcd semiconductor manuf acturing limited 13 mechanical dimensions wdfn-33-10 unit: mm(inch)
important notice bcd semiconductor manufacturing limited reserves the right to make changes without further not ice to any products or specifi- cations herein. bcd semiconductor manufacturing limited does not as sume any responsibility for us e of any its products for any particular purpose, nor does bcd semiconductor manufacturi ng limited assume any liability aris ing out of the application or use of any its products or circui ts. bcd semiconductor manufacturing limited does not convey any license under its patent rights or other rights nor the rights of others. - wafer fab shanghai sim-bcd semiconductor manufacturing co., ltd. 800 yi shan road, shanghai 200233, china tel: +86-21-6485 1491, fax: +86-21-5450 0008 main site regional sales office shenzhen office shanghai sim-bcd semiconductor manuf acturing co., ltd., shenzhen office unit a room 1203, skyworth bldg., gaoxin ave.1.s., nanshan district, shenzhen, china tel: +86-755-8826 7951 fax: +86-755-8826 7865 taiwan office bcd semiconductor (taiwan) company limited 4f, 298-1, rui guang road, nei-hu district, taipei, taiwan tel: +886-2-2656 2808 fax: +886-2-2656 2806 usa office bcd semiconductor corp. 30920 huntwood ave. hayward, ca 94544, usa tel : +1-510-324-2988 fax: +1-510-324-2788 - headquarters bcd semiconductor manufacturing limited no. 1600, zi xing road, shanghai zizhu sc ience-based industrial park, 200241, china tel: +86-21-24162266, fax: +86-21-24162277 bcd semiconductor manufacturing limited important notice bcd semiconductor manufacturing limited reserves the right to make changes without further not ice to any products or specifi- cations herein. bcd semiconductor manufacturing limited does not as sume any responsibility for us e of any its products for any particular purpose, nor does bcd semiconductor manufacturi ng limited assume any liability aris ing out of the application or use of any its products or circui ts. bcd semiconductor manufacturing limited does not convey any license under its patent rights or other rights nor the rights of others. - wafer fab shanghai sim-bcd semiconductor manufacturing limited 800, yi shan road, shanghai 200233, china tel: +86-21-6485 1491, fax: +86-21-5450 0008 bcd semiconductor manufacturing limited main site regional sales office shenzhen office shanghai sim-bcd semiconductor manuf acturing co., ltd. shenzhen office advanced analog circuits (shanghai) corporation shenzhen office room e, 5f, noble center, no.1006, 3rd fuzhong road, futian district, shenzhen 518026, china tel: +86-755-8826 7951 fax: +86-755-8826 7865 taiwan office bcd semiconductor (taiwan) company limited 4f, 298-1, rui guang road, nei-hu district, taipei, taiwan tel: +886-2-2656 2808 fax: +886-2-2656 2806 usa office bcd semiconductor corporation 30920 huntwood ave. hayward, ca 94544, u.s.a tel : +1-510-324-2988 fax: +1-510-324-2788 - ic design group advanced analog circuits (shanghai) corporation 8f, zone b, 900, yi shan road, shanghai 200233, china tel: +86-21-6495 9539, fax: +86-21-6485 9673 bcd semiconductor manufacturing limited http://www.bcdsemi.com bcd semiconductor manufacturing limited

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